Wire Modeling

The WIRE Modeling
Ahmed Saeed
Future University in Egypt

Faculty of Engineering and Technology
Project
Contents
• Introduction
• Geometry and Electrical Properties:
– Resistance
– Capacitance
• Wire Model
– Lumped-C Model
– Lumped-RC Model
– Elmore Delay
– Distributed-RC Model
• Inductance
• Signal Integrity
– Definitions
– Signal Aberrations
– System Model
WIRE Modeling 2
Contents
• Introduction
– Resistance
– Capacitance
• Wire Model
– Lumped-C Model
– Lumped-RC Model
– Elmore Delay
• Inductance
– Definitions
– System Model
WIRE Modeling 3
Introduction
A timing example
• Pin to Pin Combinational Delay (A to Y) =
U7Tpd + U5Tpd + U6Tpd = 1 + 9 + 6 = 16 ns
WIRE Modeling 4
The Wire
• A line connecting two components in a circuit diagram
– To distribute power and clock.
– communicate signals from one place to another
• Stripguides on (and in) PCB, layered over & sandwiched
between groundplanes
• Stripguides on ICs, layered atop each other
• Conductors in cables and cable assemblies
• Connectors
WIRE Modeling 5
The Wire
• We tend to think of this line representing an ideal
wire.
–no resistance,
–no inductance, and
–no capacitance to any other circuit element.
–no delay
–A voltage change at one end of the ideal wire is
immediately visible at the other.
This can be an expensive mistake.
 Clearly such an ideal wire is not physically realizable.

WIRE Modeling 6
The Wire
• Superconductors
– reduce the resistivity to zero → €
– inductance and capacitance cannot be eliminated → delay
• The ideal wire is a useful approximation

– appropriate when the effect of the parasitic elements is
small
– lets us concentrate on the circuit properties of the
components being connected.
WIRE Modeling 7
The Wire - Reality
• Real wires are not ideal: have parasitic
capacitance, resistance, and inductance which
have multiple effects on the circuit behavior.
– increase propagation delay → drop in
performance.
– impact the energy dissipation and the power
distribution.
– introduce extra noise sources, which affects the
reliability of the circuit.
• Wires dominate a modern digital system in terms

of speed, power, and cost.
WIRE Modeling 8
The Wire - Reality
X The time required to drive wires and for signals to
propagate over wires is often the largest factor in
determining cycle time.
X The bulk of the power in many systems is dissipated

driving wires, on-chip and off.
X The amount of wiring, not the number of transistors

or gates, usually determines the amount of area
required by a function on a chip.
X The number of terminals required is a major factor in

the area and cost of chips, packages, and circuit
boards.
WIRE Modeling 9
Contents
• Introduction
– Resistance
– Capacitance
• Wire Model
– Lumped-C Model
– Lumped-RC Model
– Elmore Delay
• Inductance
– Definitions
– System Model
WIRE Modeling 10
Geometry And Electrical Properties-
Resistance
• The resistance of wire is defined by its geometry:
𝜌𝑙 Rectangular Wire: on-chip wires & vias, PCB traces

ℎ𝑤
𝑅=
𝜌𝑙
Circular Wire: off-chip wires, off-PCBs
𝜋𝑟 2
WIRE Modeling 11
Resistance
• The resistivity of commonly used materials (@ 20C):
Material 𝝆 [x10-8 Ω-m]
Silver (Ag) 1.6 Seldom used in electronic packaging because of its
high cost.
Copper (Cu) 1.7 Most used material for electrical conductors: cabling,
ground planes, and stripguides in circuit boards and
bus bars.
Gold (Au) 2.2
Aluminum (Al) 2.7 Offers higher 𝝆/$ It is widely used for wiring on
integrated circuits, low-cost power cables, and bus
bars
Tungsten (W) 5.5 Used for vias (suitable high-temperature processing
after deposition)
WIRE Modeling 12
Resistance
• Since h is a constant for a given technology,
𝑅 = 𝑅∎ 𝑤𝑙
with
𝜌
𝑅∎ =
ℎ
• 𝑅∎ the sheet resistance of the material in Ω/∎
• To obtain the resistance of a wire, simply multiply

the sheet resistance by its ratio (l/w).
WIRE Modeling 13
Resistance
• Sheet resistance values for a 0.25 μm CMOS process
Material 𝐒𝐡𝐞𝐞𝐭 𝐑𝐞𝐬𝐢𝐬𝐭𝐚𝐧𝐜𝐞 [Ω/∎]
n- or p-well diffusion 1000 - 1500
n+, p+ diffusion 50 - 150
n+, p+ diffusion with silicide 3-5
n+, p+ Polysilicon 150 - 200
n+, p+ polysilicon with silicide 4 -5
Aluminum 0.05 – 0.1
• Aluminum (or copper) is the preferred material for the wiring of long wires.
• Polysilicon should only be used for local interconnect.
• The sheet resistance of the diffusion layer (n+, p+) is comparable to that of
polysilicon, the use of diffusion wires should be avoided due to its large
capacitance and the associated RC delay.
WIRE Modeling 14
Resistance
• Example: Consider a wire of which is 10 cm long and 1 μm
wide, and is routed on the first layer. Calculate the total
resistance of this wire.
1- Aluminum (𝑅∎ =0.075 Ω/∎): the total resistance of the wire

Rwire = 0.075 Ω/∎ x (0.1x106 μ m) / (1 μm)= 7.5 kΩ
2- polysilicon (𝑅∎ =175 Ω/∎):
Rwire = 175 Ω/∎ x (0.1x106 μm) / (1 μm)= 17.5 MΩ !
3- Silicided polysilicon (𝑅∎ =4 Ω/∎):

Rwire = 4 Ω/∎ x (0.1x106 μm) / (1 μm)= 400 kΩ
better alternative!
WIRE Modeling 15
Contents
• Introduction
– Resistance
– Capacitance
• Wire Model
– Lumped-C Model
– Lumped-RC Model
– Elmore Delay
• Inductance
– Definitions
– System Model
WIRE Modeling 16
Capacitance
• The capacitance of such a wire is a function of:
– its shape,
– its environment,
– its distance to the substrate, and
– the distance to surrounding wires.
WIRE Modeling 17
Capacitance
• If the width of the wire is larger than the
thickness of the insulating material -> the
electrical-field lines are orthogonal to the
capacitor plates.
• Parallel-plate Model
WIRE Modeling 18
Capacitance
• SiO2 is the dielectric material of choice.
• lower permittivity → lower capacitance.
- It is advantageous to use a Material ϵr

material with the lowest Free space 1
possible permittivity, for it Aerogels 1.5
gives not only lower Polymides 3-4
capacitance, but also a SiO2 3.9
higher propagation velocity. Glass Epoxy (PCB) 5
Silicon Nitride 7.5
Silicon 11.7
WIRE Modeling 19
Capacitance
• common wire cross sections
WIRE Modeling 20
Capacitance
• To minimize the resistance of the wires, cross-section of the
wire (W/H) as large as possible.
• On the other hand, over the years witnessed a steady
reduction in the W/H-ratio, such that it has even dropped
below unity → the parallel-plate model assumed becomes
inaccurate.
– The capacitance between the side-walls of the wires and the substrate
can no longer be ignored and contributes to the overall capacitance.
Fringing Capacitance: The capacitance between the side-

walls of the wires and the substrate.
WIRE Modeling 21
Capacitance
We will approximate it by a parallel plate capacitor of width, w, to account for the field
under the conductor, in parallel with a wire over a ground plane of thickness H, to account
for the fringing field from the two edges.
WIRE Modeling 22
Capacitance
– For larger values of (W/H) the
total capacitance approaches the
parallel-plate model.
– For (W/H) smaller than 1.5, the

fringing component actually
becomes the dominant
component.
– The fringing capacitance can

increase the overall capacitance
by a factor of more than 10 for
small line widths.
– The total capacitance levels off to

a constant value of approximately
1 pF/cm for line widths smaller
than the insulator thickness. In
other words, the capacitance is no
longer a function of the width.
WIRE Modeling 23
Capacitance
• The case of a single rectangular conductor placed over a
ground plane (microstripline), used to be a good model for
interconnections when the number of interconnect layers was
restricted to 1 or 2.
• Today’s processes offer many more layers of interconnect.
• Each wire is not only coupled to the grounded substrate, but

also to the neighboring wires on the same layer and on
adjacent layers.
WIRE Modeling 24
Capacitance
WIRE Modeling 25
Capacitance
The case of a single

rectangular conductor placed
over a ground plane
(microstripline), used to be a
good model for
interconnections when the
number of interconnect layers
was restricted to 1 or 2.
WIRE Modeling 26
Capacitance
WIRE Modeling 27
Contents
• Introduction
– Resistance
– Capacitance
• Wire Model
– Lumped-C Model
– Lumped-RC Model
– Elmore Delay
• Inductance
– Definitions
– System Model
WIRE Modeling 28
Wire Model- The Lumped-C Model
• Reality: The circuit parasitics of a wire are
distributed along its length: not lumped.
• It is often useful to lump the different fractions

into a single circuit element:
– when only a single parasitic component is dominant
– when looking at only one aspect of the circuit
behavior.
• The advantage of this approach is that the effects

of the parasitic then can be described by single
ordinary differential equation.
WIRE Modeling 29
• Lumped Capacitor Model: lump the distributed
capacitance into a single capacitor
– the resistive component of the wire is small
– the switching frequencies are up to medium range.
- The wire still represents an equipotential region, and that the wire does not introduce delay.
- The only impact on performance is introduced by the loading effect of the capacitor on the
driving gate.
WIRE Modeling 30
• Example: For the circuit shown, assume that a driver with a
source resistance of 10 kΩ is used to drive a 10 cm long, 1 μm
wide Al1 wire with total lumped capacitance of 11 pF.
The operation of this RC network is

described by:
For Vin step input (from 0 to V), the transient response of this
circuit is known to be
WIRE Modeling 31
• Example: For the circuit shown, assume that a driver with a
source resistance of 10 kΩ is used to drive a 10 cm long, 1 μm
wide Al1 wire with total lumped capacitance of 11 pF.
The time to reach 50% point is
And
Which is not acceptable -> solution is to reduce Rdriver
WIRE Modeling 32
Contents
• Introduction
– Resistance
– Capacitance
• Wire Model
– Lumped-C Model
– Lumped-RC Model
– Elmore Delay
• Inductance
– Definitions
– System Model
WIRE Modeling 33
Wire Model- The Lumped-RC Model
• Lumped RC Model: lump the distributed capacitance
and resistance into a single capacitor and resistor,
respectively.
– On-chip wires have a significant resistance.
– The equipotential is no longer adequate.
- lumped RC model is pessimistic and inaccurate for long interconnect
WIRE Modeling 34
• Consider the RC tree:
– It has a single input node (called s)
– all capacitors are between a node and the ground
– the network does not contain any resistive loops (tree)
WIRE Modeling 35
- Path resistance Rii = total resistance along the path to
node i
- Shared path resistance Rik, = the resistance shared among the
paths from node s to nodes k and i
Example
WIRE Modeling 36
Contents
• Introduction
– Resistance
– Capacitance
• Wire Model
– Lumped-C Model
– Lumped-RC Model
– Elmore Delay
• Inductance
– Definitions
– System Model
WIRE Modeling 37
Wire Model- Elmore Delay
• The Elmore delay (for N nodes tree) at node i is then
given by:
Example
The Elmore delay for node i
WIRE Modeling 38
• Special Case: non-branched RC chain (ladder)
Example
- The Elmore delay for node 2 equals to
- The Elmore delay for node i equals to
WIRE Modeling 39
• Example wire of length L is partitioned into N identical
segments, each of L/N. The resistance and capacitance of each
segment are given by rL/N and cL/N, respectively. Using
Elmore formula, the time-constant of the wire:
For very large value of N
Conclusion:
- The delay of a wire is a quadratic function of its length! Doubling the length of wire
quadruples its delay.
- The delay of the distributed rc-line is one half of the delay of lumped RC model.
WIRE Modeling 40
Contents
• Introduction
– Resistance
– Capacitance
• Wire Model
– Lumped-C Model
– Lumped-RC Model
– Elmore Delay
• Inductance
– Definitions
– System Model
WIRE Modeling 41
Wire Model- The Distributed-rc Model
The voltage at node i of this network can be determined by solving:
reducing ΔL to 0 yields V is the voltage at a particular point in the wire,

and x is the distance between this point and the
signal source.
No closed-form solution exists for this equation
WIRE Modeling 42
Wire Model- The Distributed-rc Model
Driving these rc lines and minimizing the delay and signal degradation
is one of the trickiest problems in modern digital integrated circuit.
r: distributed resistance per unit of distance

c: distributed capacitance per unit of distance
Simulated step response

of resistive-capacitive wire
as a function of time and
place
WIRE Modeling 43
Wire Model- Distributed vs Lumped
Step response of lumped and distributed RC networks—points of Interest
WIRE Modeling 44
Contents
• Introduction
– Resistance
– Capacitance
• Wire Model
– Lumped-C Model
– Lumped-RC Model
– Elmore Delay
• Inductance
– Definitions
– System Model
WIRE Modeling 45
Inductance
• High speed interconnects are considered as distributed
RLC transmission lines
• Zo of the interconnect equals both the output
impedance of the driver and the input impedance of
the receiver, there are no signal reflections.
• Any impedance difference introduces reflections,
which limit the energy transmitted to the receiver.
• Consequences:
– ringing and overshoot effects
– reflections of signals due to impedance mismatch
– inductive coupling between lines
– switching noise due to L (di/dt) voltage drops.
WIRE Modeling 46
Inductance
• To model the ringing, at least a second-order
approximation is required to characterize this
non-monotone, underdamped, response.
• So, the inductance should be taken into
account.
• A simpler approach to find the inductance of
wire relies on:
cl =ϵμ
WIRE Modeling 47
Contents
• Introduction
– Resistance
– Capacitance
• Wire Model
– Lumped-C Model
– Lumped-RC Model
– Elmore Delay
• Inductance
– Definitions
– System Model
WIRE Modeling 48
What is Signal Integrity ?
• At low clock frequencies, system interconnects assumed to
have no effect on the signals: transparent.
• In High-speed regime, the frequency-dependent behavior
of interconnects starts to impact the signal propagation.
• Speed is dominated by the interconnect between Tx and Rx.
Tx Interconnect Rx
Tx Rx
• Transistors • Transistors
• Passives • Passives
• Chip • Chip
• Etc. • Etc.
Example
Example
Tx Interconnect Rx
• Problems:
Delay Reflections
– Timing Noise Ringing
Ground bounce
– Voltage Noise Crosstalk
Critical net Terminations
– EMI Inductance
Parasitic IR drop
Overshoot, Undershoot
Rail-Collapse
Non-monotonic edges
These problems play a role in all interconnects:

• Smallest on-chip wire
• Cables connecting racks of boards
• everywhere in-between.
Contents
• Introduction
– Resistance
– Capacitance
• Wire Model
– Lumped-C Model
– Lumped-RC Model
– Elmore Delay
• Inductance
– Definitions
– System Model
WIRE Modeling 54
What are signal aberrations?
We would
Settling time like to have
Overshoot For Ringing
The real life
Undershoot
Nonlinearity
Overshoot
Rise time
WIRE Modeling 55
Signal Integrity
Timing
Valid accuracy
• “All the logic
Glitches-
free
problems that levels
arise in high-
speed systems Clean Good Fast
due to the shape Integrity transitions
interconnects".
• Good integrity,
signal has:
– clean shape
– valid logic levels
– timing accuracy
– glitches-free.
WIRE Modeling 56
When Signal Integrity ?
• Effective SI is Pre-Product Release.
• It must be designed and not discovered.
Pre-Prototype
It costs less here
Time = €
Validation
Post-Release
Cost of failure (M$)
WIRE Modeling 57
Signal Integrity- Discontinuity
• How the system performance can be affected by the
interconnects properties : electrical and mechanical ?
• The signal see the interconnect as an electrical

impedance.
– If the impedance stays the same --> undistorted signal.
– If the impedance changes --> reflections --> distorted
signal.
• Discontinuity
WIRE Modeling 58
• Discontinuity : any feature that changes the
impedance the signal sees.
• Socket or Connector
• Branch, tee, or stub
• line-width change
• A layer change: Via
WIRE Modeling 59
 Keep the impedance constant:
– Use a board with constant, or "controlled,"

impedance traces (uniform).
– Use routing rules that allow the topology to

maintain a constant impedance down the trace.
– Use strategically placed resistors to manipulate the

reflections and keep the received signals looking
clean.
WIRE Modeling 60
Signal Integrity- Solutions
Noise Category Design Principle
Signal Quality → Signals should see the same
impedance through all interconnects
X-Talk → Keep spacing of traces greater than

a minimum value, minimize mutual
inductance with non-ideal returns
Rail Collapse → Minimize the impedance of the

power/ground path.
EMI → Minimize bandwidth, minimize

ground impedance, and shielding
Even if these guidelines are followed, it is still essential to model and simulate the
system to evaluate whether the design will meet the performance requirements.
WIRE Modeling 61
Motivation
• Typical analysis of SI problems:
– How ?
• Circuit-level
• Transient-analysis tools, such as ELDO and SPICE
• Entirely in time domain.
– Cons
• it can not accurately account for the system interconnects,
elements of frequency-dependent behaviors and the
elements have non-ideal- frequency response.
• model the system interconnects by simplified lumped
models with no dispersion and constant loss, which is not
accurate in the high-speed regime.
WIRE Modeling 62
Contents
• Introduction
– Resistance
– Capacitance
• Wire Model
– Lumped-C Model
– Lumped-RC Model
– Elmore Delay
• Inductance
– Definitions
– System Model
WIRE Modeling 63
System Model
• Point-to-point connection.
Model is properly
configured and
terminated,
the signal integrity
excellent
WIRE Modeling 64
System Model
Stub resistor; to improve signal
quality by dampening ringing,
overshoots, and undershoots
Clock
Generator  DDR-3 SDRAM
 IBIS
 Stratix III FPGA

 IBIS
WIRE Modeling 65
System Model
Interconnect may include PCB
traces and vias, sockets, and
cables.
Clock
Generator  DDR-3 SDRAM
 IBIS
 Stratix III FPGA

 IBIS
WIRE Modeling 66
Problems
WIRE Modeling 67
References
• Rabaey, Jan, A. Chandrakasan, and B. Nikolic. Digital Integrated
Circuits: A Design Perspective. 2nd ed. Upper Saddle River, NJ:
Prentice Hall, 2002. ISBN: 0130909963.
• Dally, William, and J. Poulton. Digital System Engineering. 1st ed.

Cambridge University Press, 2008. ISBN: 978-0521061759.
• Hubert Kaeslin. Digital Integrated Circuit Design From VLSI

Architectures to CMOS Fabrication. Cambridge University Press,
2008. ISBN: 0521882672
• Eric Bogatin. Signal and Power Integrity. 2nd ed. Prentice Hall, 2009.
ISBN: 9780132349796.
WIRE Modeling 68

Wire Modeling

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The WIRE Modeling

Future University in Egypt

 Clearly such an ideal wire is not physically realizable.

• The ideal wire is a useful approximation

• Wires dominate a modern digital system in terms

X The bulk of the power in many systems is dissipated

X The amount of wiring, not the number of transistors

X The number of terminals required is a major factor in

𝜌𝑙 Rectangular Wire: on-chip wires & vias, PCB traces

• To obtain the resistance of a wire, simply multiply

1- Aluminum (𝑅∎ =0.075 Ω/∎): the total resistance of the wire

3- Silicided polysilicon (𝑅∎ =4 Ω/∎):

- It is advantageous to use a Material ϵr

Fringing Capacitance: The capacitance between the side-

– For (W/H) smaller than 1.5, the

– The fringing capacitance can

– The total capacitance levels off to

• Today’s processes offer many more layers of interconnect.

• Each wire is not only coupled to the grounded substrate, but

The case of a single

• It is often useful to lump the different fractions

• The advantage of this approach is that the effects

The operation of this RC network is

The time to reach 50% point is

- lumped RC model is pessimistic and inaccurate for long interconnect

For very large value of N

The voltage at node i of this network can be determined by solving:

reducing ΔL to 0 yields V is the voltage at a particular point in the wire,

r: distributed resistance per unit of distance

Simulated step response

These problems play a role in all interconnects:

Cost of failure (M$)

• The signal see the interconnect as an electrical

– Use a board with constant, or "controlled,"

– Use routing rules that allow the topology to

– Use strategically placed resistors to manipulate the

X-Talk → Keep spacing of traces greater than

Rail Collapse → Minimize the impedance of the

EMI → Minimize bandwidth, minimize

 Stratix III FPGA

 Stratix III FPGA

• Dally, William, and J. Poulton. Digital System Engineering. 1st ed.

• Hubert Kaeslin. Digital Integrated Circuit Design From VLSI

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