LDO regulator / low dropout regulator

LDO regulator means low dropout regulator. An LDO voltage regulator is just a DC
linear voltage regulator which can be operated with a very small input-output voltage
differential. This input output voltage differential is called dropout voltage. In simple
words dropout voltage is the voltage dropped by the regulator circuitry alone for its
working. For example, an LM2941 LDO voltage regulator has a dropout voltage of only
around 0.5V, which means that in order to get 5 volts at the output you need to input
only 5.5 volts where an ordinary 7805 linear voltage regulator has a dropout voltage of
around 2V. This means that, in order to get 5V at the output of 7805 you need to input
at least 7V.

LDO regulator working.

Schematic of a LDO regulator

The image shown above is the schematic of a typical LDO voltage regulator. The
working principle of LDO regulator is just like that of an ordinary linear voltage
regulator. The essential components of an LDO voltage regulator are a reference
voltage source, error amplifier and series pass element (BJT or MOSFET). The voltage
drop across the series pass element is controlled by the error amplifiers output in order
to control the output voltage. For example, suppose the load current decreases and as
results the output voltage tends increase. This increase in output voltage will increase
the error voltage (VERR).The output of the error amplifier will increase, making the
series pass element ( P-Channel MOSFET) less conducting, which results in the
reduction of the output voltage and the output voltage is brought back to the original
level.

A low dropout regulator (LDO) consists of a voltage reference, an error amplifier, a

feedback voltage divider, and a series pass element, usually a bipolar or CMOS
transistor (see Figure 1). Output current is controlled by the PMOS transistor, which in
turn is controlled by the error amplifier. This amplifier compares the reference voltage
with the feedback voltage from the output and amplifies the difference. If the feedback
voltage is lower than the reference voltage, the gate of the PMOS device is pulled
lower, allowing more current to pass and increasing the output voltage. If the feedback
voltage is higher than the reference voltage, the gate of the PMOS device is pulled
higher, allowing less current to pass and decreasing the output voltage. This is a closed-
loop system based around two main poles, the internal pole of the error amplifier/pass
transistor and the external pole of the output capacitor’s equivalent series resistance
(ESR).

Analog Devices LDOs are designed to be stable over the specified operating
temperature and voltage ranges when the recommended capacitors are used. The ESR
of the output capacitor affects the stability of the LDO control loop. A minimum ESR of
1 Ω or less is recommended to ensure stability. The LDOs response to rapid changes in
load current, i.e. the transient response, is also affected by output capacitance. Using a
larger value of output capacitor improves the transient response of the LDO; however,
it can increase the start-up time.
LDO regulators are used to derive lower output voltages from a main supply or battery.
The output voltage is ideally stable with line and load variations, immune to changes in
ambient temperature, and stable over time. LDOs should have as low a difference
between the input and output voltage as possible, called the dropout voltage. For
example, in a battery-powered design using a lithium-ion cell connected to a 2.8 V
LDO, the battery voltage can drop from 4.2 V (fully charged) to 3.0 V (battery empty)
and provide a constant 2.8 V output provided the LDO’s dropout voltage is below 200
mV. In some systems LDOs are used for postregulation. The LDO connects to the
output of a high-efficiency switching regulator and provides noise filtering, as well as a
constant and stable output voltage.

What is dropout voltage?
Low dropout refers to the difference between the input and
output voltages that allow the IC to regulate the output load voltage. That is, an LDO
can regulate the output load voltage until its input and output approach each other at
the dropout voltage. Ideally, the dropout voltage should be as low as possible to
minimize power dissipation and maximize efficiency. Typically, dropout is considered
to be reached when the output voltage has dropped to 100 mV below its nominal value.
The load current and pass transistor temperature affect the dropout voltage.

Working Principle of Voltage Controlled Oscillator

(VCO)
VCO circuits can be designed by means of many voltage control electronic components
such as varactor diodes, transistors, Op-amps etc. Here, we are going to discuss about
the working of a VCO using Op-amps. The circuit diagram is shown below.

The output
waveform of this VCO will be square wave. As we know the output frequency is related
to the control voltage. In this circuit the first Op-amp will function as an integrator. The
voltage divider arrangement is implemented here. Because of this, the half of the
control voltage that is given as input is given to the positive terminal of the Op-amp 1.
The same level of voltage is maintained at the negative terminal. This is to sustain the
voltage drop across the resistor, R1 as half of the control voltage.
When the MOSFET is
in on condition, the current flowing from the R1 resistor passes through the MOSFET.
The R2have half the resistance, same voltage drop and twice the current as that of R1.
So, the extra current charges the connected capacitor. The Op-amp 1 should provide a
gradually increasing output voltage to supply this current.
When the MOSFET is in off
condition, the current flowing from the R1resistor passes through the capacitor, get
discharged. The output voltage obtained from the Op-amp 1 at this time will be falling.
As a result, a triangular waveform is generated as the output of Op-amp 1.
The Op-
amp 2 will operate as Schmitt trigger. The input to this Op-amp is triangular wave
which is the output of the Op-amp 1. If the input voltage is higher than the threshold
level, the output from the Op-amp 2 will be VCC. If the input voltage is less than the
threshold level, the output from the Op-amp 2 will be zero. Therefore, the output of the
Op-amp 2 will be square wave.

The other form of circuit for a voltage controlled oscillator is shown below which is
implemented by using two operational amplifiers. It generates the square wave at the
output whose frequency is determined by a control voltage. The first op-amp works as
an integrator.

The control voltage is applied at the input terminal and due to the voltage divider
arrangement, half the control voltage is applied at the positive terminal of the first op-
amp. Also, at the negative terminal, the voltage is maintained at the same level in order
to maintain the voltage drop across the R1 is half the control voltage.

When the MOSFET is turned ON, the current from the resistor R1 flows through the
MOSFET. The voltage which is now converted into current signal charges the capacitor.
Therefore, to source this current, the first op-amp must provide a steadily rising output
voltage.

When the MOSFET is turned OFF, the current flows from the R1 and hence discharges
the capacitor. Therefore from the first op-amp falling output voltage is needed. Thus
the output of the first op-amp is a triangular waveform.

The second op-amp works as Schmitt trigger and it accepts the triangular wave as input
from the first op-amp. When the input voltage is above the threshold level, then it
outputs Vcc at its output and if the input falls below the threshold level, the output
becomes zero. Hence the square wave output is produced at the output.