Inverter Structure
Abstract voltage and may disable the system circuits when the
supply voltage drops below the threshold voltage [2].
This paper describes a simple architecture and low Many conventional undervoltage lockout circuits
power consumption undervoltage lockout (UVLO) employ a bandgap circuit for generating a reference
circuit with hysteretic threshold. The UVLO circuit voltage and a separate comparator circuit for comparing
monitors the supply voltage and determines whether or the reference voltage to a voltage divided representation
not the supply voltage satisfies a predetermined of the supply voltage, as shown in Figure 1.
condition. The under voltage lockout circuit is designed
based on CSMC 0.5um CMOS technology, utilizing a
VDD
relatively few amount of circuitry. It is realized with a
current source inverter. The threshold voltage is
determined by the WIL ratio of current source inverter
and resistor in reference generator. The hysteresis is
realized by using a feedback circuit to overcome the bad
disturbance and noise rejection of the single threshold.
Hysteretic threshold range is 40mV. The quiescent
current is about luA at 3V supply voltage, while the
power of circuit consumes only 3uW.
1. Introduction
Figure 1. Traditional UVLO circuit topology
Many circuits are sensitive to fluctuations in supply
voltage. More particularly, when the supply voltage Some undervoltage lockout circuits with bandgap
decrease below a minimum specified operating voltage, structure don't need separate comparator and reference
an under voltage condition may occur. Some circuits circuit [3], [4]. Figure 2 shows one of the undervoltage
may either be damaged or they may exhibit lockout circuit with bandgap structure. For the bandgap
unpredictable operation when operation may be structure using NPN transistors, the circuit can't be used
especially critical in circuits that include processing in standard CMOS processes.
engines such as microprocessors, microcontrollers, and
digital signal processors, for example.
The power supply is required to be stable under all
operating conditions, with all possible component
variations that may occur during the lifetime of the
system [1]. Unfortunately, there may be various reasons
for undervoltage events. In a typical battery-operated M7 Me
system such as a portable communication or computing
device, for example, the charge (and thus the voltage
potential) stored in the battery will inevitably decay. To
prevent damage or unpredictable circuit operation, it
may be desirable to disable circuit operation during
undervoltage events.
Many systems may employ an undervoltage lockout Figure 2. UVLO circuit with bandgap structure [4]
circuit to prevent operation of system circuits during
undervoltage condition. In such systems, the protection Unfortunately, these conventional implementations of
circuit may enable the system circuits to operate while undervoltage lockout circuits may utilize a relatively
the supply voltage is above a predetermined threshold large amount of circuitry and thus layout area. This also
VDD
G D
,
Where
(7) 2
,
,
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4
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: : : : �� : :
: : : (!' "VOUT : In order to reduce the power consumption of this
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o Il
��----�----�-1--�------�------� current through M3 is equal to M2, ID2=ID3, ignoring
channel length modulation,
o 2 VTH 3 4 5
VDD(V)
Figure 4. Curent source inverter
Two methods can determine the threshold voltage VTH• 800m -�------------�-----------
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above threshold voltage VTH, the current through M3 is I I I
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larger than the current through M2, the output of the 2 3 4
inverter consisted of transistors M2 and M3 (VI) is VDD ( V)
getting high, Mil is cut off. The current charges the Figure 6. The relation between VDD and VR
capacitor (MI2) through MIO (as a resistor). The voltage
V3 changes high, M13 is turned off. The branch of 3. Simulation and layout
generating reference voltage has resistor load made up of
RI and R2. The circuit output UVLO is high. The undervoltage lockout circuit is simulated by using
The gate-source voltage of M3 is getting small, while Hspice simulator based on CSMC 0. 5um CMOS process.
supply voltage is decreasing. When current through M3 First, the supply voltage VDD dc sweep ananlysis is
is less than that of M2, the output of inverter with current simulated. The hysteretic threshold is shown in Figure 7.
source load (V I) changes from high to low. The Schmitt VTHHand VTHL are different due to different initial voltage
trigger output (V2) tum on the transistor Mll, when VI VDD. Respectively, VTHH=2.57V, VTHL =2.53 V, about
is below the threshold voltage of Schmitt trigger. The 40mV hysteresis range is obtained.
capacitor (MI2) is discharged to GND through Mil,
node V3 is getting low. The circuit output UVLO
3 -
changes low to control relative circuit.
Hysteretic threshold is realized by changing the load 2.S -
resistance of the reference generator. When VDD is
above VTH, the gate of control transistor M13 is high, 2
M13 is cutoff. Equation (1) is modified to: >
1.S
u... VT VT H '
>
L
1 2(VOO-VTN2) 1 :::J
VR L = VTN 2 - KN2(R1 +R2) + KN2(R1 +R2)
+
KF.2(R1 +R2)2
SOOm
(6)
0 "'
--'-
When supply voltage VDD is below VTH, the gate of I I
2 2.S 3
control transistor M13 is low, M13 is turned on.
VOO(V)
Neglecting the RDS(ON) of M13, Equation (I) changes to:
Figure 7. Hysteretic threshold
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0...
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5 00rn
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�-4u -�------i-------� ------i------�-------�-
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Figure 10. Layout ofUVLO circuit
�-5u _ L ______ l _______ � ______ l ______ J _______ _ l
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:s
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