5 4 3 2 1

CHARGER
HPA02224RGRR-1-GP 44
INPUTS OUTPUTS
Project code:4PD00I010001 Cedar/Janus Block Diagram AD+
BT+
DCBATOUT
PCB P/N: 13269-1 SYSTEM DC/DC
Revision: X02 TPS51225RUKR-GP 45
INPUTS OUTPUTS
3D3V_AUX_S5
5V_AUX_S5
D D

DCBATOUT 5V_S5
3D3V_S5
DDR3L CPU Core Power
1333/1600 ISL95813HRZ-GP 46,47
Intel CPU DDR3L 1333/1600MHz Channel A
INPUTS OUTPUTS
33

GPU Broadwell ULT SODIMM A

12
DCBATOUT VCC_CORE
NVIDIA 28W (UMA)
VRAM(DDR3L) *4 DDR3L SUS
PCIE x 4 15W (DIS)
2GB N15V-GM-S-A2 TPS51716RUKR-GP 49

78,79
DDR3L GB2-64 (23x23) INPUTS OUTPUTS
LAN
25W 73,74,75,76,77 DCBATOUT 1D35V_S3
DIS only WPT-LP 10/100 & 10/100/1000 co-lay 0D65V_S0
8 USB 2.0/1.1 ports
RealTek
Cedar:(10/100)RTL8106E CPU 1.05V
4 USB 3.0 ports
PCIE x 1 Janus:(10/100/1000)RTL8111G RJ45 RT8237CZQW-2-GP 48
High Definition Audio
VGA Conn. VGA DP/VGA Converter (Janus only) DP 4 SATA ports
Conn. 31
INPUTS OUTPUTS
30 DCBATOUT 1D05V_S0
(Janus only) RTD2168 55
8 PCIE ports
LPC I/F CPU 1D5V_S0
C C
ACPI 4.0a TLV70215DBVR-GP 51
INPUTS OUTPUTS
PCIE x 1 WLAN 3D3V_S5 1D5V_S0
HDMI V1.4a 802.11a/b/g/n
HDMI Switches 36 83
(Cedar only) 54
USB2.0 x 1 BT V4.0 combo
58
INPUTS OUTPUTS
Left side 1D35V_S3 1D35V_S0
14.0"/15"/17" LCD USB2.0 x 1 5V_S5 5V_S0
eDP
(16:9) 52 USB1(USB3.0) 3D3V_S5 3D3V_S0

USB3.0 x 1 1D05V_S0 1D05V_VGA_S0

34,35
3D3V_S0 3D3V_VGA_S0
Touch Panel USB2.0 x 1 1D35V_S3 1D35V_VGA_S0
Left side

USB2.0 x 1 USB2(USB2.0)
Camera
USB2.0 x 1
Digital MIC 52
34,35 PCB LAYER
L1:Top
L2:VCC
B HDA Right side IO Board L3:Signal B

MIC_IN/GND L4:Signal
CODEC USB2.0 x 1 USB3(USB2.0) L5:GND
Realtek HDA L6:Signal
HP_R/L ALC3234
29
Combo Jack 27

2CH SPEAKER
(2CH 2W/4ohm) CardReader SD Card Slot
USB2.0 x 1
Realtek
RTS5170
29 LPC debug port LPC BUS
65

Thermal
NUVOTON SMBUS
NCT7718W 26 KBC SATA(Gen3) x 1 HDD
NUVOTON 56
SPI
Fan Control NPCE285P
ANPEC 24
A APL5606AKI 26 A

Flash ROM SATA(Gen1) x 1 ODD

PS2 8MB 56
Int. Quad Read 25
<Core Design>

FAN26 KB 62
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Touch PAD I2C Taipei Hsien 221, Taiwan, R.O.C.
Image sensor Title
62 Block Diagram
Size Document Number Rev
C Janus HSW 40/50/70 X02
Date: Friday, February 07, 2014 Sheet 2 of 104
5 4 3 2 1
 5 4 3 2 1

D D

(Blanking)
C C

B B

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

(Reserved)
Size Document Number Rev
A4
Janus HSW 40/50/70 A00
Date: Friday, February 07, 2014 Sheet 3 of 104
5 4 3 2 1
 5 4 3 2 1

SSID = CPU
1D05S_VCCST

RN401
XDP_TMS 1 8
XDP_TDI 2 7
D D
XDP_TDO
3
4
DY 6
5

SRN51J-1-GP

XDP_TRST# R402 1
DY 2 51R2J-2-GP
XDP_TCLK R406 1 2 51R2J-2-GP

1D05S_VCCST
HSW_ULT_DDR3L
CPU1B 2 OF 19
Remove TP401 for TP604 spacing.
1

R401 D61
62R2J-GP TP402 H_CATERR# PROC_DETECT# MISC
1 K61 CATERR# XDP_PRDY#
C
Layout Note: [24] H_PECI N62 PECI PRDY# J62
K62 XDP_PREQ#
XDP_PRDY# [96]
XDP_PREQ# [96] C
2

PREQ# XDP_TCLK
Impedance control:50 ohm PROC_TCK E60 XDP_TCLK [96]
E61 XDP_TMS XDP_TMS [96]
JTAG PROC_TMS
[24,42,44,46] H_PROCHOT# 1 2 H_PROCHOT#_R K63 PROCHOT# PROC_TRST# E59 XDP_TRST# XDP_TRST# [96]
R403 THERMAL F63 XDP_TDI XDP_TDI [96]
TP403 PROC_TDI XDP_TDO
156R2J-4-GP PROC_TDO F62 XDP_TDO [96]
DY H_CPUPWRGD
[36] H_THERMTRIP_EN 1 2 C61 PROCPWRGD
R411 PWR XDP_BPM[7:0]
R405 XDP_BPM[7:0] [96]
2 1 J60 XDP_BPM0
0R2J-2-GP BPM#0 XDP_BPM1
10KR2J-3-GP BPM#1 H60
Layout Note: Close to CPU H61 XDP_BPM2
BPM#2 XDP_BPM3
BPM#3 H62
SM_RCOMP_0 AU60 K59 XDP_BPM4
SM_RCOMP_1 SM_RCOMP0 DDR3L BPM#4 XDP_BPM5
AV60 SM_RCOMP1 BPM#5 H63
SM_RCOMP_2 AU61 K60 XDP_BPM6
SM_DRAMRST# SM_RCOMP2 BPM#6 XDP_BPM7
AV15 SM_DRAMRST# BPM#7 J61
DDR_PG_CTRL AV61
[12] DDR_PG_CTRL SM_PG_CNTL1

B B
HASWELL-6-GP-U

R407 1 200R2F-L-GP SM_RCOMP_0 71.HASWE.G0U 1D35V_S3

2
Layout Note:
R408 1 2 121R2F-GP SM_RCOMP_1 Place close to DIMM
R409 1 2 100R2F-L1-GP-U SM_RCOMP_2 1 R410
470R2J-2-GP
2

SM_DRAMRST# 1 R404 2 DDR3_DRAMRST# [12]

0R0402-PAD
Layout Note: <Core Design>
Design Guideline:
SM_RCOMP keep routing length less than 500 mils.
A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (THERMAL/MISC/PM)
Size Document Number Rev
A4 A00
Janus HSW 40/50/70
Date: Friday, February 07, 2014 Sheet 4 of 104
5 4 3 2 1
 5 4 3 2 1

SSID = CPU
DDR3L ball type: Non-Interleaved Type
CPU1D HSW_ULT_DDR3L 4 OF 19
HSW_ULT_DDR3L 3 OF 19
CPU1C

M_A_DQ[63:0]
[12] M_A_DQ[63:0]
M_A_DQ0 AH63 AU37 AY31 AM38
M_A_DQ1 SA_DQ0 SA_CLK#0 M_A_DIMA_CLK_DDR#0 [12] SB_DQ0 SB_CK#0
AH62 AV37 AW31 AN38
M_A_DQ2 SA_DQ1 SA_CLK0 M_A_DIMA_CLK_DDR0 [12] SB_DQ1 SB_CK0
AK63 AW36 AY29 AK38
M_A_DQ3 SA_DQ2 SA_CLK#1 M_A_DIMA_CLK_DDR#1 [12] SB_DQ2 SB_CK#1
AK62 AY36 AW29 AL38
M_A_DQ4 SA_DQ3 SA_CLK1 M_A_DIMA_CLK_DDR1 [12] SB_DQ3 SB_CK1
D AH61 AV31 D
M_A_DQ5 SA_DQ4 SB_DQ4
AH60 AU43 AU31 AY49
M_A_DQ6 SA_DQ5 SA_CKE0 M_A_DIMA_CKE0 [12] SB_DQ5 SB_CKE0
AK61 AW43 AV29 AU50
M_A_DQ7 SA_DQ6 SA_CKE1 M_A_DIMA_CKE1 [12] SB_DQ6 SB_CKE1
AK60 AY42 AU29 AW49
M_A_DQ8 SA_DQ7 SA_CKE2 SB_DQ7 SB_CKE2
AM63 AY43 AY27 AV50
M_A_DQ9 SA_DQ8 SA_CKE3 SB_DQ8 SB_CKE3
AM62 AW27
M_A_DQ10 SA_DQ9 SB_DQ9
AP63 AP33 AY25 AM32
M_A_DQ11 SA_DQ10 SA_CS#0 M_A_DIMA_CS#0 [12] SB_DQ10 SB_CS#0
AP62 AR32 AW25 AK32
M_A_DQ12 SA_DQ11 SA_CS#1 M_A_DIMA_CS#1 [12] SB_DQ11 SB_CS#1
AM61 AV27
M_A_DQ13 SA_DQ12 TP_M_A_DIMA_ODT0 TP501 SB_DQ12
AM60 AP32 1 AU27 AL32
M_A_DQ14 SA_DQ13 SA_ODT0 SB_DQ13 SB_ODT0
AP61 AV25
M_A_DQ15 SA_DQ14 SB_DQ14
AP60 AY34 M_A_RAS# [12] AU25 AM35
M_A_DQ16 SA_DQ15 SA_RAS# SB_DQ15 SB_RAS#
AP58 AW34 M_A_WE# [12] AM29 AK35
M_A_DQ17 SA_DQ16 SA_WE# SB_DQ16 SB_WE#
AR58 AU34 M_A_CAS# [12] AK29 AM33
M_A_DQ18 SA_DQ17 SA_CAS# SB_DQ17 SB_CAS#
AM57 AL28
M_A_DQ19 SA_DQ18 SB_DQ18
AK57 AU35 M_A_BS0 [12] AK28 AL35
M_A_DQ20 SA_DQ19 SA_BA0 SB_DQ19 SB_BA0
AL58 AV35 M_A_BS1 [12] AR29 AM36
M_A_DQ21 SA_DQ20 SA_BA1 SB_DQ20 SB_BA1
AK58 AY41 M_A_BS2 [12] AN29 AU49
M_A_DQ22 SA_DQ21 SA_BA2 SB_DQ21 SB_BA2
AR57 AR28
M_A_DQ23 SA_DQ22 M_A_A0 M_A_A[15:0] [12] SB_DQ22
AN57 AU36 AP28 AP40
M_A_DQ24 SA_DQ23 SA_MA0 M_A_A1 SB_DQ23 SB_MA0
AP55 AY37 AN26 AR40
M_A_DQ25 SA_DQ24 SA_MA1 M_A_A2 SB_DQ24 SB_MA1
AR55 AR38 AR26 AP42
M_A_DQ26 SA_DQ25 SA_MA2 M_A_A3 SB_DQ25 SB_MA2
AM54 AP36 AR25 AR42
M_A_DQ27 SA_DQ26 SA_MA3 M_A_A4 SB_DQ26 SB_MA3
AK54 AU39 AP25 AR45
M_A_DQ28 SA_DQ27 SA_MA4 M_A_A5 SB_DQ27 SB_MA4
AL55 AR36 AK26 AP45
M_A_DQ29 SA_DQ28 SA_MA5 M_A_A6 SB_DQ28 SB_MA5
AK55 AV40 AM26 AW46
M_A_DQ30 SA_DQ29 SA_MA6 M_A_A7 SB_DQ29 SB_MA6
AR54 AW39 AK25 AY46
M_A_DQ31 SA_DQ30 DDR CHANNEL A SA_MA7 M_A_A8 SB_DQ30 SB_MA7
AN54 AY39 AL25 AY47
M_A_DQ32 SA_DQ31 SA_MA8 M_A_A9 SB_DQ31 DDR CHANNEL B SB_MA8
AY58 AU40 AY23 AU46
M_A_DQ33 SA_DQ32 SA_MA9 M_A_A10 SB_DQ32 SB_MA9
AW58 AP35 AW23 AK36
M_A_DQ34 SA_DQ33 SA_MA10 M_A_A11 SB_DQ33 SB_MA10
AY56 AW41 AY21 AV47
M_A_DQ35 SA_DQ34 SA_MA11 M_A_A12 SB_DQ34 SB_MA11
AW56 AU41 AW21 AU47
M_A_DQ36 SA_DQ35 SA_MA12 M_A_A13 SB_DQ35 SB_MA12
AV58 AR35 AV23 AK33
M_A_DQ37 SA_DQ36 SA_MA13 M_A_A14 SB_DQ36 SB_MA13
AU58 AV42 AU23 AR46
M_A_DQ38 SA_DQ37 SA_MA14 M_A_A15 SB_DQ37 SB_MA14
AV56 AU42 AV21 AP46
M_A_DQ39 SA_DQ38 SA_MA15 SB_DQ38 SB_MA15
AU56 M_A_DQS#[7:0] [12] AU21
M_A_DQ40 SA_DQ39 M_A_DQS#0 SB_DQ39
AY54 AJ61 AY19 AW30
M_A_DQ41 SA_DQ40 SA_DQSN0 M_A_DQS#1 SB_DQ40 SB_DQSN0
AW54 AN62 AW19 AV26
M_A_DQ42 SA_DQ41 SA_DQSN1 M_A_DQS#2 SB_DQ41 SB_DQSN1
AY52 AM58 AY17 AN28
M_A_DQ43 SA_DQ42 SA_DQSN2 M_A_DQS#3 SB_DQ42 SB_DQSN2
AW52 AM55 AW17 AN25
M_A_DQ44 SA_DQ43 SA_DQSN3 M_A_DQS#4 SB_DQ43 SB_DQSN3
AV54 AV57 AV19 AW22
M_A_DQ45 SA_DQ44 SA_DQSN4 M_A_DQS#5 SB_DQ44 SB_DQSN4
C AU54 AV53 AU19 AV18 C
M_A_DQ46 SA_DQ45 SA_DQSN5 M_A_DQS#6 SB_DQ45 SB_DQSN5
AV52 AL43 AV17 AN21
M_A_DQ47 SA_DQ46 SA_DQSN6 M_A_DQS#7 SB_DQ46 SB_DQSN6
AU52 AL48 AU17 AN18
M_A_DQ48 SA_DQ47 SA_DQSN7 SB_DQ47 SB_DQSN7
AK40 M_A_DQS[7:0] [12] AR21
M_A_DQ49 SA_DQ48 M_A_DQS0 SB_DQ48
AK42 AJ62 AR22 AV30
M_A_DQ50 SA_DQ49 SA_DQSP0 M_A_DQS1 SB_DQ49 SB_DQSP0
AM43 AN61 AL21 AW26
M_A_DQ51 SA_DQ50 SA_DQSP1 M_A_DQS2 SB_DQ50 SB_DQSP1
AM45 AN58 AM22 AM28
M_A_DQ52 SA_DQ51 SA_DQSP2 M_A_DQS3 SB_DQ51 SB_DQSP2
AK45 AN55 AN22 AM25
M_A_DQ53 SA_DQ52 SA_DQSP3 M_A_DQS4 SB_DQ52 SB_DQSP3
AK43 AW57 AP21 AV22
M_A_DQ54 SA_DQ53 SA_DQSP4 M_A_DQS5 SB_DQ53 SB_DQSP4
AM40 AW53 AK21 AW18
M_A_DQ55 SA_DQ54 SA_DQSP5 M_A_DQS6 SB_DQ54 SB_DQSP5
AM42 AL42 AK22 AM21
M_A_DQ56 SA_DQ55 SA_DQSP6 M_A_DQS7 SB_DQ55 SB_DQSP6
AM46 AL49 AN20 AM18
M_A_DQ57 SA_DQ56 SA_DQSP7 SB_DQ56 SB_DQSP7
AK46 AR20
M_A_DQ58 SA_DQ57 SB_DQ57
AM49 AP49 +V_SM_VREF_CNT +V_SM_VREF_CNT [37] AK18
M_A_DQ59 SA_DQ58 SM_VREF_CA SB_DQ58
AK49 AR51 DDR_WR_VREF01 [37] AL18
M_A_DQ60 SA_DQ59 SM_VREF_DQ0 SB_DQ59
AM48 AP51 AK20
M_A_DQ61 SA_DQ60 SM_VREF_DQ1 SB_DQ60
AK48 AM20
M_A_DQ62 SA_DQ61 SB_DQ61
AM51 AR18
M_A_DQ63 SA_DQ62 SB_DQ62
AK51 AP18
SA_DQ63 SB_DQ63

HASWELL-6-GP-U
HASWELL-6-GP-U

B B

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (DDR)
Size Document Number Rev
A2 A00
Janus HSW 40/50/70
Date: Friday, February 07, 2014 Sheet 5 of 104
5 4 3 2 1
 5 4 3 2 1

SSID = CPU

D D

CPU1S HSW_ULT_DDR3L 19 OF 19
#514405

CFG[19:0]
[96] CFG[19:0]
CFG0 AC60 AV63 RSVDAV63 1 TP601
CFG1 CFG0 RSVD_TP#AV63 RSVDAU63 TP602
AC62 CFG1 RSVD_TP#AU63 AU63 1
CFG2 AC63
CFG3 CFG2
AA63 CFG3
CFG4 AA60 C63 RSVDC63 1 TP603
CFG5 CFG4 RSVD_TP#C63 RSVDC62 TP604
Y62 CFG5 RSVD_TP#C62 C62 1
CFG6 Y61 B43 EDP_SPARE 1 TP605
CFG7 CFG6 RSVD#B43
Y60 CFG7
CFG8 V62 A51 RSVDA51 1 TP606
CFG9 CFG8 RSVD_TP#A51 RSVDB51 TP607
V61 CFG9 RSVD_TP#B51 B51 1
CFG10 V60
CFG11 CFG10 RSVDL60 TP608
U60 CFG11 RSVD_TP#L60 L60 1
CFG12 T63
CFG13 CFG12 RESERVED
T62 CFG13 RSVD#N60 N60
CFG14 T61 Intel Recommend
CFG15 CFG14
T60 CFG15 RSVD#W23 W23
Y22 PROC_OPI_COMP3 R606 1 DY 2 49D9R2F-GP
CFG16 RSVD#Y22
AA62 CFG16 PROC_OPI_RCOMP AY15 PROC_OPI_COMP R602 1 2 49D9R2F-GP
CFG18 U63
CFG17 CFG18
AA61 CFG17 RSVD#AV62 AV62
CFG19 U62 D58
C CFG19 RSVD#D58 C
1 2 CFG_RCOMP V63 P22
CFG_RCOMP VSS
N21
Layout Note:
R601 VSS
A5 RSVD#A5
1.Referenced "continuous" VSS plane only.
49D9R2F-GP P20 HVM_CLK# 1 2.Avoid routing next to clock pins or noisy
RSVD#P20
E1 R20 HVM_CLK 1 TP619
D1
RSVD#E1 RSVD#R20 TP620 signals.
RSVD#D1 3.Trace width: 12~15mil
J20 RSVD#J20
H18 RSVD#H18 4.Isolation Spacing: 12mil
1 2 TD_IREF B12 5.Max length: 500mil
TD_IREF
R603
8K2R2F-1-GP

#514405 PCH strap pin:

CFG3
1

PHYSICAL_DEBUG_ENABLED (DFX PRIVACY)

R604
1KR2J-1-GP 0 : ENABLED
DY CFG[3] SET DFX ENABLED BIT IN DEBUG INTERFACE MSR
2

1 : DISABLED

B B
CFG4
1

DISPLAY PORT PRESENCE STRAP

R605
1KR2J-1-GP 0 : ENABLED
CFG[4] AN EXTERNAL DISPLAY PORT DEVICE IS CONNECTED TO THE EMBEDDED DISPLAY PORT
2

1 : DISABLED
NO PHYSICAL DISPLAY PORT ATTACHED TO EMBEDDED DISPLAY PORT

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (CFG)
Size Document Number Rev
A3 A00
Janus HSW 40/50/70
Date: Friday, February 07, 2014 Sheet 6 of 104
5 4 3 2 1
 5 4 3 2 1

SSID = CPU

VCC_CORE
HSW_ULT_DDR3L 12 OF 19
D CPU1L D

L59 RSVD#L59 VCC C36

1D35V_S3 J58 C40
RSVD#J58 VCC
VCC C44
1D05S_VCCST AH26 C48
VDDQ VCC
AJ31 VDDQ VCC C52
AJ33 VDDQ VCC C56
R703 1 2 75R2F-2-GP VR_SVID_ALERT# AJ37 E23
VDDQ VCC
AN33 VDDQ VCC E25
R704 1 2 130R2F-1-GP H_CPU_SVIDDAT AP43 E27
VCC_CORE VDDQ VCC
AR48 E29
Layout Note: AY35
VDDQ VCC
E31
VDDQ VCC
1. Place close to CPU AY40 VDDQ VCC E33
#487822 2. VCC_SENSE/ VSS_SENSE AY44 VDDQ VCC E35

1
AY50 E37
impedance=50 ohm VDDQ VCC
E39
3. Length match<25mil R702 VCC
VCC_CORE F59 VCC VCC E41
100R2F-L1-GP-U N58 E43
RSVD#N58 VCC
AC58 E45

2
RSVD#AC58 VCC
VCC E47
[46] VCC_SENSE E63 VCC_SENSE VCC E49
AB23 RSVD#AB23 VCC E51
TP701 1 TP_VCCIO_OUT A59 VCCIO_OUT VCC E53
+VCCIOA_OUT E20 VCCIOA_OUT VCC E55
AD23 RSVD#AD23 VCC E57
AA23 RSVD#AA23 VCC F24
R701 AE59 F28
43R2J-GP RSVD#AE59 VCC
VCC F32
C
[46] VR_SVID_ALERT# 1 2H_CPU_SVIDALRT# L62 VIDALERT# VCC F36 C
H_CPU_SVIDCLK N63 HSW ULT POWER F40
3D3V_S5 [46] H_CPU_SVIDCLK VIDSCLK VCC
H_CPU_SVIDDAT L63 F44
[46] H_CPU_SVIDDAT VIDSOUT VCC
H_VCCST_PW RGD B59 F48
VCCST_PWRGD VCC
SCD1U16V2KX-3GP

[46] H_VR_ENABLE F60 VR_EN VCC F52

C702 R710 1 2 10KR2J-3-GP
1D05S_VCCST IMVP_PW RGD_R DY C59 VR_READY VCC F56
G23
VCC
1

D63 VSS VCC G25

DY [96] PW R_DEBUG PW R_DEBUG H59 G27
PWR_DEBUG# VCC
1D05S_VCCST R705 1 2150R2J-L1-GP-U P62 G29
2

RSVDP60 VSS VCC

TP702 1 P60 RSVD_TP#P60 VCC G31
1

TP703 1 RSVDP61 P61 G33

U701 R706 RSVDN59 RSVD_TP#P61 VCC
TP704 1 N59 RSVD_TP#N59 VCC G35

1 5 DY 10KR2J-3-GP TP705 1 RSVDN61 N61

T59
RSVD_TP#N61 VCC G37
G39
NC#1 VCC RSVD#T59 VCC
AD60 G41
2

RSVD#AD60 VCC
2
[36,48] 1D05V_VTT_PW RGD A DY AD59
AA59
RSVD#AD59 VCC G43
G45
RSVD#AA59 VCC
3 GND Y 4 H_VCCST_PW RGD [96] AE60 RSVD#AE60 VCC G47
AC59 RSVD#AC59 VCC G49
EC701 AG58 G51
RSVD#AG58 VCC
1

74LVC1G07GW -GP DY U59 G53

1D05S_VCCST RSVD#U59 VCC
73.01G07.0HG V59 G55
SCD1U16V2KX-3GP

1D05V_S0 1D05S_VCCST RSVD#V59 VCC

R711 G57
2

VCC
0.1A AC22 VCCST VCC H23
1 2 AE22 J23

SC1U10V2KX-1GP
VCC_CORE VCCST VCC
1 2 AE23 K23

SC22U6D3V5MX-2GP
VCCST VCC

C701
R707 K57
VCC

C703
100KR2F-L1-GP 0R0603-PAD-1-GP-U AB57 L22
VCC VCC
1

B B
R709
DY DY AD57 VCC VCC M23
AG57 M57

2
47KR2F-GP VCC VCC
C24 VCC VCC P57
C28 VCC VCC U57
C32 W57
2

VCC VCC
Need to fine tune to 1.05V.
HASW ELL-6-GP-U

[24,46] IMVP_PW RGD 1 2 IMVP_PW RGD_R

R713
100KR2F-L1-GP EC702
1

1
R712
DY
SCD1U16V2KX-3GP

47KR2F-GP
2
2

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (VCC CORE)

Size Document Number Rev
A3 A00
Janus HSW 40/50/70
Date: Friday, February 07, 2014 Sheet 7 of 104
5 4 3 2 1
 5 4 3 2 1

SSID = CPU
www.vinafix.vn
D D

CPU1A HSW_ULT_DDR3L 1 OF 19

[55] PCH_DPB_N0 C54 DDI1_TXN0 EDP_TXN0 C45 EDP_TX0_DN [52]

[55] PCH_DPB_P0 C55 DDI1_TXP0 EDP_TXP0 B46 EDP_TX0_DP [52]
[55] PCH_DPB_N1 B58 DDI1_TXN1 EDP_TXN1 A47 EDP_TX1_DN [52]
[55] PCH_DPB_P1 C58 DDI1_TXP1 EDP_TXP1 B47 EDP_TX1_DP [52]
B55 DDI1_TXN2
A55 C47 +VCCIOA_OUT
DDI1_TXP2 EDP_TXN2
A57 DDI1_TXN3 EDP_TXP2 C46 Design Guideline:
B57 DDI1_TXP3 EDP_TXN3 A49 EDP_COMP keep routing length max 100 mils.

1
R801
C C51
DDI EDP
EDP_TXP3 B49
24D9R2F-L-GP
Trace Width:20 mils. C
DDI2_TXN0
DP to VGA Converter C50
C53
DDI2_TXP0
DDI2_TXN1
EDP_AUXN
EDP_AUXP
A45
B45
EDP_AUX_DN [52]
EDP_AUX_DP [52]
B54

2
DDI2_TXP1 EDP_COMP
C49 DDI2_TXN2 EDP_RCOMP D20
B50 A43 EDP_BRIGHTNESS 1 TP801
DDI2_TXP2 EDP_DISP_UTIL
A53 DDI2_TXN3
B53 DDI2_TXP3

HASW ELL-6-GP-U

B B

A <Core Design>
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (DDI/EDP)
Size Document Number Rev
A3 X02
Janus HSW 40/50/70
Date: Friday, February 07, 2014 Sheet 8 of 104
 5 4 3 2 1

SSID = CPU
CPU1P HSW_ULT_DDR3L 16 OF 19

VSS H17
D33 VSS VSS H57
D34 VSS VSS J10
D D35 J22 D
VSS VSS
D37 VSS VSS J59
D38 VSS VSS J63
D39 VSS VSS K1
D41 VSS VSS K12
D42 VSS VSS L13
D43 VSS VSS L15
D45 VSS VSS L17
D46 VSS VSS L18
D47 VSS VSS L20
D49 VSS VSS L58
D5 VSS VSS L61
D50 VSS VSS L7
D51 VSS VSS M22
D53 VSS VSS N10
D54 VSS VSS N3
D55 VSS VSS P59
D57 VSS VSS P63
D59 VSS VSS R10
D62 VSS VSS R22
C D8 R8 C
VSS VSS
E11 VSS VSS T1
E17 VSS VSS T58
F20 VSS VSS U20
F26 VSS VSS U22
F30 VSS VSS U61
F34 VSS VSS U9
F38 VSS VSS V10
F42 VSS VSS V3
F46 VSS VSS V7
F50 VSS VSS W20
F54 VSS VSS W22
F58 VSS VSS Y10
F61 VSS VSS Y59
G18 VSS VSS Y63
G22 VSS
G3 VSS
G5 VSS VSS V58
G6 VSS VSS AH46
G8 VSS VSS V23
B H13 E62 VSS_SENSE VSS_SENSE [46] B
VSS VSS_SENSE
VSS AH16

100R2F-L1-GP-U
1
HASWELL-6-GP-U
Layout Note:

R901
1. Place close to CPU
2. VCC_SENSE/ VSS_SENSE

2
impedance=50 ohm
3. Length match<25mil

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (VSS)
Size Document Number Rev
A4 A00
Janus HSW 40/50/70
Date: Friday, February 07, 2014 Sheet 9 of 104
5 4 3 2 1
 5 4 3 2 1

SSID = CPU

1D35V_S3

D D

Layout Note:
SC10U10V5KX-2GP

SC10U10V5KX-2GP

SC10U10V5KX-2GP

SC10U10V5KX-2GP

SC10U10V5KX-2GP

SC10U10V5KX-2GP
1

1
C1001

C1002

C1003

C1004

C1005

C1006
DY DY DY As close to CPU as possible
2

2
SC2D2U6D3V2MX-GP

SC2D2U6D3V2MX-GP

SC2D2U6D3V2MX-GP

SC2D2U6D3V2MX-GP
C1017

C1018

C1019

C1020
1

1
DY DY
2

Layout Note:
Direct tie to CPU VccIn/Vss balls

C C

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (Power CAP1)

Size Document Number Rev
A3
Janus HSW 40/50/70 A00
Date: Friday, February 07, 2014 Sheet 10 of 104
5 4 3 2 1
 5 4 3 2 1

MAX: 1.92A

1.838A 41mA 42mA

D D
1D05V_HSIO +V1.05DX_MODPHY_PCH 1D05V_HSIO +V1.05S_ASATA3PLL
R1101 1D05V_HSIO +V1.05S_AUSB3PLL
1 2 L1102 1 2 0R3J-0-U-GP +V1.05S_ASATA3PLL
L1101 1 2 0R3J-0-U-GP +V1.05S_AUSB3PLL

1
C1102

C1101
0R0805-PAD-1-GP-U

SC1U10V2KX-1GP

SC1U10V2KX-1GP

1
C1105

C1106

C1107
SC1U10V2KX-1GP

SC10U10V5KX-2GP

SC10U10V5KX-2GP
1

1
C1103

C1104

C1123
DY DY

SC1U10V2KX-1GP

SC10U10V5KX-2GP

SC10U10V5KX-2GP
2

2
DY DY

2
2

2
CAP need close to pin K9 L10 CAP need close to pin B18 CAP need close to pin B11

57mA 62mA 185mA

1D05V_S0 +V1.05S_APLLOPI 1D05V_S0 +V1.05S_AXCK_DCB

3D3V_S5_PCH +V3.3A_PSUS
L1103 1 2 IND-2D2UH-196-GP +V1.05S_AXCK_DCB
C 1 R1102 2 +V1.05S_APLLOPI 1 R1103 2 C
68.2R21D.10R

1
C1111
C1108

C1112

C1125
0R0603-PAD-1-GP-U 0R0603-PAD-1-GP-U

SC1U10V2KX-1GP
SC10U10V5KX-2GP

SC10U10V5KX-2GP

SC10U10V5KX-2GP
1

1
C1109

C1110

C1124
DY DY DY
SC1U10V2KX-1GP

SC10U10V5KX-2GP

SC10U10V5KX-2GP
DY DY

2
2

2
CAP need close to pin AA21 CAP need close to pin AC9 CAP need close to pin J18

31mA 658mA 1.632A 1mA

1D05V_S0 +1.05M_ASW 1D05V_S0 +V1.05S_CORE_PCH

1D05V_S0 R1105
IND-2D2UH-196-GP +V1.05S_AXCK_LCPLL RTC_AUX_S5
L1104 1 R1104 2 1 2
1 2 C1120 C1121

C1118

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
0R0603-PAD-1-GP-U 0R0805-PAD-1-GP-U
68.2R21D.10R
1

1
C1116

C1117

C1122
C1115

C1119
DY

SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP
SC10U10V5KX-2GP

SC10U10V5KX-2GP
1

1
C1113

C1114

DY DY
SC1U10V2KX-1GP

SC10U10V5KX-2GP

DY
2

2
B B
2

CAP need close to pin A20 CAP need close to pin AE9 CAP need close to pin AE8 J11 CAP need close to pin AG10

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (Power CAP2)

Size Document Number Rev
A3
Janus HSW 40/50/70 A00
Date: Friday, February 07, 2014 Sheet 11 of 104
5 4 3 2 1
 5 4 3 2 1

SSID = MEMORY
SA0_DIMA
SA1_DIMA
Note:
SA0 DIM0 = 0, SA1_DIM0 = 0

1
R1202 R1201
SO-DIMMA SPD Address is 0xA0
D DM1 0R0402-PAD 0R0402-PAD SO-DIMMA TS Address is 0x30 D
[5] M_A_A[15:0]
M_A_A0 98 NP1

2
M_A_A1 A0 NP1
97 NP2
M_A_A2 A1 NP2
96
M_A_A3 A2
95 110 M_A_RAS# [5]
M_A_A4 A3 RAS#
92 113 M_A_WE# [5]
M_A_A5 A4 WE#
91 115 M_A_CAS# [5]
M_A_A6 A5 CAS#
90
M_A_A7 A6
86 114 M_A_DIMA_CS#0 [5]
M_A_A8 A7 CS0#
89 121 M_A_DIMA_CS#1 [5]
M_A_A9 A8 CS1#
85
M_A_A10 A9
107 73 M_A_DIMA_CKE0 [5]
M_A_A11 A10/AP CKE0
84 74 M_A_DIMA_CKE1 [5]
M_A_A12 A11 CKE1
83
M_A_A13 A12
119 101 M_A_DIMA_CLK_DDR0 [5]
M_A_A14 A13 CK0
80 103 M_A_DIMA_CLK_DDR#0 [5]
M_A_A15 A14 CK0#
78
A15
79 102 M_A_DIMA_CLK_DDR1 [5]
[5] M_A_BS2 A16/BA2 CK1
104 M_A_DIMA_CLK_DDR#1 [5]
CK1#
109
[5] M_A_BS0 BA0
108 11
[5] M_A_BS1 BA1 DM0
[5] M_A_DQ[63:0] 28
M_A_DQ13 DM1
5 46
M_A_DQ8 DQ0 DM2
7 63
M_A_DQ14 DQ1 DM3
15 136
M_A_DQ10 DQ2 DM4
M_VREF_CA_DIMMA Layout Note: M_A_DQ9
17
4
DQ3 DM5
153
170
M_A_DQ12 DQ4 DM6
Place these caps 6
DQ5 DM7
187
M_A_DQ15 16
close to VREF_CA M_A_DQ11 DQ6
18 200 PCH_SMBDATA [18,62,96]
M_A_DQ29 DQ7 SDA
21 202 PCH_SMBCLK [18,62,96]
M_A_DQ28 DQ8 SCL
23
M_A_DQ30 DQ9 3D3V_S0
33 198
1

M_A_DQ31 DQ10 EVENT#

35
C1201 C1218 C1202 M_A_DQ25 DQ11
22 199
M_A_DQ24 DQ12 VDDSPD
24
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
2

M_A_DQ27 DQ13 SA0_DIMA

34 197

1
M_A_DQ26 DQ14 SA0 SA1_DIMA
36 201
M_A_DQ44 DQ15 SA1 C1203
M_A_DQ41
39
DQ16 DY
41 77

SCD1U16V2KX-3GP
2
M_A_DQ43 DQ17 NC#1
C 51 122 C
M_A_DQ47 DQ18 NC#2 1D35V_S3
53 125
M_A_DQ45 DQ19 NC#/TEST
40
M_A_DQ40 DQ20
42 75
M_A_DQ42 DQ21 VDD1
50 76
M_A_DQ46 DQ22 VDD2
Layout Note: M_A_DQ51
52
57
DQ23 VDD3
81
82
M_A_DQ50 DQ24 VDD4
Place these caps 59
DQ25 VDD5
87
M_A_DQ49 67 88
close to VREF_DQ M_A_DQ48 DQ26 VDD6 1D35V_S3
69 93
M_VREF_DQ_DIMMA M_A_DQ52 DQ27 VDD7
56 94
M_A_DQ53 DQ28 VDD8
58 99
M_A_DQ54 DQ29 VDD9
68 100

SC10U10V5KX-2GP

SC10U10V5KX-2GP

SC10U10V5KX-2GP
M_A_DQ55 DQ30 VDD10
70 105
M_A_DQ0 DQ31 VDD11

C1220

C1221

C1222
129 106

ST330U2VDM-4-GP
TC1201
M_A_DQ1 DQ32 VDD12
131 111

1
M_A_DQ2 DQ33 VDD13
141 112
1

M_A_DQ6 DQ34 VDD14

C1207

C1208

C1209
M_A_DQ5
143
DQ35 VDD15
117
DY
C1205

C1204 C1206 130 118 DY DY

DY
SC2D2U10V3KX-1GP

2
M_A_DQ4 DQ36 VDD16
132 123

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
2

M_A_DQ3 DQ37 VDD17

140 124
M_A_DQ7 DQ38 VDD18
142
M_A_DQ21 DQ39
147 2
M_A_DQ20 DQ40 VSS
149 3
M_A_DQ17 DQ41 VSS
157 8
M_A_DQ16 DQ42 VSS
159 9
M_A_DQ18 DQ43 VSS
146 13
0D675V_S0 M_A_DQ19 DQ44 VSS

C1211
148 14

SC1U10V2KX-1GP

SC1U10V2KX-1GP
M_A_DQ22 DQ45 VSS

C1212

C1213
158 19

1
M_A_DQ23 DQ46 VSS
160 20
M_A_DQ36 DQ47 VSS C1210
M_A_DQ33
163
DQ48 VSS
25 DY
165 26

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
2

2
M_A_DQ34 DQ49 VSS
175 31
SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP

M_A_DQ38 DQ50 VSS

C1214

C1215

C1216

177 32
1

M_A_DQ37 DQ51 VSS

164 37
DY
Layout Note: M_A_DQ32 166
DQ52 VSS
38
M_A_DQ35 DQ53 VSS
Place these caps 174 43
2

M_A_DQ39 DQ54 VSS

close to VTT1 and 176 44
M_A_DQ62 DQ55 VSS
181 48
VTT2. M_A_DQ58 DQ56 VSS
183 49
M_A_DQ60 DQ57 VSS 1D35V_S3
B M_A_DQ61
191
193
DQ58 VSS
54
55
Layout Note: B
M_A_DQ63 DQ59 VSS
180
DQ60 VSS
60 Place these Caps near SO-DIMMA.
M_A_DQ59 182 61
M_A_DQ56 DQ61 VSS
192 65
M_A_DQ57 DQ62 VSS
194 66

D
DQ63 VSS
[5] M_A_DQS#[7:0] 71
M_A_DQS#1 VSS Q1202
10 72
M_A_DQS#3 DQS0# VSS 5V_S5
27 127 2N7002K-2-GP
M_A_DQS#5 DQS1# VSS
45 128
M_A_DQS#6 DQS2# VSS 84.2N702.J31
62 133
M_A_DQS#0 DQS3# VSS 1D35V_S3 2ND = 84.2N702.031
135 134
M_A_DQS#2 DQS4# VSS
152 138

1
M_A_DQS#4 DQS5# VSS
169 139

S
M_A_DQS#7 DQS6# VSS R1208
186 144
DQS7# VSS 220KR2J-L2-GP M_A_B_DIMM_ODT R1206 M_A_DIMA_ODT0
[5] M_A_DQS[7:0] 145 1 2 66D5R2F-GP
M_A_DQS1 VSS
12 150
M_A_DQS3 DQS0 VSS R1207 M_A_DIMA_ODT1
29 151 1 2 66D5R2F-GP

2
M_A_DQS5 DQS1 VSS
47 155
M_A_DQS6 DQS2 VSS
M_A_DQS0
64
DQS3 VSS
156 R1205 84.05067.031 Vth = 1V max.
137 161
M_A_DQS2 DQS4 VSS DDR_PG_CTRL_R DDR_VTT_PG_CTRL
154 162 1 2 S D DDR_VTT_PG_CTRL [49]
M_A_DQS4 DQS5 VSS [4] DDR_PG_CTRL
171 167

1
M_A_DQS7 DQS6 VSS
188 168
DQS7 VSS 0R0402-PAD R1204
172
VSS Q1201
M_A_DIMA_ODT0
M_A_DIMA_ODT1
116
ODT0 VSS
173 Q1201 must use Vth=1V. DMN5L06K-7-GP DY 2MR2-GP
120 178
ODT1 VSS
179

2
VSS
M_VREF_CA_DIMMA 126 184
VREF_CA VSS
1 185
Layout Note: M_VREF_DQ_DIMMA VREF_DQ VSS
189
VSS
All VREF traces should [4] DDR3_DRAMRST#
30
RESET# VSS
190
have width=20mil; 195
VSS
196
spacing=20 mil VSS
0D675V_S0 203 205
1

VTT1 VSS
204 206
C1217 VTT2 VSS
SCD1U16V2KX-3GP
2

DY DDR3-204P-48-GP-U

A 62.10017.P41 A

close to dimm

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

DDR3-SODIMM1
Size Document Number Rev
A2 A00
Janus HSW 40/50/70
Date: Friday, February 07, 2014 Sheet 12 of 104
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
(Reserved)DDR3-SODIMM2
Size Document Number Rev
A3 A00
Janus HSW 40/50/70
Date: Friday, February 07, 2014 Sheet 13 of 104
5 4 3 2 1
 5 4 3 2 1

D D

C
(Blanking) C

B B

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
(Reserved)_SODIMM _SODIMM4
Size Document Number Rev
A4 A00
Janus HSW 40/50/70
Date: Friday, February 07, 2014 Sheet 14 of 104
5 4 3 2 1
 5 4 3 2 1

SSID = CPU PCH strap pin:

Port B Detected

Low = Disable Port B (default)

DDPB_CTRLDATA High = Enable Port B
*
D
* Low = Disable Port C (default) D
DDPC_CTRLDATA High = Enable Port C

The internal pull-down is disabled after PLTRST# deasserts

3D3V_S0

1
2
RN1501
SRN2K2J-1-GP
HSW_ULT_DDR3L 9 OF 19
CPU1I

4
3
[52] L_BKLT_CTRL B8 B9 DDPB_CTRLCLK
EDP_BKLCTL DDPB_CTRLCLK
[24] L_BKLT_EN A9 EDP_BKLEN DDPB_CTRLDATA C9 DDPB_CTRLDATA
C6 eDP SIDEBAND D9
[52] EDP_VDD_EN EDP_VDDEN DDPC_CTRLCLK
DDPC_CTRLDATA D11 DDPC_CTRLDATA 1
TP1502
RN1503 EE Note:
1 4 DGPU_HOLD_RST# [20] PIRQA# U6 If layout is on constraint, please reserve TP for DDPC_CTRLCLK.
DGPU_PW R_EN PIRQB# PIRQA#/GPIO77
2 OPS 3
PIRQC#
P4 PIRQB#/GPIO78 DDPB_AUXN C5 PCH_DPB_AUXN [55]
N4 PIRQC#/GPIO79 DDPC_AUXN B6
C SRN10KJ-5-GP PIRQD# N2 DISPLAY B5 C
TP1501 PCI_PME# PIRQD#/GPIO80 DDPB_AUXP PCH_DPB_AUXP [55]
1 AD4 PME# DDPC_AUXP A6
R1509 1 DGPU_PW ROK R1512 PCIE
UMA 2
100KR2J-1-GP [20,24,62] INT_TP# 1 0R2J-2-GP
2 INT_TP#_GPIO55 U7 GPIO55
[82,83] DGPU_PW R_EN L1 GPIO52
[73] DGPU_HOLD_RST# L3 GPIO54 DDPB_HPD C8 CRT_PCH_HPD [55]
[24,82,83] DGPU_PW ROK R5 GPIO51 DDPC_HPD A8
L4 GPIO53 EDP_HPD D6 EDP_HPD [52]

1
EC1501
DY EC1502 DY

SC1KP50V2KX-1GP

SC1KP50V2KX-1GP
2

2
3D3V_S0
HASW ELL-6-GP-U

RN1505
1 8 PIRQC#
2 7 PIRQD#
3 6 CLK_PCIE_W LAN_REQ3# [18,58]
4 5 PIRQB#

SRN10KJ-6-GP

3D3V_S0
B B
1

R1510
10KR2J-3-GP
Cedar
2

CEDAR/JANUS_ID CEDAR/JANUS_ID [19]

1

R1511
10KR2J-3-GP
Janus
2

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

PCH ( EDP/GPIO/DDI )
Size Document Number Rev
A3 X02
Janus HSW 40/50/70
Date: Friday, February 07, 2014 Sheet 15 of 104
5 4 3 2 1
 5 4 3 2 1

SSID = PCH
CPU1K HSW_ULT_DDR3L 11 OF 19 USB 2.0 Table
Pair Device
[73] CPU_RXN_C_dGPU_TXN0 F10 PERN5_L0 USB2N0 AN8 USB_PN0 [34]
[73] CPU_RXP_C_dGPU_TXP0 E10 PERP5_L0 USB2P0 AM8 USB_PP0 [34]
SCD1U16V2KX-3GP 0 USB3.0 port1
[73] dGPU_RXN_C_CPU_TXN0 C1606 1 2 OPS dGPU_RXN_CPU_TXN0 C23 AR7 USB_PN1 [34]
C1605 1 PETN5_L0 USB2N1
[73] dGPU_RXP_C_CPU_TXP0 2 OPS dGPU_RXP_CPU_TXP0 C22
SCD1U16V2KX-3GP PETP5_L0 USB2P1 AT7 USB_PP1 [34]
D 1 USB2.0 Port2 (Debug Port) D
[73] CPU_RXN_C_dGPU_TXN1 F8 PERN5_L1 USB2N2 AR8 USB_PN2 [63]
[73] CPU_RXP_C_dGPU_TXP1 E8 PERP5_L1 USB2P2 AP8 USB_PP2 [63]
SCD1U16V2KX-3GP 2 USB2.0 Port3 (IOBD)
[73] dGPU_RXN_C_CPU_TXN1 C1608 1 2 dGPU_RXN_CPU_TXN1
OPS dGPU_RXP_CPU_TXP1 B23 AR10 USB_PN3 1 TP1601
C1607 1 PETN5_L1 USB2N3
[73] dGPU_RXP_C_CPU_TXP1 2 OPS A23 PETP5_L1 USB2P3 AT10 USB_PP3 1 TP1602
SCD1U16V2KX-3GP 3 X
[73] CPU_RXN_C_dGPU_TXN2 H10 PERN5_L2 GPU USB2N4 AM15 USB_PN4 [52]
[73] CPU_RXP_C_dGPU_TXP2 G10 PERP5_L2 USB2P4 AL15 USB_PP4 [52]
SCD1U16V2KX-3GP 4 CAMERA
[73] dGPU_RXN_C_CPU_TXN2 C1610 1 2 OPS dGPU_RXN_CPU_TXN2 B21 AM13 USB_PN5 [58]
C1609 1 dGPU_RXP_CPU_TXP2 PETN5_L2 USB2N5
[73] dGPU_RXP_C_CPU_TXP2 2 OPS
SCD1U16V2KX-3GP
C21 PETP5_L2 USB2P5 AN13 USB_PP5 [58]
5 WLAN
[73] CPU_RXN_C_dGPU_TXN3 E6 PERN5_L3 USB2N6 AP11 USB_PN6 [52]
[73] CPU_RXP_C_dGPU_TXP3 F6 PERP5_L3 USB2P6 AN11 USB_PP6 [52]
SCD1U16V2KX-3GP 6 Touch Panel
[73] dGPU_RXN_C_CPU_TXN3 C1612 1 2 OPS dGPU_RXN_CPU_TXN3 B22 AR13 USB_PN7 [63]
C1611 1 PETN5_L3 USB2N7
[73] dGPU_RXP_C_CPU_TXP3 2 OPS dGPU_RXP_CPU_TXP3 A21
SCD1U16V2KX-3GP PETP5_L3 USB2P7 AP13 USB_PP7 [63]
7 Card Reader
[58] PCIE_PRX_W LANTX_N3 G11 PERN3
[58] PCIE_PRX_W LANTX_P3 F11 PERP3 USB3RN1 G20 USB3_PRX_CTX_N0 [34]
SCD1U16V2KX-3GP H20
C1601 1 PCIE_PTX_W LANRX_N3 USB3RP1 USB3_PRX_CTX_P0 [34]
[58] PCIE_PTX_W LANRX_N3_C 2 C29 PETN3 WLAN PCIE USB
[58] PCIE_PTX_W LANRX_P3_C C1602 1 2 PCIE_PTX_W LANRX_P3 B30 C33 USB3_PTX_CRX_N0 [34]
SCD1U16V2KX-3GP PETP3 USB3TN1
USB3TP1 B34 USB3_PTX_CRX_P0 [34]
[30] PCIE_PRX_LANTX_N4 F13 PERN4
[30] PCIE_PRX_LANTX_P4 G13 PERP4 USB3RN2 E18
SCD1U16V2KX-3GP LAN F18
C1603 1 PCIE_PTX_LANRX_N4 USB3RP2
[30] PCIE_PTX_LANRX_N4_C 2 B29 PETN4
C
[30] PCIE_PTX_LANRX_P4_C C1604 1 2 PCIE_PTX_LANRX_P4 A29 B33 C
SCD1U16V2KX-3GP PETP4 USB3TN2
USB3TP2 A33
G17 PERN1/USB3RN3
F17 PERP1/USB3RP3
C30
Layout Note:
PETN1/USB3TN3
C31 PETP1/USB3TP3 USBRBIAS# AJ10 USB_COMP 1 2 1. USB_COMP using 50 ohm single-ended impedance
AJ11 R1602 2. Isolation Spacing :15mil
USBRBIAS 22D6R2F-L1-GP
F15 PERN2/USB3RN4 RSVD#AN10 AN10 3. Total trace length<500mil
G15 PERP2/USB3RP4 RSVD#AM10 AM10

B31 PETN2/USB3TN4
A31 PETP2/USB3TP4
AL3 USB_OC#0_1 USB_OC#0_1 [18,35]
OC0/GPIO40# USB_OC#2_3
OC1/GPIO41# AT1 USB_OC#2_3 [35]
AH2 USB_OC#4_5 USB_OC#4_5 [20]
+V1.05S_AUSB3PLL R1601 OC2/GPIO42# USB_OC#6_7
E15 RSVD#E15 OC3/GPIO43# AV3
3KR2F-GP E13
PCIE_RCOMP RSVD#E13
1 2 A27 PCIE_RCOMP
B27 PCIE_IREF
3D3V_S5_PCH
RN1601
USB_OC#2_3 8 1
HASW ELL-6-GP-U USB_OC#6_7 7 2
6 3
Layout Note: [18] MCP_GPIO73
5 4
[17] PM_SUSW ARN#_R
1. PCIE_RCOMP/ PCIE_IREF trace width=12~15mil
B
2. Isolation Spacing: 12mil B
3. Total trace length<500mil SRN10KJ-6-GP

#515621

PCIE Table
Port Device Share BUS

1 N/A USB3.0_3

2 N/A USB3.0_4

3 WLAN

4 LAN
GPU GPU GPU GPU
5(L0~L3) GPU

6(L3) HDD SATA0

A <Core Design> A

6(L2) ODD SATA1

Wistron Corporation
6(L0~L1) N/A 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
GPU GPU GPU GPU Taipei Hsien 221, Taiwan, R.O.C.

Title

PCH (PCIE/USB)
Size Document Number Rev
A3 A00
Janus HSW 40/50/70
Date: Friday, February 07, 2014 Sheet 16 of 104
5 4 3 2 1
 5 4 3 2 1

SSID = PCH

RN1703
1 4 PM_RSMRST#
D
2 3 PM_PCH_PW ROK PCH strap pin: D

SRN10KJ-5-GP On Die DSW VR Enable R1720 RTC_AUX_S5

R1717 2 1 10KR2J-3-GP SYS_PW ROK 330KR2J-L1-GP
DY DSW ODVREN 1 2
Low = Disable
DSWVRMEN High = Enable (default) 1
DY 2
* R1721
This signal has no integrated pull-up/pull-down. 330KR2J-L1-GP

3D3V_S0

1
R1701
10KR2J-3-GP
CPU1H HSW_ULT_DDR3L 8 OF 19
2

SYSTEM POWER MANAGEMENT R1704

0R2J-2-GP
PM_SUSACK#_R AK2 AW7 DSW ODVREN NON DS3
XDP_DBRESET# SUSACK# DSWVRMEN PCH_DPW ROK PM_RSMRST#
[96] XDP_DBRESET# AC3 SYS_RESET# DPWROK AV5 1 2
[24,96] SYS_PW ROK SYS_PW ROK AG2 AJ5 PCH_W AKE# 1 DY 2 PCIE_W AKE# [24,30]
SYS_PWROK WAKE#
[24,26,36] PCH_PW ROK 1 R1706 2 PM_PCH_PW ROK AY7
PCH_PWROK
R1705
0R0402-PAD 1 R1707 2 MPW ROK AB5 APWROK
0R2J-2-GP R1705: DY for OBFF disable
0R0402-PAD PCI_PLTRST# AG7 V5 PM_CLKRUN# 1 R1709 2 PM_CLKRUN#_EC [24]
C PLTRST# CLKRUN#/GPIO32 PM_SUS_STAT#1 0R0402-PAD C
SUS_STAT#/GPIO61 AG4 TP1702 R1710
AE6 SUS_CLK_PCH 1 2 SUS_CLK [24]
SUSCLK/GPIO62 PM_SLP_S5# 1 0R2J-2-GP
SLP_S5#/GPIO63 AP5
PM_RSMRST# AW6 TP1703
PM_SUSW ARN#_R AV4 RSMRST#
[16] PM_SUSW ARN#_R PM_PW RBTN# SUSWARN#/SUSPWRDNACK#/GPIO30 PM_SLP_S4#
[24,96] PM_PW RBTN# AL7 PWRBTN# SLP_S4# AJ6 PM_SLP_S4# [24,49]
[24,76] AC_PRESENT AC_PRESENT AJ8 AT4 PM_SLP_S3# PM_SLP_S3# [24,36,48,49,51]
BATLOW # ACPRESENT/GPIO31 SLP_S3# PM_SLP_A#
[20] BATLOW # AN4 BATLOW#/GPIO72 SLP_A# AL5 1
1 PCH_SLP_S0# AF3 AP4 PM_SLP_SUS# TP1704 PM_SLP_SUS# [24,38]
TP1706 PCH_SLP_W LAN# AM5 SLP_S0# SLP_SUS# PM_SLP_LAN# 1
1 SLP_WLAN#/GPIO29 SLP_LAN# AJ7
AC_PRESENT TP1705 TP1707

EC1707
1

DY
1 R1713 2 PCI_PLTRST#
SCD1U16V2KX-3GP

[24,30,36,52,58,65,73,96] PLT_RST#
HASW ELL-6-GP-U
2

0R0402-PAD
1

R1715 C1701
100KR2J-1-GP SC220P50V2KX-3GP NON DS3
DY DY
2

R1708
2

PM_SUSW ARN#_R 1 2 PM_SUSACK#_R

3D3V_S5 0R2J-2-GP PCH_DPW ROK R1718 1 0R2J-2-GP
RN1702 DS3 2 KBC_DPW ROK [24]
RN1701 2 3 PM_SUSACK#_R
[24] PM_SUSACK# DS3

2
1 4 MCP_GPIO12 MCP_GPIO12 [20] [24] PM_SUSW ARN# 1 4 PM_SUSW ARN#_R
2 3 AC_PRESENT DS3 R1725
SRN0J-6-GP 100KR2F-L1-GP
B SRN10KJ-5-GP B

1
R1703
1 2 PCH_W AKE#
1KR2J-1-GP
(CRB#514469)
3D3V_S5_PCH 3D3V_S0
R1714
8K2R2F-1-GP
1 PM_SUS_STAT# PM_CLKRUN#
R1724 DY 2
10KR2J-3-GP 3D3V_AUX_S5 R1727
1 2

100KR2J-1-GP
1 2 SUS_CLK_PCH
NON DS3
2

2
XDP_DBRESET# R1726
SYS_PW ROK EC1701
PLT_RST#
10KR2J-3-GP
SC4D7P50V2CN-1GP DY

1
PCH_PW ROK 1KR2J-1-GP
Q1701
1

KBC_DPW ROK R1702

4 3 PM_RSMRST# 1 2 RSMRST#_KBC [24]
R1728
3V_5V_POK# 5 2 3V_5V_POK_C 1 2 3V_5V_POK [45]
NON DS3
1

EC1706
DY
EC1702
DY
EC1703
DY
EC1704
DY
EC1705
DY 6 1
0R2J-2-GP
DS3
SC1KP50V2KX-1GP

SC1KP50V2KX-1GP

SC1KP50V2KX-1GP

SC1KP50V2KX-1GP

SC1KP50V2KX-1GP
2

2N7002KDW -GP R1729 1 PM_SLP_SUS#

2
A 0R2J-2-GP <Core Design> A

84.2N702.A3F
2nd = 84.2N702.E3F Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
3rd = 75.00601.07C Taipei Hsien 221, Taiwan, R.O.C.
4th = 84.DMN66.03F
Title

PCH (PM)
Size Document Number Rev
A3 A00
Janus HSW 40/50/70
Date: Friday, February 07, 2014 Sheet 17 of 104
5 4 3 2 1
 5 4 3 2 1

SSID = PCH
C1801
R1810
XTAL24_IN 1 2 XTAL24_IN_R 2 1

0R0402-PAD
SC15P50V2JN-2-GP

1
D D
X1801

1
XTAL-24MHZ-81-GP
3D3V_S0 R1802
RN1801 1MR2J-1-GP 82.30004.841
1 8 MCP_GPIO76 MCP_GPIO76 [20]

4
2 7 PEG_CLKREQ#
C1802

2
3 6 CLK_PCIE_REQ#
4 5 XTAL24_OUT 2 1
HSW_ULT_DDR3L 6 OF 19
CPU1F
SRN10KJ-6-GP
SC15P50V2JN-2-GP

C43 A25 XTAL24_IN

CLKOUT_PCIE_N0 XTAL24_IN XTAL24_OUT
C42 CLKOUT_PCIE_P0 XTAL24_OUT B25
CLK_PCIE_REQ# U2 +V1.05S_AXCK_LCPLL
PCIECLKRQ0#/GPIO18
RSVD#K21 K21
B41 CLKOUT_PCIE_N1 RSVD#M21 M21
A41 C26 XCLK_BIASREF R1803 1 2 3KR2F-GP
CLK_PCIE_REQ# CLKOUT_PCIE_P1 DIFFCLK_BIASREF RN1803
Y5 PCIECLKRQ1#/GPIO19
C35 MCP_TESTLOW1 4 1
CLOCK TESTLOW_C35 MCP_TESTLOW2 RN1804
[58] CLK_PCIE_WLAN_N3 C41 CLKOUT_PCIE_N2 TESTLOW_C34 C34 3 2
B42 AK8 MCP_TESTLOW3 3 2
[58] CLK_PCIE_WLAN_P3
[15,58] CLK_PCIE_WLAN_REQ3# CLK_PCIE_WLAN_REQ3# AD1
CLKOUT_PCIE_P2
PCIECLKRQ2#/GPIO20
WLAN SIGNALS TESTLOW_AK8
TESTLOW_AL8 AL8 MCP_TESTLOW4 SRN10KJ-5-GP 4 1
SRN10KJ-5-GP
[30] CLK_PCIE_LAN_N4 B38 AN15 CLK_PCI_LPC_R R1804 DEBUG
1 2 0R2J-2-GP CLK_PCI_LPC [65] CLK_PCI_LPC_R R1813 1 2 0R2J-2-GP CLK_DP2VGA [55]
CLKOUT_PCIE_N3 CLKOUT_LPC_0 CLK_PCI_KBC_R R1805
C37 AP15 1 2 33R2J-2-GP CRT_DEBUG
[30] CLK_PCIE_LAN_P4
[20,30] CLK_PCIE_LAN_REQ4# CLK_PCIE_LAN_REQ4# N1
CLKOUT_PCIE_P3
PCIECLKRQ3#/GPIO21
LAN CLKOUT_LPC_1 CLK_PCI_KBC [24]

CLKOUT_ITPXDP# B35 PCIE_CLK_XDP_N [96]

[73] CLK_PCIE_VGA# A39 CLKOUT_PCIE_N4 CLKOUT_ITPXDP_P A35 PCIE_CLK_XDP_P [96]
B39
[73] CLK_PCIE_VGA
[73] PEG_CLKREQ# PEG_CLKREQ# U5
CLKOUT_PCIE_P4
PCIECLKRQ4#/GPIO22
GPU

EC1801
SC10P50V2JN-4GP

EC1802
SC10P50V2JN-4GP
C C
B37 CLKOUT_PCIE_N5

1
A37 CLKOUT_PCIE_P5
CLK_PCIE_REQ# T2 PCIECLKRQ5#/GPIO23 DY DY

2
HASWELL-6-GP-U
3D3V_S5_PCH

RN1807
SML1_CLK 8 1
LPC_AD[3..0] HSW_ULT_DDR3L 7 OF 19
[24,65] LPC_AD[3..0]
Based on the swap report. CPU1G SML1_DATA 7 2
RN1806 SML0_DATA 6 3
LPC_AD2 8 1 LPC_LAD2_PCH LPC_LAD0_PCH AU14 AN2 MCP_GPIO11 SML0_CLK 5 4
LPC_AD1 LPC_LAD1_PCH LPC_LAD1_PCH LAD0 SMBALERT#/GPIO11 SMB_CLK
7 2 AW12 AP2
LPC_AD3 LPC_LAD3_PCH LPC_LAD2_PCH LAD1 SMBCLK SMB_DATA SRN2K2J-4-GP
6 3 AY12
LAD2
LPC
SMBDATA
AH1
LPC_AD0 5 4 LPC_LAD0_PCH LPC_LAD3_PCH AW11 SMBUS AL2 CARD_PWR_EN
LPC_LFRAME#_PCH LAD3 SML0ALERT#/GPIO60 SML0_CLK
AV12 AN1
SRN0J-7-GP-U LFRAME# SML0CLK SML0_DATA RN1809
AK1
R1801 0R0402-PAD SML0DATA MCP_GPIO73 SRN10KJ-6-GP
[24,65] LPC_FRAME# 1 2 AU4 MCP_GPIO73 [16]
SML1ALERT#/PCHHOT#/GPIO73 SML1_CLK CARD_PWR_EN
AU3 SML1_CLK [24,26,76] 8 1
SML1CLK/GPIO75 SML1_DATA
AH3 SML1_DATA [24,26,76] [16,35] USB_OC#0_1 7 2
33R2J-2-GP 1 SML1DATA/GPIO74
[24,25] SPI_CLK_R 2 R1806 PCH_SPI_CLK AA3 [20,24] EC_SCI# 6 3
0R0402-PAD 1 SPI_CLK
[24,25] SPI_CS0#_R 2 R1807 PCH_SPI_CS0# Y7 AF2 TP_CL_CLK 1 TP1801 MCP_GPIO11 5 4
SPI_CS0# CL_CLK TP_CL_DATA1 TP1802
Y4 AD2
SPI_CS1# CL_DATA TP_CL_RST# 1 TP1803
AC2 SPI C-LINK AF4
0R0402-PAD R1808 PCH_SPI_SI SPI_CS2# CL_RST#
[24,25] SPI_SI_R 1 2 AA2
SPI_MOSI SRN2K2J-1-GP
[24,25] SPI_SO_R 0R0402-PAD 1 2 R1809 PCH_SPI_SO AA4
0R0402-PAD R1811 PCH_SPI_DQ2 SPI_MISO SMB_CLK
[25] SPI_WP# 1 2 Y6
SPI_IO2 3 2
0R0402-PAD 1 2 R1812 PCH_SPI_DQ3 AF1 SMB_DATA 4 1
[25] SPI_HOLD# SPI_IO3
B RN1811 B

3D3V_S5 3D3V_S0

HASWELL-6-GP-U
RN1810
2
1

3 2 3D3V_S0
RN1802 4 1
SRN1KJ-7-GP
SRN10KJ-5-GP
2N7002KDW-GP
3
4

SMB_DATA 6 1 PCH_SMBDATA [12,55,62,96]

PCH_SPI_DQ3
84.2N702.A3F 5 2
PCH_SPI_DQ2 2nd = 84.2N702.E3F
3rd = 75.00601.07C 4 3
4th = 84.DMN66.03F
Q1801

PCH_SMBCLK [12,55,62,96]

SMB_CLK

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size
PCH (CLOCK/SMBUS/CL/LPC/SPI)Rev
Document Number
Custom X02
Janus HSW 40/50/70
Date: Friday, February 07, 2014 Sheet 18 of 104
5 4 3 2 1
 5 4 3 2 1

SSID = CPU
RTC_X1

1 2 RTC_X2
R1915 10MR2J-L-GP

X1901

1 4

D
RTC_AUX_S5 D

2
2 3 C1904
C1903 SC15P50V2JN-2-GP
SC15P50V2JN-2-GP

1
XTAL-32D768KHZ-65-GP
PCH strap pin:

1
RTC_AUX_S5 R1903 R1901
Integrated SUS 1V VRM Enable R1913 330KR2J-L1-GP 1MR2J-1-GP 82.30001.841
1 PCH_INTVRMEN
Low = External VRs DY 2

2
INTVRMEN 330KR2J-L1-GP
High = Internal VRs*

2
1
RN1901
CPU1E HSW_ULT_DDR3L 5 OF 19
SRN20KJ-1-GP

RTC_X1 AW5

3
4
RTC_X2 RTCX1
AY5 RTCX2
Q1901 SM_INTRUDER# AU6 J5 SATA3_PRX_HDDTX_N0 [56]
PCH_INTVRMEN AV7 INTRUDER# SATA_RN0/PERN6_L3
[24] RTCRST_ON G INTVRMEN SATA_RP0/PERP6_L3 H5 SATA3_PRX_HDDTX_P0 [56]
HDD1
SRTC_RST# AV6 RTC B15 SATA3_PTX_HDDRX_N0 [56]
SRTCRST# SATA_TN0/PETN6_L3
1

D RTC_RST# AU7 A15 SATA3_PTX_HDDRX_P0 [56]

R1902 RTCRST# SATA_TP0/PETP6_L3

2
10KR2J-3-GP S J8

SC1U10V2KX-1GP
SATA_RN1/PERN6_L2 SATA_PRX_ODDTX_N2 [56]

1
ODD

C1901
G1901 H8 SATA_PRX_ODDTX_P2 [56]
SATA_RP1/PERP6_L2

1
2N7002K-2-GP C1902 A17 SATA_PTX_ODDRX_N2 [56]
2

SATA_TN1/PETN6_L2

GAP-OPEN
84.2N702.J31 SC1U10V2KX-1GP B17 SATA_PTX_ODDRX_P2 [56]

2
C SATA_TP1/PETP6_L2 C
2ND = 84.2N702.031

2
3rd = 84.07002.I31 HDA_BITCLK AW8 J6
HDA_SYNC HDA_BCLK/I2S0_SCLK SATA_RN2/PERN6_L1
AV11 HDA_SYNC/I2S0_SFRM SATA_RP2/PERP6_L1 H6
(#514849) HDA_RST# AU8 B14
HDA_SDIN0 HDA_RST#/I2S_MCLK# AUDIO SATA SATA_TN2/PETN6_L1
[27] HDA_SDIN0 AY10 HDA_SDI0/I2S0_RXD SATA_TP2/PETP6_L1 C15
AU12 HDA_SDI1/I2S1_RXD
HDA_SDOUT AU11 F5
HDA_SDO/I2S0_TXD SATA_RN3/PERN6_L0
Layout: Place at the open door area. TP1902 1TP_HDA_DOCK_EN# AW10 HDA_DOCK_EN#/I2S1_TXD# SATA_RP3/PERP6_L0 E5
AV10 HDA_DOCK_RST#/I2S1_SFRM# SATA_TN3/PETN6_L0 C17
AY8 I2S1_SCLK SATA_TP3/PETP6_L0 D17
[27] HDA_CODEC_BITCLK R1907 1 2 33R2J-2-GP HDA_BITCLK

[27] HDA_CODEC_SYNC R1908 1 2 0R0402-PAD HDA_SYNC V1 EC_SMI# EC_SMI# [24]

SATA0GP/GPIO34 +V1.05S_ASATA3PLL
SATA1GP/GPIO35 U1 SATA_ODD_PRSNT# [56]
R1911 1 2 0R0402-PAD HDA_RST# V6 MCP_GPIO36
PCH strap pin: [27,29] HDA_CODEC_RST# SATA2GP/GPIO36
AC1
SATA3GP/GPIO37 CEDAR/JANUS_ID [15]
TP1901 1 PCH_JTAG_TRST# AU62
PCH_JTAG_TCK PCH_TRST# SATA_IREF
AE62 PCH_TCK SATA_IREF A12 1 R1904 2
Flash Descriptor Security Overide/ [27] HDA_CODEC_SDOUT R1912 1 2 33R2J-2-GP HDA_SDOUT PCH_JTAG_TDI AD61 L11 0R0402-PAD
PCH_JTAG_TDO PCH_TDI RSVD#L11
Intel ME Debug Mode AE61 PCH_TDO RSVD#K10 K10
[24] ME_UNLOCK R1909 1 2 1KR2J-1-GP PCH_JTAG_TMS AD62 JTAG C12 SATA_RCOMP 1 2
PCH_TMS SATA_RCOMP SATA_LED#
Low = Default * AL11 RSVD#AL11 SATALED# U3
HDA_SDOUT AC4 R1906
High = Enable XDP_TCK_JTAGX RSVD#AC4 3KR2F-GP
AE63 JTAGX
The internal pull-down is disabled after AV2 RSVD#AV2
PLTRST# deasserts

B Layout Note: B
HASW ELL-6-GP-U 4mil trace at break-out and 3
1D05S_VCCST 12-15mil trace with <0.2 ohms
and length total <= 500mils.
2
DY 1 PCH_JTAG_TDI
R1916 51R2J-2-GP 3D3V_S0
2 PCH_JTAG_TDO
R1917 DY 1
51R2J-2-GP RN1902
2 PCH_JTAG_TMS SATA_ODD_PRSNT# 1
R1918 DY 1
51R2J-2-GP 2
8
7
2 XDP_TCK_JTAGX EC_SMI#
R1919 DY 1
1KR2J-1-GP MCP_GPIO36
3
4
6
5
Unused SATA[3:0]GP pins must be terminated to either
3.3V rail or GND using 8.2K
to 10K
on the SRN10KJ-6-GP
motherboard. Either pull-up or pull-down is acceptable.
3D3V_S0
R1905
EC1901
1 2 HDA_CODEC_BITCLK SATA_LED# 2 DY 1
PCH_JTAG_TCK
DY R1920
1
DY 2
51R2J-2-GP
SC10P50V2JN-4GP 10KR2J-3-GP

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

PCH (RTC/SATA/HDA/JTAG)
Size Document Number Rev
A3 A00
Janus HSW 40/50/70
Date: Friday, February 07, 2014 Sheet 19 of 104
5 4 3 2 1
 5 4 3 2 1

SSID = CPU 1D05S_VCCST

1
HSW_ULT_DDR3L 10 OF 19
CPU1J R2018
3D3V_S5 1KR2J-1-GP
RN2006
R2027

2
1 4 BATLOW#
BATLOW# [17]
2 3 MCP_GPIO27 [18] MCP_GPIO76 MCP_GPIO76 P1 D60 PCH_THERMTRIP 1 DY 2 0R2J-2-GP H_THERMTRIP# [36]
BMBUSY#/GPIO76 THRMTRIP#
[15,24,62] INT_TP# 1 R2031 2INT_TP#_GPIO8 AU2 V4 H_RCIN#
H_RCIN# [24]
MCP_GPIO12 GPIO8 RCIN#/GPIO82 INT_SERIRQ
SRN10KJ-5-GP [17] MCP_GPIO12 DY
0R2J-2-GP MCP_GPIO15
AM7
LAN_PHY_PWR_CTRL/GPIO12 CPU/ SERIRQ
T4
PCH_OPIRCOMP
INT_SERIRQ [24]
AD6 AW15 1 2
3D3V_S5_PCH GPIO15 MISC PCH_OPI_RCOMP
Y1 AF20
GPIO16 RSVD#AF20 R2003
R2015
[56] SATA_ODD_DA#
[25] RTC_DET#
RTC_DET#
T3
AD5
GPIO17 RSVD#AB21
AB21
49D9R2F-GP Layout Note:
10KR2J-3-GP 1 INT_TP#_GPIO8 MCP_GPIO27 GPIO24
2 AN5
GPIO27
1.Referenced "continuous" VSS plane only.
MCP_GPIO28 AD7
R2010 MCP_GPIO26 GPIO28 2.Avoid routing next to clock pins or noisy
D AN3 D
10KR2J-3-GP GPIO26 signals.
R6
INT_TP#_GPIO46 MCP_GPIO56 GSPI0_CS#/GPIO83
1 2 AG6
GPIO56 GSPI0_CLK/GPIO84
L6 3. Trace width: 12~15mil
HSW MCP_GPIO57 AP1 N6
GPIO57 GSPI0_MISO/GPIO85 SATA_ODD_PWRGT [56]4. Isolation Spacing: 12mil
MCP_GPIO58 AL4 L8 LPSS_GSPI0_MOSI_BBS0_R
WLAN_PLT_RST# GPIO58 GSPI0_MOSI/GPIO86 5. Max length: 500mil
AT5 R7
MCP_GPIO44 GPIO59 GPIO GSPI1_CS#/GPIO87
AK4 L5
GPU_EVENT_MCP# GPIO44 GSPI1_CLK/GPIO88
[76] GPU_EVENT# 1 R2029 2 AB6 N7
BOARD_ID1 GPIO47 GSPI1_MISO/GPIO89
U4 K2 KB_DET# [62]
0R0402-PAD BOARD_ID2 GPIO48 GSPI_MOSI/GPIO90
Y3 J1 KB_LED_BL_DET [62]
BOARD_ID3 GPIO49 UART0_RXD/GPIO91
P3 K3 DBC_EN [52]
HSIOPC GPIO50 UART0_TXD/GPIO92 3D3V_S0
[21] HSIOPC Y2 J2 PANEL_SIZE_ID [52]
MCP_GPIO13 HSIOPC/GPIO71 SERIAL IO UART0_RTS#/GPIO93 RN2002
AT3 G1
MCP_GPIO14 GPIO13 UART0_CTS#/GPIO94 SRN10KJ-6-GP
AH4 K4
GPIO14 UART1_RXD/GPIO0
TP2002 1CAMERA_PWR_EN AM4 G2 H_RCIN# 8 1
R2028 1 GC6_FB_EN_MCP GPIO25 UART1_TXD/GPIO1
[24,75,76,83] GC6_FB_EN 2 0R0402-PAD AG5 J3 [56] SATA_ODD_DA# 7 2
GPIO45 UART1_RST#/GPIO2
[15,24,62] INT_TP# 1 R2030 2INT_TP#_GPIO46 AG3 J4 BLUETOOTH_EN [58]
INT_SERIRQ 6 3
GPIO46 UART1_CTS#/GPIO3 I2C0_SDA KB_DET#
BDW
0R2J-2-GP EC_SWI# I2C0_SDA/GPIO4
F2
I2C0_SCL
5 4
[24] EC_SWI# AM3 F3
EC_SCI# GPIO9 I2C0_SCL/GPIO5 I2C1_SDA
[18,24] EC_SCI# AM2 G4 I2C1_SDA [62]
GPIO10 I2C1_SDA/GPIO6
TP2001 1HDD_DEVSLP P2 F1 I2C1_SCL
I2C1_SCL [62]
DEVSLP0/GPIO33 I2C1_SCL/GPIO7
C4 E3
SDIO_POWER_EN/GPIO70 SDIO_CLK/GPIO64 COLOR_ENGINE TP2003 3D3V_S0
L2 F4 1
DEVSLP1/GPIO38 SDIO_CMD/GPIO65 LPSS_SDIO_D0_CMNHDR
N5 D3
HDA_SPKR DEVSLP2/GPIO39 SDIO_D0/GPIO66 SRN10KJ-5-GP
[27] HDA_SPKR V2 E4
SPKR/GPIO81 SDIO_D1/GPIO67 RN2007
C3
3D3V_S5_PCH SDIO_D2/GPIO68 I2C0_SDA
E2 1 4
SDIO_D3/GPIO69 I2C0_SCL 2 3
2

HASWELL-6-GP-U HSIOPC R2007 1 2

R2013 100KR2J-1-GP
10KR2J-3-GP
3D3V_S0
1

0R0402-PAD-1-GP 1 2 R2001 MCP_GPIO58 RN2008

0R0402-PAD-1-GP 1 2 R2002 MCP_GPIO44 I2C1_SDA 1 DY 4
0R0402-PAD-1-GP 1 2 R2004 MCP_GPIO56 I2C1_SCL 2 3
0R0402-PAD-1-GP 1 2 R2009 MCP_GPIO26
SRN10KJ-5-GP
MCP_R

C 0R0402-PAD-1-GP 1 2 R2016 MCP_GPIO14 C

0R0402-PAD-1-GP 1 2 R2017 MCP_GPIO28

0R0402-PAD-1-GP 1 2 R2020 MCP_GPIO13

0R0402-PAD-1-GP 1 2 R2022 MCP_GPIO57

3D3V_S5_PCH
RN2012
SRN10KJ-6-GP
1 8 EC_SWI#
2 7 USB_OC#4_5 [16]
3 6 RTC_DET#
4 5 WLAN_PLT_RST#
PCH strap pin:
3D3V_S0 NO REBOOT
3D3V_S0
RN2011 1KR2J-1-GP
SRN10KJ-6-GP
* Low = Enable (Default) R2006
1 8 HDA_SPKR 1 2 HDA_SPKR
2 7 PIRQA#
CLK_PCIE_LAN_REQ4#
PIRQA# [15]
[18,30] High = Disable DY
3 6 DBC_EN
4 5 BLUETOOTH_EN The internal pull-down is disabled after
PLTRST# deasserts
3D3V_S0

BIOS strap pin: PCH strap pin:

1

R2023 3D3V_S0
BIOS VRAM Size Strap pin BOARD_ID1 VRAM_2G 10KR2J-3-GP Top-Block Swap Override mode

1
2

1G 0 R2011
BOARD_ID1 SDIO_D0 High = Enable "Top-Block swap" mode DY 1KR2J-1-GP
/ GPIO66 * Low = Disable "Top-Block swap" mode (Default)
2G 1
2
1

B LPSS_SDIO_D0_CMNHDR B
R2024 The internal pull-down is disabled after PLTRST# deasserts
10KR2J-3-GP
VRAM_1G Need SW double confirm if that's needed Top-Block swap
2

PCH strap pin:

3D3V_S5_PCH
3D3V_S0 TLS Confidentiality
1
1

BIOS strap pin: R2005 GPIO15

* Low = Disable Intel ME Crypto TLS (Default) DY R2014
OPS 10KR2J-3-GP
High = Enable Intel ME Crypto TLS 1KR2J-1-GP

BIOS UMA/DIS Strap pin BOARD_ID2

2

The internal pull-down is disabled after MCP_GPIO15

2

RSMRST# deasserts.
UMA 0 BOARD_ID2
1

DIS 1
R2008 PCH strap pin:
10KR2J-3-GP 3D3V_S0
UMA Boot BIOS Strap Bit BBS
2

Boot BIOS * Low = SPI (Default) R2012

Destination High = LPC
DY 1KR2J-1-GP
3D3V_S0
2

The internal pull-down is disabled after PLTRST# deasserts LPSS_GSPI0_MOSI_BBS0_R

1

BIOS strap pin: R2025 Need double confirm, GPIO table set to GPI if that's needed PH or PL
N15S-GT 10KR2J-3-GP
BIOS UMA/DIS Strap pin BOARD_ID3
2

N15V-GM-S(DVC40/50) 0 BOARD_ID3
A A
1

N15S-GT (DVC70) 1
R2026
10KR2J-3-GP
N15V-GM
2

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (GPIO/MISC)
Size Document Number Rev
A2 A00
Janus HSW 40/50/70
Date: Friday, February 07, 2014 Sheet 20 of 104
5 4 3 2 1
 5 4 3 2 1

SSID = CPU
3D3V_S5_PCH

DSW

+3.3A_DSW _PRTCSUS 1 R2102 2

1
0R0603-PAD-1-GP-U Intel Recommend
D
+V1.05DX_MODPHY_PCH C2109 D
HSW_ULT_DDR3L 13 OF 19
CPU1M

2
SC1U10V2KX-1GP
K9 VCCHSIO
1D05V_S0 L10 VCCHSIO RTC_AUX_S5
M9 VCCHSIO
1 R2105 2 +V1.05S_AIDLE N8 HSIO RTC AH11
VCC1_05 VCCSUS3_3
P9 VCC1_05 VCCRTC AG10
0R0402-PAD +V1.05S_AUSB3PLL B18 AE7 +VCCRTCEXT 1 2
VCCUSB3PLL DCPRTC

1
C2105
SC1U10V2KX-1GP
+V1.05S_ASATA3PLL B11 C2110
VCCSATA3PLL SCD1U16V2KX-3GP 3D3V_S5
DY

2
TP2102 1 TP_VCCAPLLOPI_VAL Y20 SPI Y8
RSVD#Y20 VCCSPI
+V1.05S_APLLOPI AA21 VCCAPLL
OPI

1
W21 VCCAPLL
AG14 C2147
VCCASW
AG13 1D05V_S0

2
VCCASW SCD1U16V2KX-3GP
TP2107 1 +V1.05A_VCCUSB3SUS J13 USB3
3D3V_S5_PCH +V3.3A_1.5A_HDA DCPSUS3
VCC1_05 J11 +V1.05S_CORE_PCH Broadwell(#514849): No series resistors (0 ohm).
VCC1_05 H11 Haswell(#486713):Series resistor:5 ohm.
1 R2108 2 +V3.3A_1.5A_HDA AH14 HDA H15
0R0603-PAD-1-GP-U VCCHDA VCC1_05 R2110 C2114
VCC1_05 AE8

SC1U10V2KX-1GP
AF22 5D1R2F-GP SC1U10V2KX-1GP
VCC1_05

C2116
TP2108 1 +V1.05A_USB2SUS AH13 VRM AG19 +PCH_VCCDSW 1 2 PCH_VCCDSW _R 1 2
DCPSUS2 CORE DCPSUSBYP#AG19
AG20 BDW/HSW

2
DCPSUSBYP#AG20
VCCASW AE9 +1.05M_ASW
VCCASW AF9
3D3V_S5 +V3.3A_DSW _P 3D3V_S0 AC9 AG8 C2101
+V3.3A_PSUS VCCSUS3_3 VCCASW
C AA9 VCCSUS3_3
GPIO/LPC
DCPSUS1#AD10 AD10 +V1.05A_SUS_PCH 1 TP2106 +V3.3A_DSW _P 1 2 +PCH_VCCDSW C
1 R2101 2 +V3.3A_DSW _P +V3.3A_DSW _P AH10 VCCDSW3_3 DCPSUS1#AD8 AD8
1 R2112 2 +V3.3S_PCORE V8 VCC3_3
SCD47U6D3V2KX-GP
0R0402-PAD W9 3D3V_S0
VCC3_3
1

1
0R0402-PAD C2123 J15 1D5V_S0 WistronSKB: match Intel design_20130417
C2136 THERMAL SENSOR VCCTS1_5
DY SC10U6D3V3MX-GP VCC3_3 K14
(#489999_2013WW15)
SCD1U16V2KX-3GP K16
2

2
VCC3_3

SC1U10V2KX-1GP
C2128
+V1.05S_AXCK_DCB J18 VCCCLK
1D05V_S0 +V1.05S_SSCF100 K19 SERIAL IO U8 +V3.3S_1.8S_LPSS_SDIO

2
VCCCLK VCCSDIO
+V1.05S_AXCK_LCPLL A20 VCCACLKPLL VCCSDIO T9
1 R2117 2 +V1.05S_SSCF100 +V1.05S_SSCF100 J17 VCCCLK
+V1.05S_SSCFF R21 VCCCLK
C2137

0R0402-PAD T21 LPT LP POWER

VCCCLK
1

SC1U10V2KX-1GP

1 TP_V1.05S_SSCF100 K18 SUS OSCILLATOR AB8 +V1.05A_AOSCSUS 1 TP2109

TP2103 RSVD#K18 DCPSUS4
1 TP_V1.05S_AXCK_DCB M20 RSVD#M20
TP2104 1 TP_V1.05S_SSCFF V21
2

TP2101 RSVD#V21
+V3.3A_PSUS AE20 VCCSUS3_3 RSVD#AC20 AC20 TP_V1.05S_APLLOPI 1 TP2105
AE21 VCCSUS3_3 VCC1_05 AG16 1D05V_S0
USB2 AG17
VCC1_05

SC1U10V2KX-1GP
C2135
2
HASW ELL-6-GP-U

1D05V_S0 +V1.05S_SSCFF

B B
1 R2118 2 +V1.05S_SSCFF
C2138

0R0402-PAD
1

1D05V_S0 1D05V_HSIO
SC1U10V2KX-1GP

R2122
2

1 2
Non-HSIO
0R5J-5-GP
+V3.3S_1.8S_LPSS_SDIO 3D3V_S0
R2123
1 2 HSIOPC_R 1 R2103 2
[20] HSIOPC
DY
0R0402-PAD

1
0R2J-2-GP 1D05V_HSIO
9

U2101 C2104
SC1U10V2KX-1GP
ON

2
5V_S5 1 8 R2114
VDD GND HSIO_OUT
1D05V_S0 2 D#2 S#7 7 1 0R5J-5-GP
2
3 D#3 S#6 6
4 D#4 S#5 5 DY
DY

1
SLG59M1470VTR-GP
74.59147.093 DY C2142
1

SC10U10V5KX-2GP

2
DY C2141
SC4D7U6D3V3KX-GP
A <Core Design> A
2

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (POWER2)
Size Document Number Rev
A3 A00
Janus HSW 40/50/70
Date: Friday, February 07, 2014 Sheet 21 of 104
5 4 3 2 1
 5 4 3 2 1

SSID = PCH

D D

HSW_ULT_DDR3L
CPU1Q 17 OF 19

DC_TEST_AY2_AW2 AY2 A3 DC_TEST_A3_B3

DC_TEST_AY3_AW3 DAISY_CHAIN_NCTF_AY2 DAISY_CHAIN_NCTF_A3 TP_DC_TEST_A4 TP2202
AY3 DAISY_CHAIN_NCTF_AY3 DAISY_CHAIN_NCTF_A4 A4 1
TP2201 1TP_DC_TEST_AY60 AY60 DAISY_CHAIN_NCTF_AY60
DC_TEST_AY61_AW61 AY61 A60 TP_DC_TEST_A60 1 TP2203
DC_TEST_AY62_AW62 DAISY_CHAIN_NCTF_AY61 DAISY_CHAIN_NCTF_A60 DC_TEST_A61_B61
AY62 DAISY_CHAIN_NCTF_AY62 DAISY_CHAIN_NCTF_A61 A61
TP2204 1TP_DC_TEST_B2 B2 DAISY_CHAIN_NCTF_B2 DAISY_CHAIN_NCTF_A62 A62 TP_DC_TEST_A62 1 TP2205
DC_TEST_A3_B3 B3 AV1 TP_DC_TEST_AV1 1 TP2206
DC_TEST_A61_B61 DAISY_CHAIN_NCTF_B3 DAISY_CHAIN_NCTF_AV1 TP_DC_TEST_AW1 TP2207
B61 DAISY_CHAIN_NCTF_B61 DAISY_CHAIN_NCTF_AW1 AW1 1
DC_TEST_B62_B63 B62 AW2 DC_TEST_AY2_AW2
DAISY_CHAIN_NCTF_B62 DAISY_CHAIN_NCTF_AW2 DC_TEST_AY3_AW3
B63 DAISY_CHAIN_NCTF_B63 DAISY_CHAIN_NCTF_AW3 AW3
DC_TEST_C1_C2 C1 AW61 DC_TEST_AY61_AW61
DAISY_CHAIN_NCTF_C1 DAISY_CHAIN_NCTF_AW61 DC_TEST_AY62_AW62
C2 DAISY_CHAIN_NCTF_C2 DAISY_CHAIN_NCTF_AW62 AW62
AW63 TP_DC_TEST_AW63 1 TP2208
C
DAISY_CHAIN_NCTF_AW63 C
HASWELL-6-GP-U

HSW_ULT_DDR3L
CPU1R 18 OF 19

RSVD#N23 N23
RSVD#R23 R23
RSVD#T23 T23
AT2 RSVD#AT2
RSVD#U10 U10
AU44 RSVD#AU44
AV44 RSVD#AV44
D15 RSVD#D15
RSVD#AL1 AL1
RSVD#AM11 AM11
RSVD#AP7 AP7
F22 RSVD#F22
RSVD#AU10 AU10
H22 RSVD#H22
B
RSVD#AU15 AU15 B
J21 RSVD#J21
RSVD#AW14 AW14
RSVD#AY14 AY14

HASWELL-6-GP-U

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (RSVD)
Size Document Number Rev
A4 A00
Janus HSW 40/50/70
Date: Friday, February 07, 2014 Sheet 22 of 104
5 4 3 2 1
 5 4 3 2 1

SSID = PCH

D D

HSW_ULT_DDR3L 14 OF 19 HSW_ULT_DDR3L 15 OF 19
CPU1N CPU1O

A11 VSS VSS AJ35 AP22 VSS VSS AV59

A14 VSS VSS AJ39 AP23 VSS VSS AV8
A18 VSS VSS AJ41 AP26 VSS VSS AW16
A24 VSS VSS AJ43 AP29 VSS VSS AW24
A28 VSS VSS AJ45 AP3 VSS VSS AW33
A32 VSS VSS AJ47 AP31 VSS VSS AW35
A36 VSS VSS AJ50 AP38 VSS VSS AW37
A40 VSS VSS AJ52 AP39 VSS VSS AW4
A44 VSS VSS AJ54 AP48 VSS VSS AW40
A48 VSS VSS AJ56 AP52 VSS VSS AW42
A52 VSS VSS AJ58 AP54 VSS VSS AW44
A56 VSS VSS AJ60 AP57 VSS VSS AW47
AA1 VSS VSS AJ63 AR11 VSS VSS AW50
AA58 VSS VSS AK23 AR15 VSS VSS AW51
AB10 VSS VSS AK3 AR17 VSS VSS AW59
AB20 VSS VSS AK52 AR23 VSS VSS AW60
AB22 VSS VSS AL10 AR31 VSS VSS AY11
AB7 VSS VSS AL13 AR33 VSS VSS AY16
AC61 VSS VSS AL17 AR39 VSS VSS AY18
AD21 VSS VSS AL20 AR43 VSS VSS AY22
AD3 VSS VSS AL22 AR49 VSS VSS AY24
AD63 VSS VSS AL23 AR5 VSS VSS AY26
AE10 VSS VSS AL26 AR52 VSS VSS AY30
C AE5 AL29 AT13 AY33 C
VSS VSS VSS VSS
AE58 VSS VSS AL31 AT35 VSS VSS AY4
AF11 VSS VSS AL33 AT37 VSS VSS AY51
AF12 VSS VSS AL36 AT40 VSS VSS AY53
AF14 VSS VSS AL39 AT42 VSS VSS AY57
AF15 VSS VSS AL40 AT43 VSS VSS AY59
AF17 VSS VSS AL45 AT46 VSS VSS AY6
AF18 VSS VSS AL46 AT49 VSS VSS B20
AG1 VSS VSS AL51 AT61 VSS VSS B24
AG11 VSS VSS AL52 AT62 VSS VSS B26
AG21 VSS VSS AL54 AT63 VSS VSS B28
AG23 VSS VSS AL57 AU1 VSS VSS B32
AG60 VSS VSS AL60 AU16 VSS VSS B36
AG61 VSS VSS AL61 AU18 VSS VSS B4
AG62 VSS VSS AM1 AU20 VSS VSS B40
AG63 VSS VSS AM17 AU22 VSS VSS B44
AH17 VSS VSS AM23 AU24 VSS VSS B48
AH19 VSS VSS AM31 AU26 VSS VSS B52
AH20 VSS VSS AM52 AU28 VSS VSS B56
AH22 VSS VSS AN17 AU30 VSS VSS B60
AH24 VSS VSS AN23 AU33 VSS VSS C11
AH28 VSS VSS AN31 AU51 VSS VSS C14
AH30 VSS VSS AN32 AU53 VSS VSS C18
AH32 VSS VSS AN35 AU55 VSS VSS C20
AH34 VSS VSS AN36 AU57 VSS VSS C25
AH36 VSS VSS AN39 AU59 VSS VSS C27
AH38 VSS VSS AN40 AV14 VSS VSS C38
AH40 VSS VSS AN42 AV16 VSS VSS C39
AH42 VSS VSS AN43 AV20 VSS VSS C57
B B
AH44 VSS VSS AN45 AV24 VSS VSS D12
AH49 VSS VSS AN46 AV28 VSS VSS D14
AH51 VSS VSS AN48 AV33 VSS VSS D18
AH53 VSS VSS AN49 AV34 VSS VSS D2
AH55 VSS VSS AN51 AV36 VSS VSS D21
AH57 VSS VSS AN52 AV39 VSS VSS D23
AJ13 VSS VSS AN60 AV41 VSS VSS D25
AJ14 VSS VSS AN63 AV43 VSS VSS D26
AJ23 VSS VSS AN7 AV46 VSS VSS D27
AJ25 VSS VSS AP10 AV49 VSS VSS D29
AJ27 VSS VSS AP17 AV51 VSS VSS D30
AJ29 VSS VSS AP20 AV55 VSS VSS D31

HASW ELL-6-GP-U

HASW ELL-6-GP-U

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU(VSS)
Size Document Number Rev
A3 A00
Janus HSW 40/50/70
Date: Friday, February 07, 2014 Sheet 23 of 104
5 4 3 2 1
 5 4 3 2 1

SSID = KBC VBAT 3D3V_AUX_KBC

VBAT MODEL_ID_DET(GPIO07) PULL-LOW RESISTOR PULL-HIGH RESISTOR VOLTAGE
VBAT PCB VERSION A/D(PIN98) PULL-LOW RESISTOR PULL-HIGH RESISTOR VOLTAGE
Janus-OPS 100.0K 10.0K(64.10025.6DL) 3.0V
X00 100.0K 10.0K 3.0V Janus-UMA 100.0K 13.7K(64.13725.6DL) 2.902V

1
VBAT 1 R2402 2 R2446 R2445 R2405 TBD 100.0K 17.8K(64.17825.6DL) 2.801V

1
A00 X01 100.0K 20.0K 2.75V 64K9R2F-1-GP 57K6R2F-GP 10KR2F-2-GP TBD 100.0K 22.1K(64.22125.6DL) 2.702V

2
0R0603-PAD-1-GP-U R2404 TBD 100.0K 27.0K(64.27025.6DL) 2.598V
R2403 64K9R2F-1-GP X02 100.0K 33.0K 2.48V Cedar_UMA Cedar_OPSJanus_OPS TBD 100.0K 32.4K(64.32425.6DL) 2.492V
2D2R3-1-U-GP TBD 100.0K 37.4K(64.37425.6DL) 2.402V

2
X03 100.0K 47.0K 2.24V TBD 100.0K 43.2K(64.43225.6DL) 2.304V

2
3D3V_AUX_KBC_VCC TBD 100.0K 49.9K(64.49925.6DL) 2.201V

1
PCB_VER_AD A00 100.0K 64.9K 2.0V MODEL_ID_DET Cedar-OPS 100.0K 57.6K(64.57625.6DL) 2.093V
CedarUMA 100.0K 64.9K(64.64925.6DL) 2.001V

1
Reserved 100.0K 76.8 1.87V TBD 100.0K 73.2K(64.73225.6DL) 1.905V

2
C2402 R2406 R2407 TBD 100.0K 82.5K(64.82525.6DL) 1.808V

2
D 1D05V_S0 100KR2F-L1-GP Reserved 100.0K 100.0K 1.65V C2403 100KR2F-L1-GP TBD 100.0K 93.1K(64.93125.6DL) 1.709V D

SC2D2U10V3KX-1GP
C2405

SCD1U16V2KX-3GP C2406

SCD1U16V2KX-3GP C2407

SCD1U16V2KX-3GP C2408

SCD1U16V2KX-3GP C2409

SCD1U16V2KX-3GP C2410

C2411
DY TBD 100.0K 107K(64.10735.6DL) 1.594V

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

1
1

1
1 R2401 2 EC_VTT DY DY Reserved 100.0K 143.0K 1.358V TBD 100.0K 120K(64.12035.6DL) 1.499V
DY

2
C2404 TBD 100.0K 137K(64.13735.6DL) 1.392V
DY

1
0R0402-PAD Reserved 100.0K 174.0K 1.204V TBD 100.0K 154K(64.15435.6DL) 1.299V

SCD1U16V2KX-3GP

2
C2401 TBD 100.0K 200K(64.20035.6DL) 1.099V

SC2D2U10V3KX-1GP
Reserved 100.0K 215.0K 1.048V EC_AGND TBD 100.0K 232K(64.23236.6DL) 0.994V

SCD1U16V2KX-3GP
2
EC_AGND

Layout Note:
Need very close to EC
EC_AGND

ECSCI#_KBC 0R0402-PAD-1-GP 1 2 R2408 EC_SCI# [18,20]

KBC24
ECSMI#_KBC 0R0402-PAD-1-GP 1 2 R2409 EC_SMI# [19]
KROW[0..7] [62]
19 54 KROW0
VCC KBSIN0/GPIOA0/N2TCK KROW1 ECSWI#_KBC 0R0402-PAD-1-GP
46 55 1 2 R2410 EC_SWI# [20]
VCC KBSIN1/GPIOA1/N2TMS KROW2
76 56
3D3V_S0 VCC KBSIN2/GPIOA2 KROW3
88 57
VCC KBSIN3/GPIOA3 KROW4
115 58
VCC KBSIN4/GPIOA4 KROW5
59
KBSIN5/GPIOA5 KROW6
102 60
AVCC KBSIN6/GPIOA6
SCD1U16V2KX-3GP C2412

61 KROW7
KBSIN7/GPIOA7
4 KCOL[0..16] [62]
VDD
1

[44] AD_IA EC_VTT 12 53 KCOL0

C2413 VTT KBSOUT0/GPOB0/SOUT_CR/JENK# KCOL1
DY SC2D2U10V3KX-1GP C2414 KBSOUT1/GPIOB1/TCK
52
51 KCOL2
2

KBSOUT2/GPIOB2/TMS
EC_AGND 1 2 SCD1U16V2KX-3GP 97 50 KCOL3
PCB_VER_AD GPIO90/AD0 KBSOUT3/GPIOB3/TDI KCOL4
98 49
GPIO91/AD1 KBSOUT4/GPOB4 KCOL5 3D3V_AUX_KBC
[42] PSID_EC 99 48
GPIO92/AD2 KBSOUT5/GPIOB5/TDO KCOL6
[17,26,36] PCH_PWROK 100 47
GPIO93/AD3 KBSOUT6/GPIOB6/RDY# KCOL7 3D3V_AUX_KBC
[17,38] PM_SLP_SUS# 108 43
GPIO05/AD4 KBSOUT7/GPIOB7 KCOL8
[44] BOOST_MON 96 42 RN2401
GPIO04/AD5 KBSOUT8/GPIOC0

2
[76] OVER_CURRENT_P8# 95 41 KCOL9
MODEL_ID_DET GPIO03/EXT_PURST#/AD6KBSOUT9/GPOC1/SDP_VIS# KCOL10 R2452 BAT_SCL
ALL_SYS_PWRGD assert, 94
GPIO07/AD7/VD_IN2 KBSOUT10/P80_CLK/GPIOC2
40 3 2
39 KCOL11 1KR2J-1-GP BAT_SDA 4 1
delay 10ms; PCH_PWROK assert. KBSOUT11/P80_DAT/GPIOC3
38 KCOL12
KBSOUT12/GPO64/TEST# KCOL13 SRN4K7J-8-GP
[26] FAN1_DAC_1 101 37

1
GPIO94/DA0 KBSOUT13/GP(I)O63/TRIST# KCOL14
[44] AD_IA_HW 105 36
GPIO95/DA1 KBSOUT14/GP(I)O62/XORTR#
[20,75,76,83] GC6_FB_EN 1 R2451 2 GC6_FB_EN_KBC 106 35 KCOL15
0R2J-2-GP GPIO96/DA2 KBSOUT15/GPIO61/XOR_OUT KCOL16 ECRST# R2418 1
[7,46] IMVP_PWRGD 107 34 2 10KR2J-3-GP
GPIO97/DA3 GPIO60/KBSOUT16/DSR1#
33 TP_ON# [62]
DY GPIO57/KBSOUT17/DCD1#
BAT_SCL 70 LPC_AD[3..0] [18,65]
[43,44] BAT_SCL GPIO17/SCL1/N2TCK
BAT_SDA 69 126 LPC_AD0
[43,44] BAT_SDA GPIO22/SDA1/N2TMS LAD0/GPIOF1
67 127 LPC_AD1
[18,26,76] SML1_CLK GPIO73/SCL2/N2TCK LAD1/GPIOF2
68 128 LPC_AD2
[18,26,76] SML1_DATA GPIO74/SDA2/N2TMS LAD2/GPIOF3 3D3V_AUX_KBC
[52] LCD_TST 1 R2417 2 [30] PM_LAN_ENABLE 119 1 LPC_AD3
GPIO23/SCL3/N2TCK LAD3/GPIOF4
[19] RTCRST_ON 120 2 CLK_PCI_KBC [18] R2416
0R0402-PAD PROCHOT_EC GPIO31/SDA3/N2TMS LCLK/GPIOF5 AC_IN# R2413 1 2 100KR2J-1-GP
[52] LCD_TST_EN LCD_TST_EN
24
28
GPIO47/SCL4A/N2TCK LFRAME#/GPIOF6
3
7 PLT_RST#_EC
LPC_FRAME# [18,65]
1 2 PLT_RST# [17,30,36,52,58,65,73,96] BAT_IN# R2414 1 DY 2 10KR2J-3-GP
GPIO53/SDA4A/N2TMS LRESET#/GPIOF7
[62] TP_LID_CLOSE# 1 R2450 2 TP_LID_CLOSE#_KBC 26
0R2J-2-GP ECSWI#_KBC GPIO51/TA3/N2TCK AC_IN_KBC# R2426 1
123 2100KR2J-1-GP
GPIO67/SOUT1/N2TMS

2
EC_SPI_CS#_C 0R0402-PAD
DY 90 2 R2419 1 33R2J-2-GP SPI_CS0#_R [18,25]
C GPIOC6/F_CS0# EC_SPI_CLK_C C
92 2 R2420 1 33R2J-2-GP SPI_CLK_R [18,25] DY C2415
GPIOC7/F_SCK
[62] TPCLK 72 109 SC220P50V2KX-3GP

1
GPIO37/PSCLK1 GPIO30/F_WP#/RTS1# CAP_LED# [62]
[62] TPDATA 71 80 BAT_IN# BAT_IN# [42,43,44]
GPIO35/PSDAT1 GPIO41/F_WP#/PSL_GPIO41 EC_SPI_DI_C 3D3V_S0
[36] ALL_SYS_PWRGD 10 87 2 R2422 1 33R2J-2-GP SPI_SI_R [18,25]
GPIO26/PSCLK2 GPIOC5/F_SDIO/F_SDIO0 EC_SPI_DO_C
[42] PWR_CHG_AD_OFF 11 86 2 R2423 1 33R2J-2-GP SPI_SO_R [18,25]
GPIO27/PSDAT2 GPIOC4/F_SDI/F_SDIO1
[44] AD_IA_HW2 25 91 PM_SUSACK# [17]
GPIO50/PSCLK3 GPIO81/F_WP#/F_SDIO2 SUSCLK_KBC
[52] BLON_OUT 27 77 1 R2441 2 SUS_CLK [17]
FAN_TACH1 R2415 1 2 10KR2J-3-GP
GPIO52/PSDAT3 GPIO00/32KCLKIN/F_SDIO3

Power Switch Logic(PSL)

0R0402-PAD 3D3V_AUX_S5 TOUCH_PANEL_INTR# R2443 1 2 10KR2J-3-GP
31 73 PSL_IN1# DY
R2437
[26] FAN_TACH1
[17,96] PM_PWRBTN# 117
GPIO56/TA1 PSL_IN1#/GPI70
93 PSL_IN2# Layout Note: Touch Panel PH internally.
GPIO20/TA2/IOX_DIN_DIO
PSL_IN2#/GPI06/EXT_PURST#

2
[15,82,83] DGPU_PWROK 1 OPS 2 DGPU_PWROK_KBC 63 74 PSL_OUT# Need very close to EC
GPIO14/TB1 PSL_OUT#/GPIO71 R2425
[17,36,48,49,51] PM_SLP_S3# 64
0R2J-2-GP GPIO01/TB2
330KR2J-L1-GP
29 ECSCI#_KBC 3D3V_S5
ECSCI#/GPIO54 ECRST#
[52] EC_BRIGHTNESS 32 85

1
GPIO15/A_PWM EXT_RST#
[27] KBC_BEEP 118 122 H_RCIN# [20] [61] KBC_PWRBTN# 1 R2427 2 PSL_IN2#
GPIO21/B_PWM KBRST#/GPIO86
[61] BATT_WHITE_LED# 62
65
GPIO13/C_PWM
75 C2416 0R0402-PAD
LID_CLOSE# R2421 1 DY 2100KR2J-1-GP
[42] AC_IN_KBC# GPIO32/D_PWM VSBY 3D3V_AUX_S5
[62] KB_BL_CTRL 22
16
GPIO45/E_PWM/DTR1#_BOUT1 VBKUP
114
44
EC_VBKUP
KBC_VCORF
1 R2428 2
0R0402-PAD
RTC_AUX_S5
1 2
SC1U10V2KX-1GP USB_PWR_EN# R2412 1 DY 2100KR2J-1-GP
[61] CHG_AMBER_LED# GPIO40/F_PWM/1_WIRE/RI1# VCORF
[17] KBC_DPWROK 81 13 PECI 1 2 [44] AC_IN# 1 R2430 2 PSL_IN1#
GPIO66/G_PWM/PSL_GPIO66 PECI H_PECI [4]
1 R2449 2 VD1_EN# 66 125 INT_SERIRQ [20] R2429
GPO33/H_PWM/VD1_EN# SERIRQ/GPIOF0

C2422
SC100P50V2JN-3GP
1KR2J-1-GP 6 ECSMI#_KBC 43R2J-GP 0R0402-PAD
GPIO24

1
[26] VD_IN1 104 15 RSMRST#_KBC [17]
GPIO80/VD_IN1 GPIO36/TB3/CTS1#
DY
[26] VD_OUT1# 110 21 PM_SLP_S4# [17,49]

2
GPIO82/IOX_LDSH/VD_OUT1 GPIO44/SCL4B
[17,76] AC_PRESENT 112 20 BOOST_MODE# [44]
GPIO84/IOX_SCLK/VD_OUT2 PSL_IN4#/GPI43
ALL_SYS_PWRGD de-assert, PSL_IN3#/GPI42
17 LID_CLOSE# [64]
23 ME_UNLOCK [19]
delay 100ms; SYS_PWROK assert. 84
GPIO46/SDA4B/CIRRXM
[17,96] SYS_PWROK
[35] USB_PWR_EN# 83
GPIO77/SPI_MISO
113 PCIE_WAKE# [17,30]
Layout Note:
GPIO76/SPI_MOSI GPIO87/CIRRXM/SIN_CR
LVDS backlight Control from PS8625 [58] WIFI_RF_EN 82
GPIO75/SPI_SCK GPIO34/SIN1/CIRRXL
14 S5_ENABLE [36] Need very close to EC 3D3V_AUX_S5 3D3V_AUX_S5
[17] PM_SUSWARN# 79
R2411 GPIO02/SPI_CS#

2
1 DY 2 0R2J-2-GP 5
[52] TOUCH_PANEL_INTR# TOUCH_PANEL_INTR_KBC# GND R2431 C2417
124 18 1 2 SCD1U16V2KX-3GP
GPIO10/LPCPD# GND
[15,20,62] INT_TP# 1 R2448 2 0R2J-2-GP INT_TP#_KBC 121 45 330KR2J-L1-GP
GPIO85/GA20 GND
[58] E51_TxD 111 78
L_BKLT_EN_EC GPIO83/SOUT_CR GND
9 89 D2401

S
3D3V_AUX_KBC GPIO65/SMI# GND R2432
116
GND

2
R2453 [17] PM_CLKRUN#_EC 8 LID_CLOSE# K A TOUCH_PANEL_INTR# [52] PSL_OUT# 1 2 KBC_ON#_GATE_L 1 2 KBC_ON#_GATE G
GPIO11/CLKRUN# EC_AGND
G
R2434
2 DY 1 [27] AMP_MUTE# 30
GPIO55/CLKOUT/IOX_DIN_DIO AGND
103
R2433 DY 0R2J-2-GP
1

10KR2J-3-GP 1KR2J-1-GP 20KR2F-L-GP Q2402 D

NPCE285PA0DX-GP
RB751V-40-H-GP 83.R2004.H8F DMP2130L-7-GP

1
0R0402-PAD
R2444 84.02130.031
R2435
071.00285.000G 2ND = 84.03413.A31
[15] L_BKLT_EN 1 2 L_BKLT_EN_EC D2402
2

0R0402-PAD 3D3V_AUX_KBC 3D3V_AUX_KBC

eDP backlight Control from PCH K A TP_LID_CLOSE# [62]
DY
1

1
R2447 RB751V-40-H-GP 83.R2004.H8F R2436
100KR2J-1-GP 10KR2J-3-GP
Q2403
EC_AGND G
Layout Note:
2

2
B S5_ENABLE B
D
EC_GPIO47 High Active Connect GND and AGND planes via either
0R resistor or connect directly. S
3D3V_AUX_S5
R2424 2N7002K-2-GP
R2438 0R2J-2-GP 84.2N702.J31
1

0R2J-2-GP ECRST# 2ND = 84.2N702.031

R2439
1
DY 2
3rd = 84.07002.I31
1
DY 2
10KR2J-3-GP 4th = 84.2N702.W31
Q2401 C2418
2

SC1U10V2KX-1GP
PROCHOT_EC G

E
H_PROCHOT#_EC
DY
D 1 R2440 2 H_PROCHOT# [4,42,44,46] [26,36,76] PURE_HW_SHUTDOWN# B

2
1

Q2404
R2442 S 0R0402-PAD LMBT3906LT1G-1-GP
C
1

100KR2J-1-GP C2421
DY 2N7002K-2-GP SC47P50V2JN-3GP
84.2N702.J31
DY
2

2ND = 84.2N702.031
3rd = 84.07002.I31
4th = 84.2N702.W31

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

KBC Nuvoton NPCE885

Size Document Number Rev
A1
Janus HSW 40/50/70 A00
Date: Friday, February 07, 2014 Sheet 24 of 104
5 4 3 2 1
 5 4 3 2 1

SSID = Flash.ROM

SPI Flash ROM(8M) for PCH 3D3V_S5 3D3V_S5

1
D C2501 D
SC10U10V5KX-2GPDY C2502

4
3
SCD1U16V2KX-3GP

2
R2501 RN2501
4K7R2J-2-GP
DY SRN4K7J-8-GP Single SPI shared flash connection (SPI Quad I/O mode)

1
2
SPI25 3D3V_S5

[18,24] SPI_CS0#_R 1 CS# VCC 8

[18,24] SPI_SO_R 2 DO/IO1 HOLD#/IO3 7 SPI_HOLD# [18]
[18] SPI_W P# 3 WP#/IO2 CLK 6 SPI_CLK_R [18,24]
4 GND DI/IO0 5 SPI_SI_R [18,24]
1

1
W 25Q64FVSSIQ-GP
EC2502 DY 72.25Q64.K01 EC2501 EC2503
SC4D7P50V2CN-1GP SC4D7P50V2CN-1GP DY DY SC10P50V2JN-4GP
2

2
C C
3D3V_S5
SKT25
Source QUAD/DUAL fast read DUAL fast read
SPI_CS0#_R 1 8
SPI_SO_R 2 DY 7 SPI_HOLD#
SPI_W P# 3 6 SPI_CLK_R 72.25Q64.K01 O O
4 5 SPI_SI_R

SKT-G6179HT0321-001-GP 72.25647.00A O O
62.10089.011 Refer to "NCPE985x/ NPCE995x board design reference guide"
072.25B64.0001
O O

SSID = RBATT
+RTC_VCC 3D3V_AUX_S5 RTC_AUX_S5

B AFTP2502 B
1 +RTC_VCC
D2501
1

RTC1 R2502 3
1KR2J-1-GP
1 2 1 RTC_PW R 2
PWR

1
2 C2503
GND
NP1 NP1 BAS40C-2-GP DY SCD47U6D3V2KX-GP
NP2 NP2 2
75.00040.07D

BAT-060003HA002M213ZL-GP-U1 AFTP2501
2nd = 75.00040.C7D
1
62.70014.001 3rd = 75.00040.A7D
2nd = 62.70001.061
3rd = 20.F2316.002

Q2505
A G <Core Design> A
1

D RTC_DET# [20]
R2504
10MR2J-L-GP S Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
2N7002K-2-GP Taipei Hsien 221, Taiwan, R.O.C.
2

84.2N702.J31
2ND = 84.2N702.031 Title
3rd = 84.07002.I31
4th = 84.2N702.W31 Flash/RTC
Size Document Number Rev
A3 A00
Janus HSW 40/50/70
Date: Friday, February 07, 2014 Sheet 25 of 104
5 4 3 2 1
 5 4 3 2 1

SSID = Thermal

Fan controller1
5V_S0
R2605 FAN261
0R2J-2-GP
3D3V_S0 3D3V_S0 1 FON#
D 2
DY 1 8 D

SC4D7U6D3V3KX-GP
FON# GND

C2611
5V_S0 2 VIN GND 7
FAN_VCC1 3 6

SCD1U16V2KX-3GP
VOUT GND

1
C2605
[24] FAN1_DAC_1 4 VSET GND 5

1
2

2
RN2602 AP2113MTR-G1-GP
T8 SRN2K2J-1-GP
74.02113.0E1
3D3V_S0 2N7002KDW -GP
Layout Note:

4
3
Need 10 mil trace width.
6 1 THM_SML1_DATA
[18,24,76] SML1_DATA
C2601

84.2N702.A3F 5 2 FAN1
SC10U6D3V3MX-GP

2nd = 84.2N702.E3F DY 5
1

3rd = 75.00601.07C 4 3 [24] FAN_TACH1 1 R2606 2 FAN_TACH1_C 3

DY T8 C2602 4th = 84.DMN66.03F
0R0402-PAD
2
SCD1U16V2KX-3GP Q2601
2

FAN_VCC1 1
THM_SML1_CLK 4

C2603
D2601

SC2200P50V2KX-2GP
K
ETY-CON3-8-GP

RB551V30-GP
1

1
C2604 20.F1841.003
[18,24,76] SML1_CLK Layout Note: SC4D7U6D3V3KX-GP DY 2nd = 20.F1295.003
Signal Routing Guideline: DY
DY

2
84.T3904.H11 Trace width = 15mil AFTP2803 1

A
NCT7718_DXP
C Q2603 THM26 C
LMBT3904LT1G-GP

83.R5003.H8H
C

1 8 THM_SML1_CLK
C2606 C2607 VDD SCL THM_SML1_DATA
T8 B
DY SC470P50V3JN-2GP
T8 SC2200P50V2KX-2GP
2 D+ SDA 7
ALERT#
3 T8 ALERT# 6
2

T_CRIT# D-
4 5

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
E

T_CRIT# GND

1
C2608

C2609
NCT7718_DXN

NCT7718W -GP
DY DY
2.System Sensor, Put on palm rest

2
74.07718.0B9
1

AFTP2802 1FAN_TACH1_C
R2601 FAN_TACH1 AFTP2801 1FAN_VCC1
DY 0R2J-2-GP Q2602
FAN_VCC1
Layout Note: [17,24,36] PCH_PW ROK G
2

C2812 close U2801 EC2602 EC2601

1
D
PURE_HW _SHUTDOW N# [24,36,76] DY
DY

SCD1U16V2KX-3GP
SC10P50V2JN-4GP
THERM_SYS_SHDN# S PURE_KBCT8

2
T8

SCD1U16V2KX-3GP
1

C2610
1 2 VD_OUT1#
Layout Note: 2N7002K-2-GP
DY R2612 0R2J-2-GP
Both DXN and DXP routing 10 mil trace width and 10 mil spacing. 84.2N702.J31

2
2ND = 84.2N702.031
3rd = 84.07002.I31
4th = 84.2N702.W31
3D3V_S0
B B

R2603 1 T8 2 18K7R2F-GP ALERT#

R2604 2 2KR2F-3-GP T_CRIT# 3D3V_AUX_KBC

1 T8
R2607 1 2 2KR2F-3-GP
R2602 T8
THERM_SYS_SHDN# 1 T8 2 VD_OUT1# [24]

0R2J-2-GP
Close to KBC
Close to Thermal sensor VD_IN1 for system thermal sensor
3D3V_AUX_S5 3D3V_AUX_KBC
24K9R2F-L-GP

24K9R2F-L-GP
1

1
R2609

R2608

DY
2

VD_IN1 [24]
A <Core Design> A
1

C2612
1

R2610 SCD1U16V2KX-3GP
NTC-100K-8-GP C2613 Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
2

SC100P50V2JN-3GP Taipei Hsien 221, Taiwan, R.O.C.

2

VD_IN1_C 1 R2611 2 Title

0R0402-PAD
THERMAL NCT7718W/Fan
Size Document Number Rev
A3
Janus HSW 40/50/70 A00
Date: Friday, February 07, 2014 Sheet 26 of 104
5 4 3 2 1
 5 4 3 2 1

SSID = AUDIO www.vinafix.vn

D D

[29] LINE1_VREFO_R MIC2_VREFO [29]

[29] LINE1_VREFO_L AUD_AGND

Reserved for ALC3234
moat

SC2D2U6D3V2MX-GP

SC4D7U6D3V3KX-GP
[29] AUD_HP1_JACK_L
3D3V_S0 25mA +3V_AVDD EC2707 1 2 DY SC1KP50V2KX-1GP

1
[29] AUD_HP1_JACK_R EC2706 SC1KP50V2KX-1GP
1 2 DY

1 C2705
1 R2701 2 R2711 EC2705 1 2 SCD1U25V2KX-GP
SC1U10V2KX-1GP EC2704 1 2 DY SC1KP50V2KX-1GP
100KR2J-1-GP moat

C2702
0R0402-PAD C2704 EC2703 1 2 SCD1U25V2KX-GP

1
1 2

2
1
C2701
SC4D7U6D3V3KX-GP +5V_AVDD 5V_S0

2
Close pin36 AUD_AGND

2
R2703

1
1.5A
C2703 +3V_AVDD

AUD_VREF
1 2

LDO1_CAP
+5V_AVDD

CPVEE
SC1U10V2KX-1GP

CBN
5V_S0 +5V_PVDD C2710 0R0603-PAD-1-GP-U
AUD_AGND

1
C2711 1 2 R2706
R2702
Layout Note:

SCD1U16V2KX-3GP

SC4D7U6D3V3KX-GP
1 2 0R0805-PAD-1-GP-U

2
Place close to Pin 26

36

35

34

33

32

31

30

29

28

27

26

25
0R0805-PAD-1-GP-U C2706 C2707 C2708 C2709 HDA27
1

1
SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

CPVEE

HPOUT-L/PORT-I-L

LINE1-VREFO-L

MIC2-VREFO

LDO1-CAP

AVDD1

AVSS1
CPVDD

CBN

HPOUT-R/PORT-I-R

LINE1-VREFO-R

VREF
SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP
1 R2704 2
2

2
0R0805-PAD-1-GP-U
CBP 37 24 AUD_AGND AUD_AGND Layout Note:
CBP LINE2_L/PORT-E-L
Tied at point only under
AUD_AGND 38 23 Codec or near the Codec
AVSS2 LINE2_R/PORT-E-R
C2712 1 2 SC10U6D3V3MX-GP LDO2_CAP 39 22
AUD_AGND LDO2-CAP LINE1_L/PORT-C-L LINE1_L [29] 3D3V_S5
40 21
Layout Note: Layout Note: +3V_1D5V_AVDD AVDD2 LINE1_R/PORT-C-R LINE1_R [29]
Close pin41 Close pin46 41 20 V3D3_STB R2712 1 2 0R2J-2-GP
+5V_PVDD PVDD1 NC#20
C AUD_SPK_L+ 42 19 MIC_CAP C2713 1 2 SC10U6D3V3MX-GP C
[29] AUD_SPK_L+ SPK-OUT-L+ MIC-CAP AUD_AGND
Layout Note: AUD_SPK_L-
moat Speaker trace width >40mil @ 2W4ohm speaker power [29] AUD_SPK_L-
43
SPK-OUT-L- MIC2_R/PORT-F-R/SLEEVE
18
SLEEVE [29] Layout Note:
AUD_SPK_R-
71.03234.003
[29] AUD_SPK_R-
44
SPK-OUT-R- MIC2_L/PORT-F-L/RING
17
RING2 [29]
Width>40mil, to improve Headpohone Crosstalk noise
3D3V_S0 1D5V_S0 +3V_1D5V_AVDD AUD_SPK_R+
Change it to sharp will be better.
45 16
[29] AUD_SPK_R+ SPK-OUT-R+ MONO-OUT Add 2 vias (>0.5A) when trace layer change.
R2705 1 20R0402-PAD JDREF R2707 1 2 20KR2F-L-GP
+5V_PVDD 46
PVDD2 SPDIFO/FRONT_JD/JD3/GPIO3
15 DY AUD_AGND

GPIO0/DMIC-DATA
1

GPIO1/DMIC-CLK
R2710 1 2 0R2J-2-GP 1 R2708 EAPD#
DY C2715 [24] AMP_MUTE#
2 47
PDB MIC2/LINE2_JD/JD2
14
+3V_AVDD

SDATA-OUT
SC4D7U6D3V3KX-GP 0R0402-PAD COMBO-GPI 48 13 AUD_SENSE_A 1 2 AUD_SENSE
2

SPDIF-OUT/GPIO2 HP/LINE1_JD/JD1 AUD_SENSE [29] R2722

LDO3-CAP

SDATA-IN
R2709

DVDD-IO

PCBEEP
RESET#
Close pin40 49 200KR2F-L-GP AUD_SENSE_A 2 1
GND Layout Note:

DVDD

SYNC
DVSS

BCLK
AUD_AGND Place close to Pin 13 100KR2J-1-GP
ALC3234-CG-GP moat

10

11

12
+3V_AVDD
AUD_PC_BEEP

LDO3_CAP
Azalia I/F EMI
TP2702 1 +3V_AVDD
DMIC_DATA_R

C2718

C2719
C2717

1
EC2701
SC10P50V2JN-4GP

C2716
SC4D7U6D3V3KX-GP

SCD1U16V2KX-3GP
1

1
HDA_CODEC_SDOUT

2
HDA_CODEC_BITCLK
DY
2

2
EC2708 EC2709

SCD1U16V2KX-3GP
SC4D7U6D3V3KX-GP
1

DY DY
SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
2

1 R2714 2 DMIC_DATA_R
[52] DMIC_DATA 0R0402-PAD
0R2J-2-GP
1 R2716 2 DMIC_CLK_R
[52] DMIC_CLK
0R0402-PAD 1 R2719 2 CODEC_SDOUT_R
2

B [19] HDA_CODEC_SDOUT B
C2723 0R2J-2-GP
1 R2720 CODEC_BITCLK_R
SC22P50V2JN-4GP
DY [19] HDA_CODEC_BITCLK
2
1

0R0402-PAD 1 R2718 2 HDA_CODEC_SDIN0

[19] HDA_SDIN0
Close pin3 HDA_CODEC_SYNC
[19] HDA_CODEC_SYNC

HDA_CODEC_RST#
[19,29] HDA_CODEC_RST#
D2701
RN2701 HDA_SPKR_R 2
[20] HDA_SPKR 2 3 C2720
1 4 3 AUD_PC_BEEP_C 1 2AUD_PC_BEEP
[24] KBC_BEEP
SRN0J-6-GP KBC_BEEP_R 1 SCD1U16V2KX-3GP

1
BAT54C-7-F-3-GP R2717
1KR2J-1-GP

75.00054.E7D

2
2nd = 83.R2003.W81
3rd = 75.00054.A7D
4th = 83.R2003.V81

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Audio Codec ALC3234

Size Document Number Rev
A2
Janus HSW 40/50/70 A00
Date: Monday, February 10, 2014 Sheet 27 of 104
5 4 3 2 1
 5 4 3 2 1

D D

C (Blanking) C

B B

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A4
Janus HSW 40/50/70 A00
Date: Friday, February 07, 2014 Sheet 28 of 104
5 4 3 2 1
 5 4 3 2 1

SSID = AUDIO

Layout Note: Speaker

Speaker trace width >40mil @ 2W4ohm speaker power
SPK1
5
0R0603-PAD-1-GP-U 2 1 R2904 AUD_SPK_R+_C 1
[27] AUD_SPK_R+
D D
0R0603-PAD-1-GP-U 2 1 R2903 AUD_SPK_R-_C 2
[27] AUD_SPK_R- 0R0603-PAD-1-GP-U 2
[27] AUD_SPK_L+ 1 R2902 AUD_SPK_L+_C 3
0R0603-PAD-1-GP-U 2 1 R2901 AUD_SPK_L-_C 4 CONN Pin Net name
[27] AUD_SPK_L-
6
Pin1 SPK_R+
ACES-CON4-29-GP
Pin2 SPK_R-
20.F1639.004
Pin3 SPK_L+

SC2K2P50V3KX-GP

SC2K2P50V3KX-GP

SC2K2P50V3KX-GP

SC2K2P50V3KX-GP
EC2901

EC2902

EC2903

EC2904
2nd = 20.F1804.004

1
DY DY DY DY Pin4 SPK_L-

2
AUD_SPK_L-_C 1 AFTP2901
AUD_SPK_L+_C 1 AFTP2902
AUD_SPK_R-_C 1 AFTP2903
AUD_SPK_R+_C 1 AFTP2904

C C

AUD_PORTA_L_R_B 1 AFTP2906

Combo Jack
AUD_PORTA_R_R_B 1 AFTP2907
RN2901 3D3V_S0
AUD_AGND 1 AFTP2908
1 4 AUD_SENSE 1 AFTP2909
[27] MIC2_VREFO
2 3

1
HPMIC1 R2914
SRN2K2J-1-GP 0R0603-PAD-1-GP-U 2
[27] RING2 1 R2906 RING2_R 3 10KR2J-3-GP
R2908 1 2 10R2F-L-GP AUD_HP1_JACK_L1 0R0603-PAD-1-GP-U 2 1 R2907 AUD_PORTA_L_R_B 1
[27] AUD_HP1_JACK_L C2907 1 2 LINE1-L_C R2922 1 2 1KR2J-1-GP AUD_DELAY

2
[27] LINE1_L SC4D7U6D3V3KX-GP R2912 1
[27] LINE1_VREFO_L 2 4K7R2J-2-GP JACK_PLUG 5
JACK_PLUG_DET 6 JACK_PLUG_DET
R2910 1 2 10R2F-L-GP AUD_HP1_JACK_R1 0R0603-PAD-1-GP-U 2 1 R2909 AUD_PORTA_R_R_B 2 10 mils
[27] AUD_HP1_JACK_R C2908 1
[27] LINE1_R 2 LINE1-L_R R2921 1 2 1KR2J-1-GP 0R0603-PAD-1-GP-U 2 1 R2911 SLEEVE_R 4

1
SC4D7U6D3V3KX-GP R2913 1 2 4K7R2J-2-GP MS
[27] LINE1_VREFO_R

SC100P50V2JN-3GP
EC2908

SC100P50V2JN-3GP
EC2907

SC100P50V2JN-3GP

EC2906

SC100P50V2JN-3GP

EC2905
1 0R0402-PAD

1
10KR2J-3-GP
R2920

10KR2J-3-GP
R2919
[27] SLEEVE AUDIO-JK430-GP

1
R2916
NON_DELAY

2
2 022.10002.0001

2
DY DY AUD_AGND
DY DY DY DY
2

2
AUD_AGND

B B

AUD_AGND AUD_AGND
Delay circuit
AUD_AGND
JACK_PLUG 10 mils

1
AUD_DELAY

1
R2905
AUD_DELAY 100KR2J-1-GP C2902

S
SC10U6D3V3MX-GP

2
Q2901

2
2N7002K-2-GP
AUD_AGND
AUD_AGND 84.2N702.J31
AUD_DELAY
AUD_PORTA_R_R_B 2ND = 84.2N702.031
AUD_PORTA_L_R_B
RING2_R 5V_PW R_2 +3V_AVDD

D
AUD_SENSE
SLEEVE_R R2923
1

1 2 10 mils
R2915 R2918 AUD_SENSE [27]
DY 470KR2J-2-GP 100KR2J-1-GP DY 0R0603-PAD-1-GP-U NON_DELAY
2

2
AZ2025-01H-R7G-GP

AZ2025-01H-R7G-GP

AZ2025-01H-R7G-GP

AZ2025-01H-R7G-GP

AZ2025-01H-R7G-GP

R2917
2

2
ED2901

ED2902

ED2903

ED2904

ED2905

A <Core Design> A
U2901 2 DY 1
0R3J-0-U-GP HDA_CODEC_RST# [19,27]
DY DY DY DY DY S D
moat AUD_AGND
G
4 3
G
SLEEVE [27] Wistron Corporation
SLEEVE_CTRL 5 2 MUTE_CTRL 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
D DY S
1

6 1
1

4th = 84.DMN66.03F C2901 Title

DY SC1U10V2KX-1GP
3rd = 75.00601.07C Speaker/HPMIC
2

2N7002KDW -GP
2nd = 84.2N702.E3F
84.2N702.A3F Size Document Number Rev
A3
Janus HSW 40/50/70 A00
Date: Friday, February 07, 2014 Sheet 29 of 104
5 4 3 2 1
 5 4 3 2 1

Layout:
For RTL8111G(S) C3021: colse to Pin8
* Place C3021 to C3024 close to each VDD10 pin--3, 8, 22, 30 C3022 close to Pin30
For RTL8106E
* Place C3021,C3022 close to each VDD10 pin-- 8, 30
C3023: close to Pin3
C3024: close to Pin22 LAN CHIP (10/100/1000M & 10/100M co-lay)
R3001
REGOUT VDD10
8111G/LAN_SW
1 2
C3002,R3001:
D
Only for
8111G LAN_SW 8111G/LAN_SW D
0R3J-0-U-GP

C3019 SCD1U16V2KX-3GP

C3021 SCD1U16V2KX-3GP

C3022 SCD1U16V2KX-3GP

C3023 SCD1U16V2KX-3GP

C3024 SCD1U16V2KX-3GP
RTL8111 LDO mode. R3032 C3014
LAN_SW LAN_TXP_C_PCH_RXP4

SC4D7U6D3V3KX-GP C3012
C3002 L3001 2K49R2F-GP 1 2 SCD1U16V2KX-3GP PCIE_PRX_LANTX_P4 [16]
1

1
1 2 RTL8111GUS-CG RTL8111G-CGT RTL8106EUS-CG RTL8106E-CG 1 2 LAN_TXN_C_PCH_RXN4 1 2 SCD1U16V2KX-3GP PCIE_PRX_LANTX_N4 [16]
8111G IND-4D7UH-242-GP C3016
LAN_SW PCIE_PTX_LANRX_P4_C
SCD1U16V2KX-3GP
2

2
71.08111.W03 71.08111.U03 71.08106.003 071.08106.0003 PCIE_PTX_LANRX_N4_C PCIE_PTX_LANRX_P4_C [16]
PCIE_PTX_LANRX_N4_C [16]
68.4R71E.10G
SWR mode LDO mode SWR mode LDO mode CLK_PCIE_LAN_P4 [18]
CLK_PCIE_LAN_N4 [18]

3D3V_LAN_S5

LANXOUT
10/100/1000M 10/100/1000M 10/100M 10/100M

LANXIN
VDD10
LED0 1 TP3003 TPAD14-OP-GP

RSET
LED1 1 TP3002 TPAD14-OP-GP
Layout: LED2 1 TP3001 TPAD14-OP-GP
For RTL8111G(S)
* Place C3007 and C3008 close to each VDD33 pin-- 11, 32

32
31
30
29
28
27
26
25
For RTL8106E LOM30
* Place C3003 and C3008 close to each VDD33 pin-- 23, 32

AVDD33

AVDD10
CKXTAL2
CKXTAL1
LED0
(GPO) LED1/GPO
(LED1) LED2
RSET
33
GND
3D3V_LAN_S5 VDDREG

R3006 C3018 1
40 mils 1 2 1 (NC) REGOUT 24 REGOUT
2
SC1U10V2KX-1GP
[31] LAN_MDI0P MDIP0 VDDREG C3025 1
2 23 2 SCD1U16V2KX-3GP
1

[31] LAN_MDI0N VDD10 MDIN0 (DVDD33) VDDREG VDD10 3D3V_S0

C3007 C3008 0R0603-PAD-1-GP-U 3 22
1

AVDD10 (NC) (NC) DVDD10

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

C3003 PCIE_WAKE#
8111G/LAN_SW LAN_SW LAN_SW [31] LAN_MDI1P
4
MDIP1 LANWAKE#
21 PCIE_WAKE# [17,24]
SCD1U16V2KX-3GP

8106E C3008: close to Pin32 5 71.08111.U03 ISOLATE# 20 ISOLATE# 2 1

2

1
C3009 C3010 [31] LAN_MDI1N MDIN1 PLT_RST#_LAN R3014
6 19

SCD1U16V2KX-3GP
C3007: close to Pin11 MDIP2 (NC) (071.08106.0003)
2

1
[31] LAN_MDI2P PERST# LAN_TXN_C_PCH_RXN4 1KR2J-1-GP
7 18
C3003: close to Pin23 [31] LAN_MDI2N MDIN2 (NC) HSON

SC4D7U6D3V3KX-GP
VDD10 8 17 LAN_TXP_C_PCH_RXP4 R3015

2
AVDD10 HSOP 15KR2J-1-GP

AVDD33 (NC)
MDIP3 (NC)
MDIN3 (NC)

REFCLK_N
REFCLK_P
CLKREQ#
X5R

2
HSIN
HSIP
C C
RTL8111G-CGT-1-GP-U1 071.08106.0003(DVC)/71.08111.U03(DVJ)

9
10
11
12
13
14
15
16
RTL8111G-CGT (71.08111.U03/LDO Mode): 10/100/1000M < 252 mW.
3D3V_LAN_S5 RTL8106E-CG (071.08106.0003): 10/100M <70mW.
3D3V_LAN_S5
[31] LAN_MDI3P 3D3V_S5
1
2

[31] LAN_MDI3N
C3004 C3005 3D3V_LAN_S5 R3033
RN3001 CLK_LAN_REQ4#_R PCIE_WAKE# 1 2
DY

1
SRN10KJ-5-GP PCIE_PTX_LANRX_P4_C
DY DY PCIE_PTX_LANRX_N4_C 10KR2J-3-GP
CLK_PCIE_LAN_P4
BQ402_1 4
3

2
SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP
CLK_PCIE_LAN_N4

84.T3904.H11 3D3V_LAN_S5
Layout:
Q3003 LMBT3904LT1G-GP 3D3V_LAN_S5
PLT_RST#_LAN
C3004: close to Pin32
[17,24,36,52,58,65,73,96] PLT_RST#
E DY C
C3005: close to Pin11

1
R3016
C3011 R3003 DY
1 2 LANXOUT 1 2 10KR2J-3-GP

1
SC15P50V2JN-2-GP R3004

2
0R0603-PAD

CLK_LAN_REQ#_EN
3D3V_LAN_S5 rise time must be controlled DY 10KR2J-3-GP
between 0.5 mS and 100 mS.

2
4

3
3D3V_S5 3D3V_LAN_S5 X3001
Q3004 XTAL-25MHZ-181-GP
DMP2130L-7-GP 82.30020.G71
85mA
S

B
1

2
D 84.T3904.H11
D

Q3002 LMBT3904LT1G-GP
1

[18,20] CLK_PCIE_LAN_REQ4# C E CLK_LAN_REQ4#_R

1

B C3013 R3021 B
DY
G

10KR2J-3-GP C3015 C3017

SCD1U16V2KX-3GP
2

SCD1U16V2KX-3GP

SC1U10V2KX-1GP C3001 1 R3005

R3022 DY 2
2

LANXIN 1 2
2

1 2 PM_LAN_ENABLE_R 0R0402-PAD
SC15P50V2JN-2-GP
LAN_ENABLE_R_C

20KR2J-L2-GP 84.02130.031
2nd = 84.00102.031

Q3001
3rd = 84.03413.B31
G
[24] PM_LAN_ENABLE
1

D
R3023
100KR2J-1-GP S

2N7002K-2-GP
2

1.0V Source
R3001 C3002 C3023 C3024 C3007 L3001 C3012 C3019 C3009 C3010 C3003

RTL8111G-CGT LDO X
(71.08111.U03) O O O O O X X X X X

A RTL8111GUS-CG A
SWR X X O O O O O O O O X
(71.08111.W03)/
RTL8106EUS-CG
(71.08106.003)
<Core Design>

RTL8106E-CG Wistron Corporation

LDO X X X X X X X X X X O 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
(071.08106.0003) Taipei Hsien 221, Taiwan, R.O.C.

Title

LAN RTL8111/RTL8106
Size Document Number Rev
A2
Janus HSW 40/50/70 A00
Date: Friday, February 07, 2014 Sheet 30 of 104
5 4 3 2 1
 5 4 3 2 1

SSID = LOM

LAN TransFormer (10/100/1000M & 10/100M co-lay)

Layout note:
D
30 mil spacing between MDI differential pairs. U3101 D

LAN_MDI0P 1 10 LAN_MDI0P
MCT0 LAN_MDI0N IN1 NC#10 LAN_MDI0N
2 IN2 NC#9 9
MCT1 3 8
MCT2 LAN_MDI1P GND GND LAN_MDI1P
4 IN3 NC#7 7
XF3102 XFORM-12P-48-GP MCT3 LAN_MDI1N 5 DY 6 LAN_MDI1N
IN4 NC#6

[30] LAN_MDI3N 12 1CT:1CT

1 MDO3-
1
EC3108 DY2SC10P50V2JN-4GP 3 MCT0 TVW DF1004AD0-1-GP
75.01004.073

4
3
2
1
[30] LAN_MDI3P 11 2 MDO3+
1 RN3101
EC3107 DY2SC10P50V2JN-4GP 10 SRN75J-1-GP
U3102
[30] LAN_MDI2N 8 10/100/1000
1CT:1CT
5 MDO2-
1 LAN_MDI2P LAN_MDI2P
DY 2 1 10

5
6
7
8
EC3106 SC10P50V2JN-4GP MCT1 LAN_MDI2N IN1 NC#10 LAN_MDI2N
4 2 IN2 NC#9 9
3 GND GND 8

MCT
[30] LAN_MDI2P 7 6 MDO2+ LAN_MDI3P 4 7 LAN_MDI3P
LAN_MDI3N IN3 NC#7 LAN_MDI3N
1
EC3105 DY2SC10P50V2JN-4GP 5 IN4 DY NC#6 6
9

1
68.68167.30D C3101 TVW DF1004AD0-1-GP
SC100P3KV8JN-2-GP
XF3101 75.01004.073

2
9 78.1013N.1AL
C C

[30] LAN_MDI1N 7 6 MDO1-

1
EC3104 DY2SC10P50V2JN-4GP 4 MCT2

[30] LAN_MDI1P 8 5 MDO1+

1CT:1CT
1
EC3103 DY2SC10P50V2JN-4GP 10

MDO0-
LOM_TCT

[30] LAN_MDI0N 11 2
1
EC3102 DY2SC10P50V2JN-4GP 3 MCT3 RJ45-8P-165-GP

[30] LAN_MDI0P 12 1 MDO0+ 9

1CT:1CT
MDO0+ CHASSIS#9
1
EC3101 DY2SC10P50V2JN-4GP 1 MDO0+
XFORM-12P-48-GP MDO0- 2 MDO0-
68.68167.30D MDO1+ 3
MDO2+ MDO1+
4 MDO2+
1

C3106 MDO2- 5
SCD01U50V2KX-1GP MDO1- MDO2-
6 MDO1-
MDO3+ 7
2

MDO3- MDO3+
8 MDO3-
10 CHASSIS#10
RJ45
Follow Reference Schematic 0.01uF~0.4uF
RJ45

B 022.10001.0551 B

2nd = 022.10001.0561

Layout:
Place near RJ45

AFTP3107 1 MDO0+
AFTP3102 1 MDO0-
AFTP3101 1 MDO1+
AFTP3103 1 MDO2+
AFTP3104 1 MDO2-
AFTP3106 1 MDO1-
AFTP3105 1 MDO3+
AFTP3108 1 MDO3-

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

XFOM&RJ45
Size Document Number Rev
A3
Janus HSW 40/50/70 A00
Date: Monday, February 10, 2014 Sheet 31 of 104
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size
(Reserved)Card Reader
Document Number Rev
A4
Janus HSW 40/50/70 A00
Date: Friday, February 07, 2014 Sheet 32 of 104
5 4 3 2 1
 5 4 3 2 1

D D

C
(Blanking) C

B B

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

(Reserved)
Size Document Number Rev
A4
Janus HSW 40/50/70 A00
Date: Friday, February 07, 2014 Sheet 33 of 104
5 4 3 2 1
 5 4 3 2 1

SSID = USB U3401

USB20_VCCA

Note:ZZ.09904.07C01
USB2.0 Port2
USB_PN1_R 1 6
I/O1 I/O4
2 GND VDD 5

1
USB_PP1_R 3 4 DY C3406 USB20_VCCA
I/O2 I/O3 USB2
DY

2
SCD1U16V2KX-3GP 6 8
TR3401 75.09904.07C 1
[16] USB_PN1 1 2 USB_PN1_R
AZC099-04S-1-GP USB_PN1_R 2
D [16] USB_PP1 4 3 USB_PP1_R USB_PP1_R 3 D
4
FILTER-4P-6-GP 5 7

69.10103.041
USB20_VCCA 1 AFTP6205 SKT-USB8-14-GP

USB_PN1_R 1 AFTP6204
USB_PP1_R 1 AFTP6209 22.10321.E91

C C

U3402 U3403

USB30_VCCC

Note:ZZ.09904.07C01
USB3_PRX_CTX_N0_C 1 10 USB3_PRX_CTX_N0_C USB_PN0_C 1 6
TR3404 USB3_PRX_CTX_P0_C IN1 NC#10 USB3_PRX_CTX_P0_C I/O1 I/O4
2 IN2 NC#9 9
3 GND GND 8 2 GND VDD 5
[16] USB_PN0 4 3 USB_PN0_C USB3_PTX_CRX_N0_C 4 7 USB3_PTX_CRX_N0_C
IN3 NC#7

1
USB3_PTX_CRX_P0_C 5 6 USB3_PTX_CRX_P0_C USB_PP0_C 3 4
USB_PP0_C IN4 NC#6 I/O2 I/O3 C3405
[16] USB_PP0 1 2 DY DY DY
SCD1U16V2KX-3GP

2
FILTER-4P-6-GP TVW DF1004AD0-1-GP

USB3.0 Port1
69.10103.041 AZC099-04S-1-GP
USB30_VCCC 1 AFTP6210
B 75.01004.073 USB_PN0_C 1 AFTP6211 B
75.09904.07C USB_PP0_C 1 AFTP6212
USB1
10 12
USB3_PTX_CRX_P0_C 9
USB30_VCCC 1

USB3_PTX_CRX_N0_C 8
USB_PN0_C 2
7
USB_PP0_C 3
C3404 USB3_PRX_CTX_P0_C 6
R3408 R3410
4
1 2 USB3_PTX_CRX_P0_R 2 1 USB3_PTX_CRX_P0_C [16] USB3_PRX_CTX_P0 2 1 USB3_PRX_CTX_P0_C USB3_PRX_CTX_N0_C 5
[16] USB3_PTX_CRX_P0 AFTP6217
11 13 1
SCD1U16V2KX-3GP
0R0402-PAD 0R0402-PAD
SKT-USB13-151-GP

22.10341.Q21

C3402

C3401
USB3_PTX_CRX_P0_C
USB3_PTX_CRX_N0_C

1
DY DY

2
SC4D7P50V2CN-1GP

SC4D7P50V2CN-1GP
A <Core Design> A
C3403
R3409 R3411
USB3_PTX_CRX_N0_R USB3_PTX_CRX_N0_C USB3_PRX_CTX_N0_C
[16] USB3_PTX_CRX_N0 1 2 2 1 [16] USB3_PRX_CTX_N0 2 1
Wistron Corporation
SCD1U16V2KX-3GP 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
0R0402-PAD 0R0402-PAD Taipei Hsien 221, Taiwan, R.O.C.

Title

USB 3.0
Size Document Number Rev
Custom
Janus HSW 40/50/70 A00
Date: Monday, February 10, 2014 Sheet 34 of 104
5 4 3 2 1
 5 4 3 2 1

5V_S5 U3502
USB30_VCCC
1
2
GND
IN
FLG1
OUT1
8
7 USB30_VCCC
USB3.0 Port1 2A
3 EN1# OUT2 6 USB20_VCCA

1
4 EN2# DY 5

100KR2J-1-GP
[24] USB_PW R_EN# FLG2 USB_OC#0_1 [16,18]

1
R3501

C3508
C3507
C3502

1
SC1U10V2KX-1GP DY TC3501

SC1U10V2KX-1GP
2
AP2182SG-13-GP C3512 C3513
74.02182.071
DY SC100U6D3V6MX-GP
78.10710.52L

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP
2

2
SCD1U16V2KX-3GP
2
D D
USB20_VCCA
5V_S5
U3503

5 IN OUT 1
GND 2
1

C3505
DY [24] USB_PW R_EN# 4 EN# OC# 3 USB_OC#0_1 [16,18]
Active Low
SC1U10V2KX-1GP
2

USB2.0 Port2
SY6288DAAC-GP USB20_VCCA
074.06288.009B
2A

1
C3506 DY TC3502
USB30_VCCC C3503 C3514 C3509 SC100U6D3V6MX-GP

SC1U10V2KX-1GP
5V_S5 78.10710.52L

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP
SCD1U16V2KX-3GP

2
U3504

5 IN OUT 1
GND 2
1

[24] USB_PW R_EN# 4 EN# OC# 3 USB_OC#0_1 [16,18]

C3510 Active Low
SC1U10V2KX-1GP
2

SY6288DAAC-GP
074.06288.009B
C C

Layout Note: Close CON1

5V_S5
Support 2A USB20_VCCB
U3501

2 6
2A
IN#2 OUT#6
3 7
USB2.0 Port3 (IO Board)
100KR2J-1-GP
IN#3 OUT#7
1
R3502

C3517

C3518
8

SC1U10V2KX-1GP
OUT#8

1
1

C3515 C3516
C3501 [24] USB_PW R_EN#
4 EN/EN# DY DY
1

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP
2

2
GND

SCD1U16V2KX-3GP
5 9
2

[16] USB_OC#2_3 FLT# GND

SCD1U16V2KX-3GP

TPS2000CDGNR-GP

74.02000.B71

B 2nd = 74.02301.079 B

5V_S5
Support 2A USB20_VCCB
U3505

5 IN OUT 1
GND 2
[24] USB_PW R_EN# 4 EN# OC# 3 USB_OC#2_3 [16]
Active Low
1

C3504 SY6288DAAC-GP
074.06288.009B
2

SCD1U16V2KX-3GP

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

USB Power SW
Size Document Number Rev
Janus HSW 40/50/70 A00
Date: Friday, February 07, 2014 Sheet 35 of 104
5 4 3 2 1
 5 4 3 2 1

SSID = Reset.Suspend
Power Good
3D3V_S0

ROSA Run Power

1
D D
R3601
1KR2J-1-GP

[49] 1D35V_VTT_PW RGD 1 R3610 2

2
0R0402-PAD

[7,48] 1D05V_VTT_PW RGD 1 R3611 2 ALL_SYS_PW RGD [24]

3D3V_AUX_S5 0R0402-PAD

1 PS_S3CNTRL
DY 2

R3607
100KR2J-1-GP
D G S
6

5V_S5
Q3601 5V_S5 5V_S0
2N7002KDW -GP DY U3601
84.2N702.A3F 4 13 5V_S0
1

2nd = 84.2N702.E3F S G VBIAS OUT1#13

D OUT1#14 14

1
3rd = 75.00601.07C 12 3V5V_CT1 3D3V_S0 5V_S0 Comsumption
CT1

C3603
SC10U10V5KX-2GP
1
4th = 84.DMN66.03F R3609
2
IN1#1
8
Peak current 5A

2
IN1#2 OUT2#8
[17,24,48,49,51] PM_SLP_S3# 1 2 3V5V_S0_ON 3 EN1 OUT2#9 9
10 3V5V_CT2
[17,24,26] PCH_PW ROK 0R0402-PAD
CT2 3D3V_S0

C3601
SC470P50V2KX-3GP

C3602
SC470P50V2KX-3GP
C 6 C
3D3V_S5 IN2#6

1
7 IN2#7 GND 11 3D3V_S0 Comsumption

C3605
SC10U10V5KX-2GP
5 15
EN2 GND Peak current 2.5A

2
G5016KD1U-GP

074.05016.0093

R3608

1D05V_S0 1 DY 2 H_THERMTRIP# [20]

1KR2J-1-GP
B B
Q3602
MMBT2222A-3-GP

E
[4] H_THERMTRIP_EN H_THERMTRIP_EN B 84.02222.V11

C
R3606
C3604
1

[17,24,30,52,58,65,73,96] PLT_RST# 1 2 SCD1U16V2KX-3GP

2

4K7R2J-2-GP
1

R3605
2K2R2J-2-GP
D3602
BAS16-6-GP
2ND = 83.00016.F11
2

2
3rd = 83.00016.P11
3 PURE_HW _SHUTDOW N# [24,26,76]
4th = 83.00016.G11
[45] 3V_5V_EN 1
83.00016.K11
1

1 2 S5_ENABLE [24]
R3602
DY R3603
200KR2F-L-GP

1KR2J-1-GP
A <Core Design> A
2

Check R3603 is 1k or 2k.

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Power Plane Enable

Size Document Number Rev
A3
Janus HSW 40/50/70 A00
Date: Monday, February 10, 2014 Sheet 36 of 104
5 4 3 2 1
 5 4 3 2 1

SSID = Reset.Suspend

Layout Note:
Place Close SO-DIMM1
D D
DDR_VREF_S3
1D35V_S3

1
R3704
0R2J-2-GP R3706
1K8R2F-GP

SA_DIMM_VREFDQ DY

2
2R2F-GP

SODIMM1 M_VREF_CA_DIMMA 1 R3708 2 +V_SM_VREF_CNT [5]

1
C3701
SCD022U16V2KX-3GP

2
1
R3703 +V_VREF_PATH3

1
1K8R2F-GP
R3707
24D9R2F-L-GP

2
C C

Layout Note:
Place Close SO-DIMM1

DDR_VREF_S3 1D35V_S3

1
R3710
0R2J-2-GP R3701
1K8R2F-GP
DY
2R2F-GP
2

R3702
[5] DDR_W R_VREF01 1 2 M_VREF_DQ_DIMMA
1

C3702 R3709
SCD022U16V2KX-3GP 1K8R2F-GP
2

+V_VREF_PATH1
2
1

B R3711 B
24D9R2F-L-GP
2

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

S3 Reduction Circuit
Size Document Number Rev
A3
Janus HSW 40/50/70 A00
Date: Friday, February 07, 2014 Sheet 37 of 104
5 4 3 2 1
 5 4 3 2 1

3D3V_S5 3D3V_S5_PCH
R3801
1 2
D
NON DS3 D
0R5J-5-GP

3D3V_S5
Obs reason:
For new project,
pls help to use cost down version
SY6288C10CAC for instead.
C3801

1
3D3V_S5_PCH

SC1U10V2KX-1GP
2
U3801
DS3
1
DS3 8
GND OUT#8
2 IN#2 OUT#7 7
C
[17,24] PM_SLP_SUS# 1
DS3 2 DS3_PWRCTL
3
4
IN#3 OUT#6 6
5
C

R3802 EN/EN# OCB C3802

1
0R2J-2-GP

SC1U10V2KX-1GP
SY6288CCAC-GP
74.06288.079 (OBS)

2
DS3
RdsON: 100m ohm

DS3

B B

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
DSW
Size Document Number Rev
A4 A00
Janus HSW 40/50/70
Date: Friday, February 07, 2014 Sheet 38 of 104
5 4 3 2 1
 5 4 3 2 1

D D

(Blanking)
C C

B B

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
(Reserved) 1D05_M
Size Document Number Rev
A4 A00
Janus HSW 40/50/70
Date: Friday, February 07, 2014 Sheet 39 of 104
5 4 3 2 1
(Blanking)

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A4 A00
Janus HSW 40/50/70
Date: Friday, February 07, 2014 Sheet 40 of 104
 5 4 3 2 1

D D

C
(Blanking) C

B B

<Core Design>

Wistron Corporation
A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, A
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A4
Janus HSW 40/50/70 A00
Date: Friday, February 07, 2014 Sheet 41 of 104
5 4 3 2 1
 5 4 3 2 1

SSID = PWR.Support
5V_S5

1
PR4202 3D3V_S5
15KR2F-GP PQ4202 84.T3904.H11 PR4203

E
10KR2J-3-GP

1
D PQ3802_1 B LMBT3904LT1G-GP 3D3V_S5 D

1
2
2
PD4203

1
PR4209 PSID_DISABLE#_R_C LBAV99LT1G-1-GP
100KR2J-1-GP PR4204
75.00099.O7D 2K2R2J-2-GP
Layout Note: 2nd = 75.00099.K7D

G
1

3
PSID Layout width > 25mil

2
84.05067.031 3rd = 75.00099.Q7D
PR4217 PR4205
PS_ID_R 1 2 PS_ID_R2 D S PS_ID 1 2
4th = 75.00099.D7D
PSID_EC [24]
0R3J-0-U-GP 33R2J-2-GP
PQ4201

1
DMN5L06K-7-GP
PD4204 PR4206
JGND DY 1 2
PESD24VS2UT-GP
DY
33R2J-2-GP
EL4203

3
1 2

0R0J-GP
ACES-CON7-6-GP-U
60ohm@100MHz
NP2
DCR=0.02 ohm
7 Max current = 6000mA
6 1 AFTP3806
5 1 AFTP3803 +DC_IN AD+
4 PU4201
3 +DC_IN_C 1 S D 8
S D

PC4205

PC4203

PC4204

PC4206
2 2 7

SC10U25V5KX-GP
SCD01U50V2KX-1GP

SCD01U50V2KX-1GP

SCD01U50V2KX-1GP
1
S D
EC4202

DY PC4202 PC4201

240KR3-GP
3 6
SCD1U25V2KX-GP

K
1

1
PR4214 SCD1U50V3KX-GP G D

PR4207
1 4 5

SC1U50V5ZY-1-GP-U
NP1 EC4201 PD4201 DY DY
ZZ.00PAD.V91 3K3R6J-GP P6SBMJ24APT-GP SI7121DN-T1-GE3-GP
2

2
DCIN1

2
SC10U25V5KX-GP

20.F1783.007

A
1

EL4201
2nd = 20.F1718.007 PAD-2P-4516-GP-U PR4212 PQ3809_D
C 3rd = 20.F1763.007 100KR2J-1-GP 84.2N702.A3F PQ4205 C

1
R2
JGND JGND 2nd = 84.2N702.E3F PQ4204 E Id=-9.6A
3rd = 75.00601.07C C AD_OFF_L B PR4208
2

Qg=-25nC
1

R1
4th = 84.DMN66.03F B R1 C AD_OFF_R 47KR3J-L-GP
PQ4206
E Rdson=18~30mohm
3 4 R2 PDTA124EU-1-GP

2
PDTC124EU-1-GP 84.00124.K1K
ZZ.00PAD.V91 AC_IN#_G 2 5 84.00124.H1K 2nd = 84.05124.A11
EL4202
2nd = 84.05124.011
PAD-2P-4516-GP-U 1 6

2N7002KDW-GP
1

PC4208
SC1U25V3KX-1-GP

1
PR4213
100KR2J-1-GP 1 2 PQ4208
PR4210 PR4215

2
1KR2J-1-GP G PQ3808G 1 2
2

3D3V_S5 1KR2J-1-GP
PQ3808D D

1
[24] AC_IN_KBC# S PC4209
PR4211
DY

SCD01U50V2KX-1GP
DT MODE 10KR2J-3-GP

2
2N7002K-2-GP
84.2N702.J31

1
PWR_CHG_AD_OFF_R
[24] PWR_CHG_AD_OFF

84.2N702.A3F
2nd = 84.2N702.E3F
3rd = 75.00601.07C
4th = 84.DMN66.03F
AFTP3801 1 +DC_IN_C
B AFTP3802 1 PS_ID_R
AFTP3805 1 +DC_IN_C
PR4216
2 1
DY
100KR2J-1-GP
BAT_IN#
PQ4203
B
1 6
PC4210
2 5 PQ4203_5 1 2
SCD47U6D3V2KX-GP
BAT_IN# [24,43,44]
3 4

1
[4,24,44,46] H_PROCHOT# 2N7002KDW-GP PR4218
100KR2J-1-GP

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number

DCIN Rev
A2 A00
Janus HSW 40/50/70
Date: Friday, February 07, 2014 Sheet 42 of 104
5 4 3 2 1
 5 4 3 2 1

SSID = PWR.Support
PBAT_PRES1# 1 AFTP3902
PBAT_SMBDAT1 1 AFTP3903
BT+ PBAT_SMBCLK1 1 AFTP3904
BT+ 1 AFTP3905
BT+ 1 AFTP3907
D BT+ 1 AFTP3908 D

K
1

1
EC4304
DY
SCD1U50V3KX-GP EC4303
SCD1U25V2KX-GP DY PD4302
SMF18AT1G-GP Batt Connecter
2

A
BAT1
10
1
RN4301
4 5 2
3 6 PBAT_SMBCLK1 3
[24,44] BAT_SCL
2 7 PBAT_SMBDAT1 4
[24,44] BAT_SDA
1 8 PBAT_PRES1# 5
[24,42,44] BAT_IN#
6
AFTP3901 1 BAT_ALERT 7
SRN100J-4-GP 8
9
11
C C

2
EC4301 EC4302 EC4305 ALP-CON9-6-GP-U
1

1
SC10P50V2JN-4GP

SC10P50V2JN-4GP

SC10P50V2JN-4GP
AFTP3906
DY DY
1
DY 1
1 AFTP3909
1 AFTP3910
2

20.81925.009
2nd = 20.81928.009
Placement: Close to Batt Connector

BAT_SCL
BAT_IN#

BAT_SDA

B B
3

D4302 D4303 D4301

LBAV99LT1G-1-GP LBAV99LT1G-1-GP LBAV99LT1G-1-GP
75.00099.O7D 75.00099.O7D 75.00099.O7D
1

2nd = 75.00099.K7D 2nd = 75.00099.K7D 2nd = 75.00099.K7D 3D3V_AUX_KBC <Core Design>

3rd = 75.00099.Q7D 3rd = 75.00099.Q7D 3rd = 75.00099.Q7D

A 4th = 75.00099.D7D 4th = 75.00099.D7D 4th = 75.00099.D7D
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

BATT CONN
Size Document Number Rev
A4
Janus HSW 40/50/70 A00
Date: Friday, February 07, 2014 Sheet 43 of 104
5 4 3 2 1
 5 4 3 2 1

SSID = Charger
PWR_CHG_CMPIN

1
PR4429
150KR2F-L-GP

PWR_CHG_CMPIN_R 2
AD+_TO_SYS DCBATOUT

BT+
PU4402 PR4402 PU4403
AD+ 8 D S 1 1 2 1 S D 8
7 D S 2 D01R3721F-GP-U 2 S D 7
6 D S 3 3 S D 6
2N7002KDW-GP 5 D G 4 AD+ 4 G D 5 CHARGER_SRC DCBATOUT
D D
3 4 CHG_AGND Id= -10A PG4412

1
2 1
Qg= -22nC

PR4403
100KR2J-1-GP

1
[24] AD_IA_HW2 2 5 AD_IA_HW [24] SI7121DN-T1-GE3-GP SI7121DN-T1-GE3-GP
Rdson=15~18mohm GAP-CLOSE-PWR

GAP-CLOSE-PWR-3-GP
1 6
84.07121.037 PR4405
84.07121.037 PG4413
470KR2J-2-GP

1
2nd = 84.03605.037

PWR_CHG_CMPIN_RR
PR4404 2nd = 84.03605.037 2 1

1
PQ4407 AD+_G_2

PG4402
3KR5J-GP PG4403 GAP-CLOSE-PWR

2
Id= -10A
CHG_AGND 4th = 84.DMN66.03F

2
GAP-CLOSE-PWR-3-GP PG4414

10KR2F-2-GP
3rd = 75.00601.07C Qg= -22nC PR4406 2 1

PR4401
2

2
2nd = 84.2N702.E3F Rdson=15~18mohm 0R2J-2-GP

DC_IN_D
84.2N702.A3F 2 GAP-CLOSE-PWR
DY 1
PG4415

1
2N7002KDW-GP 2 1

AD+_G_1
1 2
GAP-CLOSE-PWR
1

3 4

SC1U25V3KX-1-GP
PC4402
PR4427
66K5R2F-GP PWR_CHG_ACOK 2 5 SCD1U25V2KX-GP

SC4D7U25V5KX-GP
CHARGER_SRC

PC4404
1 6

1
AD+

SC1U25V3KX-1-GP

SC10U25V5KX-GP

SC10U25V5KX-GP
2

83.1R504.A8F

SC2200P50V2KX-2GP

SCD1U25V2KX-GP
PWR_CHG_CMPIN PQ4402 2nd = 83.1R004.H8F

PC4403

PC4408

PC4406

PC4426

PC4409

EC4402
SCD1U50V3KX-GP
2

PWR_CHG_ACN
PWR_CHG_ACP

EC4401
3rd = 83.1R504.B8F

1
4th = 84.DMN66.03F

1
4th = 83.2R004.08F

1
3rd = 75.00601.07C
DY
1

2nd = 84.2N702.E3F PWR_CHG_REGN

PR4408 CHG_AGND

2
PR4407 84.2N702.A3F PD4401 DY

2
DY

PWR_CHG_BTST_R

2
5
6
7
8
309KR2F-GP 1 2 PWR_CHG_VCC PR4409 SD103AWS-1-GP

SCD47U25V3KX-1GP

D
D
D
D
CHG_AGND 0R3J-0-U-GP
84.00412.037

PC4010
1 2 K A 1 2 PU4405
2

10R5J-GP

1
PC4407 SIS412DN-T1-GE3-GP

1
PU4404 SC1U25V3KX-1-GP
PWR_CHG_IOUT 65BOM charger

ACN
ACP
2
3D3V_AUX_S5 PWR_CHG_REGN

G
S
S
S
SCD047U25V2KX-GP
20
VCC
1

CHG_AGND

1
2
3D3V_AUX_KBC

PC4411

4
3
2
1
PC4412

PR4411
SCD01U50V2KX-1GP

PR4438 PR4430
1

1
102KR2F-GP PWR_CHG_ACDET 6 17 PWR_CHG_BTST
100KR2J-1-GP
1

PR4431 100KR2J-1-GP DY ACDET BTST

47KR2F-GP HPA02224RGRR-1-GP Charger Current=1.4~3.6A
2

2
1

PR4415 PWR_CHG_CMPOUT

2
1
16
2

PR4412 REG
3K3R2F-2-GP
2

1
PR4414 3
3K3R2F-2-GP CMPOUT PR4416
PR4413 18 PWR_CHG_HIDRV
84K5R2F-GP HIDRV BT+
PR4432 3D3MR2J-GP D01R3721F-GP-U
PC4413 PL4401
2

1 2
4
DY

SC10U25V5KX-GP
CMPIN SC3300P50V3KX-1GP

SC10U25V5KX-GP

SC10U25V5KX-GP
C C

SC10U25V5KX-GP
120KR2F-L-GP 19 PWR_CHG_PHASE 1 2 BT+_R 1 2
2

2
PHASE

GAP-CLOSE-PWR-3-GP
PWR_CHG_CMPIN IND-5D6UH-45-GP 64.R0105.7FL

GAP-CLOSE-PWR-3-GP

PC4415

PC4416

PC4417

PC4418

SCD1U50V3KX-GP
CHG_AGND 68.5R610.10U

PC4419
CHG_AGND 2 1 PWR_CHG_BAT_SCL 9 15 PWR_CHG_LODRV

2
SCL LODRV

2
PG4407 GAP-CLOSE-PWR-3-GP PU4406

PG4410

1
PG4409
[24,43] BAT_SCL

SIS412DN-T1-GE3-GP
DY

5
6
7
8
2 1 PWR_CHG_BAT_SDA 8 DY
[24,43] BAT_SDA

D
D
D
D
3D3V_AUX_S5 PG4408 GAP-CLOSE-PWR-3-GP SDA

1
PC4420

2
SCD1U25V2KX-GP
13 PWR_CHG_SRP 1 PR4421 2
SRP 65BOM charger
1

PWR_CHG_ILIM 10 10R2F-L-GP
ILIM

1
PR4417 12 PWR_CHG_SRN 1 PR4420 2
SRN

G
S
S
S
100KR2J-1-GP PR4418 7D5R2F-GP DY
[24] BOOST_MODE# 1 2 PWR_CHG_IFAULT 11

4
3
2
1
BM#
2

0R0402-PAD CHG_AGND 84.00412.037

2

10KR2F-2-GP

74.02224.073
1

2
PR4439

10KR2F-2-GP

PR4423 3D3V_S5 DY PWR_CHG_IOUT

SCD1U25V2KX-GP
5 7 1 2
PR4435

ACOK# IOUT AD_IA [24]

100KR2F-L1-GP

59KR2F-GP PR4422 PWR_CHG_CSOP_1

DY 3D3V_AUX_KBC

GND

GND
0R2J-2-GP

SC220P50V2JN-3GP
3D3V_AUX_S5
1

PC4421
2

PR4472

8K45R2F-2-GP
1

DY

1 PR4424
21

14
GAP-CLOSE-PWR-3-GP

1
1PC4422
CHG_AGND 2 1
2

2
BAT_IN# [24,42,43] CHG_AGND PG4411 PWR_CHG_CSON_1

SCD1U25V2KX-GP
DY
1

CHG_AGND

PC4423
DY PC4433
CHECK EE

1
SCD47U6D3V2KX-1-GP
2

EE need check pull high

2
CHG_AGND
PQ4406_G CHG_AGND
1

PQ4414 PWR_CHG_REGN 3D3V_AUX_S5

G

2N7002K-1-GP
84.2N702.031 DY PR4474
1

[4,24,42,46] H_PROCHOT#
DY 100KR2J-1-GP EE need pull high and net name
PR4425 PR4434
2

1 2 PQ4406_D D DY S DY 100KR2J-1-GP 100KR2J-1-GP

3D3V_AUX_S5 PWR_CHG_REGN
PR4465
2

0R2J-2-GP

1
B AD+
Close PR4416 PR4419 B
SCD1U50V3KX-GP

[24] AC_IN# DY PR4428

Customer Request 100KR2J-1-GP 100KR2J-1-GP
1

2N7002KDW-GP
1
100KR2J-1-GP

PR4433

2
DY

2
PC4401

DY120KR2F-L-GP PWR_CHG_ACOK 3 4
1
PR4469

PR4437
2

PWR_CHG_CMPOUT 1 2PQ4008_2 2 5 AC_IN#

2

DY 160KR2F-GP PR4426

BT+_R
15V_S5 1 6 PQ4008_6 1 2

BT+

1
PC4425 H_PROCHOT# [4,24,42,46]
2

DY PR4436 0R0402-PAD

SCD01U50V2KX-1GP
PQ4408

GAP-CLOSE-PWR-3-GP

GAP-CLOSE-PWR-3-GP
120KR2F-L-GP

2
4th = 84.DMN66.03F

2
2

3rd = 75.00601.07C

PG4404

PG4405

2
PR4471 PR4467 2nd = 84.2N702.E3F
E PQ4408_E

0R2J-2-GP DY 1MR2J-1-GP
DY DY DY 84.2N702.A3F

1DCBATOUT_R 1

1
H_PROCHOT# [4,24,42,46]
1

1+VCHGR_R
2

PD4404
PD4403_K

1N4148WS-7-F-GP PR4466
K DY APD4403_A B DY 0R2J-2-GP
PQ4409 DY
LMBT3906LT1G-1-GP 2N7002KDW-GP
C

PQ4408_C PR4448 PR4454

2

PR4475 PQ4405_3 3 4
PR4468 0R2J-2-GP DY 0R2J-2-GP DY 10R2F-L-GP
0R2J-2-GP 1 2 PQ4405_2 2 5 PQ4405_5
DY
2

2
DY DY
1

EC code only BQ24707

PC4434
SC1U25V3KX-1-GP

1 6
1

DY
1

1 2
DY PR4410
PU4401_5

PR4464 PQ4410
2

DY 680KR2J-GP DY PR4476 6D8R2F-GP

H_PROCHOT# AD_IA_HW AD_IA_HW2
DCBATOUT 0R2J-2-GP 4th = 84.DMN66.03F
3rd = 75.00601.07C BATTERY MON 1 DY2
PQ4405_6
2

2nd = 84.2N702.E3F PR4446 PC4424

84.2N702.A3F 45W 0 0
DY BOOST_MON_1 1 DY 2PU4401_6 SCD1U25V2KX-GP
2

1 2
[24] BOOST_MON PR4452 PU4401_4
PWR_CHG_ACOK PR4470
1
PC4427
SC1U25V3KX-1-GP

0R2J-2-GP 20KR2F-L-GP 65W 1 0

DY 100KR2F-L1-GP
DY
1

6
5
4

PR4473
2

PU4407
1

10KR2F-2-GP 90W 0 1
DY
-
+

CHECK EE DY INA199A1-GP

follow customer circuits.

2

1
2
3

A A
3D3V_S5
DCBATOUT
PC4431
SC1U25V3KX-1-GP
1

DY
2

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CHARGER HPA02224
Size Document Number Rev
Custom
Janus HSW 40/50/70 A00
Date: Friday, February 07, 2014 Sheet 44 of 104
5 4 3 2 1
 A B C D E

SSID = PWR.Plane.Regulator_5v3p3v

PWR_5V_VCLK

3D3V_AUX_S5

1
PC4521

1
4 SC1KP50V2KX-1GP PC4514 PC4532 4
DY DY

SCD1U50V3KX-GP

SCD1U50V3KX-GP
DCBATOUT PWR_DCBATOUT_5V

1
DY

2
PR4501
PG4520

BST15V_1

BST15V_2
0R2J-2-GP DY 2 1

GAP-CLOSE-PWR

2
PR4530 PR4504
75.00054.C7D
PG4536

3
2 DY 1 PWR_5V_EN1_R 1 2 PWR_5V_EN1 2 1 2nd = 83.00054.Y81 2nd = 83.00054.Y81
PD4503 PD4502
GAP-CLOSE-PWR 3rd = 83.BAT54.P81 BAT54SPT-1-GP BAT54SPT-1-GP 3rd = 83.BAT54.P81
0R2J-2-GP

2
0R0402-PAD PG4518
PR4507 2 1 75.00054.C7D DY DY

2
DCBATOUT PWR_DCBATOUT_3D3V 0R0402-PAD GAP-CLOSE-PWR 5V_PWR
PG4534 PG4530 15V_S5
GAP-CLOSE-PWR-3-GP

1
PG4525 PR4506 2 1
2 1
1 2 PWR_3D3V_EN2 GAP-CLOSE-PWR BOOST_10V 15V_PWR
[36] 3V_5V_EN 2 1
GAP-CLOSE-PWR 0R0402-PAD PG4542
PG4521 2 1

K
1

1
2 1 PC4515 PC4534 PC4533
DY DY

SCD1U50V3KX-GP

SCD1U50V3KX-GP
GAP-CLOSE-PWR SC1U25V3KX-1-GP PD4501
GAP-CLOSE-PWR PG4543
DY BZT52C15S-GP
DY

2
PG4524 2 1
2 1

A
GAP-CLOSE-PWR
GAP-CLOSE-PWR
PG4531
2 1
DCBATOUT
GAP-CLOSE-PWR

PWR_DCBATOUT_3D3V

PC4528 PC4509
PC4525 PC4519 PC4531
SC4D7U25V5KX-GP
1

1
SC10U25V5KX-GP

SC10U25V5KX-GP
PWR_DCBATOUT_5V

1
SCD1U50V3KX-GP

SCD01U50V2KX-1GP
DY
Design Current=3.3A DY
2

3 3

2
5.17A<OCP>6.11A PC4530 PC4529 PC4527
8
7
6
5

5
6
7
8

1
SIS412DN-T1-GE3-GP

SIS412DN-T1-GE3-GP

SCD1U50V3KX-GP

SC4D7U25V5KX-GP

SC10U25V5KX-GP
D
D
D
D
5V_S5
D
D
D
D

PU4504 PU4501 5V_PWR

12
84.00412.037 PG4527

2
PU4503 65BOM charger 2 1
65BOM charger

VIN
PC4535 PR4528
Design Current=8.65A GAP-CLOSE-PWR

G
S
S
S
2 1PWR_3D3V_VBST2_11 2 PWR_3D3V_VBST2 PC4516 PG4519
1 S
2 S
3 S
4 G

3D3V_S5 3D3V_PWR 1D5R3-GP PR4524 12.98A<OCP>15.34A 2 1

4
3
2
1
PG4526 9 17 PWR_5V_VBST1 1 2 PWR_5V_VBST1_1 1 2
SCD1U50V3KX-GP VBST2 VBST1 GAP-CLOSE-PWR
2 1 1D5R3-GP
3D3V_PWR 68.3R310.20A PWR_3D3V_DRVH2 10 16 PWR_5V_DRVH1 SCD1U50V3KX-GP 68.2R210.20B 5V_PWR PG4538
GAP-CLOSE-PWR PL4502 DRVH2 DRVH1 PL4501 2 1
PG4517 1 2 PWR_3D3V_LL2 8 18 PWR_5V_LL1 1 2
IND-3D3UH-57GP SW2 SW1 GAP-CLOSE-PWR
2 1
1

PWR_3D3V_DRVL2 11 15 PWR_5V_DRVL1 IND-2D2UH-46-GP-U PG4537

1
GAP-CLOSE-PWR DRVL2 DRVL1
2 1

5
6
7
8
PG4528 PR4533 DY PU4502 PR4529 PG4532 PC4518
8
7
6
5

D
D
D
D

SIS780DN-T1-GE3-GP
PC4517 PT4502 PG4535 2D2R5F-2-GP PWR_5V_VO1 2D2R5F-2-GP GAP-CLOSE-PWR
2 1 14 DY
1

1
VO1

GAP-CLOSE-PWR-3-GP
D
D
D
D

PG4533

SCD1U16V2KX-3GP
2
1

SE220U6D3VM-38-GP

GAP-CLOSE-PWR-3-GP

GAP-CLOSE-PWR PU4505 PWR_3D3V_FB2 4 2 PWR_5V_FB1 DY PT4501 2 1

SCD1U16V2KX-3GP

2
VFB2 VFB1
PG4522 DY 65BOM chargerSIS412DN-T1-GE3-GP 65BOM charger
1PWR_3D3V_SNUB

SE220U6D3VM-38-GP
2

2
G
2 1 4 79.22710.3KLGAP-CLOSE-PWR
2

2
S
S
S
84.00412.037 PG4523

1PWR_5V_SNUB
GAP-CLOSE-PWR PWR_3D3V_EN2 PWR_5V_EN1
S
S
S
G

6 20 2 1

3
2
1
EN2 EN1
PG4529
1
2
3
4

2 1 GAP-CLOSE-PWR
3V_FEEDBACK

PWR_3D3V_CS2 5 1 PWR_5V_CS1 PG4541

GAP-CLOSE-PWR CS2 CS1
2 1
1

1
TPS51225RUKR-GP
79.22710.3KL DY PR4517 19 PWR_5V_VCLK PR4531 GAP-CLOSE-PWR
PC4520 73K2R2F-GP VCLK 137KR2F-1-GP PC4536
DY PG4540
2

SC330P50V3KX-GP SC560P50V-GP
74.51225.073 2 1

2
PT4501 and PT4502 manually change to 77.52271.06L 7 21
2

2
PGOOD GND GAP-CLOSE-PWR
VREG3

VREG5
PG4545
2 1
1

1
GAP-CLOSE-PWR
3

13

2 PR4512 PR4535 3D3V_S5 5V_PWR_2 PR4525 PG4544 2

1
6K8R2F-2-GP 3D3V_PWR_2
DY0R2J-2-GP 0R2J-2-GP DY 2 1
PR4527
1

15K4R2F-GP GAP-CLOSE-PWR
PWR_5V_FB1_R
2

1 2

1 2
PWR_3D3V_FB2_R PR4534
PC4523 DY 100KR2J-1-GP

2
1

DYSC18P50V2JN-1-GP PC4524 PC4522 DY

PC4526 SC1U6D3V3KX-2GP SC18P50V2JN-1-GP
2

2
SC4D7U6D3V3KX-GP
2

2
1

1
PR4523 [17] 3V_5V_POK PR4526
10KR2F-2-GP 9K76R2F-1-GP

Close to VFB Pin (pin2)

2

2
3D3V_PWR_2 3D3V_AUX_S5
PR4532
1 2
Close to VFB Pin (pin5)
0R0402-PAD

TPS51225 & TPS51285 Co-lay

I/P cap: CHIP CAP C 10U 25V K0805 X5R/ 78.10622.51L I/P cap: CHIP CAP C 10U 25V K0805 X5R/ 78.10622.51L
Inductor: CHIP IND 3.3UH PCMC063T-3R3MN Cyntec 28mohm/30mohm Isat =13.5Arms 68.3R310.20A Inductor: CHIP CHOKE 2.2U PCMC063T-2R2MN 18mohm/20mohm Isat =14Arms 68.2R210.20B
O/P cap:CHIP CAP POL 220U 6.3V M 6.3*4.5 /Matsuki/ 17mOhm / 77.52271.09L TPS51225 TPS51285 O/P cap:CHIP CAP POL 220U 6.3V M 6.3*4.5 /Matsuki/ 17mOhm / 77.52271.09L
H/S:SIS412 / 24mOhm/30mOhm@4.5Vgs / 84.00412.037 H/S:SIS412 / 24mOhm/30mOhm@4.5Vgs / 84.00412.037
L/S:SIS780 / 14.5mOhm/17.5mOhm@4.5Vgs / 84.00780.037 PR4510 45.3KK 9.09K L/S:SIS780 / 14.5mOhm/17.5mOhm@4.5Vgs / 84.00780.037
1 1
PR4511 110K 22.1K

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

3V/5V TPS51225
Size Document Number Rev
A2
Janus HSW 40/50/70 A00
Date: Friday, February 07, 2014 Sheet 45 of 104
A B C D E
 5 4 3 2 1

SSID = CPU.Regulator

PR4614
1 2PW R_VCC_PRGM1

90K9R2F-GP
15W/28W
D D
PR4630 PR4607
1D05S_VCCST 2 1 PW R_VCC_SDA 1 2PW R_VCC_PRGM2

130R2F-1-GP 124KR2F-GP
PR4620
2 1 PW R_VCC_SCLK 2 PR4619 1 0R0402-PAD PW R_VCC_SDA
[7] H_CPU_SVIDDAT
54D9R2F-L1-GP

PR4601
1 2 PW R_VCC_ALERT# 2 PR4618 1 0R0402-PAD PW R_VCC_ALERT#
[7] VR_SVID_ALERT#
DY
75R2F-2-GP
1

PC4606 2 PR4616 1 0R0402-PAD PW R_VCC_SCLK

SCD1U16V2KX-3GP [7] H_CPU_SVIDCLK
2

5V_S0

20

19

18

11

17
PC4604 PU4601

1
SC1U10V3KX-3GP

ALERT#

PRGM2

PRGM1
SCLK

SDA
2
12 13 PW R_VCC_BOOT PW R_VCC_BOOT [47]
C VCC BOOT C

2 PR4621 1 0R0402-PAD PW R_VCC_EN 1 VR_ON UG 14 PW R_VCC_UG PW R_VCC_UG [47]

[7] H_VR_ENABLE

PR4610 100KR2F-L1-GP
1 2 PW R_VCC_IMON 3 15 PW R_VCC_PHASE PW R_VCC_PHASE [47]
IMON PHASE
ISL95813HRZ-GP
1 2
PW R_VCC_VRHOT# 4 74.95813.B73 16 PW R_VCC_LG PW R_VCC_LG [47]
PR4602 PC4609 SC1KP50V2KX-1GP VRHOT# LG
1 2 499R2F-2-GP
1D05V_S0 DY PR4624 PR4603 LL=2mohm
[4,24,42,44] H_PROCHOT# 2 1 0R0402-PAD PW R_VCC_COMP 6 COMP FB 7 PW R_VCC_FB 1 2 VCC_SENSE [7]
PC4611
PR4613 15W/28W
1K27R2F-L-GP
2 1 PW R_VCC_COMP_RC 2 1
PC4613
SC6800P50V3KX-GP 21 PR4606 PC4601
5K1R2F-2-GP GND

PGOOD
PC4610 1 2 PW R_VCC_FB_RC 1 2 2 1
DY

ISUMN

ISUMP
2 1 DY

NTC

RTN
DY 0R2J-2-GP
SCD1U16V2KX-3GP SC1KP50V2KX-1GP
R4622 SCD1U16V2KX-3GP

10
2KR2F-3-GP
3D3V_S0 1 2
B PR4628 B

[7,24] IMVP_PW RGD 2 1 0R0402-PAD PW R_VCC_POK PW R_VCC_ISUMP

PW R_VCC_ISUMP [47]

PR4617
PR4615
2 1 PW R_VCC_NTC_R 1 2 PW R_VCC_NTC
PW R_VCC_ISUMN
3K83R2F-GP PW R_VCC_ISUMN [47]
16KR2F-GP
PR4622
PR4604
2 1 2 1 VSS_SENSE [9]
NTC-470K-5-GP-U 10R2F-L-GP
B=4500K PC4612
close to H/S MOSFET 2 1

PR4622 manually change to 69.60037.001 SC1KP50V2KX-1GP

PR4603 PR4614

1.27K 90.9K
15W 64.12715.6DL
<Core Design>
A
64.90925.6DL A

1.58K 113K Wistron Corporation

28W 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
64.15815.6DL 64.11335.6DL Taipei Hsien 221, Taiwan, R.O.C.

Title
ISL95813_CPUCORE(1/2)
Size Document Number Rev
A3 Janus HSW 40/50/70 A00
Date: Friday, February 07, 2014 Sheet 46 of 104
5 4 3 2 1
 5 4 3 2 1

DCBATOUT PW R_DCBATOUT_VCCCORE
PW R_DCBATOUT_VCCCORE
DCBATOUT PG4703
1 2

GAP-CLOSE-PW R

1
PT4702 PG4708
PC4704

SE33U25VM-10-GP
DY

1
PU4701 manually change to 084.06970.0037. PC4701 PC4702 PC4703 1 2

SCD1U50V3KX-GP

2
GAP-CLOSE-PW R

SC10U25V5KX-GP

SC10U25V5KX-GP

SC10U25V5KX-GP
PG4704

2
PU4701
1 2
D 2 D
[46] PW R_VCC_UG 3 GAP-CLOSE-PW R
PR4701 PC4706 1 4 PG4707
0R3J-0-U-GP 10
PW R_VCC_BOOT_RC 1 2
1 2 1 2 9
[46] PW R_VCC_BOOT
SCD22U25V3KX-GP
7 For acoustic noice GAP-CLOSE-PW R
8 6 PG4705
5
1 2
[46] PW R_VCC_LG
GAP-CLOSE-PW R
FDMS3600-02-RJK0215-COLAY-GP
PG4706
ZZ.00215.037 1 2
1st = 084.06970.0037 VCC_CORE
GAP-CLOSE-PW R

PW R_VCC_PHASE
2nd = 84.08S36.037 PL4701 1 2 IND-D22UH-9-GP-U
[46] PW R_VCC_PHASE Shark Bay ULT 15W CPU
68.R2210.10C IccMAX=32A

2
PG4701 PG4702 TDC=10A
GAP-CLOSE-PW R-3-GP GAP-CLOSE-PW R-3-GP
35.2A<OCP<41.6A

1
Frequency=750KHZ
LL=-2.0 mV/A

PHASE1G

ISUM_R_C
1
C C
PR4702
3K65R2F-1-GP
close to CHOKE

2
PR4704
PR4703
1 2 PHASE_R_R 1 2

4K42R2F-GP NTC-10K-26-GP-U

1
PR4707 B=3370K

1
PC4710
10MR2F-GP PR4708 SCD1U25V2KX-GP

2
1 2

2
11KR2F-L-GP PR4705 (Cyntec) OCP
PC4707
1 2 15W 357 ohm (64.35705.6DL) 38A
PR4705
SCD047U25V2KX-GP
PC4708 28W 412 ohm (64.41205.6DL) 48A
15W/28W
1 2 SCD1U16V2KX-3GP 1 2 PW R_VCC_ISUMN [46]
357R2F-GP
PR4705 (Maglayers)
PC4709 PR4706 383 ohm (64.38305.6DL) 38A
1 2 ISUM_R_R 1 2 15W
DY
DY
B SCD1U16V2KX-3GP 0R2J-2-GP B
28W 464 ohm (64.46405.6DL) 48A

PW R_VCC_ISUMP [46]
Change PC4723 to 10U from 22U based on PI Simulation.

22uF/6.3V/0805*13 VCC_CORE
VCC_CORE
330uF/2.5V/6.3*4.5/12mohm*1
1

1
PC4725 PC4726 PC4729 PC4730 PC4731 PC4732 PC4733 PC4734 PC4736 PC4741 PC4721 PC4722 PC4724 PC4727 PC4728 PC4735 PC4737 PC4738 PC4739 PC4740 PC4742 PC4743
SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP
PC4723 EC4701
DY DY DY DY DY DY DY DY
SC10U10V5KX-2GP

SCD1U25V2KX-GP
2

2
A <Core Design> A
Stuff PC4727, PC4737 for 28W.
1

PT4701 PC4717 PC4718 PC4719 PC4720 PC4744

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SE330U2D5VM-8-GP
DY Wistron Corporation
2

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Change to 79.3371V.6CL Title

ISL95813_CPUCORE(2/2)
Size Document Number Rev
A3 Janus HSW 40/50/70 A00
Date: Friday, February 07, 2014 Sheet 47 of 104
5 4 3 2 1
 5 4 3 2 1

SSID = PWR.Plane.Regulator_1p05v

D
DCBATOUT PW R_DCBATOUT_1D05V D

PG4838
2 1
PW R_DCBATOUT_1D05V
GAP-CLOSE-PW R
PG4837
2 1

SC4D7U25V5KX-GP
PC4825
1D05V_PW R 1D05V_S0

SC10U25V5KX-GP

PC4814
GAP-CLOSE-PW R

PC4826

SCD1U50V3KX-GP
PG4834

1
2 1 PG4828
DY 2 1

5
6
7
8
SIS412DN-T1-GE3-GP
GAP-CLOSE-PW R

2
D
D
D
D
PU4808 PG4827 GAP-CLOSE-PW R
2 1 PG4830
0R0402-PAD 84.00412.037 2 1
[7,36] 1D05V_VTT_PW RGD 2 PR4821 1 65BOM charger GAP-CLOSE-PW R
GAP-CLOSE-PW R

G
S
S
S
PG4831
Design Current =4.43A 2 1

4
3
2
1
PR4817 SCD1U50V3KX-GP
1 2 PU4806 PR4820 6.645A<OCP<7.97A GAP-CLOSE-PW R
PC4822
105KR2F-1-GP PW R_1D05V_PW RGD 1 11 2D2R3-1-U-GP PG4826
PW R_1D05V_TRIP PGOOD GND PW R_1D05V_BOOT 1 1D05V_PW R
(current limit ~ 7.3A) 2 CS BOOT 10 2PW R_1D05V_BOOT_R 2 1 68.2R210.20B 2 1
PW R_1D05V_EN 3 9 PW R_1D05V_UGATE PL4801
PW R_1D05V_FB EN UGATE PW R_1D05V_PHASE
4 FB PHASE 8 1 2 GAP-CLOSE-PW R
PR4819 PW R_1D05V_CCM 5 7 5V_S5 IND-2D2UH-46-GP-U PG4824
RF VCC

1
[17,24,36,49,51] PM_SLP_S3# 0R0402-PAD 1 2 6 PW R_1D05V_LGATE PC4824
LGATE PT4803 2 1
1

GAP-CLOSE-PWR-3-GP
C PR4837 C

SE330U2D5VM-14-GP
PC4815 2D2R5F-2-GP
DY 79.3371V.6CL

SCD1U16V2KX-3GP
GAP-CLOSE-PW R
1

2
PR4824 RT8237CZQW -2-GP SC1U10V2KX-1GP
PC4821
SC1KP50V2KX-1GP

PG4825

5
6
7
8

SIS412DN-T1-GE3-GP

PG4832
DY 470KR2F-GP
2 1

1PWR_1D05V_SNUB 2

2
D
D
D
D
PU4805
74.08237.B73
2

84.00412.037 GAP-CLOSE-PW R

1
65BOM charger

G
S
S
S
PW R_1D05V_PW R

4
3
2
1

1
DY PC4838

1
SC560P50V-GP PR4822

2
10KR2F-2-GP DY PC4823
SC18P50V2JN-1-GP

2
2
PW R_1D05V_FB
I/P cap: CHIP CAP C 10U 25V K0805 X5R/ 78.10622.51L
Inductor: CHIP CHOKE 2.2U PCMC063T-2R2MN 18~20mohm Isat =14Arms 68.2R210.20B
O/P cap: CHIP CAP POL 330U 2.5V M 6.3*4.5 2.3Arms Matsuti/77.53371.18L Vout=0.704V*(R1+R2)/R2

1
B H/S:SIS412DN-T1-GE3 / 24mOhm/30mOhm@4.5Vgs / 84.00412.037 PR4823 B

L/S:SIS780DN-T1-GE3 / 14.5mOhm/17.5mOhm@4.5Vgs / 84.00780.037 21KR2F-GP

2
<Core Design>
A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
RT8237_1D05V
Size Document Number Rev
A3 Janus HSW 40/50/70 A00
Date: Friday, February 07, 2014 Sheet 48 of 104

5 4 3 2 1
 5 4 3 2 1

SSID = PWR.Plane.Regulator_1p35v0p675v

DCBATOUT +PWR_SRC_1D35V
PG4903
D D
2 1

GAP-CLOSE-PWR
PG4904
2 1

GAP-CLOSE-PWR
PG4905 1D35V_PWR 1D35V_S3
2 1 +PWR_SRC_1D35V
GAP-CLOSE-PWR
5V_S5 PG4908
PG4906
2 1
2 1
PC4912

SC1U10V3KX-3GP
PC4909 PC4911 PC4914 GAP-CLOSE-PWR
GAP-CLOSE-PWR

SC10U25V5KX-GP
PG4909

2
SC4D7U25V5KX-GP

SC4D7U25V5KX-GP
1

1
PC4901

SC4D7U25V5KX-GP
3D3V_S0 PC4913 2 1
DY

1
SCD1U50V3KX-GP

1
GAP-CLOSE-PWR

2
PG4910

2
1

2 1
PR4904
DY GAP-CLOSE-PWR

5
6
7
8

SIS412DN-T1-GE3-GP
20KR2F-L-GP PR4605_2
PG4911

D
D
D
D
PU4902 84.00412.037
PU4901 2 1
2

20 12 PC4919 65BOM charger

[36] 1D35V_VTT_PWRGD PGOOD V5IN GAP-CLOSE-PWR
SCD1U50V3KX-GP
Design Current=8.65A PG4912
R4909 2 10R0402-PAD DDR_VTT_PG_CTRL_R 17 PR4905
[12] DDR_VTT_PG_CTRL S3 2 1

G
S
S
S
15 PWR_1D35V_VBST 1 2 1 2 12.97A<OCP>15.57A
R4910 2 VBST
1 0R2J-2-GP PWR_1D35V_EN 16 GAP-CLOSE-PWR

4
3
2
1
[17,24,36,48,51] PM_SLP_S3# S5 2D2R3-1-U-GP
DY PWR_1D35V_VREF 6 14 PWR_1D35V_DRVH
PG4913
VREF DRVH
1

1D35V_PWR 2 1
PL4902
PR4903
GAP-CLOSE-PWR
10KR2F-2-GP 13 PWR_1D35V_SW 1 2
SW PG4914
COIL-D68UH-5-GP 2 1
2

5
6
7
8

PC4921
C PWR_1D35V_REFIN 8 11 PWR_1D35V_DRVL PU4903 68.R6810.20B C
30K1R2F-L-GP

SC4D7U6D3V3KX-GP
GAP-CLOSE-PWR

1
D
D
D
D
REFIN DRVL

SIS780DN-T1-GE3-GP

2
84.00780.037

GAP-CLOSE-PWR-3-GP
PG4915

1
PC4923 PC4924 PC4925 PC4926
PC4903

PC4902

DY

PC4920
10

PG4907
1

PGND 2 1

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP
PWR_1D35V_MODE 19 65BOM charger PR4912 DY DY EC4601
DY
1

MODE 2D2R5F-2-GP SCD1U50V3KX-GP

2 PR4901

GAP-CLOSE-PWR

2
1
G
4
1KR2F-3-GP

2
PG4916
2

SCD1U16V2KX-3GP
S
S
S
PWR_1D35V_TRIP 18 9 PWR_1D35V_VDDQS
SCD1U16V2KX-3GP
2

133KR2F-GP

TRIP VDDQSNS 2 1

PWR_1D35V_VDDQS
PR4902
PR4908
SCD01U50V2KX-1GP

3
2
1
1

TPS51216_PHS_SET
PR4601_1

2 GAP-CLOSE-PWR
PWR_1D35V_VTTREF5 VLDOIN +0D675V_DDR_P

PC4915
VTTREF PG4917
1

1
0R0402-PAD

SC10U6D3V3MX-GP
1

VTT 2 1
PR4906

PC4918 PC4922
DY

SC10U6D3V3MX-GP
1

1
SCD22U10V2KX-1GP SC330P50V2KX-3GP

PC4916

PC4917
1 GAP-CLOSE-PWR
2

2
VTTSNS
21 DY
SCD1U16V2KX-3GP
PG4918
2

GND
4
2

2
VTTGND 2 1
7
GND
GAP-CLOSE-PWR
TPS51716RUKR-GP
PG4919
74.51716.073 1D35V_PWR 2 1

SC1U10V3KX-3GP
GAP-CLOSE-PWR

PC4904
PG4920

1
+0D675V_DDR_P 0D675V_S0
PG4901 2 1
2 1 DDR_VREF_S3 1 PR4907 2 PWR_1D35V_EN
PR4911 GAP-CLOSE-PWR

2
[17,24] PM_SLP_S4#
GAP-CLOSE-PWR PWR_1D35V_VTTREF 1 2 0R0402-PAD PC4906

1
PG4902 DY
2 1

SCD1U16V2KX-3GP
0R0603-PAD-1-GP-U

2
GAP-CLOSE-PWR

B B

State S3 S5 VDDR VTTREF VTT I/P cap: 10U 25V K0805 X5R/ 78.10622.51L
Inductor: CHIP IND 0.1UH M PCMC063T-R10MN 1.5~1.7mohm Isat =60Arms 68.R1010.10T
S0 Hi Hi On On On
O/P cap: CHIP CAP POL 330U 2.5V M 6.3*4.5 2.3Arms Matsuti/77.53371.18L
S3 Lo Hi On On Off(Hi-Z) MOS: FET MOS FDMS3664S NC POWER56 / 84.03664.037 / Q1: 8.5~11mohm @Vgs=4.5V Q2: 2.6~3.2mohm @Vgs=4.5V
S4/S5 Lo Lo Off Off Off

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
TPS51716_1D35V_S3
Size Document Number Rev
C Janus HSW 40/50/70 A00
Date: Monday, February 10, 2014 Sheet 49 of 104
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
Janus HSW 40/50/70 A00
Date: Friday, February 07, 2014 Sheet 50 of 104
5 4 3 2 1
 5 4 3 2 1

SSID = PWR.Plane.Regulator_1p5v

3D3V_S5
TLV70215 for 1D5V_S0

D D

SC1U10V2KX-1GP
PC5119
2
Design Current = 150mA

PU5101 1D5V_PW R 1D5V_S0

PG5105
1 IN OUT 5 1 2
2 GND
[17,24,36,48,49] PM_SLP_S3# 1 2PW R_1D5V_EN 3 EN NC#4 4 GAP-CLOSE-PW R

PR5110

PC5120
SC1U10V2KX-1GP
0R0402-PAD TLV70215DBVR-GP
74.70215.03F

2
C C

DCBATOUT PW R_DCBATOUT_VRAM_PW R

1
PG5101
2

GAP-CLOSE-PW R
PW R_DCBATOUT_VRAM_PW R SY8208D for 1D35V_VGA_S0(1D5V)
PG5102
1 2 PC5115 PC5113
1

1
SC4D7U25V5KX-GP

SC4D7U25V5KX-GP

GAP-CLOSE-PW R 1D5V_VGA_S0 1D5V_VGA_S0 Design Current=3.4A

PR5102 PC5110
PG5103 PU5102 1D5V_VGA_S0 OCP=8A
2

1 2 1 2 VRAM_PW R_BS_R 1 2

GAP-CLOSE-PW R
1D5V_VGA_S0
1D5V_VGA_S0 0R3J-0-U-GP SCD1U50V3KX-GP

8 6 VRAM_PW R_BS
IN BS 1D35V_VGA_S0
B B
TP5101 1 PL5101 1D5V_VGA_S0 1D5V_VGA_S0
10 VRAM_PW R_PH 1 2
LX

GAP-CLOSE-PWR-3-GP
1D5V_VGA_S0
IND-1UH-206-GP

1
1D5V_VGA_S0 PU5102_PG 2 4 VRAM_PW R_FB PC5101 PC5108 PC5116 PC5117 PC5118
PG FB PC5114
1D5V_VGA_S0 DY DY

2
PR5111 2 1 PW R_VRAM_PW R_ILIM 3 7 VRAM_PW R_BYP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP
SCD1U50V3KX-GP

2
470KR2F-GP ILMT BYP 3D3V_S5 PG5104
2 PR5114 1 PW R_VRAM_PW R_EN 1
PR5112 1D5V_VGA_S0
[83] 1D35V_VGA_EN EN
0R2J-2-GP 2 1

1
1D5V_VGA_S0 9 5 VRAM_PW R_LDO 0R2J-2-GP
GND LDO
1

1D5V_VGA_S0

1
Check GPU power sequence. PR5104
1MR2J-1-GP SY8208DQNC-GP-U PC5109 VRAM_PW R_FBH
DY 1D5V_VGA_S0
1

SC1U10V2KX-1GP
PC5112

2
74.08208.K73
2

SC2D2U6D3V2MX-GP

1D5V_VGA_S0
2

1
PR5113

1
150KR2F-L-GP
1D5V_VGA_S0 PC5111
SC220P50V2KX-3GP

2
1D5V_VGA_S0

Vo=0.6x(1+R1/R2)
1D5V_VGA_S0: for DDR3 VRAM only =0.6x(1+150/100)
1
A <Core Design> A
PR5103
=1.5V 100KR2F-L1-GP
1D5V_VGA_S0 Wistron Corporation
2

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Title
TLV70215_1D5V / SY8208D_1D5V(VGA)
Size Document Number Rev
A3 Janus HSW 40/50/70 A00
Date: Friday, February 07, 2014 Sheet 51 of 104
5 4 3 2 1
 5 4 3 2 1

CAM1 EE note: Never change R5229 to short pad after MP

LCDVDD_LCD
INVERTER POWER Reserved for one time fuse: 69.43001.201
LCDVDD
LCD1 3D3V_S0 3D3V_CAMERA_S0
41 R5211 DCBATOUT DCBATOUT_LCD
1 2 0R5J-5-GP R5229
1
EE note: Never change R5211 to short pad after MP F5201 800mA 1 2
2 LCDVDD_LCD 1 2
DCBATOUT_LCD
3 0R3J-0-U-GP

1
4 Trace width = 80mil C5202

1
C5201

SC1KP50V2KX-1GP
5 POLYSW-1D1A24V-2-GP C5205 EC5210 DY C5207

2
DBC_EN_R 1 R5224 SC4D7U6D3V3KX-GP
6 2 DY

SC33P50V2JN-3GP

2
C5206 DBC_EN [20]
7
69.60040.001

2
8 DBC_EN_R SC1U10V2KX-1GP 0R0402-PAD SCD1U50V3KX-GP

1
SCD1U16V2KX-3GP
9 EDP_HPD_CONN
10 LCD_TST_C
D 11 EDP_AUX CCD1 3D3V_CAMERA_S0 D
EDP_AUX#
12
13
LCD 9
14 EDP_TX0# 3D3V_S0 1
EDP_TX0

Notice:20.F2191.008
15
16 DY 2
17 EDP_TX1# TP_RS 1 R5205 2 TOUCH_PANEL_INTR# [24] 3 DMIC_CLK_C 1 2

1
EDP_TX1 DMIC_DATA_C R5207 0R2J-2-GP
18 4 DY

1
0R0402-PAD For ESD R5208
19
20 LCD_BRIGHTNESS DY C5208 10KR2J-3-GP
5
6 USB_CAMERA#
CAM1_MIC_GND
21 BLON_OUT_C SC10P50V2JN-4GP 7 USB_CAMERA

2
22 PANEL_SIZE_ID_CONN 8

2
R5210
23 10 CAM1_MIC_GND
24 PANEL_SIZE_ID_CONN 1 2 PANEL_SIZE_ID
PANEL_SIZE_ID [20]
25
26 TP_RESET 1 R5212 2 100R2J-2-GP For AUDIO Grade B or C selection.
MIC_GND PLT_RST# [17,24,30,36,58,65,73,96]

1
27 DMIC_CLK_EDP DM-ACES-CON8-44-GP-01

1
28 DMIC_DATA_EDP 0R0402-PAD R5209 ZZ.F2191.00801
DY C5214 DY
29
30 USB_CAMERA_EDP# Camera SC10P50V2JN-4GP
0R2J-2-GP
TR5208

2
31 USB_CAMERA_EDP RN5205

2
32 USB_CAMERA# 3 4 USB_PN4_CAM# 2 3 USB_PN4 [16]
3D3V_CAMERA_S0 RN5202
USB_PN6_TPNL 1 R5203
33
USB_PN6_TPNL
2 USB_PN6 [16]
DMIC_CLK_C USB_CAMERA
69.10103.041 DY USB_PP4_CAM
1 DY 4 USB_PP4 [16]
34 1 4 DMIC_CLK [27] 2 1
USB_PP6_TPNL 0R0402-PAD DMIC_DATA_C SRN0J-6-GP
35 2 DY 3 DMIC_DATA [27]
FILTER-4P-6-GP
36
TP_RS EC5205 EC5206
37
Touch Panel

1
TP_RESET SRN33J-5-GP-U
38
39 DY DY
40 TPAN_VDD RN5204
CAM_EDP

2
SC6D8P50V2DN-GP

SC6D8P50V2DN-GP
DMIC_CLK_EDP 2 3
DMIC_DATA_EDP TR5209
42 1CAM_EDP 4 RN5206
1 R5201 2 USB_CAMERA_EDP# 3 4 USB_PN4_EDP 1 4 USB_PN4 [16]
USB_PP6_TPNL 1 R5204 2 USB_PP6 [16] SRN33J-5-GP-U 69.10103.041 CAM_EDP 2 3 USB_PP4 [16]
0R0402-PAD USB_CAMERA_EDP 2 1 USB_PP4_EDP
ACES-CON40-18-GP 0R0402-PAD SRN0J-6-GP
RN5203 FILTER-4P-6-GP
1 8 BKLT_CTRL
20.K0678.040 MIC_GND 2 7 BLON_OUT_C
3 6 EDP_HPD Layout Note: Reduce the stubs.
4 5
C R5222 1 DY 2 0R2J-2-GP C

LCD_BRIGHTNESS 1 AFTP5203 SRN100KJ-5-GP Layout Note: Reduce the stubs.

BLON_OUT_C 1 AFTP5205
D5202
LCD_TST_C 1 AFTP5207
EDP_AUX 1 AFTP5206 RN5201 1 eDP_BKLT_CTRL
EDP_AUX#
EDP_TX0#
1
1
AFTP5208
AFTP5213
LCD_TST_C
LCD_BRIGHTNESS
1
2
8
7 BKLT_CTRL LCD_TST [24]
3
LCDVDD
EDP_TX0 1 AFTP5210 BLON_OUT_C 3 6 BLON_OUT [24]
EDP_TX1# 1 AFTP5211 4 5 2 EC_BRIGHTNESS [24]
EDP_TX1 1 AFTP5212
DMIC_CLK_C 1 AFTP5222 SRN100J-4-GP
DMIC_DATA_C 1 AFTP5228 BAT54C-7-F-3-GP EC (BIST MODE)
USB_CAMERA# 1 AFTP5225 75.00054.E7D
USB_CAMERA 1 AFTP5226 EDP_HPD_CONN 100R2J-2-GP 1 2 R5233 2nd = 83.R2003.W81
EDP_HPD [15]
3D3V_CAMERA_S0 1 AFTP5227 3rd = 75.00054.A7D
EDP_HPD_CONN AFTP5201 3D3V_S0 5V_S0 4th = 83.R2003.V81
1 D5201
LCDVDD_LCD 1 AFTP5202
DCBATOUT_LCD 1 AFTP5204 TPAN_VDD 1
[15] EDP_VDD_EN

1
TP_RS 1 AFTP5209

R5231
0R3J-0-U-GP
R5230 3 LCDVDD_EN
TP_RESET 1 AFTP5214 DY 0R0603-PAD-1-GP-U
[24] LCD_TST_EN 2

2
3D3V_S0

2
C5203 1 2 SCD1U16V2KX-3GP EDP_TX0# 69.60040.001 R5202
[8] EDP_TX0_DN BAT54C-7-F-3-GP
[8] EDP_TX0_DP C5210 1 2 SCD1U16V2KX-3GP EDP_TX0 F5203 100KR2J-1-GP
TPAN_VDD_F 1 2 POLYSW-1D1A24V-2-GP 75.00054.E7D U5201
DY 2nd = 83.R2003.W81 LCDVDD

1
1 5
C5211 EDP_TX1# EN VIN#5
[8] EDP_TX1_DN 1 2 SCD1U16V2KX-3GP R5232 2 1 0R3J-0-U-GP 3rd = 75.00054.A7D 2
C5213 EDP_TX1 GND
[8] EDP_TX1_DP 1 2 SCD1U16V2KX-3GP 3 4
VOUT VIN#4

1
EE note: Never change R5232 to short pad after MP 4th = 83.R2003.V81 C5204
RT9724GB-GP SC4D7U6D3V3KX-GP
C5209 1 2 SCD1U16V2KX-3GP EDP_AUX# Reserved for one time fuse: 69.43001.201
[8] EDP_AUX_DN

2
C5212 1 2 SCD1U16V2KX-3GP EDP_AUX
[8] EDP_AUX_DP Layout Note: 74.09724.09F
Brightness Trace width = 80mil
R5206
1 2 eDP_BKLT_CTRL
B [15] L_BKLT_CTRL 0R0402-PAD B

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
LCD/Inverter CONN
Size Document Number Rev
A2
Janus HSW 40/50/70 A00
Date: Monday, February 10, 2014 Sheet 52 of 104
5 4 3 2 1
 5 4 3 2 1

D D

(Blanking)
C C

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

(Reserved)
Size Document Number Rev
A3
Janus HSW 40/50/70 A00
Date: Friday, February 07, 2014 Sheet 53 of 104
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

HDMI Level Shifter/Connector

Size Document Number Rev
A3 X02
Janus HSW 40/50/70
Date: Friday, February 07, 2014 Sheet 54 of 104
5 4 3 2 1
 5 4 3 2 1

CRT Board Connector

5V_CRT_S0_R
5V_CRT_S0
CRT1
SCD01U16V2KX-L1-GP C5519

14

13
2DY 1 9 4
VCC_CRT NC#4 U5501D
11
NC#11
CRT_DDCDATA_CON 12 12 DY 11
DDCDATA_ID1
CRT RGB
CRT_DDCCLK_CON 15 5V_CRT_S0_R 5V_CRT_S0 5V_S0
DDCCLK_ID3
D 5 D5501 D
GND
CRT H/VSYNC
CRT_R 1 6 F5501 TC74VHCT125AFTQK2M-GP

7
CRT_G CRT_RED GND
2 7 1 2 K A
CRT_GREEN GND
CRT SMBUS
CRT_B 3 8
CRT_BLUE GND
10
CRT_VSYNC_CON GND POLYSW-1D1A6V-9-GP-U RB551V30-GP
14 16
CRT_HSYNC_CON VSYNC GND
13
HSYNC GND
17 83.R5003.H8H
D-SUB 15P
69.48001.081 5V_CRT_S0
D-SUB-15-252-GP
2ND = 69.50011.081
3RD = 69.50013.101

14

10
020.20020.0015 U5501C

5V_CRT_S0
9 DY 8

CRT_DDCDATA_CON Hsync & Vsync level shift

CRT_HSYNC_CON TC74VHCT125AFTQK2M-GP

7
L5503
CRT_VSYNC_CON

1
C5515
SC100P50V2JN-L-GP

C5513
SC18P50V2JN-1-GP
DP_CRT_R 1 2 BLM18BB220SN-GP CRT_R CRT_DDCCLK_CON DY

C5507
SC18P50V2JN-1-GP
68.00084.A11 C5516

1
2nd = 68.00245.011 C5511 SCD01U16V2KX-3GP

2
DY DY DY DY SC100P50V2JN-L-GP

2
L5501

14

1
DP_CRT_G 1 2 BLM18BB220SN-GP CRT_G
68.00084.A11 U5501A
2nd = 68.00245.011 DP_CRT_HSYNC_CON 2 DY 3 HSYNC_5

L5502
TC74VHCT125AFTQK2M-GP

14

7
4
DP_CRT_B 1 2 BLM18BB220SN-GP CRT_B U5501B SRN0J-6-GP
CRT_HSYNC_CON
1 R5501

1 R5513

1 R5514

68.00084.A11 1 4
DY
C5506
SC4D7P50V2BN-GP

C5512
SC4D7P50V2BN-GP

C5509
SC4D7P50V2BN-GP

C5514
SC4D7P50V2BN-GP

C5510
SC4D7P50V2BN-GP

C5518
SC4D7P50V2BN-GP
2nd = 68.00245.011 DP_CRT_VSYNC_CON 5 DY 6 VSYNC_5 2 3 CRT_VSYNC_CON
1

1
5V_CRT_S0
RN5502
TC74VHCT125AFTQK2M-GP
2

7
75R2F-2-GP 2

75R2F-2-GP 2

75R2F-2-GP 2

4
3
C R55111 2 33R2J-2-GP C
RN5501 R55071 2 33R2J-2-GP
SRN2K2J-1-GP

1
2
CRT_DDCDATA_CON

CRT_DDCCLK_CON
3D3V_S0 AVCC33

R5504
Layout note: U5502
1 2 All cap need close to chip AVCC33 CRT_PCH_HPD CRT_PCH_HPD
2 1 24 1 CRT_PCH_HPD [15]
0R0603-PAD-1-GP-U SCD1U16V2KX-3GP C5517 AVCC_33 HPD
2

C5523 2 1 VCCK_12 25 2 PCH_SMBCLK [12,18,62,96]

1
SC10U6D3V3MX-GP SCD1U16V2KX-3GP C5503 AVCC_12 SMB_SCL
3 PCH_SMBDATA [12,18,62,96]
3D3V_S0 SMB_SDA R5510
2 1 5
1

SCD1U16V2KX-3GP2 3D3V_S0 DVCC_33 CRT_DDCCLK_CON

1C5520 20 4 100KR2J-4-GP
SCD1U16V2KX-3GP C5522 DVCC_33 VGA_SCL CRT_DDCDATA_CON
6
VCCK_12 VGA_SDA
2 1 19

2
SCD1U16V2KX-3GP2 C5501 VCCK_12
1
SC2D2U10V3KX-1GP
2 1C5504 VDD_DAC_33 9 7 DP_CRT_VSYNC_CON
SCD1U16V2KX-3GP2 VDD_DAC_33 VSYNC DP_CRT_HSYNC_CON
1C5524 8
3D3V_S0 VDD_DAC_33 SC10U6D3V3MX-GP C5502 HSYNC
LDO_EN 21 15 DP_CRT_R
LDO_EN RED_P
16
R5503 C5527 1 PCH_DPC_AUXP_U RED_N
[15] PCH_DPB_AUXP 2SCD1U16V2KX-3GP 26
C5528 1 PCH_DPC_AUXN_U AUX_P DP_CRT_G
1 2 [15] PCH_DPB_AUXN 2SCD1U16V2KX-3GP 27 12
AUX_N GREEN_P
13
0R0603-PAD-1-GP-U C5529 1 PCH_DPC_P0_U GREEN_N
[8] PCH_DPB_P0 2SCD1U16V2KX-3GP 29
2

C5521 C5526 1 PCH_DPC_N0_U LANE0P DP_CRT_B

[8] PCH_DPB_N0 2SCD1U16V2KX-3GP 30 10
SC10U6D3V3MX-GP LANE0N BLUE_P
11
C5530 1 PCH_DPC_P1_U BLUE_N
[8] PCH_DPB_P1 2SCD1U16V2KX-3GP 31
1

C5525 1 PCH_DPC_N1_U LANE1P POL1_SDA

[8] PCH_DPB_N1 2SCD1U16V2KX-3GP 32 22
LANE1N POL1_SDA POL2_SCL
R5506 23
POL2_SCL
CLK_DP2VGA 1 2 XI
CRT_DEBUG 17
[18] CLK_DP2VGA XI/CKIN
18 14
XO GND_DAC
0R2J-2-GP RRX 28 33
B RRX GND B

RTD2168-CGT-GP
1

R5505 071.02168.0003
12KR2F-L-GP
2

3D3V_S0 3D3V_S0 3D3V_S0 3D3V_S0

2

R5509 R5515 R5502 U5504

4K7R2J-2-GP 4K7R2J-2-GP 4K7R2J-2-GP
EEPROM EEPROM/ROM 1
A0 VCC
8
2 7
1

A1 WP POL2_SCL
POL1_SDA POL2_SCL LDO_EN
3 CRT_DEBUG
A2 SCL
6
POL1_SDA
4 5
VSS SDA
2

R5508 R5516 R5512 CAT24C128WI-GT3-GP

4K7R2J-2-GP ROM4K7R2J-2-GP DY 4K7R2J-2-GP DY 72.24128.J01
1

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
(Reserved)DP to VGA Converter
Size Document Number Rev
A2
Janus HSW 40/50/70 X02
Date: Friday, February 07, 2014 Sheet 55 of 104
5 4 3 2 1
SSID = SATA

SATA HDD Connector

HDD1

P1 V33 23 23
P2 V33 24 24 Layout Note:
P3 V33
NP1
Place near HDD1
5V_S0 P7
NP1
NP2 1A
V5 NP2 U5602
P8 V5
P9 5V_S0
V5 SATA_TXP0_R SATA_TXP0_R
1 LINE_1 NC#10 10
P13 S1 SATA_TXN0_R 2 9 SATA_TXN0_R
V12 GND LINE_2 NC#9
P14 S4 3 GND DY GND 8

SC10U10V5KX-2GP
V12 GND

C5605
P15 S7 SATA_RXN0_R 4 7 SATA_RXN0_R
V12 GND SATA_RXP0_R LINE_3 NC#7 SATA_RXP0_R
GND P4 5 LINE_4 NC#6 6

1
GND P5
[19] SATA3_PTX_HDDRX_P0 SCD01U50V2KX-1GP 2 1 C5602 SATA_TXP0_R S2 P6 DY C5606
SCD01U50V2KX-1GP TX+ GND
[19] SATA3_PTX_HDDRX_N0 2 1 C5603 SATA_TXN0_R S3 P10 AZ1045-04F-R7G-GP

2
TX- GND SCD1U16V2KX-3GP
GND P12
SCD01U50V2KX-1GP 1 2 C5615 SATA_RXP0_R S6
[19] SATA3_PRX_HDDTX_P0 SCD01U50V2KX-1GP RX+ 75.01045.073
[19] SATA3_PRX_HDDTX_N0 1 2 C5616 SATA_RXN0_R S5 RX- DAS/DSS P11 Swap based on the swap report.
SATA_HDD
SKT-SATA7P-15P-159-GP

022.10019.0001
Close to HDD1
2ND = 022.10019.0021
ME Note: New HDD conn symbol is not ready,
we will use original OAK HDD conn (22.10300.991) and shift to the correct position.

ODD Connector SATA Zero Power ODD

ODD_PW R_5V 3D3V_S0
ODD1
14
NP1
R5607 2.5A
1 2 SATA_ODD_PW RGT
6 ODD_PW R_5V
R5602 5V_S0
5 U5601
SATA_ODD_DA#_C 100KR2J-1-GP
4 1 2 0R0402-PAD SATA_ODD_DA# [20]
ODD_PW R_5V 5V_S0 ODD_PW R_5V
3 2 IN#2 OUT#6 6 100 mil
2 3 IN#3 OUT#7 7
8 R5603
SATA_ODD_PRSNT# C5609 OUT#8 C5610
1 SATA_ODD_PRSNT# [19] 1 DY 2

1
[20] SATA_ODD_PW RGT 4 EN/EN#
S7 DY 1 0R5J-5-GP
SATA_RXP2_R C5608 1 GND
S6 2 SCD01U50V2KX-1GP SATA_PRX_ODDTX_P2 [19] SC10U10V5KX-2GP 5 9 SC10U10V5KX-2GP

2
SATA_RXN2_R C5607 1 FLT# GND
S5 2 SCD01U50V2KX-1GP SATA_PRX_ODDTX_N2 [19]
S4
S3 SATA_TXN2_R C5611 1 2 SCD01U50V2KX-1GP SATA_PTX_ODDRX_N2 [19]
Current limit
SATA_TXP2_R C5612 1 2 SCD01U50V2KX-1GP TPS2001CDGNR-GP
S2
S1
SATA_PTX_ODDRX_P2 [19] Active High
74.02001.079
1

NP2 R5604 typ =>2.5A 2nd = 74.02311.079

10KR2J-3-GP
15 DY
SKT-SATA7P+6P-57-GP-U
2

20.81152.013

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

HDD/ODD
Size Document Number Rev
A3
Janus HSW 40/50/70 A00
Date: Friday, February 07, 2014 Sheet 56 of 104
 5 4 3 2 1

SSID = ESATA

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
ESATA
Size Document Number Rev
A3
Janus HSW 40/50/70 A00
Date: Friday, February 07, 2014 Sheet 57 of 104
5 4 3 2 1
 5 4 3 2 1

SSID = Wireless Mini Card Connector(802.11a/b/g) WLAN1

6 1.5V REFCLK+ 13 CLK_PCIE_WLAN_P3 [18]

REFCLK- 11 CLK_PCIE_WLAN_N3 [18]
3D3V_S0 2 3.3V/MS_V3
D 23 D
MS_TX+/PERN0 PCIE_PRX_WLANTX_N3 [16]
28 +1.5V MS_TX-/PERP0 25 PCIE_PRX_WLANTX_P3 [16]
48 +1.5V
MS_RX-/PETN0 31 PCIE_PTX_WLANRX_N3_C [16]
3D3V_S0 52 +3.3V/MS_V3 MS_RX+/PETP0 33 PCIE_PTX_WLANRX_P3_C [16]
24 36 USB_PN5_R
+3.3VAUX/MS_V3 USB_D- USB_PP5_R
USB_D+ 38

TP5801 1 WLAN_ACT 3 30
BT_ACT RESERVED#3 SMB_CLK
5 RESERVED#5 SMB_DATA 32
8 RESERVED#8
10 RESERVED#10
12 RESERVED#12 WAKE# 1
14 RESERVED#14 CLKREQ# 7 CLK_PCIE_WLAN_REQ3# [15,18]
16 RESERVED#16 PERST# 22 PLT_RST# [17,24,30,36,52,65,73,96]
TP5802 1 E51_RX 17 RESERVED#17
[24] E51_TXD R5804 1 20R2J-2-GP E51_TX 19 RESERVED#19
R5806 [24] WIFI_RF_EN DY 20 4
0R2J-2-GP RESERVED#20 GND
37 RESERVED#37 GND 9
C BT_ACT 1 2 3D3V_S0 39 15 C
RESERVED#39/MS_V3 GND
DY 41 RESERVED#41/MS_V3 GND 18
43 RESERVED#43 GND 21
[20] BLUETOOTH_EN R5805 1 2 0R0402-PAD R5807 45 26
0R2J-2-GP RESERVED#45 GND
47 RESERVED#47 GND 27
1 DY 2 DEBUG 49 29
RESERVED#49 GND
5V_S0 1 DY 2+5V_MINI_DEBUG 51 RESERVED#51 GND 34
R5801 0R2J-2-GP 35
GND
GND 40
42 LED_WWAN# GND 50
TP5804 1 CARD_WLAN_OUT# 44 53
CARD_WPAN_OUT# LED_WLAN# GND
TP5803 1 46 LED_WPAN# GND 54

NP1
NP2
MINI_PCI 52P
SKT-MINI52P-81-GP-U1

NP1
NP2
62.10043.C81
1.1A
B 3D3V_S0 B
1

C5802 C5803 C5804

SC10U10V5KX-2GP
2

2
SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

USB_PN5_R R5802 1 2 0R0402-PAD USB_PN5 [16]

USB_PP5_R R5803 1 2 0R0402-PAD USB_PP5 [16]

<Core Design>
WLAN_ACT
1

DY C5807 Wistron Corporation

A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, A
2

SCD1U16V2KX-3GP

Taipei Hsien 221, Taiwan, R.O.C.

Title

Mini Card (WLAN)

Size Document Number Rev
A4
Janus HSW 40/50/70 A00
Date: Friday, February 07, 2014 Sheet 58 of 104
5 4 3 2 1
 A B C D E

4 4

3
(Blanking) 3

2 2

<Core Design>

1
Wistron Corporation 1
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A4
Janus HSW 40/50/70 A00
Date: Friday, February 07, 2014 Sheet 59 of 104
A B C D E
 5 4 3 2 1

D D

C C

(Blanking)

B B

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
(Reserved)
Size Document Number Rev
A4 A00
Janus HSW 40/50/70
Date: Friday, February 07, 2014 Sheet 60 of 104
5 4 3 2 1
 5 4 3 2 1

SSID = User.Interface
Power button
D
SW1 D

R6102 6

1 2 KBC_PWRBTN#_C 4
[24] KBC_PWRBTN#
3
100R2J-2-GP 2

1
AFTP6801 1 1
DY EC6104

SCD1U25V2KX-GP
5

2
ETY-CON4-34-GP

20.K0465.004 AFTP6802
1

2nd = 20.K0422.004
3RD = 20.K0382.004
C
Battery LED1 (AMBER_LED) C

Low actived from KBC GPIO

5V_S5
Q6104
R2
E
[24] CHG_AMBER_LED# 1 R6104 2CHG_AMBER_LED_R# B R1 R6103
C AMBER_LED_BAT 2 1 BAT_AMBER
0R0402-PAD
499R2F-2-GP
DDTA144VCA-7-F-GP
AMBER

1
EC6105
84.00144.N11 DY SC220P50V2KX-3GP

2
BAT_AMBER [63]
B B
BAT_WHITE [63]
5V_S5
Q6103
R2
E R6101
1 R6105 2BATT_WHITE_LED_R# B
[24] BATT_WHITE_LED# R1
C WHITE_LED_BAT 2 1 BAT_WHITE WHITE
0R0402-PAD
330R2J-3-GP
DDTA144VCA-7-F-GP
1

84.00144.N11 DY EC6103
SC220P50V2KX-3GP
2

<Core Design>

A Battery LED2 (WHITE_LED) Wistron Corporation A

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Low actived from KBC GPIO Title

LED Bard/Power Button

Size Document Number Rev
A4
Janus HSW 40/50/70 A00
Date: Friday, February 07, 2014 Sheet 61 of 104
5 4 3 2 1
 5 4 3 2 1

BDW: Support PTP

3D3V_S5 3D3V_S0

1
SSID = KBC SSID = Touch.Pad R6213 R6212

Internal Keyboard Connector (DVC40) 0R2J-2-GP

BDW
0R2J-2-GP
HSW

2
AFTP6202 1 KB1 C6204
32 SCD1U16V2KX-3GP
30 1 2 Q6203_S TP_VDD
[20] KB_DET# AFTP6221 KROW7 R6215
1 29
AFTP6222 1 KROW6 28 2 DY 1 TP_LID_CLOSE#
AFTP6230 1 KROW4 27 1KR2J-1-GP

S
AFTP6218 1 KROW2 26 R6214 10KR2J-3-GP

2
D AFTP6214 1 KROW5 25 TP_ON# 1 2 TP_ON#_GATE G D
[24] TP_ON#
AFTP6227 KROW1
G
1 24
AFTP6234 KROW3
[24] KROW[0..7]
AFTP6228
1
KROW0
23
Q6203 D
R6209
DY
1 22
AFTP6215 1 KCOL5 21 TP_VDD DMP2130L-7-GP

1
D
Touch Pad Connector
AFTP6224 1 KCOL4 20 84.02130.031 0R2J-2-GP
[24] KCOL[0..16]
AFTP6213 1 KCOL7 19 2ND = 84.03413.A31
AFTP6223 1 KCOL6 18
AFTP6231 1 KCOL8 17 TP_VDD Pin number Pin name
AFTP6208 1 KCOL3 16 TP_VDD

2
1
AFTP6206 1 KCOL1 15 1 VDD
AFTP6226 1 KCOL2 14 RN6201 TPAD1
C6201
AFTP6207 1 KCOL0 13 SRN10KJ-5-GP 2 DAT(I2C)
AFTP6233 1 KCOL12 12 2 1
AFTP6225 1 KCOL16 11 3 CLK(I2C)
AFTP6229 1 KCOL15 10 SCD1U16V2KX-3GP 10

3
4
AFTP6203 1 KCOL13 9 2 1 4 GND
AFTP6216 1 KCOL14 8 8
AFTP6219 1 KCOL9 7 SRN33J-5-GP-U R6211 I2C1_SDA_R 7 5 ATTN
PS2
AFTP6220 1 KCOL11 6 [24] TPCLK RN6202 1 4 TPCLK_C 4K7R2J-2-GP I2C1_SCL_R 6
AFTP6232 1 KCOL10 5 2 3 TPDATA_C 5 6 GPIO
[24] TPDATA
CAP_LED 4 20.K0592.030 4
[15,20,24] INT_TP#
I2C
3 TP_LID_CLOSE# 3 7 DAT(PS2)
RN6203 2 I2C1_SCL_R [24] TP_LID_CLOSE# TPDATA_C
2 2nd = 20.K0565.030 [20] I2C1_SCL 3
I2C1_SDA_R
2
[20] I2C1_SDA 1 HSW 4 8 CLK(PS2)
AFTP6201 TPCLK_C
1 1 3rd = 20.K0621.030 SRN33J-5-GP-U
1
31
9

EC6202
SC33P50V2JN-3GP

EC6203
SC33P50V2JN-3GP

EC6204
SC33P50V2JN-3GP
ETY-CON10-22-GP-U

1
ACES-CON30-10-GP
EC6201 20.K0665.008
SC33P50V2JN-3GP DY DY DY DY 1

2
AFTP6235 2nd = 20.K0667.008
5V_S0 3D3V_S0

CAP LED Control Q6201

5V_S0

LOW actived from KBC GPIO R2

E TP_VDD Need to check if it is Active High or Active Low
SMBUS
1 R6202 2 CAP_LED_R# B R6201 0R2J-2-GP 1 DY 2 R6204 I2C1_SCL_R
[12,18,96] PCH_SMBCLK and check if there is PH on TPAD side.

1
[24] CAP_LED# R1
CAP_LED_Q CAP_LED 0R2J-2-GP 1 I2C1_SDA_R
C 1 2 [12,18,96] PCH_SMBDATA DY 2 R6210
0R0402-PAD R6216 R6217
1KR2J-1-GP 0R2J-2-GP TP_VDD
C
DDTA144VCA-7-F-GP DY 0R2J-2-GP C

2
1
Need to check with SW.

2
EC6206
SC33P50V2JN-3GP

EC6205
SC33P50V2JN-3GP
RN6204 TP side has pull high

1
84.00144.N11 SRN10KJ-5-GP
DY DY
Internal Keyboard Connector (DVC50/DVC70)
R6203

2
Q6204_G 2 1 INT_TP#

3
4
2N7002KDW-GP 10KR2J-3-GP

KB2 I2C1_SCL 1 6 I2C1_SCL_R

[20] KB_DET#
32
30 Keyboard Backlight (DVC70) 84.2N702.A3F 2 5
KROW7 29 2nd = 84.2N702.E3F BDW
KROW6 28 3rd = 75.00601.07C 3 4 I2C1_SDA_R TP_VDD 1 AFTP6239
KROW4 27 4th = 84.DMN66.03F TPCLK_C 1 AFTP6238
KROW2 26 5V_S0 +5V_KB_BL Q6204 TPDATA_C 1 AFTP6236
KROW5 25 I2C1_SCL_R 1 AFTP6237
KROW1 24 F6201 I2C1_SDA_R 1 AFTP6240
KROW3 69.50007.921 I2C1_SDA INT_TP# AFTP6241
KROW0
23
22
1
DY 2
TP_LID_CLOSE#
1
1 AFTP6242

1
KCOL5 21 POLYSW-D5A6V-1-GP
KCOL4 20 KBBL C6202
KCOL7 19 1KBBL 2

2
KCOL6 18 R6205 0R3J-0-U-GP SCD1U16V2KX-3GP
KCOL8 17 KBLIT1
KCOL3 16 5
KCOL1 15 1
KCOL2 14 R6206
KCOL0 13 1 KBBL 2 KB_LED_DET_C 2 KBBL
KCOL12 [20] KB_LED_BL_DET
12 3
1

KCOL16 11 51KR2J-1-GP 4

1
KCOL15

KB_BL_CTRL#
KCOL13
10 KBBL R6207 C6203
6

KCOL14
9 DY
100KR2J-1-GP ACES-CON4-56-GP
8

SCD1U16V2KX-3GP
2
KCOL9 7 20.K0800.004
2

KCOL11 6 1
KCOL10
CAP_LED
5 2ND = 20.K0841.004 AFTP6245
4
3

D
B 2 B
KB Backlight Power Consumption: 285mA max. Q6202
DMN3404L-7-GP
1 KBBL
31 G
[24] KB_BL_CTRL
84.03404.C31
1

ACES-CON30-10-GP
S

20.K0592.030 R6208
2nd = 20.K0565.030
DY 100KR2J-1-GP
3rd = 20.K0621.030 +5V_KB_BL 1
KB_LED_DET_C 1 AFTP6248
2

KB_BL_CTRL# 1 AFTP6246
AFTP6247

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Key Board/Touch Pad

Size Document Number Rev
A2 A00
Janus HSW 40/50/70
Date: Friday, February 07, 2014 Sheet 62 of 104
5 4 3 2 1
 5 4 3 2 1

D D

CON1
USB20_VCCB
17 TR6301
1
USB_PN2_IOBD1 3 4 USB_PN2 [16]
2
3D3V_S0 69.10103.041
USB_PP2_IOBD1
3 2 1 USB_PP2 [16]
4
5 FILTER-4P-6-GP
6
7
USB2.0 Port3
C 8 USB_PN2_IOBD1 C
9 USB_PP2_IOBD1
10
Card Reader
11 USB_PN7_IOBD1
12 USB_PP7_IOBD1
13
14
15
BAT_AMBER
BAT_WHITE
[61]
[61]
LED
16
18

PTWO-CON16-2-GP
TR6302
20.K0382.016 USB_PN7_IOBD1 3 4 USB_PN7 [16]
69.10103.041
USB_PP7_IOBD1 2 1 USB_PP7 [16]

FILTER-4P-6-GP
B The maximum range of the PMOS output current in RTS5170 (Card Reader IC) is 400mA B

USB20_VCCB
1

DY TC6301
SC100U6D3V6MX-GP
78.10710.52L
2

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

IO Board Connector
Size Document Number Rev
A4 Janus HSW 40/50/70 A00
Date: Friday, February 07, 2014 Sheet 63 of 104
5 4 3 2 1
 5 4 3 2 1

SSID = User.Interface

3D3V_S5
D D

2
R6401
100KR2J-1-GP
DY

1
[24] LID_CLOSE# LID_CLOSE#

1
C6401 3D3V_S5 LIDSW1
DY SCD047U25V2KX-GP

SCD1U16V2KX-3GP
1 VSS
2 VDD
3 OUT
C6402

1
C C
S-5712ACDL1-M3T1U-GP

2
74.05712.0BB

B B

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Hall Sensor
Size Document Number Rev
A4 A00
Janus HSW 40/50/70
Date: Friday, February 07, 2014 Sheet 64 of 104
5 4 3 2 1
 5 4 3 2 1

SSID = DEBUG PORT

D D

Debug Connector
Layout Note:
Place near trace separated point 3D3V_S0 DB1

11
LPC_AD[3..0] RN6501 1
[18,24] LPC_AD[3..0]
SRN0J-7-GP-U
LPC_AD0 1 8 LPC_LAD0_R 2
LPC_AD1 2 7 LPC_LAD1_R 3
LPC_AD2 3 DEBUG6 LPC_LAD2_R 4
LPC_AD3 4 5 LPC_LAD3_R 5
LPC_FRAME#_DEBUG 6
DEBUG
1 2 PLT_RST#_DEBUG 7
[18,24] LPC_FRAME#
[17,24,30,36,52,58,73,96] PLT_RST# R6501 DEBUG
1 2 0R2J-2-GP 8
R6502 0R2J-2-GP 9
[18] CLK_PCI_LPC
10
12
C C

PAD-10P-177042-GP
ZZ.00PAD.Y41

20.D0075.110: Dummy Pad with solder mask is ZZ.00PAD.Y41

DB1 Optional: New one smaller LPC connector is 20.F1180.010.

B B

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Dubug connector
Size Document Number Rev
A4
Janus HSW 40/50/70 A00
Date: Friday, February 07, 2014 Sheet 65 of 104
5 4 3 2 1
 5 4 3 2 1

D D

(Blanking)
C C

B B

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A4
Janus HSW 40/50/70 A00
Date: Friday, February 07, 2014 Sheet 66 of 104
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
Janus HSW 40/50/70 A00
Date: Friday, February 07, 2014 Sheet 67 of 104
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number

RESERVED Rev
A3 Janus HSW 40/50/70 A00
Date: Friday, February 07, 2014 Sheet 68 of 104
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

USB3.0 PORT
Size Document Number Rev
A3
Janus HSW 40/50/70 A00
Date: Friday, February 07, 2014 Sheet 69 of 104
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
Janus HSW 40/50/70 A00
Date: Friday, February 07, 2014 Sheet 70 of 104
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
Janus HSW 40/50/70 A00
Date: Friday, February 07, 2014 Sheet 71 of 104
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
Janus HSW 40/50/70 A00
Date: Friday, February 07, 2014 Sheet 72 of 104
5 4 3 2 1
 5 4 3 2 1

3V3_AON_S0
PDP-06877-006

1
R7312 From GPIO21
dGPU Reset GC6_20 10KR2J-3-GP D7301
R7308 1 GPU_PEX_RST_HOLD [76]
3V3_AON_S0

2
U7301 GPU_PEX_RST# 1 2 GPU_PEX_RST_D# 3 GC6_20
[15] DGPU_HOLD_RST# 1 5
A VCC SYS_PEX_RST_MON#
2
U74LVC1G08G-AL5-R-GP-U 0R2J-2-GP
[17,24,30,36,52,58,65,96] PLT_RST# 2
B OPS
GC6_20
3 4 SYS_PEX_RST_MON# [76] BAT54A-1-GP
GND Y
75.00054.X7D 1D05V_VGA_S0
To GPIO8
73.01G08.EHG 2nd = 75.00054.R7D Place close VDD ball Place close Chip

1
D 2ND = 73.7SZ08.EAH D
3RD = 73.01G08.L04 R7306 3rd = 75.BAT54.07D
R7304 1 DY 2 0R2J-2-GP OPS 100KR2F-L1-GP
4th = 75.00054.Y7D

1
OPS OPS OPS C7323 C7322 C7325 C7326
3V3_AON_S0 GPU_PEX_RST# [76]

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP
C7312 C7313 C7310 OPS OPS OPS OPS

2
SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC4D7U6D3V3KX-GP
GPU1A 1 OF 14
1/14 PCI_EXPRESS

2
GK208/GF117/GF119
Q7301
R7303 R7313 AB6 NC
PEX_WAKE#
G OPS 10KR2J-3-GP
NON_GC6 PEX_IOVDD
AA22
D SYS_PEX_RST_MON# 1 2 GPU_PEX_RST# AC7 AB23
[18] PEG_CLKREQ#

1
0R2J-2-GP PEX_RST# PEX_IOVDD
AC24
GPU_CLKREQ# PEX_IOVDD
OPS S AC6
PEX_CLKREQ# PEX_IOVDD
AD25
AE26
AE8
PEX_IOVDD
AE27
1.05V +/- 30mV
2N7002K-2-GP [18] CLK_PCIE_VGA PEX_REFCLK PEX_IOVDD
84.2N702.J31 [18] CLK_PCIE_VGA# AD8
PEX_REFCLK# 3.3A
C7301 1OPS 2SCD22U10V2KX-1GP dGPU_TXP_CPU_RXP0 AC9
[16] CPU_RXP_C_dGPU_TXP0 PEX_TX0 1D05V_VGA_S0
C7302 1OPS 2SCD22U10V2KX-1GP dGPU_TXN_CPU_RXN0 AB9
[16] CPU_RXN_C_dGPU_TXN0 PEX_TX0#
Place close VDD ball Place close Chip
1 DY 2 [16] dGPU_RXP_C_CPU_TXP0 AG6
PEX_RX0
[16] dGPU_RXN_C_CPU_TXN0 AG7 AA10
R7305 PEX_RX0# PEX_IOVDDQ
AA12
0R2J-2-GP C7303 1OPS dGPU_TXP_CPU_RXP1 PEX_IOVDDQ
[16] CPU_RXP_C_dGPU_TXP1 2SCD22U10V2KX-1GP AB10 AA13
C7304 1OPS dGPU_TXN_CPU_RXN1 PEX_TX1 PEX_IOVDDQ
[16] CPU_RXN_C_dGPU_TXN1 2SCD22U10V2KX-1GP AC10 AA16
PEX_TX1# PEX_IOVDDQ
AA18

1
PEX_IOVDDQ OPS OPS OPS C7320 C7321 C7327 C7328
[16] dGPU_RXP_C_CPU_TXP1 AF7 AA19
PEX_RX1 PEX_IOVDDQ
AE7 AA20

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP
[16] dGPU_RXN_C_CPU_TXN1 PEX_RX1# PEX_IOVDDQ
AA21 C7311 C7314 C7309 OPS OPS OPS OPS

2
PEX_IOVDDQ

SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC4D7U6D3V3KX-GP
C7305 1OPS 2SCD22U10V2KX-1GP dGPU_TXP_CPU_RXP2 AD11 AB22
[16] CPU_RXP_C_dGPU_TXP2 PEX_TX2 PEX_IOVDDQ
[16] CPU_RXN_C_dGPU_TXN2 C7306 1OPS 2SCD22U10V2KX-1GP dGPU_TXN_CPU_RXN2 AC11 AC23
PEX_TX2# PEX_IOVDDQ
AD24
PEX_IOVDDQ
[16] dGPU_RXP_C_CPU_TXP2 AE9 AE25
PEX_RX2 PEX_IOVDDQ
[16] dGPU_RXN_C_CPU_TXN2 AF9 AF26
PEX_RX2# PEX_IOVDDQ
AF27
C7307 1OPS dGPU_TXP_CPU_RXP3 PEX_IOVDDQ
C
[16] CPU_RXP_C_dGPU_TXP3 2SCD22U10V2KX-1GP AC12 C
C7308 1OPS dGPU_TXN_CPU_RXN3 PEX_TX3
[16] CPU_RXN_C_dGPU_TXN3 2SCD22U10V2KX-1GP AB12
PEX_TX3#

[16] dGPU_RXP_C_CPU_TXP3 AG9

PEX_RX3
[16] dGPU_RXN_C_CPU_TXN3 AG10
PEX_RX3#
AB13
PEX_TX4
AC13
PEX_TX4#
AF10
PEX_RX4
AE10
PEX_RX4# 3.3V +/- 5%
3V3_AON_S0
AD14
AC14
PEX_TX5
AA8
210mA
PEX_TX5# PEX_PLL_HVDD
AA9
PEX_PLL_HVDD
AE12
PEX_RX5
AF12
PEX_RX5#

C7316
AB8
PEX_SVDD_3V3
AC15
PEX_TX6
AB15 Place close Chip

1
PEX_TX6# C7315 OPS C7324 OPS

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP
GPIO5
GPIO51(PCH) AG12
PEX_RX6 OPS
AG13

2
PEX_RX6#

SCD1U16V2KX-3GP
AB16
PEX_TX7
AC16
PEX_TX7#
AF13
GPIO0 PEX_RX7
AE13
PEX_RX7#
AD17 NC
PEX_TX8
AC17 NC
PEX_TX8#
AE15 NC
PEX_RX8
AF15 NC
PEX_RX8#
GPIO45 (PCH) AC18
PEX_TX9 NC VDD_SENSE
F2 VGACORE_VDD_SENSE_1 [82]
AB18
GPIO96(KBC) PEX_TX9# NC
POWER IC
AG15 NC F1 VGACORE_GND_SENSE_1 [82]
PEX_RX9 GND_SENSE
AG16 NC
B GPIO51(KBC) PEX_RX9# B
GPIO47 (PCH)
GPIO6 AB19 NC
PEX_TX10
AC19 NC
PEX_TX10#
GPIO54(PCH) AF16
PEX_RX10 NC
AE16 NC
GPIO8 PEX_RX10#
AD20 NC
PEX_TX11
AC20 NC
GPIO21 PEX_TX11#
AE18 NC
PEX_RX11
AF18 NC
PEX_RX11#
AC21 NC
PEX_TX12 R7307
AB21 NC
PEX_TX12# 200R2F-L-GP
AG18 NC AF22 PEXTSTCLK_OUT 1 DY 2
PEX_RX12 PEX_TSTCLK_OUT
AG19 NC AE22 PEXTSTCLK_OUT# L7301
PEX_RX12# PEX_TSTCLK_OUT#
1D05V_VGA_S0
AD23
AE23
PEX_TX13 NC
NC Place close VDD ball Place close Chip MHC1608S121PBP-GP 1.05V +/- 30mV
PEX_TX13#
OPS 150mA
AF19 NC AA14 VCC1R05VIDEO_PEX_PLLVDD 1 2
PEX_RST# PEX_RX13 PEX_PLLVDD
AE19
PEX_RX13# NC PEX_PLLVDD
AA15 68.00335.151
AF24 NC C7318

1
PEX_TX14 C7317 C7319
AE24
PEX_TX14# NC OPS OPS OPS

SC4D7U6D3V3KX-GP

SC1U10V2KX-1GP
SCD1U16V2KX-3GP
AE21 NC

2
PEX_RX14 R7302
AF21 NC
PEX_RX14#
AD9 TESTMODE 1 OPS 2
TESTMODE 10KR2F-2-GP
AG24 NC
PEX_TX15
AG25 NC
PEX_TX15#
AG21 NC
PEX_RX15
AG22 NC
PEX_RX15#
OPS
GF119 GF117 R7301
GK208 AF25 PEX_TERMP 1 OPS 2
PEX_TERMP 2K49R2F-GP
A N14M-GE-S-A2-GP A

71.0N14M.B0U

<Core Design>

N15V-GM-S-A2: 071.0N15V.0A0U Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
N15V-GM-S is GF117. Taipei Hsien 221, Taiwan, R.O.C.

N15S-GT is GM108. Title

GPU_PCIE/STRAPPING(1/5)
Size Document Number Rev
A2
Janus HSW 40/50/70 A00
Date: Friday, February 07, 2014 Sheet 73 of 104

5 4 3 2 1
 5 4 3 2 1

LVDS Interface
GPU1G 7 OF 14
D 4/14 IFPAB GM108 D

GF117 GF119/GK208
GM108 NC AC4 GPU1I 9 OF 14
IFPA_TXC#
NC AC3 6/14 IFPD
GF119/GK208 GF117 IFPA_TXC
GF119/GK208 GF117
AA6 NC
IFPAB_RSET GF117 GF119/GK208
NC Y3 U6 NC
IFPA_TXD0# IFPD_RSET
NC Y4
IFPA_TXD0 DVI/HDMI DP
IFPAB_PLLVDD V7 NC GM108
IFPAB_PLLVDD IFPC_PLLVDD
NC AA2 T7 NC NC I2CX_SDA IFPD_AUX_I2CX_SDA# P4
IFPA_TXD1# IFPD_PLLVDD
W7 NC NC AA3 NC I2CX_SCL P3
IFPAB_PLLVDD IFPA_TXD1 IFPD_AUX_I2CX_SCL
R7 NC
IFPD_PLLVDD
NC AA1 NC TXC R5
IFPA_TXD2# IFPD_L3#
NC AB1 NC TXC R4
IFPA_TXD2 IFPD_L3

NC TXD0 T5
IFPD_L2#
NC AA5 NC TXD0 T4
IFPA_TXD3# IFPD_L2
NC AA4
IFPA_TXD3
NC TXD1 U4
IFPD IFPD_L1#
NC TXD1 U3
IFPD_L1
NC AB4
IFPB_TXC#
GM108 NC AB5 NC TXD2 V4
IFPB_TXC IFPD_L0#
NC TXD2 V3
GF119/GK208 GF117 IFPD_L0
IFPAB_IOVDD W6 NC AB2
IFPA_IOVDD NC IFPB_TXD4#
NC AB3 GM108
IFPB_TXD4 IFPC_IOVDD
Y6 NC R6 NC NC D4
IFPB_IOVDD IFPD_IOVDD GPIO17

NC AD2 GF119/GK208 GF117

4
3
IFPB_TXD5#
NC AD3
4
3

IFPB_TXD5 RN7401
RN7402 SRN10KJ-5-GP
DY SRN10KJ-5-GP NC IFPB_TXD6#
AD1 DY N14M-GE-S-A2-GP
NC AE1
IFPB_TXD6
71.0N14M.B0U

1
2
1
2

NC AD5
IFPB_TXD7#
NC IFPB_TXD7
AD4 OPS
C C

GM108
NC B3
GPIO14
IFPAB
N14M-GE-S-A2-GP
71.0N14M.B0U

OPS

GPU1J 10 OF 14
7/14 IFPEF
GF119/GK208
GF117
GM108 DVI-DL DVI-SL/HDMI DP
GM108

HDMI Interface IFPEF_PLLVDD

GF119
GF117
GK208 NC
NC
I2CY_SDA
I2CY_SCL
I2CY_SDA
I2CY_SCL
IFPE_AUX_I2CY_SDA#
IFPE_AUX_I2CY_SCL
J3
J2
J7 NC
GPU1H 8 OF 14 IFPEF_PLLVDD
5/14 IFPC GM108 J1
IFPC NC
NC
TXC
TXC
TXC
TXC
IFPE_L3#
K1
GF119/GK208 GF117 GM108 IFPE_L3
K7 NC
IFPEF_PLLVDD
T6 NC GF117 GF119/GK208 K3
IFPC_RSET NC TXD0 TXD0 IFPE_L2#
NC K2
TXD0 TXD0 IFPE_L2
DVI/HDMI DP
K6 NC NC TXD1 TXD1 M3
IFPD_PLLVDD IFPEF_RSET IFPE_L1#
M7 NC NC I2CW_SDA IFPC_AUX_I2CW_SDA# N5 NC TXD1 TXD1 M2
IFPC_PLLVDD IFPE_L1
N7 NC NC I2CW_SCL N4
IFPC_PLLVDD IFPC_AUX_I2CW_SCL
M1
NC TXD2 TXD2 IFPE_L0#
NC N1
TXD2 TXD2 IFPE_L0
NC TXC N3
IFPC_L3#
NC TXC N2
IFPC_L3 IFPE NC FOR GK208

NC TXD0 R3
IFPC_L2#
NC TXD0 R2 GM108
B IFPC_L2 B
NC HPD_E HPD_E C2
GPIO18
NC TXD1 R1
IFPC_L1#
NC TXD1 T1
IFPC_L1 GF117
GF119 GK208
NC TXD2 T3
IFPC_L0# IFPEF_IOVDD
NC TXD2 T2 H6 NC
IFPC_L0 IFPE_IOVDD
GF119/GK208
GF117
J6 NC
GM108 IFPF_IOVDD GM108 DVI-DL DVI-SL/HDMI DP
IFPD_IOVDD P6 NC NC C3 NC I2CZ_SDA H4
IFPC_IOVDD GPIO15 IFPF_AUX_I2CZ_SDA#
NC I2CZ_SCL H3
IFPF_AUX_I2CZ_SCL
N14M-GE-S-A2-GP
4
3

RN7404
71.0N14M.B0U NC TXC IFPF_L3#
J5
NC TXC J4
4
3

IFPF_L3
DY SRN10KJ-5-GP
OPS RN7403 NC TXD3 TXD0 IFPF_L2#
K5
DY SRN10KJ-5-GP NC TXD3 TXD0 IFPF_L2
K4
1
2

NC TXD4 TXD1 L4
IFPF IFPF_L1#
NC TXD4 TXD1 L3
1
2

IFPF_L1

NC TXD5 TXD2 M5
IFPF_L0#
NC TXD5 TXD2 M4
IFPF_L0

NC FOR GK208
GF117 GM108
NC HPD_F F7
GPIO19

N14M-GE-S-A2-GP
71.0N14M.B0U

OPS
A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

GPU Memory(2/5)
Size Document Number Rev
A2
Janus HSW 40/50/70 A00
Date: Friday, February 07, 2014 Sheet 74 of 104
5 4 3 2 1
 5 4 3 2 1

R7519
DY
1 2 GC6_FB_EN [20,24,76,83]
GPU1B 0R2J-2-GP
[78] FBA_D[0..31] 2 OF 14
R7518
2/14 FBA
FBA_D0 FB_CLAM
FBA_D1
E18
FBA_D0 NC FB_CLAMP
F3 1 OPS 2
F18
FBA_D2 FBA_D1
E16 GF119 GF117/GK208
FBA_D3 FBA_D2 10KR2J-3-GP
F17
FBA_D4 FBA_D3
D20
FBA_D5 FBA_D4
D21
FBA_D6 FBA_D5
D F20 D
FBA_D7 FBA_D6 FBA_CMD5
E21
FBA_D8 FBA_D7 FBA_CMD2
E15
FBA_D9 FBA_D8 FBA_CMD3
D15
FBA_D10 FBA_D9 FBA_CMD19
F15
FBA_D11 FBA_D10 FBA_CMD18
F13
FBA_D12 FBA_D11
C13
FBA_D13 FBA_D12
B13
FBA_D14 FBA_D13
E13
FBA_D15 FBA_D14
D13
FBA_D16 FBA_D15
B15

1
FBA_D17 FBA_D16 R7508 R7509 R7510 R7511 R7512
C16
FBA_D18 FBA_D17
A13

10KR2F-2-GP

10KR2F-2-GP

10KR2F-2-GP

10KR2F-2-GP

10KR2F-2-GP
FBA_D19 FBA_D18
A15
FBA_D19
OPS OPS OPS OPS OPS
FBA_D20 B18
FBA_D21 FBA_D20
A18

2
FBA_D22 FBA_D21
A19
FBA_D23 FBA_D22
C19
FBA_D24 FBA_D23
B24
FBA_D25 FBA_D24
C23
FBA_D26 FBA_D25
A25
FBA_D27 FBA_D26
A24
FBA_D28 FBA_D27
A21
FBA_D29 FBA_D28
B21
FBA_D30 FBA_D29
C20
FBA_D31 FBA_D30
[79] FBA_D[32..63] C21
FBA_D32 FBA_D31
FBA_D33
R22
R24
FBA_D32
C27 FBA_CMD0
FBA_CMD0 [78]
1.5V +/- 3%
FBA_D34 FBA_D33 FBA_CMD0 FBA_CMD1 TP7501 TPAD14-OP-GP
FBA_D35
T22
R23
FBA_D34 FBA_CMD1
C26
E24 FBA_CMD2
1 4.88A
FBA_D35 FBA_CMD2 FBA_CMD2 [78]
FBA_D36
FBA_D37
N25
FBA_D36 FBA_CMD3
F24 FBA_CMD3
FBA_CMD4
FBA_CMD3 [78] Under GPU Near GPU 1D35V_VGA_S0
N26 D27 FBA_CMD4 [78,79]
FBA_D38 FBA_D37 FBA_CMD4 FBA_CMD5 4 OF 14 GPU1D
N23 D26 FBA_CMD5 [78,79]
FBA_D39 FBA_D38 FBA_CMD5 FBA_CMD6
N24 F25 FBA_CMD6 [78,79] 12/14 FBVDDQ
FBA_D40 FBA_D39 FBA_CMD6 FBA_CMD7
V23 F26 FBA_CMD7 [78,79]
FBA_D41 FBA_D40 FBA_CMD7 FBA_CMD8
V22 F23 FBA_CMD8 [78,79] B26
FBA_D42 FBA_D41 FBA_CMD8 FBA_CMD9 FBVDDQ C7501 C7502 C7525 C7507 C7513 C7514 C7517 C7520
T23 G22 FBA_CMD9 [78,79] C25

1
FBA_D43 FBA_D42 FBA_CMD9 FBA_CMD10 FBVDDQ
U22 G23 E23 OPS OPS

SC10U10V5KX-2GP
SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP
FBA_D43 FBA_CMD10 FBA_CMD10 [78,79] FBVDDQ

SC22U6D3V5MX-2GP
FBA_D44 Y24 G24 FBA_CMD11 E26 OPS OPS OPS OPS OPS OPS

SC1U10V2KX-1GP

SC1U10V2KX-1GP
SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
FBA_D44 FBA_CMD11 FBA_CMD11 [78,79] FBVDDQ
FBA_D45 AA24 F27 FBA_CMD12 F14
FBA_CMD12 [78,79]

2
FBA_D46 FBA_D45 FBA_CMD12 FBA_CMD13 FBVDDQ
Y22 G25 FBA_CMD13 [78,79] F21
FBA_D47 FBA_D46 FBA_CMD13 FBA_CMD14 TP7505 TPAD14-OP-GP FBVDDQ
C AA23 G27 1 G13 C
FBA_D48 FBA_D47 FBA_CMD14 FBA_CMD15 FBVDDQ
AD27 G26 FBA_CMD15 [78,79] G14
FBA_D49 FBA_D48 FBA_CMD15 FBA_CMD16 FBVDDQ
AB25 M24 FBA_CMD16 [79] G15
FBA_D50 FBA_D49 FBA_CMD16 FBA_CMD17 TP7502 TPAD14-OP-GP FBVDDQ
AD26 M23 1 G16
FBA_D51 FBA_D50 FBA_CMD17 FBA_CMD18 FBVDDQ
AC25 K24 FBA_CMD18 [79] G18
FBA_D52 FBA_D51 FBA_CMD18 FBA_CMD19 FBVDDQ
AA27 K23 FBA_CMD19 [79] G19
FBA_D53 FBA_D52 FBA_CMD19 FBA_CMD20 FBVDDQ
AA26 M27 FBA_CMD20 [78,79] G20
FBA_D53 FBA_CMD20 FBVDDQ
FBA_D54
FBA_D55
W26
FBA_D54 FBA_CMD21
M26 FBA_CMD21
FBA_CMD22
FBA_CMD21 [78,79] GM108 FBVDDQ
G21 Close to DRAM 1D35V_VGA_S0
Y25 M25 FBA_CMD22 [78,79] FBVDDQ_AON H24
FBA_D56 FBA_D55 FBA_CMD22 FBA_CMD23 FBVDDQ
R26 K26 FBA_CMD23 [78,79] FBVDDQ_AON H26
FBA_D57 FBA_D56 FBA_CMD23 FBA_CMD24 FBVDDQ
T25 K22 FBA_CMD24 [78,79] FBVDDQ_AON J21
FBA_D58 FBA_D57 FBA_CMD24 FBA_CMD25 FBVDDQ
N27 J23 FBA_CMD25 [78,79] FBVDDQ_AON K21
FBA_D59 FBA_D58 FBA_CMD25 FBA_CMD26 FBVDDQ
R27 J25 FBA_CMD26 [78,79] L22
FBA_D60 FBA_D59 FBA_CMD26 FBA_CMD27 FBVDDQ C7503 C7504 C7526 C7511
V26 J24 FBA_CMD27 [78,79] L24

1
FBA_D61 FBA_D60 FBA_CMD27 FBA_CMD28 FBVDDQ C7528 C7527 C7515 C7516 C7519 C7521 C7530 C7531
FBA_D62
V27
FBA_D61 FBA_CMD28
K27
FBA_CMD29
FBA_CMD28 [78,79] FBVDDQ
L26 OPS OPS OPS OPS
W27 K25 M21 OPS OPS OPS OPS OPS OPS OPS OPS

SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP
SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
FBA_D62 FBA_CMD29 FBA_CMD29 [78,79] FBVDDQ
FBA_D63 W25 J27 FBA_CMD30 N21
FBA_CMD30 [78,79]

2
FBA_D63 FBA_CMD30 FBA_CMD31 FBVDDQ
J26 R21
FBA_CMD31 FBVDDQ
T21
FBA_DQM0 FBVDDQ
D19 V21
[78] FBA_DQM0 FBA_DQM1 FBA_DQM0 TP7504 TPAD14-OP-GP FBVDDQ
D14 1 W21
[78] FBA_DQM1 FBA_DQM2 FBA_DQM1 1D35V_VGA_S0 FBVDDQ
C17
[78] FBA_DQM2 FBA_DQM3 FBA_DQM2
C22
[78] FBA_DQM3 FBA_DQM4 FBA_DQM3
P24
[79] FBA_DQM4 FBA_DQM5 FBA_DQM4
W24
[79] FBA_DQM5 FBA_DQM6 FBA_DQM5
AA25
[79] FBA_DQM6 FBA_DQM7 FBA_DQM6 GM108 FBA_DEBUG0 R7501 1
U25 F22 DY 2 60D4R2F-GP
[79] FBA_DQM7 FBA_DQM7 FBA_CMD34 FBA_DEBUG0 FBA_DEBUG1 R7503 1
FBA_CMD35 FBA_DEBUG1 J22 DY 2 60D4R2F-GP

FBA_EDC0 E19
[78] FBA_EDC0 FBA_EDC1 FBA_DQS_WP0
C15
[78] FBA_EDC1 FBA_EDC2 FBA_DQS_WP1 FBA_CLK0P
B16 D24 FBA_CLK0P [78]
[78] FBA_EDC2 FBA_EDC3 FBA_DQS_WP2 FBA_CLK0 FBA_CLK0N
B22 D25 FBA_CLK0N [78]
[78] FBA_EDC3 FBA_EDC4 FBA_DQS_WP3 FBA_CLK0# FBA_CLK1P
R25 N22 FBA_CLK1P [79]
[79] FBA_EDC4 FBA_EDC5 FBA_DQS_WP4 FBA_CLK1 FBA_CLK1N
W23 M22 FBA_CLK1N [79]
[79] FBA_EDC5 FBA_EDC6 FBA_DQS_WP5 FBA_CLK1#
AB26
[79] FBA_EDC6 FBA_EDC7 FBA_DQS_WP6
T26
[79] FBA_EDC7 FBA_DQS_WP7

F19 D18
[78] FBA_DQS_RN0 FBA_DQS_RN0 FBA_WCK01
C14 C18
B [78] FBA_DQS_RN1 FBA_DQS_RN1 FBA_WCK01# B
A16 D17 1D35V_VGA_S0
[78] FBA_DQS_RN2 FBA_DQS_RN2 FBA_WCK23
A22 D16
[78] FBA_DQS_RN3 FBA_DQS_RN3 FBA_WCK23#
[79] FBA_DQS_RN4
P25
FBA_DQS_RN4 FBA_WCK45
T24 Under GPU
W22 U24
[79] FBA_DQS_RN5 FBA_DQS_RN5 FBA_WCK45# R7505
AB27 V24
[79] FBA_DQS_RN6 FBA_DQS_RN6 FBA_WCK67 FB_CAL_PD_VDDQ
[79] FBA_DQS_RN7
T27
FBA_DQS_RN7 FBA_WCK67#
V25 2 OPS 1 D22
FB_CAL_PD_VDDQ
40D2R2F-GP
FB_CAL_PU_GND C24
F16
62mA FB_CAL_PU_GND
FB_PLLAVDD 1D05V_VGA_S0
Under GPU Near GPU FB_CAL_TERM_GND
P22 L7501 B25
FB_PLLAVDD FB_CAL_TERM_GND

FB_PLLAVDD H22
35mA FBA_PLL_AVDD 1 2
FB_DLLAVDD N14M-GE-S-A2-GP
OPS
GF117 GF119/GK208
C7505 C7506 MHC1608S300QBP-GP 71.0N14M.B0U
1

1
OPS OPS C7518 68.00335.051
OPS R7507 R7506 OPS
SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SC22U6D3V5MX-2GP

2nd = 68.00334.051 OPS OPS

51D1R2F-GP
42D2R2F-GP
2

30ohm@100MHZ(ESR=0.01ohm) 1

2
TP7503 1 FB_VREF D23
FB_VREF_PROBE

N14M-GE-S-A2-GP
71.0N14M.B0U Sourcer suggest to change to
68.00335.051 from 68.00084.H41.
OPS

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

GPU_DP/LVDS/CRT/GPIO(3/5)
Size Document Number Rev
A2
Janus HSW 40/50/70 A00
Date: Friday, February 07, 2014 Sheet 75 of 104
5 4 3 2 1
 5 4 3 2 1

30ohm@100MHz
1D05V_VGA_S0 DCR=0.04 ohm
3V3_AON_S0 Max current = 3000mA
GPU1K
3/14 DACA

GF119/GK208
GM108
GF117
GM108
GF117
11 OF 14

GF119/GK208 RN7603
1
L7601

OPS
2
52mA
Straps

SCD1U16V2KX-3GP
W5 B7 I2CA_SCL 3 2 C7605
NC NC

1
DACA_VDD I2CA_SCL I2CA_SDA MHC1608S300QBP-GP C7606 GPU1M 13 OF 14
NC A7 4 1 OPS
AE2
I2CA_SDA DY 68.00335.051 OPS SC2D2U6D3V2MX-GP 9/14 XTAL_PLL 3V3_AON_S0 (DS-06814-001)
DACA_VREF TSEN_VREF NC
SRN2K2J-1-GP 2nd = 68.00334.051

2
AF2 AE3 GPU_PLL_VDD L6
DACA_RSET NC NC DACA_HSYNC CORE_PLLVDD
AE4 L7602 SP_PLLVDD M6
NC 111mA

1
DACA_VSYNC MCB1608S181FBP-GP SP_PLLVDD
1 OPS 2 N6 NC
R7617
VID_PLLVDD 49K9R2F-L-GP
AG3 N6:On co-layout designs,
NC DACA_RED DY
68.00909.261 this ball can be connected GF119/GK208 GF117
AF4 to power rail filter.

2
NC DACA_GREEN
180ohm@100MHz C7601 C7604 C7602

1
AF3 C7603 OPS
NC DACA_BLUE DCR=0.3 ohm

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
OPS DY OPS VIDEO_CLK_XTAL_SS A10 C10 N12P_XTAL_OUTBUFF
Max current = 300mA XTAL_SSIN XTAL_OUTBUFF

2
SC10U6D3V3MX-GP
SC4D7U6D3V3KX-GP
D PDP-06877-006 D
C11 B10
N14M-GE-S-A2-GP XTAL_IN XTAL_OUT

1
71.0N14M.B0U N14M-GE-S-A2-GP

1
71.0N14M.B0U 20PF 5% 50V +/-0.25PF 0402 R7602
49K9R2F-L-GP
OPS OPS R7601 R7603 OPS
10KR2J-3-GP OPS 1MR2J-1-GP

2
27MHZ_IN 1 DY 2 27MHZ_OUT

2
X7601

2
1 4 OPS
R7604 0R2J-2-GP

1
2 3 27MHZ_OUT_R GM:
OPS R7604 = 64.15005.6DL

2
XTAL-27MHZ-85-GP-U GT:
C7607 82.30034.641 C7608 C7607 = 78.18034.1FL
SC15P50V2JN-2-GP 2ND = 82.30034.651 SC15P50V2JN-2-GP (RVL-06891-001)N15V- GM -S DDR3L Recommended Memories

1
OPS 3RD = 82.30034.681 C7608 = 78.22034.1FL
OPS R7604 = 64.18015.6DL

3V3_AON_S0 Strap STRAP3 STRAP2 STRAP1 STRAP0

1
R7613
10KR2J-3-GP R7645 Hynix 0xC H5TC2G63FFR-11C 1 1 0 0
1 2 OPS 10KR2J-3-GP
[73] GPU_PEX_RST#
DY 128Mx16 DDR3L
Micron 0x1 MT41K128M16JT-107G:K 0 0 0 1

2
R7652
1 VIDEO_THERM_OVERT# OVERT# 1 OPS 2 OVERT_GPU#
TP7606
Samsung 0x5 K4W2G1646E-BY11 0 1 0 1

1
0R2J-2-GP
VGA_CORE IC not support ALERT#.
84.2N702.A3F OPS C7609

4
2nd = 84.2N702.E3F SC2700P50V2KX-1-GP

2
Q7602 3rd = 75.00601.07C
2N7002KDW-GP 4th = 84.DMN66.03F 256Mx16 DDR3L Hynix 0x4 H5TC4G63AFR-11C 0 1 0 0
OPS

3
R7653 Micron 0xD MT41K256M16HA-107G:E 1 1 0 1
GPU1N 14 OF 14 3V3_AON_S0 P_H_S#
GPIO9_ALERT
1 OPS 2 PURE_HW_SHUTDOWN# [24,26,36]
8/14 MISC1

1
D9 SMBC_THERM_NV 0R2J-2-GP
I2CS_SCL
I2CS_SDA
D8 SMBD_THERM_NV R7612
DY C7610 Samsung 0x9 K4W4G1646D-BC1A 1 0 0 1
RN7604 1 2 SC2700P50V2KX-1-GP
3V3_AON_S0

2
C A9 I2CC_SCL 3 2 OPS C
I2CC_SCL I2CC_SDA
I2CC_SDA
B9 4 DY 1
10KR2J-3-GP 3V3_AON_S0
GF119 3V3_AON_S0
SRN2K2J-1-GP (DS-06814-001)
P2800_VGA_DXN GF117 GK208
1 E12
TP7603 THERMDN I2CB_SCL 3V3_AON_S0
NC C9 3 2 RN7605
I2CB_SCL
1 P2800_VGA_DXP F12 NC C8 I2CB_SDA 4 DY 1 SRN2K2J-1-GP R7624
THERMDP I2CB_SDA

1
TP7604

4
3
R7633 2 1 Q7601_G
N12P_JTAG_TCK AE5 GC6_20 10KR2J-3-GP
N12P_JTAG_TMS JTAG_TCK 0R0402-PAD RN7601
1 AD6
TP7602 N12P_JTAG_TDI JTAG_TMS
1 AE6 OPS SRN4K7J-8-GP

2
TP7605 N12P_JTAG_TDO JTAG_TDI
1 AF6
TP7601 N12P_JTAG_TRST JTAG_TDO GC6_FB_EN_GPU GPIO5_GC6_PWR_EN_GPU
AG4 C6 Q7601

1
2
JTAG_TRST# (GC6_FB_EN/FB_CLAMP_MON) GPIO0
GPIO1
B2 3V3_MAIN_EN is an open-drain GPIO.
D6 3 4 SMBD_THERM_NV
GPIO2 [18,24,26] SML1_DATA
4
3

C7 3V3_AON_S0
RN7602 GPIO3 R7636
F9 2 5
GPIO4 GPIO5_GC6_PWR_EN_GPU
SRN10KJ-5-GP (3V3_MAIN_EN) GPIO5 A3 1 2 GPIO5_GC6_PWR_EN [83]
OPS A4 GPU_EVENT_GPU# 0R2J-2-GP 83.00400.C1F 1 6
(GPU_EVENT#/FB_CLAMP_TGL_REQ#) GPIO6

1
GK208 GPIO7
B6 GC6_20 2ND = 83.27101.01F
OVERT A6 OVERT_GPU# R7605 3RD = 83.01426.01F 2N7002KDW-GP
1
2

GPIO8 GPIO9_ALERT 100KR2J-1-GP

GPIO9
F8
GPIO10_FBVREF
OPS OPS
C5
GPIO10
E7 D7601

2
GPIO11 PWR_LEVEL VGA_CORE_VID [82] SMBC_THERM_NV
D7 A K AC_PRESENT [17,24]
GPIO12
GPIO13
B4 VGA_CORE_PSI [82] DY [18,24,26] SML1_CLK
1SS400GPT-GP 84.2N702.A3F
R7631 10KR2J-3-GP 2nd = 84.2N702.E3F
GK208 GF117 GF119
3V3_AON_S0 1 2 D7602 3rd = 75.00601.07C
GPIO16 NC GPIO16
D5 GC6_20 A K OVER_CURRENT_P8# [24] 4th = 84.DMN66.03F
GPIO20 NC GPIO20
E6
GPU_PEX_RST_HOLD_GPU# 1
GC6_20 OPS
GPIO8 NC C4 2 R7630 GPU_PEX_RST_HOLD [73] 1SS400GPT-GP
GPIO21 0R2J-2-GP 83.00400.C1F (RVL-06891-001)N15V-
GM108 DA-05691-001_V05 P15
2ND = 83.27101.01F
GT -S DDR3L Recommended Memories
GPIO20/21 NC : for ALL
3RD = 83.01426.01F
N14M-GE-S-A2-GP
71.0N14M.B0U Strap
OPS 3D3V_VGA_S0
GPIO10_FBVREF
GPU1L 12 OF 14 Hynix 0x9 H5TC2G63FFR-11C
2

10/14 MISC2
128Mx16 DDR3L
1

R7626
DY R7610
GF117/GF119/GK208 10KR2J-3-GP
OPS 100KR2J-1-GP Micron 0xA MT41K128M16JT-107G:K
E10 NC
1

VMON_IN0
F10 D12 ROM_CS#
2

VMON_IN1 NC ROM_CS#

ROM_SI
B12 ROM_SI Samsung 0xB K4W2G1646E-BY11
A12 ROM_SO 3V3_AON_S0
STRAP0 ROM_SO
B D1 C12 ROM_SCLK B
STRAP1 STRAP0 ROM_SCLK
D2
STRAP2 E4
STRAP1
STRAP2
Hynix 0x3 H5TC4G63AFR-11C
STRAP3 E3
STRAP3
2

STRAP4 D3
STRAP4 R7643
GF119 GF117 DY 10KR2J-3-GP 256Mx16 DDR3L Micron 0x4 MT41K256M16HA-107G:E
GK208
R7628
C1 NC
1

STRAP5
R7607 D11 BUFRST# 2 OPS 1
40K2R2F-GP BUFRST# SYS_PEX_RST_MON_GPU# Samsung 0x5 K4W4G1646D-BC1A
1 2 STRAP_REF0_GND_N9 F6 NC D10 10KR2J-3-GP
MULTI_STRAP_REF0_GND PGOOD
N15S-GT
GF117 GF117
GF119 GF119
N15V-GS supports Binary Mode. GK208 GK208 R7629
N15S-GT supports Multi-Level Strap. F4
MULTI_STRAP_REF1_GND NC
GPIO8 SYS_PEX_RST_MON_GPU#
GC6_20
NC E9 1 2
CEC 0R2J-2-GP SYS_PEX_RST_MON# [73]
F5 NC
MULTI_STRAP_REF2_GND GF117
GM108
GK208
GF119 Connect to SYS_PEX_RST_MON#
N14M-GE-S-A2-GP if GC62.0 is implemented.
Leave NC for GC6 1.0.
71.0N14M.B0U
NPN-06912 NPN-06975
OPS
3V3_AON_S0 3D3V_S0
2

3V3_AON_S0
2

R7648
Q7606
R7649 10KR2J-3-GP
10KR2J-3-GP G
GC6_20 GC6_20 GC6_20
1

R7623
D
1

GC6_FB_EN GPU_EVENT# [20]

[20,24,75,83] GC6_FB_EN 1 2GC6_FB_EN_GPU
GPU_EVENT_GPU# S
0R2J-2-GP
1

R7627 2N7002K-2-GP
10KR2J-3-GP 84.2N702.J31 Multi Strap:RAM_CFG[3:0]
DY 2ND = 84.2N702.031 3V3_AON_S0
2

N15S-GT_Samsung4Gb N15S-GT_Samsung

GC6_20 3D3V_VGA_S0 N15V-GM-S: Binary Strap for VRAMs.

N15S-GT_Hynix

N15S-GT_Micron

N15S-GT-S: PH 49.9k ohm on STRAP0.

3V3_AON_S0
Reserved for GC6 1.0 (N14P-GV2) R7644
10KR2F-2-GP

4K99R2F-L-GP

1
15KR2F-GP
10KR2F-2-GP

2 DY 1 N15S-GT Samsung/Micron/Micron4Gb/Samsung4Gb
1

1
3D3V_S0
R7608

R7619

R7638

20KR2F-L-GP

49K9R2F-L-GP
R7606 R7615 R7634
1
R7611

10KR2J-3-GP
10KR2J-3-GP 10KR2J-3-GP 10KR2J-3-GP A
10KR2J-3-GP
1

1
R7639

R7625
Q7603 DY DY Samsung/Hynix/Hynix4Gb/Micron4Gb Hynix/Micron4Gb/Samsung4Gb DY
2

1
R7646
2N7002KDW-GP R7650

1
84.2N702.A3F 10KR2J-3-GP
2

2
2nd = 84.DM601.03F DY STRAP2 R7635
2

3rd = 84.2N702.F3F ROM_SCLK DY 10KR2J-3-GP

2

STRAP3
1

2
ROM_SO STRAP0
N15S-GT_Hynix4Gb

N15S-GT_Micron4Gb

1 6

2
STRAP4
4K99R2F-L-GP

10KR2F-2-GP

GC6_FB_EN FB_CLAMP_MON_S ROM_SI STRAP1

4K99R2F-L-GP

24K9R2F-L-GP

30K1R2F-L-GP

2 5
N15S-GT

N15S-GT

N15V-GM
N15V_GM

N15V_GM
R7616

R7614

10KR2F-2-GP

10KR2F-2-GP

20KR2F-L-GP

DY Micron/Samsung/Hynix4Gb
1

3D3V_VGA_S0
R7620

R7618

R7640

R7641

R7642

3 4
1

1
R7651

R7637 R7609 R7632 R7621 <Core Design>

10KR2J-3-GP 10KR2J-3-GP 10KR2J-3-GP 10KR2J-3-GP R7622
2

Micron/Samsung4Gb OPS 10KR2J-3-GP

R7647 Hynix/Hynix4Gb N15V-GM Wistron Corporation
2

10KR2J-3-GP SORx_EXPOSED=0000
2

2
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
DY Taipei Hsien 221, Taiwan, R.O.C.
1

GC6_FB_EN_GPU
Title
No VBIOS ROM
GPU_POWER(4/5)
Size Document Number Rev
Custom
Janus HSW 40/50/70 A00
Date: Monday, February 10, 2014 Sheet 76 of 104
5 4 3 2 1
 5 4 3 2 1

GPU1F 6 OF 14
13/14 GND
A2 M13
GND GND
VGA_CORE AB17 M15
GND GND
AB20 GND GND M17
AB24 GND GND N10
AC2 GND GND N12
Under GPU GPU1E 5 OF 14
AC22 GND GND N14
AC26 GND GND N16
11/14 NVVDD AC5 GND GND N18
K10 VDD AC8 GND GND P11
K12 VDD AD12 GND GND P13
K14 VDD AD13 GND GND P15
C7722 C7708 C7723 C7702 C7701 K16 A26 P17
VDD GND GND

1
K18 VDD AD15 GND GND P2

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP
D DY OPS OPS OPS OPS L11 VDD AD16 GND GND P23 D
L13 AD18 P26

2
VDD GND GND
L15 VDD AD19 GND GND P5
L17 VDD AD21 GND GND R10
M10 VDD AD22 GND GND R12
M12 VDD AE11 GND GND R14
M14 VDD AE14 GND GND R16
M16 VDD AE17 GND GND R18
M18 VDD AE20 GND GND T11
N11 VDD AB11 GND GND T13
N13 VDD AF1 GND GND T15
N15 VDD AF11 GND GND T17
N17 VDD AF14 GND GND U10
P10 AF17 U12
C7709 C7725 C7721 C7720 C7719 VDD GND GND
P12 AF20 U14
VDD GND GND

1
P14 AF23 U16
VDD GND GND
SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP
OPS OPS OPS DY OPS P16
VDD
AF5
GND GND
U18
P18 AF8 U2
2

2
VDD GND GND
R11 AG2 U23
VDD GND GND
R13 AG26 U26
VDD GND GND
R15 AB14 U5
VDD GND GND
R17 B1 V11
VDD GND GND
T10 B11 V13
VDD GND GND
T12 B14 V15
VDD GND GND
T14 B17 V17
VDD GND GND
T16 B20 Y2
VDD GND GND
T18 B23 Y23
VDD GND GND
U11 B27 Y26
VDD GND GND
U13 B5 Y5
VDD GND GND
OPS OPS OPS OPS U15
VDD
B8
GND
U17 E11
VDD GND
1

1
C7714 C7713 C7712 C7711 V10 E14
VDD GND
SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
V12 E17
VDD GND
V14 E2
2

2
VDD GND
V16 E20
VDD GND
V18 E22
VDD GND
E25
GND
C E5 C
N14M-GE-S-A2-GP GND
E8
GND
H2
GND
H23
71.0N14M.B0U H25
GND
GND
H5
GND
OPS K11
GND
Near GPU K13
GND
K15
GND
K17
GND
L10
GND
L12
GND
L14
GND
L16
C7733 C7732 C7731 C7730 C7726 C7724 C7717 C7710 GND
L18
GND
1

DY L2
GND
SC10U6D3V3MX-GP
ST330U2VDM-4-GP

SC22U6D3V5MX-2GP

SC47U6D3V5MX-1-GP
SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

OPS DY OPS OPS OPS OPS OPS L23

GND
L25
2

GND
L5 AA7
GND GND
M11 AB7
GND GND

N14M-GE-S-A2-GP

71.0N14M.B0U

OPS

G10,G12:
B
If GC62.0 is implemented, connect to a 3V3 rail that will be on in GC6. B
If GC62.0 is NOT implemented, connect to the same rail as VDD33.

3V3_AON_S0
GPU1C 3 OF 14
14/14 XVDD/VDD33
3D3V_VGA_S0
AD10 G10
NC#AD10(GM108:3V3_AON) VDD33
AD7
NC#AD7 (GM108:3V3_AON) VDD33
G12 Under GPU Near GPU
B19 G8
NC#B19 FBA_CMD32 VDD33
G9
VDD33
F11
3.3V +/- 5%
3V3AUX
V5 C7734 C7729 C7727
85mA
NC#V5
1

V6 OPS OPS OPS C7728 C7703

NC#V6
SC1U10V2KX-1GP
SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SC4D7U6D3V3KX-GP

OPS
OPS
2

CONFIGURABLE
POWER CHANNELS
* nc on substrate

G1
NC#G1
G2
NC#G2
G3
NC#G3
G4
NC#G4
G5
NC#G5
G6
NC#G6
G7
NC#G7

V1 NC#V1
A V2 A
NC#V2

<Core Design>
W1 NC#W1
W2
W3
NC#W2
NC#W3
Wistron Corporation
W4 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
NC#W4 Taipei Hsien 221, Taiwan, R.O.C.

N14M-GE-S-A2-GP Title

71.0N14M.B0U
GPU_DPPWR/GND(5/5)
Size Document Number Rev
Custom
Janus HSW 40/50/70 A00
OPS Date: Friday, February 07, 2014 Sheet 77 of 104
5 4 3 2 1
 5 4 3 2 1

1D35V_VGA_S0 VRAM1 Place close VRAM1 VDD ball

FBA_D[0..31] [75] 1D35V_VGA_S0 VRAM2 1D35V_VGA_S0
FBA_D0 FBA_D[0..31] [75]
B2 VDD DQ0 E3
D9 F7 FBA_D4 B2 E3 FBA_D21 OPS
VDD DQ1 FBA_D2 VDD DQ0 FBA_D17
G7 VDD DQ2 F2 D9 VDD DQ1 F7 OPS OPS

SC1U6D3V3KX-2GP
C7805
K2 F8 FBA_D7 G7 F2 FBA_D20
VDD DQ3 VDD DQ2

1
K8 H3 FBA_D1 K2 F8 FBA_D16 C7827 C7804
VDD DQ4 VDD DQ3

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
N1 H8 FBA_D5 K8 H3 FBA_D22
VDD DQ5 FBA_D3 VDD DQ4 FBA_D19
N9 G2 N1 H8

2
VDD DQ6 FBA_D6 VDD DQ5 FBA_D23
D R1 VDD DQ7 H7 N9 VDD DQ6 G2 D
1D35V_VGA_S0 R9 D7 FBA_D10 R1 H7 FBA_D18
VDD DQ8 FBA_D13 1D35V_VGA_S0 VDD DQ7 FBA_D30
DQ9 C3 R9 VDD DQ8 D7
A1 C8 FBA_D8 C3 FBA_D25
VDDQ DQ10 FBA_D12 DQ9 FBA_D31
A8 VDDQ DQ11 C2 A1 VDDQ DQ10 C8
C1 A7 FBA_D11 A8 C2 FBA_D26
VDDQ DQ12 FBA_D15 VDDQ DQ11 FBA_D29
C9 VDDQ DQ13 A2 C1 VDDQ DQ12 A7
D2 B8 FBA_D9 C9 A2 FBA_D24
VDDQ DQ14 VDDQ DQ13
E9
F1
VDDQ DQ15 A3 FBA_D14 D2
E9
VDDQ DQ14 B8
A3
FBA_D28
FBA_D27 Place close VRAM2 VDD ball
VDDQ VDDQ DQ15 1D35V_VGA_S0
H2 VDDQ LDQS F3 FBA_EDC0 [75] F1 VDDQ
H9 VDDQ LDQS# G3 FBA_DQS_RN0 [75] H2 VDDQ LDQS F3 FBA_EDC2 [75]
H9 VDDQ LDQS# G3 FBA_DQS_RN2 [75] OPS
UDQS C7 FBA_EDC1 [75] OPS OPS

SC1U6D3V3KX-2GP
C7822
FBA_VREF_0 H1 B7 C7
VREFDQ UDQS# FBA_DQS_RN1 [75] UDQS FBA_EDC3 [75]

1
R7808 M8 FBA_VREF_0 H1 B7 C7820 C7821
VREFCA VREFDQ UDQS# FBA_DQS_RN3 [75]

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
1 OPS 2 FBA_ZQ0 L8 ZQ ODT K1 FBA_CMD2 [75] R7809 M8 VREFCA
243R2F-2-GP 1 OPS 2FBA_ZQ1 L8 K1 FBA_CMD2 [75]

2
243R2F-2-GP ZQ ODT
CS# L2 FBA_CMD0 [75]
[75,79] FBA_CMD9 N3 A0 RESET# T2 FBA_CMD5 [75,79] CS# L2 FBA_CMD0 [75]
[75,79] FBA_CMD11 P7 A1 [75,79] FBA_CMD9 N3 A0 RESET# T2 FBA_CMD5 [75,79]
[75,79] FBA_CMD8 P3 A2 NC#J1 J1 [75,79] FBA_CMD11 P7 A1
[75,79] FBA_CMD25 N2 A3 NC#J9 J9 [75,79] FBA_CMD8 P3 A2 NC#J1 J1
[75,79] FBA_CMD10 P8 A4 NC#L1 L1 [75,79] FBA_CMD25 N2 A3 NC#J9 J9
[75,79] FBA_CMD24 P2 A5 NC#L9 L9 [75,79] FBA_CMD10 P8 A4 NC#L1 L1
[75,79] FBA_CMD22 R8 A6 NC#M7 M7 [75,79] FBA_CMD24 P2 A5 NC#L9 L9
[75,79] FBA_CMD7 R2 A7 NC#T3 T3 FBA_CMD20 [75,79] [75,79] FBA_CMD22 R8 A6 NC#M7 M7
[75,79] FBA_CMD21 T8 A8 NC#T7 T7 FBA_CMD4 [75,79] [75,79] FBA_CMD7 R2 A7 NC#T3 T3 FBA_CMD20 [75,79]
[75,79] FBA_CMD6 R3 A9 [75,79] FBA_CMD21 T8 A8 NC#T7 T7 FBA_CMD4 [75,79]
C L7 R3 C
[75,79] FBA_CMD29 A10/AP [75,79] FBA_CMD6 A9
[75,79]
[75,79]
FBA_CMD23
FBA_CMD28
R7
N7
A11 VSS A9
B3
[75,79]
[75,79]
FBA_CMD29
FBA_CMD23
L7
R7
A10/AP
A9
Place close VRAM1VDDQ ball
A12/BC# VSS A11 VSS Change to 10U 0603 for height limit issue. 1D35V_VGA_S0
VSS E1 [75,79] FBA_CMD28 N7 A12/BC# VSS B3
72.41K26.00U VSS G8 VSS E1
[75,79] FBA_CMD12 M2 BA0 VSS J2 72.41K26.00U VSS G8 OPS
[75,79] FBA_CMD27 N8 BA1 VSS J8 [75,79] FBA_CMD12 M2 BA0 VSS J2

C7813
SC10U6D3V3MX-GP

C7832 SCD1U16V2KX-3GP

C7829 SCD1U16V2KX-3GP

C7831 SCD1U16V2KX-3GP

C7830 SCD1U16V2KX-3GP
[75,79] FBA_CMD26 M3 BA2 VSS M1 [75,79] FBA_CMD27 N8 BA1 VSS J8 OPS OPS OPS OPS OPS OPS OPS

SC1U6D3V3KX-2GP
C7812

SC1U6D3V3KX-2GP
C7810

SC1U6D3V3KX-2GP
C7814
VSS M9 [75,79] FBA_CMD26 M3 BA2 VSS M1

1
VSS P1 VSS M9
[75] FBA_DQM0 E7 LDM VSS P9 OPS VSS P1
[75] FBA_DQM1 D3 T1 [75] FBA_DQM2 E7 P9

2
UDM VSS LDM VSS
OPS VSS T9 [75] FBA_DQM3 D3 UDM VSS T1
VSS T9
[75] FBA_CLK0P J7 CK VSSQ B1
[75] FBA_CLK0N K7 B9 [75] FBA_CLK0P FBA_CLK0P J7 B1
CK# VSSQ FBA_CLK0N CK VSSQ
VSSQ D1 [75] FBA_CLK0N K7 CK# VSSQ B9
[75] FBA_CMD3 FBA_CMD3 K9 D8 D1
CKE VSSQ FBA_CMD3 VSSQ
VSSQ E2 [75] FBA_CMD3 K9 CKE VSSQ D8
VSSQ E8 VSSQ E2
[75,79] FBA_CMD13 L3 WE# VSSQ F9 VSSQ E8
[75,79] FBA_CMD15
[75,79] FBA_CMD30
K3
J3
CAS# VSSQ G1
G9
[75,79] FBA_CMD13
[75,79] FBA_CMD15
L3
K3
WE# VSSQ F9
G1
Place close VRAM1VDDQ ball
RAS# VSSQ CAS# VSSQ 1D35V_VGA_S0
[75,79] FBA_CMD30 J3 RAS# VSSQ G9 Change to 10U 0603 for height limit issue.
Check MT41K256M16HA-107G-E-GP OPS
MT41K256M16HA-107G-E-GP

C7815
SC10U6D3V3MX-GP

C7836 SCD1U16V2KX-3GP

C7833 SCD1U16V2KX-3GP

C7835 SCD1U16V2KX-3GP

C7834 SCD1U16V2KX-3GP
OPS OPS OPS OPS OPS OPS OPS

SC1U6D3V3KX-2GP
C7817

SC1U6D3V3KX-2GP
C7811

SC1U6D3V3KX-2GP
C7816
1

1
B B
Frame Buffer Patition A-Lower Half
FBCLK Termination place on VRAM side

2
1D35V_VGA_S0

FBA_CLK0P
1
1K33R2F-GP
R7806

2
OPS R7810
162R2F-GP
2

FBA_VREF_0
OPS
1
1
SC820P50V2KX-1GP
C7803

1K33R2F-GP
R7807
1

FBA_CLK0N
OPS OPS
2

Layout Note: Place in the end.

2

FBVREF Termination
<Core Design>
A A
Type FBVREF% Voltage GPU_GPIO10
Wistron Corporation
Un-termination 50% 0.749V High 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Termination 70% 1.0617V Low Title

20110613 GPU-VRAM1,2 (1/4)

Size Document Number Rev
A3
Janus HSW 40/50/70 A00
Date: Friday, February 07, 2014 Sheet 78 of 104

5 4 3 2 1
 5 4 3 2 1

1D35V_VGA_S0 VRAM3 1D35V_VGA_S0 VRAM4 Place close VRAM3 VDD ball

FBA_D[32..63] [75] FBA_D[32..63] [75] 1D35V_VGA_S0
B2 E3 FBA_D32 B2 E3 FBA_D41 OPS
VDD DQ0 FBA_D39 VDD DQ0 FBA_D45
D9 VDD DQ1 F7 D9 VDD DQ1 F7

C7910 SCD1U16V2KX-3GP

C7909 SCD1U16V2KX-3GP
G7 F2 FBA_D35 G7 F2 FBA_D43 OPS DY
VDD DQ2 VDD DQ2

SC1U6D3V3KX-2GP
C7906
K2 F8 FBA_D36 K2 F8 FBA_D47
VDD DQ3 VDD DQ3

1
K8 H3 FBA_D34 K8 H3 FBA_D40
VDD DQ4 FBA_D38 VDD DQ4 FBA_D46
N1 VDD DQ5 H8 N1 VDD DQ5 H8
D N9 G2 FBA_D33 N9 G2 FBA_D42 D

2
VDD DQ6 FBA_D37 VDD DQ6 FBA_D44
R1 VDD DQ7 H7 R1 VDD DQ7 H7
1D35V_VGA_S0 R9 D7 FBA_D58 1D35V_VGA_S0 R9 D7 FBA_D49
VDD DQ8 FBA_D61 VDD DQ8 FBA_D53
DQ9 C3 DQ9 C3
A1 C8 FBA_D56 A1 C8 FBA_D51
VDDQ DQ10 FBA_D63 VDDQ DQ10 FBA_D54
A8 VDDQ DQ11 C2 A8 VDDQ DQ11 C2
C1 A7 FBA_D57 C1 A7 FBA_D50
VDDQ DQ12 FBA_D62 VDDQ DQ12 FBA_D55
C9 VDDQ DQ13 A2 C9 VDDQ DQ13 A2
D2 B8 FBA_D59 D2 B8 FBA_D48
VDDQ DQ14 FBA_D60 VDDQ DQ14 FBA_D52
E9 VDDQ DQ15 A3 E9 VDDQ DQ15 A3
F1
H2
VDDQ
F3
F1
H2
VDDQ
F3
Place close VRAM4 VDD ball
VDDQ LDQS FBA_EDC4 [75] VDDQ LDQS FBA_EDC5 [75] 1D35V_VGA_S0
H9 VDDQ LDQS# G3 FBA_DQS_RN4 [75] H9 VDDQ LDQS# G3 FBA_DQS_RN5 [75]

UDQS C7 FBA_EDC7 [75] UDQS C7 FBA_EDC6 [75] OPS

C7913 SCD1U16V2KX-3GP

C7912 SCD1U16V2KX-3GP
FBA_VREF_1 H1 B7 FBA_VREF_1 H1 B7 OPS OPS
VREFDQ UDQS# FBA_DQS_RN7 [75] VREFDQ UDQS# FBA_DQS_RN6 [75]

SC1U6D3V3KX-2GP
C7911
R7912 M8 R7913 M8
VREFCA VREFCA

1
1 OPS 2FBA_ZQ2 L8 ZQ ODT K1 FBA_CMD18 [75] 1 OPS 2FBA_ZQ3 L8 ZQ ODT K1 FBA_CMD18 [75]
243R2F-2-GP 243R2F-2-GP
L2 FBA_CMD16 [75] L2 FBA_CMD16 [75]

2
CS# CS#
[75,78] FBA_CMD9 N3 A0 RESET# T2 FBA_CMD5 [75,78] [75,78] FBA_CMD9 N3 A0 RESET# T2 FBA_CMD5 [75,78]
[75,78] FBA_CMD11 P7 A1 [75,78] FBA_CMD11 P7 A1
[75,78] FBA_CMD8 P3 A2 NC#J1 J1 [75,78] FBA_CMD8 P3 A2 NC#J1 J1
[75,78] FBA_CMD25 N2 A3 NC#J9 J9 [75,78] FBA_CMD25 N2 A3 NC#J9 J9
[75,78] FBA_CMD10 P8 A4 NC#L1 L1 [75,78] FBA_CMD10 P8 A4 NC#L1 L1
[75,78] FBA_CMD24 P2 A5 NC#L9 L9 [75,78] FBA_CMD24 P2 A5 NC#L9 L9
[75,78] FBA_CMD22 R8 A6 NC#M7 M7 [75,78] FBA_CMD22 R8 A6 NC#M7 M7
[75,78] FBA_CMD7 R2 A7 NC#T3 T3 FBA_CMD20 [75,78] [75,78] FBA_CMD7 R2 A7 NC#T3 T3 FBA_CMD20 [75,78]
[75,78] FBA_CMD21 T8 A8 NC#T7 T7 FBA_CMD4 [75,78] [75,78] FBA_CMD21 T8 A8 NC#T7 T7 FBA_CMD4 [75,78]
C
[75,78]
[75,78]
FBA_CMD6
FBA_CMD29
R3
L7
A9 [75,78]
[75,78]
FBA_CMD6
FBA_CMD29
R3
L7
A9 Place close VRAM3 VDDQ ball C

A10/AP A10/AP 1D35V_VGA_S0

[75,78] FBA_CMD23 R7 A11 VSS A9 [75,78] FBA_CMD23 R7 A11 VSS A9
[75,78] FBA_CMD28 N7 A12/BC# VSS B3 [75,78] FBA_CMD28 N7 A12/BC# VSS B3
VSS E1 VSS E1
72.41K26.00U VSS G8 72.41K26.00U VSS G8

C7921 SCD1U16V2KX-3GP

C7922 SCD1U16V2KX-3GP

C7923 SCD1U16V2KX-3GP

C7925 SCD1U16V2KX-3GP
[75,78] FBA_CMD12 M2 BA0 VSS J2 [75,78] FBA_CMD12 M2 BA0 VSS J2 OPS OPS OPS OPS OPS OPS DY OPS

SC1U6D3V3KX-2GP
C7916

SC1U6D3V3KX-2GP
C7915

SC1U6D3V3KX-2GP
C7919

SC10U10V5KX-2GP
C7918
[75,78] FBA_CMD27 N8 BA1 VSS J8 [75,78] FBA_CMD27 N8 BA1 VSS J8

1
[75,78] FBA_CMD26 M3 BA2 VSS M1 [75,78] FBA_CMD26 M3 BA2 VSS M1
VSS M9 VSS M9
P1 OPS P1

2
VSS VSS
[75] FBA_DQM4 E7 LDM VSS P9 [75] FBA_DQM5 E7 LDM VSS P9
[75] FBA_DQM7 D3 UDM VSS T1 [75] FBA_DQM6 D3 UDM VSS T1
VSS T9 VSS T9

[75] FBA_CLK1P J7 OPS B1 [75] FBA_CLK1P FBA_CLK1P J7 B1

CK VSSQ FBA_CLK1N CK VSSQ
[75] FBA_CLK1N K7 CK# VSSQ B9 [75] FBA_CLK1N K7 CK# VSSQ B9
VSSQ D1 VSSQ D1
[75] FBA_CMD19 FBA_CMD19 K9 D8 [75] FBA_CMD19 FBA_CMD19 K9 D8
CKE VSSQ CKE VSSQ
VSSQ E2 VSSQ E2
VSSQ E8 VSSQ E8
[75,78] FBA_CMD13 L3 WE# VSSQ F9 [75,78] FBA_CMD13 L3 WE# VSSQ F9
[75,78] FBA_CMD15 K3 CAS# VSSQ G1 [75,78] FBA_CMD15 K3 CAS# VSSQ G1
[75,78] FBA_CMD30 J3 RAS# VSSQ G9 [75,78] FBA_CMD30 J3 RAS# VSSQ G9
Place close VRAM4 VDDQ ball
1D35V_VGA_S0
MT41K256M16HA-107G-E-GP MT41K256M16HA-107G-E-GP

B B

C7929 SCD1U16V2KX-3GP

C7928 SCD1U16V2KX-3GP

C7930 SCD1U16V2KX-3GP

C7927 SCD1U16V2KX-3GP
OPS OPS OPS OPS DY OPS OPS OPS

SC1U6D3V3KX-2GP
C7917

SC1U6D3V3KX-2GP
C7926

SC1U6D3V3KX-2GP
C7924

SC10U10V5KX-2GP
C7920
1

1
Frame Buffer Patition A-Lower Half
FBCLK Termination place on VRAM side

2
1D35V_VGA_S0
1
1K33R2F-GP
R7903

FBA_CLK1P

2
OPS R7914
2

FBA_VREF_1 162R2F-GP
OPS
1
SC820P50V2KX-1GP
C7902

1K33R2F-GP
R7904

1
1

OPS FBA_CLK1N
OPS
2

Layout Note: Place in the end.

<Core Design>
A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

GPU-VRAM3,4 (2/4)
Size Document Number Rev
A3
Janus HSW 40/50/70 A00
Date: Friday, February 07, 2014 Sheet 79 of 104

5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

<Core Design>
A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

GPU-VRAM5,6 (3/4)
Size Document Number Rev
A3
Janus HSW 40/50/70 A00
Date: Friday, February 07, 2014 Sheet 80 of 104

5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

<Core Design>
A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

GPU-VRAM7,8 (4/4)
Size Document Number Rev
A3
Janus HSW 40/50/70 A00
Date: Friday, February 07, 2014 Sheet 81 of 104

5 4 3 2 1
 5 4 3 2 1

DCBATOUT PWR_DCBATOUT_VGA_CORE2 DCBATOUT PWR_DCBATOUT_VGA_CORE1

PG8201 PG8207
PU8203, PU8205, PU8207 and PU8209 manually change to 84.SRA12.037
1 2 1 2

GAP-CLOSE-PWR GAP-CLOSE-PWR
PG8202 PG8208
PWR_DCBATOUT_VGA_CORE1
1 2 1 2

GAP-CLOSE-PWR GAP-CLOSE-PWR
D PG8203 PG8209 D
1 2 1 2 PC8208 PC8209

1
OPS OPS PC8210 PC8214

2
SCD1U25V2KX-GP
GAP-CLOSE-PWR GAP-CLOSE-PWR PU8202 PU8204 PC8220

SC10U25V5KX-GP

SC10U25V5KX-GP
OPS OPS

SC4D7U25V5KX-GP

SC4D7U25V5KX-GP
PG8204 PG8210
OPS

5
6
7
8

5
6
7
8
SIRA14DP-T1-GE3-GP

SIRA14DP-T1-GE3-GP
5V_S0

2
PWR_VGA_CORE_UGATE1
1 2 1 2

1
D
D
D
D

D
D
D
D
GAP-CLOSE-PWR GAP-CLOSE-PWR 84.A14DP.037

1
PG8205 PG8211
1 2 1 2 PR8223 OPS(65BOM VGA)
DY

G
2D2R3J-2-GP 4 4

S
S
S

S
S
S
GAP-CLOSE-PWR GAP-CLOSE-PWR
PG8206 PG8212
OPS

3
2
1

3
2
1
1 2 1 2 VGA_CORE
RT8812_PVCC
GAP-CLOSE-PWR GAP-CLOSE-PWR
PL8201 OPS

1
PC8202 PC8207 1 2
OPS
2PWR_VGA_CORE_TON_1 SCD1U50V3KX-GP IND-D33UH-7-GP

1
1

2
PT8206 PT8207
OPS PR8216
DY 2D2R5F-2-GP 68.R3310.201

18

5
6
7
8

5
6
7
8

1
SE330U2D5VM-14-GP

SE330U2D5VM-14-GP
SCD1U25V2KX-GP PU8203 PU8205

SIRA12DP-T1-GE3-GP

SIRA12DP-T1-GE3-GP
PU8201
OPS OPS

D
D
D
D

D
D
D
D
84.SRA12.037 84.SRA12.037

PVCC

2
PWR_VGA_SNUB1
PR8202 PR8201 OPS(65BOM VGA) OPS(65BOM VGA)
2 PWR_VGA_CORE_TON PWR_VGA_CORE_UGATE1 N15V_GM_S

1
DCBATOUT OPS
1 2 OPS
1 9 2

G
2D2R2F-GP 499KR2F-1-GP TON UGATE1 4 4 DYPC8206

S
S
S

S
S
S
SC330P50V2KX-3GP
PR8203
PWR_VGA_CORE_BOOT1 1
PR8210
2PWR_VGA_CORE_BOOT1_1 1
Config D

3
2
1

3
2
1

2
3V3_AON_S0 1 OPS 2 13 1 2
PGOOD BOOT1 0R3J-0-U-GP OPS
100KR2J-1-GP PC8211
OPS SCD1U50V3KX-GP Design Current=33.5A
PWR_VGA_CORE_EN 3 20 PWR_VGA_CORE_PHASE1
[15,24,83] DGPU_PWROK EN PHASE1
56.65A <OCP< 66.7A
PWR_VGA_CORE_PSI 4 19 PWR_VGA_CORE_LGATE1
PSI LGATE1 PWR_DCBATOUT_VGA_CORE2
PR8207
[76] VGA_CORE_VID 1 2 1
PR8224
2 OPS OCP setting (current limit ~ 61.5A)
0R0402-PAD
8K06R2F-GP OPS should be in DUMMY column.
Component N15V-GM-S N15-S-GT-S
PC8203 1 SC1KP50V2KX-1GP PWR_VGA_CORE_VID PWR_VGA_CORE_UGATE2 PC8212 PC8213
DY2 5 14 Config D Config B

2
VID UGATE2 OPS OPS

SCD1U25V2KX-GP
PC8215 PC8224 PC8221 value
C C

SC10U25V5KX-GP

SC10U25V5KX-GP
PC8201 PR8211 PU8208
DY OPS OPS OPS

SC4D7U25V5KX-GP

SC4D7U25V5KX-GP
PU8206
PWR_VGA_CORE_RGND 2 SCD1U16V2KX-3GP PWR_VGA_CORE_VREF PWR_VGA_CORE_BOOT2 1 2PWR_VGA_CORE_BOOT2_1 1

PWR_VGA_CORE_UGATE2
1 8 15 OPS 2

1
5
6
7
8
VREF BOOT2 OPS

SIRA14DP-T1-GE3-GP
0R3J-0-U-GP

5
6
7
8
27K 20K

SIRA14DP-T1-GE3-GP
PC8216

D
D
D
D
R1 (PR8222) 64.27025.6DL

D
D
D
D
SCD1U50V3KX-GP 64.20025.6DL
1

PWR_VGA_CORE_REFIN 7 16 PWR_VGA_CORE_PHASE2 84.A14DP.037

R2 PR8206 REFIN PHASE2 R2 (PR8206) 7.5K 20K
7K5R2F-1-GP OPS
R1 DY OPS(65BOM VGA) 64.75015.6DL 64.20025.6DL
PWR_VGA_CORE_REFADJ PWR_VGA_CORE_LGATE2

G
6 17 4 0

G
REFADJ LGATE2 4 R3 (PR8208) 2K

S
S
S
1

63.R0034.1DL

S
S
S
REFIN_VREF
2

PR8222 64.20015.6DL
27KR2F-L-GP

3
2
1
7.87K 18K
R3 PWR_VGA_CORE_SS PWR_VGA_CORE_VSNS

3
2
1
11 12 VGA_CORE R4+R5 (PR8209) 64.78715.6DL 64.18025.6DL
SS VSNS
OPS
1

PR8208 5.6nF 2.7nF

PL8202 OPS C (PC8223)
DY PC8205 PWR_VGA_CORE_RGND
2

1 2 21 10 78.56222.2FL 78.27224.2FL
0R2J-2-GP GND RGND 1 2
SC1KP50V2KX-1GP
2

OPS IND-D33UH-7-GP

1
RT8812AGQW-GP PT8208

5
6
7
8

5
6
7
8
PU8207 PU8209
1

3V3_AON_S0

SIRA12DP-T1-GE3-GP

SIRA12DP-T1-GE3-GP
PR8215

1
OPS PC8223 OPS

D
D
D
D

D
D
D
D

SE330U2D5VM-14-GP
84.SRA12.037 84.SRA12.037 2D2R5F-2-GP
SC5600P25V2KX-1GP 74.08812.073
DY
2

OPS(65BOM VGA) OPS(65BOM VGA)

2
C

2
PWR_VGA_CORE_RGND PR8258 PWR_VGA_SNUB2

G
10KR2J-3-GP 4 4

S
S
S

S
S
S

1
PC8218
OPS OPS

3
2
1

3
2
1
SC330P50V2KX-3GP
2

PR8257
R4+R5 DY

2
1 2 PWR_VGA_CORE_PSI
[76] VGA_CORE_PSI
1

0R0402-PAD
1

PR8209 OPS PC8226

DY
2
SCD1U25V2KX-GP

7K87R2F-GP PC8204 PR8259

10KR2J-3-GP
SCD01U50V2KX-1GP
DY
2

DY
1
PWR_VGA_CORE_RGND

PWR_VGA_CORE_RGND

VGA_CORE
2

1
PR8212
B 100R2F-L1-GP-U B
Check
3D3V_VGA_S0 OPS

2
OPS PR8221
PR8256 1 2
PWR_VGA_CORE_EN VGACORE_VDD_SENSE_1 [73]

1
1 2 PC8222
1KR2J-1-GP 0R0402-PAD

1
PC8219 SC47P50V2JN-3GP
SC47P50V2JN-3GP
2

DY
SCD1U25V2KX-GP

PC8225

2
OPS
2
PR8260 DY PR8220
1

[15,83] DGPU_PWR_EN 1 DY 2 1 2
VGACORE_GND_SENSE_1 [73]

1
PC8217 0R0402-PAD
SC47P50V2JN-3GP

1
13KR2F-GP
DY

2
PR8213
100R2F-L1-GP-U
For tuning VGA_CORE sequence.
OPS

2
I/P cap: 10U 25V K0805 X5R/ 78.10622.51L
Inductor:CHIP CHOKE 0.22UH PCMC104T-R22/ 1mohm/ Isat =60A rms /68.R2210.10C
O/P cap: CHIP CAP EL 330U 2.5V M6.3*4.4 Chemi-con/79.3371V.6CL
H/S: SIRA14DP-T1-GE3 / 6.8mohm/8.5mOhm@4.5Vgs/ 84.A14DP.037
L/S:SIRA06DP-T1-GE3 / 2.75mohm/3.5mOhm@4.5Vgs/ 84.SRA06.037

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

RT8812_VGACORE
Size Document Number Rev
A2
Janus HSW 40/50/70 A00
Date: Friday, February 07, 2014 Sheet 82 of 104
5 4 3 2 1
 5 4 3 2 1

3D3V_VGA_S0
1D05V_VGA_S0
3D3V_VGA_S0 should ramp-up before VGA_Core
VGA_Core should ramp-up before 1D5V_VGA_S0
1D35V_VGA_S0 should ramp-up before 1D05V_VGA_S0
3D3V_VGA_S0
D D

3D3V_S0 to 3D3V_VGA_S0
1D05V_S0 to 1D05V_VGA_S0 VGA_CORE&1D05V_VGA_S0 Discharge Circuit

1
PR8301 1D05V_VGA_S0
1KR2J-1-GP U8301
1D05V_S0
GC6_20 4 13 PG8313 VGA_CORE
5V_S0

2
R8313 VBIAS OUT1#13 1D05V_VGA_OUT2
OUT1#14 14 1 2
1 2 1D05V_VGA_EN 12 VTT_CT_105VC_2
CT1

1
[15,24,82] DGPU_PWROK 3V3_AON_S0 GAP-CLOSE-PWR
1 IN1#1
0R2J-2-GP 2 8 PG8312 3D3V_AUX_S5 PR8317
1D05V_VGA_EN IN1#2 OUT2#8 3D3V_VGA_OUT1 1D05V_VGA_S0 10R2J-2-GP
NON_GC6 2 3 EN1 OUT2#9 9
VTT_CT_3VC_1
1 2
PG8314 DGPU_PWR_EN# OPS
OPS CT2 10 1
OPS2
C8309 C8305 GAP-CLOSE-PWR 1 2

2
1
SCD1U16V2KX-3GP 3D3V_S0 6 C8308 PR8313 D G S
1

IN2#6

1
SC470P50V2KX-3GP
7 11 OPS C8316 C8307 OPS GAP-CLOSE-PWR 100KR2J-1-GP
DY IN2#7 GND

SC10U10V5KX-2GP
5 15 DY VGA_CORE_DISCHG

SCD1U16V2KX-3GP
2
EN2 GND

1
[15,82] DGPU_PWR_EN

SC2200P50V2KX-2GP
OPS

2
PG8315 PQ8305

2
G5016KD1U-GP OPS 10R2J-2-GP
1 2 2N7002KDW-GP
OPS PR8316

D
84.2N702.A3F
1

1
DY C8302 DY C8304 GAP-CLOSE-PWR
074.05016.0093

2
1

2
C8310 2nd = 84.2N702.E3F PQ8307
SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC10U10V5KX-2GP
DY C8306 OPS 3rd = 75.00601.07C S G D 2N7002K-2-GP
2

SCD1U16V2KX-3GP
84.2N702.J31

1
4th = 84.DMN66.03F
OPS
1D05V_VGA_S0_DISCHG

S
G
[15,82] DGPU_PWR_EN

3D3V_S0 3D3V_VGA_S0
Q8302
C Cold Boot/Optimus: 3V3_AON&3V3_MAIN==>NVDD&PEX_1.05V==>FBVDD/Q DMP2130L-7-GP C
GC6 2.0 Exit: 3.3V_MAIN==>NVDD&PEX1.05V DGPU_PWR_EN#
S
D

D
C8311

G
GC6_20 GC6_20

1
R8302 GC6_20

SCD1U16V2KX-3GP

1
GC6_20 10KR2J-3-GP C8301

2
SCD01U50V2KX-1GP C8303
R8303

2
SCD1U16V2KX-3GP

GPIO5_GC6_PWR_EN# 2

2
GPIO5_GC6_PWR_EN_R# 3V3_AON_S0 3D3V_VGA_S0
1 GC6_20
2
DY
0R2J-2-GP
3V3_AON_S0
84.02130.031
R8315 0R2J-2-GP 2nd = 84.00102.031 R8304
1 2
DY 3rd = 84.03413.B31 1 2
3V3_MAIN_EN is an open-drain GPIO. Q8301
G 0R5J-5-GP
[76] GPIO5_GC6_PWR_EN
NON_GC6
1

D
R8301
100KR2J-1-GP DY S GC6_20 GT: R8303 = 0 ohm (63.R0034.1DL); C8301 = 0.01u (78.10324.2FL)
2N7002K-2-GP
2

Could also be used for tuning sequence.

B
1D35V_VGA_S0 AO4468, SO-8
1.35V +/- 3%. B

Id=?A, Qg=9~12nC 1D35V_S3 5.6A 1D35V_VGA_S0

Rdson=17.4~22m ohm PQ8308

8 D S 1
7 D S 2
6 D S 3
1

D PC8307
1D35V_VGA_S0 5 1D35V_VGA_S0
1

SC10U6D3V3MX-GP
PC8303 G 1D35V_VGA_S0
4

SC10U6D3V3MX-GP SIRA06DP-T1-GE3-GP
2

84.SRA06.037
2nd = 84.08057.037
3D3V_AUX_KBC 1D35V_ENABLE_RC
R8314
DY 1D35V_VGA_EN#
1 2 1D35V_VGA_S0
1 2
1D35V_VGA_S0
PR8314
Discharge Circuit
1

100KR2J-1-GP PC8302 750KR2J-GP

3D3V_AUX_S5 SCD01U50V2KX-1GP
1D35V_VGA_S0
1

OPS OPS
2

1 2
10R2J-2-GP
PR8311 D G S PR8315
100KR2J-1-GP
2

OPS
6

DIS_1D35V_VGA_S0
PQ8304 15V_S5 DCBATOUT
2nd = 83.R2003.W81 2N7002KDW-GP
84.2N702.A3F
3rd = 75.00054.A7D
D
1

A
2nd = 84.2N702.E3F A
4th = 83.R2003.V81 3rd = 75.00601.07C S G D PR8312 PQ8306
D8301 DY PR8310 330KR2J-L1-GP 2N7002K-2-GP
4th = 84.DMN66.03F <Core Design>
1 100KR2J-1-GP
[20,24,75,76] GC6_FB_EN 1D35V_VGA_S0 84.2N702.J31
OPS
1

GC6_20 3 1D35V_VGA_EN
75.00054.E7D Wistron Corporation
2 1D35V_ENABLE 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
S
G

[15,24,82] DGPU_PWROK Taipei Hsien 221, Taiwan, R.O.C.

BAT54C-7-F-3-GP
1D35V_VGA_EN# Title
1 2 1D35V_VGA_EN [51] DISCRETE VGA POWER
R8312
0R2J-2-GP 1 2 Size Document Number Rev
NON_GC6 R8305 GC6_20
1MR2J-1-GP
Custom Janus HSW 40/50/70 A00
Date: Monday, February 10, 2014 Sheet 83 of 104

5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
Janus HSW 40/50/70 A00
Date: Friday, February 07, 2014 Sheet 84 of 104
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
Janus HSW 40/50/70 A00
Date: Friday, February 07, 2014 Sheet 85 of 104
5 4 3 2 1
 5 4 3 2 1

SSID = Mechanical
H5 H6 H4
H2 H1 H3
HOLE335R115-GP HT85BE85R29-U-5-GP HT85BE85R29-U-5-GP HOLE335R115-GP HOLE335R115-GP HOLE256R115-GP
S1 S2
STF237R117H83-1-GP STF237R117H83-1-GP
1

1
34.4CK01.001 34.4CK01.001
D D
2nd = 34.4CK01.601 2nd = 34.4CK01.601 ZZ.00PAD.D01 ZZ.00PAD.D01 ZZ.00PAD.D11
3rd = 34.4CK01.501 3rd = 34.4CK01.501
ZZ.00PAD.D41 ZZ.00PAD.D41
ZZ.00PAD.D01

SPR2 SPR3 SPR4

SPR5
C1 C2 C3
SPRING-102-GP SPRING-102-GP SPRING-63-GP SPRING-43-GP-U HOLE197R166-1-GP HOLE197R166-1-GP HOLE197R166-1-GP
1

1
34.41V01.001 34.41V01.001 34.4Y806.001 34.15J03.001 ZZ.00PAD.V71 ZZ.00PAD.V71 ZZ.00PAD.V71

C C

SSID = EMI
Mind the voltage rating of the caps.
AUD_AGND
DCBATOUT 1D35V_VGA_S0

EC9708 EC9709 EC9710 EC9727 EC9725 EC9726 EC9730 EC9728 EC9729 EC9731 EC9739 EC9744 EC9743 EC9745
1

1
EC9701 EC9702 EC9703 EC9704 EC9705 EC9706 EC9707
DY DY DY DY DY DY DY DY DY DY DY DY DY DY
SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC1KP50V2KX-1GP
SC1KP50V2KX-1GP

SC1KP50V2KX-1GP

SC1KP50V2KX-1GP
2

2
SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP
EC9711 EC9714
1

EC9717 EC9712 EC9713 EC9716 EC9715

B B
DY DY DY DY DY DY
SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP
SC1KP50V2KX-1GP

SC1KP50V2KX-1GP
2

DCBATOUT

EC9740 EC9741 EC9742 EC9747 EC9748 EC9749

2
DY

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP
DY DY DY DY DY

SCD1U25V2KX-GP

SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
2

1
5V_S0

EC9720 EC9719 EC9718 EC9723 EC9721 EC9722 EC9724

1

DY DY DY DY DY DY DY
SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP
SC1U10V2KX-1GP

SC1U10V2KX-1GP
2

3D3V_S0 5V_S5

EC9737 EC9735 EC9736 EC9738 EC9734 EC9732 EC9733

1

1
A <Core Design> A
DY DY DY DY DY DY DY
SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP
2

2
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

UNUSED PARTS/EMI Capacitors

Size Document Number Rev
A3
Janus HSW 40/50/70 A00
Date: Friday, February 07, 2014 Sheet 86 of 104
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
Janus HSW 40/50/70 A00
Date: Friday, February 07, 2014 Sheet 87 of 104
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
Janus HSW 40/50/70 A00
Date: Friday, February 07, 2014 Sheet 88 of 104
5 4 3 2 1
 5 4 3 2 1

D D

C (Blanking) C

B B

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
(Reserved)Finger Print
Size Document Number Rev
A4
Janus HSW 40/50/70 A00
Date: Friday, February 07, 2014 Sheet 89 of 104
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Free Fall Sensor

Size Document Number Rev
A3
Janus HSW 40/50/70 A00
Date: Friday, February 07, 2014 Sheet 90 of 104
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
Janus HSW 40/50/70 A00
Date: Friday, February 07, 2014 Sheet 91 of 104
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
Janus HSW 40/50/70 A00
Date: Friday, February 07, 2014 Sheet 92 of 104
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

<Core Design>
A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Express Card
Size Document Number Rev
A3
Janus HSW 40/50/70 A00
Date: Friday, February 07, 2014 Sheet 93 of 104

5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

<Core Design>
A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

LVDS_Switch
Size Document Number Rev
A3
Janus HSW 40/50/70 A00
Date: Friday, February 07, 2014 Sheet 94 of 104

5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

<Core Design>
A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CRT_Switch
Size Document Number Rev
A3
Janus HSW 40/50/70 A00
Date: Friday, February 07, 2014 Sheet 95 of 104

5 4 3 2 1
 5 4 3 2 1

SSID = XDP
CPU XDP

D D

CFG[19:0]
[6] CFG[19:0]
XDP_BPM[7:0]
[4] XDP_BPM[7:0]
XDP_PREQ# 1 TP9601 TPAD14-OP-GP
[4] XDP_PREQ#

[4] XDP_PRDY# XDP_PRDY# 1 TP9602 TPAD14-OP-GP

[4] XDP_TDO XDP_TDO 1 TP9624 TPAD14-OP-GP
[4] XDP_TRST# XDP_TRST# 1 TP9621 TPAD14-OP-GP
[4] XDP_TDI XDP_TDI 1 TP9623 TPAD14-OP-GP
XDP_TMS 1 TP9611 TPAD14-OP-GP
[4] XDP_TMS
XDP_BPM0 1 TP9612 TPAD14-OP-GP
XDP_BPM1 1 TP9613 TPAD14-OP-GP
XDP_BPM2 TP9614 TPAD14-OP-GP
[7] H_VCCST_PWRGD R9601 1 DY 2 1KR2J-1-GP VCCST_PWRGD_XDP 1 TP9648 TPAD14-OP-GP XDP_BPM3
1
1 TP9615 TPAD14-OP-GP
R9603 1 2 0R2J-2-GP BP_PWRGD_RST# TP9645 TPAD14-OP-GP XDP_BPM4 TP9616 TPAD14-OP-GP
[17,24] PM_PWRBTN# DY 1
XDP_BPM5
1
1 TP9617 TPAD14-OP-GP
R9604 1 2 0R2J-2-GP XDP_PWR_DEBUG TP9647 TPAD14-OP-GP XDP_BPM6 TP9618 TPAD14-OP-GP
C
[7] PWR_DEBUG R9605 1 DY 2 0R2J-2-GP XDP_SYS_PWROK
1
1 TP9644 TPAD14-OP-GP XDP_BPM7
1
1 TP9619 TPAD14-OP-GP
C

[17,24] SYS_PWROK RN9601

DY1 4 XDP_SMBDAT 1 TP9646 TPAD14-OP-GP
[12,18,62] PCH_SMBDATA
2 DY 3 XDP_SMBCLK 1 TP9649 TPAD14-OP-GP CFG0 1 TP9626 TPAD14-OP-GP
[12,18,62] PCH_SMBCLK
CFG1 1 TP9627 TPAD14-OP-GP
[4] XDP_TCLK SRN0J-6-GP XDP_TCLK 1 TP9650 TPAD14-OP-GP CFG2 1 TP9620 TPAD14-OP-GP
CFG3 1 TP9622 TPAD14-OP-GP
CFG4 1 TP9630 TPAD14-OP-GP
[18] PCIE_CLK_XDP_P PCIE_CLK_XDP_P 1 TP9652 TPAD14-OP-GP CFG5 1 TP9631 TPAD14-OP-GP
[18] PCIE_CLK_XDP_N PCIE_CLK_XDP_N 1 TP9651 TPAD14-OP-GP CFG6 1 TP9629 TPAD14-OP-GP
CFG7 1 TP9628 TPAD14-OP-GP
0R2J-2-GP 2 1 R9602 XDP_RST TP9654 TPAD14-OP-GP CFG17 TP9634 TPAD14-OP-GP
[17,24,30,36,52,58,65,73] PLT_RST# DY XDP_DBRESET#
1
1 TP9653 TPAD14-OP-GP CFG16
1
1 TP9635 TPAD14-OP-GP
[17] XDP_DBRESET# C9602 CFG8 TP9633 TPAD14-OP-GP
1
1

DY CFG9 1 TP9632 TPAD14-OP-GP

SCD1U16V2KX-3GP

CFG10 1 TP9637 TPAD14-OP-GP

CFG11 1 TP9639 TPAD14-OP-GP
2

CFG19 1 TP9638 TPAD14-OP-GP

CFG18 1 TP9636 TPAD14-OP-GP
B CFG12 1 TP9640 TPAD14-OP-GP B
CFG13 1 TP9643 TPAD14-OP-GP
CFG14 1 TP9642 TPAD14-OP-GP
CFG15 1 TP9641 TPAD14-OP-GP

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU/PCH XDP
Size Document Number Rev
A4
Janus HSW 40/50/70 A00
Date: Friday, February 07, 2014 Sheet 96 of 104
5 4 3 2 1
 5 4 3 2 1

Shark Bay Platform Power Sequence

(DC mode) Red Words: Controlled by EC GPIO

+RTC_VCC t01 >9ms

RTC_RST#

DCBATOUT

3D3V_AUX_S5
D D

Sense the power button status

Press Power button
KBC_PWRBTN# Platform to KBC PSL_IN2
PSL_OUT#(GPIO71) keep low
3D3V_AUX_KBC
KBC GPIO34 control power on by 3V_5V_EN
S5_ENABLE

5V_S5
V5REF_Sus must be powered up before
5V_S5 & 3D3V_S5 need meet 0.7V difference
VccSus3_3, or after VccSus3_3 within
0.7 V. Also, V5REF_Sus must power
3D3V_S5
down after VccSus3_3, or before
5V_S5 & 3D3V_S5 need meet 0.7V difference
VccSus3_3 within 0.7 V.
+5VA_PCH_VCC5REFSUS Ta
KBC GPIO43 to PCH
PM_RSMRST#(RSMRST#_RST) t05 >10ms
In case of a non-Deep S4/S5 Platform
t07 >100ms PCH to KBC GPIO00
timing t42 should be added to t07
which will make it 100mS minimum.
PCH_SUSCLK_KBC

KBC GPIO20 to PCH

PM_PWRBTN#

DC PM_PWRBTN#
After Power Button
PCH to KBC GPIO44
PM_SLP_S4#
t10 PCH to KBC GPIO01
PM_SLP_S3# >30us
KBC GPIO47 to LAN
PM_LAN_ENABLE
Enable by PM_SLP_S4#
1D5V_S3
C C
DDR_VREF_S3(0.75V)
5V_S0 & 3D3V_S0 need meet 0.7V difference
5V_S0

V5REF must be powered up before 3D3V_S0

Vcc3_3, or after Vcc3_3 within 0.7
V. Also, V5REF must power down
after Vcc3_3, or before Vcc3_3
within 0.7 V. +5VS_PCH_VCC5REF Tb

1D5V_S0

1D8V_S0

0D75V_S0
1D8V_S0 & 1D5V_S3 power ready
RUNPWROK

1D05V_PCH

VCCP_CPU

1D05_VTT_PWRGD

0D85V_S0

0D85V_S0
D85V_PWRGD

SetVID ACK
CPU SVID BUS 50us< t36 <2000us

VCC_CORE

VCC_GFXCORE
t37
<5ms
IMVP_PWRGD
B B

PCH_CLOCK_OUT

This signal represents the Power

ALL_SYS_PWRGD=D85V_PWRGD t14 >99ms KBC GPIO77 to PCH
Good for all the non-CORE and
non-graphics power rails.
PWROK(S0_PWR_GOOD)
t18
D85V_PWRGD >0us PCH to CPU
DRAMPWROK(VDDPWRGOOD) 2ms<t17 <650ms
t19 >1ms
t20 >2ms
1D8V_S0
5ms<t13 <650ms PCH to CPU
UNCOREPWRGOOD(H_CPUPWRGD)

SYS_PWROK t21+t22 >1ms+60us

1ms< t25 <100ms PCH to all system
PLT_RST#
t39 <200us
DMI

N14P-GT Power-Up/Down Sequence

3D3V_S0
PCH GPIO54 output
DGPU_PWR_EN#(Discrete only)

3D3V_VGA_S0(VDD33)

A
8209A_EN/DEM_VGA(Discrete only) A

VGA_CORE(NVVDD) tNVVDD >0ms

RT8208 PGOOD
DGPU_PWROK(Discrete only)

1D5V_VGA_S0(FBVDDQ) tNV-FBVDDQ >0ms

1D05V_VGA_S0(PEX_VDD) tNV-PEX_VDD >0ms

First rail to power down VGA_CORE,1D05V_VGA_S0 <Core Design>

1D5V_VGA_S0,3D3V_VGA_S0
Last rail to power down Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
tPOWER-OFF <10ms Taipei Hsien 221, Taiwan, R.O.C.

Title

Power Sequence
Size Document Number Rev
For power-down, reversing the ramp-up sequence is recommended. A1
Janus HSW 40/50/70 A00
Date: Friday, February 07, 2014 Sheet 97 of 104
5 4 3 2 1
 5 4 3 2 1

Wistron SHARK BAY POWER UP SEQUENCE DIAGRAM

D D

DC 3
BT+ SWITCH
Battery PM_SLP_S4#
Page43 Page44

-7 -3 DCBATOUT
AC +DC_IN SWITCH DCBATOUT
Adapter in S5_ENABLE 3a
Page44 4a
Page42 VIN 1D35V_S3
SW
VIN 1D05V_S0
AD+ SW

4 TPS51367
-5 EN1 EN2 RUNPWROK
3D3V_S5 TPS51367 EN PGOOD
PM_SLP_S3# RUNPWROK Page48
Charger EN PGOOD
DCBATOUT TPS51225CRUKR Page48 4b
BQ24715 VIN
DC/DC -2 4b
(3.3V/5V) 5V_S5
ACOK Page44 1D35V_S3
Page41

3D3V_AUX_S5 RUNPWROK 5V_S0

4 SWITCH
Page36
DDR_VTT_PG_CTRL 0D675V_S0
C
-4 SWITCH TPS51206 C

Page24 Page46
RUNPWROK 3D3V_S0
-6 SWITCH
3D3V_AUX_KBC -3 4b Page36
5
AC_IN S5_ENABLE 7
PSL_IN1# GPIO34
DDR_PG_CTL RUNPWROK Level H_VCCST_PWRGD
1 H_VR_ENABLE Shifter
VR_EN
Page7
KBC_PWRBTN# -1
PSL_IN2# KBC DPWROK H_CPU_SVIDDAT
VIDSOUT
PM_SLP_S4#
NPCE985 GPIO43
RSMRST#_KBC
RSMRST# Haswell ULT CPU
GPIO8 PM_PWRBTN# 11
PM_SLP_S3#
GPIO01
GPIO20 PWRBTN#
with
3D3V_S5
GPIO80 2 Lynx Point PCH
Page24 12 4a
SLP_S3# de-assert, delay 20ms; APWROK PCI_PLTRST# 4 VIN 1D5V_S0
PCH_PWROK assert. PLTRST# VOUT
10 S0_PWR_GOOD
6 PCH_PWROK VCCST_PWRGD SYS_PWROK VR_READY PM_SLP_S3# TPS51312 RUNPWROK
SLP_S3# de-assert, delay 200ms; EN PGOOD
S0_PWR_GOOD assert. Page51

5 4b
PCH_PWROK H_VCCST_PWRGD
B B

SYS_PWROK be asserted after S0_PWR_GOOD

assertion and CPU core VR power good
assertion.
11
S0_PWR_GOOD
H_CPU_SVIDDAT
VDIO

TPS51622 9
7 H_VR_ENABLE IMVP_PWRGD
VR_ON PGOOD

Page46

PWR_VCC_PWM1

DCBATOUT 8
CSD97374
VCC_CORE
VSW
Page47

A A

<Core Design>

1 2 3a 4 4a 4b 5 6 7 8 9 10 11 12
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Power Sequence Diagram

Size Document Number Rev
A2
Janus HSW 40/50/70 A00
Date: Friday, February 07, 2014 Sheet 98 of 104
5 4 3 2 1
 5 4 3 2 1

DCBATOUT
Adapter
RT8237 TPS51216RUKR ISL95813 AP3211
D D

Charger
1D05V_S0
BQ24717
1D35V_S3 0D675V_S0 VCC_CORE VGA_CORE
Battery +PBATT

TPS22966 TLV70215 SIRA06DP

1D05V_VGA_S0 1D5V_S0 1D35V_VGA_S0

C C

TPS51125ARGER

15V_S5 3D3V_AUX_S5 5V_AUX_S5 5V_S5 3D3V_S5

TPS22966
AP2182SG AP2301M8G TPS22966 AO3403
TLV70215

3D3V_S0
USB30_VCCA +5V_USB1 5V_S0 3D3V_LAN_S5
USB30_VCCB 1D5V_S0
B B

SY6288

ODD_PWR_5V
RT9724 TPS22966
Power Shape

LCDVDD 3D3V_VGA_S0
Regulator LDO Switch

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number

Power Block Diagram Rev
A3
Janus HSW 40/50/70 A00
Date: Friday, February 07, 2014 Sheet 99 of 104
5 4 3 2 1
 A B C D E

PCH SMBus Block Diagram KBC SMBus Block Diagram

3D3V_S5_PCH 3D3V_S0
TP_VDD
‧ ‧
3D3V_S0 ‧
SRN2K2J-1-GP SRN10KJ-5-GP
‧
DIMM 1 SRN10KJ-5-GP

1 SMBCLK SMB_CLK
‧ ‧PCH_SMBCLK 1

SMBDATA SMB_DATA
‧ ‧ PCH_SMBDATA
SCL

SDA
TouchPad Conn.
PSDAT1 TPDATA
‧ TPDATA TPDATA

SMBus Address:0xA0/0xA1 PSCLK1 TPCLK

‧ TPCLK TPCLK
2N7002SPT
3D3V_AUX_KBC

TPAD
PCH_SMBCLK
SCL
‧
PCH_SMBDATA
3D3V_S5_PCH SDA
SRN4K7J-8-GP
SMBus Address:0x58/0x59
‧
SRN33J-7-GP Battery Conn.
GPIO17/SCL1 ‧‧BAT_SCL PBAT_SMBCLK1 CLK_SMB
SRN2K2J-1-GP PTN3355 GPIO22/SDA1 BAT_SDA PBAT_SMBDAT1 DAT_SMB SMBus address:16
PCH_SMBCLK
VDDA33_DP
‧ ‧
PCH_SMBDATA
TMS (Janus Only)
SML0CLK SML0_CLK

SML0DATA SML0_DATA SMBus Address:0xC0H/0x40H HPA02224RGRR

SCL
KBC SDA SMBus address:12
NPCE285P
2 2

GPIO73/SCL2

GPIO74/SDA2

PCH 3D3V_S0 SMBus Address:

3D3V_S5_PCH 0x94/0x95/0x96/0x97
‧
3D3V_S0
SRN2K2J-8-GP

‧ SRN2K2J-8-GP

SML1CLK ‧ ‧ SML1_CLK
‧ THM_SML1_CLK
SCL Thermal
‧ ‧ SML1_DATA ‧ THM_SML1_DATA
SML1DATA SDL
NCT7718W
SMBus Address:0x82/0x83 SMBus Address:0x98/0x99
2N7002SPT
3D3V_VGA_S0

‧SRN4K7J-8-GP
3D3V_VGA_S0

‧
dGPU
3 3

SMBC_Therm_NV I2CS_SCL
‧
SMBD_Therm_NV I2CS_SDA
‧
SMBus Address:0x9E/0x9F

3D3V_S0 5V_S0

0R2J-2-GP
‧ ‧ DY
3D3V_S0
SRN2K2J-1-GP SRN2K2J-1-GP GPIO47/SCL4A PROCHOT_EC
‧ ‧ H_PROCHOT_EC
GPIO53/SDA4A LCD_TST_EN LCD_TST_EN
‧ ‧
0R2J-2-GP
DDPB_CTRLCLK ‧PCH_HDMI_CLK DDC_CLK_HDMI ‧ LCD_TST
DDPB_CTRLDATA
‧ PCH_HDMI_DATA ‧‧ DDC_DATA_HDMI ‧ HDMI CONN
2N7002DW-1-GP

4 4

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

SMBUS Block Diagram

Size Document Number Rev
A2 Janus HSW 40/50/70 A00
Date: Friday, February 07, 2014 Sheet 100 of 104
A B C D E
 5 4 3 2 1
CLK Block Diagram

Intel CPU
D Haswell/Broadwell ULT D
M_A_DIMA_CLK_DDR0
CK0 SA_CLK0
M_A_DIMA_CLK_DDR#0
CK0# SA_CLK#0
DDR3L DIMM1
M_A_DIMA_CLK_DDR1
CK1 SA_CLK1
M_A_DIMA_CLK_DDR#1
CK1# SA_CLK#1 CLK_PCIE_WLAN_P3
CLKOUT_PCIE_P2 REFCLKP0
WLAN
CLK_PCIE_WLAN_N3
CLKOUT_PCIE_N2 REFCLKN0 NGFF

LAN
CLK_PCIE_LAN_P4
RTL8106E/RTL8111G
CLKOUT_PCIE_P3 REFCLK_P

FBA_CLK0P CLK_PCIE_LAN_N4
CK CLKOUT_PCIE_N3 REFCLK_N
C VRAM1 FBA_CLK0N
VGA C
CK#
N15V-GM-S-A2
LANXIN
FBA_CLK0P
GB2-64 (23x23) CKXTAL1
CLK_PCIE_VGA#
CK
FBA_CLK0N ‧ FBA_CLK0 PEX_REFCLK# CLKOUT_PCIE_N4
VRAM2 CK# ‧ FBA_CLK0# X3001
25MHz
CLK_PCIE_VGA
PEX_REFCLK CLKOUT_PCIE_P4
LANXOUT
CKXTAL2
FBA_CLK1P
CK 27MHZ_IN
XTAL_IN
VRAM3 CK#
FBA_CLK1N

X7601
27MHz
FBA_CLK1P
CK
FBA_CLK1N ‧ FBA_CLK1
27MHZ_OUT Audio
VRAM4 CK# ‧ FBA_CLK1# XTAL_OUT

RN2102
Realtek
HDA_BITCLK HDA_CODEC_BITCLK
HDA_BCLK/I2S0_SCLK BITCLK ALC3223
SRN33J-5-GP-U

B RTC_X1
RTCX1 B

X1901
R5815
0R2J-2-GP
SUSCLK_NGFF
SUS_CLK NGFF
32.768KHz

RTC_X2
RTCX2
XTAL24_IN KBC
XTAL24_IN
NPCE285P
SUS_CLK_PCH R1710 SUS_CLK R2441 SUS_CLK_KBC
X1801 SUSCLK/GPIO62
0R2J-2-GP ‧ 0R2J-2-GP
GPIO0/EXTCLK/F_SDIO3
24MHz CLK_PCI_KBC_R R1805 CLK_PCI_KBC
CLKOUT_LPC_1 LCLK/GPIOF5
0R2J-2-GP
XTAL24_OUT CLKOUT_LPC_0 CLK_PCI_LPC_R R1804 CLK_PCI_LPC
XTAL24_OUT 0R2J-2-GP
LPC

CLKOUT_ITPXDP#
CLKOUT_ITPXDP_P
Test Point

A A
<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
CLK Block Diagram
Size Document Number Rev
A2
Janus HSW 40/50/70 A00
Date: Friday, February 07, 2014 Sheet 101 of 104

5 4 3 2 1
 A B C D E

Thermal Block Diagram Audio Block Diagram

1 1

3D3V_S5_PCH 3D3V_S0
PAGE28 D+ NCT7718_DXP
PCH MMBT3904-3-GP
SPKR_L+
SPKR_L-

D- NCT7718_DXN
SC2200P50V2KX-2GP SPKR_R-
SPKR_R+ SPEAKER
Thermal Place near CPU
SML1_DATA THM_SML1_DATA
NCT7718 PWM CORE
Codec
SML1DATA/GPIO74 ‧ ‧‧ 2N7002 ‧ SDA

SML1CLK/GPIO75 SML1_CLK
‧‧ ‧ THM_SML1_CLK
‧ SCL
MMBT3904-3-GP
ALC3223
T8 AUD_HP1_JACK_L HP MIC
SML1_DATA

AUD_HP1_JACK_R
SML1_CLK

PAGE20
3D3V_S0
T_CRIT# THERM_SYS_SHDN#
2N7002
S
D
PURE_HW_SHUTDOWN#

PCH_PWROK
EN 3V/5V SLEEVE COMBO
G RING2
2 2
‧ Put under CPU(T8 HW shutdown)

PAGE27 GPIO74
PAGE86

KBC GPIO73
R2714
Digital
NPCE285P 2N7002
SMBD_THERM_NV I2CS_SCL
VGA GPIO0/DMIC_DATA
DMIC_DATA_R
0R2J-2-GP
DMIC_DATA
MIC
SMBC_THERM_NV I2CS_SDA DMIC_CLK_R R2716 DMIC_CLK
GPIO1/DMIC_CLK
0R2J-2-GP

GPIO4
N15V-GM-S-A2
GPIO94 GPIO56
GB2-64 (23x23)
FAN_TACH1
FAN1_DAC_1

3 3
TACH

FAN
VIN
FAN_VCC1

5V

VIN VSET VOUT

FAN CONTROL
APL5606AKI
PAGE28

4 4
<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size
Thermal/Audio Block Diagram
Document Number Rev
Custom
Janus HSW 40/50/70 A00
Date: Friday, February 07, 2014 Sheet 102 of 104
A B C D E
 5 4 3 2 1

Change notes -
DATE VERSON DATE Page Modify List OWNER

D D

C C

B B

<Core Design>
A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Change History
Size Document Number Rev
A3
Janus HSW 40/50/70 A00
Date: Friday, February 07, 2014 Sheet 103 of 104

5 4 3 2 1
 5 4 3 2 1
VERSION DATA PAGE Change Iteam

D D

C C

B B

<Core Design>
A A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Change History
Size Document Number Rev
A3
Janus HSW 40/50/70 A00
Date: Friday, February 07, 2014 Sheet 104 of 104