Basic Electronics Engineering

(ECT 101)
(B Tech I semester)

Course File
(2019-20 Odd Semester)

Department of Electronics and Communication Engineering

Malaviya National Institute of Technology, Jaipur
Jaipur-India, 302017
 Basic Electronics Engineering
COURSE FILE

Program : Bachelor of Technology

Semester : I

Course Code : ECT 101

Approved By

HoD
Electronics and CommunicationEngineering

2
 CONTENTS

1. SYLLABUS
2. REFERENCES
3. COURSE OUTCOMES
4. COURSE FLOW CHART
5. COURSE OUTCOME EVALUATION
6. QUESTION PAPER MODRATION
7. LECTURE PLAN
8. ASSIGNMENTS
9. PREVIOUS YEARS EXAMINATION PAPERS
10. MoIs OF THE PREVIOUS PAPERS

3
 1. SYLLABUS (Module wise)

Semester: I Code: ECT 101

Subject: Basic Electronics Engineering Credits: L-T-P: 3-1-0
Total Theory Periods: 36 Total Tutorial Periods: 00
Marks: 100, 30 in Mid-Term, 50 in End-Term, 20 marks assignments

Module 1[Total 14 Marks, MT 10, ET 4, Lectures: 08]

Diode Circuits: Band structure of insulators, Metals & Semiconductors, mobility, conductivity, doping,
Electrons and holes in an intrinsic semiconductor. Donor and acceptor impurities, charge densities in a
semiconductor, Hall Effect. Current components in diode, Zener diode and applications. Single phase
rectifier (half -wave and full -wave rectifier) & their analysis, comparison of half -wave and full -wave
rectifiers, comparison of bridge and centre -tap rectifier, various types of filter (Capacitor filter, Inductor
Filter, Choke -Input LC filter, π filter), clipping circuits (series and shunt) & clamping circuits..

Module 2[Total 08 Marks, MT 8, ET 0, Lectures: 03]

BipolarJunctionTransistors(BJT): Bipolar
JunctionTransistor,Currentcomponentsintransistor,transistorconstruction,ThetransistorasanAmplifier,
various configurations (CE, CB. CC) and characteristics (Inputand Output) of BJT's configurations, cut
off, saturation and active region,Early effect, analytical expression for transistor characteristics (Ebers-
MollModel).

Module 3[Total 15 Marks, MT 2, ET 13, Lectures: 07]

Transistor Biasing & Stabilization:Operating point. DC &AC load line, biased stability, various types
of transistor biased circuits (Fixed bias circuit,Fixed -biaswithemitterresistor,self -
biasorEmitterBias),stabilizationagainst variation in Ico,Vbe and β bias compensation,
thermister&sensitorcompensation, thermal runaway &thermal stability.

Module 4[Total 13 Marks, MT 0, ET 13, Lectures: 07]

FieldEffectTransistor(FET):Introduction to Junction field effect transistors (n -channel and p -channel),
comparison between BJT and JFET, Construction of JFET, the JFET Volt- Ampere characteristics, the
pinch off voltage, Construction & characteristics of MOSFET (depletion type MOSFET and
Enhancement type MOSFET), biasing of FET's.

Module 5[Total 10 Marks, MT 10, ET 0, Lectures: 04]

Number Systems: Binary arithmetic: addition, subtraction, multiplicationand division, Base conversion,
conversion formulas with examples, one’sand two’s compliment arithmetic. Logic Gates, Boolean
algebra, Booleanpostulates, Evaluation of truth functions, Truth- function calculus as Booleanalgebra.

Module 6[Total 20 Marks, MT 0, ET 20, Lectures: 07]

Minimization Techniques:Using Boolean identities, standardrepresentations for logical functions (SOP &
POS forms), Karnaugh maprepresentation, simplification of logical functions using K-map,Minimization
of logical functions specified in miniterms/maxterms or TruthTable.

4
 2. REFERENCES
Text Books:
T1. Basic Electronics and linear Circuits, N NBhagava, TMH
T2. Electronic Devices and Circuit Theory, R. L. Boylestad, Pearson Education
T3. Digital Electronics, Moris-Mano, PHI

Other References:
R1. http://www.edutalks.org/downloads/Filters.pdf
R2. http://www.circuitstoday.com/filter-circuits
R3. https://nptel.ac.in/courses/117103063/
R4: Electronics Devices and Circuits 4e, S Salihavanan, N Suresh Kumar, McGraw Hills.
R5: http://vlabs.iitkgp.ernet.in/be/#

5
 3. COURSE OUTCOMES

(And their mapping with Modules/Units, POs)

CO1 An understanding of basic electronics PO1,PO11 PSO1

engineering principles, which are essential
for analysis and design of electronic devices
and circuits
CO2 The capability to apply the principles learned PO1 PSO1
to analyse simple electronics circuit
CO3 The ability to formulate and solve PO3,PO5,P PSO1
mathematical equations for given electronic O11
circuits
CO4 Ability to design the simple circuits using PO1,PO PSO1
transistors, diodes and FETs 3,PO13

CO5 An understanding of modelling of complex PO1,PO3,P PSO1

devices such as semiconductor diodes, BJT O5,PO11
and FET and how the models are used in
design and analysis of useful circuits
CO6 An understanding of basic principles of PO1,PO3 PSO1
digital electronics concepts including
Boolean arithmetic, realisation of Boolean
functions using basic gates, minimisation
principles
CO7 Application of principles learned to design PO3,PO11 PSO1
and analyse simple electronic utilities like,
rectifiers, biasing circuits
.

Mapping of COs with Modules/Units

COs
CO1 CO2 CO3 CO4 CO5 CO6 CO7
1 √
ul

ni
e/
U

6
 2
3
4 √
5 √
6 √

Mapping of COs with POs

POs
1 2 3 4 5 6 7 8 9 10 11 12 13
CO1 1 1 0 0 1 0.5 0 1 0.5 0.5 1 1 0.5
COs

CO2 1 1 0.5 0 1 0 0 0.5 0.5 0 1 1 1

CO3 1 1 0.5 0.5 1 0 0 0.5 0.5 0 1 1 1
CO4 1 1 0 0.5 1 0 0 1 0.5 0 1 1 1

Note: COs-POs Mapping:

Score Description
0 The CO does not help in achieving the PO
0.5 The CO partially helps in achieving the PO
1 The CO helps in achieving the PO

7
4. COURSE FLOW CHART
(UNIT PRECEDENCE DIAGRAM)

Module 1: 7 Lectures

Assignment 1:
Analytical
Module 2: 3 Lectures

Module 5: 4 Lectures

Assignment 2

Module 3: 4 Lectures

M Term: Syllabus till

Module 5: 30 marks
Module 3: 3 Lectures

Module 4: 7 Lectures

Module 6: 7 Lectures End Term: 50 Marks

8
5. COURSE OUTCOME EVALUATION

6.1 (2018-19)

Mid Term Test

Module 1: 08 Marks
Module 2:

End Term Examination:

Unit 1: 5 marks-Q3
Unit 2: 5 Marks-Q4
Unit 3: 20 Marks-Q5
Unit 4: 20 Marks-Q6

SN Student ID CO1 CO2 CO3 CO4

Q1 Q3 Q2 Q4 Q5 Q6
1
2
3
4
5
6
7
8
9
10
Total Avg.(Q1+Q3 Avg.(Q2+Q4) Avg.(Q5) Avg.(Q6)
) = = =
=12/20 16/20 10/20 10/20
This is the 60% 80% 50% 50%
percentageachievemen
t of COs

60+80+50+50
Average Achievement in COs 2018-19: = 60%
4

9
6.2 (2019-20)

SN Student CO1 CO2 CO3 CO4

ID
Q1 Q3 Q2 Q4 Q5 Q6
1
2
3
4
5
6
7
8
9
10
Total Avg(Q1+Q3) Avg(Q2+Q4)= Avg(Q5)= Avg(Q6)=
=14/20 16/20 10/20 10/20
This is the 70% 80% 80% 30%
percentage
achievement of
COs
70+80+80+30
Average Achievement in COs 2018-19: = 65%
4

65−60
Percentage Improvement from last year = = 8.3%
60

10
 6. QUESTION PAPER MODRATION
(According to Bloom’s Taxonomy)
MST and ET, Semester VI, 2019
SEM: VI SUB: Control System Engineering CODE: ET20512

Q Parts Blooms Level Score Question-CO Mapping

No.
Re Un Ap An Cr Ev I II III IV
Q1 a √ 2 √
b √ 2
c √ 1
Q2 a √ 2 √
b √ 2
c √ 2
Q3 a √ 3 √
b √ 2
c √ 2
Q4 a √ 1 √
b √ 1
c √ 3
Q5 a √ 2 √
b √ 2
c √ 2
Q6 a √ 1 √
b √ 2
c √ 3

(Total Score- 35/54; 64.8%),

11
NOTE:

(18 Questions with score 3 each is most difficult question paper=100% score)
(18 Questions with score 1 each is very easy question paper=33% score)

A moderately difficult Question paper is in the range of 60-70%.

How to decide score for a question?

Question Level Score Question Level Score

Re: Remembering 1 Un: Understanding 1
Ap: Application 2 An: Analysis 2
Cr: Creation 3 Ev: Evaluation 3

12
 7. LECTURE PLAN

Department Electronics & Communication Engineering Session : 2019-20

Name of Dr R K Chaurasiya, Dr. Menka, Dr. Deepak
Semester I
Teacher Bharti
Basic Electronics Engineering
Subject Sub. Code ECT 101
TIME SCHEDULE : Total Theory Periods: 36 Total Tutorial Periods: 0
Day Mon Tue Wed Thu Fri

Period No.

Time

SN Lect- Topic Date Date References

ures Proposed Compltd.
UNIT-I
Total Lectures required: 8 (8 Theory and 0 Tutorials)
1 L1 Band structure of insulators, metals and T1, T2
semiconductors, mobility, conductivity
2 L2 Doping, Electrons and holes in semiconductors, T1, T2
Charge densities in semiconductor, Hall effect
3 L3 Analysis of current components in Diode T1, T2
4 L4 Half wave and full wave rectifiers and their analysis T2
5 L5 Zener Diode as voltage regulator T2
6 L6 Various kinds of LC filters R1, R2
7 L7 Clipper circuits T2
8 L8 Clippers and clamper circuits T2
Assignment 1

UNIT- II
Total Lectures required: 3 (3 Theory and 0 Tutorials)
9 L1 BJT: introduction, current components, mode of T1, T2
operation, configurations.
10 L2 Input and output characteristics of CE, CB and CC T1, T2
configurations
11 L3 Transistor as an amplifier T1, T2
Mid Semester Test
UNIT- III
Total Lectures required: 7(7 Theory and 0 Tutorials)
12 L1 Operating point, DC Analysis, DC load line T2
13 L2 Biasing circuits: Fixed-bias, T2
13
14 L3 Biasing circuits: Fixed-bias with emitter resistance T2
15 L4 Biasing circuits: Emitter bias T2
16 L5 Concept of bias stability T2
17 L6 Stabilization against variation in ICO, VBE and β T2
18 L7 Thermal runaway and thermal stability. T1
Assignment 2

UNIT-IV
Total Lectures required: 7 (7 Theory and 0 Tutorials)
19 L1 Introduction to FETs, comparison with BJTs T2
20 L2 JFETs: introduction, working principles T2
21 L3 JFET biasing techniques T2
22 L4 MOSFET: Introduction, working principles T2
23 L5 MOSFET: Introduction, working principles T2
24 L6 MOSFET biasing techniques T2
25 L7 MOSFET biasing techniques T2

UNIT -V
26 L1 Binary arithmetic: addition, subtraction,
T3
multiplication
27 L2 Division, conversion formulas with examples, T3
28 L3 one’s and two’s compliment arithmetic , Logic Gates,
T3
Boolean algebra,
29 L4 Boolean postulates, Evaluation of truth functions,
T3
Truth- function calculus as Boolean algebra

UNIT-VI
30 L1 Minimization Techniques:Using Boolean identities,
T3
examples
31 L2 standard representations for logical functions (SOP &
T3
POS forms), examples
32 L3 Karnaugh map representation, simplification of
T3
logical functions using K-map,
33 L4 K-map-examples T3
34 L5 Minimization of logical functions specified in
T3
miniterms/maxterms or TruthTable, examples
35 L6 Minimization examples T3

COURSE REVISION
36 L1 Total Lectures required: 1 (1 Theory and 0
Tutorials)

Course Coordinator
Dr R. K. Chaurasiya
Dr. Deepak Bharti
Dr. Menka

14
 HoD
Electronics and Communication Enginneering

15
 8. ASSIGNMENTS

Department Electronics & Communication Engineering Session : 2019-20

Name of
Dr R K Chaurasiya Semester VI
Teacher
Control System Engineering
Subject Sub. Code ECT 314

Assignment 1

1. On application of potential of 0.5 V, current flowing through a diode is 0.3 mA.

Determine the value of applied voltage at which current flowing the diode would
be10 mA?
2. Determine the range of values of Vi, that would maintain the zener diode in the
following figure in the ON state.

3. Draw the waveforms V01(t) and V02(t) in the circuit given below:

16
 9. PREVIOUS YEAR PAPERS
(Mid Test, End Semester and Supplementary Examinations)

Department Electronics & Communication Engineering Session : 2019-20

Name of
Dr R K Chaurasiya Semester VI
Teacher
Control System Engineering
Subject Sub. Code ECT 314

Add Question Papers here for

Academic year 2017-18, 2018-19, 2019-20.

17
 10. MoIs of PREVIOUS PAPERS

Department Electronics & Communication Engineering Session : 2019-20

Name of
Dr R K Chaurasiya Semester VI
Teacher
Control System Engineering
Subject Sub. Code ECT 314

(Attached as Hand Written solution manuals)

18