Datasheet de Via VT6103

Fast Ethernet
10 / 100
1-Port PHY / Transceiver
Revision 1.1
April 15, 2002
VIA TECHNOLOGIES, INC.

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We Connect VT6103 - Fast Ethernet 10 / 100 PHY / Transceiver
REVISION HISTORY
Document Release Date Revision Initials
1.0 4/9/02 Initial Public Release – same as internal release 0.4 except for update of legal page, DH
fix of miscellaneous document formatting errors, update of document title,
addition of typical system block diagram, fix of RXER and TXER pin
descriptions, update of application schematics, and addition of marking spec
1.1 4/15/02 Revised document title and page headers DH
Fixed Taiwan office fax number on legal page
Cleaned up schematics and added as figures
Revision 1.1 April 15, 2002 -i- Revision History

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TABLE OF CONTENTS
REVISION HISTORY .......................................................................................................................................................................I
TABLE OF CONTENTS ................................................................................................................................................................. II
LIST OF FIGURES .........................................................................................................................................................................IV
LIST OF TABLES ...........................................................................................................................................................................IV
PRODUCT FEATURES ................................................................................................................................................................... 1
OVERVIEW....................................................................................................................................................................................... 2
PINOUTS............................................................................................................................................................................................ 3
PIN DIAGRAM ................................................................................................................................................................................ 3
PIN LIST ......................................................................................................................................................................................... 3
PIN DESCRIPTIONS......................................................................................................................................................................... 4
REGISTERS....................................................................................................................................................................................... 7
REGISTER OVERVIEW ................................................................................................................................................................... 7
REGISTER DESCRIPTIONS ............................................................................................................................................................. 9
FUNCTIONAL DESCRIPTION .................................................................................................................................................... 16
GENERAL ..................................................................................................................................................................................... 16
802.3U MII................................................................................................................................................................................... 18
Serial Management Register Access ................................................................................................................................... 18
Serial Management Access Protocol ................................................................................................................................... 18
Preamble Suppression.......................................................................................................................................................... 18
PHY Address Sensing........................................................................................................................................................... 18
Nibble-Wide MII Data Interface......................................................................................................................................... 19
Collision Detect ..................................................................................................................................................................... 19
Carrier Sense ........................................................................................................................................................................ 19
MII Isolate Mode .................................................................................................................................................................. 19
LINK INTEGRITY AND AUTONEGOTIATION ................................................................................................................................ 20
General .................................................................................................................................................................................. 20
10Base-T Link Integrity Algorithm – 10Mbps .................................................................................................................. 20
100Base-TX Link Integrity Algorithm -100Mbps ............................................................................................................. 20
AutoNegotiation Algorithm ................................................................................................................................................. 20
AutoNegotiation Outcome Indication................................................................................................................................. 20
AutoNegotiation Status ........................................................................................................................................................ 20
AutoNegotiation Enable....................................................................................................................................................... 20
Auto Negotiation Reset ........................................................................................................................................................ 20
Link Indication ..................................................................................................................................................................... 20
ENCODER ..................................................................................................................................................................................... 21
4B5B Encoder – 100 Mbps................................................................................................................................................... 21
Manchester Encoder – 10 Mbps.......................................................................................................................................... 21
DECODER ..................................................................................................................................................................................... 21
4B5B Encoder – 100 Mbps................................................................................................................................................... 21
Manchester Encoder – 10 Mbps.......................................................................................................................................... 21
CLOCK AND DATA RECOVERY .................................................................................................................................................... 22
Revision 1.1 April 15, 2002 -ii- Table of Contents

Technologies, Inc.
Clock Recovery – 100 Mbps ................................................................................................................................................ 22

Data Recovery – 100 Mbps .................................................................................................................................................. 22
Clock Recovery – 10 Mbps .................................................................................................................................................. 22
Data Recovery – 10 Mbps .................................................................................................................................................... 22
SCRAMBLER / DESCRAMBLER ..................................................................................................................................................... 22
100 Mbps Scrambler ............................................................................................................................................................ 22
10 Mbps Scrambler .............................................................................................................................................................. 22
100 Mbps Descrambler ........................................................................................................................................................ 22
10 Mbps Descrambler .......................................................................................................................................................... 22
TWISTED PAIR TRANSMITTER .................................................................................................................................................... 23
Transmitter - 100 Mbps ....................................................................................................................................................... 23
Transmitter - 10 Mbps ......................................................................................................................................................... 23
TWISTED PAIR RECEIVER ........................................................................................................................................................... 24
Receiver - 100 Mbps ............................................................................................................................................................. 24
Receiver - 10 Mbps ............................................................................................................................................................... 24
MISCELLANEOUS FUNCTIONS ..................................................................................................................................................... 25
Smart Squelch....................................................................................................................................................................... 25
Collision Detection................................................................................................................................................................ 25
Carrier Sense ........................................................................................................................................................................ 25
Normal Link Pulse Detection / Generation ........................................................................................................................ 25
Jabber Function.................................................................................................................................................................... 26
Status Information ............................................................................................................................................................... 26
Automatic Link Polarity Detection ..................................................................................................................................... 26
Internal Loopback ................................................................................................................................................................ 26
100BASE-FX ................................................................................................................................................................................ 27
APPLICATION SCHEMATICS.................................................................................................................................................... 28
ELECTRICAL SPECIFICATIONS .............................................................................................................................................. 31
ABSOLUTE MAXIMUM RATINGS ................................................................................................................................................. 31
DC CHARACTERISTICS ............................................................................................................................................................... 31
AC CHARACTERISTICS ............................................................................................................................................................... 31
100BaseT Transmitter Characteristics............................................................................................................................... 32
10BaseT Transmitter Characteristics................................................................................................................................. 32
Crystal Oscillator Characteristics....................................................................................................................................... 33
PLL Frequency Multiplier Characteristics........................................................................................................................ 33
FX Characteristics................................................................................................................................................................ 33
PACKAGE MECHANICAL SPECIFICATIONS ....................................................................................................................... 40
Revision 1.1 April 15, 2002 -iii- Table of Contents

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LIST OF FIGURES
FIGURE 1. TYPICAL SYSTEM BLOCK DIAGRAM ................................................................................................................ 2
FIGURE 2. PIN DIAGRAM ............................................................................................................................................................ 3
FIGURE 3. INTERNAL BLOCK DIAGRAM............................................................................................................................. 17
FIGURE 4. APPLICATION SCHEMATIC EXAMPLE PAGE 1 ............................................................................................ 29
FIGURE 5. APPLICATION SCHEMATIC EXAMPLE PAGE 2 ............................................................................................ 30
FIGURE 6. MI INTERFACE MDIO TIMING ........................................................................................................................... 34
FIGURE 7. MI INTERFACE MDIO INTERRUPT PULSE TIMING ..................................................................................... 34
FIGURE 8. LED ON / OFF TIMING ........................................................................................................................................... 35
FIGURE 9. MII TRANSMIT DATA TIMING............................................................................................................................ 35
FIGURE 10. MII RECEIVE DATA TIMING ............................................................................................................................. 35
FIGURE 11. MII HEARTBEAT TIMING................................................................................................................................... 36
FIGURE 12. MII JABBER TIMING............................................................................................................................................ 36
FIGURE 13. MII NORMAL LINK PULSE TIMING ................................................................................................................ 37
FIGURE 14. MII AUTO-NEGOTIATION FAST LINK PULSE TIMING.............................................................................. 37
FIGURE 15. 100MB/S RECEIVE PACKET TIMING ............................................................................................................... 38
FIGURE 16. 100MB/S TRANSMIT PACKET TIMING............................................................................................................ 38
FIGURE 17. 10MB/S RECEIVE PACKET TIMING ................................................................................................................. 39
FIGURE 18. 10MB/S TRANSMIT PACKET TIMING.............................................................................................................. 39
FIGURE 19. MECHANICAL SPECIFICATIONS – 48 PIN SSOP PACKAGE ..................................................................... 40
LIST OF TABLES
TABLE 1. PIN LIST (ALPHABETICAL ORDER) ...................................................................................................................... 3
TABLE 2. PIN DESCRIPTIONS .................................................................................................................................................... 4
TABLE 3. REGISTER SUMMARY ............................................................................................................................................... 7
TABLE 4. REGISTER BIT SUMMARY – REGISTERS DEFINED BY 802.3U ...................................................................... 8
TABLE 5. REGISTER BIT SUMMARY - VENDOR DEFINED REGISTERS ........................................................................ 8
TABLE 6. LED FUNCTION DEFINITION ................................................................................................................................ 26
TABLE 7. MI INTERFACE MDIO OUTPUT TIMING............................................................................................................ 34
TABLE 8. MI INTERFACE MDIO INTERRUPT PULSE TIMING ....................................................................................... 34
TABLE 9. LED ON / OFF TIMING ............................................................................................................................................. 35
TABLE 10. MII TRANSMIT DATA TIMING............................................................................................................................ 35
TABLE 11. MII RECEIVE DATA TIMING ............................................................................................................................... 35
TABLE 12. MII HEARTBEAT TIMING..................................................................................................................................... 36
TABLE 13. MII JABBER TIMING.............................................................................................................................................. 36
TABLE 14. MII 10BASE-T NORMAL LINK PULSE TIMING ............................................................................................... 37
TABLE 15. MII AUTO-NEGOTIATION FAST LINK PULSE TIMING................................................................................ 37
TABLE 16. 100MB/S RECEIVE PACKET TIMING ................................................................................................................. 38
TABLE 17. 100MB/S TRANSMIT PACKET TIMING.............................................................................................................. 38
TABLE 18. 10MB/S RECEIVE PACKET TIMING ................................................................................................................... 39
TABLE 19. 10MB/S TRANSMIT PACKET TIMING................................................................................................................ 39
Revision 1.1 April 15, 2002 -iv- Table of Contents

Technologies, Inc.
VT6103
FAST ETHERNET 10 / 100
1-PORT PHY / TRANSCEIVER
PRODUCT FEATURES
• Single Chip 100Base-TX / 10Base-T Physical Layer Solution
• Dual Speed – 100 / 10 Mbps
• Half and Full Duplex
• MII Interface to Ethernet Controller
• MII Interface to Configuration & Status
• Optional Repeater Interface
• Auto Negotiation: 10 / 100, Full / Half Duplex
• Meet All Applicable IEEE 802.3, 10Base-T and 100Base-Tx Standards
• On Chip Wave Shaping – No External Filters Required
• Adaptive Equalizer
• Baseline Wander Correction
• LED Outputs
– Link Status
– Duplex status
– Speed Status
– Collision
• 48 Pin SSOP Package
Revision 1.1 April 15, 2002 -1- Product Features

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OVERVIEW
The VT6103 is a Physical Layer device for Ethernet 10Base-T and 100Base-TX using category 5 Unshielded, Type 1 Shielded,
and Fiber Optic cables. This VLSI device is designed for easy implementation of 10 / 100 Mb/s Fast Etherent LANs. It interfaces
to a MAC through an MII interface ensuring interoperability between products from different vendors.
Serial
PCI
EEPROM LEDs
Bus
MI Interface TX+,-
VT6102 VT6103 Physical
MII Interface RX+,- Ethernet
MAC PHY Connection
Boot Straps
ROM
Figure 1. Typical System Block Diagram
Revision 1.1 April 15, 2002 -2- Overview

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PINOUTS
Pin Diagram
MDIO 1 48 RESET#
MDC 2 47 VCCOSC
PHYAD1 / RXD3 3 46 XI
PHYAD2 / RXD2 4 45 XO
PHYAD3 / RXD1 5 44 GNDOSC
PHYAD4 / RXD0 6 43 GNDTX
VDD 7 42 VCCTX
GND 8 VT6103 41 TX+
BYPOSC / RXDV 9 40 TX-
RXC 10 39 GNDTXC
ISO / RXER 11 Fast 38 VCCPLL
GND 12 37 REXT
VCC 13 Ethernet 36 GNDPLL
TXER 14 Media 35 GNDRX
TXC 15 34 SD / FXEN
TXEN 16 Interface 33 RX+
TXD0 17 32 RX-
TXD1 18 Chip 31 VCCRX
TXD2 19 30 PD#
TXD3 20 29 LED3 / NWAYEN
SYMB / COL 21 28 LED2 / DUPLEX
RPTR / CRS 22 27 LED1 / SPD100
GND 23 26 LED0 / LINK
VDD 24 25 INT# / PHYAD0
Figure 2. Pin Diagram
Pin List
Table 1. Pin List (Alphabetical Order)
Pin # Pin Name Pin # Pin Name
21 O/I COL / SYMB 5 IO / I RXD1 / PHYAD3
22 O/I CRS / RPTR 4 IO / I RXD2 / PHYAD2
8 P GND 3 IO / I RXD3 / PHYAD1
12 P GND 9 IO / I RXDV / BYPOSC
23 P GND 11 O/I RXER / ISO
44 P GNDOSC 34 I/I SD / FXEN
36 P GNDPLL 40 O TX–
35 P GNDRX 41 O TX+
43 P GNDTX 15 O TXC
39 P GNDTXC 17 I TXD0
25 O/I INT# / PHYAD0 18 I TXD1
26 O/I LED0 / LINK 19 I TXD2
27 O/I LED1 / SPD100 20 I TXD3
28 O/I LED2 / DUPLEX 16 I TXEN
29 O/I LED3 / NWAYEN 14 I TXER
2 I MDC 13 P VCC
1 IO MDIO 47 P VCCOSC
30 I PD# 38 P VCCPLL
48 I RESET# 31 P VCCRX
37 A REXT 42 P VCCTX
32 I RX– 7 P VDD
33 I RX+ 24 P VDD
10 O RXC 46 I XI
6 IO / I RXD0 / PHYAD4 45 O XO
Revision 1.1, April 15, 2002 -3- Pinouts

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Pin Descriptions
Table 2. Pin Descriptions
Management Interface (MI)

Signal Name Pin # I/O Signal Description
MDIO 1 IO Management Interface (MI) Data I/O. Received from the external MAC.
MDC 2 I Management Interface (MI) Clock. Received from the external MAC as a timing
reference for MDIO
INT# / PHYAD0 25 O Management Interface (MI) Interrupt Out. Active low.
Media Independent Interface (MII)

RXC 10 O Receive Clock. Timing reference for transfer of RXD and RXDV. 25 MHz when
operating at 100 Mbps and 2.5 MHz when operating at 10 Mbps (always active).
RXD3 / PHYAD1, 3 O Receive Data. These bits transition with RXC. RXD[3:0] should accepted by the external
RXD2 / PHYAD2, 4 MAC for each RXC period in which RXDV is asserted. RXD0 is the least significant bit.
RXD1 / PHYAD3, 5 While RXDV is de-asserted, RXD[3:0] have no effect upon the switch’s MAC and the
RXD0 / PHYAD4 6 value of RXD[3:0] is unspecified.
RXDV / BYPOSC 9 O Receive Data Valid. RXDV is driven to indicate that nibbles are being presented on the
MII for receiving. RXDV transitions synchronous to RXC. It is asserted synchronously
with the first nibble of the preamble and remains asserted while all nibbles to be received
are presented to the MII.
RXER / ISO 11 O Receive Error. The VT6103 asserts this output when it receives invalid symbols from the
network
TXC 15 O Transmit Clock. Timing reference for transfer of TXD and TXEN. 25MHz when
operating at 100 Mbps and 2.5 MHz when operating at 10 Mbps (always active).
TXD[3-0] 20, 19, I Transmit Data. These bits transition relative to TXC. TXD[3:0] are accepted from the
18, 17 external MAC for each TXC period in which TXEN is asserted. TXD0 is the least
significant bit. While TXEN is de-asserted, TXD[3:0] have no effect and the value of
TXD[3:0] is unspecified.
TXEN 16 I Transmit Enable. Indicates transmit active from the MII port. TXEN transitions
synchronous to TXC. TXEN indicates that the nibbles presented on TXD[3-0] are valid
for transmission. TXEN is asserted synchronously with the first nibble of the preamble
and remains asserted while all nibbles to be transmitted are presented to the MII interface.
TXER 14 I Transmit Error. The MAC asserts this input when an error has occurred in the input
stream.
COL / SYMB 21 O Collision Detect. Asserted asynchronously upon detection of a collision on the medium
and remains asserted while the collision condition persists.
CRS / RPTR 22 O Carrier Sense. Asserted asynchronously upon detection of a non-idle medium or while
TXEN is asserted. Deasserted asynchronously upon detection of idle conditions on both
transmit and receive media. Remains asserted throughout the duration of a collision
condition.
Physical Cable Connection

TX+ 41 O Transmit Plus. Differential outputs for FX, 100BaseTx, or 10BaseT transmission.
TX– 40 O Transmit Minus. Differential outputs for FX, 100BaseTx, or 10BaseT transmission.
RX+ 33 I Receive Plus. Differential inputs for FX, 100BaseTx, or 10BaseT reception.
RX– 32 I Receive Minus. Differential inputs for FX, 100BaseTx, or 10BaseT reception.
Revision 1.1, April 15, 2002 -4- Pin Descriptions

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Strap Options
SYMB / COL 21 I Symbol Mode. Latched into register 16 (register 10h) bit-2 at power-up /
reset. Internally pulled low for default disabled.
RPTR / CRS 22 I Repeater Mode. Latched into register 16 (register 10h) bit-4 at power-up /
reset. Internally pulled low for default disabled.
ISO / RXER 11 I Isolate. Latched into register 0 bit-10 at power-up / reset. Internally pulled
low for default disabled.
PHYAD[4:0] / RXD[0:3], INT# 6, 5, 4, I PHY Address. Latched into register 16 (register 10h) bits 15-11 at power-up
3, 25 / reset. Internally pulled low, low, low, low, and high for default 00001b.
LINK / LED0 26 I Test Mode Enable. 0=Enable, 1=Disable. Do not leave floating. Pull high
with 10K ohms if not used.
SPD100 / LED1 27 I Speed Select. Latched into register 0 bit-13 at power-up / reset (0=Speed 10,
1=Speed100). If NWAYEN is not pulled down at power-up / reset, this pin
is also latched as Speed support in register 4 (Auto-Negotiation
Advertisement Base Page). Do not leave floating. Pull high or low with 10K
ohms.
DUPLEX / LED2 28 I Duplex Mode Select. Latched into register 0 bit-8 at power-up / reset
(0=Half, 1=Full). If NWAYEN is not pulled down at power-up / reset, this
pin is also latched as Duplex support in register 4 (Auto-Negotiation
Advertisement Base Page). Do not leave floating. Pull high or low with 10K
ohms.
NWAYEN / LED3 29 I N-Way Enable. Latched into register 0 bit-12 (Auto-Negotiation Enable) at
power-up / reset (0=Disable, 1=Enable). Do not leave floating. Pull low with
10K ohms if not used.
FXEN / SD 34 I Fiber Mode Enable. Latched into register 16 (register 10h) bit-10 at power-
up / reset (0=Disable, 1=Enable). Do not leave floating. Pull low with 10K
ohms if not used.
Note: For the pins listed above, pullup / pulldown status is latched during powerup / reset. External strap option values may be
set by connecting the indicated pin to a 10K ohm pull down for 0 (L) or to a 10K pull up for 1 (H).
LED Outputs
LED0 / LINK 26 IO LED Output 0. See Register 16 (10h) bits 5-6 & Table 6 for LED function.
LED1 / SPD100 27 IO LED Output 1. See Register 16 (10h) bits 5-6 & Table 6 for LED function.
LED2 / DUPLEX 28 IO LED Output 2. See Register 16 (10h) bits 5-6 & Table 6 for LED function.
LED3 / NWAYEN 29 IO LED Output 3. See Register 16 (10h) bits 5-6 & Table 6 for LED function.

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Resets, Clocks, Control and Status

XI 46 I Crystal In. Connect to 25 MHz crystal and to 22pF 5% to GNDOSC. Can alternately be
driven by an external clock source (3.3V voltage swing) with XO unconnected.
XO 45 O Crystal Feedback. Connect to other side of 25 MHz crystal and to 22pF 5% to GNDOSC
BYPOSC / RXDV 9 I Bypass Oscillator. Connect to pullup to use an external oscillator instead of a crystal.
REXT 37 A External Resistor. Connect 6.49K 1% resistor to GNDOSC.
SD / FXEN 34 I Signal Detect. Used in fiber mode.
PD# 30 I Power Down. Active low.
RESET# 48 I Reset. Active low. Schmitt input for improved noise immunity..
Power and Ground

VDD 7, 24 P Digital I/O Power. 3.3V nominal (3.15V to 3.45V). For digital I/O
GND 8, 23 P Ground. Connect to primary motherboard ground plane.
VCC 13 P Core Power. 3.3V nominal (3.15V to 3.45V). For internal digital logic.
GND 12 P Core Ground. Connect to primary motherboard ground plane.
VCCOSC 47 P Oscillator Power. 3.3V. Isolate from digital supply voltage with a ferrite bead
GNDOSC 44 P Oscillator Ground. Connect to primary motherboard ground plane.
VCCRX 31 P Receiver Power. 3.3V. Isolate from digital supply voltage with a ferrite bead
GNDRX 35 P Receiver Ground. Connect to primary motherboard ground plane.
VCCTX 42 P Transmitter Power. 3.3V. Isolate from digital supply voltage with a ferrite bead
GNDTX 43 P Transmitter Ground. Connect to primary motherboard ground plane.
GNDTXC 39 P Transmit Clock Ground. Connect to primary motherboard ground plane.
VCCPLL 38 P PLL Power. 3.3V. Isolate from digital supply voltage with a ferrite bead
GNDPLL 36 P PLL Ground. Connect to primary motherboard ground plane.

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REGISTERS
Register Overview
The VT6103 internal register set consists of thirty-two 16-bit In the register descriptions that follow, the following
MI (Management Interface) registers (of which 9 registers are abbreviations are used:
currently undefined / reserved).
RW = Read / Write
The bits of PHY registers 0-8 are defined by the IEEE 802.3u RO = Read Only
standard. The remaining PHY registers have vendor specific SC = Self Clearing
bit definitions. All register bits implemented by the VT6103 LH = Latch High
are described in this data sheet (see register summary table LL = Latch Low
below, bit summary table on the next page, and detailed
“Self Clearing” bits are normally 0. If set to 1 they will
register descriptions on following pages).
perform the indicated function then automatically be cleared
PHY registers are addressed by the MAC by sending register back to 0 by the chip. “Latch High” and “Latch Low” bits are
address pointer information via the MI interface (serially over used to record that an event (level) occurred. For Latch High
the MDIO pin clocked by MDC) with register read / write bits, if the bit ever goes high, it will latch at that high level
data transfer via the same pins. For more information on this until read (the read will clear the bit). For “Latch Low” bits,
mechanism, refer to IEEE 802.3 section 22.2.4. if the bit goes low, it will stay at a low level until read (the
read will set the bit high).
Table 3. Register Summary

Offset Offset Management Interface Registers Bits Default Acc Page
00 00h Management Interface Control 16 3100h RW 9
01 00h Management Interface Status 16 7849h RO 9
02 01h PHY Identifier 0 16 0101h RO 9
03 02h PHY Identifier 1 16 8F20h RO 9
04 03h Auto-Negotiation Advertisement Base 16 05E1h RW 10
05 04h Link Partner Advertisement Base 16 0000h RO 10
06 05h Auto-Negotiation Expansion 16 0004h RO 10
07 06h Auto-Negotiation Advertisement Next 16 2001h RW 10
08 07h Link Partner Advertisement Next 16 0000h RO 10
9-15 09-0Fh -reserved- — — —
16 10h PHY Configuration 1 16 0800h RW 11
17 11h PHY Configuration 2 16 F7FFh RW 11
18 12h PHY Configuration 3 16 0800h RW 11
19 13h PHY Configuration 4 16 FFFCh RW 12
20 14h PHY Status 16 0000h RO 12
21 15h Link Fail Counter 16 0000h RO 13
22 16h Invalid Symbol / Jabber Error Counter 16 0000h RO 13
23 17h False Carrier / SQE Counter 16 0000h RO 13
24-25 18-19h -reserved- — — —
26 1Ah PHY Test Configuration 1 16 0012h RW 14
27 1Bh PHY Test Configuration 2 16 C500h RW 14
28 1Ch PHY Test Configuration 3 16 0208h RW 15
29 1Dh PHY Test Configuration 4 16 0030h RW 15
30 1Eh PHY Test Configuration 5 16 001Bh RW 15
31 1Fh PHY Test Configuration 6 16 0000h RW 15
Revision 1.1 April 15, 2002 -7- Register Descriptions

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Table 4. Register Bit Summary – Registers Defined by 802.3u

Bit Register 0 Register 1 Register 2 Register3 Register4 Register 5 Register 6 Register 7 Register 8
15 Reset Cap 100T4 Next Pg LP Next Pg Next Page LP NxtPg
14 Loop Back Cap Tx100F Ack LP Ack Ack1 LP Ack1
13 Speed Cap Tx100H Rem Flt LP Rem Flt Msg Page LP MP
12 Aneg Ena Cap Tx10F OUI (lsb) – – Ack2 LP Ack2
11 Power Down Cap Tx10H – – Toggle LP Toggle
10 Isolate Cap 100T2F Pause LP Pause –
9 Aneg Restart Cap 100T2H 100T4 LP 100T4
8 Duplex Extd Status OUI (msb) Tx100F LP Tx100F Link
7 COL Test – Part Tx100H LP Tx100H Message Partner
6 Cap Supr Number Tx10F LP Tx10F Code Field Message
5 Aneg Complete Tx10H LP Tx10H or Code Field
4 Remote Fault Parallel Fault Det Unformatted or
3 – Cap Aneg Link LP Cap Next Pg Code Field Unformatted
2 Link Status Revision Selector Partner Cap Next Page Code Field
1 Jabber Detect Number Field Selector Aneg Page Rcvd
0 Extd Reg Field LP Cap Aneg
Table 5. Register Bit Summary - Vendor Defined Registers

Bit Register 16 Register 17 Register 18 Register 19 Register 20 Rx21 Rx22 Rx23 26-31
15 Jabber Det Byp Scram Mask Interrupt Polarity Invert
14 PHY SQE Detect Byp 4B5B Mask Link Up Int Link Up Status
13 Address Pol Correct Byp Align Mask Link Fail Int Link Fail Status
12 FarEndFault Byp NRZI Mask Link Change Int Link Status
11 ChangeSeed LostSyncEna Mask Aneg Compete Int Aneg Comp Status
10 Fiber Mode LostSyncSel Mask Page Rcvd Int Page Rcvd Status
9 Cable Type Mask Jabber Int Jabber Status Link Receive False Used
8 Force Link Mask Rcvd Code Err Int Rcvd Code Err Status Fail Error Carrier For
7 10LoSquSel Mask Bad SSD Int Bad SSD Status Count Count Count Test
6 Repeater Mask Bad ESD Int Bad ESD Status
5 LED Seed – Mask SQE Err Int SQE Err Status
4 Select Mask LnkFail MaxCnt Int LnkFail MaxCnt Status
3 Int Select Mask Rx Err MaxCnt Int Rx Err MaxCnt Status
2 Symbol Mask FalCarr MaxCnt Int FalseCarr MaxCnt Stat
1 – – Speed
0 – – Duplex

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Register Descriptions
Offset 0 (00h) – MI Control (3100h)................................RW Offset 1 (01h) – MI Status (7849h)................................... RO

15 PHY Reset ........................................default = 0, SC 15 Capable of 100 Base-T4 Operation................. def=0
14 Loopback Mode 14 Capable of 100 Base-TX Full Duplex ............. def=1
0 Disable ...................................................default 13 Capable of 100 Base-TX Half Duplex ............ def=1
1 Enable 12 Capable of 10 Base-TX Full Duplex ............. def=1
13 Speed Select LSB 11 Capable of 10 Base-TX Half Duplex ............ def=1
0 10 10 Capable of 100 Base-T2 Full Duplex .............. def=0
1 100 ....................................................default 9 Capable of 100 Base-T2 Half Duplex ............. def=0
12 Auto-Negotiation Process 8 Extended Status Information in Rx15............ def=0
0 Disable 7 Reserved ........................................always reads 0
1 Enable ...................................................default 6 Capable of Accepting MI Frames
11 Power Down with MI Preamble Suppressed........................ def=1
0 Disable ...................................................default 5 Auto-Negotiation Process Completed............. def=0
1 Enable 4 Remote Fault Condition Detected ...........LH, def=0
10 Electrically Isolate PHY from MII 3 Capable of Auto-Negotiation Operation ........ def=1
0 Disable ...................................................default 2 Link Status ............................................... LL, def=0
1 Enable 1 Jabber Condition Detected.......................LH, def=0
9 Auto-Negotiation Restart ..................default = 0, SC 0 Capable of Extended Register......................... def=1
8 Duplex Mode Select
0 Half
1 Full ....................................................default
7 COL Test Offset 2 (02h) – PHY Identifier 0 (0101h) ....................... RO
0 Disable ...................................................default 15-0 Company ID MSBs ....................always reads 0101h
1 Enable
Offset 3 (03h) – PHY Identifier 1 (8F20h)....................... RO
6 Speed Select MSB ...............reserved, always reads 0
5-0 Reserved ........................................ always reads 0 15-10 Company ID LSBs .........................always reads 23h
9-4 Manufacturer’s Part number .......always reads 32h
3-0 Manufacturer’s Revision Number....always reads 0

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Offset 4 (04h) – AutoNegotiation Advertisement Base Page Offset 7 (07h) – AutoNegotiation Advertisement Next Page
(05E1h)...............................................................................RW (2001h)............................................................................... RW
15 Next Page .............................................. default = 0 15 Next Page .............................................. default = 0
14 Received Code Word Recognized....RO, default = 0 14 Received Code Word Recognized ... RO, default = 0
13 Remote Fault ............................................ default = 0 13 Message Page............................................ default = 1
12-11 Reserved ........................................ always reads 0 12 Capable of Complying with Message ..... default = 0
10 Pause Operation for Full Duplex Link .. default = 1 11 Toggle Bit ...................................... RO, default = 0
9 100 Base-T4 Capable ............................... default = 0 10-0 Message Code Field or Unformatted Code Field
8 100 Base-TX Full DuplexCapable .......... default = 1 ........................................ default = 001h
7 100 Base-TX Half Duplex Capable ........ default = 1
6 10 Base-TX Full Duplex Capable ......... default = 1
4-0 Selector Field.................................. default = 00001b
Offset 5 (05h) – Link Partner Advertisement Base Page Offset 8 (08h) – Link Partner Advertisement Next Page
(0000h) ................................................................................RO (0000h)................................................................................ RO
15 Next Page .............................................. default = 0 15 Next Page .............................................. default = 0
14 Received Code Word Recognized........... default = 0 14 Received Code Word Recognized ........... default = 0
13 Remote Fault ............................................ default = 0 13 Message Page............................................ default = 0
12-11 Reserved ........................................ always reads 0 12 Capable of Complying with Message ..... default = 0
10 Pause Operation for Full Duplex Link .. default = 0 11 Toggle Bit .............................................. default = 0
9 100 Base-T4 Capable ............................... default = 0 10-0 Message Code Field or Unformatted Code Field
8 100 Base-TX Full DuplexCapable .......... default = 0 .............................................. default = 0
6 10 Base-TX Full Duplex Capable ......... default = 0
4-0 Selector Field............................................ default = 0
Offset 6 (06h) – Auto-Negotiation Expansion (0004h)....RO

15-5 Reserved ........................................ always reads 0
4 Parallel Fault Detect in Auto-Negotiation Process
....................................... LH, default = 0
3 Link Partner Capable of Next Page Process
.............................................. default = 0
2 Capable of Next Page Process................. default = 0
1 Page Received in Auto-Negotiation Process
....................................... LH, default = 0
0 Link Partner Capable of Auto-Negotiation
Process .............................................. default = 0

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Offset 16 (10h) – PHY Configuration 1 (0800h).............RW Offset 17 (11h) – PHY Configuration 2 (F7FFh)........... RW
15-11 PHY Address........................................ default = 01h 15 Jabber Detect
10 Fiber Mode 0 Disable
0 Disable ...................................................default 1 Enable................................................... default
1 Enable 14 Signal Quality Error Detect
9 Cable Type 0 Disable
0 UTP5 and STP (100 ohm) cable ............default 1 Enable................................................... default
1 STP 150 ohm cable 13 Auto-Polarity Correction
8 Force PHY in Link Good Status 0 Disable
1 Enable 12 Far End Fault Detect
7 Base10Tx Low Squelch Level Select 0 Disable
0 Regular Cable Length ............................default 1 Enable................................................... default
1 Long Cable (> 100 meters) 11 Change Seed ........................................ Self Clearing
6-5 Programmable LED Output Select 0 Disable................................................... default
LED0 LED1 LED2 LED3 1 Enable
00 Link/Act Speed Duplex COL ....def 10-0 Seed ........................................default = 7FFh
01 Pwr/TxAct Link/RxAct Speed Duplex
10 Speed100 Speed10 Act Duplex
11 Pwr/TxAct Link/RxAct Speed COL
4 Repeater Mode Offset 18 (12h) – PHY Configuration 3 (0800h) ............ RW
0 Disable ...................................................default 15 Bypass Scrambler and Descrambler Functions
1 Enable 0 Disable................................................... default
3 Interrupt Select 1 Enable
0 Assert interrupt on INT#........................default 14 Bypass 4B5B Encoding and Decoding Functions
1 Assert interrupt on MDIO 0 Disable................................................... default
2 Symbol Mode .......................................................RO 1 Enable
0 Disable ...................................................default 13 Bypass Symbol Alignment Function
1 Enable
12 Bypass NRZI Encoding and Decoding Functions
0 Disable................................................... default
1 Enable
11 Loss Sync Function ............................. Self Clearing
0 Disable
1 Enable................................................... default
10 Lost Sync Timer Select
0 722 usec................................................. default
1 2 msec
9-0 Reserved ........................................always reads 0

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Offset 19 (13h) – PHY Configuration 4 (FFFCh) ..........RW Offset 20 (14h) – PHY Status (0000h).............................. RO
15 Mask Interrupt Function 15 Polarity Inversion Base10-Tx
0 Disable 0 Disable................................................... default
1 Enable ...................................................default 1 Enable
14 Mask Interrupt on Link-Up Status 14 Link Up Status...................................LH, default = 0
0 Disable
1 Enable ...................................................default
13 Mask Interrupt on Link-Fail Status 13 Link Fail Status ................................. LL, default = 0
0 Disable
1 Enable ...................................................default
12 Mask Interrupt on Link Status Change 12 Link Status .............................................. default = 0
0 Disable
1 Enable ...................................................default
11 Mask Interrupt on Auto-Negotiation Process 11 Auto-Negotiation Process Complete....... default = 0
Complete
0 Disable
1 Enable ...................................................default
10 Mask Interrupt on Page Received in Auto- 10 Page Received in Auto-Negotiation Process
Negotiation Process .......................................LH, default = 0
0 Disable
1 Enable ...................................................default
9 Mask Interrupt on Jabber Condition Detect 9 Jabber Condition Detect...................LH, default = 0
0 Disable
1 Enable ...................................................default
8 Mask Interrupt on Invalid Symbol Received 8 Error Code Symbol Received...........LH, default = 0
0 Disable
1 Enable ...................................................default
7 Mask Interrupt on SSD Delimiter Error Detected 7 Start of Stream Delimiter Error ......LH, default = 0
0 Disable
1 Enable ...................................................default
6 Mask Interrupt on ESD Delimiter Error Detected 6 End of Stream Delimiter Error........LH, default = 0
0 Disable
1 Enable ...................................................default
5 Mask Interrupt on Signal Quality Error Detected 5 Signal Quality Error Detected .........LH, default = 0
0 Disable
1 Enable ...................................................default
4 Mask Interrupt on Link Fail Counter in Rx15 4 Link Fail Counter in Rx15 Count to Max
Count to Max .......................................LH, default = 0
0 Disable
1 Enable ...................................................default
3 Mask Interrupt on Invalid Symbol Received 3 Invalid Symbol Received Counter in Rx16 Count
Counter in Rx16 Count to Max to Max .......................................LH, default = 0
0 Disable
1 Enable ...................................................default
2 Mask Interrupt on False Carrier Counter in Rx17 2 False Carrier Counter in Rx17 Count to Max
Count to Max .......................................LH, default = 0
0 Disable
1 Enable ...................................................default
1-0 Reserved ........................................ always reads 0 1 PHY Speed Status .................................... default = 0
0 PHY Duplex Status .................................. default = 0

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Offset 21 (15h) – Link Fail Counter (0000h) ...................RO Offset 23 (17h) – False Carrier / SQE Counter (0000h). RO
15-0 Link Fail Count........................................ default = 0
Speed 100
15-0 False Carrier Count ................................. default = 0
Offset 22 (16h) – Invalid Symbol / Jabber Error Counter
Speed 10
(0000h) ................................................................................RO
15-0 SQE Detect Count .................................... default = 0
Speed 100
15-0 Count of Invalid Symbols Received ....... default = 0
Speed 10
15-0 Jabber Detect Count................................ default = 0

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Offset 26 (1Ah) – PHY Test Configuration 1 (0012h) ...RW Offset 27 (1Bh) – PHY Test Configuration 2 (C500h) .. RW
15 PHY Capability to Set Baseline Wander 15 10 Squelch Signals Debounce
Correction Circuit Correction Amount 0 Disable
1 Enable 14 10 Squelch Signals Go Idle State Debounce
14-9 Baseline Wander Correction Circuit Value 0 Disable
8 PHY Capability to Read Baseline Wander 1 Enable................................................... default
Correction Circuit Correction Amount 13 10 Squelch Signals Idle Condition Select ..... def = 0
0 Disable ...................................................default 12 NLP Pulse Length
1 Enable 0 100 ns .................................................... default
1 150 ns
7 Baseline Wander Upper Limit Overflow 11 Force Transmit Data
Indication .......................................................... LH 0 Disable................................................... default
0 Disable ...................................................default 1 Enable
1 Enable 10 NLP Watchdog
6 Baseline Wander Lower Limit Overflow 0 Disable
Indication .......................................................... LH 1 Enable (10 will go Link Fail if too many
0 Disable ...................................................default NLP’s received in NLPMinTime at Link Up
1 Enable Status)................................................... default
9 Set Rx21-23 MIB Counters to FFFEh
5-4 FTxD10, FTxData10En Clock Phase Selection 0 Disable................................................... default
......................................... default = 01b 1 Enable.......................................... Self Clearing
8 10 Stop Receive Data if Squelch Signals Go Idle
3 Drive Kill Pattern Mode State
0 Disable ...................................................default 0 Disable
1 Enable 1 Enable................................................... default
7 Drive Overshoot Pattern for 100 Characterization
2 Asynchronous Baseline Wander Correction 0 Disable................................................... default
0 Disable ...................................................default 1 Enable
1 Enable 6 Fast Drive NLP Pattern for 10 Characterization
1-0 Asynchronous Baseline Wander Correction Peak 0 Disable................................................... default
Detection Threshold ........................... default = 10h 1 Enable
5 F Direct Drive (See Bits 0-4)
0 Disable................................................... default
1 Enable
4 Replacement Value for TXER if FDirectDrive
(bit-5) is Set
3-0 Replacement Value for TXD if FDirectDrive (bit-
5) is Set

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Offset 28 (1Ch) – PHY Test Configuration 3 (0208h) ...RW Offset 29 (1Dh) – PHY Test Configuration 4 (0030h)... RW
15 Hold DPLL Phase Setting 15 Hold Adeq Operation, Keep Current Equalizer
0 Disable ...................................................default Gain Setting
14-10 DPLL Clock Phase Setting...................... default = 0 1 Enable
9-8 DPLL Low Pass Filter Bandwidth ..... default = 10b 14-9 Adeq Gain Amount Setting ..................... default = 0
7 Output DPLL Recovered Clock Phase to PHY 8 Adeq Can Output Gain Setting
0 Disable ...................................................default 0 Disable................................................... default
1 Enable 1 Enable
6 PHY Set DPLL Phase Capability 7 PHY Can Set Adeq Gain Amount
1 Enable 1 Enable
5 DPLL Loopback Mode 6-5 Adeq Low Pass Filter Bandwidth ....... default = 01b
0 Disable ...................................................default 4 Adeq Test Buffers AOP1/AON1, AOP2/AON2
1 Enable 0 Disable
4 Rd100, Rd10 Output to PHY 1 Enable................................................... default
0 Disable ...................................................default 3-2 Adeq Clock Setting for 100BaseT Adaptive
1 Enable Equalizer .............................................. default = 0
3 Slew Rate Control for 100 Transmitter 1 Bypass 10BaseT Receiver Filter
0 Disable 0 Disable................................................... default
1 Enable ...................................................default 1 Enable
2 Baseline Wander Correction 0 Mask Sqh10m and Sq110m in Test Mode
1 Enable 1 Enable
1 Equalizer Peak Detector Scheme Control Using
Value in Bit-0
0 Disable ...................................................default
Offset 30 (1Eh) – PHY Test Configuration 5 (001Bh) .. RW
1 Enable
0 Control Equalizer Peak Detector Scheme ... def = 0 15-14 Fx Mode Transmitter Current Source Control,
10BaseT Transmitter Output Slew Rate Control
.......................................... default = 00b
13-12 10BaseT Pre-Emphasis Control.......... default = 00b
11-10 Control Attenuator Attenuation Factor,
100 Transmitter Output Amplitude ... default = 00b
9-8 100BaseT Programmable Select Clock Phase to
Latch Transmit Data ........................... default = 00b
7-6 10BaseT Transmitter Output Signal Amplitude
.......................................... default = 00b
5-3 ADEQ Peak Detector Reference Peak Select
........................................ default = 011b
2-0 ADEQ Slicer Threshold Level Select
........................................ default = 011b
Offset 31 (1Fh) – PHY Test Configuration 6 (0000h) ... RW

15-10 Select Signal Output to LED Pins........... default = 0
9-5 Select Signal Output to MII Pins ............ default = 0
4 Speedup Flags in NwayTxSm.................. default = 0
3 Speedup Tx10Flag in TxAct10................ default = 0
2 Speedup NLPMaxFlag in Timer............. default = 0
1 Speedup NLPMinFlag in Timer ............. default = 0
0 Speedup StabFlag in MLTStatus............ default = 0

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FUNCTIONAL DESCRIPTION
General
The VT6103 is a complete 10 / 100 Mbps Ethernet Media On the receive side for 100 Mbps TX operation, the twisted
Interface IC. The VT6103 has the following main sections: pair receiver receives incoming encoded and scrambled MLT-
controller interface, encoder, decoder, scrambler, descrambler, 3 data from the twisted pair cable, removes any high
clock and data recovery, twisted pair transmitter, twisted pair frequency noise, equalizes the input signal to compensate for
receiver, and MI serial port. A block diagram is shown in the effects of the cable, qualifies the data with a squelch
Figure 3. algorithm, and converts the data from MLT-3 coded twisted
pair levels to internal digital levels. The output of the twisted
The VT6103 can operate as a 100Base-TX device (hereafter
pair receiver then goes to a clock and data recovery block
referred to as 100 Mbps mode) or as a 10Base-T device
which recovers a clock from the incoming data, uses the clock
(hereafter referred to as 10 Mbps mode). The differences
to latch in valid data into the device, and converts the data
between 100 Mbps mode and 10 Mbps mode are data rate,
back to NRZ format. The NRZ data is then unscrambled and
signalling protocol, and allowed wiring. 100 Mbps TX mode
decoded by the 4B5B decoder and descrambler, respectively,
uses two pairs of category 5 or better UTP or STP twisted pair
and outputted to an external Ethernet controller by the
cable with 4B5B encoded, scrambled, and MLT-3 coded 62.5
controller interface. 10 Mbps operation is similar to 100
MHz ternary data to achieve a throughput of 100 Mbps. 10
Mbps TX operation except (1) there is no
Mbps mode uses two pairs of category 3 or better UTP or STP
scrambler/descrambler, (2) the encoder/decoder is Manchester
twisted pair cable with Manchester encoded, 10 MHz binary
instead of 4B5B, (3) the data rate is 10 Mbps instead of 100
data to achieve a 10 Mbps thruput. The data symbol format
Mbps, and (4) the twisted pair symbol data is two level
on the twisted pair cable for the 100 and 10 Mbps modes is
Manchester instead of ternary MLT-3.
defined in the IEEE 802.3 specification.
The Management Interface, (hereafter referred to as the MI
On the transmit side for 100 Mbps TX operation, data is
serial port), is a two-pin bidirectional link through which
received on the controller interface from an external Ethernet
configuration inputs can be set and status outputs can be read.
controller. The data is then sent to the 4B5B encoder for
Each block plus the operating modes is described in more
formatting. The encoded data is then sent to the scrambler.
detail in the following sections. Since the VT6103 can
The scrambled and encoded data is then sent to the TP
operate as either a 100Base-TX or a 10Base-T device, each of
transmitter. The TP transmitter converts the encoded and
the following sections describes the performance of the
scrambled data into MLT-3 ternary format, preshapes the
respective section in both 100 and 10 Mbps modes.
output, and drives the twisted pair cable.
Revision 1.1 April 15, 2002 -16- Functional Description

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MII INTERFACE
MDIO/NDC
MII PIN
S100
PhyMap
Watchmux Block
S100
5B/4B ByPass 4B/5B 4B/5B

S10 S10
S100
S100
S_TO_P P_TO_S
ByPass SERIAL /
(Rx10 (Tx10
PARALLEL
Rx100) Tx100)
S100
S100
S10
S10
ByPass DESCRAM /
DESCRAM SCRAM
SCRAM
S100 ENMACH S100

DEMACH
ByPass Encode /
DENRZI ENNRZI
Decode
S10
S100
NWayArb S10
Mux S100
(From Analog or MII NWayTx
pad for tdm or Inter NWayRx
Loop)
NLP Rx LinkStatus Mux (Select DrvCmd

or standard output)
Signal detect
TRANSCEIVER INTERFACE
DPLL
NRZI to
MLT3
SLICER
APLL
MLT3 to NRZI FXTX 10TX
10RX FXRX 100TX

Adaptive EQ
BaseLine Wander OSC PAD
RXTP/RXFX TXTP/TXFX
Figure 3. Internal Block Diagram

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802.3u MII
The VT6103 incorporates the Media Independent Inter-face The VT6103 waits until it has received this preamble
(MII) as specified in clause 22 of the IEEE 802.3u standard. sequence before responding to any other transaction. Once
This interface may be used to connect PHY devices to MAC the VT6103 serial management port has initialized, no further
or repeater devices in 10/100 Mb/s systems. This section preamble sequencing is required until after a power-on / reset
describes both the serial MII management interface as well as has occurred. The Start code is indicated by a <01> pattern.
the nibble wide MII data interface. The management interface This assures the MDIO line transitions from the default idle
of the MII allows the configuration and control of multiple line state. Turnaround is an idle bit time inserted between the
PHY devices, the gathering of status and error information, Register Address field and the Data field. To avoid
and the determination of the type and abilities of the attached contention, no device actively drives the MDIO signal during
PHY(s). The nibble wide MII data interface consists of a the first bit of Turnaround during a read transaction. The
receive bus and a transmit bus each with control signals to addressed VT6103 drives MDIO with a zero for the second bit
facilitate data transfer between the PHY and the upper layer of Turn-around and follows this with the required data. IEEE
(MAC or repeater.) The VT6103 supports the MII interrupt 802.3 section 22.3.4.1 shows the timing relationship between
function. MDC and MDIO as driven / received by the Station
Management Entity (SME) and the VT6103 (PHY) for a
Serial Management Register Access typical register read access. For write transactions, the station
management entity writes data to an addressed VT6103
The serial MII specification defines a set of thirty-two 16-bit
eliminating the requirement for MDIO Turnaround. The
status and control registers that are accessible through the
Turnaround time is filled by the management entity inserting
serial management data interface pins MDC and MDIO. The
<10> for these two bits.
VT6103 implements all the required MII registers as well as
several optional registers. These registers are fully described
in the registers section of this document. A description of the Preamble Suppression
serial management access protocol follows. The VT6103 supports a Preamble Suppression mode. If the
station management entity (i.e. MAC or other management
Serial Management Access Protocol controller) determines that all PHYs in the system support
Preamble Suppression by returning a one in this bit, then the
The serial control interface consists of two pins, Management
station management entity need not generate preamble for
Data Clock (MDC) and Management Data Input/Output
each management transaction. The VT6103 requires a single
(MDIO). MDC has a maximum clock rate of 10 MHz and no
initialization sequence of 32 bits of preamble following
minimum rate. The MDIO line is bidirectional and may be
power-up/hardware reset. This requirement is generally met
shared by up to 32 devices. The MDIO frame format is
by the mandatory pull-up resistor on MDIO in conjunction
shown in IEEE802.3, section 22.2.4.4. The MDIO pin has an
with a continuous MDC, or the management access made to
internal pull-up resistor (1.5Kohm) which will pull MDIO
determine whether Preamble Suppression is supported. While
high during IDLE and turnaround. In order to initialize the
the VT6103 requires an initial preamble sequence of 32 bits
MDIO interface, the station management entity sends a
for management initialization, it does not require a full 32 bit
sequence of 32 contiguous logic ones on MDIO to provide the
sequence between each subsequent transaction. A minimum
VT6103 with a sequence that can be used to establish
of one idle bit between management transactions is required as
synchronization. This preamble may be generated either by
specified in IEEE 802.3u.
driving MDIO high for 32 consecutive MDC clock cycles, or
by simply allowing the MDIO pull-up resistor to pull the
MDIO pin high during which time 32 MDC clock cycles are PHY Address Sensing
provided. In addition, 32 MDC clock cycles should be used if The VT6103 can be set to respond to any of the possible 32
an invalid start, pop code, or turn-around bit is detected. PHY addresses. Each VT6103 connected to a common serial
MII must have a unique address. It should be noted that while
an address selection of all zeros <00000> will result in PHY
Isolate mode, this will not effect serial management access.
The VT6103 provides five PHY address pins, the state of
which are latched into the PHYCTRL register (address 10h) at
system power-up / reset. These pins are described in the pin
descriptions section of this document.

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Nibble-Wide MII Data Interface Carrier Sense

Clause 22 of the IEEE 802.3u specification defines the Media Carrier Sense (CRS) may be asserted due to receive activity,
Independent Interface. This interface includes a dedicated once valid data is detected via the Smart Squelch function
receive bus and a dedicated transmit bus. These two data during 10 Mb/s operation. For 10 Mb/s Half Duplex
buses, along with various control and indicate signals, allow operation, CRS is asserted during either packet transmission
for the simultaneous exchange of data between the VT6103 or reception. For 10 Mb/s Full Duplex operation, CRS is
and the upper layer agent (MAC or repeater). The receive asserted only due to receive activity. CRS is deasserted
interface consists of a nibble wide data bus RXD[3:0], a following an end of packet. In Repeater mode (pin 63 / bit 9,
receive error signal RXER, a receive data valid flag RXDV, register address 19h), CRS is only asserted due to receive
and a receive clock RXC for synchronous transfer of the data. activity.
The receive clock can operate at either 2.5 MHz to support 10
Mb/s operation modes or at 25 MHz to support 100 Mb/s MII Isolate Mode
operational modes. The transmit interface consists of a nibble
A 100Base-X PHY connected to the mechanical MII inter-
wide data bus TXD[3:0], a transmit error flag TXER, a
face specified in IEEE 802.3u is required to have a default
transmit enable control signal TXEN, and a transmit clock
value of one in bit 10 of the Basic Control Register (BCR,
TXC which runs at either 2.5 MHz or 25 MHz. Additionally,
address 00h.). The VT6103 will set this bit to one if the PHY
the MII includes the carrier sense signal CRS, as well as a
Address is set to 00000 upon power-up / hardware Reset.
collision detect signal COL. The CRS signal asserts to
Otherwise, the VT6103 will set this bit to zero upon power-up
indicate the reception of data from the network or as a
/ hardware reset. With bit 10 in the BMCR set to one, the
function of transmit data in Half Duplex mode. The COL
VT6103 does not respond to packet data present at TXD[3:0],
signal asserts as an indication of a collision which can occur
TXEN, and TXER inputs and presents a high impedance on
during half-duplex operation when both a transmit and a
the TXCK, RXCK, RXDV, RXER, RXD[3:0], COL, and CRS
receive operation occur simultaneously.
outputs. The VT6103 will continue to respond to all serial
management transactions over the MII. While in Isolate
Collision Detect mode, the TX+ / ΤX− outputs are dependent on the current
For Half Duplex, a 10Base-T or 100Base-X collision is state of Auto-Negotiation. The VT6103 can Auto-Negotiate
detected when the receive and transmit channels are active or parallel detect to a specific technology depending on the
simultaneously. Collisions are reported by the COL signal on receive signal at the RX+ / RX− inputs. It is recommended
the MII. that the user have a basic understanding of clause 22 of the
If the VT6103 is transmitting in 10 Mb/s mode when a 802.3u standard.
collision is detected, the collision is not reported until seven
bits have been received while in the collision state. This
prevents a collision from being reported incorrectly due to
noise on the network. The COL signal remains set for the
duration of the collision. If a collision occurs during a receive
operation, it is immediately reported by the COL signal.
When heartbeat is enabled (only applicable to 10 Mb/s
operation), approximately 1 ms after the transmission of each
packet, a Signal Quality Error (SQE) signal of approximately
10 bit times is generated (internally) to indicate successful
transmission. SQE is reported as a pulse on the COL signal of
the MII.

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Link Integrity and AutoNegotiation FLP's from the remote device, then the remote device is
determined to have Auto Negotiation capability and the device
General then uses the contents of the MI serial port Auto Negotiation
The VT6103 can be configured to implement either the Advertisement register and FLP's to advertise its capabilities
standard link integrity algorithms or the Auto Negotiation to a remote device. The remote device does the same, and the
algorithm. The standard link integrity algorithms are used capabilities read back from the remote device are stored in the
solely to establish an active link to and from a remote device. MI serial port Auto Negotiation Remote End Capability
There are different standard link integrity algorithms for 10 register. The VT6103 negotiation algorithm then matches its
and 100 Mbps modes. The Auto Negotiation algorithm is capabilities to the remote device's capabilities and determines
used for two purposes: (1) To automatically configure the what mode the device should be configured to according to
device for either 10/100 Mbps and Half/Full Duplex modes, the priority resolution algorithm defined in IEEE 802.3 Clause
and (2) to establish an active link to and from a remote device. 28. Once the negotiation process is completed, the V6103
The standard link integrity and Auto Negotiation algorithms then configures itself for either 10 or 100 Mbps mode and
are described below. either Full or Half Duplex modes (depending on the outcome
of the negotiation process), and it switches to either the
100Base-TX or 10Base-T link integrity algorithms (depending
10Base-T Link Integrity Algorithm – 10Mbps
on which mode was enabled by AutoNegotiation). Refer to
The VT6103 uses the same 10Base-T link intergrity algorithm IEEE 802.3 Clause 28 for more details.
that is defined in IEEE 802.3 Clause 14. This algorithm uses
normal link pulses, referred to as NLP's and transmitted
AutoNegotiation Outcome Indication
during idle periods, to determine if a device has successfully
established a link with a remote device (called Link Pass The outcome or result of the Auto Negotiation process is
state). The transmit link pulse meets the template defined in stored in the speed detect and duplex detect bits in the MI
IEEE 802.3 Clause 14. Refer to IEEE 802.3 Clause 14 for serial port Status Output register.
more details if needed.
AutoNegotiation Status
100Base-TX Link Integrity Algorithm -100Mbps The status of the Auto Negotiation process can be monitored
Since 100Base-TX is defined to have an active idle signal, by reading the Auto Negotiation acknowledgement bit in the
there is no need to have separate link pulses like those defined MI serial port Status register. The MI serial port Status
for 10Base-T. The VT6103 uses the squelch criteria and register contains a single Auto Negotiation acknowledgement
descrambler synchronization algorithm on the input data to bit which indicates when an AutoNegotia-tion has been
determine if the device has successfully established a link with initiated and successfully completed.
a remote device (called Link Pass state). Refer to IEEE 802.3
for both of these algorithms for more details. AutoNegotiation Enable
The Auto Negotiation algorithm can be enabled (or re-started)
AutoNegotiation Algorithm by setting the Auto Negotiation enable bit in the MI serial port
As stated previously, the Auto Negotiation algorithm is used Control register or by strapping the LED3 pin (NWAYEN
for two purposes: (1) To automatically configure the device strap). When the Auto Negotiation algorithm is enabled, the
for either 10/100 Mbps and Half/Full Duplex modes, and (2) device halts all transmissions including link pulses for 1250-
to establish an active link to and from a remote device. The 1600 mS, enters the Link Fail State, and restarts the
Auto Negotiation algorithm is the same algorithm that is negotiation process. When the Auto Negotiation algorithm is
defined in IEEE 802.3 Clause 28. Auto Negotiation uses a disabled, the selection of 100 Mbps or 10 Mbps modes is
burst of link pulses, called fast link pulses and referred to as determined by the speed select bit in the MI serial port Control
FLP's, to pass up to 16 bits of signaling data back and forth register, and the selection of Half or Full Duplex is
between the VT6103 and a remote device. The transmit FLP determined by the duplex select bit in the MI serial port
pulses meet the templated specified in IEEE 802.3. A timing Control register.
diagram contrasting NLP's and FLP's is shown in IEEE802.3.
The Auto Negotiation algorithm is initiated by any of the Auto Negotiation Reset
following events: (1) Power up, (2) device reset, (3) Auto The AutoNegotiation algorithm can be initiated at any time by
Negotiation reset, (4) Auto Negotiation enabled, or (5) a setting the Auto Negotiation reset bit in the MI serial port
device entering the Link Fail State. Once a negotiation has Control register.
been initiated, the VT6103 first determines if the remote
device has Auto Negotiation capability. If the remote device
Link Indication
is not Auto Negotiation capable and is just transmitting either
a 10Base-T or 100Base-TX signal, the VT6103 will sense that Link activity is also indicated on the LED0 pin whenever a
and place itself in the correct mode. If the VT6103 detects link is detected. LED0 starts blinking on activity.

Technologies, Inc.
Encoder Decoder
4B5B Encoder – 100 Mbps 4B5B Encoder – 100 Mbps

100Base-TX requires that the data be 4B5B encoded. 4B5B Since the TP input data is 4B5B encoded on the transmit side,
coding converts the 4-Bit data nibbles into 5-Bit data code it must also be decoded by the 4B5B decoder on the receive
words. The mapping of the 4B nibbles to the 5B code words side. The mapping of 5B nibbles to 4B code words is
is specified in IEEE 802.3. The 4B5B encoder takes 4B specified in IEEE 802.3. The 4B5B decoder takes the 5B
nibbles and converts to 5B words according to IEE802.3, and code words from the descrambler, converts them into 4B
sends the 5B words to the scrambler. The 4B5B encoder also nibbles. The 4B5B decoder also strips off the SSD delimiter
substitutes the first 8 bits of the preamble with the SSD (/J/K symbols) and replaces them with two 4B Data 5 nibbles
delimiters (/J/K symbols) and adds an ESD delimiter (/T/R (/5 symbol), and strips off the ESD delimiter (/T/R symbols)
symbols) to the end of every packet, as defined in IEEE 802.3. and replaces it with two 4B Data 0 nibbles (/I symbol), per
The 4B5B encoder also fills the period between packets, IEEE 802.3 specifications. The 4B5B decoder detects SSD,
called the idle period, with a continuous stream of idle ESD and, codeword errors in the incoming data stream as
symbols, as shown in IEE802.3. specified in IEEE 802.3. These errors are indicated by
asserting RXER output while the errors are being transmitted
Manchester Encoder – 10 Mbps across RXD[3:0], and they are also indicated in the MI
Register by setting SSD, ESD, and codeword error bits in the
The Manchester encoding process combines clock and NRZ
MI Status Output register.
data such that the first half of the data bit contains the
complement of the data, and the second half of the data bit
contains the true data, as specified in IEEE 802.3. This Manchester Encoder – 10 Mbps
guarantees that a transition always occurs in the middle of the In Manchester coded data, the first half of the data bit contains
bit cell. The Manchester encoder in the VT6103 converts the the complement of the data and the second half of the data bit
10 Mbps NRZ data from the controller interface into a contains the true data. The Manchester decoder converts the
Manchester Encoded data stream for the TP transmitter and Manchester encoded data stream from the TP receiver into
adds a start of idle pulse (SOI) at the end of the packet as NRZ data for the controller interface by decoding the data and
specified in IEEE 802.3. Manchester encoding of the NRZ stripping off the SOI pulse. Since the clock and data recovery
data occurs only when TXEN is asserted. block has already separated the clock and data from the TP
receiver, the Manchester decoding process to NRZ data is
inherently performed by that block.

Technologies, Inc.
Clock and Data Recovery Scrambler / Descrambler
Clock Recovery – 100 Mbps 100 Mbps Scrambler

Clock recovery is done with a PLL. If there is no valid data 100Base-TX requires scrambling to reduce the radiated
present on the TP inputs, the PLL is locked to the 25 MHz emissions on the twisted pair. The VT6103 scrambler takes
TXC Transmit Clock. When valid data is detected on the TP the encoded data from the 4B5B encoder, scrambles it per the
inputs with the squelch circuit and when the adaptive IEEE 802.3TP-PMD specifications, and sends it to the TP
equalizer has settled, the PLL input is switched to the transmitter.
incoming data on the TP input. The PLL then recovers a
clock by locking onto the transitions of the incoming signal 10 Mbps Scrambler
from the twisted pair wire. The recovered data clock
A scrambler is not used in 10 Mbps mode.
frequency is 125 MHz and is divided down to produce a 25
MHz clock that is sent to the controller interface signal RXC
Receive Clock. The PLL can reliably perform the clock and 100 Mbps Descrambler
data recovery process with up to +/-3 ns or jitter on the TP The VT6103 descrambler takes the scrambled data from the
input. The VT6103 has an internal PLL watchdog timer that data recovery block, descrambles it per the IEEE 802.3 TP-
monitors the receiver PLL output frequency. If the receive PMD specifications, aligns the data on the correct 5B word
PLL output frequency deviates from the TXC frequency by boundaries, and sends it to the 4B5B decoder. The algorithm
more that 3% over a 8 us interval, the device assumes that the for synchronization of the descrambler is the same as the
receive PLL has not locked onto the TP input data properly algorithm outlined in the IEEE802.3 TP-PMD specification.
and the PLL is reset. The PLL is reset by switching its input Once the descrambler is synchronized, it will maintain
from the TP input data to the TXC for a period of 200 us to synchronization as long as enough descrambled idle pattern
retrain it to the 25 MHz frequency from the oscillator. 1's are detected within a given interval. To stay in
synchronization, the descrambler needs to detect at least 25
Data Recovery – 100 Mbps consecutive descrambled idle pattern 1's in a 1 ms interval. If
25 consecutive descrambled idle pattern 1's are not detected
Data recovery is performed by latching in valid data from the
within the 1 ms interval, the descrambler goes out of
TP receiver with the recovered clock extracted by the PLL.
synchronization and restarts the synchronization process. If
When invalid data is detected on the TP input, the receive data
the descrambler is in the unsynchronized state, the
is held low. When valid data is detected on the TP inputs, the
descrambler loss of synchronization detect bit is set in the MI
clock recovery block extracts a 125 MHz clock from the data
Status Output register to indicate this condition. Once this bit
stream from the TP receiver. This 125 MHz recovered clock
is set, it will stay set until the descrambler achieves
is then used to latch in valid data from the TP receiver.
synchronization. The output of the descrambler is also
aligned according to the 4B/5B code groups. This alignment
Clock Recovery – 10 Mbps procedure is done by looking for the /J/K/ symbols at the
The clock recovery process for 10 Mbps mode is identical to beginning of the packet and then aligning all subsequent
the 100 Mbps mode except, (1) the recovered clock frequency 4B/5B words relative to the beginning of the /J/K/ symbols.
is a 2.5 MHz nibble clock, (2) the PLL is switched from TXC
to the TP input when the squelch indicates valid data, and (3) 10 Mbps Descrambler
the PLL takes up to 12 transitions (bit times) to lock onto the
A descrambler is not used in 10 Mbps mode.
preamble, so some of the preamble data symbols are lost, but
the clock recovery block recovers enough preamble symbols
to pass at least 6 nibbles of preamble to the receive controller
interface.
Data Recovery – 10 Mbps

The data recovery process for 10 Mbps mode is identical to
the 100 Mbps mode. As mentioned in the Manchester
Decoder section, the data recovery process inherently
performs decoding of Manchester encoded data from the TP
inputs.

Technologies, Inc.
Twisted Pair Transmitter
Transmitter - 100 Mbps Transmitter - 10 Mbps

The transmitter consists of an MLT-3 encoder, waveform The operation of the 10 Mbps transmitter is much different
generator and line driver. The MLT-3 encoder converts the from the operation of the 100 Mbps transmitter. Even so, the
NRZ data from the scrambler into a three level MLT-3 code. transmitter still consists of a waveform generator and line
MLT-3 coding uses three levels, converts 1's to transitions driver. The purpose of the waveform generator is to shape the
between the three levels, and converts 0's to no transitions or output transmit pulse.
changes in level. The purpose of the waveform generator is to
shape the transmitter output pulse. The waveform generator
takes the MLT-3 three level encoded waveform and uses an
array of switched current sources to control the rise / fall time
and level of the signal at the output. The output of the
switched current sources then goes through a lowpass filter in
order to "smooth" the current output and remove any high
frequency components. In this way, the waveform generator
preshapes the output waveform transmitted onto the twisted
pair cable to meet the pulse template requirements outlined in
IEEE 802.3. The waveform generator eliminates the need for
any external filters on the TP transmit output. The line driver
converts the shaped and smoothed waveform to a current
output that can drive 100 meters of category 5 unshielded
twisted pair cable or 150 ohm shielded twisted pair cable.

Technologies, Inc.
Twisted Pair Receiver the three level MLT-3 encoded output data from the
comparators and converts it to normal NRZ data to be used for
clock and data recovery.
Receiver - 100 Mbps
The TP receiver detects input signals from the twisted pair Receiver - 10 Mbps
input and converts them to a digital data bit stream ready for The 10 Mbps receiver is able to detect input signals from the
clock and data recovery. The receiver can reliably detect data twisted pair cable that are within the template shown in
from a 100Base-TX compliant transmitter that has been IEEE802.3. The inputs are biased by internal resistors. The
passed through 0-100 meters of 100 Ohm category 5 UTP or TP inputs pass through a low pass filter designed to eliminate
150 Ohm STP. The 100 Mbps receiver consists of a level any high frequency noise on the input. The output of the
shifter, low pass filter, adaptive equalizer, peak detector, receive filter goes to two different types of comparators:
comparator, baseline wander correction circuit, and MLT-3 squelch and zero crossing. The squelch comparator
decoder. A block diagram of the receiver is shown in Figure determines whether the signal is valid and the zero crossing
3. The TP receiver inputs are assumed to be transformer comparator is used to sense the actual data transitions once the
coupled and terminated by external resistors. The TP inputs signal is determined to be valid. The output of the squelch
are then level shifted and pass through a 2nd order low pass comparator goes to the squelch circuit and is also used for link
filter designed to eliminate any high frequency noise on the pulse detection, SOI detection, and reverse polarity detection.
input. The signal then goes to an adaptive equalizer. The The output of the zero crossing comparator is used for clock
adaptive equalizer consists of a programmable bandpass filter and data recovery in the Manchester decoder.
and peak detector. The adaptive equalizer uses the bandpass
filter characteristic to compensate for the low pass
characteristics of the cable, and it uses the peak detector to
capture the peak value of the input waveform. It then uses the
peak value as a measure of cable length to adjust the pole and
zero placement of the bandpass filter. The bandpass filter is
digitally programmable and has a 5 bit digital input, called the
equalizer setting, that adjusts the frequency response to one of
32 settings. The peak detector captures the peak voltage of
the TP inputs, qualifies the input, and digitizes the qualified
value to a 5 bit digital result. This digital result, called the
equalizer setting, is used to adjust the programmable bandpass
filter characteristic. The peak detector qualifies the incoming
data stream by only allowing single and double baud wide
pulses to update the equalizer setting. If the digitized peak
value of any single or double baud wide pulse deviates from
the current equalizer setting in the same direction for more
than 16 consecutive pulses, the equalizer setting is
incremented by one digital step only, independent of how
much the new setting and current setting differ. The equalizer
updating is only enabled when the receiver is in the unsquelch
state (valid data detected by the TP squelch circuit). The
baseline wander correction circuit restores the DC component
of the input waveform that was removed by external
transformers by subtracting the filtered output of the data
comparator from the filtered output of the equalizer and
adding this difference back into the input of VT6103. The
baseline wander correction circuit is only enabled when the
descrambler is in the synchronized state. The comparators are
used to qualify and slice the data. There are two types of
receive comparators: squelch and data. The squelch
comparator compares the signal and the output of the LPF
before the equalizer against a fixed threshold. The output of
the squelch comparator is used by the squelch circuit and link
integrity blocks to qualify the data. The data comparators
compare the signal at the output of the equalizer against fixed
positive and negative thresholds. The MLT-3 decoder takes

Technologies, Inc.
Miscellaneous Functions
Smart Squelch Collision Detection

Smart squelch is responsible for determining when valid data For Half Duplex, a 10Base-T collision is detected when the
is present on the differential receive inputs (TPRD+/-). The receive and transmit channels are active simultaneously.
VT6103 implements an intelligent receive squelch algorithm Collisions are reported by the COL signal on the MII. If the
to ensure that impulse noise on the receive inputs will not be ENDEC is transmitting when a collision is detected, the
mistaken for a valid signal. Smart squelch operation is collision is not reported until seven bits have been received
independent of the 10Base-T operational mode. The squelch while in the collision state. This prevents a collision from
circuitry employs a combination of amplitude and timing being reported incorrectly due to noise on the network. The
measurements (as specified in the IEEE 802.3 10Base-T COL signal remains set for the duration of the collision. If the
standard) to determine the validity of data on the twisted pair ENDEC is receiving when a collision is detected, it is reported
inputs (refer to IEEE802.3). immediately (through the COL signal). When heartbeat is
enabled, approximately 1 ms after the transmission of each
The signal at the Start of Packet is checked by the smart
packet, a Signal Quality Error (SQE) signal of approximately
squelch circuit and any pulses not exceeding the squelch level
10 bit times is generated (internally) to indicate successful
(either positive or negative, depending upon polarity) will be
transmission. SQE is reported as a pulse on the COL signal of
rejected. Once this first squelch level is overcome correctly,
the MII.
the opposite squelch level must then be exceeded within 150
ns. Finally the signal must exceed the original squelch level
within a further 150 ns to ensure that the input waveform will Carrier Sense
not be rejected. The checking procedure results in the loss of Carrier Sense (CRS) may be asserted due to receive activity
typically three preamble bits at the beginning of each packet. once valid data is detected via the smart squelch function. For
Only after all these conditions have been satisfied will a 10 Mb/s Half Duplex operation, CRS is asserted during either
control signal be generated to indicate to the remainder of the packet transmission or reception. For 10 Mb/s Full Duplex
circuitry that valid data is present. At this time, the smart operation, CRS is asserted only due to receive activity. CRS
squelch circuitry is reset. Valid data is considered to be is deasserted following an end of packet. In Repeater mode,
present until squelch level has not been generated for a time CRS is only asserted due to receive activity.
longer than 150ns, indicating End of Packet. Once good data
has been detected the squelch levels are reduced to minimize Normal Link Pulse Detection / Generation
the effect of noise causing premature End of Packet detection.
The receive squelch threshold level can be lowered for use in The link pulse generator produces pulses as defined in the
longer cable or STP applications. This is achieved by setting IEEE 802.3 10Base-T standard. Each link pulse is nominally
the F10LSS bit in the PHYCONFIG register (bit 7, register 100 ns in duration and is transmitted every 16 ms ± 8 ms, in
10h). the absence of transmit data. Link pulse is used to check the
integrity of the connection with the remote end. If valid link
pulses are not received, the link detector disables the 10Base-
T twisted pair trans-mitter, receiver and collision detection
functions. When the link integrity function is disabled, the
10Base-T transceiver will operate regardless of the presence
of link pulses.

Technologies, Inc.
Jabber Function Automatic Link Polarity Detection

The jabber function monitors the VT6103's output and The VT6103's 10Base-T transceiver module incorporates an
disables the transmitter if it attempts to transmit a packet of automatic link polarity detection circuit. When seven
longer than legal size. A jabber timer monitors the transmitter consecutive link pulses or three consecutive receive packets
and disables the transmission if the transmitter is active for with inverted End-of-Packet pulses are received, bad polarity
approximately 20-30 ms. Once disabled by the Jabber is reported. The VT6103's 10Base-T transceiver module
function, the transmitter stays disabled for the entire time that corrects for this error internally and will continue to decode
the ENDEC module's internal transmit enable is asserted. received data correctly. This eliminates the need to correct the
This signal has to be deasserted for approximately 400-600 ms wiring error immediately.
(the “unjabber” time) before the Jabber function re-enables the
transmit outputs. The Jabber function is only meaningful in Internal Loopback
10Base-T mode.
When the FLB_DPLL bit (bit-5) of the PHY Configuration
Register (register address 1Ch) is set, transmit data is looped
Status Information back in the ENDEC to the receive channel. The transmit
VT6103 Status Information is available on the LED output drivers and receive input circuitry are enabled in transceiver
pins. Transmit activity, receive activity, link status, link loopback mode. Loopback is used for diagnostic testing of
polarity and collision activity information is output to the four the data path through the transceiver without transmitting on
LED output pins, selectable via LEDSEL at Rx16 (Rx10h) the network or being interrupted by receive traffic. This
bit[6:5] as follows: loopback function causes the data to loop back via the output
driver buffers such that the entire transceiver path is tested.
Table 6. LED Function Definition
LEDSE
LED0 LED1 LED2 LED3
L
00 Link / Act Speed Duplex COL
01 Pwr / TxAct Link / RxAct Speed Duplex
10 Speed 100 Speed 10 Act Duplex
11 Pwr / TxAct Link / RxAct Speed COL

Technologies, Inc.
100Base-FX
The VT6103 is fully capable of supporting 100Base-FX

applications. 100Base-FX is similar to 100Base-TX with the
exceptions being the PMD sublayer, lack of data scrambling,
and signaling medium and connectors. Chapter 26 of the
IEEE 802.3u specification defines the interface to this PMD
sublayer. The VT6103 can be configured for 100Base-FX
operation through either hardware or software. Configuration
through hardware is accomplished by forcing the FXEN pin
(pin 34) to a logic low level prior to power-up / reset

Technologies, Inc.
APPLICATION SCHEMATICS
Revision 1.1 April 15, 2002 -28- Application Schematics

Technologies, Inc.
VT6103 U1
B1 -12V GF1 TRST# A1 AD31 119 AD31 MCRS 84 MCRS Optional
B2 A2 AD30 120 85 MCOL
TCK +12V AD30 MCOL 22
B3 A3 AD29 121 88 1 2 TXD3
GND0 TMS AD29 MTXD3
B4 A4 AD28 122 89 3 4 TXD2
TDO TDI AD28 MTXD2
B5 A5 AD27 125 90 5 6 TXD1
+5V_0 +5V_1 AD27 MTXD1
B6 A6 -INTA AD26 126 91 7 8 TXD0
+5V_2 INTA# AD26 MTXD0
R1 for EMI test B7 INTB# INTC# A7 AD25 127 AD25 MTXE 92 TXEN
-PRSNT1
B8
B9
INTD# +5V_3 A8
A9
AD24
AD23
128
3
AD24 MTXC 93
94
TXCK
RXER
RN1
EEPROM
PRSNT#1 RESERVED0 AD23 MERR
B10
RESERVED1 I/O_0
A10 AD22 5
AD22 MRXC
97 RXCK RN1 for EMI test U2
-PRSNT2 B11 A11 AD21 6 98 RXDV D3V3
PRSNT#2 RESERVED2 AD21 MRXDV EECS 1 8
AD20 7 99 RXD0 CS VCC
AD20 MRXD0 MD2 2 7
AD19 9 100 RXD1 SK NC2
Optional B14 A14 AD18 10
AD19 MRXD1
101 RXD2
MD1 3 DI NC1 6 C1
RESERVED3 3.3VAVX 3V3AUX AD18 MRXD2 MD0 4 5
B15 A15 -PCIRST AD17 11 102 RXD3 DO GND 0.1u
PCICLK 0 R1 GND3 RST# AD16 AD17 MRXD3 MDC
B16 A16 12 105 93C46-3P
CLK I/O_1 -GNT AD15 AD16 MDC MDIO
B17 GND4 GNT# A17 25 AD15 MDIO 106
-REQ B18 A18 AD14 26
REQ# GND14 -PME AD14
B19 A19 AD13 27 107 R2 D3V3
I/O_2 PME# AD13 VTEST
AD31 B20 A20 AD30 AD12 28
AD31 AD30 AD12
AD29 B21 A21 AD11 29 109 10K-0603 5%
AD29 +3.3V_0 AD11 PYHRST -PHYRST1
B22 A22 AD28 AD10 30 108 R3 D3V3
GND5 AD28 AD10 AUXRST#
AD27 B23 A23 AD26 AD9 33 110
AD25 AD27 AD26 AD8 AD9 WOL -PM E WOL 10K-0603 5%
B24 AD25 GND15 A24 34 AD8 PME# 111
B25 A25 AD24 AD7 36
-CBE3 +3.3V_1 AD24 IDSEL AD6 AD7
B26 A26 37 86 D3V3
AD23 C/BE3# IDSEL AD5 AD6 SVDD1
B27 A27 38 95
B28
AD23 +3.3V_2
A28 AD22 AD4 40
AD5 SVDD2
104 Optional
AD21 GND6 AD22 AD20 AD3 AD4 SVDD3
B29 A29 41
-BPWR
AD21 AD20 AD3
MA12
MA15
AD19 B30 A30 AD2 42
AD19 GND16 AD18 AD1 AD2 MA15
B31 A31 43 82
AD17 +3.3V_3 AD18 AD16 AD0 AD1 MA15 MA14 D3V3
B32 A32 44 81
-CBE2 AD17 AD16 AD0 MA14 MA13 10K-0603 5% R4
B33 C/BE2# +3.3V_4 A33 MA13 80
B34 A34 -FRAME -CBE3 1 79 MA12
GND7 FRAME# CBE3# MA12 10K-0603 5% R5 R6 10K-0603 5%
-IRDY B35 A35 -CBE2 14 78 MA11
IRDY# GND17 CBE2# MA11
B36 A36 -TRDY -CBE1 24 77 MA10
+3.3V_5 TRDY# CBE1# MA10
-DEVSEL B37 A37 -CBE0 35 76 MA9
DEVSEL# GND18 CBE0# MA9
B38 A38 -STOP 71 MA8
32
31
30
GND8 STOP# MA8
4
3
2
1
IDSEL MA7 U3
B39 LOCK# +3.3V_6 A39 2 IDSEL MA7 70
-PERR B40 A40 -FRAME 15 69 MA6
A12
A15
A16
A18
WE#
A17
PERR# RESERVED4 FRAME# MA6
VCC
B41 A41 -IRDY 16 68 MA5
+3.3V_7 RESERVED5 -TRDY IRDY# MA5 MA4 MA7
B42 A42 17 67 5 A7 A14 29 MA14
SERR# GND19 PAR -DEVSEL TRDY# MA4 MA3 MA6
B43 A43 18 64 6 A6 A13 28 MA13
-CBE1 +3.3V_8 PAR AD15 -STOP DEVSEL# MA3 MA2 MA5
B44 A44 19 63 7 A5 A8 27 MA8
AD14 C/BE1# AD15 PAR STOP# MA2 MA1 MA4
B45 A45 23 62 8 A4 A9 26 MA9
AD14 +3.3V_9 AD13 PCICLK PAR MA1 MA0 MA3
B46 A46 114 61 9 A3 A11 25 MA11
AD12 GND9 AD13 AD11 -INTA PCICLK MA0 MA2
B47 A47 112 10 A2 OE# 24 -BPRD
AD10 AD12 AD11 -PCIRST INTA# MA1 11 23
B48 A48 113 60 MD7 MA10
AD10 GND20 PCIRST# MD7 MA0 A1 A10
B49 A49 AD9 -GNT 117 59 MD6 12 22 -BPCS
M66EN AD9 GNT# MD6 MD0 A0 CE#
-REQ 118 58 MD5 13 21 MD7
REQ# MD5 10K-0603 5% DQ0 DQ7
-PERR 21 55 MD4
PERR# MD4
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
VSS
AD8 B52 A52 -CBE0 D3V3 54 MD3
AD8 C/BE0# MD3 R7
AD7 B53 A53 53 MD2 29020 / 39020
AD7 +3.3V_10 MD2/EECK
B54 A54 AD6 8 52 MD1
+3.3V_11 AD6 VDD1 MD1/EEDI
14
15
16
17
18
19
20
AD5 B55 A55 AD4 20 51 MD0
AD5 AD4 VDD2 MD0/EEDO
AD3 B56
B57
AD3
GND11
GND21
AD2
A56
A57 AD2
32
45
VDD3
VDD4 EECS 47 EECS BOOT
AD1 AD0 -BPCS
MD1
MD2
MD3
MD4
MD5
MD6
B58 A58 56 50
PCIVCC2 B59
AD1
I/O_3
AD0
I/O_4
A59 PCIVCC2 65
VDD5
VDD6
BPCS#
BPRD#
49 -BPRD
-BPWR
ROM
B60 A60 74 48
ACK64# REQ64# VDD7 BPWR#
B61 A61 83
+5V_4 +5V_5 VDD8 2
B62 A62 116 72 D3V3
+5V_6 +5V_7
123
VDD9 RAMVDD Remove when not using BootROM
VDD10 C2 R8
SVSS3
SVSS2
SVSS1
VSS11
VSS10
PCI32_62X2-UNIVERSAL 0.1u
VSS9
VSS8
VSS7
VSS6
VSS5
VSS4
VSS3
VSS2
VSS1
73
RAMVSS
124
115
103
D3V3
96
87
75
66
57
46
39
31
22
13
4
VDD DECOUPLING FOR VT6103
C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17

0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u
Figure 4. Application Schematic Example Page 1

Technologies, Inc.
D3V3
A3V3 U4
RX+ C19
C18
0.1u 25 INT#/PHYAD0 VDD2 24
RX- 0.1u LINK 26 23
SPEED LED0/LINK GND2
R9 R10 27 22 MCRS
DUPLEX LED1/SPD100 CRS/RPTR MCOL
28 LED2/DUPLEX COL/SYMB 21
1
49.9 1% 49.9 1% NWAY 29 20 TXD3
CN1 LED3/NWAYEN TXD3 TXD2
+ - T - + 30 19
X X T D D PD# TXD2 TXD1
RJ-45 C 31 18
R R C R R
RD- VDDRX TXD1 TXD0
1 32 17
RD+ RX- TXD0 TXEN
2 33 16
R11 SD RX+ TXEN TXC K
3 34 15
U5 SD/FXEN TXC TXER
4 10K 1% 35 14
GNDRX TXER
5 36 13
GTS FC-518LS R12 GNDPLL VDDC
6 37 12
7 + - - + 6.49K 1% 38
REXT GNDC
11 RXER RN2 for EMI test
X X T T D D VDDPLL RXER/ISO
RXCK
8 T T C C T T
TD-
39 GNDTXC RXC 10
RXDV
Optional
40 TX- RXDV/BYPOSC 9
TD+
LEG4
LEG3
LEG2
LEG1
41 TX+ GND1 8
10
11
12
13
14
15
16
R13 R14 R15 RN2 22
9
42 VDDTX VDD1 7
TX+ 43 6 1 2 RXD0
75 GNDTX RXD0/PHYAD4 RXD1
44 GNDOSC RXD1/PHYAD3 5 3 4
75 75 TX- 45 4 5 6 RXD2
XO RXD2/PHYAD2 RXD3
46 3 7 8
XI RXD3/PHYAD1
R18 47 2 MDC
A3V3 -PHYRST2 VDDOSC MDC
48 1 MDIO D3V3
R16 49.9 1% X1 RST# MDIO
C20 75 1%
0.01u/2KV 25MHz 1.50K 1% R19
1 2 VT610 3 SSOP48
R17
C21
49.9 1% 0.1u C22 C23
22p 22p
GTS FC-518LS
PULSE PE-68515
YCL
20PMT04/20PMT04B
D3V3
R20 10K-0603 5% NWAY
5VSB
PCIVCC2 U6 PCIVCC2 U7 D3V3
D3V3
AMS1117 R21 10K-0603 5% DUPLEX
1 8 AMS1117-3.3
3V3AUX 2
5VSB GND2
7 3 2 AME1117
3
5VCC GND1
6
VIN VOUT1
PAD1 AIC1117 TOP
3V3OUT EN2V5 VOUT2
4 5 + PJ1117 R22 330-0603 5% 3 4 SPEED
3V3AUX 2V5OUT C24 C26
GND
0.1u C25 0.1u

C27 C28 C29 C30
AAT1201 10uF/16V LM1117
0.1u 0.1u 0.1u 0.1u LD1117 R23 330-0603 5% 1 2 LINK
1
RC1117
LED1
Optional Optional
For WOL function For no WOL function
D3V3 D3V3 DECOUPLING D3V3 A3V3 A3V3 DECOUPLING

D3V3
Optional FOR VT6103 L1
FOR VT6103
To use MAC Phyreset signal
Optional
Mount R25
FB-0805 100MHz@100ohm C35 C36 C37 C38
5VSB C32 C33 C34
R24
J1 .1U .1U .1U .1U .1U .1U .1U
10K-0603 5% R25
1 0-0603
2 -PHYRST2 -PHYRST1
WOL 3
WOL
PIN.3 C31
For WOL function 1u
L2 L3
FB-1206 100MHz@52ohm FB-1206 100MHz@52ohm
Remove when not using WOL function
To use External reset signal
Mount R24 and C31
Figure 5. Application Schematic Example Page 2

Technologies, Inc.
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
Parameter Min Max Unit Comment

Storage Temperature -55 125 oC TS
Operating Temperature – Case 0 100 oC TC
Electrostatic Discharge - 3 KV Human Body Model
Power Supply Voltages (All) -0.5 4.0 Volts VDD, VCC, VCCOSC, VCCPLL, VCCRX, VCCTX
Input voltage -0.5 VDD+0.5 Volts
Output Voltage At Any Output -0.5 VDD–0.5 Volts
Note: Stress above the conditions listed may cause permanent damage to the device. Functional operation of this
device should be restricted to the conditions described under operating conditions.
DC Characteristics
TC -0-100oC, VDD =3.3V ±0.3V, GND = 0V
Symbol Parameter Min Max Unit Comment

VIL Input Low Voltage -0.5 0.9 V
VIH Input High Voltage 2.4 VDD+0.5 V
VOL Output Low Voltage - 0.1 VDD V LED0-3
VOH Output High Voltage 0.9 VDD - V LED0-3
IIL Input Leakage Current - ±50 uA
IOZ Tristate Leakage Current - ±50 uA
CIN Input Capacitance - 7.5 pF Fc=1MHz, TXD, TXEN, TXER
COUT Output Capacitance - 7.5 pF Fc=1MHz, RXD, RXDV, RXER, RXCK, TXCK
IDD Power Supply Current - 130 mA 10Base-T
IDD Power Supply Current - 80 mA 100Base-Tx
TPU Power-Up Reset Time 2 - ms
TSETUP Setup Time 6 ns 50% to 50%, 10pF load
THOLD Hold Time 0 ns 50% to 50%, 10pF load
TDELAY Delay Time 6 ns 50% to 50%, 10pF load
AC Characteristics
AC timing specifications provided assume an REXT of 6.19K ±1%, clock rate of 25MHz ±0.005%, power supply voltage of 3.3
to 3.6V, and case temperature between 0 and 100 oC.
Revision 1.1 April 15, 2002 -31- Electrical Specifications

Technologies, Inc.
100BaseT Transmitter Characteristics
Symbol Parameter Min Typ Max Unit Comment

Output Differential Amplitude 2 Vpp UTP (100 ohm)
Output Differential Amplitude 2 Vpp STP (100 ohm)
Output Differential Amplitude 2.45 Vpp STP (150 ohm)
Output Symmetry 0.98 1.02 V/V Differential Pos/Neg
TR / TF Output Rise / Fall 3 4 5 ns
Output Rise / Fall Skew 0.5 ns
Output Overshoot 5 %
Output Timing Jitter (Peak to Peak) 0.4 1.4 ns Scrambled
Return Loss 16 dB 2 ~ 30 MHz
Return Loss 16 dB 30 ~ 60 MHz
Return Loss 20log(f/30M)10 dB 60 ~ 80 MHz
DCD Duty Cycle Distortion - –0.25 0.25 ns
Transmitter On-Chip Power Consumption 45 mA 100 ohm
10BaseT Transmitter Characteristics

Output Differential Amplitude 4.4 5 5.6 Vpp UTP (100 ohm)
THD Total Harmonic Distortion 5 % All 1 and all 0
Idle Pulse Width 250 ns
Link Pulse Width 100 ns
Output Jitter without Cable ±8 ns
Output Jitter with Cable ±3.5 ns

Technologies, Inc.
Crystal Oscillator Characteristics

Output Frequency 24.9975 25 25.0025 MHz
Output Frequency Jitter - Short Term 50 ps
Output Frequency Jitter - Long Term 500 ps
PLL Frequency Multiplier Characteristics

PLL Loop Bandwidth 2.5 5 MHz
PLL Acquisition Time 50 us 25% Frequency Change
VCO Operating Frequency – 100Base Mode 250 MHz
VCO Operating Frequency – 10Base Mode 200 MHz
PLL Output Clock Jitter – Short Term 200 ps
PLL Output Clock Jitter – Long Term 1000 ps
FX Characteristics

VOH PECL Output Voltage High 2.28 2.35 2.42 Volts
VOL PECL Output Voltage Low 1.49 1.58 1.68 Volts
VIH PECL Input Voltage High 2.135 2.42 Volts
VIL PECL Input Voltage Low 1.49 1.825 Volts
FX Mode Enable Voltage (SD) 1.49 1.825 Volts
Input Common Mode Range 1.3 2.8 Volts
Input Differential Amplitude 0.15 Volts
Output Jitter 1.4 ns

Technologies, Inc.
Table 7. MI Interface MDIO Output Timing

T4 / TMC MDCK Frequency 10 MHz
T2 / TMIOS MDIO Input Setup Time 10 ns To MDCK rising edge
T3 / TMIOH MDIO Input Hold Time 10 ns To MDCK rising edge
T1 / TMOD MDIO Output Delay 0 300 ns To MDCK rising edge
MDC
T4 T1
MDIO
(OUTPUT)
MDC
T2 T3
MDIO
Valid Data
(INPUT)
Figure 6. MI Interface MDIO Timing
Table 8. MI Interface MDIO Interrupt Pulse Timing

T1 MDCK to MDIO Interrupt Pulse Asertion Delay 10 ns
T2 MDCK to MDIO Interrupt Pulse Deassertion Delay 10 ns
Interrupt
Event
MDC
T1 T2
MDIO
(OUTPUT)
Figure 7. MI Interface MDIO Interrupt Pulse Timing

Technologies, Inc.
Table 9. LED On / Off Timing

T1 LED[3:0] On Time 68 ms
T2 LED[3:0] Off Time 68 ms
T1 T2
LED[3:0]
Figure 8. LED On / Off Timing
Table 10. MII Transmit Data Timing

T1 TXD[3:0], TXEN, TXER Setup to TXC 10 ns
T2 TXD[3:0], TXEN, TXER Hold from TXC 0 ns
TX_CLK
T1 T2
TXD[3:0]
TX_EN Valid Data
TX_ER(INPUT)
Figure 9. MII Transmit Data Timing
Table 11. MII Receive Data Timing

T1 RXD[3:0], RXDV, RXER to RXC Output Delay 25 ns
T2 RXC Clock Period 40 ns
T2
RX_CLK
T1
RXD[3:0]
RX_DV Valid Data
RX_ER(OUTPUT)
Figure 10. MII Receive Data Timing

Technologies, Inc.
Table 12. MII Heartbeat Timing

T1 COL Heartbeat Delay 900 ns
T2 COL Heartbeat Duration 1000 ns
TX_EN
TX_CLK
T1 T2
COL
Figure 11. MII Heartbeat Timing
Table 13. MII Jabber Timing

T1 Jabber Activation Time 20 150 ms
T2 Jabber Deactivation Time 490 ms
TX_EN
T1 T2
TXD[3:0]
COL
Figure 12. MII Jabber Timing

Technologies, Inc.
Table 14. MII 10Base-T Normal Link Pulse Timing

T1 Clock, Data Pulse Width 100 ns
T2 Link Pulse to Link Pulse Period 8 ms
T2
T1
NLP
Figure 13. MII Normal Link Pulse Timing
Table 15. MII Auto-Negotiation Fast Link Pulse Timing

T1 Clock, Data Pulse Width 100 ns
T2 Clock Pulse to Clock Pulse Period 125 us
T3 Clock Pulse to Data Pulse Period 62.5 us
T4 Burst Width 2 ms
T5 FLP Burst to FLP Burst Period 8 ms
T2
T3
T1 T1
Fast Link
Pulse(s)
clock data clock data
pulse pulse pulse pulse
T5
T4
FLP FLP
Burst Burst
Figure 14. MII Auto-Negotiation Fast Link Pulse Timing

Technologies, Inc.
Table 16. 100Mb/s Receive Packet Timing

T1 Carrier Sense On Delay 100 ns
T2 Receive Data Latency 160 ns
RD+/- IDLE (J/K) Data
T1
CRS
T2
RXD[3:0]
RX_DV
RX_ER/RXD[4]
Figure 15. 100Mb/s Receive Packet Timing
Table 17. 100Mb/s Transmit Packet Timing

T1 TXC to TX+/– Latency 120 ns
T2 TXC to TX+/– Deassertion 120 ns
TX_CLK
T2
TX_EN
T1
TD+/- IDLE (J/K) DATA TR IDLE
Figure 16. 100Mb/s Transmit Packet Timing

Technologies, Inc.
Table 18. 10Mb/s Receive Packet Timing

T1 Carrier Sense On Delay 550 ns
T2 Receive Data Valid Delay 2200 ns
T3 Receive Data Latency 750 ns
RD+/- IDLE Preamble Data
T1
CRS
T2
RX_DV
T3
RXD[3:0]
RX_ER/RXD[4]
Figure 17. 10Mb/s Receive Packet Timing
Table 19. 10Mb/s Transmit Packet Timing

T1 TXC to TX+/– Latency 470 ns
T2 TXC to TX+/– Deassertion 700 ns
TX_CLK
T2
TX_EN
T1
TD+/- IDLE Preamble DATA SOP IDLE
Figure 18. 10Mb/s Transmit Packet Timing

Technologies, Inc.
PACKAGE MECHANICAL SPECIFICATIONS
Product Part Number
VT6103 Date Code, Chip Revision,

YYWWRR TAIWAN and Country of Assembly
LLLLLLLLL C M
Lot Code
SEATING PLANE
See Detail F
CONTROLLING DIMENSION : INCH

Millimeter Inch
Symbol Min Nom Max Min Nom Max
A 2.41 2.59 2.79 0.095 0.102 0.110
A1 0.20 0.30 0.40 0.008 0.012 0.016
A2 2.26 2.39 2.52 0.089 0.094 0.099
b 0.20 0.25 0.34 0.008 0.010 0.0135
c 0.13 0.20 0.25 0.005 0.008 0.010
D 15.75 15.88 16.00 0.620 0.625 0.630 GAUGE PLANE
E1 7.39 7.49 7.59 0.291 0.295 0.299
e 0.64 BASIC 0.025 BASIC
E 10.03 10.31 10.67 0.395 0.406 0.420
L 0.51 0.76 1.02 0.020 0.030 0.040
L1 1.42 0.056
0- 0° 8° 0° 8° Detail F
Figure 19. Mechanical Specifications – 48 Pin SSOP Package
Revision 1.1 April 15, 2002 -40- Package Mechanical Specifications

Datasheet de Via VT6103

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Fast Ethernet

VIA TECHNOLOGIES, INC.

is a registered trademark of VIA Technologies, Incorporated.

Revision 1.1 April 15, 2002 -i- Revision History

Revision 1.1 April 15, 2002 -ii- Table of Contents

Clock Recovery – 100 Mbps ................................................................................................................................................ 22

Revision 1.1 April 15, 2002 -iii- Table of Contents

Revision 1.1 April 15, 2002 -iv- Table of Contents

• Single Chip 100Base-TX / 10Base-T Physical Layer Solution

• Dual Speed – 100 / 10 Mbps

• Half and Full Duplex

• MII Interface to Ethernet Controller

• MII Interface to Configuration & Status

• Optional Repeater Interface

• Auto Negotiation: 10 / 100, Full / Half Duplex

• Meet All Applicable IEEE 802.3, 10Base-T and 100Base-Tx Standards

• On Chip Wave Shaping – No External Filters Required

• Baseline Wander Correction

• 48 Pin SSOP Package

Revision 1.1 April 15, 2002 -1- Product Features

Figure 1. Typical System Block Diagram

Revision 1.1 April 15, 2002 -2- Overview

Figure 2. Pin Diagram

Revision 1.1, April 15, 2002 -3- Pinouts

Management Interface (MI)

Media Independent Interface (MII)

Physical Cable Connection

Revision 1.1, April 15, 2002 -4- Pin Descriptions

Revision 1.1, April 15, 2002 -5- Pin Descriptions

Resets, Clocks, Control and Status

Power and Ground

Revision 1.1, April 15, 2002 -6- Pin Descriptions

Table 3. Register Summary

Revision 1.1 April 15, 2002 -7- Register Descriptions

Table 4. Register Bit Summary – Registers Defined by 802.3u

Table 5. Register Bit Summary - Vendor Defined Registers

Revision 1.1 April 15, 2002 -8- Register Descriptions

Offset 0 (00h) – MI Control (3100h)................................RW Offset 1 (01h) – MI Status (7849h)................................... RO

Revision 1.1 April 15, 2002 -9- Register Descriptions

Offset 6 (06h) – Auto-Negotiation Expansion (0004h)....RO

Revision 1.1 April 15, 2002 -10- Register Descriptions

Revision 1.1 April 15, 2002 -11- Register Descriptions

Revision 1.1 April 15, 2002 -12- Register Descriptions

Revision 1.1 April 15, 2002 -13- Register Descriptions

Revision 1.1 April 15, 2002 -14- Register Descriptions

Offset 31 (1Fh) – PHY Test Configuration 6 (0000h) ... RW

Revision 1.1 April 15, 2002 -15- Register Descriptions

Revision 1.1 April 15, 2002 -16- Functional Description

5B/4B ByPass 4B/5B 4B/5B

S100 ENMACH S100

NLP Rx LinkStatus Mux (Select DrvCmd

MLT3 to NRZI FXTX 10TX

10RX FXRX 100TX

Figure 3. Internal Block Diagram

Revision 1.1 April 15, 2002 -17- Functional Description

Revision 1.1 April 15, 2002 -18- Functional Description

Nibble-Wide MII Data Interface Carrier Sense

Revision 1.1 April 15, 2002 -19- Functional Description

Revision 1.1 April 15, 2002 -20- Functional Description

4B5B Encoder – 100 Mbps 4B5B Encoder – 100 Mbps

Revision 1.1 April 15, 2002 -21- Functional Description

Clock and Data Recovery Scrambler / Descrambler

Clock Recovery – 100 Mbps 100 Mbps Scrambler

Data Recovery – 10 Mbps