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Innovation in power conversion
Data Book and Design Guide

2007
Enabling cost-effective, and energy efficient

power supplies
General Information & Table of Contents
Product Selector Guide 1
Data Sheets 2
Application Notes 3
Reference Designs and Design Tools 4
Quality and Reliability 5
Package & Assembly Information 6

Introduction to the Data Book and Design Guide
Dear Designer:
With over 2 billion of our monolithic integrated circuits designed into switching power supplies worldwide,
Power Integrations is the clear leader in high-voltage ICs for power conversion. For nearly two decades, we
have focused on meeting the needs of power supply designers with innovative products and comprehensive
design support. If a product requires an AC-DC power supply up to 250 W or a 24/48 V DC-DC converter
up to 100 W, Power Integrationsʼ ICs can provide a cost-effective, energy-efficient solution with a rapid time
to market.
The drive to reduce energy waste in electronic equipment continues to gain momentum as governments around
the world adopt stricter energy-efficiency standards. Meeting these efficiency standards is now a critical design
consideration for all power supply engineers. With our award-winning EcoSmart® technology, we were the
worldʼs first semiconductor company to address the issue of standby and no-load energy waste. Today, our
products enable designs that easily meet all current and proposed energy-efficiency requirements without
adding cost or complexity. Weʼre also proud to report that this year, our EcoSmart technology has been honored
with prestigious energy-efficiency awards from both ENERGY STAR and the Alliance to Save Energy.
This 2007 Data Book and Design Guide provides all the resources you need to optimize your designs for cost,
simplicity, performance, and energy efficiency. This edition features four new product families, including the
®
revolutionary PeakSwitch®, delivering peak power without a cost penalty, and LinkSwitch-LP, enabling the
industryʼs simplest, most cost-effective designs to replace linear-transformer-based chargers and adapters. The
Product Selector Guide section provides a quick overview of our product families, including detailed examples
of system-level cost savings compared to discrete designs. The expanded Application Notes section offers
numerous examples of tested power supply circuits using our ICs. To complete your power supply design in
the shortest possible time, please take advantage of the Reference Designs and Design Tools section, which
contains details on our Reference Design Kits and our PI Expert™ design software.
Thanks for your interest in our power conversion ICs. To make sure that youʼre always using our latest
design-support materials, please visit our website at www.powerint.com. Extensive information on global
energy-efficiency standards and EcoSmart solutions can be found in the Power Integrations Green Room at
www.powerint.com/greenroom. As always, we welcome your suggestions to further improve our technical
support materials and to better serve your needs.
Balu Balakrishnan
President and CEO
December 2006
San Jose, California
i
GENERAL INFORMATION
Stresses listed under the Absolute Maximum Ratings section of each Power Integrations' product data sheet may be applied to the
product, one at a time, for a reasonable period of time, without causing permanent damage to the product. Exposing a product to
an Absolute Maximum Rating condition for an extended period of time may affect the productʼs reliability.
Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power
Integrations does not assume any liability arising from the use of any device or circuit described herein.
POWER INTEGRATIONS MAKES NO WARRANTY HEREIN AND SPECIFICALLY DISCLAIMS ALL WARRANTIES
INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS.
For the latest data book updates, visit our website: www.powerint.com
PATENT INFORMATION
The products and applications illustrated herein (including transformer construction and circuits external to the products) may be
covered by one or more U.S. and foreign patents, or potentially by pending U.S. and foreign patent applications assigned to Power
Integrations. A complete list of Power Integrationsʼ patents may be found at www.powerint.com. Power Integrations grants its
customers a license under certain patent rights as set forth at http://www.powerint.com/ip.htm.
LIFE SUPPORT POLICY
POWER INTEGRATIONSʼ PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE
SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF POWER
INTEGRATIONS. As used herein:
1. A life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life,
and (iii) whose failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to
result in significant injury or death to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected
to cause the failure of the life support device or system, or to affect its safety or effectiveness.
The PI logo, TOPSwitch, TinySwitch, LinkSwitch, DPA-Switch, PeakSwitch, EcoSmart, Clampless,

E-Shield, Filterfuse, PI Expert and PI FACTS are trademarks of Power Integrations, Inc. Other trademarks are property
of their respective companies.
Printed in the U.S.A. ©Copyright 2007, Power Integrations, Inc.
ii
DATA CLASSIFICATION
Product Concept: This notation on a data sheet indicates that the device is at a definition or planning stage. These devices may or
may not be introduced and the datasheet may be subject to drastic changes. The disclaimer at the bottom of the first page reads:
“This document contains proprietary information on a product concept under consideration. Power Integrations reserves the right
to change any specification and/or functionality on this product. This datasheet does not constitute an offer by Power Integrations
to produce this device.”
Preliminary: This notation on a data sheet indicates that the device is either in design, sampling, pre-production, or first production
stage. This device has not been fully characterized. The disclaimer at the bottom of the first page reads:
“This document contains information on a new product. Specifications and information herein are subject to change without
notice.”
Fully Released: A fully released data sheet contains neither a notation nor a disclaimer at the bottom of the first page. This document
contains information on a product in production. Power Integrations reserves the right to make changes to any products herein to
improve performance, reliability or manufacturability.
iii
Part Numbering Convention
(See data sheet for ordering information)
XXX###Y Z-TL
NOTES: ACTUAL MARKING WILL BE ABBREVIATED
TO ACCOMODATE AVAILABLE MARKING SPACE. NOT
ALL OPTIONS ARE AVAILABLE. PLEASE
CONSULT DATA SHEET FOR SPECIFIC OPTIONS.
PRODUCT FAMILY = ALPHA CHARACTERS
DPA DPA-Switch®
LNK LinkSwitch®
PKS PeakSwitch®
TNY TinySwitch®
TOP TOPSwitch®
SERIES NUMBER = NUMERICAL CHARACTERS
PACKAGE IDENTIFIER
F Plastic TO-262 package

G Plastic surface mount DIP package
P Plastic DIP
R Plastic TO-263 (D2PAK)
S Plastic MO-169 (S-PAK)
Y Plastic TO-220 package
LEAD FINISH
Blank Standard (SnPb)

N Pure Matte Tin (Pb-Free)
TAPE & REEL PACKAGING and OTHER OPTIONS
TL Tape & Reel packaging option
iv
TABLE OF CONTENTS
PRODUCT SELECTOR GUIDE .............................................................................................................................1-0
DATA SHEETS .......................................................................................................................................................2-0
DC-DC CONVERSION ICs
DPA-Switch Family............................................................................................................................2-1
DPA423
DPA424
DPA425
DPA426
AC-DC CONVERSION ICs
LinkSwitch-TN Family .....................................................................................................................2-33
LNK302
LNK304
LNK305
LNK306
LinkSwitch-XT Family .....................................................................................................................2-47
LNK362
LNK363
LNK364
LinkSwitch Family ...........................................................................................................................2-60
LNK500
LNK501
LNK520
LinkSwitch-LP Family ...................................................................................................................2-110
LNK562
LNK563
LNK564
PeakSwitch Family ........................................................................................................................2-123
PKS603
PKS604
PKS605
PKS606
v
TinySwitch-III Family.....................................................................................................................2-142
TNY274
TNY275
TNY276
TNY277
TNY278
TNY279
TNY280
TOPSwitch-GX Family ..................................................................................................................2-163
TOP242
TOP243
TOP244
TOP245
TOP246
TOP247
TOP248
TOP249
TOP250
APPLICATION NOTES ..........................................................................................................................................3-0
AN-15 TOPSwitch Power Supply Design Techniques for EMI and Safety .........................3-1
AN-18 TOPSwitch Flyback Transformer Construction Guide ...........................................3-34
AN-29 TOPSwitch-GX Flyback Quick Selection Curves ..................................................3-66
AN-30 TOPSwitch-GX Forward Design Methodology ......................................................3-74
AN-31 DPA-Switch Forward Converter Design Guide ....................................................3-100
AN-32 TOPSwitch-GX Flyback Design Methodology ..................................................... 3-118
AN-35 LinkSwitch Design Guide.....................................................................................3-133
AN-37 LinkSwitch-TN Design Guide...............................................................................3-152
AN-39 LinkSwitch-LP Flyback Design Guide..................................................................3-167
AN-40 LinkSwitch-XT Design Guide ...............................................................................3-183
AN-41 PeakSwitch Design Guide ...................................................................................3-196
DESIGN IDEAS
DI-12 Lead Acid Battery Charger (TOP244P, 13.55 V @ 16 W, Universal) ..................3-212

DI-16 Set-top Box (TOP246Y, Multiple Outputs @ 43 W (Cont), 57 W (Peak),
180-265 VAC) ......................................................................................................3-214
DI-17 PC Standby (TOP242Y, 3.3 V / 5 V @ 17 W, 200-375 VDC) ..............................3-216
DI-18 Charger or Adapter (LNK501, 5.5 V @ 2.75 W, Universal) .................................3-218
DI-19 Charger or Adapter (LNK501, 5.5 V @ 1.5 W, Universal) ...................................3-220
DI-21 LCD Monitor Adapter (TOP247Y, 12 V @ 45 W, Universal) ................................3-222
DI-22 External Laptop Adapter (TOP249Y, 19 V @ 70 W, Universal) ...........................3-224
DI-24 DC-DC Converter (DPA424R, 5 V @ 30 W, 36-75 VDC) ....................................3-226
DI-25 DC-DC Converter w/Sync Rectification (DPA425R, 5 V @ 30 W, 36-75 VDC) ...3-228
DI-26 DVB-T Supply (TOP242P, Multiple Outputs @ 7 W, 195-265 VAC) ....................3-230
DI-29 Flyback DC-DC Converter (DPA425R, 7 V @ 25 W, 36-75 VDC).......................3-232
DI-30 PC Main SFX Supply (TOP249Y, Multiple Outputs @ 180 W, 90-130 VAC
and 180-265 VAC) ...............................................................................................3-234
DI-31 DC-DC Converter w/Sync Rectification (DPA426R, 5 V @ 70 W, 36-75 VDC) ...3-236
vi
DI-35 Audio Amplifier Power Supply (TOP245P, 16 V @ 16 W, 35 W (Peak),
Universal ) ...........................................................................................................3-238
DI-37 DC-DC Converter (DPA424R, 3.3 V @ 16.5 W, 36-75 VDC) ..............................3-240
DI-39 DVD Supply: 70 mW No-load (TOP244P, Multiple Outputs @ 13 W,
17 W (Peak), Universal) ......................................................................................3-242
DI-40 DC-DC Converter w/Sync Rectification (DPA424R, 2.5 V @ 20 W, 36-75 VDC) 3-244
DI-41 Set-top Box (TOP247Y, Multiple Outputs @ 43 W (Cont), 57 W (Peak),
90-132 VAC) ........................................................................................................3-246
DI-43 Adapter: <250 mW No-Load (TOP244Y, 12 V @ 30 W, Universal) .....................3-248
DI-51 Flyback DC-DC Converter (DPA423R, 5 V @ 5 W, 36-75 VDC).........................3-250
DI-52 DC-DC Converter w/Sync Rectification (DPA426R, 12 V @ 60 W, 36-75 VDC) .3-252
DI-53 DC-DC Converter w/Sync Rectification (DPA425R, 5 V / 3.3 V @ 50 W,
36-75 VDC)..........................................................................................................3-254
DI-55 DVD Supply (TOP245P, Multiple Outputs @ 20 W, 25 W (Peak), Universal) .....3-256
DI-56 Flyback DC-DC Converter (DPA425R, ±12 V @ 19.2 W, 36-75 VDC)................3-258
DI-57 Flyback DC-DC Converter (DPA426R, 12 V @ 60 W, 36-75 VDC).....................3-260
DI-58 Low Cost CV/CC Charger or Adapter (LNK500, 5.5 V @ 1.5 W, Universal) .......3-262
DI-60 Low Cost Regulated Charger/Adapter (LNK501, 5.5 V @ 2.5 W, Universal) ......3-264
DI-67 Isolated, Power Factor Corrected (PFC), LED Driver (TOP246F, 16-24 V @
17.6 W max, 108-132 VAC) .................................................................................3-266
DI-69 VoIP Phone DC-DC Converter w/Sync Rectification (DPA424P, 5 V / 7.5 V /
20 V @ 15 W, 36-75 VDC) ..................................................................................3-268
DI-70 Power over Ethernet Interface Circuit and DC-DC Converter (DPA424P, 5 V /
7.5 V / 20 V @ 15 W, 28-57 VDC) .......................................................................3-270
DI-74 Non-Isolated Constant Current LED Driver (LNK304P, 12 V @ 1.25 W,
Universal) ............................................................................................................3-272
DI-75 Low Cost Regulated Charger/Adapter (LNK520, 5.0 V @ 2.5 W, Universal) ......2-274
DI-76 Low Parts Count Power Supply (LNK520P, 12 V @ 3.1 W, 100-375 VDC) ........3-276
DI-80 Non-Isolated Utility Meter Power Supply (LNK302, 12 V @
0.6 W, Universal) .................................................................................................3-278
DI-85 Charger (LNK564P, 6 V @ 2 W, 90-265 VAC).....................................................3-280
DI-88 PoE Interface Circuit (DPA423G, 3.3 V @ 6.49 W, 36-57 VDC) .........................3-282
DI-89 CV Power Adapter (LNK362P, 6.2 V @ 2 W, Universal) .....................................3-284
DI-91 CV Adapter (TNY278P, 12 V @ 12 W, Universal) ...............................................3-286
DI-92 LED Driver (LNK302P, 40 mA @ 0.5 W, Universal).............................................3-288
DI-93 General Purpose (PKS606Y, 30 V @ 32 W / 81 W Peak, 90-265 VAC) .............3-290
DI-116 Multiple Output Supply (TNY280P, Multiple Outputs @ 25 W / 28 W Peak,
90-265 VAC) .......................................................................................................3-292
DI-117 Adapter (TNY279P, 12 V @ 15 W, 90-265 VAC) .................................................3-294
DI-118 CV/CC Charger (TNY276P, 5.7 V @ 4.56 W, 90-265 VAC) ................................3-296
DI-119 Linear Adapter Replacement (LNK562P, 7.7 V @ 1.6 W, 85-265 VAC;
10 kV Surge Withstand).......................................................................................3-298
DI-123 Multiple Output Supply (TNY275P, 12/5 V @ 9.65 W, 185-265 VAC) .................3-300
DI-124 Ultra-wide Range Supply (LNK304, 12 V / 250 mA, 57-580 VAC) ......................3-302
DI-128 Variable-speed DC Motor Drive (PKS606Y, 12 V @ 35 W / 75 W Peak
90-265 VAC) ........................................................................................................3-304
DI-129 PVR Power Supply (PKS606P, 3.3 V / 5 V / 17.5 V / 22 V @ 33 W /
60 W Peak, 195-265 VAC) ..................................................................................3-306
DI-130 Passive PFC LED Lighting Supply (TNY279P, 10 V @ 18 W,
185-265 VAC) ......................................................................................................3-308
vii
REFERENCE DESIGNS AND DESIGN TOOLS ...................................................................................................4.0
DESIGN SOFTWARE
PI Expert Suite .............................................................................................................................4-1

PI Expert ......................................................................................................................................4-2
PI Xls Design Spreadsheet ..........................................................................................................4-3
PI Transformer Designer ..............................................................................................................4-4
REFERENCE DESIGNS
DAK-16A 2.75 W, 5.5 V AC-DC Power Supply........................................................................4-5
DAK-18 10 W, Multi-Output AC-DC Power Supply ...............................................................4-5
DAK-21A 30 W, 5 V DC-DC Power Supply .............................................................................4-6
DAK-32 20 W, Multi-Output AC-DC Power Supply ...............................................................4-6
DAK-33 45 W, 12 V AC-DC LCD Monitor External Power Supply ........................................4-6
DAK-34 30 W, 12 V AC-DC Power Supply............................................................................4-6
DAK-48A 1.44 W, 12 V Non-Isolated Appliance Power Supply ...............................................4-7
DAK-54 2.75 W, 5.5 V Cost Effective Linear Transformer Replacement ..............................4-7
DAK-68A 6.6 W, 3.3 V PoE DC-DC Converter ........................................................................4-7
DAK-71A 6.6 W, 3.3 V DC-DC Converter................................................................................4-7
RDK-83 1.6 W, 7.7 V Cordless Phone Linear Adapter Replacement ....................................4-8
DAK-85 2 W, 6 V Lowest Cost Charger – Linear Transformer Replacement .......................4-8
DAK-86 6.6 W, 3.3 V PoE PD Power Device ........................................................................4-8
DAK-89 2 W, 6.2 V CV Adapter.............................................................................................4-9
DAK-91 12 W, 12 V Universal Input Supply ..........................................................................4-9
DAK-93 32 W / 81 W Peak, 30 V Universal Input Supply .....................................................4-9
QUALITY AND RELIABILITY ................................................................................................................................5-0
Quality and Reliability Overview ..................................................................................................5-1
PACKAGE & ASSEMBLY INFORMATION............................................................................................................6-0
TO-220-7C ...................................................................................................................................6-1
TO-263-7C ...................................................................................................................................6-2
S-PAK MO-169-7C ......................................................................................................................6-3
TO-262-7C ...................................................................................................................................6-4
DIP-8............................................................................................................................................6-5
DIP-8B .........................................................................................................................................6-5
DIP-8C .........................................................................................................................................6-6
SMD-8..........................................................................................................................................6-7
SMD-8B .......................................................................................................................................6-7
SMD-8C .......................................................................................................................................6-8
Tape & Reel .................................................................................................................................6-9
Pb-Free and RoHS Compliant Products .................................................................................... 6-11
Solder Temperature Profiles ......................................................................................................6-12
PC Board Cleaning ....................................................................................................................6-13
Mounting Guidelines for TO-220 Package .................................................................................6-14
viii
Data Sheets 2
Application Notes 3

TABLE OF CONTENTS
AC-DC Product Selector Guide ............................................................1-1
DC-DC Product Selector Guide ......................................................... 1-11

AC-DC SELECTOR GUIDE
AC-DC Product Selector Guide
Non-Isolated ®
Buck/Buck-Boost LinkSwitch-TN
Converters
®
TOPSwitch-GX
Isolated Flyback
Main, Bias or TinySwitch-III
®
Standby Supply
LinkSwitch-LP, LinkSwitch, LinkSwitch-XT
PeakSwitch ™ up to 300%
(continuous) Peak Power
85-265 VAC 0W 20 W 40 W 200 W

230 VAC 0W 30 W 60 W 275 W
Output Characteristic Low Power Products

Requirements
1
Linear
Transformer/ LNK562 563 564 KEY
Loose CV/CC
LinkSwitch-LP
LinkSwitch
Loose LNK500/501/520
CV/CC LinkSwitch-XT
TinySwitch-III
Tight CV, LNK500/501/520

Loose CC OPTO
Tight 274
CV/CC LNK362 TNY
363 276 277 278 279 280
OPTO 364 275
Loose LNK362 363 364 TNY 276 277 278 279 280
CV 275
Tight 274 TNY

CV LNK362 363 276 277 278 279 280
OPTO 364 275
Enclosed 0W 1W 1.5 W 2W 2.5 W 3W 3.7 W 5W 6W 6.5 W 8W 10 W 12 W 14 W

Open Frame 0W 1W 1.5 W 2W 2.5 W 4.5 W 4.7 W 8.5 W 11.5 W 15 W 18.5 W 21.5 W 25 W 28.5 W
1-1
04/06

I. VERY LOW POWER AC-DC, NON-ISOLATED LINEAR/PASSIVE SUPPLY REPLACEMENT (≤360 mA)
Output Output
No-load Power Consumption

Max. Duty Cycle % (DCMAX)
Current9 Current9
Simultaneous Line Sensing

Switching Frequency (kHz)
EcoSmart® Low Standby/

Adjustable Current Limit
(Y-Yes; N.R.-Not Required)
Thermal Shutdown
Line UV Detection
Line OV Detection
and Current Limit

Remote ON/OFF
Frequency Jitter
Control Method
Power Limiting
HV-FET Rating
Self-Powered4
Product1,5
Auto Restart
MDCM7
MDCM7
Soft-Start
CCM8
LinkSwitch-TN 230 VAC ± 15% 85-265 VAC

CCM8
LNK302 P or G 63 mA 80 mA 63 mA 80 mA 700 V 66 ON/OFF Y N.R. Hys. Y Y Y Y 69
LNK304 P or G 120 mA 170 mA 120 mA 170 mA 700 V 66 ON/OFF Y N.R. Y Hys. Y Y Y Y 69
II. VERY LOW POWER AC-DC POWER CONVERSION (UP TO 9 W)

Continuous Continuous

Max. Duty Cycle % (DCMAX)
Output Power Output Power

Switching Frequency (kHz)
EcoSmart Low Standby/

Adjustable Current Limit
Thermal Shutdown
Line UV Detection
Line OV Detection
Open Frame3
Open Frame3
and Current Limit

Remote ON/OFF
Frequency Jitter
Control Method
Power Limiting
HV-FET Rating
Self-Powered4
Product1,5
Auto Restart
Adapter2
Adapter2
®
Soft-Start
1 LinkSwitch-LP 230 VAC ± 15% 85-265 VAC

LNK562 P or G 1.9 W 1.9 W 1.9 W 1.9 W 700 V 66 ON/OFF Y N.R. Y Hys. Y Y Y Y 66
LNK564 P or G 3W 3W 3W 3W 700 V 100 ON/OFF Y N.R. Y Hys. Y Y Y Y 66
LinkSwitch 230 VAC ± 15% 85-265 VAC
LNK500 P or G6 4W 3W 700 V 42 PWM Y Y Hys. Y Y 77
LinkSwitch-XT 230 VAC ± 15% 85-265 VAC
LNK363 P or G 5W 7.5 W 3.7 W 4.7 W 700 V 132 ON/OFF Y N.R. Y Hys. Y Y Y Y 60
LNK364 P or G 5.5 W 9W 4W 6W 700 V 132 ON/OFF Y N.R. Y Hys. Y Y Y Y 60
III. LOW POWER AC-DC POWER CONVERSION (UP TO 36.5 W)


EcoSmart® Low Standby /
Thermal Shutdown
Line UV Detection
Line OV Detection
Open Frame3
Open Frame3
and Current Limit

Cycle % (DCMAX)
Frequency (kHz)
Remote ON/OFF
Frequency Jitter
Control Method
Power Limiting
HV-FET Rating
Self-Powered4
Product1,5
Current Limit
Auto Restart
Adapter2
Adapter2
Adjustable
Max. Duty
Switching
Soft-Start
TinySwitch-III 230 VAC ± 15% 85-265 VAC

TNY274 P or G 6W 11 W 5W 8.5 W 700 V 132 ON/OFF Y N.R. Y Y Hys. Y Y Y Y Y 65
TNY275 P or G 8.5 W 15 W 6W 11.5 W 700 V 132 ON/OFF Y N.R. Y Y Hys. Y Y Y Y Y 65
TNY276 P or G 10 W 19 W 6.5 W 15 W 700 V 132 ON/OFF Y N.R. Y Y Hys. Y Y Y Y Y 65
TNY277 P or G 13 W 23.5 W 8W 18.5 W 700 V 132 ON/OFF Y N.R. Y Y Hys. Y Y Y Y Y 65
TNY278 P or G 16 W 28 W 10 W 21.5 W 700 V 132 ON/OFF Y N.R. Y Y Hys. Y Y Y Y Y 65
TNY279 P or G 18 W 32 W 12 W 25 W 700 V 132 ON/OFF Y N.R. Y Y Hys. Y Y Y Y Y 65
TNY280 P or G 20 W 36.5 W 14 W 28.5 W 700 V 132 ON/OFF Y N.R. Y Y Hys. Y Y Y Y Y 65
1-2
04/06

IV. SUPER PEAK AC-DC POWER CONVERSION (UP TO 68 W CONTINUOUS, 117 W PEAK)
Latching Shutdown and Reset

Adaptive On-Time Extension

Adaptive Current Limit
Smart AC Sense With

Peak Power Delivery

Adapter Peak10
Adapter Peak10
Thermal Shutdown
Line UV Detection
Cycle % (DCMAX)
Frequency (kHz)
Frequency Jitter
Control Method
Power Limiting
HV-FET Rating
Self-Powered4
Product1,5
Auto Restart
Adapter2
Adapter2
Max. Duty
Switching
Soft-Start
PeakSwitch 230 VAC ± 15% 85-265 VAC
PKS603 P 13 W 32 W 9W 25 W 700 277 ON/OFF NR Y Hys. Y Y Y Y 65 Y Y Y Y
PKS604 P 23 W 56 W 16 W 44 W 700 277 ON/OFF NR Y Hys. Y Y Y Y 65 Y Y Y Y
PKS604 Y or F 35 W 56 W 23 W 44 W 700 277 ON/OFF NR Y Hys. Y Y Y Y 65 Y Y Y Y
V. HIGH POWER AC-DC POWER CONVERSION (UP TO 290 W)


SimultaneousLine Sensing
Thermal Shutdown
Line UV Detection
Line OV Detection
Open Frame3
Open Frame3
and Current Limit

Cycle % (DCMAX)
Frequency (kHz)
Remote ON/OFF
Frequency Jitter
Control Method
Power Limiting
1
HV-FET Rating
Self-Powered4
Product1,5
Current Limit
Auto Restart
Adapter2
Adapter2
Adjustable
Max. Duty
Switching
Soft-Start
TOPSwitch-GX 230 VAC ± 15% 85-265 VAC

TOP242 P or G 9W 15 W 6.5 W 10 W 700 V 132 PWM Y Y Y Hys. Y Y Y Y Y Y 78
TOP242 R 21 W 22 W 11 W 14 W 700 V 132/66 PWM Y Y Y Hys. Y Y Y Y Y Y 78 Y
TOP242 Y or F 10 W 22 W 7W 14 W 700 V 132/66 PWM Y Y Y Hys. Y Y Y Y Y Y 78 Y
TOP243 P or G 13 W 25 W 9W 15 W 700 V 132 PWM Y Y Y Hys. Y Y Y Y Y Y 78
TOP243 Y or F 20 W 45 W 15 W 30 W 700 V 132/66 PWM Y Y Y Hys. Y Y Y Y Y Y 78 Y
TOP244 P or G 16 W 28 W 11 W 20 W 700 V 132 PWM Y Y Y Hys. Y Y Y Y Y Y 78
Notes:
1. Packages: P–Plastic DIP, G–Surface Mount DIP, Y–TO-220, R–TO-263, F–TO-262. Consult data sheet for product ordering information. 2. Minimum continuous power in a typical non-ventilated encased adapter
with minimal heat sinking, measured at a device ambient of 50 ºC. 3. Minimum continuous power in an open frame with adequate heat sinking. 4. No bias winding needed for LNK500, LNK501 and LNK362-364. 5.
Shipping quantities per package: Tubes: F and Y- 50 pc., P and G - 50 pc. Tape and reel: G-TL- 1000 pc., R-TL- 750 pc. R-package is available in tape and reel only. 6. Typical power ratings shown for CV/CC charger
applications. LNK501 provides tighter output CC tolerances. LNK520 is optimized for EMI reduction. See data sheets for full specifications. 7. Mostly discontinuous conduction mode. 8. Continuous conduction
mode. 9. Typical output current in a non-isolated buck converter. 10. Typical peak power for a period of 100 ms and a duty cycle of 10% in a non-ventilated enclosed adapter measured at +50 °C (see data
sheet for details).
1-3
04/06
AC-DC Product Features and Benefits

Comprehensive Fault Protection – Simplifies Design & Improves Reliability
- On-chip hysteretic thermal shutdown provides auto-recovery
- Protects entire system: device, PC board, magnetics and output rectifiers
- Control loop fault protection is independent of bias voltage
Ave. Ouput
PI-3225-082202
Shutdown ~140 ºC Power
100%
140
Temperature ºC
Directly detects
loss of feedback
signal – independent
of bias voltage
60 75 ºC Hysteresis 5%
Fault applied Fault removed t
Fault Applied
- open loop
0 20 40 60 80 100 - short circuit
- overload PI-3946-101404
Time (mins)
Hysteretic Thermal Shutdown Output Power During Loss of Feedback
Tight Device Tolerances – Reduces System Cost

- PI ICs exhibit an Internal Current Limit (ILIMIT) tolerance of only ±7% and a Switching Frequency (fOSC) tolerance of
only ±6% or a combined I2f tolerance of only ±11%
- Reduces necessary power rating in a reliable design for the output rectifier, transformer and clamp circuit
PI-4290-020306
1
System with Competitor Device C ILIMIT: ±20%, fOSC: ±10%
System with Competitor Device B ILIMIT: ±12%, fOSC: ±10%
System with Competitor Device A ILIMIT: ±10%, fOSC: ±10%

Requires over-rated
power components
System with PI Device (no I f parameter)
2 ILIMIT: ±7%, fOSC: ±6% for reliable design.
System with PI Device (with I2f parameter) I2f: ±11%
0% 50% 100% 150% 200% 250%

Variation in Flyback Converter Output Power Capability Over Device
Tolerance Range (Normalized to Rated Output Power)
Frequency Jittering Reduces EMI & EMI Filtering Costs

- Enables smaller, lower cost filter components
80 80
PI-3947-101804
PI-3948-101804
70 70
60 60
EN55022B Limits EN55022B Limits
Amplitude (dBµV)
Amplitude (dBµV)
50 50
40 40
QP
30 30
QP
20 20
AV
-10 -10 AV
0 0
-10 -10
-20 -20
0.15 1 10 30 0.15 1 10 30
Frequency (MHz) Frequency (MHz)
Conducted EMI without Jitter Conducted EMI with Jitter
1-4
04/06
AC-DC Product Features and Benefits

Source Heatsinking for Low Radiated EMI
- Heatsink connected to SOURCE for low radiated EMI
Typical Power Device Power Integrations Device

EMI
DRAIN SOURCE
DIP-8 DIP-8
PCB Copper Area PCB Copper Area
DRAIN SOURCE
H Connection H Connection
E E
A A
T
TO-220
T
TO-220
1
S S
I I
N N
PC Board K PC Board K
“Hot” Switching Node Electrically Quiet Node

PI-3945-102904
Package Design/Pin Layout – Improves Reliability

- Wide package DRAIN – SOURCE creepage reduces probability of arcing
- Important for forced air cooled (high pollutant) environments
- Optimal pin arrangement allows compliance with safety agency adjacent pin short-circuit test
Y-package P-package
PI-3147-081602
PI-3149-072406
3.4 mm
1.73 mm
2.87 mm 3.5 mm
1-5
04/06
Enabling Energy Efficiency

EcoSmart Technology –
Power Integrations EcoSmart® IC technology enables power supply designers to meet the requirements of all
existing and proposed energy efficiency standards worldwide.
• Extremely Low No-load Consumption
- Solutions under 300 mW and as low as 50 mW
• High Standby Efficiency
- Less than 1 W input power with greater than 0.67 W output
Sample Reference Designs With Standby and No-load Energy Consumption

POUT at 1 W PIN at MEETS MEETS EU
REFERENCE OUTPUT MEETS
APPLICATION INPUT (W) NO-LOAD (W) 1 WATT NO-LOAD
DESIGN CEC**
STANDBY SPEC*
W VDC 115 V 230 V 115 V 230 V
AC Adapter/Charger EP-14 3W 9V 0.70 0.58 0.09 0.20 ✓ ✓ ✓
AC Adapter/Charger EP-16 2.75 W 5.5 V 0.68 0.64 0.23 0.27 ✓ ✓ ✓
AC-DC Power Supply EP-34 30 W 12 V 0.67 0.59 0.18 0.29 ✓ ✓ ✓
Appliance/White Goods EP-48 1.44 W 12 V 0.75 0.70 0.105 0.15 ✓ N/A N/A
1
DVD Player EP-29 11 W 3.3 V, 5 V, ±12 V 0.73 0.69 0.02 0.028 ✓ N/A ✓
DVD Player EP-32 25 W 3.3 V, 5 V, 12 V, 24 V 0.66 0.63 0.065 0.078 ✓ N/A ✓
Inkjet Printer EP-93 32 W 30 V 0.72 0.69 0.1 0.16 ✓ ✓ ✓
LCD Monitor/TV Adapter EP-33 45 W 12 V 0.67 0.56 0.17 0.23 ✓ ✓ ✓
Set-top Box EP-13 43 W 3.3 V, 5 V, 12 V, 18 V, 30 V --- 0.13 --- 0.70 ✓ N/A ✓
*Code of Conduct on Efficiency of External Power Supplies **California Energy Commission N/A = Not Applicable
For an extensive list of tested, energy-efficient reference designs and circuit examples, see the EcoSmart-Enabled
Energy-Efficient Solutions Brochure (www.powerint.com/PDFFiles/ecosmarteffbro.pdf) and visit our Design
Examples Web page (www.powerint.com/appcircuits.htm).
The Green Room –

For the latest in energy efficiency guidelines
and design solutions, visit the Power Integrations
Green Room at www.powerint.com/greenroom
• Energy Efficiency Regulations Database

- Searchable by product, geographic region
or regulation name
• Application Specific Design Tools
- Data Sheets
- Application Notes
- Reference Designs
www.powerint.com/greenroom
1-6
04/06
Cost Savings
all
LinkSwitch-LP – Replacement for Unregulated Linear Transformer
2 W, UNIVERSAL INPUT POWER SUPPLY
Built-in Frequency Jitter Simplifies Optimized ILIMIT and
Input Stage tight tolerances enable Optimized switching
ßSimple inductor and capacitor Clampless™ design – frequency enables low Tight parametric tolerances and auto-restart
EMI filter Up to $0.04 savings cost core size minimize diode size – Up to $0.02 savings
ßAllows inductor to be used as
a fuse (Filterfuse™) C5
D1 RF1* L1 T1 D4 220 µF R3 6 V,
L 1N4937 8.2 Ω 3300 µH EE16 7 UF4002 25 V 2 kΩ 0.33 A
2
Primary Sensed Feedback
2.5 W
C1 ßEliminates optocoupler
90-265 10 µF
VAC 400 V
1 6 ßSimplifies PCB layout
4 RTN
N
D2
1N4005 5
R1
Small value Y capacitor for
LinkSwitch-LP
U1
37.4 kΩ low line leakage current enabled
Auto-restart protects supply D3 C4*
D LNK564P 1N4005 C3 100 pF by E-Shield™ and frequency jitter
in overload conditions and FB
330 nF 250 VAC
allows simple low power Zener BP 50 V
C2 R2
for open loop protection S 3 kΩ
0.1 µF *Optional components
50 V
Combined ON/OFF and variable PI-4284-012706
frequency control provides CV/CC
output characteristic without Design Flexibility
secondary sensing ßFamily members have same ILIMIT but different switching frequencies
-Allows simple replacement of LinkSwitch-LP device to give different output powers –
no other changes required
-Reduces time-to-market and development cost
1
*Co
LinkSwitch-XT – Low Cost Switcher with Accurate Output

Low ILIMIT allows Clampless™ Small value Y capacitor for
Built-in frequency jitter designs using LNK362 – low line leakage current enabled
C4*
allows simple EMI filter – Up to $0.03 savings 100 pF by E-Shield™ and frequency jitter
Up to $0.03 savings 250 VAC
ed
C5
L1 T1 330 µF 6.2 V,
1 mH EE16 9 16 V 322 mA
4
5
D5
1N4934
3 8
NC NC RTN
RF1 D1 D2 R1 VR1
8.2 k 1N4005 1N4005 3.9 k BZX79-
2.5 W 1/8 W B5V1
5.1 V, 2%
Tight parametric tolerances and
R3
auto-restart minimize diode size – 390 Ω
85-265 C1 C2 1/8 W ON/OFF control eliminates
3.3 µF 3.3 µF Up to $0.02 savings
VAC
400 V 400 V compensation components
R2 and allows accurate
U2
1k output with low cost
1/8 W
D
FB
PC817A Zener reference –
LinkSwitch-XT
Up to $0.07 savings
U1 BP
LNK362P with 4 fewer components
D3 D4 S
C3
1N4005 1N4005 L2 100 nF
1 mH 50 V
PI-4287-03316
*Optional component Self-powered from drain,
Typically 2% to 5% higher
no bias winding needed –
efficiency than RCC
Up to $0.02 savings
1-7
04/06
Cost Savings
LinkSwitch – Low Cost Switcher for Loose CV/CC Output
2.75 W, UNIVERSAL INPUT POWER SUPPLY
LinkSwitch
Transformer – 2 Windings
ßPrimary CV/CC control
ß700 V MOSFET ßNo bias winding required CV/CC Output With No Voltage/
ßEcoSmart (300 mW no-load consumption) ßLow cost Current Sense Components
EMI Filter – 3 Components ßSimple design
ßLow cost ßILIMIT and thermal protection ßLow cost
ßLow component count ßHigh efficiency
ßEliminates up to 10 components
5.5 V,
500 mA
RTN
85-265
VAC
Combines:
ßClamp circuit
ßIC supply
1 PI-3488-020206
ßFeedback
ßEliminates up to 10 components
Total component cost <$0.65 at >1 million units per month (excluding cable, connectors and enclosure).
LinkSwitch-TN – Low Cost Switcher for Appliance Control

1.44 W, UNIVERSAL INPUT NON-ISOLATED POWER SUPPLY
LinkSwitch-TN
ß700 V MOSFET for extended line transient withstand
ßAuto-restart for open loop protection Low Cost Direct Sense Feedback
ßThermal overload protection ß±10% typical output tolerance
ßEcoSmart (100 mW no-load consumption) ßNo optocoupler required
Frequency Jitter Simplifies ßSelf-powered
EMI Filter Design
ßThree parts for low cost
12 V,
120 mA
85-265
VAC
RTN
PI-3757-020206
Low Cost Standard

Twice the Output
Off-the-Shelf Inductor
Current of Equivalent
Cost Capacitive Dropper
Total component cost <$0.50 at >100,000 units per month.
1-8
04/06
Cost Savings
TinySwitch-III vs. Discrete Design*
Single resistor UV lockout 132 kHz operation
prevents output glitches allows 3 W with EE13 Tight parametric tolerances and auto-restart
C5
minimize diode size – Up to $0.02 savings
Typically 2% to 5% during power up/down
2.2 nF
for reduced product size 250 VAC
higher efficiency D7
L2
VR1 Ferrite Bead
than RCC P6KE150A T1 BYV28-200 3.5 × 7.6 mm +12 V, 1 A
On-time extension NC 8
increases hold-up C10 C11

100 µF
D1 D2 R2 1000 µF
time 1N4007 1N4007 100 Ω 1 6 25 V 25 V
F1
3.15 A C4 RTN
C1 C2 R1
6.8 µF 22 µF 1 kΩ 10 nF
1 kV 3 R7
400 V 400 V
85-265 RV1 4 20 Ω
VAC 275 VAC
D5
1N4007GP 2 D6
R5* UF4003 ON/OFF control eliminates
3.6 MΩ
D3 D4 5 compensation components
1N4007 1N4007
L1 VR2
C6 VR3
and allows accurate
1 mH 1N5255B
28 V 1 µF
60 V
BZX79-C11 output with low cost
11 V
Built-in frequency jitter Zener reference –
R3
allows simple EMI filter – 47 Ω Up to $0.07 savings
1/8 W
Up to $0.03 savings
R6 with 4 fewer components
390 Ω
R8* 1/8 W
Optional TinySwitch-III
21 kΩ
1%
U2 Simple latching output OV shut-
*R5 and R8 are optional TinySwitch-III D PC817A
components bias resistor reduces EN/UV down removes or reduces rated
U1
no-load consumption TNY278P S
BP/M power of secondary components –
below 50 mW S R4 Up to $0.02 savings
C7 On-time extension 2 kΩ
100 nF 1/8 W
Tight I f parameter
2 50 V maximizes hold-up
maximizes power delivery and time
minimizes overload power – PI-4286-020306
Up to $0.03 savings Self-powered from drain, Single capacitor selects Modulated feedback threshold prevents
no bias winding needed – ILIMIT, provides design group pulsing, reduces output ripple
Up to $0.02 savings flexibility
*Cost savings based on high-volume quantities (>1 M/yr.). Higher savings possible at lower volumes. 1
TOPSwitch-GX vs. Discrete Design*
High (132 kHz) frequency and soft-start can reduce
Soft-start, tight parametric transformer core size – Up to $0.20 savings
tolerances and power limiting Primary power limiting (R1 and R2) and very
(R1 and R2) optimizes RCD tight parametric tolerances reduce diode
clamp design – Up to $0.05 savings current rating – Up to $0.05 savings
Frequency jittering simplifies
EMI filter design reducing
development time and component
cost – Up to $0.20 savings in
components plus
reduced development
costs Combined power and
feedback insensitive to
bias voltage variation –
no linear regulator
required – Up to $0.03
savings
Overvoltage
shutdown
protection (R4)
can eliminate
input surge
protection PI-3486-020206
circuitry
(MOVs etc) – High max duty cycle (78%) ILIMIT control (R2) allows more Soft-start reduces output voltage overshoot
Up to $0.10 allows smaller input cap – continuous operation for higher at turn on – eliminates soft finish capacitor
savings Up to $0.25 savings efficiency – Up to $0.10 savings in most applications – Up to $0.10 savings
*Cost savings based on high-volume quantities (>1 M/yr.). Higher savings possible at lower volumes.
1-9
04/06
Cost Savings
PeakSwitch vs. Discrete Design
Simple, time delayed
277 kHz operation during peak C10 R8 output overload detection
1 nF 68 Ω C11
load allows small EE-25 core 250 VAC 1/2 W 330 pF
(activating latching shutdown)
size – Up to $0.06 savings C13 R9 C14 30 V @
D9 47 µF 0.33 Ω L2 220 nF 1.07 A Cont.
Frequency jittering simplifies EMI 16 V 2W 2.7 A Peak
1N4148 5.3 µH 50 V
filter design, reducing development time
and component cost – Up to $0.10 savings C17 C5 VR1 9,10 D8
4.7 nF 2.2 nF 1N4764A Q1 Accurate latching OVP
in components plus earlier 1 kV 1 kV 100 V
STPS3150 C12 2N3906
330 µF without 2nd redundant
time to market R10
C4
1 50 V VR2 1.5 kΩ optocoupler – Up to
D1-D4 R11
150 µF
1N5255B
3 kΩ
$0.05 savings
1N4007 7,8 28 V
400 V
R3
10 kΩ RTN
R15 1/2 W 3
2.2 Ω
4
D10
R4 UF4003
C15
22 Ω C6 R12
2 100 nF
1/2 W 47 µF 1 kΩ
L1 50 V VR3
5.3 mH 35 V R7
1N5258B
D6 4.7 kΩ
Q2 36 V
FR106 5
R2 R1 FS202DA
1.3 MΩ 1.3 MΩ D7
T1
D5 R5 R6 EE25 1N4148
1N4007 2.2 MΩ 2.4 MΩ
C3 R16
680 nF t
O
2.7 MΩ C16
X1 RT1 100 nF
PeakSwitch
10 Ω D
U1 EN/UV
PKS606Y R14
BP 100 Ω
C7
C1-C2 C8 U2 R13
F1 100 nF
100 pF S GND 220 nF PC817X4 1 kΩ
3.15 A 400 V
250 VAC 50 V
1
J1
L J3
RTN Connected to PE via Flying Lead C19
1 nF, 250 VAC PCB Term 18 AWG
PE
PI-4170-060706
N
Smart AC line sensing provides latching PeakSwitch
100% tested, accurate thermal shutdown ßON/OFF control maintains constant efficiency over entire load range
shutdown during output overload or open
with automatic recovery provides complete (i.e. from standby and sleep mode to full load)
loop fault. Prevents power on/off glitches
system level overload protection and ßTight I2f parameter optimizies overall tolerances
during brownout and fast latch reset when
eliminates need for manual reset – ßAdaptive ILIMIT reduces high-line overload power
AC is removed with only 2 extra components –
Up to $0.05 savings ßAdaptive on-time extension increases low-line peak output power
Up to $0.12 savings
1-10
04/06
DC-DC SELECTOR GUIDE
DC-DC Selector Guide

DPA-Switch Device Selector Guide
P or G
DPA423
R or S
P or G
DPA424
R or S
P or G
DPA425
R or S
DPA426 R or S
0 5 15 20 30 50 70 90 100
24 V / 48 V DC-DC Power Conversion (Up to 100 W) 1

Output Power Table
36-75 VDC INPUT RANGE (FORWARD)4,5 36-75 VDC INPUT RANGE (FLYBACK)4,5
Total Device Max Total Device Max
Dissipation3 0.5 W 1W 2.5 W 4W 6W Power Dissipation3 0.5 W 0.75 W 1W 1.5 W Power
PRODUCT1,2 Output PRODUCT1,2 Output
DPA423 12 W 16 W - - - 18 W DPA423 9W 13 W - - 13 W
DPA424 16 W 23 W 35 W - - 35 W
DPA424 10 W 14.5 W 18 W 24 W 26 W
DPA425 23 W 32 W 50 W 62 W 70 W
DPA426 25 W 35 W 55 W 70 W 83 W 100 W DPA425 - - - 25.5 W 52 W
Integrated Features
HV-FET Rating 220 V Soft-Start Hysteretic Thermal Shutdown Remote ON/OFF
Fully Integrated Current EcoSmart® Low Standby/

Switching Frequency (kHz) 400/300 Power Limiting
Sensing No-load Power Consumption
Synchronizable to Lower
Max. Duty Cycle (DCMAX) 75% Adjustable Current Limit Line UV Detection
External Clock Frequency
Control Method PWM Auto Restart Line OV Detection
and Current Limit
Notes:
1. Packages: P–Plastic DIP, G–Surface Mount DIP, R–TO-263, S–MO-169. Pb-free package options are available for P, G, & S packages. Consult data sheet
for product ordering information. 2. Shipping quantities per package: Tubes: P and G - 50 pc. Tape and reel: G-TL- 1000 pc., R-TL- 750 pc., S-TL- 1000 pc.
R-package and S-PAK are available in tape and reel only. 3. For example, in a 55 W output design, the DPA426R will dissipate a worst case total of 2.5 W. 4.
See data sheet for power capability at 16 VDC and 24 VDC input. 5. Power based on diode rectification assuming worst case RDS(ON) @ TJ=100 ºC. Up to 5%
higher output power possible using synchronous rectification.
1-11
04/06
DC-DC Product Features and Benefits

DPA-Switch® cost effectively combines a high frequency power MOSFET, PWM control, fault protection and other control
circuitry onto a single CMOS chip. Features include short circuit and open loop protection, programmable current limit,
under-voltage and overvoltage detection, hysteretic thermal shutdown, soft-start, feedback compensation and remote
ON/OFF. DPA-Switch ICs can save over 20 external components when compared to conventional discrete designs, pro-
viding significant savings in both board space and cost.
Product • Wide input voltage range: 16 VDC to 75 VDC

• Supports flyback and forward topology
Highlights • Eliminates all external current sensing circuitry
• Auto-restart for output overload/open loop protection
• Voltage mode control allows 75% duty cycle without slope compensation while providing 5-10 kHz
loop bandwidth
• Line under-voltage (UV) detection: meets ETSI standards
• Line overvoltage (OV) shutdown protection
• Low-cost synchronous rectification: line UV/OV shutdown limits gate drive
voltage range when driven directly from the transformer winding
• Fully integrated soft-start for minimum stress/overshoot
• Externally programmable current limit for high-efficiency low-cost designs and power limiting
• Programmable maximum duty cycle varies with input voltage to guarantee core reset in forward
converter designs
®
EcoSmart • Extremely low consumption at no-load (10 mA typ.)
Energy and in remote off (2 mA max.)
• Cycle skipping at light load for high standby efficiency
Efficiency
1 Package • S, P and G packages are available in Pb-free finish (100% matte tin), are RoHS compliant and meet
Information the requirements of JEDEC standard (see J-STD-020C, Table 4.2).
G Package P Package
C 1 8 S C 1 8 S
L 2 7 S L 2 7 S
X 3 6 D X 3 6 D
F 4 5 S F 4 5 S
SMD-8 DIP-8
S Package R Package
1 2 3 4 5 7
MO-169-7C CLXSF D TO-263-7C
(S-PAK) (Not available in Pb-free) 123 4 5 7
CL X S F D
Typical • PoE Powered Devices: VoIP Phones, WLAN and WAP Transmitters, Security Cameras, Bar Code
Applications Scanners, Alarm Systems and Smoke Detectors
• Telco Central Office Equipment: xDSL, ISDN, PABX, etc.
• Distributed Power Architectures (24/48 V Bus, etc.)
• Industrial Control (24/48 V)
Visit our Web site www.powerint.com/dpaproduct.htm for more information.
1-12
04/06
What is Power over Ethernet?

Power over Ethernet (PoE) is a method whereby power is transmitted to Ethernet-connected equipment (VoIP telephones,
WLAN transmitters, security cameras) from the central switch. By using the existing CAT-5 cabling, the need for AC power (and
wiring costs) can be eliminated. The network switch is also able to control power distribution to the powered devices, allowing
sophisticated uninterruptible power management for vital systems.
Operation: Fundamentally, a PoE Powered Device (PD) must fulfill three functions in order to act in conjunction with the
sending end Power Sourcing Equipment (PSE). The functions are detection, classification and under-voltage lockout.
Detection Phase: When a PoE-enabled Ethernet cable is plugged into a PD, the PSE interrogates the device to determine
if it is PoE-enabled. This period is termed the detection phase. During the detection phase, the PSE applies a voltage ramp
to the PD and looks for a characteristic impedance from the load (25 k ). If the correct impedance is not detected, the PSE
assumes that the load is not PoE-enabled and shuts down the PoE sending end. The system then operates as a standard
Ethernet connection. If the signature impedance is detected, the PSE moves on to the classification phase. The signature
identification voltage is a ramp voltage between 2.5 V and 10 V. A 24.9 k resistor provides the correct signature impedance
for discovery (see Figure 1).
30 2.0
PI-4035-030506
PI-4036-062805
Detection
Voltage
Range
25 1.5
Input Current (mA)

Resistance (kΩ)
20 1.0
15 0.5
Classification
Voltage
Range
10 0
0 5 10 15 20
Input Voltage (V)
25 30 35 0 5 10 15 20 25
Input Voltage (V)
30 35
1
Figure 1. Detection Impedance. Figure 2. Classification Current (Class 0).
Classification Phase: The PSE continues to ramp the voltage to the PD. Between 14.5 V and 20.5 V, the classification phase
occurs. During this voltage transition, the PD must draw a specified current to identify the device class (see Figure 2). The
simplest class (Class 0) is also implemented by the use of the 24.9 k signature resistor. The classification current describes
the amount of power the PD will require during normal operation. It is this information that is fed to the controller by the PSE,
which allows the system to determine power budget requirements. A table of classification current and operating PD power
requirements is shown in Table 1.
Power Power ICLASS ICLASS

Class
(MIN) (MAX) (MIN) (MAX)
0 0.44 W 12.95 W 0 mA 4 mA R51 R52
24.9 kΩ/1% 51 kΩ
1 0.44 W 3.84 W 9 mA 12 mA 1/4 W 1/8 W
2 3.84 W 6.49 W 17 mA 20 mA
3 6.49 W 12.95 W 26 mA 30 mA
4 Reserved Reserved 36 mA 44 mA PI-3825-072205
Table 1. Classification Power Levels. Figure 3. PoE Class 0 Interface Circuit Using
a MOSFET Pass-Switch.
Turn-on Phase: After the classification phase, the PSE continues to ramp the input voltage up to 30 V, when the under-voltage
lockout (UVLO) circuit is released and the PD is allowed to power up. Soft-start circuitry may be required to limit current drawn
from the PSE. A typical under-voltage lockout circuit is shown in Figure 3.
By this process, the PSE and PD work together to determine the nature of the load and apply power only to PoE enabled
equipment. The system controller at the central location can determine load requirements and allocate power according to an
operational needs hierarchy during power failure from its available UPS budget.
For additional information about driving PoE compatible load equipment and circuits for implementing Class 1 through Class 3
classification, see Design Ideas DI-70 (www.powerint.com/PDFFiles/di70.pdf) & DI-88 (www.powerint.com/PDFFiles/di88.pdf).
1-13
04/06
Cost Savings
DPA-Switch vs. Discrete Design*
34-57 VDC INPUT, 12.95 W MULTIPLE OUTPUT POWER OVER ETHERNET DC-DC CONVERTER
Integrated Current Sense and Current Limit
ßTight tolerance and temperature compensated Integrated Start-up
ßNo current sense resistor (higher efficiency) ßHigher efficiency
ßNo current sense transformer even for high-power designs (no “boot strap” losses)
ßProgrammable using X pin resistor ßSaves up to 4 components
ßSaves up to 6 components ßUp to $0.02 Savings
ßUp to $0.25 Savings Simple Synchronous Rectification
ßDPA-Switch line UV/OV shutdown
Simplified PoE Interface Circuit limits gate drive voltage range from
ßIncludes detection signature transformer winding
impedance (24.9 kΩ from 2.5 VDC Integrated Line Sense ßUp to $0.05 Savings
to 10 VDC) ßAccurate temperature stability
ßIncludes Class 0 classification ßProvide UV/OV protection
D41
(Class 1, 2 and 3 solutions also available) ßSaves up to 10 components BAV19WS 20 V, 10 mA
ßLow cost with bipolar pass switch ßUp to $0.20 Savings C41
4.7 µF, 35 V
(87% min. efficiency)
Ethernet VR41 D42
4 3 6.8 V IN4148
(RJ-45) D101 D31
Connector DL4002 L1
PoE Interface 1 µH 2.5 A 20CJQ060
1 8 7.5 V, 0.4 A
(1,2)
7 6 C31
Q22 100 µF
Si4804 10 V
3 7 C25
DL4002 VR51 L2 C22-C24 R4 1 µF
28 V 6 C21 16 µH 4 A
D102 2.2 nF 100 µF 5 V 160 Ω 10 V 5 V, 2.4 A
R1 R21 8 5
649 kΩ 10 Ω
1% 4 7 2
R52 R22
20 kΩ D6
D103 10 Ω BAV
1
5 19WS RTN
DL4002
T1 Q21 VR21 D21
(4,5) C1 C2 Si4804 SL13
1 µF 1 µF R23 15 V
R51 100 V 174 k R23 C6
100 V 4.7 µF U2
24.9 kΩ 1% 10 kΩ R16
DL4002 1% 1/4 W 20 V 10 kΩ
D104 1%
R21
10 k
Q20
MMBTS3906
R22
D105 10 kΩ U2
DL4002 PC357
(3,6) N1T R11
DPA-Switch 10 kΩ
C51 R12 C12
1 nF U1
D51 D L DPA424P 150 Ω 100 nF
DL4002 BAV19 50 V
D106 CONTROL
R13
C 11 Ω
D11
BAV19WS
D52
BAV19 S X F R3 C11 C13 R14
VR1 1.0 Ω
D107 SMAJ 2.2 µF 68 nF 1 kΩ
R53 C4 10 V
DL4002 R54 150 220 nF C5
20 kΩ 20 Ω U3
(7,8) R2 47 µF R15
10 V LM431AIM3 10 kΩ
13.3 kΩ
1% 1%
Q51
TIP29C (100 V/1 A) PI-3824-040706
DL4002
D108 or MMBTA06
Simple Multiple Output Design
ßLow cost secondary outputs
Source Connected Tab Integrated Voltage Mode Controller
ßNo secondary regulation required
ßHeat sink connected to source ß>50% duty cycle operation without
ßUp to $0.20 Savings
reduces EMI (electrically “quiet”) requiring slope compensation
ßReduces EMI filter costs Accurate Integrated Oscillator ßSaves up to 10 components Integrated Thermal Shutdown
ßUp to $0.20 Savings ßNo external components ßUp to $0.15 Savings ßDirectly senses power MOSFET temperature
ßTight tolerance and temperature stable ßHysteretic auto-restarting
ßSelectable 300/400 kHz operation ßWide hysteresis prevents highaverage temperatures
ßSaves up to 5 components ßSaves up to 4 components
ßUp to $0.05 Savings ßUp to $0.15 Savings
*Cost savings based on high-volume quantities (>50 k/mo.). Higher savings possible at lower volumes.
Visit our Web site www.powerint.com/dpaproduct.htm for more information.
1-14
04/06
Data Sheets 2
Application Notes 3

PRODUCT DATA SHEETS
Quick Reference Guide
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Battery Chargers
Cell phone adapter/charger � � � � �
Cordless phone charger � � � �
Cordless tool charger � � � � � �
Digital camera charger � � � � �
PDA adapter � � � � �
MP3 / MD players � � � �
Industrial Charger � � �
Communication
24/48 V DC-DC converter �
Broadband modem � � � �
Router � � �
Telecomm line card �
VoIP phone �
PoE powered device (PD) �
Computer
PC main power supply �
PC standby power supply � �
External media drive � � �
Laptop adapter �
LCD monitor / TV � �
LCD projector � �
Multimedia speaker amplifier � � �
Printer � �
Scanner � � � �
USB Hub � �
Wireless access point/router � � �
Consumer
Cable/satellite set-top box � � �
DVD player/recorder � � �
Television standby � � �
Video game �
Home Appliance
Major Appliance � � �
Small Appliance � � �
Home Comfort � � �
General Lighting � � � � � �
LED lighting � � � �
Industrial
Lighting � � � �
Programmable logic controller � � � �
Uninterruptible power supply � �
Utility meter � � � � � �
TABLE OF CONTENTS
DPA423-426 .........................................................................................2-1
LNK302/304-306 ................................................................................2-33
LNK362-364 .......................................................................................2-47
LNK500 ..............................................................................................2-60
LNK501 ..............................................................................................2-76
LNK520 ..............................................................................................2-92
LNK562-564 ..................................................................................... 2-110
PKS603-606 .....................................................................................2-123
TNY274-280 .....................................................................................2-142
TOP242-250 .....................................................................................2-163
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DPA423-426
DPA423-426
®
DPA-Switch Family
Highly Integrated DC-DC Converter ICs for
Power over Ethernet & Telecom DC-DC
Product Highlights
VO
Highly Integrated Solution
• Eliminates 20-50 external components–saves space, cost
SENSE
• Integrates 220 V high frequency MOSFET, PWM control CIRCUIT
• Lower cost plastic DIP surface mount (G package) and DPA-Switch

through-hole (P package) options for designs ≤35 W VIN L
D
• Thermally efficient MO-169-7C (S-PAK) and RESET/
CONTROL
C
TO-263-7C (R package) options for high power applications CLAMP
CIRCUIT
X F
Superior Performance and Flexibility S
• Eliminates all external current sensing circuitry

• Built-in auto-restart for output overload/open loop protection PI-2770-032002
• Pin selectable 300/400 kHz fixed frequency

Figure 1. Typical Forward Converter Application.
• Wide input (line) voltage range: 16-75 VDC
• Externally programmable current limit
• Source connected tab reduces EMI OUTPUT POWER TABLE
• Line undervoltage (UV) detection: meets ETSI standards 36-75 VDC INPUT RANGE (FORWARD)2
• Line overvoltage (OV) shutdown protection Total Device Max
• UV/OV limits gate drive voltage for synchronous rectification Dissipation3 0.5 W 1 W 2.5 W 4W 6W Power
• Fully integrated soft-start for minimum stress/overshoot PRODUCT4 Output1
• Supports forward or flyback topology
DPA423 12 W 16 W - - - 18 W
• Cycle skipping: regulation to zero load without preload
• Hysteretic thermal shutdown for automatic fault recovery DPA424 16 W 23 W 35 W - - 35 W 2
• RoHS compliant P, G and S package options DPA425 23 W 32 W 50 W 62 W 70 W
®
EcoSmart – Energy Efficient DPA426 25 W 35 W 55 W 70 W 83 W 100 W
5
• Extremely low consumption at no load 36-75 VDC INPUT RANGE (FLYBACK)2

• Cycle skipping at light load for high standby efficiency Total Device Max
Dissipation3 0.5 W 0.75 W 1W 1.5 W Power
Applications
PRODUCT4 Output1
• PoE applications, VoIP phones, WLAN, security cameras
• Telco central office equipment: xDSL, ISDN, PABX DPA423 9W 13 W - - 13 W
• Distributed power architectures (24 V/48 V bus) DPA424 10 W 14.5 W 18 W 24 W 26 W
• Industrial controls
DPA425 - 6
- 6
- 6
25.5 W 52 W
Description Table 1. Output Power Table.
The DPA-Switch IC family is a highly integrated solution for Notes:
1. Maximum output power is limited by device internal
DC-DC conversion applications for 16-75 VDC input. current limit.
2. See Applications Considerations section for complete description of
DPA-Switch uses the same proven topology as TOPSwitch®, assumptions and for output powers with other input voltage ranges.
3. For device dissipation of 1.5 W or below, use P or G packages.
cost effectively integrating a power MOSFET, PWM Device dissipation above 1.5 W is possible with S and R packages.
control, fault protection and other control circuitry onto 4. Packages: P: DIP-8, G: SMD-8, R: TO-263-7C, S: MO-169-7C. For lead-
a single CMOS chip. High-performance features are free package options, see Part Ordering Information.
5. Available in S and R package only.
enabled with three user-configurable pins. Hysteretic 6. Due to higher switching losses, the DPA425 may not deliver additional
thermal shutdown is also provided. In addition, all critical power compared to a smaller device.
parameters (i.e. current limit, frequency, PWM gain) have
tight temperature and absolute tolerance, to simplify design
and reduce system cost.
2-1
Rev. Q 05/06
DPA423-426
Section List
Functional Block Diagram .................................................................................................................................... 2-3

Pin Functional Description ................................................................................................................................... 2-3
DPA-Switch Family Functional Description ......................................................................................................... 2-4
CONTROL (C) Pin Operation ............................................................................................................................... 2-4
Oscillator and Switching Frequency .................................................................................................................... 2-5
Pulse Width Modulator & Maximum Duty Cycle .................................................................................................. 2-6
Minimum Duty Cycle and Cycle Skipping ........................................................................................................... 2-6
Error Amplifier ...................................................................................................................................................... 2-6
On-chip Current Limit with External Programmability .......................................................................................... 2-6
Line Undervoltage Detection (UV) ....................................................................................................................... 2-6
Line Overvoltage Shutdown (OV) ........................................................................................................................ 2-7
Line Feed-Forward with DCMAX Reduction ........................................................................................................... 2-7
Remote ON/OFF .................................................................................................................................................. 2-7
Synchronization ................................................................................................................................................... 2-8
Soft-Start .............................................................................................................................................................. 2-8
Shutdown/Auto-Restart ........................................................................................................................................ 2-8
Hysteretic Over-Temperature Protection .............................................................................................................. 2-8
Bandgap Reference ............................................................................................................................................ 2-8
High-Voltage Bias Current Source ....................................................................................................................... 2-8
Using Feature Pins .................................................................................................................................................. 2-9
FREQUENCY (F) Pin Operation ........................................................................................................................... 2-9
LINE-SENSE (L) Pin Operation ............................................................................................................................ 2-9
EXTERNAL CURRENT LIMIT (X) Pin Operation ................................................................................................... 2-9
Typical Uses of FREQUENCY (F) Pin ................................................................................................................... 2-12
Typical Uses of LINE-SENSE (L) and EXTERNAL CURRENT LIMIT (X) Pins ................................................... 2-12
2 Application Examples ........................................................................................................................................... 2-15
Key Application Considerations .......................................................................................................................... 2-18
DPA-Switch Design Considerations ................................................................................................................... 2-18
DPA-Switch Layout Considerations ................................................................................................................... 2-19
Quick Design Checklist ..................................................................................................................................... 2-20
Design Tools ...................................................................................................................................................... 2-20
Product Specifications and Test Conditions ...................................................................................................... 2-22
Typical Performance Characteristics ............................................................................................................... 2-28
Part Ordering Information .................................................................................................................................... 2-32
2-2
2-2
Rev. Q 05/06
DPA423-426
VC
0
CONTROL (C) DRAIN (D)
ZC INTERNAL
1 SUPPLY
SHUNT REGULATOR/
ERROR AMPLIFIER +
SOFT START
- 5.8 V
4.8 V -
+ 5.8 V
INTERNAL UV
IFB COMPARATOR
VI (LIMIT)
CURRENT
LIMIT SOFT
ADJUST START -
ON/OFF ÷8
+
VBG + VT SHUTDOWN/
AUTO-RESTART CURRENT LIMIT
COMPARATOR
EXTERNAL
CURRENT LIMIT (X) HYSTERETIC
STOP LOGIC THERMAL
SHUTDOWN
LINE-SENSE (L) 1V
CONTROLLED
VBG TURN-ON
STOP SOFT- GATE DRIVER
OV/UV START
LINE DMAX
SENSE DCMAX DCMAX
CLOCK
S Q
300/400 kHz SAW - LEADING
R EDGE
FREQUENCY (F) + BLANKING
OSCILLATOR
PWM
COMPARATOR
CYCLE
RE SKIPPING
SOURCE (S)
PI-2760-070501
Figure 2. Functional Block Diagram.
Pin Functional Description connected to SOURCE pin and 300 kHz if connected to
DRAIN (D) Pin:
High-voltage power MOSFET drain output. The internal
CONTROL pin. 2
startup bias current is drawn from this pin through a switched SOURCE (S) Pin:
high-voltage current source. Internal current limit sense point Output MOSFET source connection for the power return.
for drain current. Primary side control circuit common and reference point.
CONTROL (C) Pin:

Error amplifier and feedback current input pin for duty cycle
control. Internal shunt regulator connection to provide S-PAK Tab Internally Connected
internal bias current during normal operation. It is also used (MO-169-7C) to SOURCE Pin
as the connection point for the supply bypass and auto-restart/ (See layout considerations)
compensation capacitor.
LINE-SENSE (L) Pin: 1 2 3 4 5 7

Input pin for overvoltage (OV), undervoltage (UV) lock out, CL XSF D
P Package (DIP-8)
line feed-forward with the maximum duty cycle (DCMAX) G Package (SMD-8)
reduction, remote ON/OFF and synchronization. A connection R Package
to SOURCE pin disables all functions on this pin. (TO-263-7C) C 1 8 S
L 2 7 S
EXTERNAL CURRENT LIMIT (X) Pin:
Input pin for external current limit adjustment and remote X 3 6 D
ON/OFF. A connection to SOURCE pin disables all functions F 5
4 S
on this pin.
123 4 5 7
CL X S F D PI-4030-071305
FREQUENCY (F) Pin:
Input pin for selecting switching frequency: 400 kHz if Figure 3. Pin Configuration (Top View).
2-3
Rev. Q 05/06
DPA423-426
DPA-Switch Family Functional

Auto-restart
Description ICD1 IB
DPA-Switch is an integrated switched mode power supply chip
that converts a current at the control input to a duty cycle at the 75
Slope = PWM Gain
open drain output of a high-voltage power MOSFET. During
Duty Cycle (%)

normal operation the duty cycle of the power MOSFET decreases
linearly with increasing CONTROL pin current as shown in 42
Figure 4. A patented high-voltage CMOS technology allows IL < IL(DC)
I
both the high-voltage power MOSFET and all the low-voltage C (SKIP)
control circuitry to be cost effectively integrated onto a single

monolithic chip. 4
IL = 115 µA
In addition to the standard TOPSwitch features, such as the IC (mA)

high-voltage startup, the cycle-by-cycle current limiting, loop PI-2761-112102
compensation circuitry, auto-restart and thermal shutdown, Figure 4. Relationship of Duty Cycle to CONTROL Pin Current.
DPA-Switch also offers many advanced features that reduce
system cost and increase power supply performance and design
flexibility. Following is a summary of the advanced features: Three pins, LINE-SENSE (L), EXTERNAL CURRENT LIMIT
(X) and FREQUENCY (F), are used to implement all the pin
1. A fully integrated 5 ms soft-start limits peak currents and controllable features. A resistor from the LINE-SENSE pin to DC
voltages during startup and reduces or eliminates output input bus implements line UV, line OV and line feed-forward with
overshoot in most applications. DCMAX reduction. A resistor from the EXTERNAL CURRENT
2. A 75% maximum duty cycle (DCMAX) together with the LIMIT pin to the SOURCE pin sets current limit externally. In
line feed-forward with DCMAX reduction feature makes addition, remote ON/OFF may be implemented through either
DPA-Switch well suited for both flyback and forward the LINE-SENSE pin or the EXTERNAL CURRENT LIMIT
topologies. pin depending on the polarity of the logic signal available as
3. High switching frequency (400 kHz/300 kHz, pin selectable) well as other system specific considerations. Shorting both the
allows the use of smaller size transformers and offers high LINE-SENSE and the EXTERNAL CURRENT LIMIT pins to
2 bandwidth for power supply control loop.
4. Cycle skipping operation at light load minimizes standby
the SOURCE pin disables line OV, line UV, line feed-forward
with DCMAX reduction, external current limit, remote ON/OFF
power consumption (typically <10 mA input current). and synchronization. The FREQUENCY pin sets the switching
5. Line undervoltage ensures glitch free operations at both frequency to 400 kHz if connected to the SOURCE pin, or
power-up and power-down and is tightly toleranced over 300 kHz if connected to the CONTROL pin. This pin should
process and temperature to meet system level requirements not be left open. Please refer to “Using Feature Pins” section for
common in DC to DC converters (e.g. ETSI). detailed information regarding the proper use of those pins.
6. Line overvoltage protects DPA-Switch against excessive
input voltage and line surge. CONTROL (C) Pin Operation
7. External current limit adjustment allows the setting of the The CONTROL pin is a low impedance node that is capable
current limit externally to a lower level near the operating of receiving a combined supply and feedback current. During
peak current and, if desired, further adjusts the level normal operation, a shunt regulator is used to separate the
gradually as line voltage rises. This makes possible an ideal feedback signal from the supply current. CONTROL pin voltage
implementation of overload power limiting. VC is the supply voltage for the control circuitry including the
8. Synchronization function allows the synchronization of MOSFET gate driver. An external bypass capacitor closely
DPA-Switch operation to an external lower frequency. connected between the CONTROL and SOURCE pins is required
9. Remote ON/OFF feature permits DPA-Switch based power to supply the instantaneous gate drive current. The total amount
supplies to be easily switched on or off using logic signals. of capacitance connected to this pin also sets the auto-restart
Maximum input current consumption is 2 mA in remote timing as well as control loop compensation.
OFF.
10. Hysteretic over-temperature shutdown provides automatic When the DC input voltage is applied to the DRAIN pin during
recovery from thermal fault. startup, the MOSFET is initially off, and the CONTROL
11. Tight absolute tolerances and small temperature variations pin capacitor is charged through the switched high-voltage
on switching frequency, current limit, and undervoltage lock current source connected internally between the DRAIN and
out threshold (UV). CONTROL pins. When the CONTROL pin voltage VC reaches
2-4
2-4
Rev. Q 05/06
DPA423-426
approximately 5.8 V, the control circuitry is activated and the standby mode. The high-voltage current source turns on and
soft-start begins. The soft-start circuit gradually increases charges the external capacitance again. A hysteretic internal
the duty cycle of the MOSFET from zero to the maximum supply undervoltage comparator keeps VC within a window
value over approximately 5 ms. The high-voltage current of typically 4.8 V to 5.8 V by turning the high-voltage current
source is turned off at the end of the soft-start. If no external source on and off as shown in Figure 5. The auto-restart circuit
feedback/supply current is fed into the CONTROL pin by the has a divide-by-8 counter that prevents the output MOSFET
end of the soft-start, the CONTROL pin will start discharging from turning on again until eight discharge/charge cycles have
in response to the supply current drawn by the control circuitry elapsed. This is accomplished by enabling the output MOSFET
and the gate current of the switching MOSFET driver. If the only when the divide-by-8 counter reaches full count (S7).
power supply is designed properly, and no fault condition such The counter effectively limits DPA-Switch power dissipation
as open loop or overloaded output exists, the feedback loop as well as the maximum power delivered to the power supply
will close, providing external CONTROL pin current, before output by reducing the auto-restart duty cycle to typically 4%.
the CONTROL pin voltage has had a chance to discharge to Auto-restart mode continues until output voltage regulation is
the lower threshold voltage of approximately 4.8 V (internal again achieved through closure of the feedback loop.
supply undervoltage lockout threshold). When the externally
fed current charges the CONTROL pin to the shunt regulator Oscillator and Switching Frequency
voltage of 5.8 V, current in excess of the consumption of the The internal oscillator linearly charges and discharges an internal
chip is shunted to SOURCE through resistor RE as shown in capacitance between two voltage levels to create a sawtooth
Figure 2. This current flowing through RE controls the duty cycle waveform for the pulse width modulator. The oscillator sets
of the power MOSFET to provide closed loop regulation. The both the pulse width modulator latch and the current limit latch
shunt regulator has a finite low output impedance ZC that sets at the beginning of each cycle.
the gain of the error amplifier when used in a primary feedback
configuration. The dynamic impedance ZC of the CONTROL The nominal switching frequency of 400 kHz was chosen to
pin together with the external CONTROL pin capacitance sets minimize the transformer size and to allow faster power supply
the dominant pole for the control loop. loop response. The FREQUENCY pin, when shorted to the
CONTROL pin, lowers the switching frequency to 300 kHz,
When a fault condition such as an open loop or overloaded output which may be preferable in some applications such as those
prevents the flow of an external current into the CONTROL employing secondary synchronous rectification. Otherwise, the
pin, the capacitor on the CONTROL pin discharges towards FREQUENCY pin should be connected to the SOURCE pin
4.8 V. At 4.8 V auto-restart is activated which turns the output for the default 400 kHz.
MOSFET off and puts the control circuitry in a low current 2
~
~
~
~
VUV
~
~
VLINE
0V
S7 S0 S1 S2 S6 S7 S0 S1 S2 S6 S7 S0 S1 S2 S6 S7 S7 5.8 V
~
~
~
~
~
~
VC 4.8 V
0V
~
~
~
~
VDRAIN
~
~
0V
VOUT
0V
~
~
~
~
~
~
1 2 3 2 4
Note: S0 through S7 are the output states of the auto-restart counter PI-3867-050602
Figure 5. Typical Waveforms for (1) Power Up (2) Normal Operation (3) Auto-restart (4) Power Down.
2-5
Rev. Q 05/06
DPA423-426
Pulse Width Modulator and Maximum Duty Cycle The CONTROL pin current in excess of the supply current
The pulse width modulator implements voltage mode control is separated by the shunt regulator and flows through RE as a
by driving the output MOSFET with a duty cycle inversely voltage error signal.
proportional to the current into the CONTROL pin that
is in excess of the internal supply current of the chip (see On-chip Current Limit with External Programmability
Figure 4). The excess current is the feedback error signal that The cycle-by-cycle peak drain current limit circuit uses the
appears across RE (see Figure 2). This signal is filtered by an RC output MOSFET ON-resistance as a sense resistor. A current
network with a typical corner frequency of 30 kHz to reduce the limit comparator compares the output MOSFET on-state
effect of switching noise in the chip supply current generated by drain to source voltage, VDS(ON) with a threshold voltage. At
the MOSFET gate driver. The filtered error signal is compared the current limit, VDS(ON) exceeds the threshold voltage and the
with the internal oscillator sawtooth waveform to generate the MOSFET is turned off until the start of the next clock cycle.
duty cycle waveform. As the control current increases, the duty The current limit comparator threshold voltage is temperature
cycle decreases. A clock signal from the oscillator sets a latch compensated to minimize the variation of the current limit due
that turns on the output MOSFET. The pulse width modulator to temperature related changes in RDS(ON) of the output MOSFET.
resets the latch, turning off the output MOSFET. Note that a The default current limit of DPA-Switch is preset internally.
minimum current must be driven into the CONTROL pin before However, with a resistor connected between EXTERNAL
the duty cycle begins to change. CURRENT LIMIT pin and SOURCE pin, the current limit can
be programmed externally to a lower level between 25% and
The maximum duty cycle, DCMAX is set at a default maximum 100% of the default current limit. Please refer to the graphs
value of 75% (typical). However, by connecting the in the Typical Performance Characteristics section for the
LINE-SENSE to the DC input bus through a resistor selection of the resistor value. By setting current limit low,
with appropriate value, the maximum duty cycle can be a larger DPA-Switch than necessary for the power required
made to decrease from 75% to 33% (typical) as shown in can be used to take advantage of the lower RDS(ON) for higher
Figure 7 when input line voltage increases (see Line Feed- efficiency/smaller heat sinking requirements. With a second
Forward with DCMAX Reduction). resistor connected between the EXTERNAL CURRENT
LIMIT pin and the DC input bus, the current limit is reduced
Minimum Duty Cycle and Cycle Skipping with increasing line voltage, allowing a true power limiting
To maintain power supply output regulation, the pulse width operation against line variation to be implemented in a flyback
modulator reduces duty cycle as the load at the power supply configuration.
output decreases. This reduction in duty cycle is proportional to
2 the current flowing into the CONTROL pin. As the CONTROL The leading edge blanking circuit inhibits the current limit
pin current increases, the duty cycle reduces linearly towards a comparator for a short time after the output MOSFET is turned
minimum value specified as minimum duty cycle, DCMIN. After on. The leading edge blanking time has been set so that, if a
reaching DCMIN, if CONTROL pin current is increased further power supply is designed properly, current spikes caused by
by approximately 2 mA, the pulse width modulator will force primary-side capacitance and secondary-side rectifier reverse
the duty cycle from DCMIN to zero in a discrete step (refer to recovery time should not cause premature termination of the
Figure 4). This feature allows a power supply to operate in a switching pulse.
cycle skipping mode when the load consumes less power than
the DPA-Switch delivers at minimum duty cycle, DCMIN. No The current limit after the leading edge blanking time is as shown
additional control is needed for the transition between normal in Figure 31. To avoid triggering the current limit in normal
operation and cycle skipping. As the load increases or decreases, operation, the drain current waveform should stay within the
the power supply automatically switches between normal and envelope shown.
cycle skipping mode as necessary.
Line Undervoltage Detection (UV)
Cycle skipping may be avoided, if so desired, by connecting At power up, UV keeps DPA-Switch off until the input line
a minimum load at the power supply output such that the duty voltage reaches the under voltage upper threshold. At power
cycle remains at a level higher than DCMIN at all times. down, UV holds DPA-Switch on until the input voltage falls
below the under voltage lower threshold. A single resistor
Error Amplifier connected from the LINE-SENSE pin to the DC input bus sets
The shunt regulator can also perform the function of an error UV upper and lower thresholds. To avoid false triggering by
amplifier in primary side feedback applications. The shunt noise, a hysteresis is implemented which sets the UV lower
regulator voltage is accurately derived from a temperature- threshold typically at 94% of the UV upper threshold. If the UV
compensated bandgap reference. The gain of the error amplifier is lower threshold is reached during operation without the power
set by the CONTROL pin dynamic impedance. The CONTROL supply losing regulation and the condition stays longer than
pin clamps external circuit signals to the VC voltage level. 10 µs (typical), the device will turn off and stay off until the
2-6
2-6
Rev. Q 05/06
DPA423-426
UV upper threshold has been reached again. Then, a soft-start threshold was chosen to ensure that the power capability of
will be initiated the next time CONTROL pin voltage reaches the DPA-Switch is not restricted by this feature under normal
5.8.V. If the power supply loses regulation before reaching the operation.
UV lower threshold, the device will enter auto-restart. At the end
of each auto-restart cycle (S7), the UV comparator is enabled. If Remote ON/OFF
the UV upper threshold is not exceeded, the MOSFET will be Remote ON/OFF control describes operation where the IC is
disabled during the next cycle (see Figure 5). The UV feature turned on or off for long periods as opposed to the cycle-by-
can be disabled independent of OV feature. cycle ON/OFF control, which is described in the Synchronization
section below.
Line Overvoltage Shutdown (OV)
The same resistor used for UV also sets an overvoltage DPA-Switch can be turned on or off by controlling the current into
threshold which, once exceeded, will force the DPA-Switch the LINE-SENSE pin or out from the EXTERNAL CURRENT
output into the off-state within one switching cycle. The ratio LIMIT pin (see Figure 7). This allows easy implementation of
of OV and UV thresholds is preset at 2.7 as can be seen in remote ON/OFF control of DPA-Switch in several different
Figure 7. When the MOSFET is off, the input voltage surge ways. A transistor or an optocoupler output connected between
capability is increased to the voltage rating of the MOSFET the EXTERNAL CURRENT LIMIT pin and the SOURCE pin
(220 V), due to the absence of the reflected voltage and leakage implements this function with “active-on” (Figures 17, 19 and 21)
spikes on the drain. A small amount of hysteresis is provided on while a transistor or an optocoupler output connected between
the OV threshold to prevent noise triggering. The OV feature the LINE-SENSE pin and the CONTROL pin implements the
can be disabled independent of the UV feature as shown in function with “active-off” (Figures 18, 20 and 22).
Figure 13.
When a signal is received at the LINE-SENSE pin or the
Line Feed-Forward with DCMAX Reduction EXTERNAL CURRENT LIMIT pin to disable the output
The same resistor used for UV and OV also implements line through any of the pin functions such as OV, UV and remote
voltage feed-forward that minimizes output line ripple and ON/OFF, DPA-Switch always completes its current switching
reduces power supply output sensitivity to line transients. cycle before the output is forced off. The internal oscillator is
This feed-forward operation is illustrated in Figure 4 by the stopped at the end of the current cycle and stays there as long
different values of IL. Note that for the same CONTROL pin as the disable signal exists. When the signal at the above pins
current, higher line voltage results in smaller operating duty changes state from disable to enable, the internal oscillator
cycle. As an added feature, the maximum duty cycle DCMAX starts the next switching cycle.
is also reduced from 75% (typical) at a voltage slightly higher 2
than the UV threshold to 33% (typical) at the OV threshold The remote ON/OFF feature can be used as a standby or power
(see Figures 4, 7). Limiting DCMAX at higher line voltages switch to turn off the DPA-Switch and keep it in a very low
helps prevent transformer saturation due to large load transients power consumption state for indefinitely long periods. If the
in forward converter applications. DCMAX of 33% at the OV DPA-Switch is held in remote-off state for longer than 10 µs
fSYNC ≥ 128 kHz; tOFF ≤ 7.7 µs; 120 ns ≤ tON ≤ 2250 ns for fOSC = 400 kHz
≤ 3080 ns for fOSC = 300 kHz
Oscillator
(SAW)
DMAX
VL 2V Time
0V
tON
tOFF
ON OFF SYNC
PI-2762-070501
Figure 6. Synchronization Timing Diagram.
2-7
Rev. Q 05/06
DPA423-426
(typical), the CONTROL pin goes into the hysteretic mode at each restart attempt during auto-restart and when restarting
of operation. In this mode, the CONTROL pin goes through after being in hysteretic regulation of CONTROL pin voltage
alternate charge and discharge cycles between 4.8 V and (VC), due to remote off or thermal shutdown conditions. This
5.8 V (see CONTROL Pin Operation section above) and the IC effectively minimizes current and voltage stresses on the output
runs entirely off the high-voltage DC input, but with very low MOSFET, the clamp circuit and the output rectifier during
power consumption (30 mW typical at 48 V with LINE-SENSE startup. This feature also helps minimize output overshoot and
and EXTERNAL CURRENT LIMIT pins open). When the prevents saturation of the transformer during startup.
DPA-Switch is remotely turned on after entering this mode, it
will initiate a normal startup sequence with soft-start the next Shutdown/Auto-Restart
time the CONTROL pin reaches 5.8 V. In the worst case, To minimize DPA-Switch power dissipation under fault
the delay from remote on to startup can be equal to the full conditions, the shutdown/auto-restart circuit turns the power
discharge/charge cycle time of the CONTROL pin, which is supply on and off at an auto-restart duty cycle of typically 4%
approximately 36 ms for a 22 µF CONTROL pin capacitor. if an out of regulation condition persists. Loss of regulation
This reduced-consumption remote-off mode can eliminate interrupts the external current into the CONTROL pin. VC
expensive and unreliable in-line mechanical switches. It also regulation changes from shunt mode to the hysteretic auto-
allows for microprocessor-controlled turn-on and turn-off restart mode as described in CONTROL pin operation section.
sequences that may be required in certain applications. When the fault condition is removed, the power supply output
becomes regulated, VC regulation returns to shunt mode, and
Synchronization normal operation of the power supply resumes.
In addition to sensing incoming current for OV, UV and
remote ON/OFF, the LINE-SENSE pin also monitors its pin Hysteretic Over-Temperature Protection
voltage through a 1 V threshold comparator. A pin voltage Over temperature protection is provided by a precision analog
below 1 V turns on DPA-Switch. When the voltage at LINE- circuit that turns the output MOSFET off when the junction
SENSE pin rises beyond 1 V to disable the output, DPA-Switch temperature exceeds the thermal shutdown temperature
completes its current switching cycle before the output is (137 °C typical). When the junction temperature cools to below
forced off (similar to remote ON/OFF operation). The internal the hysteretic temperature (110 °C typical), normal operation
oscillator is stopped at the end of the current cycle awaiting the resumes providing automatic recovery. VC is regulated in
LINE-SENSE pin voltage to go low to start the next cycle. This hysteretic mode and a 4.8 V to 5.8 V (typical) sawtooth waveform
allows the use of the 1 V threshold to synchronize DPA-Switch is present on the CONTROL pin while in thermal shutdown.
to an external signal with a frequency lower than its internal
2 switching frequency. A transistor or an optocoupler output Bandgap Reference
connected between the LINE-SENSE pin and the SOURCE All critical DPA-Switch internal voltages are derived from a
pin implements this function (see Figure 24). Please refer to temperature-compensated bandgap reference. This reference
Figure 6 for the timing waveforms of synchronization is also used to generate a temperature-compensated current
operation. reference that is trimmed to accurately set the switching
frequency, current limit, and the line OV/UV thresholds.
In order to be recognized as a synchronization pulse, the DPA-Switch has improved circuitry to maintain all of the above
LINE-SENSE pin needs to stay low (on-time) for at least critical parameters within very tight absolute and temperature
120 ns but no more than 2250 ns for 400 kHz (or 3080 ns for tolerances.
300 kHz) internal switching frequency. In addition, the off-
time must be kept below 7.7 µs, which is a limitation set by High-Voltage Bias Current Source
the lowest synchronization frequency of 128 kHz allowed by This current source biases DPA-Switch from the DRAIN pin
the chip. The effective DCMAX for synchronization operation and charges the CONTROL pin external capacitance during
can be calculated as 0.75 • fSYNC/fOSC. An off-time longer than startup or hysteretic operation. Hysteretic operation occurs
7.7 µs may force the CONTROL pin to go into the hysteretic during auto-restart, remote off and over-temperature shutdown.
mode and initiate a soft-start cycle at next turn-on. In this mode of operation, the current source is switched on and
off with an effective duty cycle of approximately 20%. This
Soft-Start duty cycle is determined by the ratio of CONTROL pin charge
Two on-chip soft-start functions are activated at startup with (IC(CH)) and discharge currents (ICD1 and ICD2). This current source
a duration of 5 ms (typical). Maximum duty cycle starts from is turned off during normal operation when the output MOSFET
0% and linearly increases to the default maximum of 75% at is switching. The effect of the current source switching may be
the end of the 5 ms duration and the current limit starts from seen on the DRAIN voltage waveform as small disturbances,
about 85% and linearly increases to 100% at the end of the which is normal.
5 ms duration. In addition to startup, soft-start is also activated
2-8
2-8
Rev. Q 05/06
DPA423-426
Using Feature Pins pin and the SOURCE pin to generate synchronization pulse.
Each time the MOSFET turns on, the falling edge of the
FREQUENCY (F) Pin Operation LINE-SENSE pin voltage initiates a new switching cycle. The
The FREQUENCY pin is a digital input pin. Shorting the lowest synchronization frequency guaranteed by DPA-Switch is
FREQUENCY pin to SOURCE pin selects the nominal 128 kHz. Refer to Table 2 for possible combinations of the
switching frequency of 400 kHz (Figure 9) which is suited for functions with example circuits shown in Figure 11 through
most applications. For other applications that may benefit from Figure 24. A description of specific functions in terms of the
lower switching frequency, a 300 kHz switching frequency can LINE-SENSE pin I/V characteristic is shown in Figure 7 (right
be selected by shorting the FREQUENCY pin to the CONTROL hand side). The horizontal axis represents LINE-SENSE pin
pin (Figure 10). This pin should not be left open. current with positive polarity indicating currents flowing into
the pin. The meaning of the vertical axes varies with functions.
LINE-SENSE (L) Pin Operation For those that control the on or off states of the output such
When current is fed into the LINE-SENSE pin, it works as a as UV, OV and remote ON/OFF, the vertical axis represents
voltage source of approximately 2.6 V up to a maximum current the enable/disable states of the output. UV triggers at IUV
of +240 µA (typical). At +240 µA, this pin turns into a constant (+50 µA typical with 4 µA hysteresis) and OV triggers at IOV
current sink. Refer to Figure 8. In addition, a comparator with (+135 µA typical with 4 µA hysteresis). Between the UV and
a threshold of 1 V is connected at the pin and is used to detect OV thresholds, the output is enabled. For line feed-forward with
when the pin is shorted to the SOURCE pin. DCMAX reduction, the vertical axis represents the magnitude
of the DCMAX Line feed-forward with DCMAX reduction lowers
There are a total of five functions available through the use of maximum duty cycle from 75% at IL(DC) (+55 µA typical) to
the LINE-SENSE pin: OV, UV, line feed-forward with DCMAX 33% at IOV (+135 µA).
reduction, remote ON/OFF and synchronization. Shorting the
LINE-SENSE pin to the SOURCE pin disables all five functions. EXTERNAL CURRENT LIMIT (X) Pin Operation
The LINE-SENSE pin is typically used for line sensing by When current is drawn out of the EXTERNAL CURRENT
connecting a resistor from this pin to the positive input DC LIMIT pin, it works as a voltage source of approximately
voltage bus to implement OV, UV and line feed-forward with 1.3 V up to a maximum current of -230 µA (typical). At
DCMAX reduction over line voltage. In this mode, the value of -230 µA, it turns into a constant current source (refer to Figure 8).
the resistor determines the line OV/UV thresholds, and the
DCMAX is reduced linearly with input DC high voltage starting There are two functions available through the use of the
from just above the UV threshold. This pin can also be used EXTERNAL CURRENT LIMIT pin: external current limit
as the input pin for remote ON/OFF and synchronization. and remote ON/OFF. Shorting the EXTERNAL CURRENT 2
An external transistor placed between the LINE-SENSE pin LIMIT pin and SOURCE pin disables both functions. In high
and the CONTROL pin realizes remote ON/OFF via UV or efficiency applications, this pin can be used to reduce the current
OV threshold. Synchronization is available by connecting limit externally to a value close to the operating peak current,
an open drain external MOSFET between the LINE-SENSE by connecting the pin to the SOURCE pin through a resistor.
LINE-SENSE AND EXTERNAL CURRENT LIMIT PIN TABLE*

Figure Number 11 12 13 14 15 16 17 18 19 20 21 22 23 24
▼
Three Terminal Operation ✓

Undervoltage ✓ ✓ ✓ ✓ ✓
Overvoltage ✓ ✓ ✓ ✓ ✓
Line Feed-Forward (DCMAX) ✓ ✓ ✓ ✓
Overload Power Limiting ✓
External Current Limit ✓ ✓ ✓ ✓ ✓ ✓
Remote ON/OFF ✓ ✓ ✓ ✓ ✓ ✓
Synchronization ✓
*This table is only a partial list of many LINE-SENSE and EXTERNAL CURRENT LIMIT pin configurations that are possible.
Table 2. Typical LINE-SENSE and EXTERNAL CURRENT LIMIT Pin Configurations.
2-9
Rev. Q 05/06
DPA423-426
IREM(U) IUV(U) IOV(U)

(Enabled) (Enabled)
Output Output
MOSFET MOSFET
Switching Switching
(Disabled) (Disabled)
ILIMIT (Default)
DCMAX (75%)
Current Maximum
Limit Duty Cycle
-21.5 µA
VBG + VTP
-25.5 µA
131 µA
VBG 135 µA
47 µA
X Pin Voltage L Pin Voltage
-250 -200 -150 -100 -50 0 0 50 100 150 200 250

X Pin Current (µA) L Pin Current (µA)
Note: These figures provide idealized functional characteristics with typical performance values. Please refer to the
parametric table and typical performance characteristics sections of the data sheet for measured data.
PI-2778-080801
2 Figure 7. LINE-SENSE and EXTERNAL CURRENT LIMIT Pin Characteristics.
The pin can also be used as a remote ON/OFF control input. output such as remote ON/OFF, the vertical axis represents the
Table 2 shows several different ways of using this pin. See enable/disable states of the output. For external current limit,
Figure 7 for a description of the functions where the horizontal the vertical axis represents the magnitude of the ILIMIT. Please
axis (left hand side) represents the EXTERNAL CURRENT see graphs in the Typical Performance Characteristics section
LIMIT pin current. The meaning of the vertical axes varies for the current limit programming range and the selection of
with function. For those that control the ON/OFF states of the the appropriate resistor value.
2-10
2-10
Rev. Q 05/06
DPA423-426
CONTROL (C)
DPA-Switch
230 µA
(Negative Current Sense - ON/OFF,

Current Limit Adjustment)
VBG + VT
EXTERNAL CURRENT LIMIT (X)
LINE-SENSE (L) (Voltage Sense)

1V
VBG
(Positive Current Sense - Under-Voltage,
Overvoltage, ON/OFF Maximum Duty
Cycle Reduction)
240 µA
PI-2765-061704
Figure 8. LINE-SENSE (L) and EXTERNAL CURRENT LIMIT (X) Pin Input Simplified Schematic.
2-11
2-11
Rev. Q 05/06
DPA423-426
Typical Uses of FREQUENCY (F) Pin T
+ +
DC DC
D D
Input Input
Voltage CONTROL Voltage CONTROL
C C
S F S F
- -
PI-2654-071700 PI-2655-071700
Figure 9. 400 kHz Frequency Operation. Figure 10. 300 kHz Frequency Operation.
Typical Uses of LINE-SENSE (L) and EXTERNAL CURRENT LIMIT (X) Pins
+ + VUV = IUV x RLS + VL (I = I )

L UV
VOV = IOV x RLS + VL (I = I )
L OV
C L X S F D RLS 619 kΩ
1%
DC DC For RLS = 619 kΩ
Input Input VUV = 33.3 V
Voltage Voltage VOV = 86.0 V
D L D L
C S D
2 CONTROL
C
CONTROL
C
S X F S
- -
PI-2766-070901 PI-2767-091302
Figure 11. Three Terminal Operation (LINE-SENSE and Figure 12. Line-Sensing for Undervoltage, Overvoltage and
EXTERNAL CURRENT LIMIT Features Disabled – Line Feed-forward.
FREQUENCY Pin can be tied to SOURCE or
CONTROL Pin).
+ VUV = RLS x IUV +

+
VOV = IOV x RLS +
464 kΩ 590 kΩ
VL (I = I ) VL (I = I )
1% L UV 1% L OV
RLS
For Values Shown For Values Shown
RLS
VUV = 33.1 V VOV = 86.2 V
DC DC
150 kΩ 30 kΩ
Input 1% Input
1%
Voltage Voltage 1N4148
D L D L
CONTROL CONTROL
C C
15 V
S S
- -
PI-2852-121504 PI-2853-091302
Figure 13. Line-Sensing for Undervoltage Only Figure 14. Line-Sensing for Overvoltage Only (Undervoltage
(Overvoltage Disabled). Disabled). Maximum Duty Cycle will be reduced
at Low Line.
2-12
2-12
Rev. Q 05/06
DPA423-426
Typical Uses of LINE-SENSE (L) and EXTERNAL CURRENT LIMIT (X) Pins (cont.)
+ For RIL = 12 kΩ + ILIMIT = 100% @ 36 VDC

ILIMIT = 64% ILIMIT = 64% @ 72 VDC
RLS 363 kΩ
For RIL = 25 kΩ
ILIMIT = 34%
DC See Figure 34 for other DC

D resistor values (RIL) D
Input Input
C C
S X S X
RIL RIL
- 4.2 kΩ
-
PI-2836-011904 PI-2854-050602
Figure 15. Externally Set Current Limit. Figure 16. Current Limit Reduction with Line Voltage.
+ + QR can be an
QR can be an optocoupler optocoupler output or
output or can be replaced by can be replaced
a manual switch. by a manual switch.
QR
ON/OFF
47 kΩ RMC
DC DC
D
Input Input 37.4 kΩ
Voltage CONTROL Voltage
C
D L
CONTROL
S X C
QR
47 KΩ
ON/OFF 2
S
- -
PI-2625-040501 PI-2855-050602
Figure 17. Active-on (Fail Safe) Remote ON/OFF. Figure 18. Active-off Remote ON/OFF.
Maximum Duty Cycle will be reduced.
+ QR can be an optocoupler + QR
QR can be an
output or can be replaced optocoupler output
ON/OFF or can be replaced
by a MOSFET or manual RMC
switch.
47 kΩ by a manual switch.
For RIL = 12 kΩ 37.4 kΩ For RIL = 12 kΩ
ILIMIT = 64%
DC DC ILIMIT = 64%
D For RIL = 25 kΩ D L
Input Input
For RIL = 25 kΩ
Voltage CONTROL ILIMIT = 34% Voltage CONTROL
C C ILIMIT = 34%
S X S X
RIL RIL
QR ON/OFF
- 47 kΩ -
PI-2856-072602 PI-2857-050602
Figure 19. Active-on Remote ON/OFF with Figure 20. Active-off Remote ON/OFF with
Externally Set Current Limit. Externally Set Current Limit.
2-13
2-13
Rev. Q 05/06
DPA423-426
+ + QR can be an optocoupler
DCMAX@36 V = 75% RLS 619 kΩ output or can be replaced
DCMAX@72 V = 42% 1% by a MOSFET or manual
RLS 619 kΩ switch.
1% QR
For RLS = 619 kΩ
ON/OFF
QR can be an optocoupler 47 kΩ
DC output or can be replaced VUV = 33.3 V
D L
Input by a manual switch. VOV = 86.0 V
Voltage CONTROL DC
C For RIL = 12 kΩ Input D L
ILIMIT = 64% Voltage CONTROL
S X C
QR
RIL
ON/OFF
S
- 47 kΩ -
PI-2859-050602 PI-2858-072602
Figure 21. Active-on Remote ON/OFF with LINE-SENSE and Figure 22. Active-off Remote ON/OFF with LINE-SENSE.
EXTERNAL CURRENT LIMIT.
For RLS = 619 kΩ
output.
VUV = 33.3 V
619 KΩ For timing requirements,
RLS VOV = 86.0 V
1%
see Figure 6.
DCMAX@36 V = 75%
DC DCMAX@72 V = 42% DC
D L D L
Input Input
C C
2
For RIL = 12 kΩ
S X ILIMIT = 64% S
RIL See Figure 34 for other QR ON/OFF
12 kΩ resistor values (RIL) 47 kΩ
- to select different ILIMIT -
values PI-2837-011904 PI-3868-050602
Figure 23. LINE-SENSE and EXTERNAL CURRENT LIMIT. Figure 24. Synchronization.
2-14
2-14
Rev. Q 05/06
DPA423-426
Application Examples
C7
1 nF R14
L1 1.5 kV 10 Ω
+ VIN 1 µH C10 C11 C12
2.5 A 100 µF 100 µF 1 µF
36-75 VDC L2 10 V 10 V 10 V 5 V, 6 A
C17
R1 3300 pF
R15
619 kΩ 10 Ω R16 D2
1% D1
R17 10 kΩ BAV
10 Ω Q1
Si4888 19WS
DY
RTN
T1 Q2 D4
Si4888 C4
BAV19WS 4.7 µF
DY U2
20 V
R7
C1, C2 & C3 10 kΩ R10
1 µF C9* R5* 10.0 kΩ
100 V 1%
DPA-Switch D3 C16
U1 U2 100 nF
D L
PC357N1T BAV19WS
DPA425R
CONTROL R6 R12
C 150 Ω 5.1 Ω
R9
220 Ω
S X F
R4 C13
10 µF C14
VR1 1.0 Ω 1 µF
R3 10 V
SMBJ C5 U3
150 18.2 kΩ 220 nF C6
1% 68 µF LM431AIM3 R11
10 V 10.0 kΩ
VIN 1%
*Optional components PI-3472-061704
Figure 25. A High Efficiency 30 W, 5 V, Telecom Input DC-DC Converter.
High Efficiency 30 W Forward Converter requiring any other circuit changes. This has been used here 2
The circuit shown in Figure 25 is a typical implementation of a to replace the DPA424R with a DPA425R.
single output DC-DC converter using DPA-Switch in a forward
configuration with synchronous rectification. This design The selectable 300/400 kHz switching frequency is set to 300 kHz
delivers 30 W at 5 V, from a 36 VDC to 75 VDC input with a by connecting the FREQUENCY (F) pin to CONTROL (C).
nominal efficiency at 48 VDC of 90% using the DPA425R.
DRAIN voltage clamping is provided by VR1, which keeps
By taking advantage of many of the built-in features of the the peak DRAIN voltage within acceptable limits. Transformer
DPA-Switch, the design is greatly simplified compared to core reset is provided by the gate capacitance of Q1 with R17
a discrete implementation. Resistor R1 programs the input in series. Optional reset capacitance C9 with R5 can be added
undervoltage and overvoltage thresholds to typically 33 V and 86 if necessary to supplement the gate capacitance of Q1.
V respectively. This resistor also linearly reduces the maximum
duty from the internal maximum of 75% at 36 V to 42% at The output of the transformer is rectified using MOSFETs
72 V to prevent core saturation during load transients at high input to provide synchronous rectification. The UV/OV function,
voltages. The DPA-Switch internal thresholds are toleranced together with the turns ratio of the transformer, defines the
and characterized so the designer can guarantee the converter maximum MOSFET gate voltage, allowing the very simple
will begin operation at 36 V, necessary to meet ETSI standards, gate drive arrangement, without the need for drive windings
without the cost of an external reference IC. or a drive IC. During primary on-time, capacitor C17 couples
charge through resistor R15 to drive the gate of the forward
The current limit is externally set by resistor R3 to just above the MOSFET, Q2. Capacitor C17 provides a DC isolated drive for
drain current level needed for maximum load regulation to limit Q2, preventing gate overstress on Q1 during power down. The
the maximum overload power of the converter. The externally time constant formed by R16 and C17 is selected to be much
programmable current limit feature also allows a larger longer than one switching cycle. Diode D4 resets the voltage
DPA-Switch family member to be selected. Using the X pin, the on capacitor C17 before the next switching cycle. During the
current limit can be adjusted to the same level. A large device primary off-time, the diode D2 provides a conduction path for
reduces conduction losses and improves efficiency without the energy in inductor L2 while Q1 is still off. The transformer
2-15
2-15
Rev. Q 05/06
DPA423-426
+VIN L1
36 - 57 VDC T1 1 µH, 2A 3.3 V, 2 A
1 9, 10
J1-1 J2-1
D2
SL43 C5 C6 C7 C9
R1 R2 330 µF 330 µF 1 µF
1 MΩ 330 µF
619 kΩ 2 6V 6V 6V 10 V
1% 1%
6, 7 RTN
C2 4 J2-2
47 pF
200 V R5 D3
3 100 Ω BAV19, SOD323
R8
R6 34 kΩ
5 R7 1%
51 Ω 1 kΩ
C8
C1 DPA-Switch 1 µF
1 µF VR1 50 V
SMAJ D L U1
100 V DPA423G U2
150A CONTROL
C
PC357
C11
C3 R4 0.1 µF
S X F 5.1 Ω
0.1 µF
50 V U3
R3 C4 C10 R9
0.33 µF CAT431L, 20 kΩ
8.66 kΩ 22 µF SOT23
-VIN 1% 10 V 1%
J1-2
PI-3806-061704
Figure 26. A Cost Effective 6.6 W, 3.3 V Flyback DC-DC Converter.
reset voltage on the secondary winding directly drives a positive sense resistor R1 reduces the current limit with increasing input
voltage on the gate of catch MOSFET, Q1. MOSFET Q1 voltage, preventing excessive overload output current. In this
provides a low loss conduction path for a substantial portion design the overload output current varies less than ±2.5% across
of the primary off-time. An isolated auxiliary winding on L2, the entire input voltage range. Controlling the current limit also
rectified and filtered by D1 and C4, provides the bias supply reduces secondary component stress and leakage inductance
for the optocoupler transistor. Output regulation is achieved spikes, allowing the use of a lower VRRM (30 V rather than
2 by using secondary side voltage reference, U3. The resistor 40 V) Schottky output diode, D2.
divider formed by R10 and R11, together with the reference
voltage, determines the output voltage. Diode D3 and C13 form The primary side Zener clamp VR1 ensures the peak drain
a soft-finish network that, together with the internal duty cycle voltage is kept below the 220 V BVDSS rating of U1 under
and current limit soft-start of the DPA-Switch, prevent output input surge and overvoltage events. During normal operation,
overshoot at startup. Resistor R7 ensures that the soft-finish VR1 does not conduct and C2 is sufficient to limit the peak
capacitor is discharged quickly when the output falls out of drain voltage.
regulation. Control loop response is shaped by R6, C16, R12,
C14, R9, R4 and C5, providing a wide bandwidth and good The primary bias winding provides CONTROL pin current after
phase margin at gain crossover. Since the PWM control in startup. Diode D3 rectifies the bias winding, while components
DPA-Switch is voltage mode, no slope compensation is required R5 and C8 reduce high frequency switching noise and prevent
for duty cycles above 50%. peak charging of the bias voltage. Capacitor C3 provides
local decoupling of U1 and should be physically close to the
Cost Effective 6.6 W Flyback Converter CONTROL and SOURCE pins. Energy storage for startup and
The DPA-Switch flyback power supply provides a cost effective auto-restart timing is provided by C4.
solution for high density PoE and VoIP DC-DC applications.
The secondary is rectified by D2 and the Low ESR tantalum
Figure 26 shows a typical implementation of a single output output capacitors, C5-C7, minimizing switching ripple and
flyback converter using the DPA423G. For applications that maximizing efficiency. A small footprint secondary output choke
require input to output isolation, this simple, low component L1 and ceramic output capacitor C9 are adequate to reduce high
count design delivers 6.6 W at 3.3 V from a 36 VDC to 57 VDC frequency noise and ripple to below 35 mV peak-to-peak under
input with a nominal efficiency at 48 VDC of 80%. full load conditions.
Resistor R2 programs the input undervoltage and overvoltage The output voltage is sensed by the voltage divider formed by
thresholds to 33 V and 86 V respectively. Resistors R1 and R3 resistors R8 and R9 and is fed to the low-voltage 1.24 V reference
program the internal device current limit. The addition of line- U3. Feedback compensation is provided by R6, R7 and C11
2-16
2-16
Rev. Q 05/06
DPA423-426
D41
BAV19WS 20 V, 10 mA
C41
4.7 µF, 35 V
Ethernet VR41 D42
4 3 6.8 V IN4148
(RJ-45) D101 D31
Connector DL4002 L1
PoE Interface 1 µH 2.5 A 20CJQ060
1 8 7.5 V, 0.4 A
(1,2)
7 6 C31
Q22 100 µF
Si4804 10 V
3 7 C25
DL4002 VR51 L2 C22-C24 R4 1 µF
28 V 6 C21 16 µH 4 A
D102 2.2 nF 100 µF 5 V 160 Ω 10 V 5 V, 2.4 A
R1 R21 8 5
649 kΩ 10 Ω
1% 4 7 2
R52 R22
20 kΩ D6
D103 10 Ω BAV
5 19WS RTN
DL4002
T1 Q21 VR21 D21
(4,5) C1 C2 Si4804 SL13
1 µF 1 µF R23 15 V
R51 100 V 174 k R23 C6
100 V 4.7 µF U2
24.9 kΩ 1% 10 kΩ R16
DL4002 1% 1/4 W 20 V 10 kΩ
D104 1%
R21
10 k
Q20
MMBTS3906
R22
D105 10 kΩ U2
DL4002 PC357
(3,6) N1T R11
DPA-Switch 10 kΩ
C51 R12 C12
1 nF U1
D51 D L DPA424P 150 Ω 100 nF
DL4002 BAV19 50 V
D106 CONTROL
R13
C 11 Ω
D11
BAV19WS
D52
BAV19 S X F R3 C11 C13 R14
VR1 1.0 Ω
D107 SMAJ 2.2 µF 68 nF 1 kΩ
R53 C4 10 V
DL4002 R54 150 220 nF C5
20 kΩ 20 Ω U3
(7,8) R2 47 µF R15
10 V LM431AIM3 10 kΩ
13.3 kΩ
1% 1%
Q51
TIP29C (100 V/1 A) PI-3824-040706
DL4002
D108 or MMBTA06
Figure 27. PoE Interface Circuit Using a Bipolar Transistor Pass-Switch and DPA424P.
2
together with C4 and R4. Capacitor C10 provides a soft-finish The second “classification” phase occurs at input voltages
characteristic, preventing output overshoot during startup. 15 VDC to 20 VDC. The PD must draw a specified current to
identify the device class (Class 0 specifies 0.5 mA to 4 mA).
Low Cost PoE VoIP Phone Converter This is again accomplished by resistor R51.
The basic circuitry to support IEEE standard 802.3af Power
over Ethernet (PoE) is straightforward. Class 0 signature and In the third phase, the bipolar pass-switch (Q51 in Figure 27)
classification circuits can be implemented with a single resistor connects the input voltage to the power supply at voltages
and the required undervoltage lockout function is a voltage above approximately 30 VDC (28 V+VR52). Zener diode VR51
controlled pass-switch. By adding this circuitry to the front conducts, driving the current through resistor R52 to the base
end of a DPA converter, a low cost and low component count of Q51. Resistor R53 prevents turn-on under other conditions.
PoE powered device (PD) power supply can be implemented. Once the Power supply has started, components D51, D52, C51
Figure 27 shows a typical PD solution. and R54 enhance the base-current drive by coupling power from
the power supply bias winding.
The PoE specification requires the PD to provide three
fundamental functions: discovery, classification, and pass- Once the three startup phases have been successfully completed,
switch connection. the DPA-Switch is allowed to function as a forward converter
(described in Figure 25 and accompanying text).
When input voltage is applied to the PD, it must present the
correct discovery signature impedance in the voltage range of
2.5 VDC to 10 VDC. This impedance is provided by R51 in
Figure 27.
2-17
2-17
Rev. Q 05/06
DPA423-426
Key Application Considerations OUTPUT POWER TABLE

DPA-Switch Design Considerations 16-32 VDC RANGE (FORWARD)2
Total Device Max
Power Table Dissipation 0.5 W 1W 2.5 W 4W 6W Power
This section provides a description of the assumptions used PRODUCT3 Output1
to generate the power tables (Tables 1 and 3 through 6) and DPA423 5W 7W - - - 7.5 W
explains how to use the information provided by them.
DPA424 7 W 10 W 15 W - - 15.5 W
All Power tables: Tables 1 and 3 through 6 DPA425 10 W 14 W 22 W 27 W 31 W
• Maximum output power is limited by the device internal DPA426 12 W 16.5 W 25 W 31 W 37 W 43 W
current limit. This is the peak output power which could
Table 3. Output Power Table for 16-32 VDC Input Voltage.
become the continuous output power, provided adequate Notes: 1. Limited by device internal current limit. 2. See text in this
heat sinking is used. section for a complete description of assumptions. 3. See Part Ordering
• Data assumes adequate heat sinking to keep the junction Information.
temperature at or below 100 °C and worst case RDS(ON) at
TJ = 100 °C. OUTPUT POWER TABLE
• The use of P and G packages are recommended for device 24-48 VDC RANGE (FORWARD)2
dissipation equal to or less than 1.5 W only due to package Total Device Max
thermal limitation. For device dissipation above 1.5 W, use Dissipation 0.5 W 1 W 2.5 W 4W 6W Power
S and R packages. PRODUCT3 Output1
Forward power tables: Tables 1 (upper half), 3 and 4 DPA423 8 W 11 W - - - 11.5 W

• Output power figures are based on forward topology using DPA424 11 W 16 W 23.5 W - - 25 W
Schottky diode rectification. Up to 5% higher output power DPA425 16 W 22 W 35 W 43 W 47 W
is possible using synchronous rectification.
• Dissipation data assumes a diode loss representing 6% DPA426 18 W 25 W 39 W 48 W 58 W 65 W
of the total output power and combined loss in magnetic Table 4. Output Power Table for 24-48 VDC Input Voltage
components representing 6% of the total output power. (See Table 3 for Notes).
DPA-Switch losses are based on a ratio between conduction
2 and switching losses of approximately 3:1. These OUTPUT POWER TABLE
assumptions are typical for a single 5 V output forward 16-32 VDC RANGE (FLYBACK)2
converter design using Schottky rectification and adequately Total Device Max
designed magnetic components. Dissipation 0.5 W 0.75 W 1W 1.5 W Power
PRODUCT3 Output1
Flyback power tables: Tables 1 (lower half), 5 and 6
• Output power and dissipation figures are based on a 5 V DPA423 5W - - - 6W
output using Schottky diode rectification with an efficiency DPA424 6.5 W 8.5 W 10 W - 11 W
of 85%. Values are generated by calculation based on DPA425 7W 10 W 12 W 15 W 22 W
I2 • RDS(ON) losses and characterization of switching losses,
correlated to bench measurement of each DPA-Switch Table 5. Flyback Output Power Table for 16-32 VDC Input
Voltage (See Table 3 for Notes).
device.
• Device dissipations above 1.5 W are possible using the
S and R packages. However the forward converter topology
OUTPUT POWER TABLE
is recommended for such higher power designs. 24-48 VDC RANGE (FLYBACK)2
Total Device Max
The power tables provide two types of information. The first is Dissipation 0.5 W 0.75 W 1W 1.5 W Power
the expected device dissipation for a given output power. The PRODUCT3,4 Output1
second is the maximum power output. Each table specifies
DPA423 7W - - - 8.5 W
the input voltage range and assumes a single 5 V output using
Schottky diode rectification. DPA424 8.5 W 11.5 W 14 W - 17 W
Table 6. Flyback Output Power Table for 24-48 VDC Input Voltage.
For example, referring to Table 1, for 36 VDC to 75 VDC input Notes: 1. Maximum output power is limited by device internal
range, DPA424 would typically dissipate 1 W in a 23 W forward current limit. 2. See text in this section for a complete description of
assumptions. 3. See Part Ordering Information. 4. Higher switching losses
converter and has a maximum power capacity of 35 W. In the may prevent DPA425 from delivering more power than a smaller device.
2-18
2-18
Rev. Q 05/06
DPA423-426
same converter, DPA425 would dissipate 0.5 W. Selecting Soft-Start

DPA425 with associated reduced dissipation would increase Generally a power supply experiences maximum stress at
overall converter efficiency by approximately 2%. startup before the feedback loop achieves regulation. For a
period of 5 ms the on-chip soft-start linearly increases the duty
Issues Affecting Dissipation: cycle from zero to the default DCMAX at turn-on. In addition,
1) Using synchronous rectification will tend to reduce device the primary current limit increases from 85% to 100% over the
dissipation. same period. This causes the output voltage to rise in an orderly
2) Designs with lower output voltages and higher currents manner allowing time for the feedback loop to take control of
will tend to increase the device dissipation listed in the the duty cycle. This integrated soft-start reduces the stress on
power table. the DPA-Switch MOSFET, clamp circuit and output diode(s),
3) Reduced input voltage decreases the available output and helps prevent transformer saturation during startup. Also,
power for the same device dissipation. Tables 3 to 6 are soft-start limits the amount of output voltage overshoot, and in
the power tables for 16 VDC and 24 VDC input voltages. many applications eliminates the need for a soft-finish capacitor.
Input voltages below 16 V are possible, but since the internal If necessary, to remove output overshoot, a soft-finish capacitor
startup current source is not specified at voltages below may be added to the secondary reference.
16 V, an external chip supply current should be fed into the
CONTROL pin approximately equal to but less than ICD1. Switching Frequency
The FREQUENCY pin of DPA-Switch offers a switching
DPA-Switch Selection frequency option of 400 kHz or 300 kHz. Operating at 300 kHz
Use Tables 1 and 3 through 6 to select the DPA-Switch based will increase the amount of magnetization energy stored in the
on device dissipation. Selecting the optimum DPA-Switch transformer. This is ideal for applications using synchronous
depends upon required maximum output power, efficiency, heat rectification driven directly from the transformer secondary
sinking constraints and cost goals. With the option to externally where this energy can be used to drive the catch MOSFET
reduce current limit, a larger DPA-Switch may be used for gate.
lower power applications where higher efficiency is needed
or minimal heat sinking is available. Generally, selecting the Transformer Design
next larger device, than is required for power delivery will give It is recommended that the forward converter transformer be
the highest efficiency. Selecting even larger devices may give designed for maximum operating flux swing of 1500 Gauss
little or no improvement in efficiency due to the improvement and a peak flux density of 3500 Gauss. When operating at the
in conduction losses being negated by larger device switching maximum current limit of the selected DPA-Switch (during
losses. Figure 50 provides information on switching losses. overload conditions), neither magnetic component (transformer 2
This together with conduction loss calculations give an estimate and output inductor) should be allowed to saturate. When a larger
of device dissipation. device than necessary has been selected, reducing the internal
current limit close to the operating peak current limits overload
Primary Clamp power and minimizes the size of the secondary components.
A primary clamp network is recommended to keep the peak
DRAIN voltage due to primary leakage inductance to below No-load and Standby Consumption
the BVDSS specification. A Zener diode combined with a small Cycle skipping operation at light or no load can significantly
value capacitor connected across the primary winding is a low reduce power loss. In addition this operating mode ensures
cost and low part count implementation. that the output maintains regulation even without an external
minimum load. However, if cycle skipping is undesirable in
Output Rectification a particular application, it can be avoided by adding sufficient
Rectification of the secondary is typically performed using preload.
Schottky diodes or synchronous rectification. Schottky diodes
are selected for peak inverse voltage, output current, forward drop DPA-Switch Layout Considerations
and thermal conditions. Synchronous rectification requires the
additional complication of providing gate drive. The specified The DPA-Switch can operate with large DRAIN current, the
line undervoltage and line overvoltage thresholds of DPA-Switch following guidelines should be carefully followed.
simplifies deriving gate drive directly from the transformer
secondary winding for many applications. The turns ratio of Primary Side Connections
the transformer together with the under/overvoltage thresholds The tab of DPA-Switch R package and S-PAK is the intended
defines the minimum and maximum gate voltages, removing return path for the high switching currents. Therefore, the tab
l the need for Zeners to clamp the gate voltage. should be connected by wide, low impedance traces back to
f
s
2-19
2-19
Rev. Q 05/06
DPA423-426
the input decoupling capacitor. The SOURCE pin should not Quick Design Checklist
be used to return the power currents; incorrect operation of the
device may result. The SOURCE is only intended as a signal As with any power supply design, all DPA-Switch designs
ground. The device tab (SOURCE) is the correct connection should be verified on the bench to make sure that component
for high current with the R package and S-PAK. specifications limits are not exceeded under worst case
conditions. The following minimum set of tests for DPA-Switch
The CONTROL pin bypass capacitor should be located as forward converters is strongly recommended:
close as possible to the SOURCE and CONTROL pins and its
SOURCE connection trace should not be shared by the main 1. Maximum drain voltage – Verify that peak VDS does not
MOSFET switching currents. All SOURCE pin referenced exceed minimum BVDSS at highest input voltage and
components connected to the LINE-SENSE or EXTERNAL maximum overload output power. It is normal, however, to
CURRENT LIMIT pins should also be located closely between have additional margin of approximately 25 V below BVDSS
their respective pin and SOURCE. Once again, the SOURCE to allow for other power supply component unit-to-unit
connection trace of these components should not be shared variations. Maximum overload output power occurs when
by the main MOSFET switching currents. It is critical that the output is loaded to a level just before the power supply
the tab (SOURCE) power switching currents are returned to the goes into auto-restart (loss of regulation).
input capacitor through a separate trace that is not
shared by the components connected to CONTROL, 2. Transformer reset margin – Drain voltage should also be
LINE-SENSE or EXTERNAL CURRENT LIMIT pins. checked at highest input voltage with a severe load step
(50-100%) to verify adequate transformer reset margin. This
Any traces to the L or X pins should be kept as short as possible test shows the duty cycle at high input voltage, placing the
and away from the DRAIN trace to prevent noise coupling. most demand on the transformer reset circuit.
LINE-SENSE resistor (R1 in Figure 25) should be located close
to the L pin to minimize the trace length on the L pin side. 3. Maximum drain current – At maximum ambient temperature,
maximum input voltage and maximum output load,
In addition to the CONTROL pin capacitor (C6 in Figure 25), verify drain current waveforms at startup for any signs of
a high frequency bypass capacitor in parallel is recommended transformer or output inductor saturation and excessive
as close as possible between SOURCE and CONTROL pins for leading edge current spikes. DPA-Switch has a leading edge
better noise immunity. The feedback optocoupler output should blanking time of 100 ns to prevent premature termination
also be located close to the CONTROL and SOURCE pins of of the on cycle. Verify that the leading edge current spike
2 DPA-Switch. does not extend beyond the blanking period.
Heat Sinking 4. Thermal check – At maximum output power, minimum

To maximize heat sinking of the DPA-Switch S, R or G package input voltage and maximum ambient temperature, verify
and the other power components, special thermally conductive that temperature specifications are not exceeded for the
PC board material (aluminum clad PC board) is recommended. transformer, output diodes, output choke(s) and output
This has an aluminum sheet bonded to the PC board during capacitors. The DPA-Switch is fully protected against over-
the manufacturing process to provide heat sinking directly temperature conditions by its thermal shutdown feature. It
and allow the attachment of an external heat sink. If normal is recommended that sufficient heat sinking is provided
PC board material is used (such as FR4), providing copper to keep the tab temperature at or below 115 °C (S and R
areas on both sides of the board and using thicker copper will packages), SOURCE pins at or below 100 °C (P/G packages)
improve heat sinking. under worst case continuous load conditions (at low input
voltage, maximum ambient and full load). This provides
If an aluminum clad board is used then shielding of switching adequate margin to minimum thermal shutdown temperature
nodes is recommended. This consists of an area of copper placed (130 °C) to account for part-to-part RDS(ON) variation. When
directly underneath switching nodes such as the drain node, monitoring device temperatures, note that the junction-
and output diode to provide an electrostatic shield to prevent to-case thermal resistance should be accounted for when
coupling to the aluminum substrate. These areas are connected estimating die temperature.
to input negative in the case of the primary and output return
for secondary. This reduces the amount of capacitive coupling Design Tools
into the insulated aluminum substrate that can then appear on
the output as ripple and high frequency noise. Up-to-date information on design tools is available at the Power
Integrations website: www.powerint.com.
2-20
2-20
Rev. Q 05/06
DPA423-426
Solder Side
Component Side
TOP VIEW Output

Diode
V
Transformer
+
D Inductor
(Coupled)
V
DC DPA-Switch
S
In
X
L
V
C +
DC
Opto- Out
- coupler
-
V
Maximize hatched copper area for optimum heat sinking
V Via between board layers

PI-2883-060602
Figure 28. Layout Considerations for DPA-Switch Using S-PAK or R Package.
Top Side PCB
Bottom Side PCB

2
Bottom Diode
TOP VIEW (Two sided printed circuit board) Heatsink
V
V
+ V
V
T
r V
DC a
In V
n V
- s
- f
o
S S D S r
V
DPA-Switch m
e +
C L X F r
DC
V Out
V V
-
PI-3805-012904
DPA-Switch Heatsink
Opto-
V coupler

Figure 29. Layout Considerations for DPA-Switch Using G Package.
2-21
2-21
Rev. Q 05/06
DPA423-426
ABSOLUTE MAXIMUM RATINGS(1,4)

DRAIN Voltage .................................................. -0.3 V to 220 V Operating Junction Temperature(2) ..................... -40 °C to 150 °C
DRAIN Peak Current: DPA423......................................1.75 A Lead Temperature(3) ...................................................... 260 °C
DPA424....................................... 3.5 A
DPA425........................................... 7A Notes:
DPA426....................................... 9.6 A 1. All voltages referenced to SOURCE, TA = 25 °C.
CONTROL Voltage ................................................ -0.3 V to 9 V 2. Normally limited by internal circuitry.
CONTROL Current .................................................... 100 mA 3. 1/16” from case for 5 seconds.
LINE-SENSE Pin Voltage ...................................... -0.3 V to 9 V 4. Maximum ratings specified may be applied, one at a time,
EXTERNAL CURRENT LIMIT Pin Voltage ........ -0.3 V to 9 V without causing permanent damage to the product.
FREQUENCY Pin Voltage .................................... -0.3 V to 9 V Exposure to Absolute Maximum Rating conditions for
Storage Temperature .......................................... -65 °C to 150 °C extended periods of time may affect product reliability.
THERMAL IMPEDANCE
Thermal Impedance: P or G Package: Notes:
(θJA) ........................... 70 °C/W(1); 60 °C/W(2) 1. Soldered to 0.36 sq. in. (232 mm2), 2 oz. (610 g/m2) copper clad.
(θJC)(3) ............................................11 °C/W 2. Soldered to 1 sq. in. (645 mm2), 2 oz. (610 g/m2) copper clad.
R Package: 3. Measured on pin 7 (SOURCE) close to plastic interface.
(θJA) ............................................... 40 °C/W(4) 4. Soldered to 1 sq. in. (645 mm2), 2 oz. (610 g/m2) copper clad.
(θJA) ............................................... 30 °C/W(5) 5. Soldered to 3 sq. in. (1935 mm2), 2 oz. (610 g/m2) copper clad.
(θJC)(6) ............................................. ..2 °C/W 6. Measured at the back surface of tab.
S-PAK:
(θJA) ............................................... 49 °C/W(4)
(θJA) ............................................... 39 °C/W(5)
(θJC)(6) ............................................. ..2 °C/W
Conditions
2 Parameter Symbol SOURCE = 0 V; TJ = -40 to 125 °C
See Figure 33
Min Typ Max Units
(Unless Otherwise Specified)
CONTROL FUNCTIONS
FREQUENCY Pin
375 400 425
Switching Connected to SOURCE
fOSC TJ = 25 °C kHz
Frequency FREQUENCY Pin
282 300 317
Connected to CONTROL
Duty Cycle (Prior
DCMIN 4 6 %
to Cycle Skipping)
VL = 0 V 71 75 79
Maximum Duty IL = 80 µA
DCMAX IC = ICD1 52 62 71 %
Cycle
IL = 115 µA 32 42 57
DPA423 7.2 9.0
Control Current
DPA424 8.2 10.0
at Start of Cycle IC(skip) TJ = 25 °C; fOSC = 400 kHz mA
DPA425 10.0 12.0
Skipping
DPA426 11.5 14.0
DPA423 2 2.8 3.5
External Bias DPA424 2.5 3.5 4.4
IB TJ = 25 °C; fOSC = 400 kHz mA
Current DPA425 3.6 4.8 6.0
DPA426 4.4 5.7 7.1
2-22
2-22
Rev. Q 05/06
DPA423-426
Conditions
Parameter Symbol SOURCE = 0 V; TJ = -40 to 125 °C Min Typ Max Units
See Figure 33
CONTROL FUNCTIONS (cont.)
Softstart Time tSOFT TJ = 25 °C; DCMIN to DCMAX 5 7.2 ms
PWM Gain DCreg TJ = 25 °C; IC = (IC(skip) + IB)/2 -28 -22 -18 %/mA
PWM Gain
See Note A -0.01 %/mA/°C
Temperature Drift
Dynamic
ZC TJ = 25 °C; IC = (IC(skip) + IB)/2 10 15 22 Ω
Impedance
Dynamic
Impedance 0.18 %/°C
Temperature Drift
CONTROL Pin
30 kHz
Internal Filter Pole
SHUTDOWN/AUTO-RESTART
During Startup and Auto-Restart:
VC = 5.0 V; VD = 16 V & 40 V; TJ = 25 °C -5.2 -4 -3
CONTROL Pin
IC(CH) Average Current at the Beginning of mA
Charging Current
Softstart: VC = 5.0 V; -19
VD = 16 V & 40 V; TJ = 25 °C
Charging Current
See Note A -0.6 %/°C
2
Temperature Drift
Auto-Restart
Upper Threshold VC(AR)U 5.8 V
Voltage
Auto-Restart
Lower Threshold VC(AR)L 4.5 4.8 5.1 V
Voltage
Auto-Restart
V 0.8 1 V
Hysteresis Voltage C(AR)Hyst
Auto-Restart Duty CCONTROL = 22 µF; fOSC = 400 kHz;
DC(AR) 10 %
Cycle VX = 0 V
Auto-Restart CCONTROL = 22 µF; fOSC = 400 kHz;

f(AR) 3.8 Hz
Frequency VX = 0 V
LINE-SENSE (L) AND EXTERNAL CURRENT LIMIT (X) INPUTS

Line Under- Threshold from Off to On 48 50 52
Voltage Threshold
IUV TJ = 25 °C Threshold from On to Off 44.5 47 49.5 µA
Current and
Hysteresis (L Pin) Hysteresis 2 3
2-23
2-23
Rev. Q 05/06
DPA423-426
Conditions
See Figure 33
LINE-SENSE (L) AND EXTERNAL CURRENT LIMIT (X) INPUTS (cont.)
Line Overvoltage Threshold from On to Off 135 149
or Remote ON/
OFF Threshold IOV TJ = 25 °C Threshold from Off to On 117 131 µA
Current and
Hysteresis (L Pin) Hysteresis 4
Remote ON/OFF Threshold from On to Off -27 -21.5 -16

Negative Thresh-
old Current and IREM TJ = 25 °C Threshold from Off to On -25.5 µA
Hysteresis
(X Pin) Hysteresis 4.5
L Pin Short Circuit VL = VC 175 240 380

IL(SC) µA
Current VL = 0 V -230 -170
X Pin Short Circuit Normal Mode -270 -230 -185

IX(SC) VX = 0 V µA
Current Remote OFF using L Pin -105 -85 -65
Line Pin Voltage IL = IUV 2.05 2.35 2.6

VL
(Positive Current) IL = IOV 2.1 2.5 2.9
V
X Pin Voltage IX = -50 µA 1.35
2 (Negative Current)
VX
IX = -150 µA 1.25
Maximum Duty
Cycle Reduction
IL(DC) TJ = 25 °C 55 µA
Onset Threshold
Current
Remote OFF VL = Floating 0.6 1.1
VD = 40 V
DRAIN Supply ID(RMT)
VX = 0 V
mA
Current VL = VC 0.9 1.5
L Pin Voltage
Turn-On Thresh-
VL(TH) 0.6 1 1.4 V
old in Synchro-
nous Mode
On-Time Pulse fOSC = 400 kHz 120 2250
Width for ton(sync) ns
Synchronization fOSC = 300 kHz 120 3080
Off-Time Pulse
Width for toff(sync) 0.25 7.7 µs
Synchronization
Synchronous From Synchronous On to Drain
tdelay(sync) 250 ns
Turn-On Delay Turn-On
2-24
2-24
Rev. Q 05/06
DPA423-426
Conditions
See Figure 33
FREQUENCY (F) INPUT
FREQUENCY Pin
VF 1.1 4 V
Threshold Voltage
FREQUENCY Pin VF = 0 V -0.38
IF µA
Input Current VF = VC 17 120
FREQUENCY Pin
tdelay(VF) 2 µs
Delay Time
CIRCUIT PROTECTION
DPA423 di/dt = 300 mA/µs 1.16 1.25 1.34
Self Protection DPA424 di/dt = 600 mA/µs 2.32 2.50 2.68
Current Limit (See ILIMIT TJ = 25 °C A
DPA425 di/dt = 1.25 A/µs 4.65 5.00 5.35
Note B)
DPA426 di/dt = 1.75 A/µs 6.50 7.00 7.50
Initial Current 0.9 x
IINIT VD = 35 V A
Limit ILIMIT(min)
Leading Edge
tLEB TJ = 25 °C 100 ns
Blanking Time
Current Limit
tIL(D) IC = (IC(skip) + IB)/2 100 ns
Delay
Thermal Shut-
TJ(SD) 130 137 145 °C 2
down Temperature
Thermal Shut-
TJ(SD)hyst 27 °C
down Hysteresis
Power-Up Reset
V 1.5 2.75 4 V
Threshold Voltage C(RESET)
OUTPUT
DPA423 TJ = 25 °C 1.30 1.50
ID = 300 mA TJ = 100 °C 2.00 2.30
DPA424 TJ = 25 °C 0.65 0.75
ON-State ID = 600 mA TJ = 100 °C 1.00 1.15
RDS(ON) Ω
Resistance DPA425 TJ = 25 °C 0.33 0.38
ID = 1.25 A TJ = 100 °C 0.50 0.58
DPA426 TJ = 25 °C 0.24 0.28
ID = 1.75 A TJ = 100 °C 0.37 0.43
DPA423 65
VX, VL = Floating;
OFF-State Drain VD = 150 V; DPA424 130
IDSS µA
Leakage Current TJ = 125 °C; DPA425 260
IC = (IC(skip) + IB)/2
DPA426 360
2-25
2-25
Rev. Q 05/06
DPA423-426
Conditions
See Figure 33
OUTPUT (cont.)
Breakdown VX, VL = Floating; TJ = 25 °C;
BVDSS 220 V
Voltage IC = (IC(skip) + IB)/2; See Note C
Rise Time tR Measured in a Typical Application 10 ns
Fall Time tF Measured in a Typical Application 10 ns
SUPPLY VOLTAGE CHARACTERISTICS
DRAIN Supply
See Note D 16 V
Voltage
Shunt Regulator
VC(SHUNT) IC = (IC(skip) + IB)/2: TJ = 25 °C 5.6 5.85 6.0 V
Voltage
Shunt Regulator
IC = (IC(skip) + IB)/2 ±50 PPM/°C
Temperature Drift
DPA423 1.9 2.3 2.7
Output
MOSFET Enabled DPA424 2.6 3.0 3.4
CONTROL ICD1
VL = 0 V; DPA425 3.7 4.3 4.8
Supply/Discharge fOSC = 400 kHz mA
DPA426 4.8 5.4 6
Current
Output MOSFET Disabled
ICD2 0.4 0.73 1.2
VL = 0 V; fOSC = 400 kHz
2 NOTES:
A. For specifications with negative values, a negative temperature coefficient corresponds to an increase in
magnitude with increasing temperature, and a positive temperature coefficient corresponds to a decrease in
magnitude with increasing temperature.
B. For externally adjusted current limit values, please refer to Figure 35 (Current Limit vs. External Current Limit
Resistance) in the Typical Performance Characteristics section.
C. Breakdown voltage may be checked against minimum BVDSS specification by ramping the DRAIN pin voltage up
to but not exceeding minimum BVDSS.
D. It is possible to start up and operate DPA-Switch at DRAIN voltages well below 16 V. However, the CONTROL
pin charging current is reduced, which affects startup time, auto-restart frequency, and auto-restart duty cycle.
Refer to Figure 45, the characteristic graph on CONTROL pin charge current (IC) vs. DRAIN voltage for low
voltage operation characteristics.
2-26
2-26
Rev. Q 05/06
DPA423-426
t2
t1
HV
90% 90%
DRAIN t
D= 1
VOLTAGE t2
10%
0V
PI-2039-033001
Figure 30. Duty Cycle Measurement.
120 1.4
PI-2880-060302
PI-2889-061302
tLEB (Blanking Time) +
tIL(D) (Current Limit Delay)
CONTROL Pin Current (mA)
DRAIN Current (Normalized)

100 1.2
1
80
0.8
60
0.6
40
Dynamic 1 0.4
= Temperature Range:
Impedance Slope
20 -40 °C to 125 °C
0.2
0
2
0
0 2 4 6 8 10 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
CONTROL Pin Voltage (V) Time (µs)
Figure 31. CONTROL Pin I-V Characteristic. Figure 32. Typical Drain Operation Current Envelope.
S1 470 Ω
0-200 kΩ
5W
5-50 V
40 V
L D
470 Ω CONTROL
C C DPA-Switch
S2
S4 F X S
0-15 V
S3
47 µF 0.1 µF
0-70 kΩ
NOTE: This test circuit is not applicable for current limit or output characteristic measurements.
PI-2860-050602
Figure 33. DPA-Switch General Test Circuit.
2-27
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Rev. Q 05/06
DPA423-426
BENCH TEST PRECAUTIONS FOR EVALUATION OF ELECTRICAL CHARACTERISTICS
The following precautions should be followed when testing while in this auto-restart mode, there is only a 12.5% chance
DPA-Switch by itself outside of a power supply. The schematic that the CONTROL pin oscillation will be in the correct state
shown in Figure 33 is suggested for laboratory testing of (drain active state) so that the continuous drain voltage waveform
DPA-Switch. may be observed. It is recommended that the VC power supply
be turned on first and the DRAIN pin power supply second if
When the DRAIN pin supply is turned on, the part will be in continuous drain voltage waveforms are to be observed. The
the auto-restart mode. The CONTROL pin voltage will be 12.5% chance of being in the correct state is due to the divide-
oscillating at a low frequency between 4.8 V and 5.8 V and by-8 counter. Temporarily shorting the CONTROL pin to the
the drain is turned on every eighth cycle of the CONTROL pin SOURCE pin will reset DPA-Switch, which then will come up
oscillation. If the CONTROL pin power supply is turned on in the correct state.
Typical Performance Characteristics

1.1
(Normalized to Internal Current Limit)
PI-2838-032202
1.0
0.9
0.8
Current Limit
0.7
0.6
0.5
0.4
0.3
0.2
0.1
2 -230 -180 -130

IX (µA)
-80 -30 0
Figure 34. Current Limit vs. EXTERNAL CURRENT LIMIT Pin Current.
1.1
(Normalized to Internal Current Limit)
PI-2839-032202
1.0
0.9
Maximum
0.8
Current Limit
0.7 Minimum
0.6
0.5
Typical
0.4
0.3
0.2
0.1
0 5 10 15 20 25 30 35
External Current Limit Resistor RIL (kΩ)
Figure 35. Current Limit vs. EXTERNAL CURRENT LIMIT Resistance.
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Rev. Q 05/06
DPA423-426
Typical Performance Characteristics (cont.)

1.2 1.2
PI-2866-051702
PI-2868-051502
1.0 1.0
(Normalized to 25 °C)
Output Frequency
0.8
Current Limit
0.8
0.6 0.6
0.4 0.4
0.2 0.2
0 0
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
Junction Temperature (°C) Junction Temperature (°C)
Figure 36. Frequency vs. Temperature. Figure 37. Internal Current Limit vs. Temperature.
1.2 1.2
PI-2872-051602
PI-2865-051702
1.0
Overvoltage Threshold
1.0
0.8 0.8
Current Limit
0.6 0.6
0.4 0.4
0.2
0.2 2
0
0 -50 -25 0 25 50 75 100 125 150
-50 -25 0 25 50 75 100 125 150
Junction Temperature (°C)
Figure 38. External Current Limit vs. Temperature with Figure 39. Overvoltage Threshold vs. Temperature.
RIL = 12 kΩ.
7.0 PI-2871-051502
1.2
PI-2867-051502
LINE-SENSE Pin Voltage (V)
6.0
Under-Voltage Threshold
1.0
5.0
0.8
4.0
0.6
3.0
0.4
2.0
0.2 1.0
0 0.0
-50 -25 0 25 50 75 100 125 150 -200 -150 -100 -50 0 50 100 150 200 250
Junction Temperature (°C) LINE-SENSE Pin Current (µA)
Figure 40. Undervoltage Threshold vs. Temperature. Figure 41. LINE-SENSE Pin Voltage vs. Current.
2-29
2-29
Rev. Q 05/06
DPA423-426

1.6 1.2
PI-2863-011904
PI-2869-051502
VX = 1.375 - IXx 843 kΩ
EXTERNAL CURRENT LIMIT
1.4 -200 µA ≤ IX ≤ -25 µA 1.0
CONTROL Pin Current

1.2
Pin Voltage (V)
0.8
1.0
0.8 0.6
0.6
0.4
0.4
0.2
0.2
0 0
-225 -175 -125 -75 -25
-250 -200 -150 -100 -50 0 -50 -25 0 25 50 75 100 125 150
EXTERNAL CURRENT LIMIT Pin Current (µA) Junction Temperature (°C)
Figure 42. External Current Limit Pin Voltage Figure 43. CONTROL Pin Current at Minimum
vs. Current Duty Cycle vs. Temperature.
1.2 5.0
PI-2841-051502
PI-2864-051702
VC = 5 V
4.5
Onset Threshold Current
1.0
Charging Current (mA)

4.0
3.5
CONTROL Pin
0.8
3.0
0.6 2.5
2.0
0.4 1.5
2 0.2
1.0
0.5
0 0.0
-50 -25 0 25 50 75 100 125 150 0 10 20 30 40 50 60
Junction Temperature (°C) DRAIN Voltage (V)
Figure 44. Max. Duty Cycle Reduction Onset Threshold Figure 45. IC vs. DRAIN Voltage.
Current vs. Temperature.
1.2 1.1
Remote OFF DRAIN Supply Current
PI-176B-033001
PI-2870-051502
1.0
Breakdown Voltage
0.8
0.6 1.0
0.4
0.2
0 0.9
-50 -20 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
Figure 46. Remote OFF DRAIN Supply Figure 47. Breakdown Voltage vs. Temperature.
Current vs. Temperature.
2-30
2-30
Rev. Q 05/06
DPA423-426

20 2.5
PI-2849-050302
PI-2850-011904
18 Scaling Factors:
DPA423 = 0.18 TCASE = 25 °C
16 DPA424 = 0.36 2
DPA425 = 0.72
Drain Current (A)
14 DPA426 = 1.00
On-resistance
12 1.5
10
8 1
TCASE = 100 °C
6
4 0.5
2
0 0
0 1 2 3 4 5 -50 -25 0 25 50 75 100 125 150
Drain Voltage (V) Temperature (°C)
Figure 48. Output Characteristics. Figure 49. On-Resistance vs. Temperature.
10000 2.5
PI-2877-061704
PI-2851-011904
Switching Loss (W) at 400 kHz

Scaling Factors:
DPA423 = 0.18
Data taken from a typical
DPA424 = 0.36 2 forward converter design.
DPA425 = 0.72
DPA426 = 1.00
Capacitance (pF)
1000
1.5
Scaling Factors:
1 DPA423 = 0.08
DPA424 = 0.20
100 DPA425 = 0.55
DPA426 = 1.00
0.5
2
10 0
0 20 40 60 80 100 120 140 160 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
DRAIN Voltage (V) In-Circuit Peak Drain Current Normalized to

Nominal Device Internal Current Limit
Figure 50. COSS vs. DRAIN Voltage.
Figure 51. Typical Switching Loss.
2-31
2-31
Rev. Q 05/06
DPA423-426
PART ORDERING INFORMATION

DPA-Switch Product Family
Series Number
Package Identifier
G Plastic Surface Mount DIP
(423, 424 & 425 only)
P Plastic DIP
R Plastic TO-263-7C (available only with TL option)
S S-PAK (available only with TL option)
Lead Finish
Blank Standard (Sn Pb) not available with S-PAK
N Pure Matte Tin (Pb-Free) (P & G packages and S-PAK)
Tape & Reel and Other Options
Blank Standard Configurations
Tape & Reel, (G package and S-PAK: 1000 min./mult.,
DPA 423 G N - TL TL
R package: 750 min./mult.)
2
Revision Notes Date
F 1) Final release data sheet. 6/02
G 2) Updated Figure 25 and text description. 9/02
H 1) Corrected missing text on page 9 and corrected Table 4. 4/03
2) Updated R package description.
3) Revised thermal impedances (θJA), DCMIN, VF, IF, and BVDSS.
4) Updated Figure 25 and description in text.
I 1) Corrected text errors on pp. 1, 7 and 20. 5/03
J 1) Figure 25 and description in text updated. 5/03
K 1) Added P and G packages. 1/04
L 1) Corrected Figure 3. 4/04
M 1) Added package information to Table 1. 12/04
2) Revised Figure 13.
3) Added lead-free ordering information.
N 1) Minor error corrections. 2/05
O 1) Added S-PAK. 7/05
P 1) Added notes to Table 6. 7/05
Q 1) Updated Figure 27 to best reflect current requirements for PoE. 5/06
2-32
2-32
Rev. Q 05/06
LNK302/304-306
LNK302/304-306
LinkSwitch-TN Family
®
Lowest Component Count, Energy-Efficient

Off-Line Switcher IC
Product Highlights
Cost Effective Linear/Cap Dropper Replacement
• Lowest cost and component count buck converter solution
• Fully integrated auto-restart for short-circuit and open FB BP
loop fault protection – saves external component costs + D S +

• LNK302 uses a simplified controller without auto-restart Wide Range LinkSwitch-TN DC
HV DC Input Output
for very low system cost
• 66 kHz operation with accurate current limit – allows low cost
off-the-shelf 1 mH inductor for up to 120 mA output current PI-3492-111903
• Tight tolerances and negligible temperature variation
Figure 1. Typical Buck Converter Application (See Application
• High breakdown voltage of 700 V provides excellent Examples Section for Other Circuit Configurations).
input surge withstand
• Frequency jittering dramatically reduces EMI (~10 dB)
– minimizes EMI filter cost OUTPUT CURRENT TABLE1
• High thermal shutdown temperature (+135 °C minimum) 230 VAC ±15% 85-265 VAC
PRODUCT4
Much Higher Performance over Discrete Buck and MDCM2 CCM3 MDCM2 CCM3
Passive Solutions
LNK302P or G 63 mA 80 mA 63 mA 80 mA
• Supports buck, buck-boost and flyback topologies
• System level thermal overload, output short-circuit and LNK304P or G 120 mA 170 mA 120 mA 170 mA
open control loop protection LNK305P or G 175 mA 280 mA 175 mA 280 mA
• Excellent line and load regulation even with typical
configuration
LNK306P or G 225 mA 360 mA 225 mA 360 mA 2
• High bandwidth provides fast turn-on with no overshoot Table 1. Output Current Table.
• Current limit operation rejects line ripple Notes:
1. Typical output current in a non-isolated buck converter. Output
• Universal input voltage range (85 VAC to 265 VAC) power capability depends on respective output voltage. See Key
• Built-in current limit and hysteretic thermal protection Applications Considerations Section for complete description of
• Higher efficiency than passive solutions assumptions, including fully discontinuous conduction mode (DCM)
operation.
• Higher power factor than capacitor-fed solutions 2. Mostly discontinuous conduction mode.
• Entirely manufacturable in SMD 3. Continuous conduction mode.
®
4. Packages: P: DIP-8B, G: SMD-8B. For lead-free package options,
EcoSmart – Extremely Energy-Efficient see Part Ordering Information.
• Consumes typically only 50/80 mW in self-powered buck
topology at 115/230 VAC input with no load (opto feedback)
LinkSwitch-TN devices integrate a 700 V power MOSFET,
• Consumes typically only 7/12 mW in flyback topology
oscillator, simple ON/OFF control scheme, a high-voltage
with external bias at 115/230 VAC input with no load
switched current source, frequency jittering, cycle-by-cycle
• Meets California Energy Commission (CEC), ENERGY
current limit and thermal shutdown circuitry onto a monolithic
STAR, and EU requirements
IC. The start-up and operating power are derived directly from
Applications the voltage on the DRAIN pin, eliminating the need for a bias
• Appliances and timers supply and associated circuitry in buck or flyback converters.
• LED drivers and industrial controls The fully integrated auto-restart circuit in the LNK304-306 safely
limits output power during fault conditions such as short-circuit
Description or open loop, reducing component count and system-level load
LinkSwitch-TN is specifically designed to replace all linear and protection cost. A local supply provided by the IC allows use
capacitor-fed (cap dropper) non-isolated power supplies in the of a non-safety graded optocoupler acting as a level shifter to
under 360 mA output current range at equal system cost while further enhance line and load regulation performance in buck
offering much higher performance and energy efficiency. and buck-boost converters, if required.
2-33
2-33
Rev. G 03/05
LNK302/304-306
BYPASS DRAIN
(BP) (D)
REGULATOR
5.8 V
BYPASS PIN
UNDER-VOLTAGE
+
5.8 V -
4.85 V CURRENT LIMIT
6.3 V COMPARATOR
- VI
LIMIT
JITTER
CLOCK
DCMAX
THERMAL
SHUTDOWN
OSCILLATOR
FEEDBACK
1.65 V -VT
(FB)
S Q
R Q
LEADING
EDGE
BLANKING
SOURCE
(S)
PI-3904-020805
Figure 2a. Functional Block Diagram (LNK302).
BYPASS DRAIN
(BP) (D)
REGULATOR
2
5.8 V
FAULT
PRESENT
AUTO-
RESTART BYPASS PIN
COUNTER UNDER-VOLTAGE
+
CLOCK
5.8 V -
RESET 4.85 V
CURRENT LIMIT
6.3 V COMPARATOR
- VI
LIMIT
JITTER
CLOCK
DCMAX
THERMAL
SHUTDOWN
OSCILLATOR
FEEDBACK
1.65 V -VT
(FB)
S Q
R Q
LEADING
EDGE
BLANKING
SOURCE
(S)
PI-2367-021105
Figure 2b. Functional Block Diagram (LNK304-306).
2-34
2-34
Rev. G 03/05
LNK302/304-306
Pin Functional Description The LinkSwitch-TN oscillator incorporates circuitry that

introduces a small amount of frequency jitter, typically 4 kHz
DRAIN (D) Pin: peak-to-peak, to minimize EMI emission. The modulation rate
Power MOSFET drain connection. Provides internal operating of the frequency jitter is set to 1 kHz to optimize EMI reduction
current for both start-up and steady-state operation. for both average and quasi-peak emissions. The frequency
jitter should be measured with the oscilloscope triggered at
BYPASS (BP) Pin: the falling edge of the DRAIN waveform. The waveform in
Connection point for a 0.1 µF external bypass capacitor for the Figure 4 illustrates the frequency jitter of the LinkSwitch-TN.
internally generated 5.8 V supply.
Feedback Input Circuit
FEEDBACK (FB) Pin: The feedback input circuit at the FB pin consists of a low
During normal operation, switching of the power MOSFET is impedance source follower output set at 1.65 V. When the current
controlled by this pin. MOSFET switching is terminated when delivered into this pin exceeds 49 µA, a low logic level (disable)
a current greater than 49 µA is delivered into this pin. is generated at the output of the feedback circuit. This output
is sampled at the beginning of each cycle on the rising edge of
SOURCE (S) Pin: the clock signal. If high, the power MOSFET is turned on for
This pin is the power MOSFET source connection. It is also the that cycle (enabled), otherwise the power MOSFET remains off
ground reference for the BYPASS and FEEDBACK pins. (disabled). Since the sampling is done only at the beginning of
each cycle, subsequent changes in the FB pin voltage or current
during the remainder of the cycle are ignored.
P Package (DIP-8B)
5.8 V Regulator and 6.3 V Shunt Voltage Clamp
G Package (SMD-8B)
The 5.8 V regulator charges the bypass capacitor connected to
the BYPASS pin to 5.8 V by drawing a current from the voltage
S 1 8 S on the DRAIN, whenever the MOSFET is off. The BYPASS
pin is the internal supply voltage node for the LinkSwitch-TN.
S 2 7 S
When the MOSFET is on, the LinkSwitch-TN runs off of the
BP 3 energy stored in the bypass capacitor. Extremely low power
consumption of the internal circuitry allows the LinkSwitch-TN
FB 4 5 D
to operate continuously from the current drawn from the DRAIN
pin. A bypass capacitor value of 0.1 µF is sufficient for both 2
high frequency decoupling and energy storage.
PI-3491-111903
In addition, there is a 6.3 V shunt regulator clamping the
Figure 3. Pin Configuration. BYPASS pin at 6.3 V when current is provided to the BYPASS
pin through an external resistor. This facilitates powering of
LinkSwitch-TN externally through a bias winding to decrease
LinkSwitch-TN the no-load consumption to about 50 mW.
Functional Description
BYPASS Pin Undervoltage
LinkSwitch-TN combines a high-voltage power MOSFET
The BYPASS pin undervoltage circuitry disables the power
switch with a power supply controller in one device. Unlike
MOSFET when the BYPASS pin voltage drops below 4.85 V.
conventional PWM (pulse width modulator) controllers,
Once the BYPASS pin voltage drops below 4.85 V, it must rise
LinkSwitch-TN uses a simple ON/OFF control to regulate the
back to 5.8 V to enable (turn-on) the power MOSFET.
output voltage. The LinkSwitch-TN controller consists of an
oscillator, feedback (sense and logic) circuit, 5.8 V regulator,
Over-Temperature Protection
BYPASS pin undervoltage circuit, over-temperature protection,
The thermal shutdown circuitry senses the die temperature.
frequency jittering, current limit circuit, leading edge blanking
The threshold is set at 142 °C typical with a 75 °C hysteresis.
and a 700 V power MOSFET. The LinkSwitch-TN incorporates
When the die temperature rises above this threshold (142 °C) the
additional circuitry for auto-restart.
power MOSFET is disabled and remains disabled until the die
temperature falls by 75 °C, at which point it is re-enabled.
Oscillator
The typical oscillator frequency is internally set to an average
Current Limit
of 66 kHz. Two signals are generated from the oscillator: the
The current limit circuit senses the current in the power MOSFET.
maximum duty cycle signal (DCMAX) and the clock signal that
When this current exceeds the internal threshold (ILIMIT), the
indicates the beginning of each cycle.
2-35
2-35
Rev. G 03/05
LNK302/304-306
600 12 V, 120 mA non-isolated power supply used in appliance
PI-3660-081303
control such as rice cookers, dishwashers or other white goods.
500
This circuit may also be applicable to other applications such
VDRAIN
400
as night-lights, LED drivers, electricity meters, and residential
heating controllers, where a non-isolated supply is acceptable.
300
The input stage comprises fusible resistor RF1, diodes D3 and
200 D4, capacitors C4 and C5, and inductor L2. Resistor RF1 is
a flame proof, fusible, wire wound resistor. It accomplishes
100
several functions: a) Inrush current limitation to safe levels for
0 rectifiers D3 and D4; b) Differential mode noise attenuation;
68 kHz c) Input fuse should any other component fail short-circuit
64 kHz (component fails safely open-circuit without emitting smoke,
fire or incandescent material).
0 20
The power processing stage is formed by the LinkSwitch-TN,
Time (µs)
free-wheeling diode D1, output choke L1, and the output
Figure 4. Frequency Jitter. capacitor C2. The LNK304 was selected such that the power
supply operates in the mostly discontinuous-mode (MDCM).
power MOSFET is turned off for the remainder of that cycle. Diode D1 is an ultra-fast diode with a reverse recovery time (trr)
The leading edge blanking circuit inhibits the current limit of approximately 75 ns, acceptable for MDCM operation. For
comparator for a short time (tLEB) after the power MOSFET continuous conduction mode (CCM) designs, a diode with a trr of
is turned on. This leading edge blanking time has been set so ≤35 ns is recommended. Inductor L1 is a standard off-the- shelf
that current spikes caused by capacitance and rectifier reverse inductor with appropriate RMS current rating (and acceptable
recovery time will not cause premature termination of the temperature rise). Capacitor C2 is the output filter capacitor;
switching pulse. its primary function is to limit the output voltage ripple. The
output voltage ripple is a stronger function of the ESR of the
Auto-Restart (LNK304-306 only) output capacitor than the value of the capacitor itself.
In the event of a fault condition such as output overload, output
short, or an open loop condition, LinkSwitch-TN enters into auto- To a first order, the forward voltage drops of D1 and D2 are
2 restart operation. An internal counter clocked by the oscillator identical. Therefore, the voltage across C3 tracks the output
gets reset every time the FB pin is pulled high. If the FB pin voltage. The voltage developed across C3 is sensed and regulated
is not pulled high for 50 ms, the power MOSFET switching is via the resistor divider R1 and R3 connected to U1ʼs FB pin.
disabled for 800 ms. The auto-restart alternately enables and The values of R1 and R3 are selected such that, at the desired
disables the switching of the power MOSFET until the fault output voltage, the voltage at the FB pin is 1.65 V.
condition is removed.
Regulation is maintained by skipping switching cycles. As the
Applications Example output voltage rises, the current into the FB pin will rise. If
this exceeds IFB then subsequent cycles will be skipped until the
A 1.44 W Universal Input Buck Converter current reduces below IFB. Thus, as the output load is reduced,
The circuit shown in Figure 5 is a typical implementation of a more cycles will be skipped and if the load increases, fewer
R1
13.0 kΩ
1%
R3 C3
RF1 2.05 kΩ 10 µF
8.2 Ω L2 D2
C1 1% 35 V 1N4005GP
2W 1 mH FB BP
100 nF 12 V,
D S L1 120 mA
D3 1 mH
1N4007 LinkSwitch-TN C2
85-265 C4 C5 280 mA R4
VAC 4.7 µF 4.7 µF LNK304 D1 100 µF 3.3 kΩ
D4 400 V 400 V UF4005 16 V
1N4007
RTN
PI-3757-112103
Figure 5. Universal Input, 12 V, 120 mA Constant Voltage Power Supply Using LinkSwitch-TN.
2-36
2-36
Rev. G 03/05
LNK302/304-306
LinkSwitch-TN
RF1 D3 L2
D FB
D2
R1
BP +
C1
AC C4 C5 S S R3 C3 L1
INPUT DC
OUTPUT
S S C2
D4 D1
Optimize hatched copper areas ( ) for heatsinking and EMI. PI-3750-121106
Figure 6. Recommended Printed Circuit Layout for LinkSwitch-TN in a Buck Converter Configuration.
cycles are skipped. To provide overload protection if no cycles LinkSwitch-TN Selection and
are skipped during a 50 ms period, LinkSwitch-TN will enter Selection Between MDCM and CCM Operation
auto-restart (LNK304-306), limiting the average output power
to approximately 6% of the maximum overload power. Due to Select the LinkSwitch-TN device, free-wheeling diode and
tracking errors between the output voltage and the voltage across output inductor that gives the lowest overall cost. In general,
C3 at light load or no load, a small preload may be required MDCM provides the lowest cost and highest efficiency converter.
(R4). For the design in Figure 5, if regulation to zero load is CCM designs require a larger inductor and ultra-fast (trr ≤35 ns)
required, then this value should be reduced to 2.4 kΩ. free-wheeling diode in all cases. It is lower cost to use a larger
LinkSwitch-TN in MDCM than a smaller LinkSwitch-TN in CCM
Key Application Considerations because of the additional external component costs of a CCM
design. However, if the highest output current is required, CCM
LinkSwitch-TN Design Considerations should be employed following the guidelines below.
Output Current Table

2
Topology Options
Data sheet maximum output current table (Table 1) represents
the maximum practical continuous output current for both LinkSwitch-TN can be used in all common topologies, with or
mostly discontinuous conduction mode (MDCM) and continuous without an optocoupler and reference to improve output voltage
conduction mode (CCM) of operation that can be delivered from tolerance and regulation. Table 2 provide a summary of these
a given LinkSwitch-TN device under the following assumed configurations. For more information see the Application
conditions: Note – LinkSwitch-TN Design Guide.
1) Buck converter topology. Component Selection

2) The minimum DC input voltage is ≥70 V. The value of
input capacitance should be large enough to meet this Referring to Figure 5, the following considerations may be
criterion. helpful in selecting components for a LinkSwitch-TN design.
3) For CCM operation a KRP* of 0.4.
4) Output voltage of 12 VDC. Free-wheeling Diode D1
5) Efficiency of 75%. Diode D1 should be an ultra-fast type. For MDCM, reverse
6) A catch/free-wheeling diode with trr ≤75 ns is used for recovery time trr ≤75 ns should be used at a temperature of
MDCM operation and for CCM operation, a diode with 70 °C or below. Slower diodes are not acceptable, as continuous
trr ≤35 ns is used. mode operation will always occur during startup, causing high
7) The part is board mounted with SOURCE pins soldered leading edge current spikes, terminating the switching cycle
to a sufficient area of copper to keep the SOURCE pin prematurely, and preventing the output from reaching regulation.
temperature at or below 100 °C. If the ambient temperature is above 70 °C then a diode with
*KRP is the ratio of ripple to peak inductor current. trr ≤35 ns should be used.
For CCM an ultra-fast diode with reverse recovery time

trr ≤35 ns should be used. A slower diode may cause excessive
2-37
2-37
Rev. G 03/05
LNK302/304-306
TOPOLOGY BASIC CIRCUIT SCHEMATIC KEY FEATURES

High-Side 1. Output referenced to input
Buck – 2. Positive output (VO) with respect to -VIN
Direct 3. Step down – VO < VIN
FB BP
Feedback 4. Low cost direct feedback (±10% typ.)
+ D S +
LinkSwitch-TN
VIN VO
PI-3751-121003
High-Side 1. Output referenced to input

Buck – 2. Positive output (VO) with respect to -VIN
FB BP
Optocoupler 3. Step down – VO < VIN
Feedback + D S + 4. Optocoupler feedback
LinkSwitch-TN - Accuracy only limited by reference
VIN VO choice
- Low cost non-safety rated opto
- No preload required
PI-3752-121003 5. Minimum no-load consumption
Low-Side + +
Buck –
Optocoupler LinkSwitch-TN
Feedback VIN VO
BP FB
1. Output referenced to input
2. Negative output (VO) with respect to +VIN
S D
PI-3753-111903 3. Step down – VO < VIN
Low-Side 4. Optocoupler feedback
+ - Accuracy only limited by reference
Buck – IO
2 Constant LinkSwitch-TN
choice
Current LED VIN VF +
Driver - No preload required
- Ideal for driving LEDs
BP FB
S D
VF PI-3754-112103
R=
IO
High-Side
Buck Boost –
Direct
Feedback FB BP
+ D S
LinkSwitch-TN 1. Output referenced to input
VIN VO
2. Negative output (VO) with respect to +VIN
+
PI-3755-121003 3. Step up/down – VO > VIN or VO < VIN

4. Low cost direct feedback (±10% typ.)
High-Side 5. Fail-safe – output is not subjected to input
2V
Buck Boost – 300 Ω RSENSE =
IO voltage if the internal MOSFET fails
2 kΩ
Constant FB BP RSENSE IO 6. Ideal for driving LEDs – better accuracy
Current LED D S and temperature stability than Low-side
+
Driver LinkSwitch-TN
Buck constant current LED driver
VIN 10 µF 100 nF
50 V
PI-3779-120803
Table 2. Common Circuit Configurations Using LinkSwitch-TN. (continued on next page)
2-38
2-38
Rev. G 03/05
LNK302/304-306

Low-Side 1. Output referenced to input
Buck Boost – 2. Positive output (VO) with respect to +VIN
Optocoupler + 3. Step up/down – VO > VIN or VO < VIN
Feedback 4. Optocoupler feedback
LinkSwitch-TN
VIN VO
- Accuracy only limited by reference
choice
BP FB + - No preload required
S D
PI-3756-111903 5. Fail-safe – output is not subjected to input
voltage if the internal MOSFET fails
Table 2 (cont). Common Circuit Configurations Using LinkSwitch-TN.
leading edge current spikes, terminating the switching cycle Feedback Capacitor C3
prematurely and preventing full power delivery. Capacitor C3 can be a low cost general purpose capacitor. It
provides a “sample and hold” function, charging to the output
Fast and slow diodes should never be used as the large reverse voltage during the off time of LinkSwitch-TN. Its value should
recovery currents can cause excessive power dissipation in the be 10 µF to 22 µF; smaller values cause poorer regulation at
diode and/or exceed the maximum drain current specification light load conditions.
of LinkSwitch-TN.
Preload Resistor R4
Feedback Diode D2 In high-side, direct feedback designs where the minimum load
Diode D2 can be a low-cost slow diode such as the 1N400X is <3 mA, a preload resistor is required to maintain output
series, however it should be specified as a glass passivated type regulation. This ensures sufficient inductor energy to pull the
to guarantee a specified reverse recovery time. To a first order, inductor side of the feedback capacitor C3 to input return via
the forward drops of D1 and D2 should match. D2. The value of R4 should be selected to give a minimum
output load of 3 mA.
Inductor L1
Choose any standard off-the-shelf inductor that meets the In designs with an optocoupler the Zener or reference bias
2
design requirements. A “drum” or “dog bone” “I” core inductor current provides a 1 mA to 2 mA minimum load, preventing
is recommended with a single ferrite element due to to its “pulse bunching” and increased output ripple at zero load.
low cost and very low audible noise properties. The typical
inductance value and RMS current rating can be obtained from LinkSwitch-TN Layout Considerations
the LinkSwitch-TN design spreadsheet available within the
PI Expert design suite from Power Integrations. Choose L1 In the buck or buck-boost converter configuration, since the
greater than or equal to the typical calculated inductance with SOURCE pins in LinkSwitch-TN are switching nodes, the copper
RMS current rating greater than or equal to calculated RMS area connected to SOURCE should be minimized to minimize
inductor current. EMI within the thermal constraints of the design.
Capacitor C2 In the boost configuration, since the SOURCE pins are tied
The primary function of capacitor C2 is to smooth the inductor to DC return, the copper area connected to SOURCE can be
current. The actual output ripple voltage is a function of this maximized to improve heatsinking.
capacitorʼs ESR. To a first order, the ESR of this capacitor
should not exceed the rated ripple voltage divided by the typical The loop formed between the LinkSwitch-TN, inductor (L1),
current limit of the chosen LinkSwitch-TN. free-wheeling diode (D1), and output capacitor (C2) should
be kept as small as possible. The BYPASS pin capacitor
Feedback Resistors R1 and R3 C1 (Figure 6) should be located physically close to the
The values of the resistors in the resistor divider formed by SOURCE (S) and BYPASS (BP) pins. To minimize direct
R1 and R3 are selected to maintain 1.65 V at the FB pin. It is coupling from switching nodes, the LinkSwitch-TN should be
recommended that R3 be chosen as a standard 1% resistor of placed away from AC input lines. It may be advantageous to
2 kΩ. This ensures good noise immunity by biasing the feedback place capacitors C4 and C5 in-between LinkSwitch-TN and the
network with a current of approximately 0.8 mA. AC input. The second rectifier diode D4 is optional, but may
2-39
2-39
Rev. G 03/05
LNK302/304-306
be included for better EMI performance and higher line surge 4) Thermal check – at maximum output power, minimum
withstand capability. input voltage and maximum ambient temperature, verify
that the LinkSwitch-TN SOURCE pin temperature is
Quick Design Checklist 100 °C or below. This figure ensures adequate margin due
to variations in RDS(ON) from part to part. A battery powered
As with any power supply design, all LinkSwitch-TN designs thermocouple meter is recommended to make measurements
should be verified for proper functionality on the bench. The when the SOURCE pins are a switching node. Alternatively,
following minimum tests are recommended: the ambient temperature may be raised to indicate margin
to thermal shutdown.
1) Adequate DC rail voltage – check that the minimum DC
input voltage does not fall below 70 VDC at maximum load, In a LinkSwitch-TN design using a buck or buck boost converter
minimum input voltage. topology, the SOURCE pin is a switching node. Oscilloscope
2) Correct Diode Selection – UF400x series diodes are measurements should therefore be made with probe grounded
recommended only for designs that operate in MDCM at to a DC voltage, such as primary return or DC input rail, and
an ambient of 70 °C or below. For designs operating in not to the SOURCE pins. The power supply input must always
continuous conduction mode (CCM) and/or higher ambients, be supplied from an isolated source (e.g. via an isolation
then a diode with a reverse recovery time of 35 ns or better, transformer).
such as the BYV26C, is recommended.
3) Maximum drain current – verify that the peak drain current Design Tools
is below the data sheet peak drain specification under
worst-case conditions of highest line voltage, maximum Up-to-date information on design tools is available at the Power
overload (just prior to auto-restart) and highest ambient Integrations website: www.powerint.com.
temperature.
2-40
2-40
Rev. G 03/05
LNK302/304-306

DRAIN Voltage .................................................. -0.3 V to 700 V Notes:
Peak DRAIN Current (LNK302).................200 mA (375 mA)(2) 1. All voltages referenced to SOURCE, TA = 25 °C.
Peak DRAIN Current (LNK304).................400 mA (750 mA)(2) 2. The higher peak DRAIN current is allowed if the DRAIN
Peak DRAIN Current (LNK305).................800 mA (1500 mA)(2) to SOURCE voltage does not exceed 400 V.
Peak DRAIN Current (LNK306).................1400 mA (2600 mA)(2) 3. Normally limited by internal circuitry.
FEEDBACK Voltage .........................................-0.3 V to 9 V 4. 1/16 in. from case for 5 seconds.
FEEDBACK Current.............................................100 mA 5. Maximum ratings specified may be applied, one at a time,
BYPASS Voltage ..........................................-0.3 V to 9 V without causing permanent damage to the product.
Storage Temperature .......................................... -65 °C to 150 °C Exposure to Absolute Maximum Rating conditions for
Operating Junction Temperature(3) ..................... -40 °C to 150 °C extended periods of time may affect product reliability.
Lead Temperature(4) ........................................................260 °C
THERMAL IMPEDANCE
(θJA) ........................... 70 °C/W(2); 60 °C/W(3) 1. Measured on pin 2 (SOURCE) close to plastic interface.
(θJC)(1) ............................................... 11 °C/W 2. Soldered to 0.36 sq. in. (232 mm2), 2 oz. (610 g/m2) copper clad.
3. Soldered to 1 sq. in. (645 mm2), 2 oz. (610 g/m2) copper clad.
Conditions
See Figure 7
CONTROL FUNCTIONS
Output Average 62 66 70
fOSC TJ = 25 °C kHz
Frequency Peak-Peak Jitter 4
Maximum Duty 2
DCMAX S2 Open 66 69 72 %
Cycle
FEEDBACK Pin
Turnoff Threshold IFB TJ = 25 °C 30 49 68 µA
Current
FEEDBACK Pin
Voltage at Turnoff VFB 1.54 1.65 1.76 V
Threshold
VFB ≥2 V
IS1 (MOSFET Not Switching) 160 220 µA
See Note A
DRAIN Supply FEEDBACK LNK302/304 200 260
Current Open
IS2 (MOSFET LNK305 220 280 µA
Switching)
See Notes A, B LNK306 250 310
2-41
2-41
Rev. G 03/05
LNK302/304-306
Conditions
See Figure 7
VBP = 0 V LNK302/304 -5.5 -3.3 -1.8
ICH1
TJ = 25 °C LNK305/306 -7.5 -4.6 -2.5
BYPASS Pin
mA
Charge Current VBP = 4 V LNK302/304 -3.8 -2.3 -1.0
ICH2
TJ = 25 °C LNK305/306 -4.5 -3.3 -1.5
BYPASS Pin
VBP 5.55 5.8 6.10 V
Voltage
BYPASS Pin
VBPH 0.8 0.95 1.2 V
Voltage Hysteresis
BYPASS Pin
IBPSC See Note D 68 µA
Supply Current
CIRCUIT PROTECTION
di/dt = 55 mA/µs
126 136 146
TJ = 25 °C
LNK302
di/dt = 250 mA/µs
145 165 185
TJ = 25 °C
di/dt = 65 mA/µs
240 257 275
2 TJ = 25 °C
LNK304
di/dt = 415 mA/µs
271 308 345
ILIMIT (See TJ = 25 °C
Current Limit Note E)
mA
di/dt = 75 mA/µs
350 375 401
TJ = 25 °C
LNK305
di/dt = 500 mA/µs
396 450 504
TJ = 25 °C
di/dt = 95 mA/µs
450 482 515
TJ = 25 °C
LNK306
di/dt = 610 mA/µs
508 578 647
TJ = 25 °C
LNK302/304 280 360 475

Minimum On Time tON(MIN) LNK305 360 460 610 ns
LNK306 400 500 675
2-42
2-42
Rev. G 03/05
LNK302/304-306
Conditions
See Figure 7
CIRCUIT PROTECTION (cont.)
Leading Edge TJ = 25 °C
tLEB 170 215 ns
Blanking Time See Note F
Thermal Shutdown
TSD 135 142 150 °C
Temperature
Thermal Shutdown
TSHD See Note G 75 °C
Hysteresis
OUTPUT
LNK302 TJ = 25 °C 48 55.2
ID = 13 mA TJ = 100 °C 76 88.4
LNK304 TJ = 25 °C 24 27.6
ON-State ID = 25 mA TJ = 100 °C 38 44.2
RDS(ON) Ω
Resistance LNK305 TJ = 25 °C 12 13.8
ID = 35 mA TJ = 100 °C 19 22.1
LNK306 TJ = 25 °C 7 8.1
ID = 45 mA TJ = 100 °C 11 12.9
LNK302/304 50
VBP = 6.2 V, VFB ≥2 V,
OFF-State Drain
Leakage Current
IDSS VDS = 560 V,
TJ = 25 °C
LNK305 70 µA 2
LNK306 90
VBP = 6.2 V, VFB ≥2 V,
Breakdown Voltage BVDSS
TJ = 25 °C
700 V
Rise Time tR Measured in a Typical Buck 50 ns

Fall Time tF Converter Application 50 ns
DRAIN Supply
50 V
Voltage
Output Enable
tEN See Figure 9 10 µs
Delay
Output Disable
tDST 0.5 µs
Setup Time
Auto-Restart TJ = 25 °C LNK302 Not Applicable
tAR ms
ON-Time See Note H LNK304-306 50
Auto-Restart LNK302 Not Applicable

DCAR %
Duty Cycle LNK304-306 6
2-43
2-43
Rev. G 03/05
LNK302/304-306
NOTES:
A. Total current consumption is the sum of IS1 and IDSS when FEEDBACK pin voltage is ≥2 V (MOSFET not
switching) and the sum of IS2 and IDSS when FEEDBACK pin is shorted to SOURCE (MOSFET switching).
B Since the output MOSFET is switching, it is difficult to isolate the switching current from the supply current at the
DRAIN. An alternative is to measure the BYPASS pin current at 6 V.
C. See Typical Performance Characteristics section Figure 14 for BYPASS pin start-up charging waveform.
D. This current is only intended to supply an optional optocoupler connected between the BYPASS and FEEDBACK
pins and not any other external circuitry.
E. For current limit at other di/dt values, refer to Figure 13.
F. This parameter is guaranteed by design.
G. This parameter is derived from characterization.
H. Auto-restart on time has the same temperature characteristics as the oscillator (inversely proportional to
frequency).
470 Ω
5W 470 kΩ
D FB
S1 S2
2
BP
50 V 50 V
S S 0.1 µF
S S
PI-3490-060204
Figure 7. LinkSwitch-TN General Test Circuit.
DCMAX
(internal signal)
tP
FB
tEN
VDRAIN
1
tP =
fOSC
PI-3707-112503
Figure 8. LinkSwitch-TN Duty Cycle Measurement. Figure 9. LinkSwitch-TN Output Enable Timing.
2-44
2-44
Rev. G 03/05
LNK302/304-306
1.1 1.2
PI-2680-012301
PI-2213-012301
1.0
Breakdown Voltage
Output Frequency
0.8
1.0 0.6
0.4
0.2
0.9 0
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125
Figure 10. Breakdown vs. Temperature. Figure 11. Frequency vs. Temperature.
1.4 1.4
PI-3710-071204
PI-3709-111203
1.2 Normalized Current Limit 1.2

1.0 1.0
Current Limit
0.8 0.8
Normalized
Normalized di/dt Normalized Current
0.6 di/dt = 1 0.6 di/dt = 1 Limit = 1
di/dt = 6
2
LNK302 55 mA/µs 136 mA
0.4 0.4 LNK304 65 mA/µs 257 mA
0.2 0.2
0 0
-50 0 50 100 150 1 2 3 4 5 6
Temperature (°C) Normalized di/dt
Figure 12. Current Limit vs. Temperature at Figure 13. Current Limit vs. di/dt.
Normalized di/dt.
7 400
PI-2240-012301
PI-3661-071404
6 350
BYPASS Pin Voltage (V)
25 °C
DRAIN Current (mA)
5 300
100 °C
4 250
3 200
2 150
Scaling Factors:
LNK302 0.5
1 100 LNK304 1.0
LNK305 2.0
0 50 LNK306 3.4
0
0 0.2 0.4 0.6 0.8 1.0 0 2 4 6 8 10 12 14 16 18 20
Time (ms) DRAIN Voltage (V)
Figure 14. BYPASS Pin Start-up Waveform. Figure 15. Output Characteristics.
2-45
2-45
Rev. G 03/05
LNK302/304-306
1000
PI-3711-071404
Drain Capacitance (pF)
100
Scaling Factors:
LNK302 0.5
LNK304 1.0
LNK305 2.0
LNK306 3.4
10
1
0 100 200 300 400 500 600
Drain Voltage (V)
Figure 16. COSS vs. Drain Voltage.

LinkSwitch Product Family
TN Series Number
Package Identifier
2 P
Lead Finish
Plastic DIP
Blank Standard (Sn Pb)

LNK 304 G N - TL TL Tape & Reel, 1 k pcs minimum, G Package only
Revision Notes Date

C 1) Released Final Data Sheet. 3/03
D 1) Corrected Minimum On Time. 1/04
E 1) Added LNK302. 8/04
F 1) Added lead-free ordering information. 12/04
G 1) Minor error corrections. 3/05
2) Renamed Feedback Pin Voltage parameter to Feedback Pin Voltage at Turnoff Threshold and
removed condition.
2-46
2-46
Rev. G 03/05
LNK362-364
LNK362-364
®
LinkSwitch-XT Family
Energy Efficient, Low Power
Off-Line Switcher IC
Product Highlights
Optimized for Lowest System Cost +
DC
+
• Proprietary IC trimming and transformer construction Output
techniques enable Clampless™ designs with LNK362

for lower system cost, component count and higher LinkSwitch-XT
Wide Range
efficiency HV DC Input D
LNK362
• Fully integrated auto-restart for short circuit and FB
open loop protection BP
• Self-biased supply – saves transformer auxiliary winding S
and associated bias supply components

• Frequency jittering greatly reduces EMI a) Clampless flyback converter with LNK362 PI-4086-081005
• Meets HV creepage requirements between DRAIN and
all other pins both on the PCB and at the package
+ +
• Lowest component count switcher solution DC
Output
Features Superior to Linear/RCC

• Accurate hysteretic thermal shutdown protection – LinkSwitch-XT
automatic recovery improves field reliability Wide Range
HV DC Input D
LNK363-364
• Universal input range allows worldwide operation FB
• Simple ON/OFF control, no loop compensation needed BP
• Eliminates bias winding – simpler, lower cost S
transformer
• Very low component count – higher reliability and single b) Flyback converter with LNK363/4 PI-4061-081005
2
side printed circuit board
• Auto-restart reduces delivered power by 95% during Figure 1. Typical Application with LinkSwitch-XT.
short circuit and open loop fault conditions
• High bandwidth provides fast turn-on with no overshoot OUTPUT POWER TABLE(4)
and excellent transient load response 230 VAC ±15% 85-265 VAC
®
EcoSmart – Extremely Energy-Efficient PRODUCT(3) Open Open
Adapter(1) Adapter(1)
• Easily meets all global energy efficiency regulations with Frame(2) Frame(2)
no added components LNK362P or G 2.8 W 2.8 W 2.6 W 2.6 W
• No-load consumption <300 mW without bias winding at
LNK363P or G 5W 7.5 W 3.7 W 4.7 W
265 VAC input (<50 mW with bias winding)
• ON/OFF control provides constant efficiency to very LNK364P or G 5.5 W 9W 4W 6W
light loads – ideal for mandatory CEC regulations
Table 1. Output Power Table.
Applications Notes:
1. Minimum continuous power in a typical non-ventilated enclosed
• Chargers/adapters for cell/cordless phones, PDAs, digital adapter measured at 50 °C ambient.
cameras, MP3/portable audio players, and shavers 2. Minimum practical continuous power in an open frame design
• Supplies for appliances, industrial systems, and metering with adequate heat sinking, measured at 50 °C ambient.
3. Packages: P: DIP-8B, G: SMD-8B. Please see Part Ordering
Information.
Description 4. See Key Application Considerations section for complete description
of assumptions.
LinkSwitch-XT incorporates a 700 V power MOSFET, oscillator,
simple ON/OFF control scheme, a high-voltage switched current and operating power are derived directly from the DRAIN
source, frequency jittering, cycle-by-cycle current limit and pin, eliminating the need for a bias winding and associated
thermal shutdown circuitry onto a monolithic IC. The startup circuitry.
2-47
2-47
Rev. C 12/05
LNK362-364
BYPASS DRAIN
(BP) (D)
REGULATOR
5.8 V
FAULT
PRESENT
AUTO-
RESTART BYPASS PIN
COUNTER UNDER-VOLTAGE
+
CLOCK
5.8 V -
RESET 4.8 V
CURRENT LIMIT
6.3 V COMPARATOR
- VI
LIMIT
JITTER
CLOCK
DCMAX
THERMAL
SHUTDOWN
OSCILLATOR
FEEDBACK
VFB -VTH
(FB)
S Q
R Q
LEADING
EDGE
BLANKING
SOURCE
(S)
2 PI-4232-110205
Pin Functional Description

DRAIN (D) Pin: P Package (DIP-8B)
Power MOSFET drain connection. Provides internal operating G Package (SMD-8B)
current for both startup and steady-state operation.
S 1 8 S
BYPASS (BP) Pin:
Connection point for a 0.1 µF external bypass capacitor for the S 2 7 S
internally generated 5.8 V supply. If an external bias winding is
BP 3
used, the current into the BP pin must not exceed 1 mA.
FB 4 5 D
FEEDBACK (FB) Pin:
During normal operation, switching of the power MOSFET is
controlled by this pin. MOSFET switching is disabled when a
current greater than 49 µA is delivered into this pin. PI-3491-111903
Figure 3. Pin Configuration.

SOURCE (S) Pin:
This pin is the power MOSFET source connection. It is also the
ground reference for the BYPASS and FEEDBACK pins.
48
2-48
2-48
Rev. C 12/05
LNK362-364
pin through an external resistor. This facilitates powering of

LinkSwitch-XT the device externally through a bias winding to decrease the
Functional Description no-load consumption to less than 50 mW.
LinkSwitch-XT combines a high-voltage power MOSFET
switch with a power supply controller in one device. Unlike BYPASS Pin Undervoltage
conventional PWM (pulse width modulator) controllers, a The BYPASS pin undervoltage circuitry disables the power
simple ON/OFF control regulates the output voltage. The MOSFET when the BYPASS pin voltage drops below 4.8 V.
controller consists of an oscillator, feedback (sense and logic) Once the BYPASS pin voltage drops below 4.8 V, it must rise
circuit, 5.8 V regulator, BYPASS pin undervoltage circuit, back to 5.8 V to enable (turn-on) the power MOSFET.
over-temperature protection, frequency jittering, current limit
circuit, and leading edge blanking integrated with a 700 V Over-Temperature Protection
power MOSFET. The LinkSwitch-XT incorporates additional The thermal shutdown circuitry senses the die temperature.
circuitry for auto-restart. The threshold is set at 142 °C typical with a 75 °C hysteresis.
When the die temperature rises above this threshold (142 °C) the
Oscillator power MOSFET is disabled and remains disabled until the die
The typical oscillator frequency is internally set to an average temperature falls by 75 °C, at which point it is re-enabled.
of 132 kHz. Two signals are generated from the oscillator: the
maximum duty cycle signal (DCMAX) and the clock signal that Current Limit
indicates the beginning of each cycle. The current limit circuit senses the current in the power MOSFET.
The oscillator incorporates circuitry that introduces a small power MOSFET is turned off for the remainder of that cycle.
amount of frequency jitter, typically 9 kHz peak-to-peak, The leading edge blanking circuit inhibits the current limit
to minimize EMI emission. The modulation rate of the comparator for a short time (tLEB) after the power MOSFET
frequency jitter is set to 1.5 kHz to optimize EMI reduction is turned on. This leading edge blanking time has been set so
for both average and quasi-peak emissions. The frequency that current spikes caused by capacitance and rectifier reverse
jitter should be measured with the oscilloscope triggered at recovery time will not cause premature termination of the
the falling edge of the DRAIN waveform. The waveform in switching pulse.
Figure 4 illustrates the frequency jitter.
Auto-Restart
In the event of a fault condition such as output overload, output
Feedback Input Circuit
The feedback input circuit at the FB pin consists of a low short circuit, or an open loop condition, LinkSwitch-XT enters 2
impedance source follower output set at 1.65 V for LNK362 into auto-restart operation. An internal counter clocked by the
and 1.63 V for LNK363/364. When the current delivered into oscillator gets reset every time the FB pin is pulled high. If the
this pin exceeds 49 µA, a low logic level (disable) is generated FB pin is not pulled high for approximately 40 ms, the power
at the output of the feedback circuit. This output is sampled MOSFET switching is disabled for 800 ms. The auto-restart
at the beginning of each cycle on the rising edge of the clock alternately enables and disables the switching of the power
signal. If high, the power MOSFET is turned on for that cycle MOSFET until the fault condition is removed.
(enabled), otherwise the power MOSFET remains off (disabled). 600
PI-4047-110205
Since the sampling is done only at the beginning of each cycle,
subsequent changes in the FB pin voltage or current during the 500 V
remainder of the cycle are ignored. DRAIN
400
300
The 5.8 V regulator charges the bypass capacitor connected to the
BYPASS pin to 5.8 V by drawing a current from the voltage on 200
the DRAIN, whenever the MOSFET is off. The BYPASS pin is
the internal supply voltage node. When the MOSFET is on, the 100
LinkSwitch-XT runs off of the energy stored in the bypass capacitor.
Extremely low power consumption of the internal circuitry allows 0
136.5 kHz
the device to operate continuously from the current drawn from 127.5 kHz
the DRAIN pin. A bypass capacitor value of 0.1 µF is sufficient
for both high frequency decoupling and energy storage.
0 5 10
In addition, there is a 6.3 V shunt regulator clamping the Time (µs)
BYPASS pin at 6.3 V when current is provided to the BYPASS Figure 4. Frequency Jitter.
2-49
2-49
Rev. C 12/05
LNK362-364
CY1
100 pF
250 VAC
C4
L1 T1 330 µF 6.2 V,
1 mH EE16 9 16 V 322 mA
4
5 J3
D5
1N4934
3 8
NC NC J4
RF1 VR1
D1 D2 R1 BZX79-
8.2 Ω 1N4005 1N4005 3.9 k
J1 2.5 W B5V1
1/8 W 5.1 V, 2%
R2
390 Ω
85-265 C1 C2 1/8 W
VRMS 3.3 µF 3.3 µF
400 V 400 V
R3
1k
J2 U2 1/8 W
D PC817A
LinkSwitch-XT FB
U1 BP
LNK362P
D3 D4 S
C3
1N4005 1N4005 L2 100 nF
1 mH 50 V
PI-4162-110205
Figure 5. 2 W Universal Input CV Adapter Using LNK362.
Applications Example The rectified and filtered input voltage is applied to the primary
winding of T1. The other side of the primary is driven by the
A 2 W CV Adapter integrated MOSFET in U1. No primary clamp is required as the
2 The schematic shown in Figure 5 is a typical implementation of
a universal input, 6.2 V ±7%, 322 mA adapter using LNK362.
low value and tight tolerance of the LNK362 internal current
limit allows the transformer primary winding capacitance to
This circuit makes use of the Clampless technique to eliminate the provide adequate clamping of the leakage inductance drain
primary clamp components and reduce the cost and complexity voltage spike.
of the circuit.
The secondary of the flyback transformer T1 is rectified by D5,
The EcoSmart features built into the LinkSwitch-XT family a low cost, fast recovery diode, and filtered by C4, a low ESR
allow this design to easily meet all current and proposed capacitor. The combined voltage drop across VR1, R2 and the
energy efficiency standards, including the mandatory California LED of U2 determines the output voltage. When the output
Energy Commission (CEC) requirement for average operating voltage exceeds this level, current will flow through the LED
efficiency. of U2. As the LED current increases, the current fed into the
FEEDBACK pin of U1 increases until the turnoff threshold
The AC input is rectified by D1 to D4 and filtered by the bulk current (~49 µA) is reached, disabling further switching cycles
storage capacitors C1 and C2. Resistor RF1 is a flameproof, of U1. At full load, almost all switching cycles will be enabled,
fusible, wire wound type and functions as a fuse, inrush current and at very light loads, almost all the switching cycles will be
limiter and, together with the π filter formed by C1, C2, L1 disabled, giving a low effective frequency and providing high
and L2, differential mode noise attenuator. Resistor R1 damps light load efficiency and low no-load consumption.
ringing caused by L1 and L2.
Resistor R3 provides 1 mA through VR1 to bias the Zener
This simple input stage, together with the frequency jittering of closer to its test current. Resistor R2 allows the output voltage
LinkSwitch-XT, a low value Y1 capacitor and PIʼs E-Shield™ to be adjusted to compensate for designs where the value of the
windings within T1, allow the design to meet both conducted Zener may not be ideal, as they are only available in discrete
and radiated EMI limits with >10 dBµV margin. The low value voltage ratings. For higher output accuracy, the Zener may be
of CY1 is important to meet the requirement for a very low replaced with a reference IC such as the TL431.
touch current (the line frequency current that flows through
CY1) often specified for adapters, in this case <10 µA.
50
2-50
2-50
Rev. C 12/05
LNK362-364
The LinkSwitch-XT is completely self-powered from the DRAIN The following requirements are recommended for a universal
pin, requiring only a small ceramic capacitor C3 connected to input or 230 VAC only Clampless design:
the BYPASS pin. No auxiliary winding on the transformer is
required. 1. A Clampless design should only be used for PO ≤ 2.5 W,
using the LNK362† and a VOR** ≤ 90 V.
Key Application Considerations 2. For designs where PO ≤ 2 W, a two-layer primary should be
used to ensure adequate primary intra-winding capacitance
LinkSwitch-XT Design Considerations in the range of 25 pF to 50 pF.
3. For designs where 2 < PO ≤ 2.5 W, a bias winding should be
Output Power Table added to the transformer using a standard recovery rectifier
The data sheet maximum output power table (Table 1) represents diode to act as a clamp. This bias winding may also be used
the maximum practical continuous output power level that can to externally power the device by connecting a resistor from
be obtained under the following assumed conditions: the bias-winding capacitor to the BYPASS pin. This inhibits
the internal high-voltage current source, reducing device
1. The minimum DC input voltage is 90 V or higher for 85 VAC dissipation and no-load consumption.
input, or 240 V or higher for 230 VAC input or 115 VAC 4. For designs where PO > 2.5 W Clampless designs are not
with a voltage doubler. The value of the input capacitance practical and an external RCD or Zener clamp should be
should be large enough to meet these criteria for AC input used.
designs. 5. Ensure that worst-case high line, peak drain voltage is below
2. Secondary output of 6 V with a fast PN rectifier diode. the BVDSS specification of the internal MOSFET and ideally
3. Assumed efficiency of 70%. ≤ 650 V to allow margin for design variation.
4. Voltage only output (no secondary-side constant current
circuit). †For 110 VAC only input designs it may be possible to extend
5. Discontinuous mode operation (KP >1). the power range of Clampless designs to include the LNK363.
6. A primary clamp (RCD or Zener) is used. However, the increased leakage ringing may degrade EMI
7. The part is board mounted with SOURCE pins soldered performance.
to a sufficient area of copper to keep the SOURCE pin
temperature at or below 100 °C. **VOR is the secondary output plus output diode forward voltage
8. Ambient temperature of 50 °C for open frame designs drop that is reflected to the primary via the turns ratio of the
and an internal enclosure temperature of 60 °C for adapter transformer during the diode conduction time. The VOR adds
designs. to the DC bus voltage and the leakage spike to determine the 2
peak drain voltage.
Below a value of 1, KP is the ratio of ripple to peak primary
current. Above a value of 1, KP is the ratio of primary MOSFET Audible Noise
OFF time to the secondary diode conduction time. Due to The cycle skipping mode of operation used in LinkSwitch-XT
the flux density requirements described below, typically a can generate audio frequency components in the transformer.
LinkSwitch-XT design will be discontinuous, which also has To limit this audible noise generation, the transformer should
the benefits of allowing lower cost fast (instead of ultra-fast) be designed such that the peak core flux density is below
output diodes and reducing EMI. 1500 Gauss (150 mT). Following this guideline and using the
standard transformer production technique of dip varnishing
Clampless Designs practically eliminates audible noise. Vacuum impregnation
Clampless designs rely solely on the drain node capacitance of the transformer should not be used due to the high primary
to limit the leakage inductance induced peak drain-to-source capacitance and increased losses that result. Higher flux densities
voltage. Therefore, the maximum AC input line voltage, the are possible, however careful evaluation of the audible noise
value of VOR, the leakage inductance energy, a function of performance should be made using production transformer
leakage inductance and peak primary current, and the primary samples before approving the design.
winding capacitance determine the peak drain voltage. With no
significant dissipative element present, as is the case with an Ceramic capacitors that use dielectrics, such as Z5U, when
external clamp, the longer duration of the leakage inductance used in clamp circuits may also generate audio noise. If this is
ringing can increase EMI. the case, try replacing them with a capacitor having a different
dielectric or construction, for example a film type.
2-51
2-51
Rev. C 12/05
LNK362-364
Input Filter
TOP VIEW Capacitor
Y1-
Capacitor
FB
D
LinkSwitch-XT
T
r
S
a
BP
n S S
s - HV DC +
S
f INPUT
o S
r S
m
CBP
e
r
Opto-
coupler
+
DC Maximize hatched copper
OUT
- areas ( ) for optimum
heatsinking
Output Filter
Capacitor
2 PI-4155-102705
Figure 6. Recommended Printed Circuit Layout for LinkSwitch-XT in a Flyback Converter Configuration.
LinkSwitch-XT Layout Considerations Zener (~200 V) and diode clamp across the primary winding.
In all cases, to minimize EMI, care should be taken to minimize
See Figure 6 for a recommended circuit board layout for the circuit path from the clamp components to the transformer
LinkSwitch-XT. and LinkSwitch-XT.
Single Point Grounding Thermal Considerations

Use a single point ground connection from the input filter The copper area underneath the LinkSwitch-XT acts not only
capacitor to the area of copper connected to the SOURCE as a single point ground, but also as a heatsink. As this area is
pins. connected to the quiet source node, it should be maximized for
good heat sinking of LinkSwitch-XT. The same applies to the
Bypass Capacitor CBP cathode of the output diode.
The BYPASS pin capacitor should be located as near as possible
to the BYPASS and SOURCE pins. Y-Capacitor
The placement of the Y-type cap should be directly from the
Primary Loop Area primary input filter capacitor positive terminal to the common/
The area of the primary loop that connects the input filter return terminal of the transformer secondary. Such a placement
capacitor, transformer primary and LinkSwitch-XT together will route high magnitude common-mode surge currents away
should be kept as small as possible. from the LinkSwitch-XT device. Note that if an input pi (C, L, C)
EMI filter is used, then the inductor in the filter should be placed
Primary Clamp Circuit between the negative terminals of the input filter capacitors.
A clamp is used to limit peak voltage on the DRAIN pin at
turn-off. This can be achieved by using an RCD clamp or a
52
2-52
2-52
Rev. C 12/05
LNK362-364
Optocoupler 2. Maximum drain current – At maximum ambient temperature,

Place the optocoupler physically close to the LinkSwitch-XT to maximum input voltage and peak output (overload) power,
minimize the primary-side trace lengths. Keep the high current, verify drain current waveforms for any signs of transformer
high-voltage drain and clamp traces away from the optocoupler saturation and excessive leading-edge current spikes at
to prevent noise pick up. startup. Repeat under steady state conditions and verify that
the leading-edge current spike event is below ILIMIT(MIN) at the
Output Diode end of the tLEB(MIN). Under all conditions, the maximum drain
For best performance, the area of the loop connecting the current should be below the specified absolute maximum
secondary winding, the output diode and the output filter ratings.
capacitor should be minimized. In addition, sufficient copper 3. Thermal Check – At specified maximum output power,
area should be provided at the anode and cathode terminals minimum input voltage and maximum ambient temperature,
of the diode for heat sinking. A larger area is preferred at the verify that the temperature specifications are not exceeded
quiet cathode terminal. A large anode area can increase high for LinkSwitch-XT, transformer, output diode and output
frequency radiated EMI. capacitors. Enough thermal margin should be allowed for
part-to-part variation of the RDS(ON) of LinkSwitch-XT as
Quick Design Checklist specified in the data sheet. Under low line, maximum power,
a maximum LinkSwitch-XT SOURCE pin temperature of
As with any power supply design, all LinkSwitch-XT designs 105 °C is recommended to allow for these variations.
should be verified on the bench to make sure that component
specifications are not exceeded under worst-case conditions. The Design Tools
following minimum set of tests is strongly recommended:
Up-to-date information on design tools can be found at the
1. Maximum drain voltage – Verify that VDS does not exceed Power Integrations web site: www.powerint.com.
650 V at the highest input voltage and peak (overload) output
power. The 50 V margin to the 700 V BVDSS specification
gives margin for design variation, especially in Clampless
designs.
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Rev. C 12/05
LNK362-364

DRAIN Voltage .................................. .............-0.3 V to 700 V Notes:
Peak DRAIN Current: LNK362................200 mA (375 mA)(2) 1. All voltages referenced to SOURCE, TA = 25 °C.
LNK363/364.........400 mA (750 mA)(2) 2. The higher peak DRAIN current is allowed while the
FEEDBACK Voltage ...........................................-0.3 V to 9 V DRAIN voltage is simultaneously less than 400 V.
FEEDBACK Current ...................................................100 mA 3. Normally limited by internal circuitry.
BYPASS Voltage.................................................. -0.3 V to 9 V 4. 1/16 in. from case for 5 seconds.
Storage Temperature .....................................-65 °C to 150 °C 5. Maximum ratings specified may be applied, one at a time,
Operating Junction Temperature(3) ................-40 °C to 150 °C without causing permanent damage to the product.
Lead Temperature(4) ....................................................... 260 °C Exposure to Absolute Maximum Rating conditions for
extended periods of time may affect product reliability.
THERMAL IMPEDANCE
Conditions
See Figure 7
CONTROL FUNCTIONS
Average 124 132 140
Output Frequency fOSC TJ = 25 °C kHz
Peak-Peak Jitter 9
Maximum Duty
DCMAX S2 Open 60 %
2 Cycle
FEEDBACK Pin
Turnoff Threshold IFB TJ = 25 °C 30 49 68 µA
Current
FEEDBACK Pin LNK362 1.55 1.65 1.75
TJ = 0 °C to
Voltage at Turnoff VFB
125 °C
V
Threshold LNK363-364 1.53 1.63 1.73
VFB ≥2 V
DRAIN Supply See Note A
Current FEEDBACK Open
IS2 (MOSFET 250 300 µA
Switching)
VBP = 0 V, TJ = 25 °C
ICH1 -5.5 -3.5 -1.8
BYPASS Pin See Note C
mA
Charge Current ICH2
VBP = 4 V, TJ = 25 °C
-3.8 -2.3 -1.0
See Note C
BYPASS Pin
VBP 5.55 5.8 6.10 V
Voltage
BYPASS Pin
VBPH 0.8 1.0 1.2 V
Voltage Hysteresis
54
2-54
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Rev. C 12/05
LNK362-364
Conditions
SOURCE = 0 V; TJ = -40 to 125 °C
Parameter Symbol Min Typ Max Units
See Figure 7
CONTROL FUNCTIONS (cont)
BYPASS Pin
IBPSC See Note D 68 µA
Supply Current
CIRCUIT PROTECTION
di/dt = 30 mA/µs
LNK362 130 140 150
TJ = 25 °C
ILIMIT
di/dt = 42 mA/µs
Current Limit (See TJ = 25 °C
LNK363 195 210 225 mA
Note E)
di/dt = 50 mA/µs
LNK364 233 250 268
TJ = 25 °C
di/dt = 30 mA/µs
LNK362 2199 2587
TJ = 25 °C
di/dt = 42 mA/µs
Power Coefficient I2f
TJ = 25 °C
LNK363 4948 5821 A2Hz
di/dt = 50 mA/µs
LNK364 7425 8250
TJ = 25 °C
Leading Edge TJ = 25 °C LNK362 300 375

tLEB ns
Blanking Time See Note F LNK363/364 170 250
Current Limit TJ = 25 °C 2
tILD 125 ns
Delay See Note F
Thermal
Shutdown TSD 135 142 150 °C
Temperature
Thermal
Shutdown TSHD See Note G 75 °C
Hysteresis
OUTPUT
LNK362 TJ = 25 °C 48 55
ID = 14 mA TJ = 100 °C 76 88
ON-State LNK363 TJ = 25 °C 29 33
RDS(ON) Ω
Resistance ID = 21 mA TJ = 100 °C 46 54
LNK364 TJ = 25 °C 24 28
ID = 25 mA TJ = 100 °C 38 45
VBP = 6.2 V, VFB ≥2 V,
OFF-State Drain
IDSS VDS = 560 V, 50 µA
Leakage Current TJ = 125 °C
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Rev. C 12/05
LNK362-364
Conditions
See Figure 7
OUTPUT (cont)
Breakdown VBP = 6.2 V, VFB ≥ 2 V,
BVDSS 700 V
Voltage See Note H, TJ = 25 °C
DRAIN Supply
50 V
Voltage
Output Enable
Delay
Output Disable
tDST 0.5 µs
Setup Time
Auto-Restart TJ = 25 °C LNK362 40
tAR ms
ON-Time See Note I LNK363-364 45
Auto-Restart Duty
DCAR 5 %
Cycle
NOTES:
A. Total current consumption is the sum of IS1 and IDSS when FEEDBACK pin voltage is ≥2 V (MOSFET not
2 B Since the output MOSFET is switching, it is difficult to isolate the switching current from the supply current at the
C. See Typical Performance Characteristics section Figure 14 for BYPASS pin startup charging waveform.
D. This current is only intended to supply an optional optocoupler connected between the BYPASS and FEEDBACK
H. Breakdown voltage may be checked against minimum BVDSS specification by ramping the DRAIN pin voltage up
I. Auto-restart on time has the same temperature characteristics as the oscillator (inversely proportional to
frequency).
56
2-56
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Rev. C 12/05
LNK362-364
470 Ω
5W 470 kΩ
D FB
S1 S2
BP
50 V 50 V
S S 0.1 µF
S S
PI-3490-060204
Figure 7. LinkSwitch-XT General Test Circuit.
DCMAX
t2 (internal signal)
t1 tP
HV 90% 90%
FB
DRAIN t
D= 1
VOLTAGE t2 VDRAIN tEN
10%
0V tP =
1
fOSC
2
PI-2048-033001 PI-3707-112503
Figure 8. LinkSwitch-XT Duty Cycle Measurement. Figure 9. LinkSwitch-XT Output Enable Timing.
2-57
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Rev. C 12/05
LNK362-364
1.1 1.2
PI-2680-012301
PI-2213-012301
1.0
Breakdown Voltage
Output Frequency
0.8
1.0 0.6
0.4
0.2
0.9 0
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125
1.4 1.4
PI-4091-081505
PI-4092-081505
1.2 Normalized Current Limit 1.2
1.0 1.0
Current Limit
0.8 0.8 Normalized

Normalized Current
TBD
di/dt = 1 Limit = 1
0.6 0.6 LNK362 30 mA/µs 140 mA
2
0.4 0.4
0.2 0.2
0 0
-50 0 50 100 150 1 2 3 4 5
Figure 12. Current Limit vs. Temperature. Figure 13. Current Limit vs. di/dt.
7 400
PI-2240-012301
PI-4093-081605
6 350
25 °C
DRAIN Current (mA)
5 300
100 °C
4 250
3 200
Scaling Factors:
2 150 LNK362 0.5
LNK363 0.8
1 100 LNK364 1.0
0 50
0
0 0.2 0.4 0.6 0.8 1.0 0 2 4 6 8 10 12 14 16 18 20
Figure 14. BYPASS Pin Startup Waveform. Figure 15. Output Characteristics.
58
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Rev. C 12/05
LNK362-364
1000
PI-4094-081605
100
Scaling Factors:
LNK362 0.5
LNK363 0.8
LNK364 1.0
10
1
0 100 200 300 400 500 600
Drain Voltage (V)

XT Series Number
Package Identifier
P Plastic DIP
Lead Finish 2
LNK 364 G N - TL TL Tape & Reel, 1000 pcs minimum, G Package only
Revision Notes Date

B 1) Released Final Data Sheet. 11/05
C 1) Corrected Application Example section. 12/05
2-59
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Rev. C 12/05
LNK500
LNK500
LinkSwitch® Family
Energy-Efficient, CV or CV/CC Switcher for
Very Low Cost Adapters and Chargers
Product Highlights LinkSwitch
D S
Cost Effective Linear/RCC Replacement
C
• Lowest cost and component count, constant voltage (CV)
or constant voltage/constant current (CV/CC) solution Wide Range DC
• Extremely simple circuit configuration HV DC Input Output
(VO)
• Up to 75% lighter power supply reduces shipping cost
• Primary based CV/CC solution eliminates 10 to 20 secondary
components for low system cost
• Combined primary clamp, feedback, IC supply, and loop (a)
compensation functions – minimizes external components Example Characteristic
• Fully integrated auto-restart for short circuit and open loop VO Min Typ VO
(CV only) (CV/CC)
fault protection – saves external component costs ±5%
• 42 kHz operation simplifies EMI filter design ±10%
Much Higher Performance Over Linear/RCC

• Universal input range allows worldwide operation
• Up to 70% reduction in power dissipation – reduces enclosure IO IO
size significantly ±25%* ±25%*
(b)
• CV/CC output characteristic without secondary feedback For Circuit
Shown Above
With Optional
Secondary Feedback**
• System level thermal and current limit protection
*Estimated tolerance achievable in high volume production
• Meets all single point failure requirements with only one including transformer and other component tolerances.
2 additional clamp capacitor

• Controlled current in CC region provides inherent soft-start
**See Optional Secondary Feedback section.
PI-3415-021103
• Optional opto feedback improves output voltage accuracy Figure 1. Typical Application – Not a Simplified Circuit (a) and
Output Characteristic Tolerance Envelopes (b).
®
EcoSmart – Extremely Energy-Efficient
• Consumes <300 mW at 265 VAC input with no load OUTPUT POWER TABLE1
• Meets California Energy Commission (CEC), ENERGY 230 VAC ±15% 85-265 VAC No-Load
STAR, and EU requirements PRODUCT4 Input
• No current sense resistors – maximizes efficiency Min2 Typ2 Min2 Typ2 Power
LNK500 3.2 W 4 W 2.4 W 3 W <300 mW
Applications
• Linear transformer replacement in all ≤3 W applications P or G 4.3 W 5.5 W 2.9 W 3.5 W <500 mW3
• Chargers for cell phones, cordless phones, PDAs, digital Table 1. Output Power Table.
cameras, MP3/portable audio devices, shavers, etc. Notes:
• Home appliances, white goods and consumer electronics 1. Output power for designs in an enclosed adapter measured at
• Constant output current LED lighting applications 50 °C ambient.
2. See Figure 1 (b) for Min (CV only designs) and Typ (CV/CC charger
• TV standby and other auxiliary supplies designs) power points identified on output characteristic.
3. Uses higher reflected voltage transformer designs for increased
Description power capability – see Key Application Considerations section.
4. For lead-free package options, see Part Ordering Information.
LinkSwitch is specifically designed to replace low power linear
transformer/RCC chargers and adapters at equal or lower system attractive package when compared with the traditional “brick.”
cost with much higher performance and energy efficiency. With efficiency of up to 75% and <300 mW no-load consumption,
LNK500 is a lower cost version of the LNK501 with a wider a LinkSwitch solution can save the end user enough energy
tolerance output CC characteristic. LinkSwitch introduces a over a linear design to completely pay for the full power
revolutionary patented topology for the design of low power supply cost in less than one year. LinkSwitch integrates a
switching power supplies that rivals the simplicity and low 700 V power MOSFET, PWM control, high voltage startup, current
cost of linear adapters, and enables a much smaller, lighter, and limit, and thermal shutdown circuitry, onto a monolithic IC.
2-60
2-60
Rev. D 02/05
LNK500
0 DRAIN
CONTROL VC
INTERNAL
1 SUPPLY
ZC
SHUTDOWN/
SHUNT REGULATOR/ AUTO-RESTART CURRENT
ERROR AMPLIFIER LIMIT
+ ADJUST
- ÷8
5.6 V -
4.7 V CURRENT LIMIT
+ 5.6 V COMPARATOR
+
I FB HYSTERETIC
THERMAL
SHUTDOWN
OSCILLATOR
D MAX
CLOCK S Q
SAW - R
+
PWM
COMPARATOR
IDCS
LEADING
EDGE
EDGE
LOW BLANKING
RE FREQUENCY
OPERATION
SOURCE
PI-3416-032603
Figure 2. Block Diagram. 2

LNK500
DRAIN (D) Pin:
Power MOSFET drain connection. Provides internal operating S 1 8 C
current for startup. Internal current limit sense point for drain S 2 7 S
current.
S 3
CONTROL (C) Pin: S 4 5 D
and current limit control. Internal shunt regulator connection
to provide internal bias current during normal operation. It is P Package (DIP-8B)
also used as the connection point for the supply bypass and G Package (SMD-8B)
PI-3417-111802
auto-restart/compensation capacitor.
SOURCE (S) Pin:
Output MOSFET source connection for high voltage power
return. Primary side control circuit common and reference
point.
2-61
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Rev. D 02/05
LNK500
LinkSwitch Functional Description Internal Current Limit
The duty cycle, current limit and operating frequency Auto-restart
relationships with CONTROL pin current are shown in ILIM

Figure 4. Figure 5 shows a typical power supply outline
schematic which is used below to describe the LinkSwitch
operation.
Power Up
During power up, as VIN is first applied (Figure 5), the CONTROL
pin capacitor C1 is charged through a switched high voltage
current source connected internally between the DRAIN and CONTROL Current IC IDCT
CONTROL pins (see Figure 2). When the CONTROL pin
voltage reaches approximately 5.6 V relative to the SOURCE Duty Cycle
pin, the high voltage current source is turned off, the internal
control circuitry is activated and the high voltage internal
Auto-restart
MOSFET starts to switch. At this point, the charge stored on
77%
C1 is used to supply the internal consumption of the chip.
Constant Current (CC) Operation

As the output voltage, and therefore the reflected voltage
30%
across the primary transformer winding ramp up, the feedback
CONTROL current IC increases. As shown in Figure 4, the
internal current limit increases with IC and reaches ILIM when IC 3.8%
is equal to IDCT. The internal current limit vs. IC characteristic ICD1 IDCS
is designed to provide an approximately constant power supply CONTROL Current IC
output current as the power supply output voltage rises. Frequency
Constant Voltage (CV) Operation Auto-restart
2 When IC exceeds IDCS, typically 2 mA (Figure 4), the maximum

duty cycle is reduced. At a value of IC that depends on power
fOSC
supply input voltage, the duty cycle control limits LinkSwitch fOSC(low)
peak current below the internal current limit value. At this point
the power supply transitions from CC to CV operation. With
minimum input voltage in a typical universal input design, this
transition occurs at approximately 30% duty cycle. Resistor R1
(Figure 5) is therefore initially selected to conduct a value of IC
CONTROL Current IC
approximately equal to IDCT when VOUT is at the desired value
at the minimum power supply input voltage. The final choice PI-2799-112102
of R1 is made when the rest of the circuit design is complete.
Figure 4. CONTROL Characteristics.
When the duty cycle drops below approximately 4%, the
frequency is reduced, which reduces energy consumption under
light load conditions.
LinkSwitch
D S
Auto-Restart Operation
C C1
When a fault condition, such as an output short circuit or open
loop, prevents flow of an external current into the CONTROL C2
R1
pin, the capacitor C1 discharges towards 4.7 V. At 4.7 V, auto-
C4 VOUT
restart is activated, which turns the MOSFET off and puts the
VIN D1
control circuitry in a low current fault protection mode. In
auto-restart, LinkSwitch periodically restarts the power supply R2
D2
so that normal power supply operation can be restored when
the fault is removed. PI-2715-112102
Figure 5. Power Supply Outline Schematic.
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Rev. D 02/05
LNK500
The characteristics described above provide an approximate from Figure 5 by the addition of R3, C3 and optocoupler U1.
CV/CC power supply output without the need for secondary- R3 forms a potential divider with R1 to limit the U1 collector
side voltage or current feedback. The output voltage regulation emitter voltage.
is influenced by how well the voltage across C2 tracks the
reflected output voltage. This tracking is influenced by the On the secondary side, the addition of voltage sense circuit
value of the transformer leakage inductance which introduces components R4, VR1 and U1 LED provide the voltage feedback
an error. Resistor R2 and capacitor C2 partially filter the signal. In the example shown, a simple Zener (VR1) reference
leakage inductance voltage spike reducing this error. This is used though a precision TL431 reference is typically needed
circuitry, used with standard transformer construction to provide ±5% output voltage tolerancing and cable drop
techniques provides much better output load regulation than a compensation, if required. Resistor R4 provides biasing for VR1.
linear transformer, making this an ideal power supply solution The regulated output voltage is equal to the sum of the VR1
in many low power applications. If tighter load regulation is Zener voltage plus the forward voltage drop of the U1 LED.
required, an optocoupler configuration can be used while still Resistor R5 is an optional low value resistor to limit U1 LED
employing the constant output current characteristics provided peak current due to output ripple. Manufacturerʼs specifications
by LinkSwitch. for U1 current and VR1 slope resistance should be consulted
to determine whether R5 is required.
Optional Secondary Feedback
Figure 6 shows a typical power supply outline schematic using U1 is arranged with collector connected to primary ground and
LinkSwitch with optocoupler feedback to improve output emitter to the anode of D1. This connection keeps the opto in
voltage regulation. On the primary side, the schematic differs an electrically “quiet” position in the circuit. If the opto was
LinkSwitch
D S
VOUT
LNK500
C C1
R5
C2
R1 U1
85-265 R4
VAC R2
D1
U1
VR1 2
R3 C3
RTN
PI-3418-071304
Figure 6. Power Supply Outline Schematic with Optocoupler Feedback.
Output Voltage
Inherent
CC to CV Tolerance envelope
transition without optocoupler
point Typical inherent
Voltage
feedback characteristic without
threshold optocoupler
Characteristic with
optocoupler
Load variation
during battery
charging
Output Current
PI-2788-092101
Figure 7. Influence of the Optocoupler on the Power Supply Output Characteristic.
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Rev. D 02/05
LNK500
instead placed on the cathode side of D1, it would become a The extent to which R3 can be increased is limited by opto
switching node, generating additional common mode EMI transistor voltage and dissipation ratings and should be fully
currents through its internal parasitic capacitance. tested before finalizing a design. The values of C2 and C3 are
less important other than to make sure they are large enough
The feedback configuration in Figure 6 is simply a resistive to have very little influence on the impedance of the voltage
divider made up of R1 and R3 with D1, R2, C1 and C2 rectifying, division circuit set up by R1, R3 and U1 at the switching
filtering and smoothing the primary winding voltage signal. The frequency. Normally, the values of C2 and C3 in Figure 6 are
optocoupler therefore effectively adjusts the resistor divider ratio chosen equal to the value of C2 in Figure 5, though the voltage
to control the DC voltage across R1 and therefore, the feedback rating may be reduced depending on the relative values of R1
current received by the LinkSwitch CONTROL pin. and R2 discussed above. See Applications section for typical
values of components.
When the power supply operates in the constant current (CC)
region, for example when charging a battery, the output voltage Figure 7 shows the influence of optocoupler feedback on the
is below the voltage feedback threshold defined by U1 and output characteristic. The envelope defined by the dashed lines
VR1 and the optocoupler is fully off. In this region, the circuit represent the worst case power supply DC output voltage and
behaves exactly as previously described with reference to current tolerances (unit-to-unit and over the input voltage
Figure 5 where the reflected voltage increases with increasing range) if an optocoupler is not used. A typical example of an
output voltage and the LinkSwitch internal current limit is inherent (without optocoupler) output characteristic is shown
adjusted to provide an approximate CC output characteristic. dotted. This is the characteristic that would result if U1, R4 and
Note that for similar output characteristics in the CC region, VR1 were removed. The optocoupler feedback results in the
the value of R1 in Figure 5 will be equal to the value of characteristic shown by the solid line. The load variation arrow in
R1 + R3 in Figure 6. Figure 7 represents the locus of the output characteristic normally
seen during a battery charging cycle. The two characteristics
When the output reaches the voltage feedback threshold set by are identical as the output voltage rises but then separate as
U1 and VR1, the optocoupler turns on. Any further increase shown when the voltage feedback threshold is reached. This
in the power supply output voltage results in the U1 transistor is the characteristic seen if the voltage feedback threshold is
current increasing, which increases the percentage of the above the output voltage at the inherent CC to CV transition
reflected voltage appearing across R1. The resulting increase point also indicated in Figure 7.
in the LinkSwitch CONTROL current reduces the duty cycle
according to Figure 4 and therefore, maintains the output Figure 8 shows a case where the voltage feedback threshold is
2 voltage regulation. set below the voltage at the inherent CC to CV transition point.
In this case, as the output voltage rises, the secondary feedback
Normally, R1 and R3 are chosen to be equal in value. However, circuit takes control before the inherent CC to CV transition
increasing R3 (while reducing R1 to keep R1 + R3 constant) occurs. In an actual battery charging application, this simply
increases loop gain in the CV region, improving load regulation. limits the output voltage to a lower value.
Output Voltage
Inherent Tolerance envelope
CC to CV without optocoupler
transition
Typical inherent
point
characteristic without
Voltage optocoupler
VO(MAX)
feedback Characteristic with
Power supply peak
output power curve
Load variation
during battery
charging Characteristic observed with
load variation often applied during
laboratory bench testing
Output Current PI-2790-112102
Figure 8. Output Characteristic with Optocoupler Regulation (Reduced Voltage Feedback Threshold).
2-64
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Rev. D 02/05
LNK500
However, in laboratory bench tests, it is often more convenient The secondary of the transformer is rectified and filtered by D6
to test the power supply output characteristic starting from a and C5 to provide the DC output to the load.
low output current and gradually increasing the load. In this
case, the optocoupler feedback regulates the output voltage until LinkSwitch dramatically simplifies the secondary side by
the peak output power curve is reached as shown in Figure 8. controlling both the constant voltage and constant current regions
Under these conditions, the output current will continue to rise entirely from the primary side. This is achieved by monitoring
until the peak power point is reached and the optocoupler turns the primary-side VOR (voltage output reflected).
off. Once the optocoupler is off, the CONTROL pin feedback
current is determined only by R1 and R3 and the output current Diode D5 and capacitor C4 form the primary clamp network.
therefore folds back to the inherent CC characteristic as shown. This both limits the peak drain voltage due to leakage inductance
Since this type of load transition does not normally occur in a and provides a voltage across C4, which is equal to the VOR plus
battery charger, the output current never overshoots the inherent an error due to the parasitic leakage inductance. Resistor R2
constant current value in the actual application. filters the leakage inductance spike and reduces the error in the
value of the VOR. Resistor R1 converts this voltage into a current
In some applications it may be necessary to avoid any output that is fed into the CONTROL pin to regulate the output.
current overshoot, independent of the direction of load variation.
To achieve this goal, the minimum voltage feedback threshold During CV operation the output is regulated through control of
should be set at VO(MAX). This will ensure that the voltage at the the duty cycle. As the current into the CONTROL pin exceeds
CC to CV transition point of the inherent characteristic will approximately 2 mA, the duty cycle begins to reduce, reaching
always occur below the voltage feedback threshold. However, the 30% at a CONTROL pin current of 2.3 mA.
output voltage tolerance is then increased, since the inherent CV
characteristic tolerance below VO(MAX) is added to the tolerance Under light or no-load conditions, when the duty cycle reaches
of the optocoupler feedback circuit. approximately 4%, the switching frequency is reduced to lower
energy consumption.
Applications Example
If the output load is increased beyond the peak power point
The circuit shown in Figure 9 shows a typical implementation (defined by 0.5·LP·ILIM2·f), the output voltage and VOR falls.
of an approximate constant voltage / constant current (CV/CC) The reduced CONTROL pin current will lower the internal
charger using LinkSwitch. This design delivers 2.75 W with LinkSwitch current limit (current limit control) providing an
a nominal peak power point voltage of 5.5 V and a current of
500 mA. Efficiency is greater than 70% over an input range
approximately constant current output characteristic. If the
load is increased and the CONTROL pin current falls below 2
of 85 VAC to 265 VAC. approximately 1 mA, the CONTROL pin capacitor C3 will
discharge and the supply enters auto-restart.
The bridge rectifier, BR1, rectifies the AC input. Resistor, RF1
is a fusible type providing protection from primary-side short Current limit control removes the need for any secondary side
circuits. The rectified AC is smoothed by C1 and C2 with current sensing components (sense resistor, transistor, opto
inductor L1 forming a pi-filter in conjunction with C1 and C2 coupler and associated components). Removing the secondary
to filter conducted EMI. The switching frequency of 42 kHz sense circuit dramatically improves efficiency, giving the
allows such a simple EMI filter to be used without the need for a associated benefit of reduced enclosure size.
Y-capacitor while still meeting international EMI standards.
When power is applied, high voltage DC appears at the DRAIN

Key Application Considerations
pin of LinkSwitch (U1). The CONTROL pin capacitor C3 is then Design Output Power
charged through a switched high voltage current source connected
internally between the DRAIN and CONTROL pins. When Table 1 (front page) provides guidance for the maximum
the CONTROL pin reaches approximately 5.6 V relative to the continuous output power from a given device under the
SOURCE pin, the internal current source is turned off. The internal conditions specified.
control circuitry is activated and the high voltage MOSFET starts
to switch, using the energy in C3 to power the IC. The output of chargers (CV/CC) are normally specified at
the typical output peak power point. Conversely, non-charger
When the MOSFET is on, the high voltage DC bus is connected applications (CV only, which applies to many converters such
to one end of the transformer primary, the other end being as adapters, standby/auxiliary supplies and other embedded
connected to primary return. As the current ramps in the AC-DC converters) where CC operation is not required, are
primary of flyback transformer T1, energy is stored. This normally specified at the minimum output power they will
energy is delivered to the output when the MOSFET turns off supply under worst case conditions.
each switching cycle.
2-65
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Rev. D 02/05
LNK500
L1 LinkSwitch
1 mH T1
D S 1 5 5.5 V,
C3 500 mA
U1 C 0.22 µF
LNK500 50 V
116 T 4 15 T C5
34 AWG 30 AWG 470 µF
BR1 C4 TIW
0.1 µF 10 V
RF1 1 A, 600 V R1
10 Ω 1 W 100 V
20.5 kΩ
Fusible 1% RTN
3 6
C1 C2 D6
85-265 4.7 µF 4.7 µF 11DQ06
VAC 400 V 400 V EE13
D5 LP = 2.55 mH PERFORMANCE SUMMARY
1N4937
Output Power: 2.75 W
R2 Efficiency: ≥72%
100 Ω
No Load
Consumption: 260 mW, 230 VAC
200 mW, 115 VAC
PI-3419-071304
Figure 9. 2.75 W Constant Voltage/Constant Current (CV/CC) Charger using LinkSwitch.
10
PI-3420-111802
9 VIN = 85 VAC
VIN = 115 VAC
2 8 VIN = 185 VAC
VIN = 265 VAC
7
Output Voltage (V)
0
0 100 200 300 400 500 600 700
Output Current (mA)
Figure 10. Measured Output Characteristic of the Circuit in Figure 9.
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To aid the designer, the power table reflects these differences. For As primary inductance tolerance is part of the expression
CV/CC designs the typical power column and for CV designs that determines the peak output power point (start of the CC
the minimum power column should be used, respectively. characteristic) this parameter should be well controlled. For
Additionally, figures are based on the following conditions: an estimated overall constant current tolerance of ±25% the
primary inductance tolerance should be ±10% or better. This
1. The minimum DC input bus voltage is 90 V or higher. This is achievable using standard low cost, center leg gapping
corresponds to a filter capacitor of 3 µF/W for universal input techniques where the gap size is typically 0.08 mm or larger.
and 1 µF/W for 230 VAC or 115 VAC input with doubler Smaller gap sizes are possible but require non-standard, tighter
input stage. ferrite AL tolerances.
2. Design is a discontinuous mode flyback converter.
Continuous mode designs can result in loop instability and Other gapping techniques such as film gapping allow tighter
are therefore not recommended. For typical output power tolerances (±7% or better) with associated improvements in
figures, nominal values for primary inductance and I2f are the tolerance of the peak power point. Please consult your
assumed. For minimum output power figures, primary transformer vendor for guidance.
inductance minus 10% and the minimum I2f value are
assumed. For no-load consumption <300 mW, a VOR in the Core gaps should be uniform. Uneven core gapping, especially
range 40 V to 60 V is assumed. For no-load consumption with small gap sizes, may cause variation in the primary
<500 mW and higher output power capability, a VOR in the inductance with flux density (partial saturation) and make the
range 60 V to 100 V is assumed. constant current region non-linear. To verify uniform gapping
3. A secondary output of 5 V with a Schottky rectifier diode. it is recommended that the primary current wave-shape be
4. Assumed efficiency of 70%. examined while feeding the supply from a DC source. The
5. The part is board mounted with SOURCE pins soldered to gradient is defined as di/dt = V/L and should remain constant
sufficient area of copper to keep the die temperature at or throughout the MOSFET on time. Any change in gradient of
below 100 °C. the current ramp is an indication of uneven gapping.
6. An output cable with a total resistance of 0.2 Ω.
Measurements made using an LCR bridge should not be solely
In addition to the thermal environment (sealed enclosure, relied upon; typically these instruments only measure at currents
ventilated, open frame, etc), the maximum power capability of a few milliamps. This is insufficient to generate high enough
of LinkSwitch in a given application depends on transformer flux densities in the core to show uneven gapping.
core size, efficiency, primary inductance tolerance, minimum
specified input voltage, input storage capacitance, output voltage, For a typical EE13 core using center leg gapping, a 0.08 mm 2
output diode forward drop, etc., and can be different from the gap (ALG of 190 nH/t2) allows a primary inductance tolerance of
values shown in Table 1. ±10% to be maintained in standard high volume production.
This allows the EE13 to be used in designs up to 2.75 W with
Transformer Design less than 300 mW no-load consumption. If film gapping is used
To provide an approximately CV/CC output, the transformer then this increases to 3 W. Moving to a larger core, EE16 for
should be designed to be discontinuous; all the energy stored example, allows a 3 W output with center leg gapping.
in the transformer is transferred to the secondary during the
MOSFET off time. Energy transfer in discontinuous mode is The transformer turns ratio should be selected to give a VOR
independent of line voltage. (output voltage reflected through secondary to primary turns
ratio) of 40 V to 60 V. In designs not required to meet 300 mW
The peak power point prior to entering constant current operation no-load consumption targets, the transformer can be designed
is defined by the maximum power transferred by the transformer. with higher VOR as long as discontinuous mode operation is
The power transferred is given by the expression P = 0.5·LP·I2·f, maintained. This increases the output power capability. For
where LP is the primary inductance, I2 is the primary peak current example, a 230 VAC input design using an EE19 transformer
squared and f is the switching frequency. core with VOR >70 V, is capable of delivering up to 5.5 W typical
output power. Note: the linearity of the CC region of the power
To simplify analysis, the data sheet parameter table specifies an supply output characteristic is influenced by VOR. If this is an
I2f coefficient. This is the product of current limit squared and important aspect of the application, the output characteristic
switching frequency normalized to the feedback parameter IDCT. should be checked before finalizing the design.
This provides a single term that specifies the variation of the
peak power point in the power supply due to LinkSwitch. Output Characteristic Variation
Both the device tolerance and external circuit govern the overall
tolerance of the LinkSwitch output characteristic. Estimated
peak power point tolerances for a 3 W design are ±10% for
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LNK500
voltage and ±25% for current limit for overall variation in high time during startup for the output voltage to reach regulation.
volume manufacturing. This includes device and transformer Any capacitor type is acceptable with a voltage rating of
tolerances and line variation. Lower power designs may have 10 V or above.
poorer constant current linearity.
Feedback Resistor – R1
As the output load reduces from the peak power point, the The value of R1 is selected to give a feedback current into the
output voltage will tend to rise due to tracking errors compared CONTROL pin of approximately 2.3 mA at the peak output
to the load terminals. Sources of these errors include the power point of the supply. The actual value depends on the VOR
output cable drop, output diode forward voltage and leakage selected during design. Any 0.25 W resistor is suitable.
inductance, which is the dominant cause. As the load reduces,
the primary operating peak current reduces, together with the Output Diode – D2
leakage inductance energy, which reduces the peak charging Either PN fast, PN ultrafast or Schottky diodes can be used,
of the clamp capacitor. With a primary leakage inductance of depending on the efficiency target for the supply, Schottky
50 µH, the output voltage typically rises 30% over a 100% to diodes giving higher efficiency then PN diodes. The diode
5% load change. voltage rating should be sufficient to withstand the output
voltage plus the input voltage transformed through the turns
At very light or no-load, typically less than 2 mA of output current, ratio (a typical VOR of 50 V requires a diode PIV of 50 V).
the output voltage rises due to leakage inductance peak charging Slow recovery diodes are not recommended (1N400X types).
of the secondary. This voltage rise can be reduced with a small
preload with little change to no-load power consumption. Output Capacitor – C4
Capacitor C4 should be selected such that its voltage and ripple
The output voltage load variation can be improved across the current specifications are not exceeded.
whole load range by adding an optocoupler and secondary
reference (Figure 6). The secondary reference is designed to only LinkSwitch Layout Considerations
provide feedback above the normal peak power point voltage
to maintain the correct constant current characteristic. Primary Side Connections
Since the SOURCE pins in a LinkSwitch supply are switching
Component Selection nodes, the copper area connected to SOURCE together with C1,
C2 and R1 (Figure 5) should be minimized, within the thermal
The schematic shown in Figure 5 outlines the key components contraints of the design, to reduce EMI coupling.
2 needed for a LinkSwitch supply.
The CONTROL pin capacitor C1 should be located as close as
Clamp Diode – D1 possible to the SOURCE and CONTROL pins.
Diode D1 should be either a fast (trr <250 ns) or ultrafast type
(trr <50 ns), with a voltage rating of 600 V or higher. Fast To minimize EMI coupling from the switching nodes on the
recovery types are preferred, being typically lower cost. Slow primary to both the secondary and AC input, the LinkSwitch
diodes are not recommended; they can allow excessive DRAIN should be positioned away from the secondary of the transformer
ringing and the LinkSwitch to be reverse biased. and AC input.
Clamp Capacitor – C2 Routing the primary return trace from the transformer primary
Capacitor C2 should be a 0.1 µF, 100 V capacitor. Low cost around LinkSwitch and associated components further reduces
metallized plastic film types are recommended. The tolerance coupling.
of this part has a very minor effect on the output characteristic
so any of the standard ±5%, ±10% or ±20% tolerances are Y-Capacitor
acceptable. Ceramic capacitors are not recommended. The If a Y-capacitor is required, it should be connected close to the
common dielectrics used such as Y5U or Z5U are not stable transformer secondary output return pin(s) and the primary bulk
with voltage or temperature and may cause output instability. capacitor negative return. Such placement will maximize the
Ceramic capacitors with high stability dielectrics may be used EMI benefit of the Y-capacitor and avoid problems in common-
but are expensive compared to metallized film types. mode surge testing.
CONTROL Pin Capacitor – C1

Capacitor C1 is used during startup to power LinkSwitch and
sets the auto-restart frequency. For designs that have a battery
load, this component should have a value of 0.22 µF and for
resistive loads, a value of 1 µF. This ensures there is sufficient
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Quick Design Checklist 3. Thermal check – At peak output power, minimum input
voltage and maximum ambient temperature, verify that the
As with any power supply design, all LinkSwitch designs temperature specifications are not exceeded for LinkSwitch,
should be verified on the bench to make sure that component transformer, output diode and output capacitors. Enough
specifications are not exceeded under worst case conditions. thermal margin should be allowed for part-to-part variation of
Note: In a LinkSwitch circuit, the SOURCE is a switching the RDS(ON) of LinkSwitch as specified in the data sheet. Under
node. This should be taken into consideration during testing. low line, peak power, a maximum LinkSwitch SOURCE pin
Oscilloscope measurements should be made with probe grounded temperature of 100 °C is recommended to allow for these
to DC voltages such as primary return or DC rail but not to variations.
SOURCE. Power supply input voltage should always be supplied
using an isolation transformer. The following minimum set of 4. Centered output characteristic – Using a transformer with
tests is strongly recommended: nominal primary inductance and at an input voltage midway
between low and high line, verify that the peak power point
1. Maximum drain voltage – Verify that VDS does not exceed occurs at the desired nominal output current, with the correct
675 V at highest input voltage and peak output power. output voltage. If this does not occur then the design should
be refined to ensure the overall tolerance limits are met.
2. Maximum drain current – At maximum ambient temperature,
maximum input voltage and peak output power, verify drain Design Tools
current waveforms at startup for any signs of transformer
saturation and excessive leading edge current spikes. Up-to-date information on design tools can be found at the
LinkSwitch has a minimum leading edge blanking time of Power Integrations website: www.powerint.com.
200 ns to prevent premature termination of the on-cycle.
Verify that the leading edge current spike event is below
current limit at the end of the 200 ns blanking period.
Input Filter
Capacitor
C S D
2
+
LinkSwitch
HV DC
Input
-
Transformer S S S S
Y1-
Capacitor
DC Out
Output
Capacitor
PI-2900-070202
Figure 11. Recommended Circuit Board Layout for LinkSwitch using P Package.
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LNK500

DRAIN Peak Current......................................400 mA 1. All voltages referenced to SOURCE, TA = 25 °C.
CONTROL Current (not to exceed 9 V)............100 mA 3. 1/16 in. from case for 5 seconds.
Storage Temperature .......................................... -65 °C to 150 °C 4. Maximum ratings specified may be applied, one at a time,
Operating Junction Temperature(2) ..................... -40 °C to 150 °C without causing permanent damage to the product.
Lead Temperature(3) ........................................................260 °C Exposure to Absolute Maximum Rating conditions for
THERMAL IMPEDANCE
Conditions
See Figure 12
CONTROL FUNCTIONS
Switching
fOSC IC = IDCT, TJ = 25 °C 34.5 42 49.5 kHz
Frequency
Low Switching Duty Cycle = DCLF
fOSC(LOW) 24 30 36 kHz
Frequency TJ = 25 °C
2 Duty Cycle at Low
Frequency Switching from fOSC to
Switching DCLF
fOSC(LOW), TJ = 25 °C
2.4 3.8 5.2 %
Frequency
Low Frequency
DC(RANGE) Frequency = fOSC(LOW), TJ = 25 °C 1.8 3.15 4.5 %
Duty Cycle Range
Maximum Duty
DCMAX IC = 1.5 mA 74 77 80 %
Cycle
PWM Gain DCREG IC = IDCT, TJ = 25 °C -0.45 -0.35 -0.25 %/µA
CONTROL Pin
TJ = 25 °C
Current at 30% IDCT
See Figure 4
2.21 2.30 2.39 mA
Duty Cycle
CONTROL Pin
VC(IDCT) IC = IDCT 5.5 5.75 6 V
Voltage
Dynamic
ZC IC = IDCT, TJ = 25 °C 60 90 120 Ω
Impedance
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Rev. D 02/05
LNK500
Conditions
See Figure 12
CONTROL Pin VC = 0 V -4.5 -3.25 -2
IC(CH) TJ = 25 °C mA
Charging Current VC = 5.15 V -2.3 -1.3 -0.3
Control/Supply/ ICD1 TJ = 25 °C Output MOSFET Enabled 0.95 1.06 1.14

mA
Discharge Current ICD2 TJ = 25 °C Output MOSFET Disabled 0.7 0.9 1.1
Auto-Restart
VC(AR) 5.6 V
Threshold Voltage
Auto-Restart
VC(AR)hyst 0.9 V
Hysteresis Voltage
Auto-Restart Duty Short Circuit Applied at
DC(AR) 8 %
Cycle Power Supply Output
Auto-Restart S2 Open
f(AR) 300 Hz
Frequency C1 = 0.22 µF (See Figure 12)
CIRCUIT PROTECTION
TJ = 25 °C
Self-Protection
ILIM di/dt = 90 mA/µs 228 254 280 mA
Current Limit See Note C
TJ = 25 °C
I f Coefficient
2 I2 f di/dt = 90 mA/µs 2412 2710 3008 A2Hz
See Notes C, D 2
Current Limit at
ILIM(AR) IC = ICD1, TJ = 25 °C 158 mA
Auto-Restart
Power Up Reset
VC(RESET) 1.5 2.75 4.0 V
Threshold Voltage
Leading Edge
tLEB IC = IDCT, TJ = 25 °C 200 300 ns
Blanking Time
Current Limit Delay tIL(D) TJ = 25 °C 100 ns
Thermal Shutdown
IC = IDCT 125 135 °C
Temperature
Thermal Shutdown
70 °C
Hysteresis
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LNK500
Conditions
See Figure 12
OUTPUT
ON-State TJ = 25 °C 28 32
RDS(ON) ID = 25 mA Ω
Resistance TJ = 100 °C 42 48
OFF-State Drain VC = 6.2 V
IDSS 50 µA
Leakage Current VD = 560 V, TA = 125 °C
See Note B
VC = 6.2 V, TA = 25 °C
700 V
DRAIN Supply
See Note E 36 50 V
Voltage
NOTES:
A. For specifications with negative values, a negative temperature coefficient corresponds to an increase in magnitude with
increasing temperature, and a positive temperature coefficient corresponds to a decrease in magnitude with increasing
temperature.
B. Breakdown voltage may be checked against minimum BVDSS specification by ramping the DRAIN pin voltage up to but not
exceeding minimum BVDSS.
C. IC is increased gradually to obtain maximum current limit at di/dt of 90 mA/µs. Increasing IC further would terminate the cycle
through duty cycle control.
D. This parameter is normalized to IDCT to correlate to power supply output current (it is multiplied by IDCT(nominal)/IDCT).
2 E. It is possible to start up and operate LinkSwitch at DRAIN voltages well below 36 V. However, the CONTROL pin charging
current is reduced, which affects startup time, auto-restart frequency, and auto-restart duty cycle. Refer to the characteristic
graph on CONTROL pin charge current (IC) vs. DRAIN voltage (Figure 13) for low voltage operation characteristics.
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LNK500
750 Ω LinkSwitch
D S
S1
S
S S
10 kΩ
C S
S2
40 V 40 V C1
0.22 µF
PI-2894-031004
Figure 12. LinkSwitch General Test Circuit.
2
PI-2901-071602
VC = 5.15 V
1.6
CONTROL Pin
1.2
0.8
0.4
2
0
0 20 40 60 80 100
DRAIN Voltage (V) Figure 14. Duty Cycle Measurement.
Figure 13. IC vs. DRAIN Voltage.
120 90
PI-2895-102303
PI-2902-051904
80
100
70
Duty Cycle (%)
80 60
50
60
40
40 30
20
20
10
0 0
0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 2.15 2.25 2.35 2.45 2.55 2.65
CONTROL Pin Voltage (V) CONTROL Pin Current (mA)
Figure 15. CONTROL Pin I-V Characteristic. Figure 16. Duty Cycle vs. CONTROL Pin Current.
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LNK500
1.1 1.200
PI-2213-012301
PI-2896-062802
1.000
(Normalized for 25 °C)

Switching Frequency
Breakdown Voltage
0.800
1.0 0.600
0.400
0.200
0.9 0.000
-50 -25 0 25 50 75 100 125 150 -50 0 50 100 150
Figure 17. Breakdown Voltage vs. Temperature. Figure 18. Switching Frequency vs. Temperature.
1.200 1.2
PI-2897-062802
PI-2910-071602
1.000 1.0

I2f Coefficient
Current Limit
0.800 0.8
0.600 0.6
0.400 0.4
2 0.200 0.2
0.000 0.0
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150

Figure 19. Current Limit vs. Temperature. Figure 20. I f Coefficient vs. Temperature. 2
1.200 1.2
PI-2899-062802
PI-2898-062802
PWM Gain (Normalized for 25 °C)

IDCT (Normalized for 25 °C)
1.000 1
0.800 0.8
0.600 0.6
0.400 0.4
0.200 0.2
0.000 0
-50 0 50 100 150 -50 0 50 100 150
Junction Temperature (°C) Temperature (°C)
Figure 21. IDCT vs. Temperature. Figure 22. PWM Gain vs. Temperature.
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LNK500
300
PI-2222-031401
TCASE=25 °C
250 TCASE=100 °C
Drain Current (mA)

200
150
100
50
0
0 2 4 6 8 10
Drain Voltage (V)
Figure 23. Output Characteristics (DRAIN Current vs.
DRAIN Voltage).

Series Number
Package Identifier
P
Lead Finish
Plastic DIP
2
LNK 500 G N - TL TL Tape & Reel, 1 k pcs minimum, G package only
Revision Notes Date

B 1) Released Final Data Sheet. 3/03
C 1) Added lead-free ordering information. 12/04
D 1) Minor error and formatting corrections. 2/05
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LNK501
LNK501
LinkSwitch® Family
Energy-Efficient, CV/CC Switcher for
Very Low Cost Chargers and Adapters
Product Highlights LinkSwitch
D S
Cost Effective Linear/RCC Replacement
C
• Lowest cost and component count, constant voltage,
constant current (CV/CC) solution Wide Range DC
• Extremely simple circuit configuration HV DC Input Output
(VO)
• Primary based CV/CC solution eliminates 10 to 20
secondary components for low system cost
• Combined primary clamp, feedback, IC supply, and loop (a)
compensation functions – minimizes external components
VO VO
• Fully integrated auto-restart for short circuit and open ±5%
loop fault protection – saves external component costs ±10%
• 42 kHz operation simplifies EMI filter design
• 3 W output with EE13 core for low cost and small size
Much Higher Performance Over Linear/RCC

IO IO
• Universal input range allows worldwide operation ±20%*
(b)
±20%*
• Up to 70% reduction in power dissipation – reduces For Circuit With Optional
Shown Above Secondary Feedback**
enclosure size significantly
• CV/CC output characteristic without secondary feedback *Estimated tolerance achievable in high volume production
including transformer and other component tolerances.
• System level thermal and current limit protection
2 • Meets all single point failure requirements with only one
**See Optional Secondary Feedback section.
PI-2776-022603
additional clamp capacitor
• Controlled current in CC region provides inherent soft-start Figure 1. Typical Application – Not a Simplified Circuit (a) and
• Optional opto feedback improves output voltage accuracy Output Characteristic Tolerance Envelopes (b).
®
EcoSmart – Extremely Energy-Efficient OUTPUT POWER TABLE1
• Consumes <300 mW at 265 VAC input with no load No-Load
230 VAC 85-265
• Meets California Energy Commission (CEC), Energy PRODUCT3 Input
±15% VAC
Star, and EU requirements Power
• No current sense resistors – maximizes efficiency 4W 3W <300 mW
LNK501P or G
Applications 5.5 W 3.5 W <500 mW2
• Linear transformer replacement in all ≤3 W applications Table 1. Output Power Table.
• Chargers for cell phones, cordless phones, PDAs, digital Notes:
cameras, MP3/portable audio devices, shavers, etc. 1. Typical output power for designs in an enclosed adapter
• Home appliances, white goods and consumer electronics measured at 50 °C ambient.
2. Uses higher reflected voltage transformer designs for increased
• Constant output current LED lighting applications power capability – See Key Application Considerations section.
• TV standby and other auxiliary supplies 3. For lead-free package options, see Part Ordering Information.
enables a much smaller, lighter, and attractive package when

Description compared with the traditional “brick.” With efficiency of up
LinkSwitch is specifically designed to replace all linear to 75% at 3 W output and <300 mW no-load consumption, a
transformer/RCC chargers and adapters in the ≤3 W universal LinkSwitch solution can save the end user enough energy
range at equal or lower system cost with much higher performance over a linear design to completely pay for the power supply
and energy efficiency. LinkSwitch introduces a revolutionary cost in less than one year. LinkSwitch integrates a 700 V power
topology for the design of low power switching power supplies MOSFET, PWM control, high-voltage startup, current limit, and
that rivals the simplicity and low cost of linear adapters, and thermal shutdown circuitry, onto a monolithic IC.
2-76
Rev. I 02/05
LNK501
0 DRAIN
CONTROL VC
INTERNAL
1 SUPPLY
ZC
SHUTDOWN/
+ ADJUST
- ÷8
5.6 V -
4.7 V CURRENT LIMIT
+ 5.6 V COMPARATOR
+
I FB HYSTERETIC
THERMAL
SHUTDOWN
OSCILLATOR
D MAX
CLOCK S Q
SAW - R
+
PWM
COMPARATOR
IDCS
LEADING
EDGE
EDGE
LOW BLANKING
RE FREQUENCY
OPERATION
SOURCE
PI-2777-032503
Figure 2. Block Diagram. 2

LNK501
DRAIN (D) Pin:
current.
S 3
PI-2711-073107
SOURCE (S) Pin:
Output MOSFET source connection for high-voltage power
point.
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Rev. I 02/05
LNK501
The duty cycle, current limit and operating frequency Auto-restart

Figure 4. Figure 5 shows a typical power supply outline
schematic which is used below to describe the LinkSwitch
operation.
Power Up
pin capacitor C1 is charged through a switched high-voltage
current source connected internally between the DRAIN and CONTROL Current IC IDCT
CONTROL pins (see Figure 2). When the CONTROL pin
voltage reaches approximately 5.6 V relative to the SOURCE Duty Cycle
pin, the high-voltage current source is turned off, the internal
control circuitry is activated and the high-voltage internal
Auto-restart
MOSFET starts to switch. At this point, the charge stored on
77%
C1 is used to supply the internal consumption of the chip.

As the output voltage, and therefore the reflected voltage
30%
across the primary transformer winding ramp up, the feedback
CONTROL current IC increases. As shown in Figure 4, the
internal current limit increases with IC and reaches ILIM when IC 3.8%
is equal to IDCT. The internal current limit vs. IC characteristic ICD1 IDCS
is designed to provide an approximately constant power supply CONTROL Current IC
output current as the power supply output voltage rises. Frequency
Constant Voltage (CV) Operation Auto-restart
2 When IC exceeds IDCS, typically 2 mA (Figure 4), the maximum

duty cycle is reduced. At a value of IC that depends on power
fOSC
supply input voltage, the duty cycle control limits LinkSwitch fOSC(low)
peak current below the internal current limit value. At this point
CONTROL Current IC
approximately equal to IDCT when VOUT is at the desired value
at the minimum power supply input voltage. The final choice PI-2799-112102
When the duty cycle drops below approximately 4%, the Figure 4. CONTROL Characteristics.
LinkSwitch
D S
Auto-Restart Operation
C C1
When a fault condition, such as an output short circuit or open
loop, prevents flow of an external current into the CONTROL C2
R1
pin, the capacitor C1 discharges towards 4.7 V. At 4.7 V, auto-
C4 VOUT
restart is activated, which turns the MOSFET off and puts the
VIN D1
control circuitry in a low current fault protection mode. In
auto-restart, LinkSwitch periodically restarts the power supply R2
D2
so that normal power supply operation can be restored when
the fault is removed. PI-2715-112102
Figure 5. Power Supply Outline Schematic.
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LNK501
The characteristics described above provide an approximate from Figure 5 by the addition of R3, C3 and optocoupler U1.
CV/CC power supply output without the need for secondary Resistor R3 forms a potential divider with R1 to limit the U1
side voltage or current feedback. The output voltage regulation collector emitter voltage.
is influenced by how well the voltage across C2 tracks the
reflected output voltage. This tracking is influenced by the On the secondary side, the addition of voltage sense circuit
value of the transformer leakage inductance which introduces components R4, VR1 and U1 LED provide the voltage feedback
an error. Resistor R2 and capacitor C2 partially filter the signal. In the example shown, a simple Zener (VR1) reference
leakage inductance voltage spike, reducing this error. This is used though a precision TL431 reference is typically needed
circuitry, used with standard transformer construction to provide ±5% output voltage tolerancing and cable drop
techniques, provides much better output load regulation than a compensation, if required. Resistor R4 provides biasing for VR1.
linear transformer, making this an ideal power supply solution The regulated output voltage is equal to the sum of the VR1
in many low power applications. If tighter load regulation is Zener voltage plus the forward voltage drop of the U1 LED.
required, an optocoupler configuration can be used while still Resistor R5 is an optional low value resistor to limit U1 LED
employing the constant output current characteristics provided peak current due to output ripple. Manufacturerʼs specifications
by LinkSwitch. for U1 current and VR1 slope resistance should be consulted
to determine whether R5 is required.
Optional Secondary Feedback
Figure 6 shows a typical power supply outline schematic using U1 is arranged with collector connected to primary ground and
LinkSwitch with optocoupler feedback to improve output emitter to the anode of D1. This connection keeps the opto in
voltage regulation. On the primary side, the schematic differs an electrically “quiet” position in the circuit. If the opto was
LinkSwitch
D S
VOUT
LNK501 C C1
R5
C2
R1 U1
85-265 R4
VAC R2
D1
U1
VR1 2
R3 C3
RTN
PI-2787-112102
Output Voltage
Inherent
Voltage
Characteristic with
optocoupler
Load variation
during battery
charging
Output Current
PI-2788-092101
2-79
Rev. I 02/05
LNK501
instead placed on the cathode side of D1, it would become a The extent to which R3 can be increased is limited by opto
switching node, generating additional common mode EMI transistor voltage and dissipation ratings and should be fully
currents through its internal parasitic capacitance. tested before finalizing a design. The values of C2 and C3 are
less important other than to make sure they are large enough
The feedback configuration in Figure 6 is simply a resistive to have very little influence on the impedance of the voltage
divider made up of R1 and R3 with D1, R2, C1 and C2 rectifying, division circuit set up by R1, R3 and U1 at the switching
filtering and smoothing the primary winding voltage signal. The frequency. Normally, the values of C2 and C3 in Figure 6 are
optocoupler therefore effectively adjusts the resistor divider ratio chosen equal to the value of C2 in Figure 5, though the voltage
to control the DC voltage across R1 and therefore, the feedback rating may be reduced depending on the relative values of R1
current received by the LinkSwitch CONTROL pin. and R2 discussed above. See Applications section for typical
values of components.
When the power supply operates in the constant current (CC)
region, for example when charging a battery, the output voltage Figure 7 shows the influence of optocoupler feedback on the
is below the voltage feedback threshold defined by U1 and output characteristic. The envelope defined by the dashed lines
VR1 and the optocoupler is fully off. In this region, the circuit represent the worst case power supply DC output voltage and
behaves exactly as previously described with reference to current tolerances (unit-to-unit and over the input voltage
Figure 5 where the reflected voltage increases with increasing range) if an optocoupler is not used. A typical example of an
output voltage and the LinkSwitch internal current limit is inherent (without optocoupler) output characteristic is shown
adjusted to provide an approximate CC output characteristic. dotted. This is the characteristic that would result if U1, R4 and
Note that for similar output characteristics in the CC region, VR1 were removed. The optocoupler feedback results in the
the value of R1 in Figure 5 will be equal to the value of R1+R3 characteristic shown by the solid line. The load variation arrow in
in Figure 6. Figure 7 represents the locus of the output characteristic normally
seen during a battery charging cycle. The two characteristics
When the output reaches the voltage feedback threshold set by are identical as the output voltage rises but then separate as
U1 and VR1, the optocoupler turns on. Any further increase shown when the voltage feedback threshold is reached. This
in the power supply output voltage results in the U1 transistor is the characteristic seen if the voltage feedback threshold is
current increasing, which increases the percentage of the above the output voltage at the inherent CC to CV transition
reflected voltage appearing across R1. The resulting increase point also indicated in Figure 7.
in the LinkSwitch CONTROL current reduces the duty cycle
according to Figure 4 and therefore, maintains the output Figure 8 shows a case where the voltage feedback threshold is
2 voltage regulation. set below the voltage at the inherent CC to CV transition point.
In this case, as the output voltage rises, the secondary feedback
Normally, R1 and R3 are chosen to be equal in value. However, circuit takes control before the inherent CC to CV transition
increasing R3 (while reducing R1 to keep R1 + R3 constant) occurs. In an actual battery charging application, this simply
increases loop gain in the CV region, improving load regulation. limits the output voltage to a lower value.
Output Voltage
transition
Typical inherent
point
Voltage optocoupler
VO(MAX)
Power supply peak
output power curve
Load variation
during battery
2-80
Rev. I 02/05
LNK501
However, in laboratory bench tests, it is often more convenient The secondary of the transformer is rectified and filtered by D6
to test the power supply output characteristic starting from a and C5 to provide the DC output to the load.
low output current and gradually increasing the load. In this
case, the optocoupler feedback regulates the output voltage until LinkSwitch dramatically simplifies the secondary side by
the peak output power curve is reached as shown in Figure 8. controlling both the constant voltage and constant current regions
Under these conditions, the output current will continue to rise entirely from the primary side. This is achieved by monitoring
until the peak power point is reached and the optocoupler turns the primary-side VOR (voltage output reflected).
off. Once the optocoupler is off, the CONTROL pin feedback
current is determined only by R1 and R3 and the output current Diode D5 and capacitor C4 form the primary clamp network.
therefore folds back to the inherent CC characteristic as shown. This both limits the peak drain voltage due to leakage inductance
Since this type of load transition does not normally occur in a and provides a voltage across C4, which is equal to the VOR plus
battery charger, the output current never overshoots the inherent an error due to the parasitic leakage inductance. Resistor R2
constant current value in the actual application. filters the leakage inductance spike and reduces the error in the
value of the VOR. Resistor R1 converts this voltage into a current
In some applications it may be necessary to avoid any output that is fed into the CONTROL pin to regulate the output.
current overshoot, independent of the direction of load variation.
To achieve this goal, the minimum voltage feedback threshold During CV operation the output is regulated through control of
should be set at VO(MAX). This will ensure that the voltage at the the duty cycle. As the current into the CONTROL pin exceeds
CC to CV transition point of the inherent characteristic will approximately 2 mA, the duty cycle begins to reduce, reaching
always occur below the voltage feedback threshold. However, the 30% at a CONTROL pin current of 2.3 mA.
output voltage tolerance is then increased, since the inherent CV
characteristic tolerance below VO(MAX) is added to the tolerance Under light or no-load conditions, when the duty cycle reaches
of the optocoupler feedback circuit. approximately 4%, the switching frequency is reduced to lower
energy consumption.
Applications Example
If the output load is increased beyond the peak power point
The circuit shown in Figure 9 shows a typical implementation (defined by 0.5·LP·ILIM2·f), the output voltage and VOR falls.
of an approximate constant voltage / constant current (CV/CC) The reduced CONTROL pin current will lower the internal
charger using LinkSwitch. This design delivers 2.75 W with LinkSwitch current limit (current limit control) providing an
a nominal peak power point voltage of 5.5 V and a current of approximately constant current output characteristic. If the
500 mA. Efficiency is greater than 70% over an input range load is increased and the CONTROL pin current falls below 2
of 85 VAC to 265 VAC. approximately 1 mA, the CONTROL pin capacitor C3 will
discharge and the supply enters auto-restart.
The bridge rectifier, BR1, rectifies the AC input. Resistor RF1
is a fusible type providing protection from primary side short Current limit control removes the need for any secondary side
circuits. The rectified AC is smoothed by C1 and C2 with current sensing components (sense resistor, transistor, opto
inductor L1 forming a pi-filter in conjunction with C1 and C2 coupler and associated components). Removing the secondary
to filter conducted EMI. The switching frequency of 42 kHz sense circuit dramatically improves efficiency, giving the
allows such a simple EMI filter to be used without the need for a associated benefit of reduced enclosure size.
Y-capacitor while still meeting international EMI standards.
When power is applied, high-voltage DC appears at the DRAIN Key Application Considerations
pin of LinkSwitch (U1). The CONTROL pin capacitor C3 is then Design Output Power
charged through a switched high-voltage current source connected
internally between the DRAIN and CONTROL pins. When Table 1 (front page) shows the maximum continuous output
the CONTROL pin reaches approximately 5.6 V relative to the power that can be obtained under the following conditions:
SOURCE pin, the internal current source is turned off. The internal
control circuitry is activated and the high-voltage MOSFET starts 1. The minimum DC input bus voltage is 90 V or higher.
to switch, using the energy in C3 to power the IC. This corresponds to a filter capacitor of 3 µF/W for
universal input and 1 µF/W for 230 VAC or 115 VAC
When the MOSFET is on, the high-voltage DC bus is connected input with doubler input stage.
to one end of the transformer primary, the other end being
2. Design is a discontinuous mode flyback converter, with
connected to primary return. As the current ramps in the
nominal primary inductance value and a VOR in the range
primary of flyback transformer T1, energy is stored. This
40 V to 60 V. Continuous mode designs can result in loop
energy is delivered to the output when the MOSFET turns off
instability and are therefore not recommended.
each switching cycle.
2-81
Rev. I 02/05
LNK501
U1
LNK501
L1 LinkSwitch 5.5 V,
1 mH T1 500 mA
D S 1 5
C C3
0.22 µF
50 V 15 T
116 T 4 #30 AWG C5
BR1 #34 AWG TIW 470 µF
10 V
RF1 1 A, 600 V R1 C4
10 Ω 1 W 20.5 kΩ 0.1 µF
Fusible 1% 100 V
C1 3 6 RTN
C2 D6
85-265 4.7 µF 4.7 µF 11DQ06
VAC 400 V 400 V EE13
D5 LP = 2.55 mH
1N4937
R2 PERFORMANCE SUMMARY
100 Ω
Efficiency: ≥72%
No Load
200 mW, 115 VAC
PI-2904-080304
Figure 9. 2.75 W Constant Voltage/Constant Current (CV/CC) Charger using LinkSwitch.
10
PI-2964-112702
9 VIN = 85 VAC
2 VIN = 115 VAC

VIN = 185 VAC
8
VIN = 265 VAC
7
6
Output Voltage (V)
0
0 100 200 300 400 500 600 700
Output Current (mA)
2-82
Rev. I 02/05
LNK501
3. A secondary output of 5 V with a Schottky rectifier diode. Core gaps should be uniform. Uneven core gapping, especially
4. Assumed efficiency of 70%. with small gap sizes, may cause variation in the primary
inductance with flux density (partial saturation) and make the
5. The part is board mounted with SOURCE pins soldered to constant current region non-linear. To verify uniform gapping
sufficient area of copper to keep the die temperature at or it is recommended that the primary current wave-shape be
below 100 °C. examined while feeding the supply from a DC source. The
6. An output cable with a total resistance of 0.2 Ω. gradient is defined as di/dt = V/L and should remain constant
throughout the MOSFET on time. Any change in gradient of
In addition to the thermal environment (sealed enclosure, the current ramp is an indication of uneven gapping.
ventilated, open frame, etc), the maximum power capability
of LinkSwitch in a given application depends on transformer Measurements made using a LCR bridge should not be solely
core size, efficiency, primary inductance tolerance, minimum relied upon; typically these instruments only measure at currents
specified input voltage, input storage capacitance, output voltage, of a few milliamps. This is insufficient to generate high enough
output diode forward drop, etc., and can be different from the flux densities in the core to show uneven gapping.
values shown in Table 1.
For a typical EE13 core using center leg gapping, a 0.08 mm
In designs not required to meet 300 mW no-load consumption, gap (ALG of 190 nH/t2) allows a primary inductance tolerance of
the transformer can be designed with higher VOR to extend power ±10% to be maintained in standard high volume production.
capability as noted in the following section. This allows the EE13 to be used in designs up to 2.75 W with
less than 300 mW no-load consumption. If film gapping is
Transformer Design used then this increases to 3 W. Moving to a larger core, EE16
To provide an approximately CV/CC output, the transformer for example, allows a 3 W output with center leg gapping.
should be designed to be discontinuous; all the energy stored
in the transformer is transferred to the secondary during the The transformer turns ratio should be selected to give a VOR
MOSFET off time. Energy transfer in discontinuous mode is (output voltage reflected through secondary to primary turns
independent of line voltage. ratio) of 40 V to 60 V. In designs not required to meet 300 mW
no-load consumption targets, the transformer can be designed
The peak power point prior to entering constant current operation with higher VOR as long as discontinuous mode operation is
is defined by the maximum power transferred by the transformer. maintained. This increases the output power capability. For
The power transferred is given by the expression P = 0.5·LP·I2·f, example, a 230 VAC input design using an EE19 transformer
where LP is the primary inductance, I2 is the primary peak current core with VOR >70 V, is capable of delivering up to 5 W typical 2
squared and f is the switching frequency. output power. Note: the linearity of the CC region of the power
supply output characteristic is influenced by VOR. If this is an
To simplify analysis, the data sheet parameter table specifies an important aspect of the application, the output characteristic
I2f coefficient. This is the product of current limit squared and should be checked before finalizing the design.
switching frequency normalized to the feedback parameter IDCT.
This provides a single term that specifies the variation of the Output Characteristic Variation
peak power point in the power supply due to LinkSwitch. Both the device tolerance and external circuit govern the overall
tolerance of the LinkSwitch output characteristic. Estimated
As primary inductance tolerance is part of the expression peak power point tolerances for a 2.75 W design are ±10% for
that determines the peak output power point (start of the CC voltage and ±20% for current limit for overall variation in high
characteristic) this parameter should be well controlled. For volume manufacturing. This includes device and transformer
an estimated overall constant current tolerance of ±20% the tolerances and line variation. Lower power designs may have
primary inductance tolerance should be ±10% or better. This poorer constant current linearity.
is achievable using standard low cost, center leg gapping
techniques where the gap size is typically 0.08 mm or larger. As the output load reduces from the peak power point, the
Smaller gap sizes are possible but require non-standard, tighter output voltage will tend to rise due to tracking errors compared
ferrite AL tolerances. to the load terminals. Sources of these errors include the
output cable drop, output diode forward voltage and leakage
Other gapping techniques such as film gapping allow tighter inductance, which is the dominant cause. As the load reduces,
tolerances (±7% or better) with associated improvements in the primary operating peak current reduces, together with the
the tolerance of the peak power point. Please consult your leakage inductance energy, which reduces the peak charging
transformer vendor for guidance. of the clamp capacitor. With a primary leakage inductance of
50 µH, the output voltage typically rises 30% over a 100% to
5% load change.
2-83
Rev. I 02/05
LNK501
At very light or no-load, typically less than 2 mA of output current, ratio (a typical VOR of 50 V requires a diode PIV of 50 V).
the output voltage rises due to leakage inductance peak charging Slow recovery diodes are not recommended (1N400X types).
of the secondary. This voltage rise can be reduced with a small
preload with little change to no-load power consumption. Output Capacitor – C4
Capacitor C4 should be selected such that its voltage and ripple
The output voltage load variation can be improved across the current specifications are not exceeded.
whole load range by adding an optocoupler and secondary
reference (Figure 6). The secondary reference is designed to only LinkSwitch Layout Considerations
provide feedback above the normal peak power point voltage
to maintain the correct constant current characteristic. Primary Side Connections
Since the SOURCE pins in a LinkSwitch supply are switching
Component Selection nodes, the copper area connected to SOURCE together with C1,
C2 and R1 (Figure 5) should be minimized, within the thermal
The schematic shown in Figure 5 outlines the key components contraints of the design, to reduce EMI coupling.
needed for a LinkSwitch supply.
The CONTROL pin capacitor C1 should be located as close as
Clamp Diode – D1 possible to the SOURCE and CONTROL pins.
Diode D1 should be either a fast (trr <250 ns) or ultrafast type
(trr <50 ns), with a voltage rating of 600 V or higher. Fast To minimize EMI coupling from the switching nodes on the
recovery types are preferred, being typically lower cost. Slow primary to both the secondary and AC input, the LinkSwitch
diodes are not recommended; they can allow excessive DRAIN should be positioned away from the secondary of the transformer
ringing and the LinkSwitch to be reverse biased. and AC input.
Clamp Capacitor – C2 Routing the primary return trace from the transformer primary
Capacitor C2 should be a 0.1 µF, 100 V capacitor. Low cost around LinkSwitch and associated components further reduces
metallized plastic film types are recommended. The tolerance coupling.
of this part has a very minor effect on the output characteristic
so any of the standard ±5%, ±10% or ±20% tolerances are Y-Capacitor
acceptable. Ceramic capacitors are not recommended. The If a Y-type cap is required, it should be connected close to the
common dielectrics used such as Y5U or Z5U are not stable transformer secondary output return pin(s) and the primary bulk
2 with voltage or temperature and may cause output instability. capacitor negative return. Such placement will maximize the
Ceramic capacitors with high stability dielectrics may be used EMI benefit of the Y-type cap and avoid problems in common-
but are expensive compared to metallized film types. mode surge testing.
CONTROL Pin Capacitor – C1 Quick Design Checklist

Capacitor C1 is used during startup to power LinkSwitch and
sets the auto-restart frequency. For designs that have a battery As with any power supply design, all LinkSwitch designs
load this component should have a value of 0.22 µF and for should be verified on the bench to make sure that component
resistive loads a value of 1 µF. This ensures there is sufficient specifications are not exceeded under worst case conditions.
time during startup for the output voltage to reach regulation. Note: In a LinkSwitch circuit, the SOURCE is a switching
Any capacitor type is acceptable with a voltage rating of node. This should be taken into consideration during testing.
10 V or above. Oscilloscope measurements should be made with probe grounded
to DC voltages such as primary return or DC rail but not to
Feedback Resistor – R1 SOURCE. Power supply input voltage should always be supplied
The value of R1 is selected to give a feedback current into the using an isolation transformer. The following minimum set of
CONTROL pin of approximately 2.3 mA at the peak output tests is strongly recommended:
power point of the supply. The actual value depends on the VOR
selected during design. Any 1%, 0.25 W resistor is suitable. 1. Maximum drain voltage – Verify that VDS does not exceed
675 V at highest input voltage and peak output power.
Output Diode – D2
Either PN fast, PN ultrafast or Schottky diodes can be used 2. Maximum drain current – At maximum ambient temperature,
depending on the efficiency target for the supply, Schottky maximum input voltage and peak output power, verify drain
diodes giving higher efficiency then PN diodes. The diode current waveforms at startup for any signs of transformer
voltage rating should be sufficient to withstand the output saturation and excessive leading edge current spikes.
voltage plus the input voltage transformed through the turns LinkSwitch has a minimum leading edge blanking time of
2-84
Rev. I 02/05
LNK501
200 ns to prevent premature termination of the on-cycle. 4. Centered output characteristic – Using a transformer with
Verify that the leading edge current spike event is below nominal primary inductance and at an input voltage midway
current limit at the end of the 200 ns blanking period. between low and high line, verify that the peak power point
occurs at the desired nominal output current, with the correct
3. Thermal check – At peak output power, minimum input output voltage. If this does not occur then the design should
voltage and maximum ambient temperature, verify that the be refined to ensure the overall tolerance limits are met.
temperature specifications are not exceeded for LinkSwitch,
transformer, output diode and output capacitors. Enough Design Tools
thermal margin should be allowed for part-to-part variation of
the RDS(ON) of LinkSwitch as specified in the data sheet. Under Up-to-date information on design tools can be found at the
low line, peak power, a maximum LinkSwitch SOURCE pin Power Integrations website: www.powerint.com.
temperature of 100 °C is recommended to allow for these
variations.
Input Filter
Capacitor
C S D
+
LinkSwitch
HV DC
Input
-
Transformer S S S S
2
Y1-
Capacitor
DC Out
Output
Capacitor
PI-2900-070202
Figure 11. Recommended Circuit Board Layout for LinkSwitch using P Package.
2-85
Rev. I 02/05
LNK501

THERMAL IMPEDANCE
Conditions
See Figure 12
CONTROL FUNCTIONS
Switching
fOSC IC = IDCT, TJ = 25 °C 38 42 46 kHz
Frequency
2 Duty Cycle at Low

Switching DCLF
2.4 3.8 5.2 %
Frequency
Low Frequency
Duty Cycle Range
Maximum Duty
DCMAX IC = 1.5 mA 74 77 80 %
Cycle
CONTROL Pin
TJ = 25 °C
Current at 30% IDCT
See Figure 4
2.24 2.30 2.36 mA
Duty Cycle
CONTROL Pin
Voltage
Dynamic
ZC IC = IDCT, TJ = 25 °C 60 90 120 Ω
Impedance
2-86
Rev. I 02/05
LNK501
Conditions
See Figure 12
CONTROL Pin VC = 0 V -4.5 -3.25 -2

mA
Auto-Restart
VC(AR) 5.6 V
Threshold Voltage
Auto-Restart
VC(AR)hyst 0.9 V
Hysteresis Voltage
DC(AR) 8 %
f(AR) 300 Hz
CIRCUIT PROTECTION
TJ = 25 °C
Self-Protection
ILIM di/dt = 90 mA/µs 241 254 267 mA
Current Limit See Note C
TJ = 25 °C
I f Coefficient
2 I2 f di/dt = 90 mA/µs 2547 2710 2873 A2Hz
See Notes C, D 2
Current Limit at
Auto-Restart
Power Up Reset
VC(RESET) 1.5 2.75 4.0 V
Threshold Voltage
Leading Edge
Blanking Time
Thermal Shutdown
IC = IDCT 125 135 °C
Temperature
Thermal Shutdown
70 °C
Hysteresis
2-87
Rev. I 02/05
LNK501
Conditions
See Figure 12
OUTPUT
IDSS 50 µA
See Note B
VC = 6.2 V, TA = 25 °C
700 V
DRAIN Supply
See Note E 36 50 V
Voltage
NOTES:
A. For specifications with negative values, a negative temperature coefficient corresponds to an increase in magnitude with
increasing temperature, and a positive temperature coefficient corresponds to a decrease in magnitude with increasing
temperature.
B. Breakdown voltage may be checked against minimum BVDSS specification by ramping the DRAIN pin voltage up to but not
C. IC is increased gradually to obtain maximum current limit at di/dt of 90 mA/µs. Increasing IC further would terminate the cycle
through duty cycle control.
D. This parameter is normalized to IDCT to correlate to power supply output current (it is multiplied by IDCT(nominal)/IDCT).
E. It is possible to start up and operate LinkSwitch at DRAIN voltages well below 36 V. However, the CONTROL pin charging
2 current is reduced, which affects startup time, auto-restart frequency, and auto-restart duty cycle. Refer to the characteristic
graph on CONTROL pin charge current (IC) vs. DRAIN voltage (Figure 13) for low voltage operation characteristics.
2-88
Rev. I 02/05
LNK501
750 Ω LinkSwitch
D S
S1
S
S S
10 kΩ
C S
S2
40 V 40 V C1
0.22 µF
PI-2894-031004
2
PI-2901-071602
VC = 5.15 V
1.6
CONTROL Pin
1.2
0.8
0.4 2
0
0 20 40 60 80 100
DRAIN Voltage (V) Figure 14. Duty Cycle Measurement.
Figure 13. IC vs. DRAIN Voltage.
120 90
PI-2895-102303
PI-2902-051904
80
100
70
Duty Cycle (%)
80 60
50
60
40
40 30
20
20
10
0 0
0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 2.15 2.25 2.35 2.45 2.55 2.65
CONTROL Pin Voltage (V) CONTROL Pin Current (mA)
Figure 15. CONTROL Pin I-V Characteristic. Figure 16. Duty Cycle vs. CONTROL Pin Current.
2-89
Rev. I 02/05
LNK501
1.1 1.200
PI-2213-012301
PI-2896-062802
1.000

Switching Frequency
Breakdown Voltage
0.800
1.0 0.600
0.400
0.200
0.9 0.000
-50 -25 0 25 50 75 100 125 150 -50 0 50 100 150
Figure 17. Breakdown Voltage vs. Temperature. Figure 18. Switching Frequency vs. Temperature.
1.200 1.2
PI-2897-062802
PI-2910-071602
1.000 1.0

Current Limit
I2f Coefficient
0.800 0.8
0.600 0.6
0.400 0.4
2 0.200 0.2
0.000 0.0
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
Figure 19. Current Limit vs. Temperature. Figure 20. I f Coefficient vs. Temperature. 2
1.200 1.2
PI-2899-062802
PI-2898-062802

1.000 1
0.800 0.8
0.600 0.6
0.400 0.4
0.200 0.2
0.000 0
-50 0 50 100 150 -50 0 50 100 150
Junction Temperature (°C) Temperature (°C)
Figure 21. IDCT vs. Temperature. Figure 22. PWM Gain vs. Temperature.
2-90
Rev. I 02/05
LNK501
300
PI-2222-031401
TCASE=25 °C
250 TCASE=100 °C
Drain Current (mA)

200
150
100
50
0
0 2 4 6 8 10
Drain Voltage (V)
Figure 23. Output Characteristics (DRAIN Current vs.
DRAIN Voltage).

Series Number
Package Identifier
P
Lead Finish
Plastic DIP
2
Revision Notes Date

D 1) Released Final Data Sheet. 7/02
E 1) Enhanced tolerance with optocoupler designs. 8/02
2) Updated P and G packages thermal impedance.
F 1) Corrected minor errors in text and figures. 9/02
2) Updated Figure 6 and text description.
G 1) Updated DIP-8B and SMD-8B package descriptions. 4/03
2) Updated Table 1 with no-load conditions.
3) Corrected minor errors in text and figures.
H 1) Added lead-free ordering information. 12/04
I 1) Minor error and formatting corrections. 2/05
2-91
Rev. I 02/05
LNK520
LNK520
LinkSwitch® Family
Energy Efficient, CV or CV/CC Switcher for
Very Low Cost Adapters and Chargers
Product Highlights +
DC
Cost Effective Linear/RCC Replacement Output
(VO)
• Lowest cost and component count, constant voltage (CV)
or constant voltage/constant current (CV/CC) solutions
• Optimized for bias winding feedback Wide Range
HV DC Input
D
• Primary based CV/CC solution eliminates 10 to 20 LinkSwitch
C
secondary components for low system cost
• Fully integrated auto-restart for short circuit and open S
loop fault protection – saves external component costs (a)

• 42 kHz operation with optimized switching Example Characteristic
VO Min VO
characteristics for significantly reduced EMI Typ
(CV only) (CV/CC)
±5%
Much Higher Performance Over Linear/RCC ±10%
• Universal input range allows worldwide operation
• Up to 70% reduction in power dissipation – reduces
enclosure size significantly
• CV/CC output characteristic without secondary feedback IO IO
±24%* ±24%*
(b)
• System level thermal and current limit protection For Circuit With Optional
• Meets all single point failure requirements with only one Shown Above Secondary Feedback**
additional bias capacitor *Estimated tolerance achievable in high volume production (external
components with ±7.5% transformer inductance tolerance included).
• Controlled current in CC region provides inherent soft-start
2 • Optional opto feedback improves output voltage accuracy
**See Optional Secondary Feedback section. PI-3853-030404
PI-3577-080603
® Figure 1. (a) Typical Application – not a Simplified Circuit and

EcoSmart – Extremely Energy Efficient (b) Output Characteristic Tolerance Envelopes.
• Consumes <300 mW at 265 VAC input with no load
• Meets California Energy Commission (CEC), ENERGY OUTPUT POWER TABLE1
STAR, and EU requirements
230 VAC ±15% 85-265 VAC No-Load
• No current sense resistors–maximizes efficiency PRODUCT4 Input
Min2 Typ2 Min2 Typ2 Power
Applications
• Linear transformer replacement in all ≤3 W applications LNK520 3.3 W 4 W 2.4 W 3 W <300 mW
• Chargers for cell phones, cordless phones, PDAs, digital P or G 4.2 W 5.5 W 2.9 W 3.5 W <500 mW3
cameras, MP3/portable audio devices, shavers, etc. Table 1. Output Power Table.
• Home appliances, white goods and consumer electronics Notes:
• Constant output current LED lighting applications 1. Output power for designs in an enclosed adapter measured at
• TV standby and other auxiliary supplies 50 °C ambient.
2. See Figure 1 (b) for Min (CV only designs) and Typ (CV/CC
charger designs) power points identified on output characteristic.
Description 3. Uses higher reflected voltage transformer designs for increased
power capability – see Key Application Considerations section.
LinkSwitch is specifically designed to replace low power linear 4. For lead-free package options, see Part Ordering Information.
transformer/RCC chargers and adapters at equal or lower system
cost with much higher performance and energy efficiency. <300 mW no-load consumption, a LinkSwitch solution can
LNK520 is equivalent to LNK500 but optimized for use with bias save the end user enough energy over a linear design to
winding feedback and has improved switching characteristics completely pay for the full power supply cost in less than
for significantly reduced EMI. In addition, if bias and output one year. LinkSwitch integrates a 700 V power MOSFET,
windings are magnetically well coupled, output voltage load PWM control, high-voltage startup, current limit, and thermal
regulation can be improved. With efficiency of up to 75% and shutdown circuitry, onto a monolithic IC.
2-92
Rev. E 02/05
LNK520
0 DRAIN
CONTROL VC
INTERNAL
1 SUPPLY
ZC
SHUTDOWN/
+ ADJUST
- ÷8
5.6 V -
4.7 V CURRENT LIMIT
+ 5.6 V COMPARATOR
+
I FB HYSTERETIC
THERMAL
SHUTDOWN
OSCILLATOR
D MAX
CLOCK S Q
SAW - R
+
PWM
COMPARATOR
IDCS
LEADING
EDGE
EDGE
LOW BLANKING
RE FREQUENCY
OPERATION
SOURCE
PI-2777-032503
Figure 2. Block Diagram.

2
LNK520
DRAIN (D) Pin:
current.
S 3
PI-3790-121503
SOURCE (S) Pin:
point.
2-93
Rev. E 02/05
LNK520

Auto-restart
The duty cycle, current limit and operating frequency
Figure 4. Figure 5 shows a typical power supply schematic outline
which is used below to describe the LinkSwitch operation.
Power Up
pin capacitor C1 is charged through a switched high-voltage
current source connected internally between the DRAIN and
CONTROL pins (see Figure 2). When the CONTROL pin voltage CONTROL Current IC IDCT
reaches approximately 5.6 V relative to the SOURCE pin, the
high-voltage current source is turned off, the internal control Duty Cycle
circuitry is activated and the high-voltage internal MOSFET

starts to switch. At this point, the charge stored on C1 is used Auto-restart
to supply the internal consumption of the chip. 77%

As the output voltage, and therefore the reflected voltage across
the transformer bias winding ramp up, the feedback CONTROL 30%
current IC flowing through R1 increases. As shown in Figure 4,
the internal current limit increases with IC and reaches ILIM when
3.8%
IC is equal to IDCT. The internal current limit vs. IC characteristic ICD1
is designed to provide an approximately constant power supply IDCS
CONTROL Current IC
output current as the power supply output voltage rises.
Frequency
Constant Voltage (CV) Operation

When IC exceeds IDCS, typically 2 mA (Figure 4), the maximum Auto-restart
2 duty cycle is reduced. At a value of IC that depends on power

supply input voltage, the duty cycle control limits LinkSwitch
fOSC
peak current below the internal current limit value. At this point fOSC(low)
approximately equal to IDCT when VOUT is at the desired value CONTROL Current IC
at the minimum power supply input voltage. The final choice
PI-3579-031004
When the duty cycle drops below approximately 4%, the Figure 4. CONTROL Characteristics.
D1
Auto-Restart Operation VOUT

R3 C3
When a fault condition, such as an output short circuit or open C4
loop, prevents flow of an external current into the CONTROL

pin, the capacitor C1 discharges towards 4.7 V. At 4.7 V, auto- D3
restart is activated, which turns the MOSFET off and puts the D2
VIN
control circuitry in a low current fault protection mode. In LinkSwitch D
R2
auto-restart, LinkSwitch periodically restarts the power supply IC R1
so that normal power supply operation can be restored when C
C1 C2
the fault is removed. S
PI-3578-021405
Figure 5. Power Supply Schematic outline.
2-94
Rev. E 02/05
LNK520
T1 D1 VOUT
R3 C3
C4 VR1
RTN
85-265
VAC D3
D2 R2 R4
C2 R5
LinkSwitch
LNK520 D R1
C U1
S
C1
PI-3703-030404
Figure 6. Power Supply Schematic Outline with Optocoupler Feedback, Providing Tight CV Regulation.
The characteristics described above provide an approximate for U1 current and VR1 slope resistance should be consulted
CV/CC power supply output without the need for secondary side to determine whether R5 is required.
voltage or current feedback. The output voltage regulation is
influenced by how well the voltage across C2 tracks the reflected When the power supply operates in the constant current (CC)
output voltage. This tracking is influenced by the coupling region, for example at startup and when charging a battery, the
between transformer output and bias windings. Tight coupling output voltage is below the voltage feedback threshold defined by
improves CV regulation and requires only a low value for resistor U1 and VR1 and the optocoupler is fully off. In this region, the
R2. Poor coupling degrades CV regulation and requires a higher circuit behaves exactly as previously described with reference to
value for R2 to filter leakage inductance spikes on the bias Figure 5 where the voltage across C2 and therefore the current
winding voltage waveform. This circuitry, used with standard flowing through R1 increases with increasing output voltage 2
transformer construction techniques, provides much better and the LinkSwitch internal current limit is adjusted to provide
output load regulation than a linear transformer, making this an an approximate CC output characteristic.
ideal power supply solution in many low power applications.
If even tighter load regulation is required, an optocoupler When the output reaches the voltage feedback threshold set by
configuration can be used while still employing the constant U1 and VR1, the optocoupler turns on. Any further increase
output current characteristics provided by LinkSwitch. in the power supply output voltage results in the U1 transistor
current increasing. The resulting increase in the LinkSwitch
Optional Secondary Feedback CONTROL current reduces the duty cycle according to
Figure 6 shows a typical power supply schematic outline using Figure 4 and therefore, maintains the output voltage
LinkSwitch with optocoupler feedback to improve output voltage regulation.
regulation. On the primary side, the schematic only differs
from Figure 5 by the addition of optocoupler U1 transistor in Figure 7 shows the influence of optocoupler feedback on the
parallel to R1. output characteristic. The envelope defined by the dashed lines
represent the worst-case power supply DC output voltage and
On the secondary side, the addition of voltage sense circuit current tolerances (unit-to-unit and over the input voltage range)
components R4, VR1 and U1 LED provide the voltage feedback if an optocoupler is not used. A typical example of an inherent
signal. In the example shown, a simple Zener (VR1) reference (without optocoupler) output characteristic is shown dotted.
is used though more accurate references may be employed for This is the characteristic that would result if U1, R4, R5 and
improved output voltage tolerancing and to provide cable drop VR1 were removed. The optocoupler feedback results in the
compensation, if required. Resistor R4 provides biasing for VR1. characteristic shown by the solid line. The load variation arrow in
The regulated output voltage is equal to the sum of the VR1 Figure 7 represents the locus of the output characteristic normally
Zener voltage plus the forward voltage drop of the U1 LED. seen during a battery charging cycle. The two characteristics
Resistor R5 is an optional low value resistor to limit U1 LED are identical as the output voltage rises but then separate as
peak current due to output ripple. Manufacturerʼs specifications shown when the voltage feedback threshold is reached. This
2-95
Rev. E 02/05
LNK520
Output Voltage
Inherent
Voltage
Characteristic with
optocoupler
Load variation
during battery
charging
Output Current
PI-2788-092101
Output Voltage
transition
Typical inherent
point
Voltage optocoupler
VO(MAX)
2 Power supply peak
output power curve
Load variation
during battery
is the characteristic seen if the voltage feedback threshold is optocoupler feedback regulates the output voltage until the
above the output voltage at the inherent CC to CV transition peak output power curve is reached as shown in Figure 8. Under
point also indicated in Figure 7. these conditions, the output current will continue to rise until the
peak power point is reached and the optocoupler turns off. Once
Figure 8 shows a case where the voltage feedback threshold the optocoupler is off, the CONTROL pin feedback current is
is set below the voltage at the inherent CC to CV transition determined only by R1 and the output current therefore folds
point. In this case, as the output voltage rises, the secondary back to the inherent CC characteristic as shown. Since this type
feedback circuit takes control before the inherent CC to CV of load transition does not normally occur in a battery charger,
transition occurs. In an actual battery charging application, this the output current never overshoots the inherent constant current
simply limits the output voltage to a lower value. However, in value in the actual application.
laboratory bench tests, it is often more convenient to test the
power supply output characteristic starting from a low output In some applications it may be necessary to avoid any output
current and gradually increasing the load. In this case, the current overshoot, independent of the direction of load variation.
2-96
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LNK520
PI-3854-031804
LinkSwitch LNK520
D S
VOUT
C C1 Typical
Characteristic
C2
R1
C4 VOUT
VIN D1
R2
D2
IOUT
(a) (b)
Figure 9. High-side Configuration Using LNK520: (a) Schematic Outline; (b) Typical Output Characteristic Envelope.
To achieve this goal, the minimum voltage feedback threshold In this high-side configuration, the SOURCE pins and circuit
should be set at VO(MAX). This will ensure that the voltage at the board traces form a switching node. Extra care should be taken
CC to CV transition point of the inherent characteristic will to optimize EMI performance. The LNK520 internal MOSFET
always occur below the voltage feedback threshold. However, the switching characteristics have been designed to significantly
output voltage tolerance is then increased, since the inherent CV reduce EMI, particularly in the radiated spectrum (>30 MHz).
characteristic tolerance below VO(MAX) is added to the tolerance However, the SOURCE trace area should be minimized and
of the optocoupler feedback circuit. EMI filter components should be distanced from the SOURCE
node whenever possible. In embedded applications where a
The LNK520 can also be used in the high-side configuration as high-voltage DC input voltage is available, system level EMI
shown in Figure 9(a). This configuration provides a very low filtering is typically located away from the power supply and
component count solution with an approximate CV/CC power circuit board layout is less critical.
supply output characteristic. A typical output characteristic
envelope is shown in Figure 9(b). Applications Example
This configuration is ideal for very low cost charger and adapter The circuit shown in Figure 10 shows a typical implementation
applications where output CC tolerance is loose or unspecified. of an approximate constant voltage / constant current (CV/CC)
charger using LinkSwitch in the low-side configuration. This
2
Typical applications include low cost chargers and adapters
where direct replacement for a linear transformer is required. design delivers 2.75 W with nominal peak power point voltage
In applications with a high-voltage DC input voltage, the circuit of 5.5 V and a current of 500 mA (Figure 11). Efficiency is
is further simplified with the removal of input rectifiers, EMI greater than 65% over an input range of 85 VAC to 265 VAC.
filter choke and input capacitors. Typical applications of this
type include auxiliary supplies in domestic appliances and The bridge rectifier, D1-D4, rectifies the AC input. The rectified
industrial applications. AC is smoothed by C1 and C2, with inductor L1 forming a pi-filter
to filter differential mode conducted EMI. Resistor RF1 is a
In the high-side configuration, the CONTROL pin receives fusible, flameproof type providing protection from primary-side
feedback current through R1 generated by the voltage across short circuits and line surges and provides additional differential
C2. To a first order, this voltage is proportional to VOUT since EMI filtering. The switching frequency of 42 kHz allows such
VOUT is reflected to the primary and appears across C2 during a simple EMI filter to be used without the need for a Y-capacitor
the off time of the LNK520 switching cycle. The output CV while still meeting international EMI standards.
regulation is therefore determined by how well the voltage across
C2 tracks the output voltage. This tracking is influenced by the When power is applied, high-voltage DC appears at the DRAIN
value of the transformer leakage inductance, which introduces pin of LinkSwitch (U1). The CONTROL pin capacitor C5 is
an error. This error, which is partially filtered by R2 and C2, then charged through a switched high-voltage current source
causes a slope in the output CV regulation characteristic. connected internally between the DRAIN and CONTROL
The LNK520 is optimized for use with a bias winding where pins. When the CONTROL pin reaches approximately
tracking of feedback voltage and output voltage is typically 5.6 V relative to the SOURCE pin, the internal current source
better than it is in the high-side configuration of Figure 9 (a). is turned off. The internal control circuitry is activated and the
As a consequence, the increased leakage error in the high-side high-voltage MOSFET starts to switch, using the energy in C5
configuration causes the output current to increase with falling to power the IC.
output voltage, as indicated by the output CC characteristic
envelope in Figure 9 (b).
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LNK520
5.5 V, 500 mA
L1 1 7
R1 D7 C6
1 mH 390 kΩ C4
D1 D2 0.15 A 330 pF 8T 11DQ06 330 µF
1N4005 1N4005 1/4 W 16 V
1 kV
RTN
2 6
RF1
8.2 Ω R2 100T
100 Ω J1
L 2W
D5 5
1N4007GP C3
85 - 265 26T
C1 C2 D6B R3 1 µF
VAC 4.7 µF 4.7 µF 1N4937 15 Ω 50 V
400 V 400 V 4
N LinkSwitch T1
EE16
U1 LP = 2.52 mH
D LNK520P
D3 D4 C
1N4005 1N4005
R4
S C5 6.81 kΩ
220 nF 1%, 1/4 W
PI-3723-111303
Figure 10. 2.75 W Constant Voltage/Constant Current (CV/CC) Charger Using LinkSwitch.
10
PI-3718-092503
85 VAC
9 115 VAC
190 VAC
8 230 VAC
265 VAC
Limits
7
Output Voltage (V)
2 6
0
0 100 200 300 400 500 600 700
Output Current (mA)
The secondary of the transformer is rectified and filtered by Diode D5, C4, R1 and R2 form the primary clamp network.
D7 and C6 to provide the DC output to the load. LinkSwitch This limits the peak DRAIN voltage due to leakage inductance.
dramatically simplifies the secondary side by controlling both Resistor R2 allows the use of a slow, low cost rectifier diode
the constant voltage and constant current regions entirely from by limiting the reverse current through D5 when U1 turns on.
the primary side. This is achieved by monitoring the primary- The selection of a slow diode improves radiated EMI and also
side bias voltage. improves CV regulation, especially at no-load.
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LNK520
The output during CV operation is equal to the primary-side 2. Design is a discontinuous mode flyback converter with
bias voltage multiplied by the turns ratio. The bias voltage, in nominal primary inductance value and a VOR in the range
turn, is the sum of the CONTROL pin voltage (approximately 40 V to 80 V. Continuous mode designs can result in loop
5.7 V), the voltage across the bias feedback resistor R4 and instability and are therefore not recommended.
the forward voltage of D6B. Resistor R3 can be neglected as 3. A secondary output of 5 V with a Schottky rectifier diode.
proportionally the voltage drop across this resistance is small. In 4. Assumed efficiency of 65%.
CV operation, the voltage across R4 is equal to the CONTROL 5. The part is board mounted with SOURCE pins soldered to
pin current, IDCT (2.15 mA) multiplied by the value of R4. sufficient area of copper to keep the die temperature at or
below 100 °C.
As the output load is decreased, the output and therefore 6. An output cable with a total resistance of 0.2 Ω.
bias voltage increase resulting in increased current into the
CONTROL pin. As the current into the CONTROL pin exceeds In addition to the thermal environment (sealed enclosure,
IDCS (~2 mA), the duty cycle begins to reduce, maintaining ventilated, open frame, etc.), the maximum power capability
regulation of the output, reaching 30% at a CONTROL pin of LinkSwitch in a given application depends on transformer
current of 2.15 mA. core size, efficiency, primary inductance tolerance, minimum
specified input voltage, input storage capacitance, output voltage,
Under light or no-load conditions, when the duty cycle reaches output diode forward drop, etc., and can be different from the
approximately 4%, the switching frequency is reduced from values shown in Table 1.
44 kHz to 29 kHz to lower light and no-load input power.
Transformer Design
As the output load is increased, the peak power point (defined by
0.5 • LP • ILIM2 • f) is exceeded. The output voltage and therefore To provide an approximately CV/CC output, the transformer
primary-side bias voltage reduce. The reduction in the bias should be designed to be discontinuous; all the energy stored
voltage results in a proportional reduction of CONTROL pin in the transformer is transferred to the secondary during the
current, which lowers the internal LinkSwitch current limit MOSFET off time. Energy transfer in discontinuous mode is
(current limit control). independent of line voltage.
Constant current (CC) operation controls secondary-side output The peak power point prior to entering constant current
current by reducing the primary-side current limit. The current operation is defined by the maximum power transferred by the
limit reduction characteristic has been optimized to maintain transformer. The power transferred is given by the expression
an approximate constant output current as the output voltage P = 0.5 • LP • I2 • f, where LP is the primary inductance, I2 2
and therefore, bias voltage is reduced. is the primary peak current squared and f is the switching
frequency.
If the load is increased further and the CONTROL pin current
falls below approximately 0.8 mA, the CONTROL pin capacitor To simplify analysis, the data sheet parameter table specifies an
C5 will discharge and LinkSwitch will enter auto-restart I2f coefficient. This is the product of current limit squared and
operation. switching frequency normalized to the feedback parameter IDCT.
This provides a single term that specifies the variation of the
Current limit control removes the need for any secondary- peak power point in the power supply due to LinkSwitch.
side current sensing components (sense resistor, transistor,
optocoupler and associated components). Removing the As primary inductance tolerance is part of the expression
secondary sense circuit dramatically improves efficiency, giving that determines the peak output power point (start of the CC
the associated benefit of reduced enclosure size. characteristic) this parameter should be well controlled. For
an estimated overall constant current tolerance of ±24%, the
Key Application Considerations primary inductance tolerance should be ±7.5% or better. This
is achievable using standard low cost, center leg gapping
Design Output Power techniques where the gap size is typically 0.08 mm or larger.
Smaller gap sizes are possible but require non-standard, tighter
Table 1 (front page) shows the maximum continuous output ferrite AL tolerances.
power that can be obtained under the following conditions:
Other gapping techniques such as film gapping allow tighter
1. The minimum DC input bus voltage is 90 V or higher. This tolerances (±7% or better) with associated improvements in
corresponds to a filter capacitor of 3 µF/W for universal input the tolerance of the peak power point. Please consult your
and 1 µF/W for 230 VAC or 115 VAC input with doubler transformer vendor for guidance.
input stage.
2-99
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LNK520
Core gaps should be uniform. Uneven core gapping, especially inductance, which is the dominant cause. As the load reduces,
with small gap sizes, may cause variation in the primary the primary operating peak current reduces, together with the
inductance with flux density (partial saturation) and make the leakage inductance energy, which reduces the peak charging
constant current region non-linear. To verify uniform gapping, of the clamp capacitor.
it is recommended that the primary current wave-shape be
examined while feeding the supply from a DC source. The At very light or no-load, typically less than 2 mA of output current,
gradient is defined as di/dt = V/L and should remain constant the output voltage rises due to leakage inductance peak charging
throughout the MOSFET on time. Any change in gradient of of the secondary. This voltage rise can be reduced with a small
the current ramp is an indication of uneven gapping. preload with little change to no-load power consumption. The
output voltage load variation can be improved across the whole
Measurements made using a LCR bridge should not be solely load range by adding an optocoupler and secondary reference
relied upon; typically these instruments only measure at currents (Figure 6). The secondary reference is designed to only provide
of a few milliamps. This is insufficient to generate high enough feedback above the normal peak power point voltage to maintain
flux densities in the core to show uneven gapping. the correct constant current characteristic.
For a typical EE16 or EE13 core using center leg gapping, a Component Selection
0.08 mm gap allows a primary inductance tolerance of ±10% to
be maintained in standard high volume production. This allows The schematic shown in Figure 10 outlines the key components
the EE13 to be used in designs up to 2.75 W with less than needed for a LinkSwitch supply.
300 mW no-load consumption. Using outer leg film gapping
reduces inductance tolerance to ±7% or better, allowing designs Clamp Diode – D5
up to 3 W. Using the larger EE16 allows for a 3 W output Diode D5 can be an ultra-fast (trr < 50 ns), a fast (trr < 250 ns)
with center leg gapping. The EE13 core size may be attractive or standard recovery diode with a voltage rating of 600 V or
in designs were space is limited or if there is a cost advantage higher. A standard recovery diode is recommended as it improves
over the EE16. the CV characteristic, but should be a glass-passivated type
(1N400xGP) to ensure a defined reverse recovery time.
The transformer turns ratio should be selected to give a VOR
(output voltage reflected through secondary to primary turns Clamp Capacitor – C4
ratio) of 40 V to 80 V. Higher VOR increases the output power Capacitor C4 should be in the range of 100 pF to 1000 pF,
capability of LinkSwitch but also increases no-load power 500 V capacitor. A low cost ceramic disc is recommended.
2 consumption. This allows even higher values to be used in The tolerance of this part has a very minor effect on the output
designs where no-load power is not a concern. However care characteristic so any of the standard ±5%, ±10% or ±20%
should be taken to ensure that the maximum temperature rise tolerances are acceptable. 330 pF is a good initial value, iterated
of the device is acceptable at the upper limit of the output with R1.
characteristic when used in a charger application. In all cases,
discontinuous mode operation should be maintained and note Clamp Resistor – R1
that the linearity of the CC region of the power supply output The value of R1 is selected to be the highest value that still
characteristic is influenced by the bias voltage. If this is an provides adequate margin to the DRAIN BVDSS rating at high
important aspect of the application, the output characteristic line. As a general rule, the value of C4 should be minimized
should be checked before finalizing the design. and R1 maximized.
Output Characteristic Variation CONTROL Pin Capacitor – C5

Both the device tolerance and external circuit govern the overall Capacitor C5 is used during startup to power LinkSwitch and
tolerance of the LinkSwitch power supply output characteristic. sets the auto-restart frequency. For designs that have a battery
Estimated peak power point tolerances for a LNK520, 2.75 W load, this component should have a value of 0.22 µF and for
design are ±10% for voltage and ±24% for current limit for resistive loads a value of 1 µF. This ensures there is sufficient
overall variation in high volume manufacturing. This includes time during startup for the output voltage to reach regulation.
device and transformer tolerances (±7.5% assumed) and line Any capacitor type is acceptable with a voltage rating of
variation. Lower power designs may have poorer constant 10 V or above.
current linearity.
Bias Capacitor – C3
As the output load reduces from the peak power point, the Capacitor C3 should be a 1 µF, 50 V electrolytic type. The
output voltage will tend to rise due to tracking errors compared voltage rating is consistent with the 20 V to 30 V seen across
to the load terminals. Sources of these errors include the the bias winding. Lower values give poorer regulation.
output cable drop, output diode forward voltage and leakage
2-100
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LNK520
Feedback Resistor – R4 Quick Design Checklist

The value of R4 is selected to give a feedback current into the
CONTROL pin of approximately 2.15 mA at the peak output As with any power supply design, all LinkSwitch designs
power point of the supply. The actual value depends on the bias should be verified on the bench to make sure that component
voltage, typically in the range 20 V to 35 V, selected during specifications are not exceeded under worst-case conditions.
design. Higher values for the bias voltage will increase no-load Performing the following minimum set of tests is strongly
power consumption. Any 1%, 0.25 W resistor is suitable. recommended:
Output Diode – D7 1. Maximum drain voltage – Verify that VDS does not exceed
PN fast, PN ultrafast or Schottky diodes can be used depending 675 V at highest input voltage and peak output power.
on the efficiency target for the supply, Schottky diodes giving
higher efficiency than PN diodes. The diode voltage rating 2. Maximum drain current – At maximum ambient temperature,
should be sufficient to withstand the output voltage plus the maximum input voltage and peak output power, verify drain
input voltage transformed through the turns ratio (a typical VOR current waveforms at startup for any signs of transformer
of 50 V requires a diode PIV of 50 V). Slow recovery diodes saturation and excessive leading edge current spikes.
are not recommended (1N400X types). LinkSwitch has a minimum leading edge blanking time of
200 ns to prevent premature termination of the on-cycle.
Output Capacitor – C6 Verify that the leading edge current spike event is below
Capacitor C6 should be selected such that its voltage and ripple current limit at the end of the 200 ns blanking period.
current specifications are not exceeded. Selecting a capacitor
with low equivalent series resistance (ESR) will reduce peak- 3. Thermal check – At peak output power, minimum input
to-peak output ripple and improve overall supply operating voltage and maximum ambient temperature, verify that the
efficiency. temperature specifications are not exceeded for LinkSwitch,
transformer, output diode and output capacitors. Enough
LinkSwitch Layout Considerations thermal margin should be allowed for part-to-part variation of
the RDS(ON) of LinkSwitch as specified in the data sheet. Under
Primary Side Connections low line, peak power, a maximum LinkSwitch SOURCE pin
The copper area connected to SOURCE should be maximized temperature of 100 °C is recommended to allow for these
to minimize temperature rise of the LinkSwitch device. variations.
The CONTROL pin capacitor C5 should be located as close as 4. Centered output characteristic – Using a transformer with 2
possible to the SOURCE and CONTROL pins. nominal primary inductance and at an input voltage midway
between low and high line, verify that the peak power point
To minimize EMI coupling from the switching DRAIN node on occurs at ~4% above the desired nominal output current,
the primary to both the secondary and AC input, the LinkSwitch with the correct output voltage. If this does not occur, then
should be positioned away from the secondary of the transformer the design should be refined (increase LP) to ensure the
and AC input. overall tolerance limits are met.
The length and copper area of all PCB traces connecting to the Selecting Between LNK500 and LNK520
switching DRAIN node should be kept to an absolute minimum
to limit EMI radiation. The LNK500 and LNK520 differ in the circuit location of the
LinkSwitch device. The LNK500 is designed for high-side
Y-Capacitor operation and the LNK520 is designed for low-side operation.
If a Y-type cap is required, it should be connected close to the The LNK520 can, however, be used in the high-side configuration
transformer secondary output return pin(s) and the primary bulk in certain applications. Refer to Figure 9 and supporting
capacitor positive terminal. Such placement will maximize the description. Table 2 summarizes the considerations for selecting
EMI benefit of the Y-type cap and avoid problems in common- which device to use.
mode surge testing.
Design Tools

Power Integrations Web site: www.powerint.com.
2-101
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LNK520
LinkSwitch Input Filter

Capacitor
D S
S +
HV DC
S S Input
-
C
S
Y1-
Capacitor
Transformer
-
Output Capacitor DC Out
+
PI-3732-103003
2 Figure 12. Recommended Circuit Board Layout for LinkSwitch using LNK520.
2-102
Rev. E 02/05
LNK520
Family LNK500 LNK520

• Lowest cost CV/CC implementation • Very low cost CV/CC implementation
• Source is connected to the switching • Source connected to quiet low-side
node – simple circuit configuration & low primary return - easy layout & low noise
component count (low-side configuration only)
• Fast switching speeds minimize losses • Optimized switching speed – reduces
for best efficiency radiated EMI by up to 5 dB (Figure 13)
• Source PCB copper heatsink connected • Source PCB copper heatsink connected
to switching node – size should be to primary return – area can be
Considerations
minimized to limit noise maximized for higher power without noise
(low-side configuration only)
• No bias winding required – simplest • Bias winding required – allows higher
circuit configuration VOR, increasing power capability (low-side
configuration only)
• Perfect for linear replacement in • Perfect for systems where no additional
applications where additional system filtering or shielding exists
EMI shielding or filtering exists
The LNK500 is recommended for cost The LNK520 is recommended for both
sensitive applications in larger systems with stand-alone charger and adapter
Summary existing EMI filtering (e.g. white goods). applications, and larger systems where
EMI reduction is required (e.g. emergency
lighting).
Table 2. Comparison of LNK500 and LNK520.
PI-3861-031804
2
Amplitude 10 dBµV/Div
QP: LNK500
QP: LNK520
AV: LNK500
AV: LNK520
30.0 100.0 200.0

Frequency (MHz)
Figure 13. Comparison of LNK520 and LNK500 Showing an
Approximate 5 dBµV Reduction in Radiated EMI.
2-103
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LNK520

THERMAL IMPEDANCE
Conditions
See Figure 14
CONTROL FUNCTIONS
Switching
fOSC IC = IDCT, TJ = 25 °C 34.5 42 49.5 kHz
Frequency
2 Duty Cycle at Low

Switching DCLF
2.7 4.1 5.5 %
Frequency
Low Frequency
Duty Cycle Range
Maximum Duty
DCMAX IC = 1.5 mA 74 77 80 %
Cycle
CONTROL Pin
TJ = 25 °C
Current at 30% IDCT
See Figure 4
2.06 2.15 2.25 mA
Duty Cycle
CONTROL Pin
Voltage
Dynamic
ZC IC = IDCT, TJ = 25 °C 60 90 120 Ω
Impedance
2-104
Rev. E 02/05
LNK520
Conditions
See Figure 14
CONTROL Pin VC = 0 V -4.5 -3.25 -2

mA
Auto-Restart
VC(AR) 5.6 V
Threshold Voltage
Auto-Restart
VC(AR)hyst 0.9 V
Hysteresis Voltage
DC(AR) 8 %
f(AR) 300 Hz
CIRCUIT PROTECTION
TJ = 25 °C
Self-Protection
ILIM di/dt = 90 mA/µs 228 254 280 mA
Current Limit See Note B
TJ = 25 °C
I f Coefficient
2 I2 f di/dt = 90 mA/µs 2412 2710 3008 A2Hz
See Notes B, C 2
Current Limit at
Auto-Restart
Power Up Reset
VC(RESET) 1.5 2.75 4.0 V
Threshold Voltage
Leading Edge
Blanking Time
Thermal Shutdown
IC = IDCT 125 135 °C
Temperature
Thermal Shutdown
70 °C
Hysteresis
2-105
Rev. E 02/05
LNK520
Conditions
See Figure 14
OUTPUT
IDSS 50 µA
See Note D
VC = 6.2 V, TA = 25 °C
700 V
DRAIN Supply
See Note E 36 50 V
Voltage
NOTES:
B. IC is increased gradually to obtain maximum current limit at di/dt of 90 mA/µs. Increasing IC further would
terminate the cycle through duty cycle control.
C. This parameter is normalized to IDCT to correlate to power supply output current (it is multiplied by
IDCT(nominal)/IDCT).
2 D. Breakdown voltage may be checked against minimum BVDSS specification by ramping the DRAIN pin voltage
up to but not exceeding minimum BVDSS.
E. It is possible to start up and operate LinkSwitch at DRAIN voltages well below 36 V. However, the CONTROL
pin charging current is reduced, which affects startup time, auto-restart frequency, and auto-restart duty cycle.
Refer to the characteristic graph on CONTROL pin charge current (IC) vs. DRAIN voltage (Figure 16) for low
voltage operation characteristics.
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750 Ω LinkSwitch
D S
S1
S
10 kΩ S S
C S
S2
40 V C1
40 V
0.22 µF
PI-2894-031004
t2
t1
HV 90% 90%
DRAIN t
D= 1
VOLTAGE t2
2
10%
0V
PI-2048-050798
2 120 PI-2895-102303
PI-3758-111303
VC = 5.15 V
100
1.6
CONTROL Pin
80
1.2
60
0.8
40
0.4 20
0 0
0 20 40 60 80 100 0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0
DRAIN Voltage (V) CONTROL Pin Voltage (V)
Figure 16. IC vs. DRAIN Voltage. Figure 17. CONTROL Pin I-V Characteristic.
2-107
Rev. E 02/05
LNK520

90 1.1
PI-3737-101703
PI-2213-012301
80
70
Breakdown Voltage
Duty Cycle (%)
60
50
1.0
40
30
20
10
0 0.9
1.9 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 -50 -25 0 25 50 75 100 125 150
CONTROL Pin Current (mA) Junction Temperature (°C)
Figure 18. Duty Cycle vs. CONTROL Pin Current. Figure 19. Breakdown Voltage vs. Temperature.
1.200 1.200
PI-3738-101703
PI-3739-101703
1.000 1.000

Switching Frequency
Current Limit
0.800 0.800
0.600 0.600
0.400 0.400
2
0.200 0.200
0.000 0.000
-50 0 50 100 150 -50 -25 0 25 50 75 100 125 150
Figure 20. Switching Frequency vs. Temperature. Figure 21. Current Limit vs. Temperature.
1.2 1.200
PI-3740-0101703
PI-3741-101703
1.0 1.000
I2f Coefficient
0.8 0.800
0.6 0.600
0.4 0.400
0.2 0.200
0.0 0.000
-50 -25 0 25 50 75 100 125 150 -50 -20 0 25 50 75 100 125 150
Figure 22. I2f Coefficient vs. Temperature. Figure 23. IDCT vs. Temperature.
2-108
Rev. E 02/05
LNK520

1.2 300
PI-2899-062802
PI-2222-031401
TCASE=25 °C
1 250 TCASE=100 °C
Drain Current (mA)

0.8 200
0.6 150
0.4 100
0.2 50
0 0
-50 0 50 100 150 0 2 4 6 8 10
Temperature (°C) Drain Voltage (V)
Figure 24. PWM Gain vs. Temperature. Figure 25. Output Characteristics (DRAIN Current vs.
DRAIN Voltage.

Series Number
Package Identifier
P Plastic DIP
Lead Finish
2
Revision Notes Date

C 1) Released Final Data Sheet. 3/04
D 1) Added lead-free ordering information. 12/04
E 1) Minor descriptive change and formatting correction. 2/05
2-109
Rev. E 02/05
LNK562-564
LNK562-564
®
LinkSwitch-LP
Energy Efficient Off-Line Switcher IC for
Linear Transformer Replacement
Product Highlights
+ DC
Lowest System Cost and Advanced Safety Features AC
Output
IN
• Lowest component count switcher
• Very tight parameter tolerances using proprietary IC
trimming technology and transformer construction
techniques enable Clampless™designs – decreases D
FB
component count/system cost and increases efficiency
LinkSwitch-LP BP
• Meets industry standard requirements for thermal overload
protection – eliminates the thermal fuse used with linear S
transformers or additional components in RCC designs

(a) PI-3923-092705
• Frequency jittering greatly reduces EMI – enables low cost
input filter configuration VO
• Meets HV creepage requirements between DRAIN and all Rated Output Power = VR • IR
other pins, both on the PCB and at the package
VR
• Proprietary E-Shield™ transformer eliminates Y-capacitor
Superior Performance over Linear and RCC
• Hysteretic thermal shutdown protection – automatic
recovery improves field reliability
• Universal input range allows worldwide operation IR IO
• Auto-restart reduces delivered power by >85% during
2
(b) PI-3924-011706
short circuit and open loop fault conditions
• Simple ON/OFF control, no loop compensation needed Figure 1. Typical Application – not a Simplified Circuit (a) and
• High bandwidth provides fast turn on with no overshoot Output Characteristic Envelope (b).
and excellent transient load response
®
EcoSmart – Energy Efficiency Technology OUTPUT POWER TABLE1
• Easily meets all global energy efficiency regulations with
230 VAC ±15% 85-265 VAC
no added components
• No-load consumption <150 mW at 265 VAC input PRODUCT4 Open Open
Adapter2 Adapter2
• ON/OFF control provides constant efficiency to very Frame3 Frame3
light loads – ideal for mandatory CEC regulations LNK562P or G 1.9 W 1.9 W 1.9 W 1.9 W
Applications LNK563P or G 2.5 W 2.5 W 2.5 W 2.5 W
• Chargers for cell/cordless phones, PDAs, power tools, LNK564P or G 3W 3W 3W 3W
MP3/portable audio devices, shavers etc.
• Standby and auxiliary supplies Table 1. Output Power Table.
Notes:
Description 1. Output power may be limited by specific application parameters
including core size and Clampless operation (see Key Application
LinkSwitch-LP switcher ICs cost effectively replace all Considerations).
unregulated isolated linear transformer based (50/60 Hz) power 2. Minimum continuous power in a typical non-ventilated enclosed
adapter measured at 50 °C ambient.
supplies up to 3 W output power. For worldwide operation, a 3. Minimum practical continuous power in an open frame design with
single universal input design replaces multiple linear transformer adequate heat sinking, measured at 50 °C ambient.
based designs. The self-biased circuit achieves an extremely low 4. Packages: P: DIP-8B, G: SMD-8B. For lead-free package options,
see Part Ordering Information.
no-load consumption of under 150 mW. The internal oscillator
frequency is jittered to significantly reduce both quasi-peak and
average EMI, minimizing filter cost.
2-110
Rev. F 10/05
LNK562-564
BYPASS DRAIN
(BP) (D)
REGULATOR
5.8 V
AUTO-RESTART
COUNTER FAULT BYPASS PIN
0.8 V PRESENT UNDER-VOLTAGE
RESET +
+
5.8 V -
4.85 V CURRENT LIMIT
6.3 V COMPARATOR
- VI
LIMIT
JITTER
CLOCK
DCMAX
ADJ THERMAL
SHUTDOWN
OSCILLATOR
FEEDBACK
1.69 V -VTH
(FB)
S Q
OPEN LOOP R Q
PULLDOWN
LEADING
EDGE
BLANKING
PI-3958-092905
SOURCE
(S)

DRAIN (D) Pin: P Package (DIP-8B)
The power MOSFET drain connection provides internal G Package (SMD-8B) 2
operating current for both startup and steady-state operation.
BYPASS (BP) Pin: S 1 8 S

A 0.1 µF external bypass capacitor for the internally generated S 2 7 S
5.8 V supply is connected to this pin.
BP 3
FEEDBACK (FB) Pin: FB 4 5 D
During normal operation, switching of the power MOSFET is
controlled by this pin. MOSFET switching is disabled when a
current greater than 70 µA flows into this pin.
PI-3491-111903
SOURCE (S) Pin:

This pin is the power MOSFET source connection. It is also the
ground reference for the BYPASS and FEEDBACK pins.
LinkSwitch-LP Functional protection, frequency jittering, current limit circuit, and leading
edge blanking.
Description
LinkSwitch-LP comprises a 700 V power MOSFET switch with Oscillator
a power supply controller on the same die. Unlike conventional The typical oscillator frequency is internally set to an average
PWM (pulse width modulation) controllers, it uses a simple of 66/83/100 kHz for the LNK562, 563 & 564 respectively.
ON/OFF control to regulate the output voltage. The controller Two signals are generated from the oscillator: the maximum
consists of an oscillator, feedback (sense and logic) circuit, 5.8 duty cycle signal (DCMAX) and the clock signal that indicates
V regulator, BYPASS pin undervoltage circuit, over-temperature the beginning of each switching cycle.
2-111
Rev. F 10/05
LNK562-564
The oscillator incorporates circuitry that introduces a small Over-Temperature Protection

amount of frequency jitter, typically 5% of the switching The thermal shutdown circuitry senses the die temperature.
frequency, to minimize EMI. The modulation rate of the The threshold is set at 142 °C typical with a 75 °C hysteresis.
frequency jitter is set to 1 kHz to optimize EMI reduction When the die temperature rises above this threshold (142 °C)
for both average and quasi-peak emissions. The frequency the power MOSFET is disabled and remains disabled until the
jitter, which is proportional to the oscillator frequency, should die temperature falls by 75 °C, at which point the MOSFET
be measured with the oscilloscope triggered at the falling is re-enabled.
edge of the DRAIN voltage waveform. The waveform in
Figure 4 illustrates the frequency jitter. The oscillator frequency Current Limit
is reduced when the FB pin voltage is less than 1.69 V as The current limit circuit senses the current in the power MOSFET.
described below. When this current exceeds the internal threshold (ILIMIT), the
power MOSFET is turned off for the remainder of that cycle. The
Feedback Input Circuit leading edge blanking circuit inhibits the current limit comparator
The feedback input circuit at the FB pin consists of a low for a short time (tLEB) after the power MOSFET is turned on. This
impedance source follower output set at 1.69 V. When the current leading edge blanking time has been set so that current spikes
delivered into this pin exceeds 70 µA, a low logic level (disable) caused by capacitance and rectifier reverse recovery time will
is generated at the output of the feedback circuit. This output not cause premature termination of the MOSFET conduction.
is sampled at the beginning of each cycle on the rising edge of
the clock signal. If high, the power MOSFET is turned on for
600
that cycle (enabled), otherwise the power MOSFET remains
PI-3660-081303
off (disabled). Since the sampling is done only at the beginning 500
of each cycle, subsequent changes in the FB pin voltage or VDRAIN
current during the remainder of the cycle are ignored. When 400
the FB pin voltage falls below 1.69 V, the oscillator frequency
linearly reduces to typically 48% at the auto-restart threshold 300
voltage of 0.8 V. This function limits the power supply output

200
current at output voltages below the rated voltage regulation
threshold VR (see Figure 1). 100

2
0
The 5.8 V regulator charges the bypass capacitor connected to 68 kHz
64 kHz
the BYPASS pin to 5.8 V by drawing a current from the voltage
on the DRAIN, whenever the MOSFET is off. The BYPASS
pin is the internal supply voltage node. When the MOSFET 0 20
is on, the device runs off of the energy stored in the bypass Time (µs)
capacitor. Extremely low power consumption of the internal
Figure 4. Frequency Jitter at fOSC.
circuitry allows LinkSwitch-LP to operate continuously from the
current drawn from the DRAIN pin. A bypass capacitor value of
0.1 µF is sufficient for both high frequency decoupling and Auto Restart
energy storage. In the event of a fault condition such as output short circuit or
an open loop condition, LinkSwitch-LP enters into auto-restart
In addition, there is a 6.3 V shunt regulator clamping the operation. An internal counter clocked by the oscillator gets reset
BYPASS pin at 6.3 V when current is provided to the BYPASS every time the FB pin voltage exceeds the FEEDBACK Pin
pin externally. This facilitates powering the device externally Auto-Restart Threshold Voltage (VFB(AR)). If the FB pin voltage
through a resistor from the bias winding to decrease the no- drops below VFB(AR) for more than 100 ms, the power MOSFET
load consumption. switching is disabled. The auto-restart alternately enables and
disables the switching of the power MOSFET at a duty cycle
BYPASS Pin Undervoltage of typically 12% until the fault condition is removed.
The BYPASS pin undervoltage circuitry disables the power
Once the BYPASS pin voltage drops below 4.85 V, it must rise
back to 5.8 V to enable (turn on) the power MOSFET.
2-112
Rev. F 10/05
LNK562-564
C5 VR1*
D1 RF1* L1 T1 D4 220 µF R3 1N5240B 6 V,
L 1N4937 8.2 Ω 3300 µH EE16 7 UF4002 25 V 2 kΩ 10 V 0.33 A
2
J-1 2.5 W J3-2
C1
90-265 10 µF J3-1
VAC 1 6
400 V
J-2 4 RTN
N
D2
1N4005 5
R1
D3 37.4 kΩ
1N4005 C4*
D C3 100 pF
FB 250 VAC
LinkSwitch-LP 330 nF
U1 BP 50 V
LNK564P C2 R2
S 0.1 µF 3 kΩ
*Optional components
50 V
PI-4106-101105
Figure 5. 6 V, 330 mA CV/CC Linear Replacement Power Supply.
Applications Example output of the power supply), the power supply will turn OFF
for 800 ms and then turn back on for 100 ms. It will continue
The circuit shown in Figure 5 is a typical implementation of in this mode until the auto-restart threshold is exceeded. This
a 6 V, 330 mA, constant voltage, constant current (CV/CC) function reduces the average output current during an output
output power supply. short circuit condition.
AC input differential filtering is accomplished with the very No-load consumption can be further reduced by increasing C3
low cost input filter stage formed by C1 and L1. The proprietary to 0.47 µF or higher.
frequency jitter feature of the LNK564 eliminates the need for
an input pi filter, so only a single bulk capacitor is required. A Clampless primary circuit is achieved due to the very 2
Adding a sleeve may allow the input inductor L1 to be used as a tight tolerance current limit trimming techniques used in
fuse as well as a filter component. This very simple Filterfuse™ manufacturing the LNK564, plus the transformer construction
input stage further reduces system cost. Alternatively, a fusible techniques used. Peak drain voltage is therefore limited to
resistor RF1 may be used to provide the fusing function. typically less than 550 V at 265 VAC, providing significant
margin to the 700 V minimum drain voltage specification
Input diode D2 may be removed from the neutral phase in (BVDSS).
applications where decreased EMI margins and/or decreased
input surge withstand is allowed. In such applications, D1 will Output rectification and filtering is achieved with output rectifier
need to be an 800 V diode. D4 and filter capacitor C5. Due to the auto-restart feature, the
average short circuit output current is significantly less than
The power supply utilizes simplified bias winding voltage 1 A, allowing low cost rectifier D4 to be used. Output circuitry is
feedback, enabled by LNK564 ON/OFF control. The resistor designed to handle a continuous short circuit on the power supply
divider formed by R1 and R2 determine the output voltage across output. Diode D4 is an ultra-fast type, selected for optimum
the transformer bias winding during the switch OFF time. In the V/I output characteristics. Optional resistor R3 provides a
V/I constant voltage region, the LNK564 device enables/disables preload, limiting the output voltage level under no-load output
switching cycles to maintain 1.69 V on the FB pin. Diode D3 and conditions. Despite this preload, no-load consumption is within
low cost ceramic capacitor C3 provide rectification and filtering targets at approximately 140 mW at 265 VAC. The additional
of the primary feedback winding waveform. At increased loads, margin of no-load consumption requirement can be achieved
beyond the constant power threshold, the FB pin voltage begins by increasing the value of R4 to 2.2 kΩ or higher while still
to reduce as the power supply output voltage falls. The internal maintaining output voltage well below the 9 V maximum
oscillator frequency is linearly reduced in this region until it specification. Placement is left on the board for an optional
reaches typically 50% of the starting frequency. When the FB Zener clamp (VR1) to limit maximum output voltage under
pin voltage drops below the auto-restart threshold (typically open loop conditions, if required.
0.8 V on the FB pin, which is equivalent to 1 V to 1.5 V at the
2-113
Rev. F 10/05
LNK562-564
Key Application Considerations The following requirements are recommended for a universal
input or 230 VAC only Clampless design:
Output Power Table
The data sheet maximum output power table (Table 1) represents 1. Clampless designs should only be used for PO ≤ 2.5 W using
the maximum practical continuous output power level that can a VOR of ≤ 90 V
be obtained under the following assumed conditions: 2. For designs with PO ≤ 2 W, a two-layer primary must be
used to ensure adequate primary intra-winding capacitance
1. The minimum DC input voltage is 90 V or higher for 85 VAC in the range of 25 pF to 50 pF.
input, or 240 V or higher for 230 VAC input or 115 VAC 3. For designs with 2 < PO ≤ 2.5 W, a bias winding must be added
with a voltage doubler. The value of the input capacitance to the transformer using a standard recovery rectifier diode
should be large enough to meet these criteria for AC input (1N4003– 1N4007) to act as a clamp. This bias winding may
designs. also be used to externally power the device by connecting
2. Secondary output of 6 V with a Schottky rectifier diode. a resistor from the bias winding capacitor to the BYPASS
3. Assumed efficiency of 70%. pin. This inhibits the internal high-voltage current source,
4. Voltage only output (no secondary-side constant current reducing device dissipation and no-load consumption.
circuit). 4. For designs with PO >2.5 W, Clampless designs are not
5. Discontinuous mode operation (KP > 1). practical and an external RCD or Zener clamp should be
6. A suitably sized core to allow a practical transformer design used.
(see Table 2). 5. Ensure that worst-case, high line, peak drain voltage is below
7. The part is board mounted with SOURCE pins soldered the BVDSS specification of the internal MOSFET and ideally
to a sufficient area of copper to keep the SOURCE pin ≤ 650 V to allow margin for design variation.
temperature at or below 100 °C.
8. Ambient temperature of 50 °C for open frame designs VOR (Reflected Output Voltage), is the secondary output plus
and an internal enclosure temperature of 60 °C for adapter output diode forward voltage drop that is reflected to the
designs. primary via the turns ratio of the transformer during the diode
conduction time. The VOR adds to the DC bus voltage and the
LinkSwitch-LP Device leakage spike to determine the peak drain voltage.
Core Size LNK562 LNK563 LNK564
Audible Noise
EE13 1.1 W 1.4 W 1.7 W The cycle skipping mode of operation used in LinkSwitch-LP
2 EE16 1.3 W 1.7 W 2W can generate audio frequency components in the transformer.
To limit this audible noise generation, the transformer should
EE19 1.9 W 2.5 W 3W
be designed such that the peak core flux density is below
Table 2. Estimate of Transformer Power Capability vs. 1500 Gauss (150 mT). Following this guideline and using the
LinkSwitch-LP Device and Core Size at a Flux Density of standard transformer production technique of dip varnishing,
1500 Gauss (150 mT). practically eliminates audible noise. Vacuum impregnation
of the transformer is not recommended, as it does not provide
Below a value of 1, KP is the ratio of ripple to peak primary any better reduction of audible noise than dip varnishing. And
current. Above a value of 1, KP is the ratio of primary MOSFET although vacuum impregnation has the benefit of increased
OFF time to the secondary diode conduction time. Due to transformer capacitance (which helps in Clampless designs),
the flux density requirements described below, typically a it can also upset the mechanical design of the transformer,
LinkSwitch-LP design will be discontinuous, which also has especially if shield windings are used. Higher flux densities are
the benefit of allowing lower-cost fast (vs. ultra-fast) output possible, increasing the power capability of the transformers
diodes and reducing EMI. above what is shown in Table 2. However careful evaluation of
the audible noise performance should be made using production
Clampless Designs transformer samples before approving the design.
Clampless designs rely solely on the drain node capacitance
to limit the leakage inductance induced peak drain-to-source Ceramic capacitors that use dielectrics such as Z5U, when used
voltage. Therefore the maximum AC input line voltage, the in clamp circuits, may also generate audio noise. If this is the
value of VOR, the leakage inductance energy, (a function of case, try replacing them with a capacitor having a different
leakage inductance and peak primary current), and the primary dielectric or construction, for example a film type.
winding capacitance determine the peak drain voltage. With no
significant dissipative element present, as is the case with an Bias Winding Feedback
external clamp, the longer duration of the leakage inductance To give the best output regulation in bias winding designs, a
ringing can increase EMI. slow diode such as the 1N400x series should be used as the
2-114
Rev. F 10/05
LNK562-564
TOP VIEW
D FB CBP
LinkSwitch-LP
BP
Capacitor
Input Filter
Y1-
Capacitor
S S
S
Tr a n s f o r m e r S
- HV DC +
INPUT
+
DC
OUT
-
Maximize hatched copper
areas ( ) for optimum
Output Filter heatsinking 2
Capacitor
PI-4157-101305
Figure 6. Recommended Circuit Board Layout for LinkSwitch-LP (Assumes a HVDC Input Stage).
rectifier. This effectively filters the leakage inductance spike Primary Loop Area
and reduces the error that this would give when using fast The area of the primary loop that connects the input filter
recovery time diodes. The use of a slow diode is a requirement capacitor, transformer primary and LinkSwitch-LP together
in Clampless designs. should be kept as small as possible.
LinkSwitch-LP Layout Considerations Primary Clamp Circuit

An external clamp may be used to limit peak voltage on the
Layout DRAIN pin at turn off. This can be achieved by using an RCD
See Figure 6 for a recommended circuit board layout for clamp or a Zener (~200 V) and diode clamp across the primary
LinkSwitch-LP. winding. In all cases, to minimize EMI, care should be taken
to minimize the circuit path from the clamp components to the
Single Point Grounding transformer and LinkSwitch-LP.
Use a single point ground connection from the input filter
capacitor to the area of copper connected to the SOURCE pins. Thermal Considerations
The copper area underneath the LinkSwitch-LP acts not only as
Bypass Capacitor (CBP) a single point ground, but also as a heatsink. As it is connected
The BYPASS pin capacitor should be located as near as possible to the quiet source node, this area should be maximized for
to the BYPASS and SOURCE pins. good heat sinking of LinkSwitch-LP. The same applies to the
cathode of the output diode.
2-115
Rev. F 10/05
LNK562-564
Y-Capacitor 2. Maximum drain current – At maximum ambient

The placement of the Y-type cap should be directly from the temperature, maximum input voltage and peak output
primary input filter capacitor positive terminal to the common/ (overload) power, verify drain current waveforms for any
return terminal of the transformer secondary. Such a placement signs of transformer saturation and excessive leading-edge
will route high magnitude common-mode surge currents away current spikes at startup. Repeat under steady state conditions
from the LinkSwitch-LP device. Note: If an input pi (C, L, C) and verify that the leading-edge current spike event is below
EMI filter is used, then the inductor in the filter should be placed ILIMIT(MIN) at the end of the tLEB(MIN). Under all conditions, the
between the negative terminals on the input filter capacitors. maximum DRAIN current should be below the specified
absolute maximum ratings.
Output Diode 3. Thermal Check – At specified maximum output
For best performance, the area of the loop connecting the power, minimum input voltage and maximum ambient
secondary winding, the output diode and the output filter temperature, verify that the temperature specifications
capacitor should be minimized. In addition, sufficient copper are not exceeded for LinkSwitch-LP, transformer, output
area should be provided at the anode and cathode terminals diode and output capacitors. Enough thermal margin
of the diode for heat sinking. A larger area is preferred at the should be allowed for part-to-part variation of the RDS(ON) of
quiet cathode terminal. A large anode area can increase high- LinkSwitch-LP as specified in the data sheet. Under low line and
frequency radiated EMI. maximum power, a maximum LinkSwitch-LP SOURCE pin
temperature of 100 °C is recommended to allow for these
Quick Design Checklist variations.
As with any power supply design, all LinkSwitch-LP designs Design Tools
specifications are not exceeded under worst-case conditions. The Up-to-date information on design tools can be found at the
following minimum set of tests is strongly recommended: Power Integrations web site: www.powerint.com.
1. Maximum drain voltage – Verify that VDS does not exceed

650 V at the highest input voltage and peak (overload) output
power. A 50 V margin to the 700 V BVDSS specification
gives margin for design variation, especially in Clampless
designs.
2
2-116
Rev. F 10/05
LNK562-564

DRAIN Voltage .................................................. 700 V Notes:
Peak DRAIN Current...................................200 mA (375 mA)(2) 1. All voltages referenced to SOURCE, TA = 25 °C.
Peak Negative Pulsed Drain Current (see Fig. 10) ... 100 mA(3) 2. The higher peak DRAIN current is allowed while the
FEEDBACK Voltage .........................................-0.3 V to 9 V DRAIN voltage is simultaneously less than 400 V.
FEEDBACK Current.............................................100 mA 3. Duration not to exceed 2 µs.
BYPASS Voltage ..........................................-0.3 V to 9 V 4. Normally limited by internal circuitry.
Storage Temperature .......................................... -65 °C to 150 °C 5. 1/16 in. from case for 5 seconds.
Operating Junction Temperature(4) ..................... -40 °C to 150 °C 6. Maximum ratings specified may be applied, one at a time,
Lead Temperature(5) ........................................................260 °C without causing permanent damage to the product.
Exposure to Absolute Maximum Rating conditions for
THERMAL IMPEDANCE
Conditions
See Figure 7
CONTROL FUNCTIONS
LNK562 61 66 71
Output TJ = 25 °C
fOSC Average LNK563 77 83 89 kHz
Frequency VFB =1.69 V
LNK564 93 100 107
2
Ratio of Output
Frequency At Auto- fOSC(AR) TJ = 25 °C, VFB = VFB(AR) 48 %
Restart to fOSC
Frequency Jitter Peak-Peak Jitter, TJ = 25 °C 5 %
Maximum Duty
DCMAX S2 Open 66 70 %
Cycle
FEEDBACK Pin
TJ = 25 °C
Turnoff Threshold IFB
See Note A
56 70 84 µA
Current
FEEDBACK Pin
TJ = 0 to 125 °C
Voltage at Turnoff VFB
See Note A
1.60 1.69 1.78 V
Threshold
VFB ≥ 2 V
DRAIN Supply See Note B
Current FEEDBACK Open
IS2 (MOSFET Switching) 220 260 µA
See Notes B, C
2-117
Rev. F 10/05
LNK562-564
Conditions
See Figure 7
BYPASS Pin ICH1 VBP = 0 V, TJ = 25 °C, See Note D -5.5 -3.3 -1.8
mA
Charge Current ICH2 VBP = 4 V, TJ = 25 °C, See Note D -3.8 -2.3 -1.0
BYPASS Pin
VBP 5.55 5.8 6.10 V
Voltage
BYPASS Pin
VBPH 0.8 0.95 1.2 V
Voltage Hysteresis
BYPASS Pin
IBPSC See Note E 84 µA
Supply Current
CIRCUIT PROTECTION
di/dt = 40 mA/µs
Current Limit ILIMIT
TJ = 25 °C
124 136 148 mA
LNK562 1099 1221 1380

di/dt = 40 mA/µs
Power Coefficient If
2
TJ = 25 °C
LNK563 1381 1535 1735 A2Hz
LNK564 1665 1850 2091
tLEB 220 265 ns
2
Thermal Shutdown
TSD 135 142 150 °C
Temperature
Thermal Shutdown
TSHD See Note G 75 °C
Hysteresis
OUTPUT
OFF-State Drain VBP = 6.2 V, VFB ≥2 V, VDS = 560 V,

IDSS 50 µA
Leakage Current TJ = 25 °C
VBP = 6.2 V, VFB ≥2 V,

See Note H, TJ = 25 °C
700 V
DRAIN Supply
50 V
Voltage
Output Enable
Delay
Output Disable
tDST 0.5 µs
Setup Time
2-118
Rev. F 10/05
LNK562-564
Conditions
See Figure 7
OUTPUT (cont.)
FEEDBACK Pin
Auto-Restart VFB(AR) TJ = 25 °C 0.8 V
Threshold Voltage
Auto-Restart VFB = VFB(AR)
100 ms
ON-Time TJ = 25 °C
Auto-Restart
DCAR 12 %
Duty Cycle
NOTES:
A. In a scheme using a resistor divider network at the FB pin, where RU is the resistor from the FB pin to the rectified
bias voltage and RL is the resistor from the FB pin to the SOURCE pin, the output voltage variation is influenced
by VFB and IFB variations. To determine the contribution from the VFB variation in percent, the following equation
can be used:
K VFB(MAX) b RL l + IFB(TYP) RU
J RU + RL N
O
x = 100 # K - 1O
KK VFB(TYP) b U
RL l + IFB(TYP) RU
R + R L OO
L P
To determine the contribution from IFB variation in percent, the following equation can be used:
2
K VFB(TYP) b RL l + IFB(MAX) RU
J RU + RL N
O
y = 100 # K - 1O
KK VFB(TYP) b RU + RL l + IFB(TYP) RU OO
L RL P
Since IFB and VFB are independent parameters, the composite variation in percent would be ! x 2 + y 2 .
B. Total current consumption is the sum of IS1 and IDSS when FEEDBACK pin voltage is ≥2 V (MOSFET not
C Since the output MOSFET is switching, it is difficult to isolate the switching current from the supply current at the
D. See Typical Performance Characteristics section Figure 15 for BYPASS pin startup charging waveform.
E. This current is only intended to supply an optional optocoupler connected between the BYPASS and FEEDBACK
H. Breakdown voltage may be checked against minimum BVDSS by ramping the DRAIN pin voltage up to but not
2-119
Rev. F 10/05
LNK562-564
470 Ω
5W 470 kΩ
D FB
S1 S2
BP
50 V 50 V
S S 0.1 µF
S S
PI-3490-060204
Figure 7. General Test Circuit.
DCMAX
(internal signal)
tP
FB
tEN
VDRAIN
1
2 tP =
fOSC
PI-3707-112503
Figure 8. Duty Cycle Measurement. Figure 9. Output Enable Timing.

PI-4021-101305
DRAIN Current (mA)
100
2 µs
-100
Time (µs)
Figure 10. Peak Negative Pulsed DRAIN Current

Waveform.
2-120
Rev. F 10/05
LNK562-564
1.1 1.2
PI-2680-012301
PI-2213-012301
1.0
Breakdown Voltage
Output Frequency
0.8
1.0 0.6
0.4
0.2
0.9 0
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125
1.4 1.1
PI-4164-100505
PI-4057-071905
1.2 FEEDBACK Pin Voltage
1.0
Current Limit
0.8
1.0
0.6
0.4 2
0.2
0 0.9
-50 0 50 100 150 -50 -25 0 25 50 75 100 125 150
Temperature (°C) Temperature (°C)
Figure 13. Current Limit vs. Temperature. Figure 14. FEEDBACK Pin Voltage vs. Temperature.
7 200
PI-3927-083104
PI-2240-012301
6 175
25 °C
DRAIN Current (mA)
5 150
100 °C
4 125
3 100
2 75
1 50
0 25
0
0 0.2 0.4 0.6 0.8 1.0 0 2 4 6 8 10 12 14 16 18 20
Figure 15. BYPASS Pin Startup Waveform. Figure 16. Output Characteristics.
2-121
Rev. F 10/05
LNK562-564
1000
PI-3928-083104
100
10
1
0 100 200 300 400 500 600
Drain Voltage (V)

LP Series Number
Package Identifier
P Plastic DIP
2 Lead Finish
LNK 562 G N - TL TL Tape & Reel, 1000 pcs minimum, G package only
Revision Notes Date

E 1) Final Release Data Sheet 10/05
F 2) Revision of PI-3924 10/05
2-122
Rev. F 10/05
PKS603-606
PKS603-606

PeakSwitch Family
Enhanced, Energy-Efficient,
Off-Line Switcher
Product Highlights
®
EcoSmart – Extremely Energy-Efficient AC +
• Standby output power ≥0.6 W for 1 W input (high line) IN
DC
• Sleep mode power ≥2.4 W at 3 W input (high line) OUT
• No-load consumption <200 mW at 265 VAC input

• Surpasses California Energy Commission (CEC),
ENERGY STAR, and EU requirements
PeakSwitch Features Reduce System Cost
• Delivers peak power of up to 3 times maximum Optional Smart D
continuous output power AC Sense EN/UV
• 277 kHz operation during peak power significantly PeakSwitch BP
reduces transformer size S

• Programmable smart AC line sensing provides latching
shutdown during short circuit, overload and open loop PI-3995-051006
faults and prevents power ON/OFF glitches during power
down or brownout Figure 1. Typical Peak Power Application.
• Two external components reset latch on AC removal
• Adaptive switching cycle on-time extension increases low OUTPUT POWER TABLE
line peak output power, minimizing bulk capacitor size 230 VAC ±15% 85-265 VAC
• Adaptive current limit reduces output overload power
PRODUCT3 Adapter Adapter Adapter Adapter
• Frequency jittering reduces EMI filter cost
• Tight I2f tolerances and negligible temperature variation
Cont.1 Peak2 Cont.1 Peak2 2
of key parameters ease design and lower cost PKS603 P 13 W 32 W 9W 25 W
• Accurate hysteretic thermal shutdown with automatic PKS604 P 23 W 56 W 16 W 44 W
recovery provides complete system level overload PKS604 Y/F 35 W 56 W 23 W 44 W
protection and eliminates need for manual reset
PKS605 P 31 W 60 W 21 W 44 W
Better System Cost/Performance over RCC & Discrete PKS605 Y/F 46 W 79 W 30 W 58 W
• Simple ON/OFF control – no loop compensation needed PKS606 P 35 W 66 W 25 W 46 W
• Very low component count – higher reliability and single
PKS606 Y/F 68 W 117 W 45 W 86 W
side printed circuit board
• High bandwidth provides fast turn on with no overshoot Table 1. Output Power Table.
and excellent transient load response Notes:
1. Typical continuous power in a non-ventilated enclosed adapter
• Peak current limit operation rejects line frequency ripple measured at +50 °C ambient.
• Built-in current limit and hysteretic thermal protection 2. Typical peak power for a period of 100 ms and a duty cycle of
10% in a non-ventilated enclosed adapter measured at +50 °C
Applications (see Key Applications section for details).
• Inkjet printer 3. See Part Ordering Information.
• Data storage, audio amplifier, DC motor drives
Description high-voltage switched current source for startup, current limit,

and thermal shutdown onto a monolithic device. In addition,
PeakSwitch is designed to address applications with high peak- these devices incorporate auto-restart, line undervoltage sense
to-continuous power ratio demands. The very high switching and frequency jittering. An innovative design minimizes audio
frequency during peak power loads and excellent load transient frequency components in the simple ON/OFF control scheme
response reduce system cost as well as component count and size. to practically eliminate audible noise with standard varnished
PeakSwitch incorporates a 700 V power MOSFET, oscillator, transformer construction.
2-123
Rev. H 06/06
PKS603-606
BYPASS DRAIN
(BP) (D)
REGULATOR
5.8 V
LINE UNDER-VOLTAGE
240 µA 25 µA FAULT BYPASS PIN
PRESENT UNDER-VOLTAGE
LATCH OFF/ +
AUTO-
RESTART -
COUNTER CURRENT 5.8 V
ON TIME EXT LIMIT STATE 4.8 V VI
LIMIT
MACHINE/
RESET ADAPTIVE
6.3 V
CURRENT
LIMIT
CURRENT LIMIT
COMPARATOR
ENABLE -
JITTER
CLOCK
1.0 V + VT
DCMAX THERMAL
SHUTDOWN
OSCILLATOR
ENABLE/
UNDER- 1.0 V
VOLTAGE S Q
(EN/UV)
R Q
SOURCE
(S)
LEADING
EDGE
BLANKING
GROUND (GND)
(Y & F Package
Only)
2 PI-3940-040606
Pin Functional Description Y Package (TO-220-7C)

DRAIN (D) Pin: 7D
Tab Internally
The power MOSFET drain connection provides internal Connected to 5 NC
4S
SOURCE Pin
operating current for both startup and steady-state operation. 3 EN/UV
2 GND
1 BP
BYPASS (BP) Pin:
A 0.33 µF external bypass capacitor for the internally generated
5.8 V supply is connected to this pin. In typical applications this
pin must be externally supplied via a bias winding. P Package (DIP-8C) F Package (TO-262-7C)
ENABLE/UNDERVOLTAGE (EN/UV) Pin: BP 1 8 S 7D

This pin has dual functions: enable input and line undervoltage 5 NC
EN/UV 2 7 S
sense. During normal operation, switching of the power MOSFET 4S
3 EN/UV
is controlled by this pin. MOSFET switching is disabled when a 6 S 2 GND
1 BP
current greater than 240 µA is drawn from this pin. This pin may
D 4 5 S
also sense line undervoltage conditions through either an
external resistor connected to the DC line voltage or an AC PI-3941-031506
sense circuit. Figure 3. Pin Configuration.
SOURCE (S) Pin: GROUND (GND) Pin (Y or F Package Only):

This is the MOSFET source connection for high-voltage return This is the signal ground for the bypass capacitor and
and control circuit common. optocoupler.
2-124
Rev. H 06/06
PKS603-606
through the source follower is limited to 240 µA. When the

PeakSwitch Functional Description current out of this pin exceeds 240 µA, a low logic level
PeakSwitch integrates a 700 V power MOSFET switch with a (disable) is generated at the output of the enable circuit. This
power supply controller on the same die. Unlike conventional enable circuit output is sampled at the beginning of each
PWM (pulse width modulator) controllers, PeakSwitch uses a cycle on the rising edge of the clock signal. If high, the power
simple ON/OFF control to regulate the output voltage. MOSFET is turned on for that cycle (enabled). If low, the power
MOSFET remains off (disabled). Since the sampling is done
The controller consists of an oscillator, enable only at the beginning of each cycle, subsequent changes in the
circuit (sense and logic), current limit state machine, EN/UV pin voltage or current during the remainder of the
5.8 V regulator, BYPASS pin undervoltage circuit, over- cycle are ignored.
temperature protection, current limit circuit, and leading
edge blanking. PeakSwitch incorporates additional circuitry The current limit state machine reduces the current limit by
for adaptive current limit, line undervoltage sense, discrete amounts at light loads when PeakSwitch is likely to
programmable smart line-sense, auto-restart, adaptive switch in the audible frequency range. The lower current limit
switching cycle on-time extension, and frequency jitter. raises the effective switching frequency above the audio range
Figure 2 is a functional block diagram of the deviceʼs most and reduces the transformer flux density, including the associated
important features. audible noise. The state machine monitors the sequence of
EN/UV pin voltage levels to determine the load condition and
Oscillator adjusts the current limit level accordingly in discrete amounts.
of 277 kHz. Two signals are generated from the oscillator: the Under most operating conditions (except when close to no-load),
maximum duty cycle (DCMAX) signal and the clock signal that the low impedance of the source follower keeps the voltage on
indicates the beginning of each cycle. the EN/UV pin from going much below 1.0 V in the disabled
state. This improves the response time of the optocoupler that
The oscillator incorporates circuitry that introduces a small is usually connected to this pin.
amount of frequency jitter, typically 16 kHz peak-to-peak, to
minimize EMI emission. The modulation rate of the frequency 5.8 V Regulator and 6.3 V Shunt Voltage Clamp
jitter is set to 1.1 kHz to optimize EMI reduction for both The 5.8 V regulator charges the bypass capacitor connected to
average and quasi-peak emissions. The frequency jitter should the BYPASS pin to 5.8 V by drawing a current from the voltage
be measured with the oscilloscope triggered at the falling edge on the DRAIN pin whenever the MOSFET is off. The BYPASS
of the DRAIN waveform. The waveform in Figure 4 illustrates pin is the internal supply voltage node. When the MOSFET 2
the frequency jitter. is on, the PeakSwitch operates from the energy stored in the
bypass capacitor. The voltage on the DRAIN pin powers the
Enable Input and Current Limit State Machine bypass during startup.
The enable input circuit at the EN/UV pin consists of a low
impedance source follower output set at 1.0 V. The current There is a 6.3 V shunt regulator clamping the BYPASS pin at
6.3 V when current is provided through an external resistor
600
from the bias winding in normal operation. Powering the
PI-3942-022806
PeakSwitch device in this way minimizes no-load consumption

500 to about 150 mW at 265 VAC. Note that a bias winding must be
VDRAIN used to power the device. See Key Application Considerations
400 section for details.
300
BYPASS Pin Undervoltage
200 The BYPASS pin undervoltage circuitry disables the power
100 Once the BYPASS pin voltage drops below 4.8 V, it must rise
back to 5.8 V to enable (turn-on) the power MOSFET.
0
285 kHz
269 kHz
Over-Temperature Protection
The thermal shutdown circuitry senses the die temperature. The
threshold is typically set at 142 °C with 75 °C hysteresis. When
0 2.5 5 the die temperature rises above this threshold the power MOSFET
Time (µs) is disabled and remains disabled until the die temperature falls
Figure 4. Frequency Jitter. by 75 °C, at which point it is re-enabled. A large hysteresis of
2-125
Rev. H 06/06
PKS603-606
75 °C (typical) is provided to prevent overheating of the PC

board during a continuous fault condition.
Current Limit 1. Startup
The current limit circuit senses the current in the power MOSFET.
power MOSFET is turned off for the remainder of that cycle. The
current limit state machine reduces the current limit threshold
by discrete amounts under medium and light loads.
2. UV Resistor No
9. Start Switching
Present?
The leading edge blanking circuit inhibits the current limit
comparator for a short time (tLEB) after the power MOSFET is
turned on. This leading edge blanking time has been set so that Yes
current spikes caused by capacitance and secondary-side rectifier
reverse recovery time will not cause premature termination of
No
the MOSFET conduction portion of the switching cycle. 10. No Feedback
No 3. AC Input
>30 ms?
Present?
During startup and fault conditions the controller prevents (IEN>25 µA)
excessive drain currents by reducing the switching
frequency. Yes
Yes
Adaptive Current Limit 11. Stop Switching
When switching in the full current limit state, a skipped cycle (for 5 s)
followed by a cycle that terminates at the full current limit 4. Start Switching
implies that the line voltage is at high line. Under this condition,
adaptive current limit reduces the full current limit level by
approximately 10% in order to reduce output overload power.
The next skipped cycle disables the adaptive current limit
condition and restores the full current limit level. No
5. No Feedback
2 Line Undervoltage Sense Circuit
>30 ms?
The line undervoltage circuit prevents startup below the

programmed input voltage by connecting an external resistor Yes
from either the DC line or from an AC sense circuit (see
Figure 1) to the EN/UV pin. The complete function is described
in the flow chart shown in Figure 5. During power up or when 6. Stop Switching
the switching of the power MOSFET is disabled in auto-restart,
the current flowing into the EN/UV pin must exceed 25 µA to
initiate switching of the power MOSFET. During power up once
the threshold is exceeded, the Bypass pin must charge from
4.8 V to 5.8 V before MOSFET switching is initiated.
Yes Note: Normal operation
7. AC Input
(no fault present) is denoted
Present?
The line undervoltage circuit also detects when there is no (IEN>25 µA)
by looping with a “No” response
at decision box 5 or 10.
external resistor connected to the EN/UV pin (less than ~1 µA
into pin). In this case the line undervoltage function is disabled
and the device operates with a normal auto-restart function. No
Programmable Smart AC Line-Sense

When an external AC sense circuit is used (see Figure 1) the line 8. Reset A/R Latch
undervoltage sense circuit can be used to determine the reason
for a loss of feedback signal at the EN/UV pin. In the event of
a fault condition such as output overload, output short circuit,
or an open loop condition, the power MOSFET switching is PI-4014-062305
disabled after the EN/UV pin is not pulled low for 30 ms. If the
AC line is present (IEN > 25 µA) at the time switching is disabled, Figure 5. PeakSwitch Line-Sense Function Flow Chart.
2-126
Rev. H 06/06
PKS603-606
peak output power was required in low line conditions. On-time
PI-3943-031506
300 VDRAIN extension is disabled during the startup of the power supply.
200 PeakSwitch Operation
100 PeakSwitch devices operate in the current limit mode. When

enabled, the oscillator turns the power MOSFET on at the
0
beginning of each cycle. The MOSFET is turned off when the
10 current ramps up to the current limit or when the DCMAX limit
VDC-OUTPUT is reached. Since the highest current limit level and frequency
5
V
EN
0 5 10
Time (s) CLOCK
Figure 6. PeakSwitch Auto-Restart Operation.
D
MAX
the line undervoltage sense circuit prevents a restart
attempt until the AC input voltage is removed
(IEN <25 µA). Then the internal auto-restart latch is reset and
the power MOSFET switching will resume once the AC input I DRAIN
voltage is applied again (IEN >25 µA). This effectively provides
a latching shutdown function with AC reset during such a fault
condition.
When a brownout or line sag occurs, output regulation may be V DRAIN

lost and the EN/UV pin will receive no feedback (it is pulled
low). After 30 ms of no feedback, MOSFET switching is disabled.
Since the AC line is abnormally low (IEN <25 µA) MOSFET 2
switching remains disabled until normal line voltage is restored. PI-2749-050301
The power MOSFET switching will resume once the AC input
Figure 7. PeakSwitch Operation at Near Maximum Loading.
returns to normal (IEN >25 µA). This effectively disables the
latching shutdown function during such a condition.
V
EN
Auto-Restart (UV Resistor not Present)
In the event of a fault condition such as output overload,
CLOCK
output short circuit or an open loop condition, PeakSwitch
enters into auto-restart operation. An internal counter
clocked by the oscillator is reset every time the EN/UV pin D
MAX
is pulled low. When the EN/UV pin receives no feedback
for 30 ms, the power MOSFET switching is disabled for
5 seconds (150 ms for the first auto-restart event). The
auto-restart alternately enables and disables the switching I DRAIN
of the power MOSFET until the fault condition is removed.
Figure 6 illustrates auto-restart circuit operation in the presence
of an output short circuit.
Adaptive Switching Cycle On-time Extension

V DRAIN
Adaptive switching cycle on-time extension keeps the MOSFET
on until current limit is reached, instead of terminating after
the DCMAX signal goes low. This on-time extension is adaptive
because it only occurs after the ENABLE pin has been high PI-2667-090700
for approximately 750 µs, a condition that would arise if the
Figure 8. PeakSwitch Operation at Moderately Heavy Loading.
2-127
Rev. H 06/06
PKS603-606
of a PeakSwitch design are constant, the power delivered low. The Zener diode can be replaced by a TL431 reference
to the load is proportional to the primary inductance of the circuit for improved accuracy.
transformer and peak primary current squared. Hence, designing
the supply involves calculating the primary inductance of the ON/OFF Operation with Current Limit State Machine
transformer for the maximum output power required. If the The internal clock of the PeakSwitch runs all the time. At the
chosen PeakSwitch family member is appropriate for the power beginning of each clock cycle, it samples the EN/UV pin to
level, the current in the calculated inductance will ramp up to decide whether or not to implement a switch cycle, and based
current limit before the DCMAX limit is reached. on the sequence of samples over multiple cycles, it determines
the appropriate current limit. At high loads, when the EN/UV
Enable Function pin is high (less than 240 µA out of the pin), a switching cycle
PeakSwitch senses the EN/UV pin to determine whether or not with the full current limit occurs. At lighter loads, when EN/UV
to proceed with the next switching cycle as described earlier. is high, a switching cycle with a reduced current limit occurs.
The sequence of cycles is used to determine the current limit.
Once a cycle is started, it always completes the cycle (even when
the EN/UV pin changes state half way through the cycle). This
operation results in a power supply in which the output voltage V
EN
ripple is determined by the output capacitor, amount of energy
per switch cycle and the delay of the feedback.
CLOCK
The EN/UV pin signal is produced on the secondary by

comparing the power supply output voltage with a reference D
MAX
voltage. The EN/UV pin signal is high when the power supply
output voltage is less than the reference voltage.
In a typical implementation, the EN/UV pin is driven by an I DRAIN

optocoupler. The collector of the optocoupler transistor is
connected to the EN/UV pin and the emitter is connected to
the SOURCE pin. The optocoupler LED is connected in series
with a Zener diode across the DC output voltage to be regulated.
When the output voltage exceeds the target regulation voltage
2 level (optocoupler LED voltage drop plus Zener voltage), the V DRAIN
optocoupler LED will start to conduct, pulling the EN/UV pin
PI-2661-072400
Figure 10. PeakSwitch Operation at Very Light Load.

V
EN
200
PI-4331-031506
CLOCK
100 V
DC-INPUT
D 0
MAX
I DRAIN 0
V
BYPASS
300
200
100 V
DRAIN
V DRAIN 0
0 5 10
Time (ms)
PI-2377-091100
Figure 11. PeakSwitch Power Up With Optional External UV
Figure 9. PeakSwitch Operation at Medium Loading. Resistor (4 MΩ) Connected to EN/UV Pin.
2-128
Rev. H 06/06
PKS603-606
200
PI-4332-031506
PI-2395-030801
100 V 200
DC-INPUT
V
0 100 DC-INPUT
5 V 0
BYPASS
0 400
Modifying current schematic
300 300
200 V
200 DRAIN
100 100
V
DRAIN
0 0
0 5 10 0 2.5 5
Time (ms) Time (s)
Figure 12. PeakSwitch Power Up Without Optional External UV Figure 14. Slow Power-Down Timing With Optional External
Resistor Connected to EN/UV Pin. (4 MΩ) UV Resistor Connected to EN/UV Pin.
Power Up/Down
PI-2348-030801
The PeakSwitch requires only a 0.33 µF capacitor on the

200 BYPASS pin. Because of its small size, the time to charge this
V capacitor is kept to an absolute minimum, typically less than
100 DC-INPUT
1.5 ms. Due to the fast nature of the ON/OFF feedback, there
0 is no overshoot at the power supply output. When an external
resistor is connected from the positive DC input to the EN/UV
400 pin, the power MOSFET switching will be delayed during
power up until the DC line voltage exceeds the threshold (100 V).
2
300
Figures 11 and 12 show the power-up timing waveform in
200 V applications with and without an external resistor (4 MΩ)
DRAIN connected to the EN/UV pin.
100
During power-down, when an external resistor is used, the
0 power MOSFET will switch for 30 ms after the output loses
0 .5 1 regulation. The power MOSFET will then remain off without
Time (s) any glitches since the undervoltage function prohibits restart
Figure 13. Normal Power-Down Timing (Without UV). when the line voltage is low.
Figure 13 illustrates a typical power-down timing waveform.

At maximum peak load, PeakSwitch will conduct during nearly Figure 14 illustrates a very slow power-down timing waveform
all of its clock cycles (Figure 7). At the rated continuous load, as in standby applications. An external resistor is connected to
it will “skip” additional cycles in order to maintain voltage the EN/UV pin in this case to prevent unwanted restarts.
regulation at the power supply output (Figure 8). At medium
loads, cycles will be skipped and the current limit will be Current Limit Operation
reduced (Figure 9). At very light loads, the current limit will Each switching cycle is terminated when the DRAIN current
be reduced even further (Figure 10). Only a small percentage reaches the current limit of the PeakSwitch. Current limit
of cycles will occur to satisfy the internal power consumption operation provides good line ripple rejection.
of the power supply at no-load.
BYPASS Pin Capacitor
The response time of the ON/OFF control scheme is very The BYPASS pin uses a small 0.33 uF ceramic capacitor for
fast compared to normal PWM control. This provides decoupling the internal power supply.
tight regulation and excellent transient response.
2-129
Rev. H 06/06
PKS603-606
C10 R8
1 nF 68 Ω C11
250 VAC 1/2 W 330 pF
C13 R9 C14 30 V @
D9 47 µF 0.33 Ω L2 220 nF 1.07 A Cont.
1N4148 16 V 2W 5.3 µH 50 V 2.7 A Peak
C17 C5 VR1 9,10 D8

4.7 nF 2.2 nF 1N4764A Q1
STPS3150 C12
1 kV 1 kV 100 V 2N3906
330 µF R10
1 50 V VR2
C4 R11 1.5 kΩ
D1-D4 1N5255B
1N4007 150 µF 3 kΩ
7,8 28 V
400 V
R3
10 kΩ RTN
R15 1/2 W 3
2.2 Ω
4
D10
R4 UF4003 VR3
C15
22 Ω C6 R12 1N5258B
2 100 nF
1/2 W 47 µF 1 kΩ 36 V
L1 50 V
5.3 mH 35 V R7
D6 4.7 kΩ
5 Q2
FR106
R2 R1 FS202DA
1.3 MΩ 1.3 MΩ D7
T1
D5 R5 R6 EE25 1N4148
1N4007 2.2 MΩ 2.4 MΩ
C3 R16
680 nF t
O
2.7 MΩ C16
X1 RT1 100 nF
PeakSwitch
10 Ω D
U1 EN/UV
PKS606Y R14
BP 100 Ω
C7
C1-C2 C8 U2 R13
F1 100 nF
3.15 A 400 V
250 VAC 50 V
J1
L J3
PE
PI-4170-060706
N
Figure 15. PeakSwitch PKS606Y, 32 W Average, 81 W Peak, Universal Input Power Supply.
high switching frequency (a slow diode will not recover fast

Application Example enough under startup or output faults and therefore fail due
2 The circuit shown in Figure15 is a low cost, high efficiency, to excess dissipation). The use of a Zener in series with R3
flyback power supply designed to provide a 30 V, 1.06 A average, compared to a standard RCD clamp optimizes both EMI and
2.7 A peak output from universal input using the PKS606Y. energy efficiency.
The supply features undervoltage lockout and smartAC sense with Components D5, C7, and R5-6 provide AC line and undervoltage
fast reset. Latching overload, open loop, and hysteretic thermal sensing for PeakSwitch U1. By providing a separate rectified
shutdown protect both the supply and load under fault conditions voltage across C7 which is independent from the load condition,
while high efficiency (>80%) and very low no load consumption rather than using the main input capacitor, allows PeakSwitch
(<200 mW at 230 VAC) meets both active and standby efficiency to distinguish the cause of loss of regulation. It also provides
requirements. Output regulation is accomplished using a simple fast reset when the AC input is removed should latching
zener reference and opto coupler feedback. shutdown be triggered. Connecting R5 and R6 to C4 would
still provide undervoltage lockout but after a fault the user
Components C1, C2, C3, C10, C17, C19, R15, L1 and L2 provide would have to wait for C4 to discharge before the supply would
common mode and differential mode EMI filtering. Resistors reset. Resistor R16 provides a small amount of bias to the U1
R1 and R2 discharge C3 when AC power is removed to prevent ENABLE/UNDERVOLTAGE pin to retain the undervoltage
electric shock from touching the AC input. Thermistor RT1 lockout function during brown-out conditions.
limits the peak inrush current when AC is first applied.
With R5 and R6 present, switching is inhibited until the current
The rectified and filtered input voltage is applied to the primary into the EN/UV pin exceeds 25 µA. This allows the startup
winding of T1. The other side of the transformer primary is voltage to be programmed within the normal operating input
driven by the integrated MOSFET in U1. Diode D6, C5, R3, voltage range, preventing glitching of the output under abnormal,
R4, and VR1 clamp the U1 drain voltage to safe levels. Use low-voltage conditions and also on removal of the AC input.
of a fast diode (500 ns) vs ultrafast for D6 increases power
supply efficiency by recovering some of the clamp energy. A Under a fault condition, for example an output short circuit or
slow or standard recovery diode must not be used due to the broken feedback loop, if the line voltage is within the normal
2-130
Rev. H 06/06
PKS603-606
range (>25 µA into the EN/UV pin) the PeakSwitch will latch the maximum practical continuous output power level that can
off the power supply. This protects the load and supply from be obtained under the following assumed conditions:
a continuous fault condition. Removing the AC input resets
this condition. 1. The minimum DC input voltage is 100 V or higher for
85 VAC input, or 220 V or higher for 230 VAC input or
The output voltage is determined by the Zener diode VR2, the single 100/115 VAC with a voltage doubler.
voltage drop across R12 and the forward drop of D9 and the LED 2. Efficiency of 70% for Y/F packaged devices, 75% for P
of optocoupler U2. Resistor R13 provides bias current through packaged devices at 85-265 VAC, 75% for 230 VAC input
D9 and VR2, to ensure that VR2 is operating close to its knee all packages
voltage, while R12 sets the overall gain of the feedback loop. 3. Minimum data sheet value of I2f
Capacitor C15 boosts high frequency loop gain to help distribute 4. Transformer primary inductance tolerance of ±10%
the enabled switching cycles and reduce pulse grouping. 5. Reflected output voltage (VOR) of 135 V
6. Voltage only output of 15 V with an ultrafast PN rectifier
When the output voltage exceeds the feedback threshold voltage diode
current will flow in the optocoupler LED, causing current flow in 7. Continuous conduction mode operation with transient KP*
the transistor of the optocoupler. When this exceeds the ENABLE value of 0.25
pin threshold current the next switching cycle is inhibited, as the 8. Sufficient heatsinking is provided, either externally (Y/F
output voltage falls (below the feedback threshold) a conduction packages) or through an area of PC board copper (P package)
cycle is allowed to occur and by adjusting the number of enabled to keep the SOURCE pin or tab temperature at or below
cycles output regulation is maintained. As the load reduces 110 °C.
the number of enabled cycles decreases, lowering the effective 9. Device ambient temperature of 50 °C for open frame designs
switching frequency and scaling switching losses with load. and 40 °C for sealed adapters
This provides almost constant efficiency down to very light
loads, ideal for meeting energy efficiency requirements. *Below a value of 1, KP is the ratio of ripple to peak primary
current. To prevent reduced power capability due to premature
termination of switching cycles, a transient KP limit of ≥0.25 is
PeakSwitch device U1 is supplied from an auxillary winding recommended. This avoids the initial current limit (IINIT) being
on the transformer which is rectified and filtered by D7 and C6. exceeded at MOSFET turn on.
Resistor R7 provides approximately 2 mA of supply current into
the BYPASS pin capacitor C8. During startup or fault conditions Peak vs. Continuous Power
when the bias voltage is low, the BYPASS pin is supplied from
a high-voltage current source within U1, eliminating the need
PeakSwitch devices have current limit values that allow the
specified peak power values in the power table. With sufficient
2
for separate startup components. heatsinking these power levels could be provided continuously
however this may not be practical in many applications.
Components Q1-2, R9-11, R14, C13, C16, and VR3 form PeakSwitch is optimized for use in applications that have short
an overvoltage and overcurrent protection circuit. An output duration, high peak power demand, but a significantly lower
overvoltage or overcurrent condition fires SCR Q2, clamping continuous or average power. Typical ratios would be PPEAK ≥
the output voltage and forcing PeakSwitch U1 into latching 2 × PAVE. The high switching frequency of PeakSwitch allows
shutdown after 30 ms. The low pass filter formed by R10 and a small core size to be selected to deliver the peak power but
C13 adds a delay to the over-current sense. The shutdown the short duration prevents the transformer winding from
condition can be reset by briefly removing AC power for ~3 overheating. As average power increases it may be necessary to
seconds (maximum). The latching function within PeakSwitch select a larger transformer to allow increased copper area for the
significantly reduces the size of the SCR and output rectifier, windings based on the measured transformer temperature.
D8, as the short circuit current only flows for 50 ms before the
supply latches off. The power table provides some guidance between peak power
and continuous (average) power in sealed adapters, however
This design meets EN55022 Class B conducted EMI with specific applications may differ. For example if the peak power
>10 dB margin even with the output RTN directly connected condition is very low duty cycle, say a 2 second peak occurring
to earth ground. only at power up to accelerate a hard disk drive, then the
transformerʼs thermal rise is only a function of the continuous
Key Application Considerations average power. However if the peak power occurs every
200 ms for 50 ms then it would need to be considered.
PeakSwitch Design Considerations
In all cases the acceptable temperature rise of the PeakSwitch
Output Power Table
and transformer should be verified under worst case ambient
The data sheet maximum output power table (Table 1) represents
and load conditions.
2-131
Rev. H 06/06
PKS603-606
Power (W) provides sufficient margin to prevent core saturation under

startup or output short circuit conditions.
P3
Optocoupler CTR
To minimize the delay introduced by the optocoupler it is
recommended that a high (300-600%) CTR optocoupler is used
in PeakSwitch designs.
P2
PI-4329-030906
Bias Winding
All PeakSwitch designs must use a bias winding to feed operating
current into the BYPASS pin once the supply is operational.
P1 It is recommended that the value of the resistor from the bias
winding to the BYPASS pin be selected such that it supplies the
same current as the maximum data sheet drain supply current
(IS2) for the specific device being used.
∆t1 ∆t2 Time (t)
T PeakSwitch Layout Considerations

Figure 16. Continuous (Average) Output Power Calculation
Example. See Figure 17 for a recommended circuit board layout for
PeakSwitch.
Figure 16 shows how to calculate the average power
requirements for a design with two different peak load conditions. Single Point Grounding
Devices in Y and F packages have separate return pins for the
MOSFET source (S) and the controller (GND) connections
which are internally connected. Therefore connecting these
pins on the PC board is not recommended.
Where PX are the different output power conditions, ∆tX are the
durations of each peak power condition and T is the period of Devices in the P package do not have separate return pins
one cycle of the pulse load condtion. but in both cases the low current feedback signals and IC
decoupling, high MOSFET current and bias winding primary
2 Audible Noise return connection should route through separate traces to the
The cycle skipping mode of operation used in PeakSwitch Kelvin connection.
can generate audio frequency components in the transformer.
To limit this audible noise generation the transformer should The bias winding return connection is treated separately, even
be designed such that the peak core flux density is below though it carries low current. To route high currents away from
3000 Gauss (300 mT). Following this guideline and using the the device when the supply is subjected to line surge transients,
standard transformer production technique of dip varnishing the bias winding should be returned directly to the input bulk
practically eliminates audible noise. Vacuum impregnation capacitor.
of the transformer should not be used due to the high primary
capacitance and increased losses that result. Bypass Capacitor (CBP)
The BYPASS pin capacitor should be located as close as possible
Ceramic capacitors that use dielectrics such as Z5U, when used to the BYPASS and SOURCE pins.
in clamp circuits, may also generate audio noise. If this is the
case try replacing them with a capacitor having a different type of Primary Loop Area
dielectric or construction, for example a film type capacitor. The area of the primary loop that connects the input filter
capacitor, transformer primary and PeakSwitch together should
Maximum Flux Density be kept as small as possible.
A maximum value of 3000 Gauss during normal operation
is recommended to limit the maximum flux density under Primary Clamp Circuit
startup and output short circuit. Under these conditions the A clamp is used to limit the peak voltage on the DRAIN pin
output voltage is low and little reset of the transformer occurs at turn off. This can be achieved by using an RCD clamp or a
during the MOSFET off time. This allows the transformer flux Zener (~200 V) and diode clamp across the primary winding.
density to staircase above the normal operating level. A value of In all cases to minimize EMI care should be taken to minimize
3000 Gauss at the peak current limit of the selected device the circuit path from the clamp components to the transformer
together with the built in protection features of PeakSwitch and PeakSwitch.
2-132
Rev. H 06/06
PKS603-606
Safety Spacing Maximize hatched copper

heatsinking
Y1-
Capacitor
+ Output Output Filter
Rectifier Capacitor
HV Input Filter Capacitor
- PRI T
r
BIAS a SEC
n
s
PRI f
D
S o
r
m
S e
PeakSwitch EN/UV BIAS r
S
TOP VIEW S BP
CBP
Opto-
coupler - DC +
OUT
(a) PI-4326-060706

Y1- heatsinking
+ Capacitor
HV Input Filter Capacitor Output 2

Rectifier Output Filter
Capacitor
-
PRI T
r SEC
a
n
D PRI s
NC f
o
EN/UV BIAS r
GND m
e
TOP VIEW BIAS r
BP
CBP
Heat Sink
Opto-
coupler
- DC +
OUT
(b) PI-4327-031706
Figure 17. Recommended Layout for PeakSwitch in (a) P and (b) Y/F Packages.
2-133
Rev. H 06/06
PKS603-606
Thermal Considerations Quick Design Checklist

For the P package, the four SOURCE pins are internally
connected to the IC lead frame and provide the main path to As with any power supply design, all PeakSwitch designs
remove heat from the device. Therefore, all the SOURCE pins should be verified on the bench to make sure that component
should be connected to a copper area underneath the PeakSwitch specifications are not exceeded under worst case conditions. The
to act not only as a single point ground, but also as a heatsink. following minimum set of tests is strongly recommended:
As this area is connected to the quiet source node it should be
maximized for good heatsinking. Similarly, for axial output 1. Maximum drain voltage – Verify the VDS does not exceed
diodes, maximize the PCB area connected to the cathode. 650 V at highest input voltage and peak (overload) output
power. The 50 V margin to the 700 V BVDSS specification
Y-Capacitor allows margin for design variation.
The placement of the Y-capacitor should be directly from the 2. Maximum drain currents – Verify the simultaneous drain
primary input filter capacitor positive terminal to the common/ voltage and current levels are within the curve provided in
return terminal of the transformer secondary. If a second Figure 29 under worst case condition occurs. Typically this
Y-capacitor is required from primary to secondary return, connect occurs at startup (and during an output short circuit), highest
the primary side directly to the negative terminal of the input input line voltage and maximum ambient temperature.
capacitor. Such a placement will route high magnitude common When making this measurement using a current probe, to
mode surge currents away from the PeakSwitch device. Note monitor the drain current, ensure the results are corrected
– if an input π (C, L, C) EMI filter is used then the inductor in for the 10-20 ns current probe delay.
the filter should be placed between the negative terminals on 3. Maximum drain current – At maximum ambient temperature,
the input filter capacitors. maximum input voltage and peak output (overload) power,
verify drain current waveforms for any signs of transformer
Optocoupler saturation. If the transformer shows signs of saturation it
Place the optocoupler physically close to the PeakSwitch to should be redesigned with a lower flux density or a higher
minimize the primary side trace lengths. Keep the high current quality core material should be used. To prevent false
high-voltage drain and clamp traces away from the optocoupler triggering of the current limit, verify the leading edge current
to prevent noise pick up. spike event is below IINIT(MIN) at the end of the tLEB(MIN).
Under all conditions the maximum drain current should be
Output Diode below the absolute maximum limit specified in the Absolute
For best performance, the area of the loop connecting the Maximum Ratings section.
2 secondary winding, the Output Diode and the Output Filter 4. Thermal Check – At specified maximum output power,
Capacitor, should be minimized. In addition, sufficient copper minimum input voltage and maximum ambient temperature,
area should be provided at the anode and cathode terminal verify that the temperature specifications are not exceeded for
of the diode for heatsinking. A larger area is preferred at the PeakSwitch, transformer, output diode and output capacitors.
quite cathode terminal. A large anode area can increase high Enough thermal margin should be allowed for part-to-part
frequency radiated EMI. variation of the RDS(ON) of PeakSwitch as specified in the
data sheet. Under low line, maximum power, a maximum
PeakSwitch SOURCE pin or tab temperature of 110 °C is
recommended to allow for these variations.
Design Tools

Power Integrations web site: www.powerint.com.
2-134
Rev. H 06/06
PKS603-606

DRAIN Voltage ................................................-0.3 V to 700 V Notes:
DRAIN Peak Current: ....................... ...... 2 × ILIMIT (Typical)(5) 1. All voltages referenced to SOURCE, TA = 25 °C.
EN/UV Voltage ....................................................-0.3 V to 9 V 2. Normally limited by internal circuitry.
EN/UV Current .................................................... ....... 100 mA 3. 1/16 in. from case for 5 seconds.
BYPASS Voltage ..................................................-0.3 V to 9 V 4. Maximum ratings specified may be applied one at a time,
Storage Temperature ......................................-65 °C to 150 °C without causing permanent damage to the product.
Operating Junction Temperature(2) .................-40 °C to 150 °C Exposure to Absolute Maximum Rating conditions for
Lead Temperature(3)................ ....................................... 260 °C extended periods of time may affect product reliability.
5. Peak DRAIN current is allowed while the DRAIN voltage
is simultaneously less than 400 V. See also Figure 29.
THERMAL IMPEDANCE
Thermal Impedance: Y/F Package: Notes:
(θJA)(1) ........................................80 °C/W 1. Free standing with no heatsink.
(θJC)(2) ..........................................2 °C/W 2. Measured at the back surface of tab.
P Package: 3. Soldered to 0.36 sq. in. (232 mm2), 2 oz. (610 g/m2) copper clad.
(θJA) .....................70 °C/W(3); 60 °C/W(4) 4. Soldered to 1 sq. in. (645 mm2), 2 oz. (610 g/m2) copper clad.
(θJC)(5) ..................................... 10 °C/W(5) 5. Measured on the SOURCE pin close to plastic interface.
Conditions
SOURCE = 0 V; TJ = -40 to 125 °C
See Figure 18
CONTROL FUNCTIONS
TJ = 25 °C Average 250 277 304
Output Frequency fOSC
See Figure 4 Peak-Peak Jitter 16
kHz
2
Maximum Duty
DCMAX S1 Open 62 65 68 %
Cycle
EN/UV Pin Turnoff
IDIS -350 -240 -200 µA
Threshold Current
EN/UV Pin IEN/UV = -125 µA 0.4 1.0 1.5
VEN V
Voltage IEN/UV = 25 µA 1.3 2.0 2.7
IS1 VEN/UV = 0 V 350 475 600 µA
PKS603 460 570 690
DRAIN Supply EN/UV Open
(MOSFET PKS604 600 725 870
Current IS2 µA
Switching) PKS605 700 875 1050
See Note A, B
PKS606 950 1175 1400
VBP = 0 V, PKS603-604 -7.5 -5.0 -2.5
ICH1 TJ = 25 °C
BYPASS Pin See Note C PKS605-606 -10.0 -6.6 -3.2
mA
Charge Current VBP = 4 V, PKS603-604 -4.5 -3.0 -1.5
ICH2 TJ = 25 °C
See Note C PKS605-606 -6.5 -4.5 -2.5
2-135
Rev. H 06/06
PKS603-606
Conditions
SOURCE = 0 V; TJ = -40 to 125 °C
See Figure 18
BYPASS Pin Shunt V See Note D 6.0 6.3 6.7 V
Regulator Voltage BP(SH)
BYPASS Pin VBP 5.5 5.8 6.15 V

Voltage
BYPASS Pin VBPH 0.8 1.0 1.3 V
Voltage Hysteresis
EN/UV Pin Line
Undervoltage ILUV TJ = 25 °C 22.5 25 27.5 µA
Threshold
CIRCUIT PROTECTION
PKS603 P di/dt = 200 mA/µs
0.75 0.81 0.87
TJ = 25 °C See Note E
PKS604 P/Y/F di/dt = 290 mA/µs
1.35 1.45 1.55
PKS605 P di/dt = 290 mA/µs
1.35 1.45 1.55
Current Limit ILIMIT A
PKS605 Y/F di/dt = 325 mA/µs
1.76 1.89 2.02
2 PKS606 P di/dt = 255 mA/µs
1.40 1.51 1.62
PKS606 Y/F di/dt = 660 mA/µs
2.60 2.80 3.00
PKS603 P
di/dt = 200 mA/µs 164 182 204
TJ = 25 °C
PKS604 P/Y/F
di/dt = 290 mA/µs 524 582 652
TJ = 25 °C
PKS605 P
di/dt = 290 mA/µs 524 582 652
TJ = 25 °C
Power Coefficient If
2
A2kHz
PKS605 Y/F
di/dt = 325 mA/µs 890 989 1108
TJ = 25 °C
PKS606 P
di/dt = 255 mA/µs 569 632 708
TJ = 25 °C
PKS606 Y/F
di/dt = 660 mA/µs 1955 2172 2433
TJ = 25 °C
See Figure 21 0.75 ×

Initial Current Limit IINIT
See Note F ILIMIT(Min)
mA
2-136
Rev. H 06/06
PKS603-606
Conditions
SOURCE = 0 V; TJ = -40 to 125 °C
See Figure 18
tLEB 170 215 ns
Current Limit TJ = 25 °C
tILD 150 ns
Delay See Notes F, G
Thermal Shutdown
135 142 150 °C
Temperature
Thermal Shutdown
75 °C
Hysteresis
OUTPUT
PKS603 TJ = 25 °C 7.8 9.0
ID = 81 mA TJ = 100 °C 11.7 13.5
PKS604 TJ = 25 °C 5.2 6.0

ID = 150 mA TJ = 100 °C 7.8 9.0
ON-State
RDS(ON) Ω
Resistance PKS605 TJ = 25 °C 3.9 4.5
ID = 200 mA TJ = 100 °C 5.8 6.7
PKS606 TJ = 25 °C 2.6 3.0

ID = 300 mA TJ = 100 °C 3.9 4.5 2
VBP = 6.2 V
VEN/UV = 0 V
IDSS1 VDS = 560 V 200
OFF-State Drain TJ = 125 °C
See Note H µA
Leakage Current
VDS = 375 V
VBP = 6.2 V
IDSS2 TJ = 50 °C 15
VEN/UV = 0 V
See Note H
Breakdown VBP = 6.2 V, VEN/UV = 0 V,
BVDSS 700 V
Voltage See Note I, TJ = 25 °C
Drain Supply
50 V
Voltage
Output EN/UV
tEN/UV See Figure 20 5 µs
Delay
Output Disable
tDST 0.5 µs
Setup Time
Auto-Restart TJ = 25 °C
tAR 30 ms
ON-Time See Note J
Auto-Restart
tAROFF See Note K 5 s
Off-Time
2-137
Rev. H 06/06
PKS603-606
NOTES:
A. Total current consumption is the sum of IS1 and IDSS when EN/UV pin is shorted to ground (MOSFET not
switching) and the sum of IS2 and IDSS when EN/UV pin is open (MOSFET switching).
B. Since the output MOSFET is switching, it is difficult to isolate the switching current from the supply current at the
DRAIN. An alternative is to measure the BYPASS pin current at 6.1 V.
C. See Typical Performance Characteristics section for BYPASS pin startup charging waveform.
D. BYPASS pin is externally supplied (bias winding).
F. This parameter is derived from characterization.
G. This parameter is derived from the change in current limit measured at 1X and 4X of the di/dt shown in the ILIMIT
specification.
H. IDSS1 is the worst case OFF state leakage specification at 80% of BVDSS and maximum operating junction
temperature. IDSS2 is a typical specification under worst case application conditions (rectified 265 VAC) for no-load
consumption calculations.
I. Breakdown voltage may be checked against minimum BVDSS specification by ramping the DRAIN pin voltage up
J. Auto-restart on time has the same temperature characteristics as the oscillator (inversely proportional to
frequency). Auto-restart on-time is extended during startup and certain fault conditions because the controller
reduces its oscillator clock frequency to prevent excessive drain currents. If excessive drain currents are still
occuring half way through the auto-restart on-time, output MOSFET switching is disabled for the remainder of that
auto-restart on-time episode (if the line is not sensed) or the supply latches off (if the line is sensed and adequate
2 line voltage is present).
K. Only applicable if no UV resistor is present at the EN/UV pin. 5 s applies only if the preceding switching auto-
restart event did not result in EN/UV pin going low. In that event, the first auto-restart off-time is 150 ms.
2-138
Rev. H 06/06
PKS603-606
470 Ω
5W S2
470 Ω
S D
S1
S
4 MΩ
S EN/UV 50 V
S
BP 10 V
150 V
0.33 µF
PI-4317-030606
Figure 18. PeakSwitch General Test Circuit.
DCMAX
(internal signal)
tP
EN/UV
tEN/UV
VDRAIN
tP =
1
fOSC
2
PI-2364-012699
PI-4328-030806
tLEB (Blanking Time)
0.8
IINIT(MIN)
ILIMIT(MIN) @ 100 °C
Figure 21. Current Limit Envelope.
2-139
Rev. H 06/06
PKS603-606
1.1 1.2
PI-2213-012301
PI-4294-022806
1.0
Breakdown Voltage
Output Frequency
0.8
1.0 0.6
0.4
0.2
0.9 0
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125
1.2 1.4
PI-4295-020806
PI-4297-020806
1.2
Normalized Current Limit

1
Standard Current Limit
1.0
0.8
0.8
0.6
0.6
0.4
2 0.4
0.2 0.2
0 0
-50 0 50 100 150 1 2 3 4
Junction Temperature (°C) Normalized di/dt
Figure 24. Standard Current Limit vs. Temperature. Figure 25. Current Limit vs. di/dt.
1.2 1000
PI-4307-030806
PI-4308-021306
1.0
Drain Current (A)
0.8 100
Scaling Factors:
PKS603 1.0
0.6 Scaling Factors:
PKS604 1.5
PKS603 1.0 PKS605 2.0
PKS604 1.5 PKS606 3.0
0.4 PKS605 2.0 10
PKS606 3.0
0.2
TJ = 25 °C
TJ = 100 °C
0 1
0 2 4 6 8 10 12 14 16 18 20 0 100 200 300 400 500 600
Drain Voltage (V) Drain Voltage (V)
Figure 26. Output Characteristic. Figure 27. COSS vs. Drain Voltage.
2-140
Rev. H 06/06
PKS603-606
1.2 2.5
PI-4296-020806
PI-4330-031606
(Normalized to Typical ILIMIT)
1
Under-Voltage Theshold
2
0.8
Drain Current
1.5
0.6
1
0.4
0.2 0.5
0 0
-50 0 50 100 150 0 100 200 300 400 500 600 700 800
Junction Temperature (°C) Drain Voltage (V)
Figure 28. Undervoltage Threshold vs. Temperature. Figure 29. Maximum Allowable Drain Current vs.
Drain Voltage.

PeakSwitch Product Family
Series Number
Package Identifier
P Plastic DIP-8C
Y Plastic TO-220-7C
F Plastic TO-262-7C 2
Lead Finish
PKS 604 P N N Pure Matte Tin (Pb-Free)
Revision Notes Date

F Final Release Data Sheet. 3/06
G Revised device symbol in Figures 1 and 15 to be consistent with other PI documentation (added second
4/06
ground connection). Revised layout of Figure 17 (PI-4326).
H Revised grounding in Figure 1 to match actual implementation. 6/06
2-141
Rev. H 06/06
TNY274-280
TNY274-280
TinySwitch-III Family
®
Energy-Efficient, Off-Line Switcher with

Enhanced Flexibility and Extended Power Range
Product Highlights + +
Lowest System Cost with Enhanced Flexibility DC
Output
• Simple ON/OFF control, no loop compensation needed
-
• Selectable current limit through BP/M capacitor value
Wide-Range
- Higher current limit extends peak power or, in open HV DC Input
D
EN/UV
frame applications, maximum continuous power BP/M
TinySwitch-III
- Lower current limit improves efficiency in enclosed S
adapters/chargers
-
- Allows optimum TinySwitch-III choice by swapping PI-4095-082205
devices with no other circuit redesign
• Tight I2f parameter tolerance reduces system cost Figure 1. Typical Standby Application.
- Maximizes MOSFET and magnetics power delivery
- Minimizes max overload power, reducing cost of OUTPUT POWER TABLE
transformer, primary clamp & secondary components 230 VAC ±15% 85-265 VAC
• ON-time extension – extends low line regulation range/
hold-up time to reduce input bulk capacitance PRODUCT3 Peak or Peak or
• Self-biased: no bias winding or bias components Adapter1 Open Adapter1 Open
• Frequency jittering reduces EMI filter costs Frame2 Frame2
• Pin-out simplifies heatsinking to the PCB TNY274 P or G 6W 11 W 5W 8.5 W
• SOURCE pins are electrically quiet for low EMI TNY275 P or G 8.5 W 15 W 6W 11.5 W
2 Enhanced Safety and Reliability Features TNY276 P or G 10 W 19 W 7W 15 W
• Accurate hysteretic thermal shutdown protection with TNY277 P or G 13 W 23.5 W 8W 18 W
automatic recovery eliminates need for manual reset TNY278 P or G 16 W 28 W 10 W 21.5 W
• Improved auto-restart delivers <3% of maximum power TNY279 P or G 18 W 32 W 12 W 25 W
in short circuit and open loop fault conditions
TNY280 P or G 20 W 36.5 W 14 W 28.5 W
• Output overvoltage shutdown with optional Zener
• Line undervoltage detect threshold set using a single Table 1. Output Power Table.
optional resistor Notes:
1. Minimum continuous power in a typical non-ventilated enclosed
• Very low component count enhances reliability and adapter measured at 50 °C ambient. Use of an external heatsink
enables single-sided printed circuit board layout will increase power capability
• High bandwidth provides fast turn on with no overshoot 2. Minimum peak power capability in any design or minimum
continuous power in an open frame design (see Key Application
and excellent transient load response Considerations).
• Extended creepage between DRAIN and all other pins 3. Packages: P: DIP-8C, G: SMD-8C. See Part Ordering
improves field reliability Information.
®
EcoSmart – Extremely Energy-Efficient • PC Standby and other auxiliary supplies
• Easily meets all global energy efficiency regulations • DVD/PVR and other low power set top decoders
• No-load <150 mW at 265 VAC without bias winding, • Supplies for appliances, industrial systems, metering, etc.
<50 mW with bias winding
• ON/OFF control provides constant efficiency down to Description
very light loads – ideal for mandatory CEC regulations
and 1 W PC standby requirements TinySwitch-III incorporates a 700 V power MOSFET, oscillator,
high-voltage switched current source, current limit (user
Applications selectable) and thermal shutdown circuitry. The IC family uses
• Chargers/adapters for cell/cordless phones, PDAs, digital an ON/OFF control scheme and offers a design flexible solution
cameras, MP3/portable audio, shavers, etc. with a low system cost and extended power capability.
2-142
Rev. G 06/06
TNY274-280
BYPASS/
MULTI-FUNCTION DRAIN
(BP/M) (D)
REGULATOR
5.85 V
LINE UNDER-VOLTAGE
115 µA 25 µA
FAULT BYPASS PIN
PRESENT UNDER-VOLTAGE
+
AUTO- BYPASS
RESTART -
CAPACITOR
COUNTER SELECT AND 5.85 V VI
CURRENT 4.9 V LIMIT
6.4 V RESET LIMIT STATE

MACHINE
CURRENT LIMIT
COMPARATOR
ENABLE -
JITTER
CLOCK
1.0 V + VT
DCMAX THERMAL
SHUTDOWN
OSCILLATOR
ENABLE/ S Q
1.0 V
UNDER-
VOLTAGE
R Q
(EN/UV)
LEADING
OVP EDGE
LATCH BLANKING
SOURCE
(S)
PI-4077-062306
2

DRAIN (D) Pin: P Package (DIP-8C)
This pin is the power MOSFET drain connection. It provides G Package (SMD-8C)
internal operating current for both startup and steady-state
operation. EN/UV 8 S
1
BYPASS/MULTI-FUNCTION (BP/M) Pin: BP/M 2 7 S

This pin has multiple functions:
6 S
1. It is the connection point for an external bypass capacitor D 4 5 S

for the internally generated 5.85 V supply.
2. It is a mode selector for the current limit value, depending
on the value of the capacitance added. Use of a 0.1 µF
PI-4078-080905
capacitor results in the standard current limit value. Use of
a 1 µF capacitor results in the current limit being reduced to Figure 3. Pin Configuration.
that of the next smaller device size. Use of a 10 µF capacitor
results in the current limit being increased to that of the next with a Zener connected from the BP/M pin to a bias winding
larger device size for TNY275-280. supply.
3. It provides a shutdown function. When the current into
the bypass pin exceeds ISD, the device latches off until the ENABLE/UNDERVOLTAGE (EN/UV) Pin:
BP/M voltage drops below 4.9 V, during a power down. This pin has dual functions: enable input and line undervoltage
This can be used to provide an output overvoltage function sense. During normal operation, switching of the power
2-143
Rev. G 06/06
TNY274-280
MOSFET is controlled by this pin. MOSFET switching is maximum duty cycle signal (DCMAX) and the clock signal that
terminated when a current greater than a threshold current is indicates the beginning of each cycle.
drawn from this pin. Switching resumes when the current being
pulled from the pin drops to less than a threshold current. A The oscillator incorporates circuitry that introduces a small
modulation of the threshold current reduces group pulsing. The amount of frequency jitter, typically 8 kHz peak-to-peak, to
threshold current is between 75 µA and 115 µA. minimize EMI emission. The modulation rate of the frequency
jitter is set to 1 kHz to optimize EMI reduction for both average
The EN/UV pin also senses line undervoltage conditions through and quasi-peak emissions. The frequency jitter should be
an external resistor connected to the DC line voltage. If there is measured with the oscilloscope triggered at the falling edge of
no external resistor connected to this pin, TinySwitch-III detects the DRAIN waveform. The waveform in Figure 4 illustrates
its absence and disables the line undervoltage function. the frequency jitter.
SOURCE (S) Pin: Enable Input and Current Limit State Machine
This pin is internally connected to the output MOSFET source The enable input circuit at the EN/UV pin consists of a low
for high-voltage power return and control circuit common. impedance source follower output set at 1.2 V. The current
through the source follower is limited to 115 µA. When the
TinySwitch-III current out of this pin exceeds the threshold current, a low
logic level (disable) is generated at the output of the enable
Functional Description circuit, until the current out of this pin is reduced to less than
TinySwitch-III combines a high-voltage power MOSFET the threshold current. This enable circuit output is sampled
switch with a power supply controller in one device. Unlike at the beginning of each cycle on the rising edge of the clock
conventional PWM (pulse width modulator) controllers, it uses signal. If high, the power MOSFET is turned on for that cycle
a simple ON/OFF control to regulate the output voltage. (enabled). If low, the power MOSFET remains off (disabled).
Since the sampling is done only at the beginning of each cycle,
The controller consists of an oscillator, enable circuit (sense and subsequent changes in the EN/UV pin voltage or current during
logic), current limit state machine, 5.85 V regulator, BYPASS/ the remainder of the cycle are ignored.
MULTI-FUNCTION pin undervoltage, overvoltage circuit, and
current limit selection circuitry, over- temperature protection, The current limit state machine reduces the current limit by
current limit circuit, leading edge blanking, and a 700 V power discrete amounts at light loads when TinySwitch-III is likely to
switch in the audible frequency range. The lower current limit
2 MOSFET. TinySwitch-III incorporates additional circuitry for
line undervoltage sense, auto-restart, adaptive switching cycle raises the effective switching frequency above the audio range
on-time extension, and frequency jitter. Figure 2 shows the and reduces the transformer flux density, including the associated
functional block diagram with the most important features. audible noise. The state machine monitors the sequence of
enable events to determine the load condition and adjusts the
Oscillator current limit level accordingly in discrete amounts.
of 132 kHz. Two signals are generated from the oscillator: the Under most operating conditions (except when close to no-load),
the low impedance of the source follower keeps the voltage on
600 the EN/UV pin from going much below 1.2 V in the disabled
PI-2741-041901
state. This improves the response time of the optocoupler that 3

500
is usually connected to this pin.
VDRAIN
400
300 The 5.85 V regulator charges the bypass capacitor connected
to the BYPASS pin to 5.85 V by drawing a current from the
200 voltage on the DRAIN pin whenever the MOSFET is off. The
BYPASS/MULTI-FUNCTION pin is the internal supply voltage
100
node. When the MOSFET is on, the device operates from the
0
energy stored in the bypass capacitor. Extremely low power
136 kHz consumption of the internal circuitry allows TinySwitch-III to
128 kHz operate continuously from current it takes from the DRAIN
pin. A bypass capacitor value of 0.1 µF is sufficient for both
high frequency decoupling and energy storage.
0 5 10
Time (µs)
Figure 4. Frequency Jitter.
2-144
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In addition, there is a 6.4 V shunt regulator clamping the Auto-Restart

BYPASS/MULTI-FUNCTION pin at 6.4 V when current In the event of a fault condition such as output overload, output
is provided to the BYPASS/MULTI-FUNCTION pin short circuit, or an open loop condition, TinySwitch-III enters
through an external resistor. This facilitates powering of into auto-restart operation. An internal counter clocked by the
TinySwitch-III externally through a bias winding to decrease oscillator is reset every time the EN/UV pin is pulled low. If the
the no-load consumption to well below 50 mW. EN/UV pin is not pulled low for 64 ms, the power MOSFET
switching is normally disabled for 2.5 seconds (except in the
BYPASS/MULTI-FUNCTION Pin Undervoltage case of line undervoltage condition, in which case it is disabled
The BYPASS/MULTI-FUNCTION pin undervoltage circuitry until the condition is removed). The auto-restart alternately
disables the power MOSFET when the BYPASS/MULTI- enables and disables the switching of the power MOSFET until
FUNCTION pin voltage drops below 4.9 V in steady state the fault condition is removed. Figure 5 illustrates auto-restart
operation. Once the BYPASS/MULTI-FUNCTION pin voltage circuit operation in the presence of an output short circuit.
drops below 4.9 V in steady state operation, it must rise back
to 5.85 V to enable (turn-on) the power MOSFET. In the event of a line undervoltage condition, the switching of
the power MOSFET is disabled beyond its normal 2.5 seconds
Over-Temperature Protection until the line undervoltage condition ends.
The thermal shutdown circuitry senses the die temperature. The
threshold is typically set at 142 °C with 75 °C hysteresis. When Adaptive Switching Cycle On-Time Extension
the die temperature rises above this threshold the power MOSFET Adaptive switching cycle on-time extension keeps the cycle
is disabled and remains disabled until the die temperature falls on until current limit is reached, instead of prematurely
by 75 °C, at which point it is re-enabled. A large hysteresis of terminating after the DCMAX signal goes low. This feature
75 °C (typical) is provided to prevent overheating of the PC reduces the minimum input voltage required to maintain
board due to a continuous fault condition. regulation, extending hold-up time and minimizing the size
of bulk capacitor required. The on-time extension is disabled
Current Limit during the startup of the power supply, until the power supply
The current limit circuit senses the current in the power MOSFET. output reaches regulation.
power MOSFET is turned off for the remainder of that cycle. The Line Undervoltage Sense Circuit
current limit state machine reduces the current limit threshold The DC line voltage can be monitored by connecting an external
by discrete amounts under medium and light loads. resistor from the DC line to the EN/UV pin. During power up or
when the switching of the power MOSFET is disabled in auto- 2
The leading edge blanking circuit inhibits the current limit restart, the current into the EN/UV pin must exceed 25 µA to
comparator for a short time (tLEB) after the power MOSFET is initiate switching of the power MOSFET. During power up, this
turned on. This leading edge blanking time has been set so that is accomplished by holding the BYPASS/MULTI-FUNCTION
current spikes caused by capacitance and secondary-side rectifier pin to 4.9 V while the line undervoltage condition exists. The
reverse recovery time will not cause premature termination of BYPASS/MULTI-FUNCTION pin then rises from 4.9 V to
the switching pulse. 5.85 V when the line undervoltage condition goes away. When the
switching of the power MOSFET is disabled in auto-restart mode
PI-4098-082305
and a line undervoltage condition exists, the auto-restart counter

300 V
DRAIN
is stopped. This stretches the disable time beyond its normal
2.5 seconds until the line undervoltage condition ends.
200
The line undervoltage circuit also detects when there is no
100
external resistor connected to the EN/UV pin (less than
0
~2 µA into the pin). In this case the line undervoltage function
is disabled.
10
V TinySwitch-III Operation
DC-OUTPUT
5
TinySwitch-III devices operate in the current limit mode. When
0
enabled, the oscillator turns the power MOSFET on at the
beginning of each cycle. The MOSFET is turned off when the
0 2500 5000 current ramps up to the current limit or when the DCMAX limit is
Time (ms) reached. Since the highest current limit level and frequency of
Figure 5. Auto-Restart Operation. a TinySwitch-III design are constant, the power delivered to the
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load is proportional to the primary inductance of the transformer not to proceed with the next switching cycle. The sequence of
and peak primary current squared. Hence, designing the supply cycles is used to determine the current limit. Once a cycle is
involves calculating the primary inductance of the transformer started, it always completes the cycle (even when the EN/UV
for the maximum output power required. If the TinySwitch-III pin changes state half way through the cycle). This operation
is appropriately chosen for the power level, the current in the results in a power supply in which the output voltage ripple
calculated inductance will ramp up to current limit before the is determined by the output capacitor, amount of energy per
DCMAX limit is reached. switch cycle and the delay of the feedback.
Enable Function The EN/UV pin signal is generated on the secondary by

TinySwitch-III senses the EN/UV pin to determine whether or comparing the power supply output voltage with a reference
voltage. The EN/UV pin signal is high when the power supply
output voltage is less than the reference voltage.
V
EN In a typical implementation, the EN/UV pin is driven by an
optocoupler. The collector of the optocoupler transistor is
CLOCK connected to the EN/UV pin and the emitter is connected to
the SOURCE pin. The optocoupler LED is connected in series
DC with a Zener diode across the DC output voltage to be regulated.
MAX
When the output voltage exceeds the target regulation voltage
level (optocoupler LED voltage drop plus Zener voltage), the
optocoupler LED will start to conduct, pulling the EN/UV pin
I DRAIN low. The Zener diode can be replaced by a TL431 reference
circuit for improved accuracy.
ON/OFF Operation with Current Limit State Machine

The internal clock of the TinySwitch-III runs all the time. At
the beginning of each clock cycle, it samples the EN/UV pin to
V DRAIN
decide whether or not to implement a switch cycle, and based
on the sequence of samples over multiple cycles, it determines
the appropriate current limit. At high loads, the state machine
2 PI-2749-082305
sets the current limit to its highest value. At lighter loads, the
state machine sets the current limit to reduced values.
Figure 6. Operation at Near Maximum Loading.
V V
EN EN
CLOCK CLOCK
DC DC
MAX MAX
I DRAIN I DRAIN
V DRAIN
V DRAIN
PI-2667-082305 PI-2377-082305
Figure 7. Operation at Moderately Heavy Loading. Figure 8. Operation at Medium Loading.
2-146
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200
PI-2381-1030801
V V
EN 100
DC-INPUT
0
CLOCK
10
DC
MAX V
5 BYPASS
I DRAIN 400
200 V
DRAIN
0
0 1 2
Time (ms)
V DRAIN Figure 11. Power Up Without Optional External UV Resistor
Connected to EN/UV Pin.
PI-2348-030801
PI-2661-082305
Figure 9. Operation at Very Light Load. 200

V
100 DC-INPUT
At near maximum load, TinySwitch-III will conduct during 0

nearly all of its clock cycles (Figure 6). At slightly lower load,
it will “skip” additional cycles in order to maintain voltage 400
regulation at the power supply output (Figure 7). At medium 300
loads, cycles will be skipped and the current limit will be reduced
(Figure 8). At very light loads, the current limit will be reduced V
2
200
DRAIN
even further (Figure 9). Only a small percentage of cycles will
occur to satisfy the power consumption of the power supply. 100
0
The response time of the ON/OFF control scheme is very fast 0 .5 1
compared to PWM control. This provides tight regulation and Time (s)
excellent transient response.
Figure 12. Normal Power Down Timing (without UV).
200
PI-2383-030801
PI-2395-030801
100 V
DC-INPUT 200
V
0 100 DC-INPUT
10 0
V
5 BYPASS 400
0 300
400 200 V
DRAIN
200 V 100
DRAIN
0 0
0 1 2 0 2.5 5
Time (ms) Time (s)
Figure 10. Power Up with Optional External UV Resistor (4 MΩ) Figure 13. Slow Power Down Timing with Optional External
Connected to EN/UV Pin. (4 MΩ) UV Resistor Connected to EN/UV Pin.
2-147
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Power Up/Down Functional Description above). This has two main benefits.
The TinySwitch-III requires only a 0.1 µF capacitor on the First, for a nominal application, this eliminates the cost of a
BYPASS/MULTI-FUNCTION pin to operate with standard bias winding and associated components. Secondly, for battery
current limit. Because of its small size, the time to charge this charger applications, the current-voltage characteristic often
capacitor is kept to an absolute minimum, typically 0.6 ms. The allows the output voltage to fall close to zero volts while still
time to charge will vary in proportion to the BYPASS/MULTI- delivering power. TinySwitch-III accomplishes this without a
FUNCTION pin capacitor value when selecting different current forward bias winding and its many associated components. For
limits. Due to the high bandwidth of the ON/OFF feedback, applications that require very low no-load power consumption
there is no overshoot at the power supply output. When an (50 mW), a resistor from a bias winding to the BYPASS/
external resistor (4 MΩ) is connected from the positive DC MULTI-FUNCTION pin can provide the power to the chip.
input to the EN/UV pin, the power MOSFET switching will The minimum recommended current supplied is 1 mA. The
be delayed during power up until the DC line voltage exceeds BYPASS/MULTI-FUNCTION pin in this case will be clamped
the threshold (100 V). Figures 10 and 11 show the power up at 6.4 V. This method will eliminate the power draw from the
timing waveform in applications with and without an external DRAIN pin, thereby reducing the no-load power consumption
resistor (4 MΩ) connected to the EN/UV pin. and improving full-load efficiency.
Under startup and overload conditions, when the conduction time Current Limit Operation
is less than 400 ns, the device reduces the switching frequency Each switching cycle is terminated when the DRAIN current
to maintain control of the peak drain current. reaches the current limit of the device. Current limit operation
provides good line ripple rejection and relatively constant power
During power down, when an external resistor is used, the delivery independent of input voltage.
power MOSFET will switch for 64 ms after the output loses
regulation. The power MOSFET will then remain off without BYPASS/MULTI-FUNCTION Pin Capacitor
any glitches since the undervoltage function prohibits restart The BYPASS/MULTI-FUNCTION pin can use a ceramic
when the line voltage is low. capacitor as small as 0.1 µF for decoupling the internal power
supply of the device. A larger capacitor size can be used to adjust
Figure 12 illustrates a typical power down timing waveform. the current limit. For TNY275-280, a 1 µF BP/M pin capacitor
Figure 13 illustrates a very slow power down timing waveform will select a lower current limit equal to the standard current
as in standby applications. The external resistor (4 MΩ) is limit of the next smaller device and a 10 µF BP/M pin capacitor
connected to the EN/UV pin in this case to prevent unwanted will select a higher current limit equal to the standard current
2 restarts. limit of the next larger device. The higher current limit level of
the TNY280 is set to 850 mA typical. The TNY274 MOSFET
No bias winding is needed to provide power to the chip does not have the capability for increased current limit so this
because it draws the power directly from the DRAIN pin (see feature is not available in this device.
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TNY274-280
C5
2.2 nF
250 VAC
L2
D7 Ferrite Bead
VR1 BYV28-200
P6KE150A T1 3.5 × 7.6 mm +12 V, 1 A
NC 8
C10 C11 J3
D1 D2 R2 1000 µF 100 µF
1N4007 1N4007 100 Ω 1 6 25 V 25 V J4
F1
J1 3.15 A C4 RTN
C1 C2 R1
6.8 µF 22 µF 1 kΩ 10 nF
1 kV 3 R7
400 V 400 V
85-265 RV1 4 20 Ω
VAC 275 VAC
D5
1N4007GP 2 D6
R5* UF4003
J2 3.6 MΩ
D3 D4 5
1N4007 1N4007
L1 VR2
1 mH 1N5255B C6 VR3
28 V 1 µF BZX79-C11
60 V 11 V
R3
47 Ω
*R5 and R8 are optional 1/8 W R6
components 390 Ω
R8* 1/8 W
† 21 kΩ
C7 is configurable to adjust 1% U2
D PC817A
U1 current limit, see circuit EN/UV
description
BP/M
S
S R4
TinySwitch-III C7 † 2 kΩ
U1 100 nF 1/8 W
TNY278P 50 V
PI-4244-021406
Figure 14. TNY278P, 12 V, 1 A Universal Input Power Supply.
Applications Example LED forward drop, current will flow in the optocoupler LED.
The circuit shown in Figure 14 is a low cost, high efficiency,

This will cause the transistor of the optocoupler to sink current.
When this current exceeds the ENABLE pin threshold current 2
flyback power supply designed for 12 V, 1 A output from the next switching cycle is inhibited. When the output voltage
universal input using the TNY278. falls below the feedback threshold, a conduction cycle is allowed
to occur and, by adjusting the number of enabled cycles, output
The supply features undervoltage lockout, primary sensed regulation is maintained. As the load reduces, the number of
output overvoltage latching shutdown protection, high enabled cycles decreases, lowering the effective switching
efficiency (>80%), and very low no-load consumption frequency and scaling switching losses with load. This provides
(<50 mW at 265 VAC). Output regulation is accomplished using almost constant efficiency down to very light loads, ideal for
a simple zener reference and optocoupler feedback. meeting energy efficiency requirements.
The rectified and filtered input voltage is applied to the primary As the TinySwitch-III devices are completely self-powered,
winding of T1. The other side of the transformer primary is there is no requirement for an auxiliary or bias winding on the
driven by the integrated MOSFET in U1. Diode D5, C2, R1, transformer. However by adding a bias winding, the output
R2, and VR1 comprise the clamp circuit, limiting the leakage overvoltage protection feature can be configured, protecting
inductance turn off voltage spike on the DRAIN pin to a safe the load against open feedback loop faults.
value. The use of a combination a Zener clamp and parallel
RC optimizes both EMI and energy efficiency. Resistor R2 When an overvoltage condition occurs, such that bias voltage
allows the use of a slow recovery, low cost, rectifier diode by exceeds the sum of VR2 and the BYPASS/MULTIFUNCTION
limiting the reverse current through D5. The selection of a (BP/M) pin voltage (28 V+5.85 V), current begins to flow into the
slow diode also improves efficiency and conducted EMI but BP/M pin. When this current exceeds ISD the internal latching
should be a glass passivated type, with a specified recovery shutdown circuit in TinySwitch-III is activated. This condition
time of ≤2 µs. is reset when the BP/M pin voltage drops below 4.9 V after
removal of the AC input. In the example shown, on opening
The output voltage is regulated by the Zener diode VR3. When the loop, the OVP trips at an output of 17 V.
the output voltage exceeds the sum of the Zener and optocoupler
2-149
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TNY274-280
For lower no-load input power consumption, the bias winding Key Application Considerations
may also be used to supply the TinySwitch-III device. Resistor
R8 feeds current into the BP/M pin, inhibiting the internal high- TinySwitch-lll Design Considerations
voltage current source that normally maintains the BP/M pin
capacitor voltage (C7) during the internal MOSFET off time. Output Power Table
This reduces the no-load consumption of this design from The data sheet output power table (Table 1) represents the
140 mW to 40 mW at 265 VAC. minimum practical continuous output power level that can be
obtained under the following assumed conditions:
Undervoltage lockout is configured by R5 connected between
the DC bus and EN/UV pin of U1. When present, switching 1. The minimum DC input voltage is 100 V or higher for
is inhibited until the current in the EN/UV pin exceeds 25 µA. 85 VAC input, or 220 V or higher for 230 VAC input or
This allows the startup voltage to be programmed within the 115 VAC with a voltage doubler. The value of the input
normal operating input voltage range, preventing glitching of capacitance should be sized to meet these criteria for AC
the output under abnormal low-voltage conditions and also on input designs.
removal of the AC input. 2. Efficiency of 75%.
3. Minimum data sheet value of I2f.
In addition to the simple input pi filter (C1, L1, C2) for 4. Transformer primary inductance tolerance of ±10%.
differential mode EMI, this design makes use of E-Shield™ 5. Reflected output voltage (VOR) of 135 V.
shielding techniques in the transformer to reduce common 6. Voltage only output of 12 V with a fast PN rectifier diode.
mode EMI displacement currents, and R2 and C4 as a damping 7. Continuous conduction mode operation with transient KP*
network to reduce high frequency transformer ringing. These value of 0.25.
techniques, combined with the frequency jitter of TNY278, 8. Increased current limit is selected for peak and open frame
give excellent conducted and radiated EMI performance with power columns and standard current limit for adapter
this design achieving >12 dBµV of margin to EN55022 Class columns.
B conducted EMI limits. 9. The part is board mounted with SOURCE pins soldered to
a sufficient area of copper and/or a heatsink is used to keep
For design flexibility the value of C7 can be selected to pick one the SOURCE pin temperature at or below 110 °C.
of the 3 current limits options in U1. This allows the designer 10. Ambient temperature of 50 °C for open frame designs and
to select the current limit appropriate for the application. 40 °C for sealed adapters.
2 • Standard current limit (ILIMIT) is selected with a 0.1 µF BP/M *Below a value of 1, KP is the ratio of ripple to peak primary
pin capacitor and is the normal choice for typical enclosed current. To prevent reduced power capability due to premature
adapter applications. termination of switching cycles a transient KP limit of ≥0.25
• When a 1 µF BP/M pin capacitor is used, the current is recommended. This prevents the initial current limit (IINIT)
limit is reduced (ILIMITred or ILIMIT-1) offering reduced RMS from being exceeded at MOSFET turn on.
device currents and therefore improved efficiency, but at
the expense of maximum power capability. This is ideal For reference, Table 2 provides the minimum practical power
for thermally challenging designs where dissipation must delivered from each family member at the three selectable current
be minimized. limit values. This assumes open frame operation (not thermally
• When a 10 µF BP/M pin capacitor is used, the current limited) and otherwise the same conditions as listed above.
limit is increased (ILIMITinc or ILIMIT+1), extending the power These numbers are useful to identify the correct current limit
capability for applications requiring higher peak power or to select for a given device and output power requirement.
continuous power where the thermal conditions allow.
Overvoltage Protection
Further flexibility comes from the current limits between adjacent The output overvoltage protection provided by TinySwitch-III
TinySwitch-III family members being compatible. The reduced uses an internal latch that is triggered by a threshold current
current limit of a given device is equal to the standard current of approximately 5.5 mA into the BP/M pin. In addition to an
limit of the next smaller device and the increased current limit is internal filter, the BP/M pin capacitor forms an external filter
equal to the standard current limit of the next larger device. providing noise immunity from inadvertent triggering. For the
bypass capacitor to be effective as a high frequency filter, the
capacitor should be located as close as possible to the SOURCE
and BP/M pins of the device.
2-150
Rev. G 06/06
TNY274-280
OUTPUT POWER TABLE

230 VAC ±15% 85-265 VAC
PRODUCT
ILIMIT-1 ILIMIT ILIMIT+1 ILIMIT-1 ILIMIT ILIMIT+1
TNY274 P or G 9 10.9 9.1 7.1 8.5 7.1
TNY275 P or G 10.8 12 15.1 8.4 9.3 11.8
TNY276 P or G 11.8 15.3 19.4 9.2 11.9 15.1
TNY277 P or G 15.1 19.6 23.7 11.8 15.3 18.5
TNY278 P or G 19.4 24 28 15.1 18.6 21.8
TNY279 P or G 23.7 28.4 32.2 18.5 22 25.2
TNY280 P or G 28 32.7 36.6 21.8 25.4 28.5
Table 2. Minimum Practical Power at Three Selectable Current Limit Levels.
For best performance of the OVP function, it is recommended practically eliminates audible noise. Vacuum impregnation
that a relatively high bias winding voltage is used, in the range of of the transformer should not be used due to the high primary
15 V-30 V. This minimizes the error voltage on the bias winding capacitance and increased losses that result. Higher flux densities
due to leakage inductance and also ensures adequate voltage are possible, however careful evaluation of the audible noise
during no-load operation from which to supply the BP/M pin performance should be made using production transformer
for reduced no-load consumption. samples before approving the design.
Selecting the Zener diode voltage to be approximately 6 V Ceramic capacitors that use dielectrics such as Z5U, when used
above the bias winding voltage (28 V for 22 V bias winding) in clamp circuits, may also generate audio noise. If this is the
gives good OVP performance for most designs, but can be case, try replacing them with a capacitor having a different
adjusted to compensate for variations in leakage inductance. dielectric or construction, for example a film type.
Adding additional filtering can be achieved by inserting a low
value (10 Ω to 47 Ω) resistor in series with the bias winding TinySwitch-lll Layout Considerations
diode and/or the OVP Zener as shown by R7 and R3 in 2
Figure 14. The resistor in series with the OVP Zener also limits Layout
the maximum current into the BP/M pin. See Figure 15 for a recommended circuit board layout for
TinySwitch-III.
Reducing No-load Consumption
As TinySwitch-III is self-powered from the BP/M pin capacitor, Single Point Grounding
there is no need for an auxillary or bias winding to be provided Use a single point ground connection from the input filter capacitor
on the transformer for this purpose. Typical no-load consumption to the area of copper connected to the SOURCE pins.
when self-powered is <150 mW at 265 VAC input. The addition
of a bias winding can reduce this down to <50 mW by supplying Bypass Capacitor (CBP)
the TinySwitch-III from the lower bias voltage and inhibiting the The BP/M pin capacitor should be located as near as possible
internal high-voltage current source. To achieve this, select the to the BP/M and SOURCE pins.
value of the resistor (R8 in Figure 14) to provide the data sheet
DRAIN supply current. In practice, due to the reduction of the EN/UV Pin
bias voltage at low load, start with a value equal to 40% greater Keep traces connected to the EN/UV pin short and, as far
than the data sheet maximum current, and then increase the value as is practical, away from all other traces and nodes above
of the resistor to give the lowest no-load consumption. source potential including, but not limited to, the BYPASS
and DRAIN pins.
Audible Noise
The cycle skipping mode of operation used in TinySwitch-III Primary Loop Area
can generate audio frequency components in the transformer. The area of the primary loop that connects the input filter
To limit this audible noise generation the transformer should capacitor, transformer primary and TinySwitch-III together
be designed such that the peak core flux density is below should be kept as small as possible.
3000 Gauss (300 mT). Following this guideline and using the
2-151
Rev. G 06/06
TNY274-280

heatsinking
Y1-
Capacitor
+ Output Output Filter
Rectifier Capacitor
- PRI T
r
BIAS a SEC
n
s
PRI f
D
S o
r
TinySwitch-III
m
S e
BP/M BIAS r
S
TOP VIEW S
EN/UV CBP
Opto-
coupler - DC +
OUT
PI-4368-042506
Figure 15. Recommended Circuit Board Layout for TinySwitch-III with Undervoltage Lock Out Resistor.
Primary Clamp Circuit Optocoupler

A clamp is used to limit peak voltage on the DRAIN pin at turn Place the optocoupler physically close to the TinySwitch-III
2 off. This can be achieved by using an RCD clamp or a Zener
(~200 V) and diode clamp across the primary winding. In all
to minimizing the primary-side trace lengths. Keep the high
current, high-voltage drain and clamp traces away from the
cases, to minimize EMI, care should be taken to minimize the optocoupler to prevent noise pick up.
circuit path from the clamp components to the transformer and
TinySwitch-III. Output Diode
For best performance, the area of the loop connecting the
Thermal Considerations secondary winding, the output diode and the output filter
The four SOURCE pins are internally connected to the IC lead capacitor, should be minimized. In addition, sufficient copper
frame and provide the main path to remove heat from the device. area should be provided at the anode and cathode terminals
Therefore all the SOURCE pins should be connected to a copper of the diode for heatsinking. A larger area is preferred at the
area underneath the TinySwitch-III to act not only as a single quiet cathode terminal. A large anode area can increase high
point ground, but also as a heatsink. As this area is connected frequency radiated EMI.
to the quiet source node, this area should be maximized for
good heatsinking. Similarly for axial output diodes, maximize PC Board Leakage Currents
the PCB area connected to the cathode. TinySwitch-III is designed to optimize energy efficiency across
the power range and particularly in standby/no-load conditions.
Y-Capacitor Current consumption has therefore been minimized to achieve
The placement of the Y-capacitor should be directly from the this performance. The EN/UV pin undervoltage feature for
primary input filter capacitor positive terminal to the common/ example has a low threshold (~1 µA) to detect whether an
return terminal of the transformer secondary. Such a placement undervoltage resistor is present.
will route high magnitude common mode surge currents away
from the TinySwitch-III device. Note – if an input π (C, L, C) Parasitic leakage currents into the EN/UV pin are normally
EMI filter is used then the inductor in the filter should be placed well below this 1 µA threshold when PC board assembly is in
between the negative terminals of the input filter capacitors. a well controlled production facility. However, high humidity
conditions together with board and/or package contamination,
2-152
Rev. G 06/06
TNY274-280
either from no-clean flux or other contaminants, can reduce the 1. Maximum drain voltage – Verify that VDS does not exceed
surface resistivity enough to allow parasitic currents >1 µA to 650 V at highest input voltage and peak (overload) output
flow into the EN/UV pin. These currents can flow from higher power. The 50 V margin to the 700 V BVDSS specification
voltage exposed solder pads close to the EN/UV pin such as the gives margin for design variation.
BP/M pin solder pad preventing the design from starting up. 2. Maximum drain current – At maximum ambient temperature,
Designs that make use of the undervoltage lockout feature by maximum input voltage and peak output (overload) power,
connecting a resistor from the high-voltage rail to the EN/UV verify drain current waveforms for any signs of transformer
pin are not affected. saturation and excessive leading edge current spikes at
startup. Repeat under steady state conditions and verify that
If the contamination levels in the PC board assembly facility the leading edge current spike event is below ILIMIT(Min) at the
are unknown, the application is open frame or operates in a high end of the tLEB(Min). Under all conditions, the maximum drain
pollution degree environment and the design does not make use current should be below the specified absolute maximum
of the undervoltage lockout feature, then an optional 390 kΩ ratings.
resistor should be added from EN/UV pin to SOURCE pin to 3. Thermal Check – At specified maximum output power,
ensure that the parasitic leakage current into the EN/UV pin minimum input voltage and maximum ambient temperature,
is well below 1 µA. verify that the temperature specifications are not exceeded
for TinySwitch-III, transformer, output diode, and output
Note that typical values for surface insulation resistance (SIR) capacitors. Enough thermal margin should be allowed for
where no-clean flux has been applied according to the suppliersʼ part-to-part variation of the RDS(ON) of TinySwitch-III as
guidelines are >>10 MΩ and do not cause this issue. specified in the data sheet. Under low line, maximum power,
a maximum TinySwitch-III SOURCE pin temperature of
Quick Design Checklist 110 °C is recommended to allow for these variations.
As with any power supply design, all TinySwitch-III designs Design Tools
specifications are not exceeded under worst case conditions. The Up-to-date information on design tools is available at the Power
following minimum set of tests is strongly recommended: Integrations website: www.powerint.com.
2-153
Rev. G 06/06
TNY274-280

DRAIN Voltage ................................................-0.3 V to 700 V Lead Temperature(4) ....................................................... 260 °C
DRAIN Peak Current: TNY274.......................400 (750) mA(2)
TNY275.....................560 (1050) mA(2) Notes:
TNY276.....................720 (1350) mA(2) 1. All voltages referenced to SOURCE, TA = 25 °C.
TNY277.....................880 (1650) mA(2) 2. The higher peak DRAIN current is allowed while the
TNY278...................1040 (1950) mA(2) DRAIN voltage is simultaneously less than 400 V.
TNY279 ................. 1200 (2250) mA(2) 3. Normally limited by internal circuitry.
TNY280 ................. 1360 (2550) mA(2) 4. 1/16 in. from case for 5 seconds.
EN/UV Voltage ................................................... -0.3 V to 9 V 5. Maximum ratings specified may be applied one at a time,
EN/UV Current ........................................................... 100 mA without causing permanent damage to the product.
BP/M Voltage .................................................. ....-0.3 V to 9 V Exposure to Absolute Maximum Rating conditions for
Storage Temperature ......................................-65 °C to 150 °C extended periods of time may affect product reliability.
Operating Junction Temperature(3) .................-40 °C to 150 °C
THERMAL IMPEDANCE
Notes:
Thermal Impedance: P or G Package:
1. Measured on the SOURCE pin close to plastic interface.
(θJA) ........................... 70 °C/W ; 60 °C/W
(2) (3)
2. Soldered to 0.36 sq. in. (232 mm2), 2 oz. (610 g/m2) copper clad.
(θJC) ............................................... 11 °C/W
(1)
Conditions
SOURCE = 0 V; TJ = -40 to 125 °C
See Figure 16
CONTROL FUNCTIONS
2 Output Frequency
fOSC
TJ = 25 °C Average 124 132 140
kHz
in Standard Mode See Figure 4 Peak-Peak Jitter 8
Maximum Duty
DCMAX S1 Open 62 65 %
Cycle
EN/UV Pin Upper
Turnoff Threshold IDIS -150 -115 -90 µA
Current
EN/UV Pin IEN/UV = 25 µA 1.8 2.2 2.6
VEN V
Voltage IEN/UV = -25 µA 0.8 1.2 1.6
EN/UV Current > IDIS (MOSFET Not
IS1 290 µA
Switching) See Note A
TNY274 275 360
TNY275 295 400
DRAIN Supply EN/UV Open TNY276 310 430
Current (MOSFET
IS2 TNY277 365 460 µA
Switching at fOSC)
See Note B TNY278 445 540
TNY279 510 640
TNY280 630 760
2-154
Rev. G 06/06
TNY274-280
Conditions
SOURCE = 0 V; TJ = -40 to 125 °C
See Figure 16
TNY274 -6 -3.8 -1.8
VBP/M = 0 V,
ICH1 TJ = 25 °C TNY275-279 -8.3 -5.4 -2.5
See Note C, D
BP/M Pin Charge TNY280 -9.7 -6.8 -3.9
mA
Current TNY274 -4.1 -2.3 -1
VBP/M = 4 V,
ICH2 TJ = 25 °C TNY275-279 -5 -3.5 -1.5
See Note C, D
TNY280 -6.6 -4.6 -2.1
BP/M Pin Voltage VBP/M See Note C 5.6 5.85 6.15 V
BP/M Pin Voltage

VBP/MH 0.80 0.95 1.20 V
Hysteresis
BP/M Pin Shunt
VSHUNT IBP = 2 mA 6.0 6.4 6.7 V
Voltage
EN/UV Pin Line
Undervoltage ILUV TJ = 25 °C 22.5 25 27.5 µA
Threshold
CIRCUIT PROTECTION
di/dt = 50 mA/µs TNY274P 233 250 267
TJ = 25 °C 2
See Note E TNY274G 233 250 273
di/dt = 55 mA/µs TNY275P 256 275 294
TJ = 25 °C
di/dt = 70 mA/µs TNY276P 326 350 374
TJ = 25 °C
Standard Current See Note E TNY276G 326 350 382
Limit (BP/M di/dt = 90 mA/µs TNY277P 419 450 481
Capacitor = ILIMIT TJ = 25 °C mA
0.1 µF)
See Note D di/dt = 110 mA/µs TNY278P 512 550 588
TJ = 25 °C
di/dt = 130 mA/µs TNY279P 605 650 695
TJ = 25 °C
di/dt = 150 mA/µs TNY280P 698 750 802
TJ = 25 °C
2-155
Rev. G 06/06
TNY274-280
Conditions
SOURCE = 0 V; TJ = -40 to 125 °C
See Figure 16
di/dt = 50 mA/µs TNY274P 196 210 233
TJ = 25 °C
di/dt = 55 mA/µs TNY275P 233 250 277
TJ = 25 °C
di/dt = 70 mA/µs TNY276P 256 275 305
TJ = 25 °C
See Notes E TNY276G 256 275 311
Reduced Current
di/dt = 90 mA/µs TNY277P 326 350 388
Limit (BP/M
ILIMITred TJ = 25 °C mA
Capacitor = 1 µF) See Notes E TNY277G 326 350 396
See Note D
di/dt = 110 mA/µs TNY278P 419 450 499
TJ = 25 °C
di/dt = 130 mA/µs TNY279P 512 550 610
TJ = 25 °C
di/dt = 150 mA/µs TNY280P 605 650 721
TJ = 25 °C
2 di/dt = 50 mA/µs TNY274P 196 210 233
TJ = 25 °C
See Notes E, F TNY274G 196 210 237
di/dt = 55 mA/µs TNY275P 326 350 388
TJ = 25 °C
di/dt = 70 mA/µs TNY276P 419 450 499
TJ = 25 °C
Increased Current
di/dt = 90 mA/µs TNY277P 512 550 610
Limit (BP/M
ILIMITinc TJ = 25 °C mA
Capacitor = 10 µF) See Notes E TNY277G 512 550 622
See Note D
di/dt = 110 mA/µs TNY278P 605 650 721
TJ = 25 °C
di/dt = 130 mA/µs TNY279P 698 750 833
TJ = 25 °C
di/dt = 150 mA/µs TNY280P 791 850 943
TJ = 25 °C
2-156
Rev. G 06/06
TNY274-280
Conditions
SOURCE = 0 V; TJ = -40 to 125 °C
See Figure 16
0.9 × 1.12 ×
Standard Current TNY274-280P I2f
I2f I2f
Limit, I2f = ILIMIT(TYP)2
× fOSC(TYP) 0.9 × 1.16 ×
TNY274-280G I2f
I2f I2f
Reduced Current 0.9 × 1.16 ×
TNY274-280P I2f
Limit,I2f = I2f I2f
Power Coefficient I2f
ILIMITred(TYP)2
A2Hz
0.9 × 1.20 ×
× fOSC(TYP) TNY274-280G If
2
I2f I2f
0.9 × 1.16 ×
Increased Current TNY274-280P I2f
I2f I2f
Limit, I2f =
ILIMITinc(TYP)2 × fOSC(TYP) 0.9 × 1.20 ×
TNY274-280G I2f
I2f I2f
See Figure 19 0.75 ×
Initial Current Limit IINIT
TJ = 25 °C, See Note G ILIMIT(MIN) mA
tLEB 170 215 ns
Blanking Time See Note G
Current Limit TJ = 25 °C
tILD 150 ns
Delay See Note G, H
Thermal Shut-
TSD 135 142 150 °C 2
down Temperature
Thermal Shut-
TSDH 75 °C
down Hysteresis
BP/M Pin Shut-
down Threshold ISD 4 6.5 9 mA
Current
BP/M Pin Power

Up Reset Thresh- VBP/M(RESET) 1.6 2.6 3.6 V
old Voltage
OUTPUT
TNY274 TJ = 25 °C 28 32
ID = 25 mA TJ = 100 °C 42 48
ON-State TNY275 TJ = 25 °C 19 22
RDS(ON) Ω
Resistance ID = 28 mA TJ = 100 °C 29 33
TNY276 TJ = 25 °C 14 16
ID = 35 mA TJ = 100 °C 21 24
2-157
Rev. G 06/06
TNY274-280
Conditions
SOURCE = 0 V; TJ = -40 to 125 °C
See Figure 16
OUTPUT (cont.)
TNY277 TJ = 25 °C 7.8 9.0
ID = 45 mA TJ = 100 °C 11.7 13.5
TNY278 TJ = 25 °C 5.2 6.0

ID = 55 mA TJ = 100 °C 7.8 9.0
ON-State
RDS(ON) Ω
Resistance TNY279 TJ = 25 °C 3.9 4.5
ID = 65 mA TJ = 100 °C 5.8 6.7
TNY280 TJ = 25 °C 2.6 3.0

ID = 75 mA TJ = 100 °C 3.9 4.5
VBP/M = 6.2 V TNY274-276 50
VEN/UV = 0 V
IDSS1 VDS = 560 V TNY277-278 100 µA
OFF-State Drain TJ = 125 °C
See Note I TNY279-280 200
Leakage Current
VDS = 375 V,
VBP/M = 6.2 V
IDSS2 TJ = 50 °C 15
VEN/UV = 0 V See Note G, I
Breakdown VBP = 6.2 V, VEN/UV = 0 V,

BVDSS 700 V
2 Voltage See Note J, TJ = 25 °C
DRAIN Supply
50 V
Voltage
Auto-Restart TJ = 25 °C
tAR 64 ms
ON-Time at fOSC See Note K
Auto-Restart
DCAR TJ = 25 °C 3 %
Duty Cycle
2-158
Rev. G 06/06
TNY274-280
NOTES:
A. IS1 is an accurate estimate of device controller current consumption at no-load, since operating frequency is so
low under these conditions. Total device consumption at no-load is the sum of IS1 and IDSS2.
B Since the output MOSFET is switching, it is difficult to isolate the switching current from the supply current at the
DRAIN. An alternative is to measure the BP/M pin current at 6.1 V.
C. BP/M pin is not intended for sourcing supply current to external circuitry.
D. To ensure correct current limit it is recommended that nominal 0.1 µF / 1 µF / 10 µF capacitors are used. In
addition, the BP/M capacitor value tolerance should be equal or better than indicated below across the ambient
temperature range of the target application. The minimum and maximum capacitor values are guaranteed by
characterization.
Tolerance Relative to Nominal

Nominal BP/M Capacitor Value
Pin Cap Value
Min MAX
0.1 µF -60% +100%
1 µF -50% +100%
10 µF -50% NA
F. TNY274 does not set an increased current limit value, but with a 10 µF BP/M pin capacitor the current limit is the
same as with a 1 µF BP/M pin capacitor (reduced current limit value).
H. This parameter is derived from the change in current limit measured at 1X and 4X of the di/dt shown in the ILIMIT 2
specification.
I. IDSS1 is the worst case OFF state leakage specification at 80% of BVDSS and maximum operating junction
temperature. IDSS2 is a typical specification under worst case application conditions (rectified 265 VAC) for no-load
consumption calculations.
J. Breakdown voltage may be checked against minimum BVDSS specification by ramping the DRAIN pin voltage up
K. Auto-restart on time has the same temperature characteristics as the oscillator (inversely proportional to
frequency).
2-159
Rev. G 06/06
TNY274-280
470 Ω
5W S2
470 Ω
S D
S1
S
2 MΩ
S BP/M 50 V
EN/UV 10 V
S
150 V
0.1 µF
PI-4079-080905
Figure 16. General Test Circuit.
DCMAX
(internal signal)
tP
EN/UV
tEN/UV
VDRAIN
2 tP =
1
fOSC
PI-2364-012699
PI-4279-013006
0.8
Figure 19. Current Limit Envelope.
2-160
Rev. G 06/06
TNY274-280

1.1 1.2
PI-4280-012306
PI-2213-012301
1.0
Breakdown Voltage
Output Frequency
0.8
1.0 0.6
0.4
0.2
0.9 0
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125
1.2 1.4
PI-4081-082305
PI-4102-010906
Normalized Current Limit 1.2

1
Standard Current Limit
1.0
0.8
0.8 Normalized
0.6 di/dt = 1
0.6 TNY274 50 mA/µs
TNY275 55 mA/µs Note: For the
0.4
0.4
TNY276
TNY277
70 mA/µs
90 mA/µs
normalized current
limit value, use the
typical current limit
2
0.2 TNY278 110 mA/µs
0.2 specified for the
TNY279 130 mA/µs appropriate BP/M
TNY280 150 mA/µs capacitor.
0 0
-50 0 50 100 150 1 2 3 4
Figure 22. Standard Current Limit vs. Temperature. Figure 23. Current Limit vs. di/dt.
300 1000
PI-4083-082305
PI-4082-082305
Scaling Factors:
TNY274 1.0
250
TNY275 1.5
Drain Current (mA)
TNY276 2.0
200 TNY277 3.5 100
TNY278 5.5 Scaling Factors:
TNY279 7.3 TNY274 1.0
150 TNY280 11 TNY275 1.5
TNY276 2.0
TNY277 3.5
100 10 TNY278 5.5
TNY279 7.3
TCASE=25 °C TNY280 11
50 TCASE=100 °C
0 1
0 2 4 6 8 10 0 100 200 300 400 500 600
DRAIN Voltage (V) Drain Voltage (V)
Figure 24. Output Characteristic. Figure 25. COSS vs. Drain Voltage.
2-161
Rev. G 06/06
TNY274-280

50
PI-4084-082305
1.2
PI-4281-012306
Scaling Factors:
TNY274 1.0
40 1.0
TNY275 1.5
TNY276 2.0
TNY277 3.5
Power (mW)
0.8
30 TNY278 5.5
TNY279 7.3
TNY280 11 0.6
20
0.4
10 0.2
0 0
0 200 400 600 -50 -25 0 25 50 75 100 125
DRAIN Voltage (V) Junction Temperature (°C)
Figure 26. Drain Capacitance Power. Figure 27. Undervoltage Threshold vs. Temperature.

TinySwitch Product Family
Series Number
Package Identifier
G Plastic Surface Mount SMD-8C
P Plastic DIP-8C
Lead Finish
2 N Pure Matte Tin (Pb-Free)
TNY 278 G N - TL TL Tape & Reel, 1000 pcs min./mult., G Package only
Revision Notes Date

D Release final data sheet. 1/06
E Corrected figure numbers and references. 2/06
F Seperated current limit and power coefficient values for G package and updated Figure 15. Added 4/06
EN/UV and PC board leakage currents in Key Applications Considerations section.
G Updated line undervoltage current threshold to 2 µA. 6/06
2-162
Rev. G 06/06
TOP242-250
TOP242-250
®
TOPSwitch-GX Family
Extended Power, Design Flexible,
®
EcoSmart , Integrated Off-Line Switcher
Product Highlights +
AC DC
Lower System Cost, High Design Flexibility IN OUT
-
• Extended power range for higher power applications
• No heatsink required up to 34 W using P/G packages
• Features eliminate or reduce cost of external components
D L
• Fully integrated soft-start for minimum stress/overshoot
CONTROL
• Externally programmable accurate current limit C
TOPSwitch-GX
• Wider duty cycle for more power, smaller input capacitor
• Separate line-sense and current limit pins on Y/R/F packages S X F
• Line undervoltage (UV) detection: no turn off glitches
• Line overvoltage (OV) shutdown extends line surge limit
PI-2632-060200
• Line feed-forward with maximum duty cycle (DCMAX)
reduction rejects line ripple and limits DCMAX at high line Figure 1. Typical Flyback Application.
• Frequency jittering reduces EMI and EMI filtering costs
OUTPUT POWER TABLE
• Regulates to zero load without dummy loading
• 132 kHz frequency reduces transformer/power supply size 230 VAC ±15%4 85-265 VAC
• Half frequency option in Y/R/F packages for video applications PRODUCT3 Open Open
• Hysteretic thermal shutdown for automatic fault recovery Adapter1 Adapter1
Frame2 Frame2
• Large thermal hysteresis prevents PC board overheating TOP242 P or G 9 W 15 W 6.5 W 10 W
EcoSmart – Energy Efficient TOP242 R 15 W 22 W 11 W 14 W
• Extremely low consumption in remote off mode TOP242 Y or F 10 W 22 W 7W 14 W
TOP243 P or G 13 W 25 W 9W 15 W
(80 mW at 110 VAC, 160 mW at 230 VAC)
• Frequency lowered with load for high standby efficiency TOP243 R 29 W 45 W 17 W 23 W 2
• Allows shutdown/wake-up via LAN/input port TOP243 Y or F 20 W 45 W 15 W 30 W
TOP244 P or G 16 W 28 W 11 W 20 W
Description TOP244 R 34 W 50 W 20 W 28 W
TOP244 Y or F 30 W 65 W 20 W 45 W
TOPSwitch-GX uses the same proven topology as TOPSwitch,
cost effectively integrating the high-voltage power MOSFET, TOP245 P or G 19 W 30 W 13 W 22 W
PWM control, fault protection and other control circuitry onto TOP245 R 37 W 57 W 23 W 33 W
a single CMOS chip. Many new functions are integrated to TOP245 Y or F 40 W 85 W 26 W 60 W
reduce system cost and improve design flexibility, performance TOP246 P or G 21 W 34 W 15 W 26 W
and energy efficiency. TOP246 R 40 W 64 W 26 W 38 W
TOP246 Y or F 60 W 125 W 40 W 90 W
Depending on package type, either 1 or 3 additional pins over TOP247 R 42 W 70 W 28 W 43 W
the TOPSwitch standard DRAIN, SOURCE and CONTROL TOP247 Y or F 85 W 165 W 55 W 125 W
terminals allow the following functions: line sensing (OV/UV, TOP248 R 43 W 75 W 30 W 48 W
line feed-forward/DCMAX reduction), accurate externally set TOP248 Y or F 105 W 205 W 70 W 155 W
current limit, remote ON/OFF, synchronization to an external TOP249 R 44 W 79 W 31 W 53 W
lower frequency, and frequency selection (132 kHz/66 kHz). TOP249 Y or F 120 W 250 W 80 W 180 W
TOP250 R 45 W 82 W 32 W 55 W
All package types provide the following transparent features: TOP250 Y or F 135 W 290 W 90 W 210 W
Soft-start, 132 kHz switching frequency (automatically reduced
Table 1. Output Power Table.
at light load), frequency jittering for lower EMI, wider DCMAX,
Notes:
hysteretic thermal shutdown, and larger creepage packages. In 1. Typical continuous power in a non-ventilated enclosed adapter
addition, all critical parameters (i.e. current limit, frequency, measured at 50 °C ambient.
PWM gain) have tighter temperature and absolute tolerances 2. Maximum practical continuous power in an open frame design at
to simplify design and optimize system cost. 50 °C ambient. See Key Applications for detailed conditions.
3. For lead-free package options, see Part Ordering Information.
4. 230 VAC or 100/115 VAC with doubler.
2-163
Rev. O 11/05
TOP242-250
Section List
Functional Block Diagram ................................................................................................................................ 2-165

Pin Functional Description ................................................................................................................................ 2-166
TOPSwitch-GX Family Functional Description ................................................................................................ 2-167
CONTROL (C) Pin Operation........................................................................................................................... 2-168
Oscillator and Switching Frequency ................................................................................................................. 2-168
Pulse Width Modulator and Maximum Duty Cycle ........................................................................................... 2-169
Light Load Frequency Reduction ..................................................................................................................... 2-169
Error Amplifier .................................................................................................................................................. 2-169
On-Chip Current Limit with External Programmability ..................................................................................... 2-169
Line Undervoltage Detection (UV) ................................................................................................................... 2-170
Line Overvoltage Shutdown (OV) .................................................................................................................... 2-170
Line Feed-Forward with DCMAX Reduction ....................................................................................................... 2-170
Remote ON/OFF and Synchronization ................................................................................................................... 2-171
Soft-Start .......................................................................................................................................................... 2-171
Shutdown/Auto-Restart .................................................................................................................................... 2-171
Hysteretic Over-Temperature Protection .......................................................................................................... 2-171
Bandgap Reference ......................................................................................................................................... 2-172
High-Voltage Bias Current Source ................................................................................................................... 2-172
Using Feature Pins .............................................................................................................................................. 2-172
FREQUENCY (F) Pin Operation ...................................................................................................................... 2-172
LINE-SENSE (L) Pin Operation ....................................................................................................................... 2-172
EXTERNAL CURRENT LIMIT (X) Pin Operation ............................................................................................. 2-173
MULTI-FUNCTION (M) Pin Operation ............................................................................................................. 2-173
Typical Uses of FREQUENCY (F) Pin ................................................................................................................. 2-176
2 Typical Uses of LINE-SENSE (L) and EXTERNAL CURRENT LIMIT (X) Pins ................................................. 2-177
Typical Uses of MULTI-FUNCTION (M) Pin ...................................................................................................... 2-179
Application Examples ......................................................................................................................................... 2-182
A High Efficiency, 30 W, Universal Input Power Supply ......................................................................................... 2-182
A High Efficiency, Enclosed, 70 W, Universal Adapter Supply ......................................................................... 2-182
A High Efficiency, 250 W, 250-380 VDC Input Power Supply .......................................................................... 2-184
Multiple Output, 60 W, 185-265 VAC Input Power Supply ............................................................................... 2-185
Processor Controlled Supply Turn ON/OFF..................................................................................................... 2-186
Key Application Considerations ........................................................................................................................ 2-188
TOPSwitch-II vs. TOPSwitch-GX ..................................................................................................................... 2-188
TOPSwitch-FX vs. TOPSwitch-GX .................................................................................................................. 2-190
TOPSwitch-GX Design Considerations .......................................................................................................... 2-190
TOPSwitch-GX Layout Considerations ............................................................................................................ 2-192
Quick Design Checklist .................................................................................................................................... 2-194
Design Tools .................................................................................................................................................... 2-194
Product Specifications and Test Conditions .................................................................................................... 2-195
Typical Performance Characteristics ............................................................................................................... 2-202
Part Ordering Information .................................................................................................................................. 2-208
2-164
Rev. O 11/05
TOP242-250
VC
0
ZC INTERNAL
1 SUPPLY
SHUNT REGULATOR/
ERROR AMPLIFIER +
SOFT START
- 5.8 V
4.8 V -
+ 5.8 V
INTERNAL UV
IFB COMPARATOR
VI (LIMIT)
CURRENT
LIMIT SOFT
ADJUST START -
ON/OFF ÷8
+
VBG + VT SHUTDOWN/
COMPARATOR
EXTERNAL
CURRENT LIMIT (X) HYSTERETIC
STOP LOGIC THERMAL
SHUTDOWN
LINE-SENSE (L) 1V
CONTROLLED
VBG TURN-ON
OV/UV START
LINE DMAX
SENSE DCMAX DCMAX
CLOCK
S Q
HALF SAW - LEADING
FREQ. EDGE
R
FREQUENCY (F) + BLANKING
OSCILLATOR WITH JITTER
PWM
COMPARATOR
LIGHT LOAD
FREQUENCY
RE
REDUCTION
SOURCE (S)
PI-2639-060600
Figure 2a. Functional Block Diagram (Y, R or F Package).
2
VC
0
ZC INTERNAL
1 SUPPLY
SHUNT REGULATOR/
ERROR AMPLIFIER +
SOFT START
- 5.8 V
4.8 V -
+ 5.8 V
INTERNAL UV
IFB COMPARATOR
VI (LIMIT)
CURRENT
LIMIT SOFT
ADJUST START -
ON/OFF ÷8
+
SHUTDOWN/
VBG + VT COMPARATOR
STOP LOGIC HYSTERETIC

MULTI-
FUNCTION (M) THERMAL
SHUTDOWN
VBG CONTROLLED
TURN-ON
OV/UV START
LINE DMAX
SENSE DCMAX DCMAX
CLOCK
S Q
SAW - LEADING
R EDGE
+ BLANKING
OSCILLATOR WITH JITTER
PWM
COMPARATOR
LIGHT LOAD
FREQUENCY
RE
REDUCTION
SOURCE (S)
PI-2641-061200
Figure 2b. Functional Block Diagram (P or G Package).
2-165
Rev. O 11/05
TOP242-250
Pin Functional Description FREQUENCY (F) Pin: (Y, R or F package only)

Input pin for selecting switching frequency: 132 kHz if
DRAIN (D) Pin: connected to SOURCE pin and 66 kHz if connected to
High-voltage power MOSFET drain output. The internal CONTROL pin. The switching frequency is internally set for
startup bias current is drawn from this pin through a switched fixed 132 kHz operation in P and G packages.
high-voltage current source. Internal current limit sense point
for drain current. SOURCE (S) Pin:
CONTROL (C) Pin: return. Primary side control circuit common and reference point.
PI-2629-092203
control. Internal shunt regulator connection to provide internal
VUV = IUV x RLS
bias current during normal operation. It is also used as the +
VOV = IOV x RLS
connection point for the supply bypass and auto-restart/
compensation capacitor. For RLS = 2 MΩ
RLS 2 MΩ
VUV = 100 VDC
VOV = 450 VDC
LINE-SENSE (L) Pin: (Y, R or F package only) DC DCMAX@100 VDC = 78%
Input pin for OV, UV, line feed-forward with DCMAX reduction, Input D L
DCMAX@375 VDC = 38%
remote ON/OFF and synchronization. A connection to SOURCE Voltage CONTROL
C
pin disables all functions on this pin. For RIL = 12 kΩ
S
ILIMIT = 69%
X
EXTERNAL CURRENT LIMIT (X) Pin: (Y, R or F package RIL
See Figure 54b for
only) other resistor values
- 12 kΩ
(RIL) to select different
Input pin for external current limit adjustment, remote ILIMIT values
ON/OFF, and synchronization. A connection to SOURCE pin
disables all functions on this pin. Figure 4. Y/R/F Pkg Line-Sense and Externally Set Current Limit.
MULTI-FUNCTION (M) Pin: (P or G package only)

+
This pin combines the functions of the LINE-SENSE (L) and
VUV = IUV x RLS
EXTERNAL CURRENT LIMIT (X) pins of the Y package VOV = IOV x RLS
into one pin. Input pin for OV, UV, line feed-forward with
2 DCMAX reduction, external current limit adjustment, remote RLS 2 MΩ For RLS = 2 MΩ
VUV = 100 VDC
ON/OFF and synchronization. A connection to SOURCE pin DC VOV = 450 VDC
disables all functions on this pin and makes TOPSwitch-GX Input
Voltage DCMAX@100 VDC = 78%
operate in simple three terminal mode (like TOPSwitch-II). D M DCMAX@375 VDC = 38%
CONTROL
C
Y Package (TO-220-7C)
S
Tab Internally 7D -
Connected to 5F
PI-2509-040501
SOURCE Pin 4S
3X Figure 5. P/G Package Line-Sense.
2L
1C
R Package (TO-263-7C) +
For RIL = 12 kΩ
F Package (TO-262-7C) ILIMIT = 69%
P Package (DIP-8B)
G Package (SMD-8B) For RIL = 25 kΩ
ILIMIT = 43%
M 1 8 S DC
See Figures 54b, 55b
Input
and 56b for other resistor
S 2 7 S Voltage values (RIL) to select
D M
different ILIMIT values.
S 3 CONTROL
RIL C
C 4 5 D
123 4 5 7
CL X S F D PI-2724-010802 S
-
Figure 3. Pin Configuration (top view). PI-2517-022604
Figure 6. P/G Package Externally Set Current Limit.
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TOPSwitch-GX Family Functional Auto-restart

ICD1
Description IB
IL = 125 µA
Like TOPSwitch, TOPSwitch-GX is an integrated switched 132
mode power supply chip that converts a current at the control
Frequency (kHz)
input to a duty cycle at the open drain output of a high-voltage IL < IL(DC)
IL = 190 µA
power MOSFET. During normal operation the duty cycle
of the power MOSFET decreases linearly with increasing
CONTROL pin current as shown in Figure 7.
PI-2629-092203
30
In addition to the three terminal TOPSwitch features, such as
the high-voltage startup, the cycle-by-cycle current limiting,
loop compensation circuitry, auto-restart, thermal shutdown, IC (mA)
the TOPSwitch-GX incorporates many additional functions that
reduce system cost, increase power supply performance and
design flexibility. A patented high-voltage CMOS technology Auto-restart
allows both the high-voltage power MOSFET and all the low- ICD1 IB
voltage control circuitry to be cost effectively integrated onto
a single monolithic chip. 78
Slope = PWM Gain
Duty Cycle (%)

Three terminals, FREQUENCY, LINE-SENSE, and
EXTERNAL CURRENT LIMIT (available in Y, R or F IL = 125 µA
package) or one terminal MULTI-FUNCTION (available in P 38
or G package) have been added to implement some of the new IL < IL(DC)
functions. These terminals can be connected to the SOURCE
IL = 190 µA
pin to operate the TOPSwitch-GX in a TOPSwitch-like three 10
terminal mode. However, even in this three terminal mode, the
TOPSwitch-GX offers many new transparent features that do TOP242-5 1.6 2.0 5.2 6.0
not require any external components: TOP246-9 2.2 2.6 5.8 6.6
TOP250 2.4 2.7 IC (mA) 6.5 7.3
1. A fully integrated 10 ms soft-start limits peak currents Note: For P and G packages IL is replaced with IM. 2
and voltages during startup and dramatically reduces or PI-2633-011502
eliminates output overshoot in most applications.

Figure 7. Relationship of Duty Cycle and Frequency to
2. DCMAX of 78% allows smaller input storage capacitor, lower CONTROL Pin Current.
input voltage requirement and/or higher power capability.
3. Frequency reduction at light loads lowers the switching
losses and maintains good cross regulation in multiple output The pin can also be used as a remote ON/OFF and a
supplies. synchronization input.
4. Higher switching frequency of 132 kHz reduces the
transformer size with no noticeable impact on EMI. The EXTERNAL CURRENT LIMIT (X) pin is usually used
5. Frequency jittering reduces EMI. to reduce the current limit externally to a value close to the
6. Hysteretic over-temperature shutdown ensures automatic operating peak current, by connecting the pin to SOURCE
recovery from thermal fault. Large hysteresis prevents through a resistor. This pin can also be used as a remote
circuit board overheating. ON/OFF and a synchronization input in both modes. See
7. Packages with omitted pins and lead forming provide large Table 2 and Figure 11.
drain creepage distance.
8. Tighter absolute tolerances and smaller temperature For the P or G packages the LINE-SENSE and EXTERNAL
variations on switching frequency, current limit and PWM gain. CURRENT LIMIT pin functions are combined on one MULTI-
FUNCTION (M) pin. However, some of the functions become
The LINE-SENSE (L) pin is usually used for line sensing by mutually exclusive as shown in Table 3.
connecting a resistor from this pin to the rectified DC high
voltage bus to implement line overvoltage (OV), undervoltage The FREQUENCY (F) pin in the Y, R or F package sets the
(UV) and line feed-forward with DCMAX reduction. In this switching frequency to the default value of 132 kHz when
mode, the value of the resistor determines the OV/UV thresholds connected to SOURCE pin. A half frequency option of
and the DCMAX is reduced linearly starting from a line voltage 66 kHz can be chosen by connecting this pin to CONTROL pin
above the undervoltage threshold. See Table 2 and Figure 11. instead. Leaving this pin open is not recommended.
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CONTROL (C) Pin Operation voltage of 5.8 V, current in excess of the consumption of the
The CONTROL pin is a low impedance node that is capable chip is shunted to SOURCE through resistor RE as shown in
of receiving a combined supply and feedback current. During Figure 2. This current flowing through RE controls the duty cycle
normal operation, a shunt regulator is used to separate the of the power MOSFET to provide closed loop regulation. The
feedback signal from the supply current. CONTROL pin voltage shunt regulator has a finite low output impedance ZC that sets
VC is the supply voltage for the control circuitry including the the gain of the error amplifier when used in a primary feedback
MOSFET gate driver. An external bypass capacitor closely configuration. The dynamic impedance ZC of the CONTROL
connected between the CONTROL and SOURCE pins is required pin together with the external CONTROL pin capacitance sets
to supply the instantaneous gate drive current. The total amount the dominant pole for the control loop.
of capacitance connected to this pin also sets the auto-restart
timing as well as control loop compensation. When a fault condition such as an open loop or shorted output
prevents the flow of an external current into the CONTROL
When rectified DC high-voltage is applied to the DRAIN pin, the capacitor on the CONTROL pin discharges towards
pin during startup, the MOSFET is initially off, and the 4.8 V. At 4.8 V, auto-restart is activated which turns the output
CONTROL pin capacitor is charged through a switched high- MOSFET off and puts the control circuitry in a low current
voltage current source connected internally between the DRAIN standby mode. The high-voltage current source turns on and
and CONTROL pins. When the CONTROL pin voltage VC charges the external capacitance again. A hysteretic internal
reaches approximately 5.8 V, the control circuitry is activated supply undervoltage comparator keeps VC within a window
and the soft-start begins. The soft-start circuit gradually of typically 4.8 V to 5.8 V by turning the high-voltage current
increases the duty cycle of the MOSFET from zero to the source on and off as shown in Figure 8. The auto-restart
maximum value over approximately 10 ms. If no external circuit has a divide-by-eight counter which prevents the output
feedback/supply current is fed into the CONTROL pin by the MOSFET from turning on again until eight discharge/charge
end of the soft-start, the high-voltage current source is turned cycles have elapsed. This is accomplished by enabling the
off and the CONTROL pin will start discharging in response output MOSFET only when the divide-by-eight counter reaches
to the supply current drawn by the control circuitry. If the full count (S7). The counter effectively limits TOPSwitch-GX
power supply is designed properly, and no fault condition power dissipation by reducing the auto-restart duty cycle
such as open loop or shorted output exists, the feedback loop to typically 4%. Auto-restart mode continues until output
will close, providing external CONTROL pin current, before voltage regulation is again achieved through closure of the
the CONTROL pin voltage has had a chance to discharge to feedback loop.
the lower threshold voltage of approximately 4.8 V (internal
2 supply undervoltage lockout threshold). When the externally Oscillator and Switching Frequency
fed current charges the CONTROL pin to the shunt regulator The internal oscillator linearly charges and discharges an
~
~
~
~
VUV
VLINE
~
~
~
~
~
~
0V
S7 S0 S1 S2 S6 S7 S0 S1 S2 S6 S7 S0 S1 S2 S6 S7 S7 5.8 V
~
~
~
~
~
~
VC 4.8 V
0V
~
~
~
~
VDRAIN
~
~
0V
VOUT
0V
~
~
~
~
~
~
1 2 3 2 4
Note: S0 through S7 are the output states of the auto-restart counter PI-2545-082299
Figure 8. Typical Waveforms for (1) Power Up (2) Normal Operation (3) Auto-Restart (4) Power Down.
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internal capacitance between two voltage levels to create
PI-2550-092499
a sawtooth waveform for the pulse width modulator. This 136 kHz
oscillator sets the pulse width modulator/current limit latch at Switching
Frequency
the beginning of each cycle.
128 kHz
The nominal switching frequency of 132 kHz was chosen to

4 ms
minimize transformer size while keeping the fundamental EMI
frequency below 150 kHz. The FREQUENCY pin (available
VDRAIN
only in Y, R or F package), when shorted to the CONTROL pin,
lowers the switching frequency to 66 kHz (half frequency) which
may be preferable in some cases such as noise sensitive video Time
applications or a high efficiency standby mode. Otherwise, the

FREQUENCY pin should be connected to the SOURCE pin Figure 9. Switching Frequency Jitter (Idealized VDRAIN Waveforms).
for the default 132 kHz.
To further reduce the EMI level, the switching frequency is frequency is also reduced linearly until a minimum frequency
jittered (frequency modulated) by approximately ±4 kHz at is reached at a duty cycle of 0% (refer to Figure 7). The
250 Hz (typical) rate as shown in Figure 9. Figure 46 shows minimum frequency is typically 30 kHz and 15 kHz for
the typical improvement of EMI measurements with frequency 132 kHz and 66 kHz operation, respectively.
jitter.
This feature allows a power supply to operate at lower
Pulse Width Modulator and Maximum Duty Cycle frequency at light loads thus lowering the switching losses
The pulse width modulator implements voltage mode control while maintaining good cross regulation performance and low
by driving the output MOSFET with a duty cycle inversely output ripple.
proportional to the current into the CONTROL pin that
is in excess of the internal supply current of the chip (see Error Amplifier
Figure 7). The excess current is the feedback error signal that The shunt regulator can also perform the function of an error
appears across RE (see Figure 2). This signal is filtered by an RC amplifier in primary side feedback applications. The shunt
network with a typical corner frequency of 7 kHz to reduce the regulator voltage is accurately derived from a temperature-
effect of switching noise in the chip supply current generated compensated bandgap reference. The gain of the error
by the MOSFET gate driver. The filtered error signal is amplifier is set by the CONTROL pin dynamic impedance. 2
compared with the internal oscillator sawtooth waveform to The CONTROL pin clamps external circuit signals to the VC
generate the duty cycle waveform. As the control current voltage level. The CONTROL pin current in excess of the
increases, the duty cycle decreases. A clock signal from the supply current is separated by the shunt regulator and flows
oscillator sets a latch which turns on the output MOSFET. The through RE as a voltage error signal.
pulse width modulator resets the latch, turning off the output
MOSFET. Note that a minimum current must be driven into On-Chip Current Limit with External Programmability
the CONTROL pin before the duty cycle begins to change. The cycle-by-cycle peak drain current limit circuit uses the
output MOSFET ON-resistance as a sense resistor. A current
The maximum duty cycle, DCMAX, is set at a default maximum limit comparator compares the output MOSFET on-state drain
value of 78% (typical). However, by connecting the LINE- to source voltage, VDS(ON) with a threshold voltage. High drain
SENSE or MULTI-FUNCTION pin (depending on the current causes VDS(ON) to exceed the threshold voltage and turns
package) to the rectified DC high-voltage bus through a the output MOSFET off until the start of the next clock cycle.
resistor with appropriate value, the maximum duty cycle can The current limit comparator threshold voltage is temperature
be made to decrease from 78% to 38% (typical) as shown in compensated to minimize the variation of the current limit due
Figure 11 when input line voltage increases (see line feed to temperature related changes in RDS(ON)of the output MOSFET.
forward with DCMAX reduction). The default current limit of TOPSwitch-GX is preset internally.
However, with a resistor connected between EXTERNAL
Light Load Frequency Reduction CURRENT LIMIT (X) pin (Y, R or F package) or MULTI-
The pulse width modulator duty cycle reduces as the load at FUNCTION (M) pin (P or G package) and SOURCE pin,
the power supply output decreases. This reduction in duty current limit can be programmed externally to a lower level
cycle is proportional to the current flowing into the CONTROL between 30% and 100% of the default current limit. Please
pin. As the CONTROL pin current increases, the duty cycle refer to the graphs in the typical performance characteristics
decreases linearly towards a duty cycle of 10%. Below 10% section for the selection of the resistor value. By setting current
duty cycle, to maintain high efficiency at light loads, the limit low, a larger TOPSwitch-GX than necessary for the power
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required can be used to take advantage of the lower RDS(ON) for high-voltage bus sets UV threshold during power up. Once
higher efficiency/smaller heat sinking requirements. With the power supply is successfully turned on, the UV threshold
a second resistor connected between the EXTERNAL is lowered to 40% of the initial UV threshold to allow extended
CURRENT LIMIT (X) pin (Y, R or F package) or MULTI- input voltage operating range (UV low threshold). If the UV
FUNCTION (M) pin (P or G package) and the rectified DC low threshold is reached during operation without the power
high-voltage bus, the current limit is reduced with increasing supply losing regulation, the device will turn off and stay off
line voltage, allowing a true power limiting operation against until UV (high threshold) has been reached again. If the power
line variation to be implemented. When using an RCD clamp, supply loses regulation before reaching the UV low threshold,
this power limiting technique reduces maximum clamp the device will enter auto-restart. At the end of each auto-
voltage at high line. This allows for higher reflected voltage restart cycle (S7), the UV comparator is enabled. If the UV
designs as well as reducing clamp dissipation. high threshold is not exceeded the MOSFET will be disabled
during the next cycle (see Figure 8). The UV feature can
The leading edge blanking circuit inhibits the current limit be disabled independent of the OV feature as shown in
comparator for a short time after the output MOSFET is turned Figures 19 and 23.
on. The leading edge blanking time has been set so that, if a
power supply is designed properly, current spikes caused by Line Overvoltage Shutdown (OV)
primary-side capacitances and secondary-side rectifier reverse The same resistor used for UV also sets an overvoltage threshold
recovery time should not cause premature termination of the which, once exceeded, will force TOPSwitch-GX output into
switching pulse. off-state. The ratio of OV and UV thresholds is preset at 4.5
as can be seen in Figure 11. When the MOSFET is off, the
The current limit is lower for a short period after the leading rectified DC high-voltage surge capability is increased to the
edge blanking time as shown in Figure 52. This is due to voltage rating of the MOSFET (700 V), due to the absence
dynamic characteristics of the MOSFET. To avoid triggering of the reflected voltage and leakage spikes on the drain. A
the current limit in normal operation, the drain current waveform small amount of hysteresis is provided on the OV threshold to
should stay within the envelope shown. prevent noise triggering. The OV feature can be disabled
independent of the UV feature as shown in Figures 18 and 32.
Line Undervoltage Detection (UV)
At power up, UV keeps TOPSwitch-GX off until the input line Line Feed-Forward with DCMAX Reduction
voltage reaches the undervoltage threshold. At power down, The same resistor used for UV and OV also implements line
UV prevents auto-restart attempts after the output goes out voltage feed-forward, which minimizes output line ripple and
2 of regulation. This eliminates power down glitches caused reduces power supply output sensitivity to line transients.
by slow discharge of the large input storage capacitor present This feed-forward operation is illustrated in Figure 7 by the
in applications such as standby supplies. A single resistor different values of IL (Y, R or F package) or IM (P or G package).
connected from the LINE-SENSE pin (Y, R or F package) or Note that for the same CONTROL pin current, higher line
MULTI-FUNCTION pin (P or G package) to the rectified DC voltage results in smaller operating duty cycle. As an added
Oscillator
(SAW)
DMAX
Enable from
X, L or M Pin (STOP)
Time
PI-2637-060600
Figure 10. Synchronization Timing Diagram.
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feature, the maximum duty cycle DCMAX is also reduced cycles between 4.8 V and 5.8 V (see CONTROL pin operation
from 78% (typical) at a voltage slightly higher than the UV section above) and runs entirely off the high-voltage DC input,
threshold to 30% (typical) at the OV threshold (see Figure 11). but with very low power consumption (160 mW typical at
Limiting DCMAX at higher line voltages helps prevent transformer 230 VAC with M or X pins open). When the TOPSwitch-GX
saturation due to large load transients in TOP248, TOP249 and is remotely turned on after entering this mode, it will initiate
TOP250 forward converter applications. DCMAX of 38% at a normal startup sequence with soft-start the next time the
high line was chosen to ensure that the power capability of the CONTROL pin reaches 5.8 V. In the worst case, the delay from
TOPSwitch-GX is not restricted by this feature under normal remote on to startup can be equal to the full discharge/charge
operation. cycle time of the CONTROL pin, which is approximately
125 ms for a 47 µF CONTROL pin capacitor. This
Remote ON/OFF and Synchronization reduced consumption remote off mode can eliminate
TOPSwitch-GX can be turned on or off by controlling the expensive and unreliable in-line mechanical switches. It also
current into the LINE-SENSE pin or out from the EXTERNAL allows for microprocessor controlled turn-on and turn-off
CURRENT LIMIT pin (Y, R or F package) and into or out sequences that may be required in certain applications such as
from the MULTI-FUNCTION pin (P or G package) (see inkjet and laser printers.
Figure 11). In addition, the LINE-SENSE pin has a 1 V
threshold comparator connected at its input. This voltage Soft Start
threshold can also be used to perform remote ON/OFF Two on-chip soft-start functions are activated at startup with a
control. This allows easy implementation of remote duration of 10 ms (typical). Maximum duty cycle starts from
ON/OFF control of TOPSwitch-GX in several different ways. 0% and linearly increases to the default maximum of 78% at
A transistor or an optocoupler output connected between the end of the 10 ms duration and the current limit starts from
the EXTERNAL CURRENT LIMIT or LINE-SENSE pins about 85% and linearly increases to 100% at the end of the
(Y, R or F package) or the MULTI-FUNCTION pin (P or G 10 ms duration. In addition to startup, soft-start is also
package) and the SOURCE pin implements this function with activated at each restart attempt during auto-restart and when
“active-on” (Figures 22, 29 and 36) while a transistor or an restarting after being in hysteretic regulation of CONTROL
optocoupler output connected between the LINE-SENSE pin pin voltage (VC), due to remote OFF or thermal shutdown
(Y, R or F package) or the MULTI-FUNCTION (P or G package) conditions. This effectively minimizes current and voltage
pin and the CONTROL pin implements the function with stresses on the output MOSFET, the clamp circuit and the
“active-off” (Figures 23 and 37). output rectifier during startup. This feature also helps
minimize output overshoot and prevents saturation of the
When a signal is received at the LINE-SENSE pin or the
EXTERNAL CURRENT LIMIT pin (Y, R or F package) or
transformer during startup. 2
the MULTI-FUNCTION pin (P or G package) to disable the Shutdown/Auto-Restart
output through any of the pin functions such as OV, UV and To minimize TOPSwitch-GX power dissipation under fault
remote ON/OFF, TOPSwitch-GX always completes its current conditions, the shutdown/auto-restart circuit turns the power
switching cycle, as illustrated in Figure 10, before the output is supply on and off at an auto-restart duty cycle of typically 4%
forced off. The internal oscillator is stopped slightly before the if an out of regulation condition persists. Loss of regulation
end of the current cycle and stays there as long as the disable interrupts the external current into the CONTROL pin. VC
signal exists. When the signal at the above pins changes state regulation changes from shunt mode to the hysteretic auto-
from disable to enable, the internal oscillator starts the next restart mode as described in CONTROL pin operation section.
switching cycle. This approach allows the use of these pins When the fault condition is removed, the power supply output
to synchronize TOPSwitch-GX to any external signal with a becomes regulated, VC regulation returns to shunt mode, and
frequency between its internal switching frequency and 20 kHz. normal operation of the power supply resumes.
As seen above, the remote ON/OFF feature allows the Hysteretic Over-Temperature Protection
TOPSwitch-GX to be turned on and off instantly, on a cycle- Temperature protection is provided by a precision analog
by-cycle basis, with very little delay. However, remote circuit that turns the output MOSFET off when the junction
ON/OFF can also be used as a standby or power switch to temperature exceeds the thermal shutdown temperature
turn off the TOPSwitch-GX and keep it in a very low power (140 °C typical). When the junction temperature cools to
consumption state for indefinitely long periods. If the below the hysteretic temperature, normal operation resumes
TOPSwitch-GX is held in remote off state for long enough providing automatic recovery. A large hysteresis of 70 °C
time to allow the CONTROL pin to discharge to the internal (typical) is provided to prevent overheating of the PC board due
supply undervoltage threshold of 4.8 V (approximately 32 ms to a continuous fault condition. VC is regulated in hysteretic mode
for a 47 µF CONTROL pin capacitance), the CONTROL pin and a 4.8 V to 5.8 V (typical) sawtooth waveform is present on
goes into the hysteretic mode of regulation. In this mode, the the CONTROL pin while in thermal shutdown.
CONTROL pin goes through alternate charge and discharge
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Bandgap Reference may be used to lower the switching frequency from 132 kHz in
All critical TOPSwitch-GX internal voltages are derived from normal operation to 66 kHz in standby mode for very low
a temperature-compensated bandgap reference. This reference standby power consumption.
is also used to generate a temperature-compensated current
reference, which is trimmed to accurately set the switching LINE-SENSE (L) Pin Operation (Y, R and F Packages)
frequency, MOSFET gate drive current, current limit, and the When current is fed into the LINE-SENSE pin, it works as
line OV/UV thresholds. TOPSwitch-GX has improved circuitry a voltage source of approximately 2.6 V up to a maximum
to maintain all of the above critical parameters within very tight current of +400 µA (typical). At +400 µA, this pin turns into
absolute and temperature tolerances. a constant current sink. Refer to Figure 12a. In addition, a
comparator with a threshold of 1 V is connected at the pin and
High-Voltage Bias Current Source is used to detect when the pin is shorted to the SOURCE pin.
This current source biases TOPSwitch-GX from the DRAIN
pin and charges the CONTROL pin external capacitance There are a total of four functions available through the use of
during startup or hysteretic operation. Hysteretic operation the LINE-SENSE pin: OV, UV, line feed-forward with DCMAX
occurs during auto-restart, remote OFF and over-temperature reduction, and remote ON/OFF. Connecting the LINE-SENSE
shutdown. In this mode of operation, the current source pin to the SOURCE pin disables all four functions. The LINE-
is switched on and off with an effective duty cycle of SENSE pin is typically used for line sensing by connecting a
approximately 35%. This duty cycle is determined by the resistor from this pin to the rectified DC high-voltage bus to
ratio of CONTROL pin charge (IC) and discharge currents implement OV, UV and DCMAX reduction with line voltage. In
(ICD1 and ICD2). This current source is turned off during normal this mode, the value of the resistor determines the line OV/UV
operation when the output MOSFET is switching. The effect of thresholds, and the DCMAX is reduced linearly with rectified DC
the current source switching will be seen on the DRAIN voltage high-voltage starting from just above the UV threshold. The
waveform as small disturbances and is normal. pin can also be used as a remote ON/OFF and a synchronization
input. Refer to Table 2 for possible combinations of the functions
with example circuits shown in Figure 16 through Figure 40. A
Using Feature Pins description of specific functions in terms of the LINE-SENSE
pin I/V characteristic is shown in Figure 11 (right hand side).
FREQUENCY (F) Pin Operation
The horizontal axis represents LINE-SENSE pin current with
The FREQUENCY pin is a digital input pin available in the
positive polarity indicating currents flowing into the pin. The
Y, R or F package only. Shorting the FREQUENCY pin to
meaning of the vertical axes varies with functions. For those
2 SOURCE pin selects the nominal switching frequency of
132 kHz (Figure 13), which is suited for most applications.
that control the ON/OFF states of the output such as UV, OV
and remote ON/OFF, the vertical axis represents the enable/
For other cases that may benefit from lower switching
disable states of the output. UV triggers at IUV (+50 µA typical
frequency such as noise sensitive video applications, a
with 30 µA hysteresis) and OV triggers at IOV (+225 µA
66 kHz switching frequency (half frequency) can be selected by
typical with 8 µA hysteresis). Between the UV and OV
shorting the FREQUENCY pin to the CONTROL pin
thresholds, the output is enabled. For line feed-forward with
(Figure 14). In addition, an example circuit shown in Figure 15
LINE-SENSE AND EXTERNAL CURRENT LIMIT PIN TABLE*

Figure Number 16 17 18 19 20 21 22 23 24 25 26 27 28 29
▼

Undervoltage ✓ ✓ ✓ ✓ ✓
Overvoltage ✓ ✓ ✓ ✓ ✓
Line Feed-Forward (DCMAX) ✓ ✓ ✓ ✓
External Current Limit ✓ ✓ ✓ ✓ ✓ ✓
Remote ON/OFF ✓ ✓ ✓ ✓ ✓ ✓ ✓
*This table is only a partial list of many LINE-SENSE and EXTERNAL CURRENT LIMIT pin configurations that are possible.
Table 2. Typical LINE-SENSE and EXTERNAL CURRENT LIMIT Pin Configurations.
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DCMAX reduction, the vertical axis represents the magnitude of for P and G packages. The comparator with a 1 V threshold
the DCMAX. Line feed-forward with DCMAX reduction lowers at the LINE-SENSE pin is removed in this case as shown in
maximum duty cycle from 78% at IL(DC) (+60 µA typical) to Figure 2b. All of the other functions are kept intact. However,
38% at IOV (+225 µA). since some of the functions require opposite polarity of input
current (MULTI-FUNCTION pin), they are mutually exclusive.
EXTERNAL CURRENT LIMIT (X) Pin Operation For example, line sensing features cannot be used simultaneously
(Y, R and F Packages) with external current limit setting. When current is fed into
When current is drawn out of the EXTERNAL CURRENT the MULTI-FUNCTION pin, it works as a voltage source of
LIMIT pin, it works as a voltage source of approximately approximately 2.6 V up to a maximum current of +400 µA
1.3 V up to a maximum current of -240 µA (typical). At (typical). At +400 µA, this pin turns into a constant current
-240 µA, it turns into a constant current source (refer to sink. When current is drawn out of the MULTI-FUNCTION
Figure 12a). pin, it works as a voltage source of approximately 1.3 V up to
a maximum current of -240 µA (typical). At -240 µA, it turns
There are two functions available through the use of the into a constant current source. Refer to Figure 12b.
EXTERNAL CURRENT LIMIT pin: external current limit
and remote ON/OFF. Connecting the EXTERNAL CURRENT There are a total of five functions available through the use
LIMIT pin to the SOURCE pin disables the two functions. In of the MULTI-FUNCTION pin: OV, UV, line feed-forward
high efficiency applications, this pin can be used to reduce the with DCMAX reduction, external current limit and remote
current limit externally to a value close to the operating peak ON/OFF. A short circuit between the MULTI-FUNCTION
current by connecting the pin to the SOURCE pin through pin and SOURCE pin disables all five functions and forces
a resistor. The pin can also be used for remote ON/OFF. TOPSwitch-GX to operate in a simple three terminal mode
Table 2 shows several possible combinations using this pin. See like TOPSwitch-II. The MULTI-FUNCTION pin is typically
Figure 11 for a description of the functions where the horizontal used for line sensing by connecting a resistor from this pin to
axis (left hand side) represents the EXTERNAL CURRENT the rectified DC high-voltage bus to implement OV, UV and
LIMIT pin current. The meaning of the vertical axes varies DCMAX reduction with line voltage. In this mode, the value
with function. For those that control the ON/OFF states of the of the resistor determines the line OV/UV thresholds, and the
output such as remote ON/OFF, the vertical axis represents the DCMAX is reduced linearly with increasing rectified DC high-
enable/disable states of the output. For external current limit, voltage starting from just above the UV threshold. External
the vertical axis represents the magnitude of the ILIMIT. Please current limit programming is implemented by connecting the
see graphs in the Typical Performance Characteristics section MULTI-FUNCTION pin to the SOURCE pin through a resistor.
for the current limit programming range and the selection of However, this function is not necessary in most applications 2
appropriate resistor value. since the internal current limit of the P and G package devices
has been reduced, compared to the Y, R and F package
MULTI-FUNCTION (M) Pin Operation (P and G devices, to match the thermal dissipation capability of the P
Packages) and G packages. It is therefore recommended that the MULTI-
The LINE-SENSE and EXTERNAL CURRENT LIMIT pin FUNCTION pin is used for line sensing as described above and
functions are combined to a single MULTI-FUNCTION pin not for external current limit reduction. The same pin can also
MULTI-FUNCTION PIN TABLE*

Figure Number 30 31 32 33 34 35 36 37 38 39 40
▼

Undervoltage ✓ ✓ ✓
Overvoltage ✓ ✓ ✓
Line Feed-Forward (DCMAX) ✓ ✓
External Current Limit ✓ ✓ ✓ ✓
Remote ON/OFF ✓ ✓ ✓ ✓ ✓
*This table is only a partial list of many MULTI-FUNCTION pin configurations that are possible.
Table 3. Typcial MULTI-FUNCTION Pin Configurations.
2-173
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M Pin
X Pin L Pin
IREM(N) IUV IOV

(Enabled)
Output
MOSFET
Switching
(Disabled)
Disabled when supply I

output goes out of
regulation
ILIMIT (Default)
Current
Limit
DCMAX (78.5%)
Maximum
Duty Cycle
I
-22 µA
-27 µA
VBG + VTP
2 Pin Voltage
VBG
I
-250 -200 -150 -100 -50 0 50 100 150 200 250 300 350 400
X and L Pins (Y, R or F Package) and M Pin (P or G Package) Current (µA)
Note: This figure provides idealized functional characteristics with typical performance values. Please refer to the parametric
table and typical performance characteristics sections of the data sheet for measured data.
PI-2636-010802
Figure 11. MULTI-FUNCTION (P or G Package), LINSE-SENSE, and EXTERNAL CURRENT LIMIT (Y, R or F Package) Pin Characteristics.
be used as a remote ON/OFF and a synchronization input in (+50 µA typical) and OV triggers at IOV (+225 µA typical with
both modes. Please refer to Table 3 for possible combinations 30 µA hysteresis). Between the UV and OV thresholds, the
of the functions with example circuits shown in Figure 30 output is enabled. For external current limit and line feed-
through Figure 40. A description of specific functions in terms forward with DCMAX reduction, the vertical axis represents the
of the MULTI-FUNCTION pin I/V characteristic is shown in magnitude of the ILIMIT and DCMAX. Line feed-forward with
Figure 11. The horizontal axis represents MULTI-FUNCTION DCMAX reduction lowers maximum duty cycle from 78% at IM(DC)
pin current with positive polarity indicating currents flowing into (+60 µA typical) to 38% at IOV (+225 µA). External current
the pin. The meaning of the vertical axes varies with functions. limit is available only with negative MULTI-FUNCTION
For those that control the ON/OFF states of the output such pin current. Please see graphs in the Typical Performance
as UV, OV and remote ON/OFF, the vertical axis represents Characteristics section for the current limit programming
the enable/disable states of the output. UV triggers at IUV range and the selection of appropriate resistor value.
2-174
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TOP242-250
Y, R and F Package
CONTROL (C)
TOPSwitch-GX
240 µA

EXTERNAL CURRENT LIMIT (X) VBG + VT
(Voltage Sense)
LINE-SENSE (L) 1V
VBG
Overvoltage, ON/OFF Maximum Duty
Cycle Reduction)
400 µA
PI-2634-022604
Figure 12a. LINE-SENSE (L), and EXTERNAL CURRENT LIMIT (X) Pin Input Simplified Schematic.
P and G Package
CONTROL (C)
TOPSwitch-GX
240 µA
2
VBG + VT
MULTI-FUNCTION (M)
VBG
Overvoltage, Maximum Duty
Cycle Reduction)
.
400 µA
PI-2548-022604
Figure 12b. MULTI-FUNCTION (M) Pin Input Simplified Schematic.
2-175
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TOP242-250
Typical Uses of FREQUENCY (F) PIN
+ +
DC DC
D D
Input Input
C C
S F S F
- -
PI-2654-071700 PI-2655-071700
Figure 13. Full Frequency Operation (132 kHz). Figure 14. Half Frequency Operation (66 kHz).
+
QS can be an optocoupler output.
DC
D
Input
Voltage CONTROL
C
2 S
RHF
F
QS
47 kΩ
STANDBY
20 kΩ 1 nF
-
PI-2656-040501
Figure 15. Half Frequency Standby Mode (For High Standby

Efficiency).
2-176
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TOP242-250
Typical Uses of LINE-SENSE (L) and EXTERNAL CURRENT LIMIT (X) Pins
+ + VUV = IUV x RLS

VOV = IOV x RLS
For RLS = 2 MΩ
CL XS F D RLS 2 MΩ VUV = 100 VDC
VOV = 450 VDC
DC DC
Input Input DCMAX@100 VDC = 78%
Voltage Voltage DCMAX@375 VDC = 38%
D L D L
CONTROL C S D CONTROL
C C
S X F S
- -
PI-2617-050100 PI-2618-081403
Figure 16. Three Terminal Operation (LINE-SENSE and Figure 17. Line-Sensing for Undervoltage, Overvoltage and Line
EXTERNAL CURRENT LIMIT Features Disabled. Feed-Forward.
FREQUENCY Pin Tied to SOURCE or CONTROL Pin).
+ +
2 MΩ VUV = RLS x IUV 2 MΩ VOV = IOV x RLS
For Value Shown For Values Shown

RLS VUV = 100 VDC RLS VOV = 450 VDC
DC DC
Input 22 kΩ Input 30 kΩ
Voltage Voltage 1N4148
2
D M D L
CONTROL CONTROL
C C
6.2 V
S
- S -
PI-2510-040501 PI-2620-040501
Figure 18. Line-Sensing for Undervoltage Only (Overvoltage Figure 19. Linse-Sensing for Overvoltage Only (Undervoltage
Disabled). Disabled). Maximum Duty Cycle Reduced at Low Line
and Further Reduction with Increasing Line Voltage.
+ For RIL = 12 kΩ + ILIMIT = 100% @ 100 VDC

RLS 2.5 MΩ
For RIL = 25 kΩ
ILIMIT = 43%
DC See Figure 54b for DC

D other resistor values D
Input Input
Voltage CONTROL (RIL) Voltage CONTROL
C C
S X S X
RIL RIL
6 kΩ
- -
PI-2623-092303 PI-2624-040501
Figure 20. Externally Set Current Limit. Figure 21. Current Limit Reduction with Line Voltage.
2-177
Rev. O 11/05
TOP242-250
+ + QR can be an
QR can be an optocoupler optocoupler output or
output or can be replaced by can be replaced
a manual switch. by a manual switch.
QR
ON/OFF
47 kΩ RMC
DC DC
D
Input Input 45 kΩ
C
D L
CONTROL
S X C
QR ON/OFF
47 KΩ S
- -
PI-2625-040501 PI-2621-040501
Figure 22. Active-on (Fail Safe) Remove ON/OFF. Figure 23. Active-off Remote ON/OFF.
Maximum Duty Cycle Reduced.
+ QR can be an optocoupler + QR
QR can be an
output or can be replaced optocoupler output
ON/OFF or can be replaced
by a manual switch.
47 kΩ RMC by a manual switch.
For RIL = 12 kΩ
45 kΩ
ILIMIT = 69%
DC DC
D For RIL = 25 kΩ D L
Input Input
Voltage CONTROL ILIMIT = 43% Voltage CONTROL
C C
2 S X S X
RIL
ON/OFF RIL
QR
- 47 kΩ -
PI-2626-040501 PI-2627-040501
Figure 24. Active-on Remote ON/OFF with Figure 25. Active-off Remote ON/OFF with
Externally Set Current Limit. Externally Set Current Limit.
+ QR can be an optocoupler + VUV = IUV x RLS

RLS 2 MΩ output or can be replaced VOV = IOV x RLS
by a manual switch.
DCMAX@100 VDC = 78%
RLS 2 MΩ
QR DCMAX@375 VDC = 38%
For RLS = 2 MΩ
ON/OFF
47 kΩ
QR can be an optocoupler
VUV = 100 VDC DC output or can be replaced
D L
VOV = 450 VDC Input by a manual switch.
DC Voltage CONTROL
C For RIL = 12 kΩ
Input D L
Voltage CONTROL ILIMIT = 69%
C S X
QR
RIL
ON/OFF
S
- - 47 kΩ
PI-2622-040501 PI-2628-040501
Figure 26. Active-off Remote ON/OFF with LINE-SENSE. Figure 27. Active-on Remote ON/OFF with LINE-SENSE
and EXTERNAL CURRENT LIMIT.
2-178
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PI-2629-092203
+ VUV = IUV x RLS + QR can be an optocoupler
VOV = IOV x RLS
output or can be replaced by
For RLS = 2 MΩ a manual switch.
RLS 2 MΩ
VUV = 100 VDC
VOV = 450 VDC
DC DC 300 kΩ
D L DCMAX@100 VDC = 78% D L
Input Input
DCMAX@375 VDC = 38% CONTROL
C C
For RIL = 12 kΩ
S
ILIMIT = 69% S
X
See Figure 54b for QR ON/OFF
RIL
other resistor values 47 kΩ
- 12 kΩ
(RIL) to select different -
ILIMIT values PI-2640-040501
Figure 28. Line-Sensing and Externally Set Current Limit. Figure 29. Active-on Remote ON/OFF.
Typical Uses of MULTI-FUNCTION (M) Pin
+ +
VUV = IUV x RLS
C S S
VOV = IOV x RLS
M
RLS 2 MΩ For RLS = 2 MΩ
D S S VUV = 100 VDC
DC DC VOV = 450 VDC
Input Input
Voltage
D M
C D S
Voltage
D M
DCMAX@100 VDC = 78%
DCMAX@375 VDC = 38%
2
CONTROL CONTROL
C C
S S
- -
PI-2508-081199 PI-2509-040501
Figure 30. Three Terminal Operation Figure 31. Line-Sensing for Undervoltage, Overvoltage
(MULTI-FUNCTION Features Disabled). and Line Feed-Forward.
+ +
2 MΩ VUV = RLS x IUV 2 MΩ
VOV = IOV x RLS
For Value Shown For Values Shown

RLS
RLS VUV = 100 VDC VOV = 450 VDC
DC DC
Input 22 kΩ Input 30 kΩ
1N4148
Voltage Voltage
D M D M
CONTROL CONTROL
C C
6.2 V
S S
- -
PI-2510-040501 PI-2516-040501
Figure 32. Line-Sensing for Undervoltage Only Figure 33. Line-Sensing for Overvoltage Only (Undervoltage
(Overvoltage Disabled). Disabled). Maximum Duty Cycle Reduced at Low Line
and Further Reduction with Increasing Line Voltage.
2-179
Rev. O 11/05
TOP242-250
Typical Uses of MULTI-FUNCTION (M) Pin (cont.)
+ +
For RIL = 12 kΩ
RLS 2.5 MΩ ILIMIT = 63% @ 300 VDC
For RIL = 25 kΩ
ILIMIT = 43%
DC DC
See Figures 54b, 55b
Input Input
and 56b for other resistor
Voltage values (RIL) to select Voltage
D M D M
different ILIMIT values.
CONTROL RIL CONTROL
RIL C 6 kΩ C
S S
- -
PI-2517-022604 PI-2518-040501
Figure 34. Externally Set Current Limit (Not Normally Required- Figure 35. Current Limit Reduction with Line Voltage (Not Normally
See M Pin Operation Description). Required-See M Pin Operation Description).
QR can be an optocoupler output or can be replaced
output or can be replaced by a manual switch.
by a manual switch.
QR
DC DC ON/OFF
Input Input 47 kΩ RMC
Voltage Voltage
45 kΩ
2
D M D M
CONTROL CONTROL
QR C C
ON/OFF
47 kΩ S
- S
-
PI-2519-040501 PI-2522-040501
Figure 36. Active-on (Fail Safe) Remote ON/OFF. Figure 37. Active-off Remote ON/OFF.
Maximum Duty Cycle Reduced.
2-180
Rev. O 11/05
TOP242-250
Typical Uses of MULTI-FUNCTION (M) Pin (cont.)
QR can be an optocoupler output or can be replaced
output or can be replaced by a manual switch.
by a manual switch.
For RIL = 12 kΩ QR
ON/OFF
DC ILIMIT = 69% DC 47 kΩ
Input For RIL = 25 kΩ Input
Voltage Voltage RMC 24 kΩ RMC = 2RIL
RIL D M ILIMIT = 43% D M
CONTROL CONTROL
QR C RIL 12 kΩ C
ON/OFF
47 kΩ S S
- -
PI-2520-040501 PI-2521-040501
Figure 38. Active-on Remote ON/OFF with Externally Set Current Figure 39. Active-off Remote ON/OFF with Externally Set Current
Limit (See M Pin Operation Description). Limit (See M Pin Operation Description).
+ QR can be an optocoupler
output or can be replaced
by a manual switch.
RLS 2 MΩ
QR
DC ON/OFF
Input 47 kΩ
Voltage For RLS = 2 MΩ
2
D M
CONTROL
VUV = 100 VDC
C VOV = 450 VDC
S
-
PI-2523-040501
Figure 40. Active-off Remote ON/OFF with LINE-SENSE.
2-181
Rev. O 11/05
TOP242-250
Application Examples TOPSwitch-GX (guaranteed minimum value of 75% vs. 64%

for TOPSwitch-II) allows the use of a smaller input capacitor
A High Efficiency, 30 W, Universal Input Power Supply (C1). The extended maximum duty cycle and the higher
The circuit shown in Figure 41 takes advantage of several of reflected voltage possible with the RCD clamp also permit
the TOPSwitch-GX features to reduce system cost and power the use of a higher primary to secondary turns ratio for T1,
supply size and to improve efficiency. This design delivers which reduces the peak reverse voltage experienced by the
30 W at 12 V, from an 85 VAC to 265 VAC input, at an ambient secondary rectifier D8. As a result a 60 V Schottky rectifier
of 50 °C, in an open frame configuration. A nominal efficiency can be used for up to 15 V outputs, which greatly improves
of 80% at full load is achieved using TOP244Y. power supply efficiency. The frequency reduction feature of the
TOPSwitch-GX eliminates the need for any dummy loading
The current limit is externally set by resistors R1 and R2 to a for regulation at no load and reduces the no-load/standby
value just above the low line operating peak DRAIN current consumption of the power supply. Frequency jitter provides
of approximately 70% of the default current limit. This improved margin for conducted EMI, meeting the CISPR 22
allows use of a smaller transformer core size and/or higher (FCC B) specification.
transformer primary inductance for a given output power,
reducing TOPSwitch-GX power dissipation, while at the same Output regulation is achieved by using a simple Zener sense
time avoiding transformer core saturation during startup and circuit for low cost. The output voltage is determined by the
output transient conditions. The resistors R1 & R2 provide a Zener diode (VR2) voltage and the voltage drops across the
signal that reduces the current limit with increasing line voltage, optocoupler (U2) LED and resistor R6. Resistor R8 provides
which in turn limits the maximum overload power at high input bias current to Zener VR2 for typical regulation of ±5% at
line voltage. This function in combination with the built-in the 12 V output level, over line and load and component
soft-start feature of TOPSwitch-GX, allows the use of a low cost variations.
RCD clamp (R3, C3 and D1) with a higher reflected voltage,
by safely limiting the TOPSwitch-GX drain voltage, with A High Efficiency, Enclosed, 70 W, Universal Adapter Supply
adequate margin under worst case conditions. Resistor R4 The circuit shown in Figure 42 takes advantage of several of the
provides line sensing, setting UV at 100 VDC and OV at TOPSwitch-GX features to reduce cost, power supply size and
450 VDC. The extended maximum duty cycle feature of
PERFORMANCE SUMMARY
2 Output Power:
Regulation:
30 W
± 4%
CY1
2.2 nF
Efficiency: ≥ 79% C14 R15
Ripple: ≤ 50 mV pk-pk 1 nF 150 Ω
L3 12 V @
3.3 µH 2.5 A
C3 R3
4.7 nF 68 kΩ
D8 C10 C11 C12
1 kV 2W
MBR1060 560 µF 560 µF 220 µF
35 V 35 V 35 V
BR1
600 V D1 RTN
2A UF4005
R4 D2
L1 2 MΩ 1N4148 R6
20 mH 1/2 W 150 Ω
R8
R1 T1 C6 150 Ω
4.7 MΩ 0.1 µF
C1 U2
68 µF 1/2 W
CX1 TOPSwitch-GX LTV817A
100 nF 400 V D L U1
250 VAC CONTROL TOP244Y
C
R5
F1 S X F 6.8 Ω VR2
J1 3.15 A 1N5240C
10 V, 2%
L R2
C5
9.09 kΩ 47 µF
10 V
N
PI-2657-081204
Figure 41. 30 W Power Supply using External Current Limit Programming and Line Sensing for UV and OV. F
2-182
Rev. O 11/05
TOP242-250
increase efficiency. This design delivers 70 W at 19 V, from an reduce Zener clamp dissipation. With a switching frequency of
85 VAC to 265 VAC input, at an ambient of 40 °C, in a small 132 kHz, a PQ26/20 core can be used to provide 70 W. To
sealed adapter case (4” x 2.15” x 1”). Full load efficiency is maximize efficiency, by reducing winding losses, two output
85% at 85 VAC rising to 90% at 230 VAC input. windings are used each with their own dual 100 V Schottky
rectifier (D2 and D3). The frequency reduction feature of the
Due to the thermal environment of a sealed adapter, a TOP249Y TOPSwitch-GX eliminates any dummy loading to maintain
is used to minimize device dissipation. Resistors R9 and R10 regulation at no load and reduces the no-load consumption of
externally program the current limit level to just above the the power supply to only 520 mW at 230 VAC input. Frequency
operating peak DRAIN current at full load and low line. This jittering provides conducted EMI meeting the CISPR 22
allows the use of a smaller transformer core size without (FCC B) / EN55022B specification, using simple filter components
saturation during startup or output load transients. Resistors (C7, L2, L3 and C6), even with the output earth grounded.
R9 and R10 also reduce the current limit with increasing line
voltage, limiting the maximum overload power at high input To regulate the output, an optocoupler (U2) is used with a
line voltage, removing the need for any protection circuitry on secondary reference sensing the output voltage via a resistor
the secondary. Resistor R11 implements an undervoltage and divider (U3, R4, R5, R6). Diode D4 and C15 filter and smooth
overvoltage sense as well as providing line feed-forward for the output of the bias winding. Capacitor C15 (1 µF) prevents
reduced output line frequency ripple. With resistor R11 set at the bias voltage from falling during zero to full load transients.
2 MΩ, the power supply does not start operating until the DC Resistor R8 provides filtering of leakage inductance spikes,
rail voltage reaches 100 VDC. On removal of the AC input, keeping the bias voltage constant even at high output loads.
the UV sense prevents the output glitching as C1 discharges, Resistor R7, C9 and C10 together with C5 and R3 provide
turning off the TOPSwitch-GX when the output regulation is loop compensation.
lost or when the input voltage falls to below 40 V, whichever
occurs first. This same value of R11 sets the OV threshold to Due to the large primary currents, all the small signal control
450 V. If exceeded, for example during a line surge, components are connected to a separate source node that is
TOPSwitch-GX stops switching for the duration of the surge, Kelvin connected to the SOURCE pin of the TOPSwitch-GX.
extending the high-voltage withstand to 700 V without device For improved common-mode surge immunity, the bias winding
damage. Capacitor C11 has been added in parallel with VR1 to common returns directly to the DC bulk capacitor (C1).
PERFORMANCE SUMMARY
2
C7 2.2 nF D2
C13 C12 C11 Output Power: 70 W
0.33 µF 0.022 µF 0.01 µF MBR20100
400 V 400 V 400 V Y1 Safety Regulation: ± 4%
Efficiency: ≥ 84%
Ripple: ≤ 120 mV pk-pk
No Load Consumption: < 0.52 W @ 230 VAC
VR1 D3
P6KE- MBR20100
C3 C14
200 820 µF L1 0.1 µF 19 V
BR1 25 V 200 µH 50 V @ 3.6 A
RS805 D1
8A 600 V UF4006
C2 C4 RTN
D4 820 µF R1 820 µF
1N4148 25 V 270 Ω 25 V
L2 R11
820 µH 2 MΩ R4
U2 31.6 kΩ
2A 1/2 W R8 PC817A
C1 4.7 Ω 1%
T1 R2
150 µF C15 R5
400 V 1 kΩ
C6 TOPSwitch-GX 1 µF 562 Ω
0.1 µF D L 50 V C9 1%
X2 L3 TOP249Y 4.7 nF 50 V
CONTROL
RT1 75 µH R9 C U1
10 Ω t° 2A 13 MΩ C10
1.7 A R3 0.1 µF
S X F R7
F1 6.8 Ω 56 kΩ 50 V
J1 3.15 A R10 C8 U3
0.1 µF TL431 R6
85-265 VAC
20.5 kΩ 4.75 kΩ
L 50 V C5
47 µF 1%
16 V
N All resistors 1/8 W 5% unless otherwise stated.
PI-2691-042203
Figure 42. 70 W Power Supply using Current Limit Reduction with Line and Line Sensing for UV and OV.
2-183
Rev. O 11/05
TOP242-250
A High Efficiency, 250 W, 250-380 VDC Input Power Supply However, VR1 is essential to limit the peak drain voltage
The circuit shown in Figure 43 delivers 250 W (48 V @ during startup and/or overload conditions to below the 700 V
5.2 A) at 84% efficiency using a TOP249 from a 250 VDC to rating of the TOPSwitch-GX MOSFET.
380 VDC input. DC input is shown, as typically at this power
level a p.f.c. boost stage would preceed this supply, providing the The secondary is rectifed and smoothed by D2 and C9, C10 and
DC input (C1 is included to provide local decoupling). Flyback C11. Three capacitors are used to meet the secondary ripple
topology is still usable at this power level due to the high output current requirement. Inductor L2 and C12 provide switching
voltage, keeping the secondary peak currents low enough so noise filtering.
that the output diode and capacitors are reasonably sized.
A simple Zener sensing chain regulates the output voltage.
In this example, the TOP249 is at the upper limit of its power The sum of the voltage drop of VR2, VR3 and VR4 plus the
capability and the current limit is set to the internal maximum LED drop of U2 gives the desired output voltage. Resistor R6
by connecting the X pin to SOURCE. However, line sensing limits LED current and sets overall control loop DC gain.
is implemented by connecting a 2 MΩ resistor from the L pin Diode D4 and C14 provide secondary soft-finish, feeding
to the DC rail. If the DC input rail rises above 450 VDC, then current into the CONTROL pin prior to output regulation and
TOPSwitch-GX will stop switching until the voltage returns to thus ensuring that the output voltage reaches regulation at startup
normal, preventing device damage. under low line, full load conditions. Resistor R9 provides a
discharge path for C14. Capacitor C13 and R8 provide control
Due to the high primary current, a low leakage inductance loop compensation and are required due to the gain associated
transformer is essential. Therefore, a sandwich winding with with such a high output voltage.
a copper foil secondary was used. Even with this technique,
the leakage inductance energy is beyond the power capability Sufficient heat sinking is required to keep the TOPSwitch-GX
of a simple Zener clamp. Therefore, R2, R3 and C6 are added device below 110 °C when operating under full load, low line
in parallel to VR1. These have been sized such that during and maximum ambient temperature. Airflow may also be
normal operation, very little power is dissipated by VR1, required if a large heatsink area is not acceptable.
the leakage energy instead being dissipated by R2 and R3.
C7
2.2 nF Y1 D2
2
MUR1640CT
R2 R3 C6 C10 C11 L2
+250-380 VR1 68 kΩ 68 kΩ 4.7 nF 560 µF 560 µF 48 V@
VDC P6KE200 3 µH 8A 5.2 A
2W 2W 1 kV 63 V 63 V
C9 C12
560 µF 68 µF
63 V 63 V
D1
BYV26C RTN
D2
1N4148 U2
LTV817A
R1
2 MΩ
1/2 W R9
T1 10 kΩ
C4
C1 1 µF
22 µF 50 V
400 V R6
TOPSwitch-GX 100 Ω
C13
D L TOP249Y 150 nF D4
PERFORMANCE SUMMARY U1
CONTROL 63 V 1N4148
Output Power: 250 W C
VR2 22 V
Line Regulation: ± 1% BZX79B22
Load Regulation: ± 5% R4
S X F 6.8 Ω C14
Efficiency: ≥ 85% VR3 12 V 22 µF
Ripple: < 100 mV pk-pk C3 BZX79B12 R8 63 V
0.1 µF C3 56 Ω
No Load Consumption: ≤ 1.4 W (300 VDC) 50 V 47 µF
10 V VR4 12 V
BZX79B12
0V All resistor 1/8 W 5% unless

otherwise stated. PI-2692-081204
Figure 43. 250 W, 48 V Power Supply using TOP249.
2-184
Rev. O 11/05
TOP242-250
Multiple Output, 60 W, 185-265 VAC Input Power Supply to the relatively large size of C2). An optional MOV (RV1)
Figure 44 shows a multiple output supply typical for high end extends the differential surge protection to 6 kV from 4 kV.
set-top boxes or cable decoders containing high capacity hard
disks for recording. The supply delivers an output power of Leakage inductance clamping is provided by VR1, R5 and C5,
45 W continuous/60 W peak (thermally limited) from an input keeping the DRAIN voltage below 700 V under all conditions.
voltage of 185 VAC to 265 VAC. Efficiency at 45 W, Resistor R5 and capacitor C5 are selected such that VR1
185 VAC is ≥ 75%. dissipates very little power except during overload conditions.
The frequency jittering feature of TOPSwitch-GX allows the
The 3.3 V and 5 V outputs are regulated to ±5% without circuit shown to meet CISPR22B with simple EMI filtering
the need for secondary linear regulators. DC stacking (the (C1, L1 and C6) and the output grounded.
secondary winding reference for the other output voltages is
connected to the cathode of D10 rather than the anode) is used The secondaries are rectified and smoothed by D7 to D11, C7,
to minimize the voltage error for the higher voltage outputs. C9, C11, C13, C14, C16 and C17. Diode D11 for the 3.3 V
output is a Schottky diode to maximize efficiency. Diode D10
Due to the high ambient operating temperature requirement for the 5 V output is a PN type to center the 5 V output at 5 V.
typical of a set-top box (60 °C), the TOP246Y is used to The 3.3 V and 5 V output require two capacitors in parallel to
reduce conduction losses and minimize heatsink size. Resistor meet the ripple current requirement. Switching noise filtering
R2 sets the device current limit to 80% of typical to limit is provided by L2 to L5 and C8, C10, C12, C15 and C18.
overload power. The line-sense resistor (R1) protects the Resistor R6 prevents peak charging of the lightly loaded 30 V
TOPSwitch-GX from line surges and transients by sensing when output. The outputs are regulated using a secondary reference
the DC rail voltage rises to above 450 V. In this condition the (U3). Both the 3.3 V and 5 V outputs are sensed via R11
TOPSwitch-GX stops switching, extending the input voltage and R10. Resistor R8 provides bias for U3 and R7 sets the
withstand to 496 VAC, which is ideal for countries with overall DC gain. Resistor R9, C19, R3 and C5 provide loop
poor power quality. A thermistor (RT1) is used to prevent compensation. A soft-finish capacitor (C20) eliminates output
premature failure of the fuse by limiting the inrush current (due overshoot.
R6 D7
PERFORMANCE SUMMARY
2
10 Ω UF4003 30 V @
Output Power: 45 W Cont./60 W Peak 0.03 A
C7 L2 C8
Regulation: D8 47 µF 10 µF
3.3 µH
3.3 V: ± 5% UF5402 50 V 3A 50 V 18 V @
5 V: ± 5% 0.5 A
C9
12 V: ± 7% 330 µF L3 C10
100 µF
D9 3.3 µH
18 V: ± 7% UF5402 25 V
3A 25 V 12 V @
30 V: ± 8% 0.6 A
Efficiency: ≥75% C11 C13 C16 C12
C6 390 µF 1000 µF 1000 µF 100 µF
No Load Consumption: 0.6 W 2.2 nF 35 V 25 V 25 V L4
3.3 µH 25 V
Y1
VR1 R5 5A 5V@
P6KE170 68 kΩ 3.2 A
2W C14 C15
1000 µF L5 220 µF
D10 3.3 µH
BYV32-200 25 V 16 V
5A 3.3 V @
C5 3A
1 nF
400 V D11 C18
C17 220 µF
MBR1045 1000 µF 16 V
D1-D4 25 V
1N4007 V RTN
D6
1N4937
C2
L1 68 µF
20 mH 400 V R10
0.8A D6 C3 R7 15.0
R1
1N4148 1 µF 150 Ω kΩ
2 MΩ 50 V
C1 1/2 W T1 U2
0.1 µF LTV817 R8
X1 1 kΩ R11
9.53
TOPSwitch-GX kΩ
RV1 D L
TOP246Y
275 V CONTROL U1
14 mm R9 C19
C 3.3 kΩ 0.1 µF
F1 C3
3.15 A 0.1 µF R3
J1 S X F 50 V 6.8 Ω
RT1
C20
185-265 VAC
10 Ω U3
t°
R2 C5
L 1.7 A 47 µF 22 µF TL431 R12
9.08 kΩ 10 V 10 V 10 k
PI-2693-081704
N
Figure 44. 60 W Multiple Output Power Supply using TOP246.
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Processor Controlled Supply Turn ON/OFF parking the print heads in the storage position. In the case of
A low cost momentary contact switch can be used to turn products with a disk drive, the shutdown procedure may include
the TOPSwitch-GX power on and off under microprocessor saving data or settings to the disk. After the shutdown procedure
control, which may be required in some applications such as is complete, when it is safe to turn off the power supply, the
printers. The low power remote OFF feature allows an microprocessor releases the M pin by turning the optocoupler
elegant implementation of this function with very few external U4 off. If the manual switch and the optocouplers U3 and U4
components, as shown in Figure 45. Whenever the push are not located close to the M pin, a capacitor CM may be needed
button momentary contact switch P1 is closed by the user, the to prevent noise coupling to the pin when it is open.
optocoupler U3 is activated to inform the microprocessor of
this action. Initially, when the power supply is off (M pin is The power supply could also be turned on remotely through
floating), closing of P1 turns the power supply on by shorting a local area network or a parallel or serial port by driving the
the M pin of the TOPSwitch-GX to SOURCE through a diode optocoupler U4 input LED with a logic signal. Sometimes it is
(remote ON). When the secondary output voltage VCC is easier to send a train of logic pulses through a cable (due to AC
established, the microprocessor comes alive and recognizes that coupling of cable, for example) instead of a DC logic level as
the switch P1 is closed through the switch status input that is a wake up signal. In this case, a simple RC filter can be used
driven by the optocoupler U3 output. The microprocessor then to generate a DC level to drive U4 (not shown in Figure 45).
sends a power supply control signal to hold the power supply This remote on feature can be used to wake up peripherals
in the on-state through the optocoupler U4. If the user presses such as printers, scanners, external modems, disk drives, etc.,
the switch P1 again to command a turn off, the microprocessor as needed from a computer. Peripherals are usually designed
detects this through the optocoupler U3 and initiates a shutdown to turn off automatically if they are not being used for a period
procedure that is product specific. For example, in the case of of time, to save power.
the inkjet printer, the shutdown procedure may include safely
VCC
(+5 V)
2 External
Wake-up
High Voltage Signal
DC Input
MICRO- Power
PROCESSOR/ Supply
100 kΩ CONTROLLER ON/OFF
U2 Control
27 kΩ
LOGIC LOGIC 1N4148

1N4148
INPUT OUTPUT 6.8 kΩ
D M TOPSwitch-GX
U4
CONTROL
U3 C
6.8 kΩ
CM 47 µF
S F U1 U3
P1 1 nF P1 Switch
LTV817A Status U4
LTV817A
RETURN
PI-2561-030805
Figure 45. Remote ON/OFF using Microcontroller.
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In addition to using a minimum number of components, the switch and subsequent bouncing of the switch has no
TOPSwitch-GX provides many technical advantages in this effect. If necessary, the microprocessor could implement
type of application: the switch debouncing in software during turn off, or a filter
capacitor can be used at the switch status input.
1. Extremely low power consumption in the off mode: 80 mW
typical at 110 VAC and 160 mW typical at 230 VAC. This 4. No external current limiting circuitry is needed for the
is because, in the remote OFF mode, the TOPSwitch-GX operation of the U4 optocoupler output due to internal
consumes very little power and the external circuitry does limiting of M pin current.
not consume any current (either M, L or X pin is open) from
the high-voltage DC input. 5. No high-voltage resistors to the input DC voltage rail are
required to power the external circuitry in the primary. Even
2. A very low cost, low-voltage/current, momentary contact the LED current for U3 can be derived from the CONTROL
switch can be used. pin. This not only saves components and simplifies layout,
but also eliminates the power loss associated with the high-
3. No debouncing circuitry for the momentary switch is voltage resistors in both ON and OFF states.
required. During turn on, the startup time of the power
supply (typically 10 ms to 20 ms) plus the microprocessor 6. Robust design: There is no ON/OFF latch that can be
initiation time act as a debouncing filter, allowing a turn on accidentally triggered by transients. Instead, the power
only if the switch is depressed firmly for at least the above supply is held in the ON-state through the secondary-side
delay time. During turn off, the microprocessor initiates microprocessor.
the shutdown sequence when it detects the first closure of
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Key Application Considerations
TOPSwitch-II vs. TOPSwitch-GX
Table 4 compares the features and performance differences Other features increase the robustness of design, allowing cost
between TOPSwitch-GX and TOPSwitch-II. Many of the new savings in the transformer and other power components.
features eliminate the need for additional discrete components.
Function TOPSwitch-GX
TOPSwitch-II TOPSwitch-GX Figures
Advantages
Soft-Start N/A* 10 ms • Limits peak current and voltage
component stresses during start-
up
• Eliminates external components
used for soft-start in most
applications
• Reduces or eliminates output
overshoot
External Current N/A* Programmable 100% 11,20,21, • Smaller transformer
Limit to 30% of default 24,25,27, • Higher efficiency
current limit 28,34,35, • Allows power limiting (constant
38,39 overload power independent of
line voltage)
• Allows use of larger device for
lower losses, higher efficiency
and smaller heatsink
2 DCMAX 67% 78% 7 • Smaller input cap (wider dynamic
range)
• Higher power capability (when
used with RCD clamp for large
VOR)
• Allows use of Schottky secondary
rectifier diode for up to 15 V
output for high efficiency
Line Feed-Forward N/A* 78% to 38% 7,11,17, • Rejects line ripple
with DC MAX Reduction 26,27,28,
31,40
Line OV Shutdown N/A* Single resistor 11,17,19, • Increases voltage withstand
programmable 26,27,28 capability against line surge
31,33,40
Line UV Detection N/A* Single resistor 11,17,18, • Prevents auto-restart glitches
programmable 26,27,28, during power down
31,32,40
Switching Frequency 100 kHz ±10% 132 kHz ±6% 13,15 • Smaller transformer
• Below start of conducted EMI
limits
Table 4. Comparison Between TOPSwitch-II and TOPSwitch-GX (continued on next page). *Not available
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TOPSwitch-II TOPSwitch-GX Figures
Advantages
Switching Frequency N/A* 66 kHz ±7% 14,15 • Lower losses when using RC and
Option (Y, R and F RCD snubber for noise reduction
Packages) in video applications
• Allows for higher efficiency in
standby mode
• Lower EMI (second harmonic
below 150 kHz)
Frequency Jitter N/A* ±4 kHz @ 132 kHz 9,46 • Reduces conducted EMI
±2 kHz @ 66 kHz
Frequency Reduction N/A* At a duty cycle below 7 • Zero load regulation without
10% dummy load
• Low power consumption at
no-load
Remote ON/OFF N/A* Single transistor or 11,22,23, • Fast ON/OFF (cycle-by-cycle)
optocoupler interface 24,25,26, • Active-on or active-off control
or manual switch 27,29,36, • Low consumption in remote off
37,38,39, state
40 • Active-on control for fail-safe
• Eliminates expensive in-line
ON/OFF switch
• Allows processor controlled turn
ON/OFF
• Permits shutdown/wake-up of
peripherals via LAN or parallel
port
Synchronization N/A* Single transistor or • Synchronization to external lower 2
optocoupler interface frequency signal
• Starts new switching cycle on
demand
Thermal Shutdown 125 °C min. Hysteretic 130 °C • Automatic recovery from thermal
Latched min. shutdown (with fault
75 °C hysteresis) • Large hysteresis prevents circuit
board overheating
Current Limit ±10% (@ 25 °C) ±7% (@ 25 °C) • 10% Higher power capability due
Tolerance -8% (0 °C to -4% Typical to tighter tolerance
100 °C) (0 °C to 100 °C)**
DRAIN DIP 0.037” / 0.94 mm 0.137” / 3.48 mm • Greater immunity to arcing as a
Creepage SMD 0.037” / 0.94 mm 0.137” / 3.48 mm result of build-up of dust, debris
at Package and other contaminants
TO-220 0.046” / 1.17 mm 0.068” / 1.73 mm
DRAIN Creepage at 0.045” / 1.14 mm 0.113” / 2.87 mm • Performed leads accommodate
PCB for Y, R and F (R and F Package (performed leads) large creepage for PCB layout
Packages N/A*) • Easier to meet Safety (UL/VDE)
Table 4 (cont). Comparison Between TOPSwitch-II and TOPSwitch-GX. *Not available **Current limit set to internal maximum
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TOPSwitch-FX TOPSwitch-GX
Advantages
Light Load Operation Cycle skipping Frequency and duty • Improves light load efficiency
cycle reduction • Reduces no-load consumption
Line Sensing/Exter- Line sensing and Line sensing and • Additional design flexibility allows all
nally Set Current externally set current externally set current features to be used simultaneously
Limit (Y, R and F limit mutually limit possible simul-
Packages) exclusive (M pin) taneously (functions
split onto L and X pins
Current Limit 100% to 40% 100% to 30% • Minimizes transformer core size in highly
Programming Range continuous designs
P/G Package Current Identical to Y TOP243-246 P and • Matches device current limit to package
Limits package G packages internal dissipation capability
current limits reduced • Allows more continuous design to lower
device dissipation (lower RMS currents)
Y/R/F Package 100% (R and F 90% (for equivalent • Minimizes transformer core size
Current Limits package N/A*) RDS(ON)) • Optimizes efficiency for most applications
Thermal Shutdown 125 °C min. 130 °C min. • Allows higher output powers in high
70 °C hysteresis 75 °C hysteresis ambient temperature applications
90 µA 60 µA • Reduces output line frequency ripple at
low line
Maximum Duty Cycle
• DCMAX reduction optimized for forward
Reduction Threshold
designs using TOP248, TOP249 and
TOP250
Line Undervoltage N/A* 40% of positive • Provides a well defined turn-off threshold
Negative (turn-off) (turn-on) threshold as the line voltage falls
2 Threshold
Soft-Start 10 ms (duty cycle) 10 ms (duty cycle + • Gradually increasing current limit in
current limit) addition to duty cycle during soft-start
further reduces peak current and voltage
• Further reduces component stresses
during startup
Table 5. Comparison Between TOPSwitch-FX and TOPSwitch-GX. *Not available
TOPSwitch-FX vs. TOPSwitch-GX to TOP250: Higher output voltages, with a maximum output
current of 6 A.
Table 5 compares the features and performance differences
between TOPSwitch-GX and TOPSwitch-FX. Many of the new For all devices, a 100 VDC minimum for 85-265 VAC and
features eliminate the need for additional discrete components. 250 VDC minimum for 230 VAC are assumed and sufficient
Other features increase the robustness of design, allowing cost heat sinking to keep device temperature ≤100 °C. Power
savings in the transformer and other power components. levels shown in the power table for the R package device
assume 6.45 cm2 of 610 g/m2 copper heat sink area in an
TOPSwitch-GX Design Considerations enclosed adapter, or 19.4 cm2 in an open frame.
Power Table TOPSwitch-GX Selection

Data sheet power table (Table 1) represents the maximum Selecting the optimum TOPSwitch-GX depends upon required
practical continuous output power based on the following maximum output power, efficiency, heat sinking constraints
conditions: TOP242 to TOP246: 12 V output, Schottky output and cost goals. With the option to externally reduce current
diode, 150 V reflected voltage (VOR) and efficiency estimates limit, a larger TOPSwitch-GX may be used for lower power
from curves contained in application note AN-29. TOP247 applications where higher efficiency is needed or minimal heat
sinking is available.
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Input Capacitor transformer saturation during startup. Also, soft-start limits the
The input capacitor must be chosen to provide the minimum DC amount of output voltage overshoot and, in many applications,
voltage required for the TOPSwitch-GX converter to maintain eliminates the need for a soft-finish capacitor.
regulation at the lowest specified input voltage and maximum
output power. Since TOPSwitch-GX has a higher DCMAX than EMI
TOPSwitch-II, it is possible to use a smaller input capacitor. The frequency jitter feature modulates the switching frequency
For TOPSwitch-GX, a capacitance of 2 µF per watt is possible for over a narrow band as a means to reduce conducted EMI peaks
universal input with an appropriately designed transformer. associated with the harmonics of the fundamental switching
frequency. This is particularly beneficial for average detection
Primary Clamp and Output Reflected Voltage VOR mode. As can be seen in Figure 46, the benefits of jitter increase
A primary clamp is necessary to limit the peak TOPSwitch-GX with the order of the switching harmonic due to an increase in
drain to source voltage. A Zener clamp requires few parts and frequency deviation.
takes up little board space. For good efficiency, the clamp
Zener should be selected to be at least 1.5 times the output The FREQUENCY pin of TOPSwitch-GX offers a switching
reflected voltage VOR, as this keeps the leakage spike conduction frequency option of 132 kHz or 66 kHz. In applications that
time short. When using a Zener clamp in a universal input require heavy snubbers on the drain node for reducing high
application, a VOR of less than 135 V is recommended to allow
for the absolute tolerances and temperature variations of the 80
PI-2576-010600
Zener. This will ensure efficient operation of the clamp circuit
70 TOPSwitch-II (no jitter)
and will also keep the maximum drain voltage below the rated
breakdown voltage of the TOPSwitch-GX MOSFET. 60
Amplitude (dBµV) 50
A high VOR is required to take full advantage of the wider DCMAX 40
of TOPSwitch-GX. An RCD clamp provides tighter clamp
30
voltage tolerance than a Zener clamp and allows a VOR as high
as 150 V. RCD clamp dissipation can be minimized by reducing 20
the external current limit as a function of input line voltage (see -10
Figures 21 and 35). The RCD clamp is more cost effective than
0
the Zener clamp but requires more careful design (see Quick EN55022B (QP)
Design Checklist). -10
2
EN55022B (AV)
-20
Output Diode 0.15 1 10 30
The output diode is selected for peak inverse voltage, output Frequency (MHz)
current, and thermal conditions in the application (including Figure 46a. TOPSwitch-II Full Range EMI Scan (100 kHz, No Jitter).
heatsinking, air circulation, etc.). The higher DCMAX of
TOPSwitch-GX, along with an appropriate transformer turns
ratio, can allow the use of a 60 V Schottky diode for higher 80
PI-2577-010600
efficiency on output voltages as high as 15 V (see Figure 41: A 70 TOPSwitch-GX (with jitter)
12 V, 30 W design using a 60 V Schottky for the output diode).
60
Amplitude (dBµV)
Bias Winding Capacitor 50

Due to the low frequency operation at no-load a 1 µF bias 40
winding capacitor is recommended. 30
20
Soft Start
Generally, a power supply experiences maximum stress at -10
startup before the feedback loop achieves regulation. For a 0
period of 10 ms, the on-chip soft-start linearly increases the duty -10
EN55022B (QP)
EN55022B (AV)
cycle from zero to the default DCMAX at turn on. In addition,
-20
the primary current limit increases from 85% to 100% over the 0.15 1 10 30
same period. This causes the output voltage to rise in an orderly
manner, allowing time for the feedback loop to take control of Frequency (MHz)
the duty cycle. This reduces the stress on the TOPSwitch-GX Figure 46b. TOPSwitch-GX Full Range EMI Scan (132 kHz, With
MOSFET, clamp circuit and output diode(s), and helps prevent Jitter) with Identical Circuitry and Conditions.
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frequency radiated noise (for example, video noise sensitive SOURCE connection trace should not be shared by the main
applications such as VCR, DVD, monitor, TV, etc.), operating MOSFET switching currents. All SOURCE pin referenced
at 66 kHz will reduce snubber loss resulting in better efficiency. components connected to the MULTI-FUNCTION, LINE-
Also, in applications where transformer size is not a concern, SENSE or EXTERNAL CURRENT LIMIT pins should
use of the 66 kHz option will provide lower EMI and higher also be located closely between their respective pin and
efficiency. Note that the second harmonic of 66 kHz is still SOURCE. Once again, the SOURCE connection trace of these
below 150 kHz, above which the conducted EMI specifications components should not be shared by the main MOSFET
get much tighter. switching currents. It is very critical that SOURCE pin
switching currents are returned to the input capacitor negative
For 10 W or below, it is possible to use a simple inductor in terminal through a seperate trace that is not shared by the
place of a more costly AC input common mode choke to meet components connected to CONTROL, MULTI-FUNCTION,
worldwide conducted EMI limits. LINE-SENSE or EXTERNAL CURRENT LIMIT pins. This
is because the SOURCE pin is also the controller ground
Transformer Design reference pin.
It is recommended that the transformer be designed for
maximum operating flux density of 3000 Gauss and a peak flux Any traces to the M, L or X pins should be kept as short as
density of 4200 Gauss at maximum current limit. The turns ratio possible and away from the DRAIN trace to prevent noise
should be chosen for a reflected voltage (VOR) no greater than coupling. LINE-SENSE resistor (R1 in Figures 47-49) should
135 V when using a Zener clamp, or 150 V (max) when using be located close to the M or L pin to minimize the trace length
an RCD clamp with current limit reduction with line voltage on the M or L pin side.
(overload protection).
In addition to the 47 µF CONTROL pin capacitor, a high
For designs where operating current is significantly lower than frequency bypass capacitor in parallel may be used for better
the default current limit, it is recommended to use an externally noise immunity. The feedback optocoupler output should
set current limit close to the operating peak current to reduce peak also be located close to the CONTROL and SOURCE pins of
flux density and peak power (see Figures 20 and 34). In most TOPSwitch-GX.
applications, the tighter current limit tolerance, higher switching
frequency and soft-start features of TOPSwitch-GX contribute Y-Capacitor
to a smaller transformer when compared to TOPSwitch-II. The Y-capacitor should be connected close to the secondary
output return pin(s) and the positive primary DC input pin of
2 Standby Consumption the transformer.
Frequency reduction can significantly reduce power loss at
light or no load, especially when a Zener clamp is used. For Heat Sinking
very low secondary power consumption, use a TL431 regulator The tab of the Y package (TO-220) or F package (TO-262)
for feedback control. Alternately, switching losses can be is internally electrically tied to the SOURCE pin. To avoid
significantly reduced by changing from 132 kHz in normal circulating currents, a heat sink attached to the tab should not
operation to 66 kHz under light load conditions. be electrically tied to any primary ground/source nodes on the
PC board.
TOPSwitch-GX Layout Considerations
When using a P (DIP-8), G (SMD-8) or R (TO-263) package,
As TOPSwitch-GX has additional pins and operates at a copper area underneath the package connected to the
much higher power levels compared to previous TOPSwitch SOURCE pins will act as an effective heat sink. On double
families, the following guidelines should be carefully sided boards (Figure 49), top side and bottom side areas
followed. connected with vias can be used to increase the effective heat
sinking area.
Primary Side Connections
Use a single point (Kelvin) connection at the negative terminal In addition, sufficient copper area should be provided at
of the input filter capacitor for the TOPSwitch-GX SOURCE the anode and cathode leads of the output diode(s) for heat
pin and bias winding return. This improves surge capabilities sinking.
by returning surge currents from the bias winding directly to
the input filter capacitor. In Figures 47, 48 and 49, a narrow trace is shown between
the output rectifier and output filter capacitor. This trace acts
The CONTROL pin bypass capacitor should be located as as a thermal relief between the rectifier and filter capacitor to
close as possible to the SOURCE and CONTROL pins and its prevent excessive heating of the capacitor.
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Y1- heat sinking
Capacitor
+ Output Rectifier
HV Output Filter Capacitor
Input Filter Capacitor
- PRI T
r
BIAS a SEC
n
s
PRI f
S S D o
r
m
TOPSwitch-GX
e
BIAS r
TOP VIEW
M S S C
Opto-
R1 coupler
- DC +
R2 Out
PI-2670-042301
Figure 47. Layout Consideratiions for TOPSwitch-GX using P or G Package.
Safety Spacing 2
Y1- Maximize hatched copper
+ Capacitor
heat sinking
Output Rectifier
Output Filter Capacitor
-
T
r SEC
a
TOPSwitch-GX
n
D s
f
o
X r
L m
C e
TOP VIEW r
Opto-
R1 Heat Sink coupler
- DC +
Out
PI-2669-042301
Figure 48. Layout Consideratiions for TOPSwitch-GX using Y or F Package.
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Solder Side Output Filter Capacitors

Safety Spacing
Component Side
Y1-
+ Capacitor
TOP VIEW
HV
T
PRI r
a
Input Filter n
Capacitor PRI s
- f SEC
o
r
R1a - 1c m
e
r
BIAS
S
X
L - DC +
Out
C
Opto-
coupler Maximize hatched copper
TOPSwitch-GX heat sinking
PI-2734-043001
Figure 49. Layout Considerations for TOPSwitch-GX using R Package.
Quick Design Checklist 3. Thermal check – At maximum output power, minimum

2 As with any power supply design, all TOPSwitch-GX designs
input voltage and maximum ambient temperature, verify
that temperature specifications are not exceeded for
should be verified on the bench to make sure that components TOPSwitch-GX, transformer, output diodes and output
specifications are not exceeded under worst case conditions. The capacitors. Enough thermal margin should be allowed for
following minimum set of tests is strongly recommended: the part-to-part variation of the RDS(ON) of TOPSwitch-GX,
as specified in the data sheet. The margin required can
1. Maximum drain voltage – Verify that peak VDS does not either be calculated from the tolerances or it can be
exceed 675 V at highest input voltage and maximum accounted for by connecting an external resistance in
overload output power. Maximum overload output power series with the DRAIN pin and attached to the same
occurs when the output is overloaded to a level just before the heatsink, having a resistance value that is equal to the
power supply goes into auto-restart (loss of regulation). difference between the measured RDS(ON) of the device
under test and the worst case maximum specification.
maximum input voltage and maximum output load, Design Tools
verify drain current waveforms at startup for any signs of
transformer saturation and excessive leading edge current For a discussion on utilizing TOP248, TOP249 and TOP250
spikes. TOPSwitch-GX has a leading edge blanking time of in forward converter configurations, please refer to the
220 ns to prevent premature termination of the ON-cycle. TOPSwitch-GX Forward Design Methodology Application
Verify that the leading edge current spike is below the Note.
allowed current limit envelope (see Figure 52) for the
drain current waveform at the end of the 220 ns blanking Up-to-date information on design tools can be found at the
period. Power Integrations website: www.powerint.com
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DRAIN Voltage .................................................. -0.3 V to 700 V CURRENT LIMIT Pin Voltage ........................-0.3 V to 4.5 V
DRAIN Peak Current: TOP242......................................0.72 A MULTI-FUNCTION Pin Voltage ........................-0.3 V to 9 V
TOP243....................................... 1.44 A FREQUENCY Pin Voltage ..................................-0.3 V to 9 V
TOP244..........................................2.16 A Storage Temperature ..................................... -65 °C to 150 °C
TOP245....................................... 2.88 A Operating Junction Temperature(2) ................ -40 °C to 150 °C
TOP246..........................................4.32 A Lead Temperature(3) ...................................................... 260 °C
TOP247..........................................5.76 A Notes:
TOP248..........................................7.20 A 1. All voltages referenced to SOURCE, TA = 25 °C.
TOP249..........................................8.64 A 2. Normally limited by internal circuitry.
TOP250 ........................................10.08 A 3. 1/16 in. from case for 5 seconds.
CONTROL Voltage ................................................ -0.3 V to 9 4. Maximum ratings specified may be applied one at a time,
VCONTROL Current .................................................... 100 mA without causing permanent damage to the product.
LINE-SENSE Pin Voltage ................................... -0.3 V to 9 V Exposure to Absolute Maximum Rating conditions for
THERMAL IMPEDANCE
Thermal Impedance: Y or F Package: Notes:
(θJA)(1) .......................... ..................... 80 °C/W 1. Free standing with no heatsink.
(θJC)(2) ................................................ . 2 °C/W 2. Measured at the back surface of tab.
P or G Package: 3. Soldered to 0.36 sq. in. (232 mm2), 2 oz. (610 g/m2)
(θJA) ............................ 70 °C/W(3); 60 °C/W(4) copper clad.
(θJC)(5) ................................................ 11 °C/W 4. Soldered to 1 sq. in. (645 mm2), 2 oz. (610 g/m2) copper clad.
R Package: 5. Measured on the SOURCE pin close to plastic interface.
(θJA) ..........80 °C/W(7); 40 °C/W(4); 30 °C/W(6) 6. Soldered to 3 sq. in. (1935 mm2), 2 oz. (610 g/m2) copper clad.
(θJC)(5) .................................................. 2 °C/W 7. Soldered to foot print area, 2 oz. (610 g/m2) copper clad.
Conditions
2
SOURCE = 0 V; TJ = -40 to 125 °C
See Figure 53
CONTROL FUNCTIONS
FREQUENCY Pin
Switching Connected to SOURCE
124 132 140
IC = 3 mA;
Frequency fOSC
TJ = 25 °C
kHz
FREQUENCY Pin
(average) Connected to CONTROL
61.5 66 70.5
Duty Cycle at
ONSET of
DC(ONSET) 10 %
Frequency
Reduction
Switching 132 kHz Operation 30
Frequency near fOSC(DMIN) kHz
0% Duty Cycle 66 kHz Operation 15
Frequency Jitter 132 kHz Operation ±4

∆f kHz
Deviation 66 kHz Operation ±2
Frequency Jitter
fM 250 Hz
Modulation Rate
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Conditions
SOURCE = 0 V; TJ = -40 to 125 °C
See Figure 53
IL ≤ IL(DC) or IM ≤ IM(DC) 75 78 83
IL or IM = 190 µA
28 38 50
TOP242-247
Maximum Duty IL or IM = 100 µA

DCMAX IC = ICD1 66.5 %
TOP242-247
Cycle
IL = 190 µA
33 41.3 49.5
TOP248-250
IL = 100 µA
60 66.8 73.5
TOP248-250
Soft-Start Time tSOFT TJ = 25 °C; DCMIN to DCMAX 10 15 ms
PWM Gain DCreg IC = 4 mA; TJ = 25 °C -28 -23 -18 %/mA
PWM Gain
See Note A -0.01 %/mA/°C
Temperature Drift
TOP242-245 1.2 2.0 3.0
External Bias
IB See Figure 7 TOP246-249 1.6 2.6 4.0 mA
Current TOP250 1.7 2.7 4.2
CONTROL TOP242-245 6.0 7.0
Current at 0% IC(OFF) TJ = 25 °C TOP246-249 6.6 8.0 mA
Duty Cycle TOP250 7.3 8.5
2 Dynamic IC = 4 mA; TJ = 25 °C
ZC 10 15 22 Ω
Impedance See Figure 51
Dynamic
Impedance 0.18 %/°C
Temperature Drift
CONTROL Pin
7 kHz
Internal Filter Pole
CONTROL Pin VC = 0 V -5.0 -3.5 -2.0
Charging Current VC = 5 V -3.0 -1.8 -0.6
Charging Current
See Note A 0.5 %/°C
Temperature Drift
Auto-Restart
Upper Threshold VC(AR)U 5.8 V
Voltage
Auto-Restart
Lower Threshold VC(AR)L 4.5 4.8 5.1 V
Voltage
2-196
Rev. O 11/05
TOP242-250
Conditions
SOURCE = 0 V; TJ = -40 to 125 °C
See Figure 53
SHUTDOWN/AUTO-RESTART (cont.)
Auto-Restart
VC(AR)hyst 0.8 1.0 V
Hysteresis Voltage
Auto-Restart Duty
DC(AR) 4 8 %
Cycle
Auto-Restart
f(AR) 1.0 Hz
Frequency
MULTI-FUNCTION (M), LINE-SENSE (L) AND EXTERNAL CURRENT LIMIT (X) INPUTS
Line Under- Threshold 44 50 54 µA
Voltage Threshold
IUV TJ = 25 °C
Current and Hys-
Hysteresis 30 µA
teresis (M or L Pin)
Line Overvoltage
Threshold 210 225 240 µA
or Remote ON/OFF
Threshold Current IOV TJ = 25 °C
and Hysteresis Hysteresis 8 µA
(M or L Pin)
L Pin Voltage
VL(TH) 0.5 1.0 1.6 V 2
Threshold
Remote ON/OFF
Threshold -35 -27 -20
Negative
Threshold Current IREM (N) TJ = 25 °C µA
and Hysteresis Hysteresis 5
(M or X Pin)
L or M Pin Short IL(SC) or
VL, VM = VC 300 400 520 µA
Circuit Current IM(SC)
X or M Pin Short IX(SC) or Normal Mode -300 -240 -180

VX, VM = 0 V µA
Circuit Current IM(SC) Auto-Restart Mode -110 -90 -70
L or M Pin Voltage IL or IM = 50 µA 1.90 2.50 3.00

VL, VM V
(Positive Current) IL or IM = 225 µA 2.30 2.90 3.30
X Pin Voltage IX = -50 µA 1.26 1.33 1.40

VX V
(Negative Current) IX = -150 µA 1.18 1.24 1.30
M Pin Voltage IM = -50 µA 1.24 1.31 1.39

VM V
(Negative Current) IM = -150 µA 1.13 1.19 1.25
2-197
Rev. O 11/05
TOP242-250
Conditions
SOURCE = 0 V; TJ = -40 to 125 °C
See Figure 53
MULTI-FUNCTION, LINSE-SENSE AND EXTERNAL CURRENT LIMIT INPUTS (cont.)
Maximum Duty
Cycle Reduction IL(DC) or
TJ = 25 °C 40 60 75 µA
Onset Threshold IM(DC)
Current
X, L or M Pin
Remote OFF Floating
0.6 1.0
See Figure 71
DRAIN Supply ID(RMT)
VDRAIN = 150 V
mA
L or M Pin Shorted
Current to CONTROL
1.0 1.6
From Remote ON to Drain Turn-On

Remote ON Delay tR(ON)
See Note B
2.5 µs
Remote OFF Minimum Time Before Drain Turn-On

tR(OFF) 2.5 µs
Setup Time to Disable Cycle, See Note B
FREQUENCY INPUT
FREQUENCY Pin
VF See Note B 2.9 V
Threshold Voltage
FREQUENCY Pin
IF VF = VC 10 40 100 µA
Input Current
CIRCUIT PROTECTION
2 TOP242 P/G
Internal
TOP242 Y/R/F 0.418 0.45 0.481
TJ = 25 °C di/dt = 90 mA/µs
TOP243 P/G Internal

0.697 0.75 0.802
TJ = 25 °C di/dt = 150 mA/µs
TOP243 Y/R/F Internal
TJ = 25 °C 0.837 0.90 0.963
di/dt = 180 mA/µs
TOP244 P/G Internal
0.930 1.00 1.070
TJ = 25 °C di/dt = 200 mA/µs
Self Protection TOP244 Y/R/F Internal
1.256 1.35 1.445
Current Limit ILIMIT TJ = 25 °C di/dt = 270 mA/µs A
(See Note C) TOP245 P/G Internal
1.02 1.10 1.18
TJ = 25 °C di/dt = 220 mA/µs
1.674 1.80 1.926
TJ = 25 °C di/dt = 360 mA/µs
TOP246 P/G Internal
1.256 1.35 1.445
TJ = 25 °C di/dt = 270 mA/µs
2.511 2.70 2.889
TJ = 25 °C di/dt = 540 mA/µs
TJ = 25 °C 3.348 3.60 3.852
di/dt = 720 mA/µs
2-198
Rev. O 11/05
TOP242-250
Conditions
SOURCE = 0 V; TJ = -40 to 125 °C
See Figure 53
4.185 4.50 4.815
TJ = 25 °C di/dt = 900 mA/µs
Self Protection
Current Limit ILIMIT
TJ = 25 °C di/dt = 1080 mA/µs
5.022 5.40 5.778 A
(See Note C)
5.859 6.30 6.741
TJ = 25 °C di/dt = 1260 mA/µs
≤85 VAC 0.75 x
(Rectified Line Input) ILIMIT(MIN)
Initial Current Limit IINIT See Note B A
265 VAC 0.6 x
(Rectified Line Input) ILIMIT(MIN)
Leading Edge See Figure 52
tLEB 220 ns
Blanking Time TJ = 25 °C, IC = 4 mA
Current Limit
tIL(D) IC = 4 mA 100 ns
Delay
Thermal Shutdown
130 140 150 °C
Temperature
Thermal Shutdown
Ω 75 °C
Hysteresis
Power Up Reset
VC(RESET) Figure 53, S1 Open 1.75 3.0 4.25 V 2
Threshold Voltage
OUTPUT
TOP242 TJ = 25 °C 15.6 18.0
ID = 50 mA TJ = 100 °C 25.7 30.0
TOP243 TJ = 25 °C 7.80 9.00
ID = 100 mA TJ = 100 °C 12.9 15.0
TOP244 TJ = 25 °C 5.20 6.00
ID = 150 mA TJ = 100 °C 8.60 10.0
ON-State TOP245 TJ = 25 °C 3.90 4.50
RDS(ON) Ω
Resistance ID = 200 mA TJ = 100 °C 6.45 7.50
TOP246 TJ = 25 °C 2.60 3.00
ID = 300 mA TJ = 100 °C 4.30 5.00
TOP247 TJ = 25 °C 1.95 2.25
ID = 400 mA TJ = 100 °C 3.22 3.75
TOP248 TJ = 25 °C 1.56 1.80
ID = 500 mA TJ = 100 °C 2.58 3.00
2-199
Rev. O 11/05
TOP242-250
Conditions
SOURCE = 0 V; TJ = -40 to 125 °C
See Figure 53
OUTPUT (cont.)
TOP249 TJ = 25 °C 1.30 1.50
ID = 600 mA TJ = 100 °C 2.15 2.50
ON-State
RDS(ON) Ω
Resistance TOP250 TJ = 25 °C 1.10 1.28
ID = 700 mA TJ = 100 °C 1.85 2.15
OFF-State Drain VL, VM = Floating; IC = 4 mA
IDSS 470 µA
Leakage Current VDS = 560 V; TJ = 125 °C
Breakdown VL, VM = Floating; IC = 4 mA
BVDSS 700 V
Voltage See Note D, TJ = 25 °C
Rise Time tR Measured in a Typical Flyback 100 ns
Fall Time tF Converter Application 50 ns
SUPPLY VOLTAGE CHARACTERISTICS
DRAIN Supply
See Note E 36 V
Voltage
Shunt Regulator
VC(SHUNT) IC = 4 mA 5.60 5.85 6.10 V
Voltage
Shunt Regulator
±50 ppm/°C
Temperature Drift
2 Output MOSFET TOP242-245 1.0 1.6 2.5
ICD1 Enabled TOP246-249 1.2 2.2 3.2
Control Supply/ VX, VL, VM = 0 V TOP250 1.3 2.4 3.65
mA
Discharge Current Output MOSFET
ICD2 Disabled 0.3 0.6 1.3
VX, VL, VM = 0 V
NOTES:
B. Guaranteed by characterization. Not tested in production.
C. For externally adjusted current limit values, please refer to Figures 54b, 55b and 56b (Current Limit vs. External
Current Limit Resistance) in the Typical Performance Characteristics section. The tolerance specified is only valid
at full current limit.
D. Breakdown voltage may be checked against minimum BVDSS specification by ramping the DRAIN pin voltage up
E. It is possible to start up and operate TOPSwitch-GX at DRAIN voltages well below 36 V. However, the
CONTROL pin charging current is reduced, which affects startup time, auto-restart frequency, and auto-restart
duty cycle. Refer to Figure 68, the characteristic graph on CONTROL pin charge current (IC) vs. DRAIN voltage
for low voltage operation characteristics.
2-200
Rev. O 11/05
TOP242-250
t2
t1
HV
90% 90%
DRAIN t
D= 1
VOLTAGE t2
10%
0V
PI-2039-033001
PI-2022-033001
tLEB (Blanking Time)
120 1.3
PI-1939-091996
1.2
DRAIN Current (normalized)

100 1.1
1.0
80 0.9
0.8
IINIT(MIN) @ 85 VAC
0.7
60 IINIT(MIN) @ 265 VAC
0.6
0.5
40
0.4 ILIMIT(MAX) @ 25 °C
Dynamic 1 ILIMIT(MIN) @ 25 °C
= 0.3
Impedance Slope
20 0.2
0.1
0
0 2 4 6 8 10
0
0 1 2 3 4 5 6 7 8 2
CONTROL Pin Voltage (V) Time (µs)
Figure 51. CONTROL Pin I-V Characteristic. Figure 52. Drain Current Operating Envelope.
Y or R Package (X and L Pins) P or G Package (M Pin)
S1 470 Ω 0-100 kΩ
5W 0-100 kΩ
S5
5-50 V M
5-50 V
0-60 kΩ
40 V
L D
470 Ω CONTROL
C C TOPSwitch-GX
S2
S4 F X S
0-15 V
S3
47 µF 0.1 µF
0-60 kΩ
NOTES: 1. This test circuit is not applicable for current limit or output characteristic measurements.
2. For P and G packages, short all SOURCE pins together. PI-2631-081204
Figure 53. TOPSwitch-GX General Test Circuit.
2-201
Rev. O 11/05
TOP242-250
BENCH TEST PRECAUTIONS FOR EVALUATION OF ELECTRICAL CHARACTERISTICS
The following precautions should be followed when testing while in this auto-restart mode, there is only a 12.5% chance
TOPSwitch-GX by itself outside of a power supply. The that the CONTROL pin oscillation will be in the correct state
schematic shown in Figure 53 is suggested for laboratory testing (drain active state) so that the continuous drain voltage waveform
of TOPSwitch-GX. may be observed. It is recommended that the VC power supply
be turned on first and the DRAIN pin power supply second if
When the DRAIN pin supply is turned on, the part will be continuous drain voltage waveforms are to be observed. The
in the auto-restart mode. The CONTROL pin voltage will be 12.5% chance of being in the correct state is due to the divide-
oscillating at a low frequency between 4.8 V and 5.8 V and by-8 counter. Temporarily shorting the CONTROL pin to the
the drain is turned on every eigth cycle of the CONTROL pin SOURCE pin will reset TOPSwitch-GX, which then will come
oscillation. If the CONTROL pin power supply is turned on up in the correct state.

PI-2653-031904
1.1
Scaling Factors:
1.0 TOP242 P/G/Y/R/F: .45 200
TOP243 P/G: .75
0.9 TOP243 Y/R/F: .90 180
TOP244 P/G: 1
Current Limit (A)
0.8 TOP244 Y/R/F: 1.35 160
di/dt (mA/µs)
TOP245 Y/R/F: 1.80
0.7 TOP246 Y/R/F: 2.70 140
TOP247 Y/R/F: 3.60
0.6 TOP248 Y/R/F 4.50 120
TOP249 Y/R/F: 5.40
0.5 TOP250 Y/R/F: 6.32 100
0.4 80
0.3 60
2 0.2
-250 -200 -150 -100 -50 0
40
IX or IM (µA)
Figure 54a. Current Limit vs. X or M Pin Current (see Figures 55a and 56a for TOP245P/G and TOP246P/G).
PI-2652-042303
1.1
Scaling Factors:
1.0 TOP242 P/G/Y/R/F: .45 200
TOP243 P/G: .75
0.9 TOP243 Y/R/F: .90 180
TOP244 P/G: 1
Current Limit (A)
0.8 TOP244 Y/R/F: 1.35 160

di/dt (mA/µs)
Maximum TOP245 Y/R/F: 1.80

0.7 TOP246 Y/R/F: 2.70 140
Minimum
TOP247 Y/R/F: 3.60
0.6 TOP248 Y/R/F 4.50 120
TOP249 Y/R/F: 5.40
0.5 Typical 100
TOP250 Y/R/F: 6.32
0.4 80
Maximum and minimum levels
0.3 are based on characterization. 60
0.2 40
0 5K 10K 15K 20K 25K 30K 35K 40K 45K
External Current Limit Resistor RIL (Ω)
Figure 54b. Current Limit vs. External Current Limit Resistance (see Figures 55b and 56b for TOP245P/G and
TOP246P/G).
2-202
Rev. O 11/05
TOP242-250

PI-3652-110405
1.1
Scaling Factor:
1.0 TOP245P/G: 1.1 200
0.9 180
Current Limit (A)
0.8 160
di/dt (mA/µs)
0.7 140
0.6 120
0.5 100
0.4 80
0.3 60
0.2 40
-250 -200 -150 -100 -50 0
IM (µA)
Figure 55a. Current Limit vs. MULTI-FUNCTION Pin Current (TOP245P/G only).
PI-3651-110405
1.1
Scaling Factor:
1.0 TOP245P/G: 1.1 200
0.9 180
Current Limit (A)
0.8 160
di/dt (mA/µs)
Refer to MULTIFUNCTION (M) Pin
0.7 140
Operation section
0.6 120
0.5 Typical 100
0.4
Measured at 25 °C.
80
2
0.3 60
0.2 40
0 5K 10K 15K 20K 25K 30K 35K 40K 45K
Figure 55b. Current Limit vs. External Current Limit Resistance (TOP245P/G only).
1.25
Current Limit (Normalized to 25 °C)
PI-3653-073003
1.20
1.15 0 °C
1.10
1.05
1.00
.95
25 °C
.90
.85
.80 100 °C
.75
.70
0 5K 10K 15K 20K 25K 30K 35K 40K 45K
Figure 55c. External Current Limit vs. External Current Limit Resistance at 0 °C, 25 °C and 100 °C Junction
Temperature (TOP245P/G only).
2-203
Rev. O 11/05
TOP242-250

PI-3724-110405
1.1
Scaling Factor:
1.0 TOP246P/G: 1.35 200
0.9 180
Current Limit (A)
0.8 160
di/dt (mA/µs)
0.7 140
0.6 120
0.5 100
0.4 80
0.3 60
0.2 40
-250 -200 -150 -100 -50 0
IM (µA)
Figure 56a. Current Limit vs. MULTI-FUNCTION Pin Current (TOP246P/G only).
PI-3725-110405
1.1
Scaling Factor:
1.0 TOP246P/G: 1.35 200
0.9 180
Current Limit (A)
0.8 160
di/dt (mA/µs)
Refer to MULTIFUNCTION (M) Pin
0.7 140
Operation section
0.6 120
0.5 Typical
100
2 0.4 80
Measured at 25 °C.
0.3 60
0.2 40
0 5K 10K 15K 20K 25K 30K 35K 40K 45K
Figure 56b. Current Limit vs. External Current Limit Resistance (TOP246P/G only).
1.25
Current Limit (Normalized to 25 °C)
PI-3726-100703
1.20
1.15 0 °C
1.10
1.05
1.00
.95
25 °C
.90
.85
.80
100 °C
.75
.70
0 5K 10K 15K 20K 25K 30K 35K 40K 45K
Figure 56c. External Current Limit vs. External Current Limit Resistance at 0 °C, 25 °C and 100 °C Junction
Temperature (TOP246P/G only).
2-204
Rev. O 11/05
TOP242-250
1.1 1.2
PI-1123A-033001
PI-176B-033001
1.0
Output Frequency
Breakdown Voltage
0.8
1.0 0.6
0.4
0.2
0.9 0
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
Figure 57. Breakdown Voltage vs. Temperature. Figure 58. Frequency vs. Temperature.
1.2 1.2
PI-2555-033001
PI-2554-110705
1.0 1.0
0.8
Current Limit
0.8
Current Limit
0.6 0.6
Use for TOP242-250 Y/R/F

0.4 0.4
2
packages and TOP242-244 P/G
packages only. See Figures 55c
and 56c for TOP245P/G and
0.2 0.2
TOP246P/G.
0 0
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
Figure 59. Internal Current Limit vs. Temperature. Figure 60. External Current Limit vs. Temperature with
RIL = 12 kΩ.
1.2 1.2 PI-2552-033001

PI-2553-033001
1.0 1.0
Overvoltage Threshold
0.8 0.8
0.6 0.6
0.4 0.4
0.2 0.2
0
0
-50 -25 0 25 50 75 100 125 150
-50 -25 0 25 50 75 100 125 150
Figure 62. Undervoltage Threshold vs. Temperature.
Figure 61. Overvoltage Threshold vs. Temperature.
2-205
Rev. O 11/05
TOP242-250
6.0 1.6
PI-2688-102700
PI-2689-102300
VX = 1.33 - IXx 0.66 kΩ
LINE SENSE Pin Voltage (V)
EXTERNAL CURRENT LIMIT

5.5 1.4
-200 µA ≤ IX ≤ -25 µA
5.0 1.2
Pin Voltage (V)

4.5 1.0
4.0 0.8
3.5 0.6
3.0 0.4
2.5 0.2
2.0 0
0 100 200 300 400 -240 -180 -120 -60 0
LINE-SENSE Pin Current (µA) EXTERNAL CURRENT LIMIT Pin Current (µA)
Figure 63a. LINE-SENSE Pin Voltage vs. Current. Figure 63b. EXTERNAL CURRENT LIMIT Pin Voltage
vs. Current.
6 1.6
PI-2541-102700
PI-2542-102700
MULTI-FUNCTION Pin Voltage (V)
MULTI-FUNCTION Pin Voltage (V)

VM = 1.37 - IMx 1 kΩ
1.4
5 -200 µA ≤ IM ≤ -25 µA
1.2
4
1.0
3 0.8
0.6
2
2 See
0.4
1 Expanded
Version 0.2
0 0
-300 -200 -100 0 100 200 300 400 500 -300 -250 -200 -150 -100 -50 0
MULTI-FUNCTION Pin Current (µA) MULTI-FUNCTION Pin Current (µA)
Figure 64a. MULTI-FUNCTION Pin Voltage vs. Current. Figure 64b. MULTI-FUNCTION Pin Voltage vs. Current
(Expanded).
1.2 1.2
PI-2562-033001
PI-2563-033001
Onset Threshold Current
1.0 1.0
CONTROL Current
0.8 0.8
0.6 0.6
0.4 0.4
0.2 0.2
0 0
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
Figure 65. Control Current Out at 0% Duty Cycle Figure 66. Max. Duty Cycle Reduction Onset Threshold
vs. Temperaure. Current vs. Temperature.
2-206
Rev. O 11/05
TOP242-250
6 2
PI-2564-101499
PI-2645-010802
VC = 5 V

1.6
DRAIN Current (A)
CONTROL Pin
4
1.2
Scaling Factors:
3 TOP250 1.17
TOP249 1.00
TOP248 0.83 0.8
2 TOP247 0.67
TOP246 0.50
TOP245 0.33 0.4
1 TOP244 0.25
TCASE = 25 °C TOP243 0.17
TCASE = 100 °C TOP242 0.08
0 0
0 2 4 6 8 10 12 14 16 18 20 0 20 40 60 80 100
DRAIN Voltage (V) DRAIN Voltage (V)
Figure 67. Output Characteristics. Figure 68. IC vs. DRAIN Voltage.
10000 600
PI-2650-020802
PI-2646-010802
Scaling Factors:
500 TOP250 1.17
DRAIN Capacitance (pF)
TOP249 1.00
Scaling Factors: TOP248 0.83
1000 TOP250 1.17 400 TOP247 0.67
Power (mW)
TOP246 0.50
TOP249 1.00 TOP245 0.33
TOP248 0.83 TOP244 0.25
TOP247 0.67 300 TOP243 0.17
TOP246 0.50 TOP242 0.08
TOP245 0.33
TOP244 0.25
2
100 200
TOP243 0.17
TOP242 0.08
100
10 0
0 100 200 300 400 500 600 0 100 200 300 400 500 600
Drain Voltage (V) DRAIN Voltage (V)
Figure 69. COSS vs. DRAIN Voltage. Figure 70. DRAIN Capacitance Power.
1.2
Remote OFF DRAIN Supply Current
PI-2690-102700
1.0
0.8
0.6
0.4
0.2
0
-50 0 50 100 150
Figure 71. Remote OFF DRAIN Supply Current vs.
Temperature.
2-207
Rev. O 11/05
TOP242-250

TOPSwitch Product Family
GX Series Number
Package Identifier
G Plastic SMD-8B (TOP242-246 only)
P Plastic DIP-8B (TOP242-246 only)
Y Plastic TO-220-7C
R Plastic TO-263-7C (available only with TL option)
F Plastic TO-262-7C
Lead Finish
N Pure Matte Tin (Pb-Free) (P, G, Y & F Packages)
TOP 242 G N - TL TL Tape & Reel, (G Package: 1000 min., R Package: 750 min.)
Revision Notes Date

D - 11/00
E 1) Added R package (D2PAK). 7/01
2) Corrected abbreviations (s = seconds).
3) Corrected x-axis units in Figure 11 (µA).
4) Added missing external current limit resistor in Figure 25 (RIL).
5) Corrected spelling.
6) Added caption for Table 4.
2 7) Corrected Breakdown Voltage parameter condition (TJ = 25 °C).
8) Corrected font sizes in figures.
9) Figure 40 replaced.
10) Corrected schematic component values in Figure 44.
F 1) Corrected Power Table value. 9/01
G 1) Added TOP250 device and F package (TO-262). 1/02
2) Added R package Thermal Impedance parameters and adjusted Output Power values in Table 1.
3) Adjusted Off-State Current value.
H 1) Added note to parameter table for Breakdown Voltage measurement. 9/02
2) Miscellaneous text corrections.
I 1) Updated P, Y, R and F package information. 4/03
2) Revised thermal impedances (θJA) for all package types.
3) Expanded Maximum Duty Cycle and deleted Maximum Duty Cycle Reduction Slope parameters.
4) Corrected DIP-8B and SMD-8B Package Drawings.
J 1) Added TOP245P. 8/03
2) Miscellaneous text corrections.
K 1) Corrected typographic errors in Figures 4, 6, 20, 28 and 34; and in MULTI-FUNCTION (M) Pin 9/03
Operation section.
L 1) Added TOP246P. 3/04
M 1) Added lead-free ordering information. 12/04
N 1) Updated Maximum Duty Cycle conditions. 4/05
2) Minor error corrections.
3) Added Note 4 to Absolute Maximum Ratings specification.
O 1) Added TOP245G and TOP246G 11/05
2-208
Rev. O 11/05
Data Sheets 2
Application Notes 3

APPLICATION NOTES
APPLICATION NOTES
Quick Reference
Guide
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PS
PS
PS
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log
sig ak
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sig ink
sig ink
s
Li n
Fly 8 TO
Fly TO
Fo 0 TO
Fly 2 TO
Fo 1 DP
Te 5 De
Pe
Gu 5 L i
Cu ck
Me ck
L
s
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-29
-37
-39
-40
-41
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fet
rw
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-1
-1
-3
-3
-3
-3
Market/Application M
AN
AN
AN
AN
AN
AN
AN
AN
AN
AN
AN
Co
De
De
De
De
Battery Chargers B
Cell phone adapter/charger � � � � � � � Ce
Cordless phone charger � � � � � Co
Cordless tool charger � � � � � � � � Co
Digital camera charger � � � � � � Di
PDA adapter � � � � � � � PD
MP3 / MD player � � � � � MP
Industrial Charger � � � � Ind
Communication C
24/48 V DC-DC converter � 24
Broadband modem � � � � � � Br
Router � � � � � Ro
Telecomm line card � Te
VoIP phone � Vo
PoE powered device (PD) � Po
Computer C
PC main power supply � � PC
PC standby power supply � � � � PC
External media drive � � � � � Ex
Laptop adapter � � � � La
LCD monitor / TV � � � � LC
LCD projector � � � � LC
Multimedia speaker amplifier � � � � � Mu
Printer � � � � � � Pr
Scanner � � � � � � Sc
USB hub � � � � US
Wireless access point/router � � � � � W
Consumer C
Cable/satellite set-top box � � � � � Ca
DVD players/recorder � � � � � DV
Television standby � � � � � Te
Video game � � � � � Vi
Home Appliance H
Major Appliance � � � � � � Ma
Small Appliance � � � � � � Sm
Home Comfort � � � � � � Ho
General Lighting � � � � � � � � Ge
LED Lighting � � � � � � LE
Industrial In
Lighting � � � � � � � � Lig
Programmable logic controller � � � � � � Pr
Uninterruptible power supply � � � � Un
Utility meter � � � � � � Ut
DESIGN IDEAS
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Battery Chargers
Cell phone adapter / charger � �
Cordless phone charger � �
Cordless tool charger � � � � �
Digital camera charger � �
PDA adapter � �
MP3 / MD player adapter � �
Industrial Charger � � �
Communication
24/48 V DC-DC converter � � �
Broadband modem
Router � � �
Telecomm line card � � �
VoIP phone � � �
PoE Powered Device (PD) � �
Computer
PC main power supply �
PC standby power supply �
External media drives � � � �
Laptop adapter � �
LCD monitor / TV � �
LCD projector � � �
Multimedia speaker amplifier � �
Printer � � � �
Scanner � � � � �
USB hub
Wireless access point/router
Consumer
Cable / satellite set-top box � �
DVD player / recorder � �
Video game � � �
Home Appliance
Major Appliance � � � �
Small Appliance � � �
Home Comfort � � � �
General Lighting � �
LED lighting
Industrial
Lighting � � �
Programmable logic controller � � � � �
Uninterruptible power supply � � �
Utility meter � �
DESIGN IDEAS
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Market/Application Ma
DI -
DI -
DI -
DI -
DI -
DI -
DI -
DI -
DI -
DI -
DI -
DI -
Battery Chargers Batt
Cell phone adapter / charger Cell p
Cordless phone charger Cordl
Cordless tool charger �
Cordl
Digital camera charger
Digita
PDA adapter
PDA
MP3 / MD player adapter
MP3
Industrial Charger �
Indus
Communication
Com
24/48 V DC-DC converter � � � � � � �
24/48
Broadband modem
Broad
Router � � � � � � � �
Route
Telecomm line card � � � � � � �
Telec
VoIP phone � � � � � � �
VoIP
PoE Powered Device (PD) � �
PoE P
Computer
Com
PC main power supply
PC m
PC standby power supply
PC st
External media drives � � � � Exter
Laptop adapter � Lapto
LCD monitor / TV � LCD
LCD projector � LCD
Multimedia speaker amplifier � � Multim
Printer � � � � Printe
Scanner � � � � Scan
USB hub � USB
Wireless access point/router � Wirel
Consumer Con
Cable / satellite set-top box � � � Cable
DVD player / recorder � � � DVD
Television standby Telev
Video game � � � � Video
Home Appliance Hom

Major Appliance � Major
Small Appliance � Smal
Home Comfort � Home
General Lighting � Gene
LED lighting LED
Industrial Indu
Lighting � Lighti
Programmable logic controller � � � � � � � Progr
Uninterruptible power supply � Unint
Utility meter Utility
DESIGN IDEAS
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DI -
DI -
DI -
DI -
DI -
DI -
DI -
DI -
DI -
DI -
Battery Chargers
Cell phone adapter / charger � � � �
Cordless tool charger � � � �
Digital camera charger � � �
PDA adapter � � � �
MP3 / MD player adapter � � � �
Industrial Charger � �
Communication
24/48 V DC-DC converter � � �
Broadband modem
Router � � �
Telecomm line card � � �
VoIP phone � � � �
PoE Powered Device (PD) � � �
Computer
External media drives
Laptop adapter
LCD monitor / TV
LCD projector
Multimedia speaker amplifier
Printer
Scanner � � �
USB hub � �
Wireless access point/router �
Consumer
Cable / satellite set-top box
DVD player / recorder
Video game �
Home Appliance
Major Appliance � � � � �
Small Appliance � � � � �
Home Comfort � � � � �
General Lighting � � � � �
LED lighting �
Industrial
Lighting � � � � �
Programmable logic controller � � � � � �
Uninterruptible power supply
Utility meter � � � � �
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DI -
DI -
DI -
DI -
DI -
DI -
DI -
DI -
DI -
DI -
DI -
Po
Re
Va
30
Battery Chargers
Cell phone adapter / charger � � �
Cordless tool charger � � � �
Digital camera charger � � �
PDA adapter � � � �
Communication
24/48 V DC-DC converter
Broadband modem � �
Router
Telecomm line card
VoIP phone
PoE Powered Device (PD)
Computer
External media drives � �
Laptop adapter
LCD monitor / TV
LCD projector
Multimedia speaker amplifier �
Printer �
Scanner � �
USB hub �
Wireless access point/router �
Consumer
Cable / satellite set-top box � � � �
DVD player / recorder � �
Television standby
Video game �
Home Appliance
Major Appliance � �
Small Appliance � �
Home Comfort �
General Lighting
LED lighting � �
Industrial
Lighting
Programmable logic controller � �
Utility meter �
TABLE OF CONTENTS
AN-15 TOPSwitch Power Supply Design Techniques for

EMI and Safety ........................................................................3-1
AN-18 TOPSwitch Flyback Transformer Construction Guide ...........3-34
AN-29 TOPSwitch-GX Flyback Quick Selection Curves ...................3-66
AN-30 TOPSwitch-GX Forward Design Methodology .......................3-74
AN-31 DPA-Switch DC-DC Forward Converter Design Guide ........3-100
AN-32 TOPSwitch-GX Flyback Design Methodology ..................... 3-118
AN-35 LinkSwitch Design Guide .....................................................3-133
AN-37 LinkSwitch-TN Design Guide ...............................................3-152
AN-39 LinkSwitch-LP Flyback Design Guide ..................................3-167
AN-40 LinkSwitch-XT Design Guide ...............................................3-183
AN-41 PeakSwitch Design Guide ...................................................3-196
DI-12 TOPSwitch-GX 16 W Universal Input,

Lead Acid Battery Charger ...................................................3-212
DI-16 TOPSwitch-GX 57 W (Peak) Set-top Box

(Multiple Output) ..................................................................3-214
DI-17 TOPSwitch-GX 17 W PC Standby .......................................3-216
DI-18 LinkSwitch 2.75 W Universal Input,

CV/CC Charger or Adapter ..................................................3-218
DI-19 LinkSwitch 1.5 W Universal Input,

CV/CC Charger or Adapter ..................................................3-220

LCD Monitor External Adapter .............................................3-222
TABLE OF CONTENTS
DI-22 TOPSwitch-GX 70 W, 19 V, Universal Input, External

Laptop Adapter ....................................................................3-224
DI-24 DPA-Switch 30 W DC-DC Converter ...................................3-226
DI-25 DPA-Switch 30 W DC-DC Converter with

Synchronous Rectification ...................................................3-228
DI-26 TOPSwitch-GX 7 W DVB-T Supply (Multiple Output) .........3-230
DI-29 DPA-Switch 25 W Flyback DC-DC Converter ......................3-232
DI-30 TOPSwitch-GX 180 W PC Main SFX Supply ......................3-234
DI-31 DPA-Switch 70 W, 5 V DC-DC Converter with


Audio Amplifier Supply .........................................................3-238
DI-37 DPA-Switch 16.5 W DC-DC Converter with

DI-39 TOPSwitch-GX 17 W (Peak), Universal Input,

DVD Supply with <70 mW No-load (Multiple Output) ..........3-242
DI-40 DPA-Switch 20 W, 2.5 V DC-DC Converter with

DI-41 TOPSwitch-GX 43 W Set-top Box (Multiple Output) ............3-246
DI-43 TOPSwitch-GX 30 W, Universal Input, 12 V Supply

with <250 mW No-load ........................................................3-248
DI-51 DPA-Switch 5 W Flyback DC-DC Converter ........................3-250
DI-52 DPA-Switch 60 W DC-DC Converter with

TABLE OF CONTENTS
DI-53 DPA-Switch 50 W DC-DC Dual Output Converter

with Synchronous Rectification ............................................3-254
DI-55 TOPSwitch-GX 25 W (Peak) DVD Supply

(Multiple Output) ..................................................................3-256
DI-56 DPA-Switch 19.2 W Flyback DC-DC Converter ...................3-258
DI-57 DPA-Switch 60 W Flyback DC-DC Converter ......................3-260
DI-58 LinkSwitch 1.5 W Universal Input

CV/CC Charger or Adapter .................................................3-262
DI-60 LinkSwitch 2.5 W Universal Input, Regulated Charger

or Adapter ............................................................................3-264
DI-67 TOPSwitch-GX 17 W Isolated, Power Factor Corrected,

LED Driver ...........................................................................3-266
DI-69 DPA-Switch 15 W DC-DC Converter with Synchronous

Rectification (Multiple Output) ..............................................3-268
DI-70 DPA-Switch PoE Interface Circuit and 15 W DC-DC

Converter (Multiple Output) .................................................3-270
DI-74 LinkSwitch-TN 1.25 W Universal Input,

Non-Isolated Constant Current LED Driver .........................3-272
DI-75 LinkSwitch 2.5 W Universal Input, Low Cost Regulated

Charger/Adapter ..................................................................3-274
DI-76 LinkSwitch 3.1 W Low Parts Count Power Supply ..............3-276
DI-80 LinkSwitch-TN 0.6 W Universal Input,

Non-Isolated Utility Meter Power Supply .............................3-278
DI-85 LinkSwitch-LP 2 W Charger .................................................3-280

TABLE OF CONTENTS
DI-88 DPA-Switch 6.49 W PoE Class 0-3 Circuit ..........................3-282
DI-89 LinkSwitch-XT 2 W Universal Input, Low Cost Adapter .......3-284
DI-91 TinySwitch-III 12 W Universal Input, CV Adapter.................3-286
DI-92 LinkSwitch-TN 0.5 W Universal Input, LED Driver ...............3-288
DI-93 PeakSwitch 32 W / 81 W Peak General Purpose Supply ....3-290
DI-116 TinySwitch-III 25 W / 28 W Peak Multiple Output Supply .....3-292
DI-117 TinySwitch-III 15 W, 12 V Adapter ........................................3-294
DI-118 TinySwitch-III 4.5 W CV/CC Charger....................................3-296
DI-119 LinkSwitch-LP 1.6 W Linear Adapter Replacement ............3-298
DI-123 TinySwitch-III 9.65 W Dual Output Heating Control ............3-300
DI-124 LinkSwitch-TN 3 W Ultra-wide Input Supply

(57-580 VAC) ......................................................................3-302
DI-128 PeakSwitch 35 W / 75 W Peak Variable Speed

DC Motor Drive ...................................................................3-304
DI-129 PeakSwitch 33 W / 60 W Peak Personal Video

Recorder Power Supply ......................................................3-306
DI-130 TinySwitch-III 18 W Passive PFC LED Lighting

Power Supply ......................................................................3-308
AN-15 APPLICATION NOTE
Application Note AN-15
®
TOPSwitch
Power Supply Design Techniques for EMI
and Safety
120
PI-1622-111695
Offline switching power supplies have high voltage and high
FCCA QP
current switching waveforms that generate Electromagnetic FCCB QP
100
Interference (EMI) in the form of both conducted and radiated
Amplitude (dBµV)
emissions. Consequently, all off-line power supplies must be 80
designed to attenuate or suppress EMI emissions below
commonly acceptable limits. 60
This application note presents design techniques that reduce 40

conducted EMI emissions in TOPSwitch power supplies below
normally specified limits. Properly designed transformers, PC 20
boards, and EMI filters not only reduce conducted EMI emissions
but also suppress radiated EMI emissions and improve EMI 0
0.01 0.1 1 10 100
susceptibility. These techniques can also be used in applications Frequency (MHz)
with DC input voltages such as Telecom and Television Cable
Communication (or Cablecom). Refer to AN-14 and AN-20 for Figure 1. FCC Class A and B Limits (Quasi Peak).
additional information. The following topics will be presented:
120
PI-1623-111695
EN55022A QP
• EMI Specifications for North America, European EN55022A AVG
100
Community, and Germany EN55022B QP
Amplitude (dBµV)
EN55022B AVG
• Measuring Conducted Emissions with a LISN 80
• Peak, Quasi-Peak, and Average Detection Methods
• Safety Principles 60
• EMI Filter Components
• Flyback Power Supply EMI Signature Waveforms 40
• Filter Analysis
20
• Power Cord Resonances
• Transformer Construction Techniques
3
0
• Suppression Techniques 0.01 0.1 1 10 100
• General Purpose TOPSwitch EMI Filters Frequency (MHz)
• EMI Filter PC Layout Issues
Figure 2. EN55022 Class A and B Limits (Average and Quasi Peak).
• Practical Considerations
120
PI-1834-042296
120
PI-1624-111695
Vfg243 QP Vfg243 QP
Vfg1046 QP Vfg46 AVG
100 100
(VDE0871B QP)
Amplitude (dBµV)
Amplitude (dBµV)
80 80
60 60
40 40
20 20
0 0
0.01 0.1 1 10 100 0.01 0.1 1 10 100
Frequency (MHz) Frequency (MHz)
Figure 4. Vfg243 (Quasi Peak) and Vfg46 (Average) Class B
Figure 3. Vfg1046 and Vfg243 Class B Limits (Quasi Peak). Limits.
3-1
Rev. B 04/05
APPLICATION NOTE AN-15
Safety is a vital issue which determines EMI filter component

selection, the transformer reinforced insulation system, and PC
board primary to secondary spacing. In fact, safety is an integral
INPUT OUTPUT
part of the power supply/EMI filter design and is difficult to
discuss as a separate issue. Throughout this application note,
design guidance will also be presented for meeting safety LF
requirements in TOPSwitch power supplies. LINE CC
EMI Specifications CF
+
The applicable EMI specification must be identified for the VSL
RSL
intended product family and target market. In the United States, _
the Federal Communications Commission (FCC) regulates
EMI specifications. Canadian specifications are similar to FCC
specifications. Figure 1 shows the conducted emissions limits
governed by FCC rules, Part 15, subpart J. Note that specification
limits are given only for quasi-peak detection methods. A
recent part 15 amendment allows manufacturers to use the
limits contained in C.I.S.P.R. Publication 22 as an alternative
when testing devices for compliance(1). _
RSN VSN
The member countries of the European Community (EC) have +
established a harmonized program for electromagnetic
compatibility. EN55022 for Information Technology
Equipment is one of the first harmonized documents. EN55022 CF
NEUTRAL CC
together with companion measurement document C.I.S.P.R
Publication 22 set the conducted emission limits shown in
Figure 2 for information technology products marketed to the LF
European Community. In fact, EN55022 limits are the same as
C.I.S.P.R Publication 22 limits. Note that class A and class B
specification limits are given for both average and quasi-peak
PI-1625-111695
detection methods(2) (3).
Figure 5. Line Impedance Stabilization Network (LISN).
3 Figure 3 shows the well-known and most stringent VDE 0871
specification (narrow band limits) for German markets which
has traditionally been the design target. German regulation Vfg filter designed to meet Vfg/243 regulation requirements.
1046/1984 requires Information technology or Electronic Data
Processing Equipment to meet the VDE 0871 class B narrow Measuring Conducted Emissions
band limits from 10 kHz to 30 MHz. Note that specification
limits are given only for quasi-peak detection methods. When Details of testing apparatus and methodology are governed by
marketing products only in Germany, there is a choice between the various EMI regulations, but share the same general concept.
meeting the regulation requirements of Vfg 1046/1984 or the Conducted emissions measurements are made with a Line
new German regulation Vfg 243/1991 (as updated by Vfg 46/ Impedance Stabilization Network (LISN). Figure 5 shows the
1992) which has relaxed limits from 10 kHz to 150 kHz and is effective filter, represented by LF and CF, inside the LISN which
harmonized with EN55022 from 150 kHz to 30 MHz. Vfg243/ passes line frequency currents but forces higher frequency
1991 sets quasi-peak limits and Vfg 46/1992 adds mean or power supply conducted emission currents to flow through
average limits as shown in Figure 4. Figure 3 also shows coupling capacitor CC and sense resistor RS. A spectrum
Vfg243/1991 class B quasi-peak limits to compare with analyzer or EMI receiver reads the current emission signal
VDE0871(4) (5) (6). The EMI filter designed to meet VDE 0871 magnitude as sensed voltages VSL and VSN across RSL and RSN
(per Vfg 1046/1984) will generally be higher cost than the EMI in dBµV.
3-2
Rev. B 04/05
LISN Bonded to
Reference Plane Unit Non-conducting First
Under Test Table Load Pulse
Steady State Peak Current
40 cm 80 cm 80 cm
80 cm AC 0
minimum CURRENT
This Edge Flush Up height
Against Vertical
Reference Plane
Conduction Time
≅ 3 mS
PI-1626-111695
L
Figure 6. Typical Conducted Emissions Precompliance Test Set Up. V+
AC
IN ID
Figure 6 shows a typical conducted emissions pre-compliance CIN
test setup on a wooden table at least 80 cm high constructed with L V-
non-metallic fasteners(7). The unit under test, LISNs, and load
are all placed 40 cm from the edge of the table as shown. Six PI-1627-111695
foot cables are used between the unit under test and both the
LISN on the AC input and the load on the DC output. The LISN Figure 7. Differential Mode Currents Charging Input Capacitor CIN.
and load are each located 80 cm from the unit under test with
excess cable bundled non-inductively. The edge of the table is Peak, Quasi-Peak, and Average
placed flush against a vertical reference plane at least two
meters square. The LISN is bonded to the reference plane with
Detection
a low impedance, high frequency grounding strap or braided Power supplies operating from the 50 or 60 Hz AC mains use
cable. a bridge rectifier and large filter capacitor to create a high
voltage DC bus from the AC input voltage as shown in
In applications where the power supply and load are located in Figure 7. The bridge rectifier conducts input current for only
the same physical package, the cable can be omitted between a short time near the peak of AC mains voltage. Actual
the unit under test and the load. conduction time is typically 3 mS out of effective line frequency
periods of 8.3 to 10 mS which defines an effective “line
For design, investigation and precompliance testing, a spectrum frequency duty cycle” of 30% to 36%. Conducted emission 3
analyzer is highly recommended compared to EMI receivers currents can flow in the AC mains leads (and are sensed by the
which are more expensive and more difficult to use. For LISN) only during the bridge rectifier conduction time. The
conducted and radiated emissions testing, the spectrum analyzer conducted emissions signal is actually applied to the spectrum
should have a frequency range of 10 kHz to 1 Ghz, wide range analyzer or receiver detector input only during bridge diode
of resolution bandwidths (including C.I.S.P.R. specified conduction time which defines a “gating pulse” with pulse
bandwidths of 200 Hz, 9 kHz, 120 kHz), built in quasi-peak repetitive frequency (PRF)(8)(9) equal to the AC mains frequency
detector, video filter bandwidth adjustment capability down to (50 or 60 Hz) and “line frequency duty cycle” just defined. The
3 Hz or below for average measurements, maximum hold for “gating pulse” effect due to bridge rectifier conduction time
peak measurements, and an accurate and temperature causes the measured signal magnitude to change depending on
compensated local oscillator capable of centering a 100 kHz whether peak, quasi-peak, or average detection methods are
signal in the display with insignificant frequency drift. The HP used.
8591EM and Tektronix 2712 (option 12)(8)are two examples of
lower cost spectrum analyzers sufficient for conducted emissions A spectrum analyzer or EMI receiver displays the RMS value
precompliance testing. of the signal(9). For example, a 100 kHz continuous sinusoidal
3-3
Rev. B 04/05
110
voltage when viewed on an oscilloscope may have a peak
PI-1628-111695
voltage of 1 Volt and hence an RMS voltage of 0.707 Volts. The 100
spectrum analyzer (with 50 Ω input) will display a value for this 90
Amplitude (dBµV)
100 kHz signal of 0.707 volts (or 117 dBµV or 10 dBmW) 80
regardless of which detection method is used (peak, quasi-peak, 70
or average) because the signal is continuous, narrow band, and Peak Data
60
not modulated or gated. If the signal was broadband, modulated, 50
gated at a duty cycle, or in some other way not continuous, the
40
displayed RMS value will change with the detection method.
30
The measured display will then be the magnitude of an equivalent Average Data
20
continuous sinusoidal signal with an RMS value equal to the 100 200 300 400 500
RMS content of the LISN signal measured at the output of the Frequency (KHz)
detector stage. Figure 8. Peak Data vs Average Data.
Peak detection is the simplest and fastest method when measuring

conducted emissions. Resolution bandwidth is set to 200 Hz for that happens every hour. A quasi peak-detector (actually a
measurements from 10 kHz to 150 kHz and set to 9 kHz for calibrated, intermediate bandwidth video filter) behaves as a
measurements from 150 kHz to 30 MHz. Sweep times are leaky peak detector that partially discharges between input
relatively low. When displaying emissions in real time with no signal pulses. The lower the pulse repetitive frequency (PRF),
averaging, the peaks are not constant but change in magnitude the greater the dB differential between the peak and quasi-peak
with each measurement sweep due to the bridge conduction measured response (8) (9).
gating pulse effect described above. Most spectrum analyzers
have a “maximum hold” feature which displays the highest Quasi-peak and average detection methods will always give a
peak occurring over many measurement sweeps. The peak lower measured value compared to peak detection. If a peak
detector measures the magnitude of the largest signal occurring detector measurement meets the average or mean specification
during the bridge conduction gating pulse. limit with sufficient margin, additional measurements using
average detection are not necessary. When no average limit is
The average detector is simply a low pass filter with corner specified, if the peak measurement meets the quasi-peak limit
frequency sufficiently below the gating pulse repetitive with sufficient margin, additional measurements using quasi-
frequency or PRF. In typical spectrum analyzers, the video peak detection are not necessary. In general, when testing
filter bandwidth can be reduced to 30 Hz or below to average the TOPSwitch power supplies to the C.I.S.P.R. Publication 22,
signal but the sweep time must be increased for a calibrated EN55022, or Vfg 243/91(and Vfg 46/92) limits, peak measured
measurement. For test purposes, the full conducted emissions data usually meets the quasi-peak limit but, in some areas, may
3 range starting at 10 kHz (or 150 kHz or 450 kHz, depending on have insufficient margin when compared with the average
the regulation) up to 30 MHz should first be examined with a limit. In this case, further measurement is necessary using
peak detection measurement. Peak detected emissions with average detection.
insufficient margin compared to the regulation average limit
should be centered on the spectrum analyzer display with the Safety Principles
lowest possible frequency span per division setting before
reducing video bandwidth and performing the average Safety principles must be examined before proceeding further
measurement sweep(10). Figure 8 shows typical conducted with EMI filter concepts because safety requirements place
emissions from 10 kHz to 500 kHz with both peak detection and several constraints on EMI filter design.
average detection. Note that peak detection picked up an
envelope of high order harmonics from line frequency Virtually all equipment including computers, printers,
rectification in addition to the fundamental and first three televisions, television decoders, video games, battery chargers,
harmonics of the 100 kHz switching frequency. etc., must be safety recognized by meeting the safety standard
for the intended market and carrying the appropriate safety
The quasi-peak detector is designed to indicate the subjective mark. Safety principles are very similar among the various
annoyance level of interference. As an analogy, a soft noise that standards. This application note will focus on the electric shock
happens every second is much more annoying than a loud noise hazard requirements of one popular standard, IEC950(11).
3-4
Rev. B 04/05
The European International Electrotechnical Commission (1.2.8.5): Safety Extra-Low Voltage (SELV) circuit: A
Standard IEC950 entitled “Safety of Information Technology secondary circuit which is so designed and protected that under
Equipment Including Electrical Business Equipment” provides normal and single fault conditions, the voltage between any two
detailed requirements for safe equipment design. Application accessible parts, or between one accessible part and the
of IEC950 is intended to prevent injury or damage due to equipment protective earthing terminal for class I equipment,
hazards including electric shock, energy hazards, fire hazards, does not exceed a safe value.
fire, mechanical and heat hazards, radiation hazards, and
chemical hazards. IEC950 specifies the following definitions (1.2.9.2): Basic Insulation: insulation to provide basic protection
and requirements applicable to TOPSwitch power supplies. against electric shock.
(This is only a partial list of the key requirements targeted
specifically at typical TOPSwitch power supply (1.2.9.3): Supplementary Insulation: Independent insulation
implementations. The appropriate IEC950 section is identified applied in addition to basic insulation in order to ensure protection
by parentheses.) against electric shock in the event of a failure of the basic
insulation.
IEC950 Definitions (Applicable to TOPSwitch Power
Supplies): (1.2.9.4): Double Insulation: Insulation comprising both basic
(Introduction): Electric shock is due to current passing through insulation and supplementary insulation.
the human body. Currents of approximately 1 mA can cause a
reaction in persons of good health and may cause indirect (1.2.9.5): Reinforced Insulation: A single insulation system
danger due to involuntary reaction. Higher currents can have which provides a degree of protection against electric shock
more damaging effects. Voltages up to about 40 V peak, or 60 equivalent to double insulation.
VDC are not generally regarded as dangerous under dry
conditions, but parts which have to be touched or handled (1.2.9.6): Working Voltage: The highest voltage to which the
should be at earth ground potential or properly insulated. insulation under consideration is, or can be, subjected when the
equipment is operating at its rated voltage under conditions of
(1.2.4.1): Class I Equipment: equipment where protection normal use.
against electric shock is achieved by:
(1.2.9.7): Tracking: the progressive formation of conducting
a) using basic insulation, and also paths on the surface of a solid insulating material (such as PC
board or transformer bobbin) due to the combined effects of
b) providing a means of connecting to the protective electric stress and electrolytic contamination on this surface.
earthing conductor in the building wiring those conductive
parts that are otherwise capable of assuming hazardous (1.2.10.1): Creepage Distance: the shortest path between two
voltages if the basic insulation fails. conductive parts, or between a conductive part and the bounding 3
surface of the equipment, measured along the surface of the
(1.2.4.2): Class II Equipment: equipment in which protection insulation. In a TOPSwitch power supply, the most important
against electric shock does not rely on basic insulation only, but creepage distance is between all primary circuits and all
in which additional safety precautions, such as double insulation secondary circuits (typically 5mm to 6 mm).
or reinforced insulation, are provided, there being no provision
for protective earthing or reliance upon installation conditions. (1.2.10.2): Clearance: the shortest distance between two
conductive parts, or between a conductive part and the bounding
(1.2.8.1): Primary Circuit: An internal circuit which is directly surface of the equipment, measured through air.
connected to the external supply mains or other equivalent
source. In a TOPSwitch power supply, this includes the EMI (1.2.11.1): Safety Isolating Transformer: the power transformer
filter, discrete or common mode chokes, bridge rectifier, in which windings supplying SELV circuits are isolated from
transformer primary, TOPSwitch, and any components other windings (such as primary and primary bias windings)
connected to TOPSwitch such as primary bias windings and such that an insulation breakdown either is unlikely or does not
optocoupler output transistors. cause a hazardous condition on SELV windings.
(1.2.8.2): Secondary Circuit: A circuit which has no direct

connection to primary power (except through properly selected
Y-capacitors) and derives its power from a transformer.
3-5
Rev. B 04/05
IEC950 Requirements (Applicable to TOPSwitch Power

Grade of insulation U < 130 VAC 130 < U < 250VAC
Supplies)
(1.4.5): In determining the most unfavorable supply voltage for
Basic, Supplementary 1000 VAC 1500 VAC
a test, the following variables shall be taken into account:
Reinforced (Primary 2000 VAC 3000 VAC
to Secondary)
• multiple rated voltages
• extremes of rated voltage ranges
Table 2. Insulation Electric Strength.
• tolerance on rated voltage as specified by the manufacturer.
If a tolerance is not specified, it shall be taken as +6% and
- 10%. shall be so designed that the risk of fire or electric shock due to
mechanical or electrical overload or failure, or due to abnormal
(1.6.5): Equipment intended to operate directly from the mains operation or careless use, is limited as far as practicable.
supply shall be designed for a minimum supply tolerance of
+6%, -10%. (5.4.6): For components and circuits (other than motors,
transformers, PC board creepage and clearance distances, or
(2.1.10): Equipment shall be so designed that at an external secondary circuit electromechanical components) compliance
point of disconnection of the mains supply, there is no risk of with the abnormal operating and fault condition requirement
electric shock from stored charge on capacitors connected to the (5.4.1) is checked by simulating the following conditions:
mains circuit. Equipment shall be considered to comply if any
capacitor having a rated capacitance exceeding 0.1 uF and - faults in any components in primary circuits (which includes
connected to the external mains circuit, has a means of discharge EMI filter components, bridge rectifier, energy storage
resulting in a time constant not exceeding 1 second for pluggable capacitor, TOPSwitch, and all TOPSwitch connected
equipment type A (non-industrial plugs and socket-outlets). components);
This requirement specifically applies to any EMI filter capacitor
connected directly across the AC mains which could cause a - faults in any components where failure could adversely
shock hazard on the exposed prongs of an unplugged power affect supplementary or reinforced insulation (specifically
cord. failure of Y2-capacitors connected between primary circuits
and secondary circuits);
(5.2.2): Earth Leakage Current: Maximum earth leakage
current must not exceed the limits shown in the following table - additionally, for equipment that does not comply with the
under the most unfavorable (highest) input voltage. For class II requirement of Sub-clauses 4.4.2 (Minimizing the risk of
equipment when output is not connected to earth ground, the ignition) and 4.4.3 (Flammability of materials and
test shall be made on accessible conductive parts, and to metal components), faults in all components;
3 foil with an area not exceeding 10 cm x 20 cm on accessible non-
conductive parts. - faults arising from connection of the most unfavorable load
impedance to terminals and connectors that deliver power
Class Type of Equipment Maximum Leakage Current or signal outputs from the equipment, other than mains
power outlets (for example: connecting a class II equipment
II All 0.25 mA output terminal to earth ground will increase measured
I Hand-held 0.75 mA leakage current).
I Movable 3.50 mA
(other than hand-held) The equipment, circuit diagrams and component specifications
shall be examined to determine those fault conditions that might
Table 1. Maximum Leakage Current. reasonably be expected to occur.
(5.3.2): Electric Strength: The insulation shall be subjected for (In general, components designed for use between primary and
1 minute either to a voltage of substantially sine-wave form secondary circuits, rated for the full electric strength voltage,
having a frequency of 50 Hz or 60 Hz or to a DC voltage equal and carrying the appropriate safety agency approvals are not
to the peak of the prescribed AC test voltage. Test voltage shall subject to the single component fault test because a short circuit
be as specified in the following table for the appropriate grade fault is extremely unlikely. Two component examples are
of insulation and the working voltage U across the insulation: safety rated optocouplers and Y1-capacitors which can be
applied directly between primary and secondary circuits
(5.4.1): Abnormal Operating and Fault Conditions: Equipment operating from AC mains with rated voltages up to 250 VAC.)
3-6
Rev. B 04/05
Typical AC Mains Input Voltage current emissions and increase margin below the specification
limit but may not address size or cost goals of the end product.
Configurations Understanding the basics of EMI filter design and application
allows the designer to implement small, low cost, single section
TOPSwitch power supplies are typically connected to the AC
EMI filters.
mains in either 2-wire or 3-wire configurations. For the purposes
of EMI design presented in this application note, 2-wire and 3-
wire configurations are now defined. 1
Z=
2πfC
2-Wire AC Input ESL
Z= 2πfESL
The TOPSwitch power supply 2-wire AC mains connection
may consist of one line wire and one neutral wire where the AC
mains neutral is eventually connected back to earth ground at a Z Actual C
local electrical panel. The 2-wire connection may also consist
of two separately phased line wires where neither is connected
ESR
directly to earth ground. The power supply SELV output may ESR
or may not be connected directly to earth ground. Ideal
fr
In this application note, the neutral wire will be treated as an f

PI-693-031592
ungrounded AC mains or separately phased line conductor
requiring the same safety considerations as any AC mains line Figure 9. Comparison of Ideal and Real Capacitor Impedance.
conductor. In addition, the power supply SELV output return
Capacitors
will be assumed to connect directly to earth ground which
Proper capacitor selection for EMI filters requires attention to
represents the worst case and most unfavorable connection for
three key parameters: impedance characteristics, voltage ratings,
safety considerations.
and safety specifications.
3-Wire AC Input Figure 9 shows impedance characteristics for ideal and non-
In 3-wire connections, the third wire earth ground wire will be ideal capacitor behavior. An ideal capacitor has an impedance
available for connection to EMI filter components, shields, characteristic that decreases linearly with frequency. A real
chassis, and enclosures. The neutral wire will be treated as an capacitor has parasitic inductance and resistance elements
ungrounded AC mains or separately phased line conductor which cause the impedance to behave quite differently from an
requiring the same safety considerations as any AC mains line ideal capacitor.
conductor. In addition, the power supply SELV output return
will be assumed to connect directly to earth ground which Equivalent series inductance (ESL) creates a capacitor self
3
represents the worst case and most unfavorable connection for resonant frequency fr as shown on the plot. The impedance of
safety considerations. the capacitor at this self-resonant frequency is determined by
equivalent series resistance (ESR). Beyond the self-resonant
EMI Filter Components frequency (fr), the capacitor actually acts like an inductor.
Capacitors with plastic film, combination plastic film/paper, or
EMI filters are actually simple combinations of inductors or ceramic dielectrics usually have the highest self-resonant
chokes and capacitors. Series resistors, which lead to undesirable frequencies and are commonly used in EMI filters.
power dissipation, are not normally used for reducing conducted
emissions. Aluminum Electrolytic Energy Storage Capacitor
Switching power supplies always have a bridge rectifier and
Single-section EMI filters (one stage of common mode and high voltage bulk energy storage aluminum electrolytic capacitor
differential mode attenuation) take the least space and have the to convert AC mains input voltage to high DC bus voltage
lowest cost but require careful attention to details such as circuit (typically 100 to 400 Volts DC) shown as CIN in Figure 7.
parasitics, component parasitics, and layout to meet the
specifications with adequate margin. Multiple-section filters The impedance of this capacitor, which must always be
can also be used because one stage can be designed to overcome minimized, provides the first level of differential mode conducted
the deficiencies of the other. The two section design will reduce emissions filtering.
3-7
Rev. B 04/05
500 the differential mode portion of the EMI filter. X-capacitors are
PI-1629-111695
100 divided into three subclasses:
AXIAL 33µF 12x25
Impedance
10
Subclass Peak Pulse IEC-664 Application Peak Impulse
(Ω)
1
Voltage Installation Voltage VP
In Service Category applied before
0.1 RADIAL 22µF 10x20 Endurance Test
RADIAL 47µF 12x25
0.01
100 1K 10K 100K 1M 10M 40M X1 > 2.5 kV III High Pulse C < 1.0 uF
Frequency (Hz) < 4.0 kV Application UP = 4 kV
Figure 10. 200V Aluminum Electrolytic Capacitor Impedance.
X2 < 2.5 kV II General C < 1.0 uF
Purpose UP = 2.5 kV
500
PI-1630-111695
100
AXIAL 33µF 16x40 X3 < 1.2 kV - General None
Purpose
Impedance
10
(Ω)
1 Table 3. X-Capacitor Subclass.
0.1
RADIAL 10µF 12x20 X2-capacitors are most commonly used in TOPSwitch power
RADIAL 100µF 22x35
supply EMI filters for differential mode suppression. X1-
0.01
capacitors can also be used but cost is higher. X3- capacitors are
100 1K 10K 100K 1M 10M 40M
Frequency (Hz) not normally used.
Figure 11. 400V Aluminum Electrolytic Capacitor Impedance. 100K
PI-1631-111695
10K
1K
Impedance
Figures 10 and 11 show impedance of various 200V and 400V

100 0.033µF
aluminum electrolytic capacitors with radial leads (both leads
(Ω)
(LONG LEADS)
10
exiting one side of the capacitor can) compared with impedance 0.033µF
0.047µF
of a similar capacitor with axial leads (one lead exiting each side 1 0.1µF
0.22µF
of the capacitor can). Approximate dimensions are also shown 0.1 0.47µF
(diameter by length in mm). Radial capacitors have an impedance 0.01
characteristic that stays low up to 10 MHz while the axial 100 1K 10K 100K 1M 10M 40M
3 capacitors become inductive at frequencies as low as 1 MHz. Frequency (Hz)
Radial capacitors should always be used and installed on end to Figure 12. X2-Capacitor Impedance.
minimize lead length and ESL. Axial leaded capacitors should
never be used because the longer total lead length (equal to at X2-capacitors are available from a variety of vendors including
least one can diameter) increases ESL which increases Murata, Roederstein, Panasonic, Rifa, and Siemens. Figure 12
impedance. Note that above 1 MHz, the large axial capacitors shows impedance plots for various sizes of X2-capacitors with
actually have much higher impedance (and will generate higher short leads and one plot for a small X2-capacitor with long
conducted emission currents) than the smaller radial capacitors. leads. Short leads should always be used to minimize impedance
and reduce high frequency conducted emission currents.
EMI Filter Capacitors
Capacitors used in EMI filters are identified by various Y-capacitors are used where capacitor failure could expose
companies as radio interference suppressors, suppression somebody to an electric shock hazard. Y-capacitors are usually
capacitors, or safety recognized capacitors. These capacitors connected from the AC mains or bridge rectifier output to
must meet the European requirement EN 132400 for safety SELV secondaries, chassis, shields, or earth ground. The
which defines two groups, X and Y(12) (13). maximum Y-capacitor value is restricted because each
application has an allowable maximum leakage current (which
X-capacitors are used only in positions where capacitor failure can range from 0.25 mA to 3.5 mA, depending on the AC mains
does not expose anybody to an electric shock hazard. X- connection). There are four EN 132400 specified subclasses of
capacitors are usually connected across the AC mains as part of Y-capacitors:
3-8
Rev. B 04/05
Subclass Type Rated Test Voltages for Peak Impulse radiated emissions specifications. Using short leads and short
of Voltage Quality Approval, Voltage VP PC traces for all Y-capacitor connections is critical to meet both
Insulation (VAC) Periodic and applied before conducted and radiated emissions specifications.
Bridged Lot-by-Lot Testing endurance
10M
PI-1632-111695
Y1 Double Insulation or < 250 V 4000 VAC 8.0 kV
1M
Reinforced Insulation
100K
Y2 Basic Insulation or > 150 V 1500 VAC 5.0kV
Impedance
10K
Supplementary Insulation < 250 V
1K
(Ω)
Y3 Basic Insulation or > 150 V 1500 VAC none 100 4700pF
Supplementary Insulation < 250 V 2200pF
10 1000pF
680pF 4700pF
1 330pF
Y4 Basic Insulation or < 150 V 900 VAC 2.5 kV (LONG LEADS)
Supplementary Insulation 0.1
100 1K 10K 100K 1M 10M 40M
Frequency (Hz)
Table 4. Y-Capacitor Subclass.
Figure 13. Y2-Capacitor Impedance.
In two-wire 230 VAC or universal input applications, a single
In 115 VAC applications, a series combination of two Y2-
Y1-safety capacitor can be directly connected between the AC
safety or two Y4-safety capacitors can be directly connected
mains or bridge rectifier output to the SELV secondary. The
between the AC mains or bridge rectifier to the SELV secondary.
single Y1-capacitor will also meet the electric strength voltage
Y3-safety capacitors are not normally used.
requirement (for 230 VAC mains connected power supplies,
typically 3,000 VAC for one minute). Y1-capacitors with a
Safety specifications such as UL1950, UL544, and IEC950
value of 1000 pF are available from Murata(14) (ACT4K-KD
limit the amount of fault current that can flow when a safety
series, DE1110 E 102M ACT4K-KD), Roederstein(15) (WKP
ground connection has been opened or one component has
series, WKP102MCPE.OK) and Rifa(12) (PME 294 series, PME
failed (Y1-capacitors, because of their construction, are excluded
294RB4100M). In general, Y1-capacitors are not used in 3-
from the failed component test). For example, UL1950 specifies
wire applications.
that information technology equipment with Class I or three
wire input (line, neutral, and earth ground), 240 VAC, 60 Hz
Y2-capacitors do not meet reinforced insulation requirements.
input must have a leakage current no higher than 3.5 mA if earth
In a single component failure safety investigation, one Y2-
ground is opened or one component has failed short which
capacitor may be replaced with a wire jumper to see if an electric
restricts Y-capacitor maximum value below 0.039 µF (or
shock or fire hazard condition will exist. In most 2-wire
39 nF). For class II or two wire input (line, neutral, with no earth
applications, a series combination of two 2200 pF Y2-capacitors
are commonly used between primary and SELV outputs so that
ground), leakage current must be less than 250 µA with one 3
failed component which restricts Y-capacitor size to under
a short circuit failure of one Y2-capacitor creates no safety
0.0028 µF (2.8 nF or 2800 pF) for 240 VAC, 60 Hz input.
hazard. A series connection of two Y2-capacitors is also
Capacitor and input voltage tolerance must also be taken into
necessary to meet the electric strength requirement (for 230
VAC mains connected power supplies, typically 3,000 VAC
for one minute). In 3-wire applications, the Y2-capacitor may
be directly connected between AC mains or bridge rectifier LINE DUT
output and earth ground because the earth ground wire will
safely shunt the fault current created by a shorted Y2-capacitor. Leakage
Y2-capacitors rated at 250 VAC are available from a variety of Currents
vendors including Murata, Roederstein, Panasonic, Rifa, and
Siemens. Figure 13 shows impedance plots for various sizes of
Y2-capacitors with short leads and one plot for a large Y2-
capacitor with long leads. Y-capacitors perform most of the NEUTRAL
GND
high frequency filtering from 10 MHz to 200 MHz. Note that
capacitor resonant frequency is usually 40 MHz or higher
unless artificially reduced with long leads or long PC traces.
Long leads and long PC traces can also cause emission currents, PI-717-032192
though low enough to meet conducted emissions specifications,
to radiate sufficient energy from the power cord to exceed Figure 14. Typical Safety Measurement Setup.
3-9
Rev. B 04/05
account. Figure 14 shows a typical test setup for measuring

leakage current. Single
Layer
Inductors or Chokes Windings
Proper inductor selection for EMI filters requires attention to
three key parameters: effective impedance characteristic, current
rating, and surge current capability.
Figure 15 shows impedance characteristics for ideal and non-

ideal inductor behavior. Ideal inductors have an impedance
characteristic that increases linearly with frequency. Real
inductors have parasitic series resistance RS and parallel
interwinding capacitance (CW). CW creates a resonant frequency
as shown on the plot. Beyond the resonant frequency (fr), the
inductor actually behaves like a capacitor.
TOROIDAL SOLENOIDAL
PI-708-031992
LINE DUT Figure 16. Diffferential Mode Chokes.
Leakage Effective inductance varies with peak differential mode choke

Currents
current flow. Refer again to Figure 7 where the bridge rectifier
and filter creates a high voltage DC bus from the AC line. AC
input current flows only during a small conduction time as
NEUTRAL shown. Peak AC input current during normal operation
GND is relatively high. Differential mode chokes are designed
or selected to limit saturation at peak AC input current.
Figure 17 shows how inductance for a powdered iron toroidal
core varies with number of turns and peak current. To achieve
PI-717-032192 the desired inductance under high peak AC input current, higher
numbers of turns and/or larger choke cores are normally required.
Figure 15. Comparison of Real and Ideal Inductor Impedance.
Typical impedance characteristics for two different differential
Power supplies have bridge rectifier input filters which draw mode chokes are shown in Figure 18. Note that the larger choke
3 line frequency currents with high peak values but relatively resonates at a lower frequency and becomes capacitive. The
narrow widths as previously shown in Figure 7. A discrete filter smaller choke has a higher impedance above 3 MHz due to the
choke usually has a minimal effect on the peak current but must
pass the peak current without significant saturation (which
reduces effective inductance). The discrete choke must also be
rated to safely pass the higher peak value of the first surge of No
current occurring when AC power is initially applied with input Bias
capacitor CIN completely discharged.
Inductance
Differential Mode Chokes Heavy

Differential mode chokes are simply discrete inductors designed Bias
for EMI filters that pass line frequency or DC currents while Current
blocking or filtering high frequency conducted emission currents.
Differential mode chokes are usually wound on low cost
solenoidal cores of either iron powder or ferrite material as
shown in Figure 16. Toroids tend to be significantly higher in # of Turns
PI-709-031992
cost but can also be used. Chokes with single layer windings
have the lowest capacitance and highest resonant frequency. Figure 17. Inductance Under Current Bias.
3-10
Rev. B 04/05
higher self-resonant frequency. Installing the larger choke to mode choke winding. IC1 and IC2 are “common mode” currents
attenuate the fundamental may have the effect of letting through which may or may not be related in magnitude and phase. The
current components above 3 MHz. common mode choke behaves like a large inductor to common
mode currents.
IMPEDANCE vs. FREQUENCY
105
PI-739-032392
104
Impedance (Ω)
103 ID
1 mH IN OUT
102
100 µH ID
101
100 PI-1633-111695
103 104 105 106 107
Frequency (Hz) Figure 19. Ideal Common Mode Choke.
Figure 18. Typical Differential Mode Choke Impedance.

Two low-cost bobbin style common mode chokes simplify
EMI filter design. Figure 20 shows a typical “U-core” style
Differential mode chokes are usually used in EMI filters for common mode choke in which the windings are wound on a
both differential mode and common mode filtering only for the conventional bobbin. Two U-core halves are inserted into the
lowest output power levels (under 5 Watts). At higher power bobbin and secured with clamps. U-core common mode chokes
levels, a properly selected common mode choke will also have are widely available from several companies such as Tokin(16),
differential mode inductance for essentially no additional cost. Tamura(17), Panasonic/Matsushita(18), TDK(19), and Murata(20).
Common Mode Chokes

Common mode chokes are specialized inductors designed 16max.
18max.
specifically for common mode EMI filters. The common mode 3
choke consists of two identical windings wound such that the
magnetic fields caused by differential mode currents cancel.
Figure 19 shows a toroidal implementation which is good for
20max.
illustration purposes but (as will be seen shortly) is not the best
choice for low-cost and practical EMI filter implementations.
Figure 19 shows three current components ID, IC1, and IC2. ID is
a differential mode current (shown also in Figure 7) which 0.7
4min.
circulates by starting at the AC mains source, flows through one

common mode choke winding towards the power supply, flows
through one bridge rectifier diode, charges the high voltage 10±0.5 PI-1634-111695
energy storage capacitor CIN, flows back through another bridge
rectifier diode, and then flows back towards the source through Figure 20. U Core Common Mode Choke (All dimension in mm).
the other common mode choke winding. The magnetic fields
within the core due to the circulating differential current ID
cancel perfectly because of dot polarity. Note that the “start” of Figure 21 shows a newer common mode choke design with a
both windings enters the core on the same side and the “finish” “spool” style two-piece bobbin. The two-piece bobbin is
of both windings leaves the core on the other side. Common snapped together around a one-piece ungapped core. A sprocket
mode chokes behave like short circuits for circulating differential on the bobbin engages a gear on a winding machine to spool the
mode currents such as ID which flow in through one common wire onto the bobbin. Spool style common mode chokes are
mode choke winding and flow out through the other common available from Panasonic/Matsushita(18) and Tokin(16).
3-11
Rev. B 04/05
Common mode inductance of each winding is the measured

inductance of one winding with the other winding open circuited.
Differential mode inductance of each winding is equal to half
21.5±1.0
the measured inductance of one winding with the other winding
short circuited.
Common mode impedance is shown for the U-core style in

Figure 23 and the spool style in Figure 24. Also shown is
common mode impedance for a typical toroidal implementation.
0.8
3.5±0.5
Note that the toroidal common mode impedance is generally
13.0±0.5 10.0±0.5 lower than both the U-core and spool style common mode
chokes.
21.0±1.0 16.0±1.0
PI-1635-111695 1M
PI-1637-111695
33 mH
100K 18 mH
Figure 21. Spool Wound Common Mode Choke (All dimension in 10 mH
5.6 mH
mm). 10K
Impedance
One very important advantage to the bobbin style common 1K
(Ω)
mode choke is an “inherent differential mode choke” due to 100
parasitic leakage inductance which usually eliminates any need
for additional discrete differential mode chokes. Figure 22 10
Toroid
1mH
shows the effective common mode choke schematic consisting 1
1K 10K 100K 1M 10M 40M
of a common mode inductance in series with an effective
differential mode leakage inductance. Unlike most other Frequency (Hz)
magnetic components, leakage inductance in a common mode
Figure 23. U Core Common Mode Choke (Common Mode
choke is a desirable parasitic effect which provides balanced Impedance).
differential mode filtering for no additional component cost.
The common mode choke is modeled by a common mode 1M
PI-1638-111695
33 mH
inductance in series with a differential mode inductance. 22 mH
100K 10 mH
3.3 mH
2.2 mH
Impedance
10K 0.82 mH
(Ω)
1K
Common Mode 100

3 Inductance 10
Toroid
1mH
1
1K 10K 100K 1M 10M 40M
Frequency (Hz)
Input Output Figure 24. Spool Wound Common Mode Choke (Common Mode
Impedance).
Differential mode impedance is shown for the U-core style in

Figure 25 and the spool style in Figure 26. Also shown is
Differential Mode differential mode impedance for a typical toroidal
"Leakage" implementation. Note that the toroidal differential mode
Inductance impedance is quite a bit lower than both the U-core and spool
style common mode choke. With toroidal common mode
chokes, additional differential mode chokes are usually required.
PI-1636-111695
For these reasons, toroidal common mode chokes are not
recommended except for the high frequency, supplemental
Figure 22. Effective Common Mode Choke Schematic. torodial common mode choke described below.
3-12
Rev. B 04/05
500K together in parallel and wound as a pair for typically 3 to 5 turns.
PI-1639-111695
33 mH
100K 18 mH
10 mH
The toroidal core should be ferrite and “lossy” at high frequency
10K 5.6 mH such as Fair-Rite 75 material. Fair-Rite toroid part number
5975001101 (with 0.5 inch OD x 0.32 inch ID x 0.25 inch
Impedance
1K
thickness) is suitable for most applications(21). This high
(Ω)
100
Toroid frequency common mode choke is usually located between
1mH
10 power entry and the rest of the power supply EMI filter. This
1
common mode choke technique can also be used on power
supply output wires.
0.1
1K 10K 100K 1M 10M 40M
Frequency (Hz) INSULATED WIRES
Figure 25. U-Core Wound Common Mode Choke (Differential
Mode Impedance). INPUT
500K
PI-1640-111695
33 mH
100K 22 mH
10 mH
FERRITE
10K 3.3 mH TOROID
2.2 mH
0.82 mH
Impedance
1K
(Ω)
100
Toroid OUTPUT
1mH
10
1 HIGH FREQUENCY COMMON MODE CHOKE

PI-1641-111695
0.1
1K 10K 100K 1M 10M 40M
Frequency (Hz) Figure 27. High Frequency Common Mode Choke.
Figure 26. Spool Wound Common Mode Choke (Differential Mode

Impedance).
Flyback Power Supply EMI Signature
Flyback power supplies have a distinctive EMI signature caused
Bobbin style common mode chokes can have either one or two by superposition of several waveforms shown in Figure 28. The
sections in each winding. One section per winding is lowest transformer primary current IPRI, TOPSwitch Drain voltage
cost but two sections per winding splits the winding capacitance VDrain, diode voltage VDiode, and transformer secondary current
in half to increase resonant frequency and effective bandwidth. ISEC waveforms each generate emission currents which may
The U-core common mode choke shown in Figure 20 has one exceed the desired EMI specification limits without proper 3
section per winding while the spool style common mode choke EMI design technique.
shown in Figure 21 has two sections per winding. Figure 23
shows that the single section U-core style common mode Primary Current Waveform
impedance is lower and resonant frequency is lower with Primary current IPRI begins to flow when TOPSwitch turns on.
sharper peaking compared with the two section spool style Transformer primary current ramps to a peak value determined
common mode impedance shown in Figure 24. Two sections by input voltage, primary inductance, switching frequency, and
per winding reduce capacitance to improve common mode duty cycle. This trapezoidal (or triangular) current waveform
impedance at high frequency. is characterized in the frequency domain by a spectrum with a
fundamental at the switching frequency and harmonics
The common mode choke must also survive the surge current determined by the relative squareness of the waveform and
occurring when voltage is first applied to the power supply as causes primarily differential mode emission currents to circulate
described earlier, as well as operate at the steady-state RMS between the AC mains and the power supply input. This current
input current. waveform can also create common mode emissions due to
radiated magnetic fields if the current path defined by the PC
For reducing high frequency common mode conducted emissions board layout encircles a large physical area.
in the 10 MHz to 200 MHz range, a simple common mode choke
using a small ferrite toroid(21) and insulated wire can be wound TOPSwitch Drain-Source Voltage Waveform
as shown in Figure 27 and used in addition to one of the bobbin The Drain-Source voltage waveform VDrain is characterized by
style common mode chokes. Both wires have thick, safety high dv/dt transitions. Parasitic circuit elements (leakage
insulated wires with different colors. The wires are held inductance, TOPSwitch output capacitance, and transformer
3-13
Rev. B 04/05
capacitance) cause additional voltage peaking and ringing at cause additional voltage peaking and ringing at frequencies
frequencies typically between 3 MHz and 12 MHz. The typically between 20 MHz and 30 MHz. The diode voltage
TOPSwitch Drain, transformer primary, and Drain clamping waveform will drive displacement currents to earth ground
components connected to the Drain node will drive displacement through transformer capacitance or stray capacitance. The
currents to earth ground through transformer capacitance or displacement currents generated by the diode voltage waveform
stray capacitance. This displacement current returns cause spectral energy in the form of common mode emission
“backwards” through the line and neutral conductors back to currents to be concentrated at the switching frequency and
the TOPSwitch Drain driving node as a common mode emission 20 MHz to 30 MHz resonant frequency (f2) of the indicated
current. The displacement currents generated by the drain ringing voltage waveform.
voltage waveform cause spectral energy in the form of a
common mode conducted emission currents to be concentrated Secondary Current Waveform
at the switching frequency and 3 MHz to 12 MHz resonant Secondary current ISEC begins to flow as soon as TOPSwitch
frequency (f1) of the indicated ringing voltage waveform. turns off. Current starts at a peak value and decreases linearly
at a rate determined by secondary inductance and output voltage.
Common mode emission currents will be lower with TOPSwitch This trapezoidal (or triangular) current waveform is characterized
when compared with discrete MOSFET implementations in the frequency domain by a spectrum with a fundamental at
because TOPSwitch has a controlled turn on gate driver to the switching frequency and harmonics determined by the
reduce dv/dt. Common mode emissions currents are also lower relative squareness of the waveform. Additional ringing
because the TOPSwitch TO-220 tab is connected to the relatively superimposed on the waveform is related to the drain source
quiet source pin while a discrete MOSFET has the noisy drain voltage VDrain waveform previously discussed. This composite
“transmitting” node connected directly to the tab (and heat sink) current waveform can cause significant magnetic fields to
“broadcasting antenna”. radiate if the current path defined by the PC board layout
encircles a large physical area. Spectral energy in the form of
Diode Voltage Waveform a common mode emission current would be concentrated at the
The diode voltage waveform VDIODE is also characterized by fast switching frequency and 3 MHz to 12 MHz resonant frequency
voltage changes and fast rise and fall times. Parasitic circuit (f1) of the indicated ringing current waveform.
elements (transformer leakage inductance and diode capacitance)
ISEC
IPRI
IPRI
+
3 VDIODE C LOAD
- VDRAIN
f1
VIN
ISEC
+
V VDIODE
- DRAIN
f2
PI-1724-121895
Figure 28. Examples of Typical Flyback Power Supply Waveforms Causing EMI.
3-14
Rev. B 04/05
LISN ISENSE I2 IPRI

RESISTORS
LD +
IPRI I4 LD I1
VSL RSL +
-
VIN CD ESR
CIN +
-
CD
VSN RSN I4 I1
- LD
+
ESR ISENSE I2 IPRI
LD -
IPRI
ACTUAL IPRI MODEL

PI-1642-111695
Figure 29. Circuit Origin for Differential Mode Emissions.
Suppression Techniques conducting current and is replaced with a short circuit. The AC
source impedance is modeled by the effective series combination
Controlling EMI requires attention to the following areas. of the 50 Ω LISN sense resistors RSL and RSN. Differential mode
filtering is performed by the LC filter consisting of differential
• Differential mode filtering mode capacitor CD and two identical differential mode chokes
LD. This model is valid up to roughly 1 MHz.
• Common mode filtering
The primary current switching frequency fundamental and
• Power cord damping harmonic components IPRI(n) must be estimated, measured, or
derived by simulation. Note that measured harmonic components
• Transformer construction are given in RMS but calculated or simulated components are
given in peak values and must be converted to RMS. A typical
Differential mode Filter Analysis
Differential mode conducted emissions are caused by currents
harmonics envelope is shown in Figure 30 as a function of
frequency.
3
circulating between the power supply and AC mains input
which means that a differential current which flows into the
PI-1738010496
power supply through the Line input wire will flow out of the
power supply through the Neutral input wire.
Fourier Coefficient
Most differential mode conducted emissions are caused by the

fundamental and harmonics of the triangular or trapezoidal
TOPSwitch Drain current waveform. During EMI testing,
differential mode currents generate test voltages equal in
magnitude and opposite in phase across Line LISN sense
resistor RSL and Neutral LISN sense resistor RSN.
Differential mode analysis starts by replacing the actual circuitry

with an equivalent model as shown in Figure 29. The primary
current is modeled by current source IPRI. The effective
1 2 3 5 7 ...
impedance of energy storage capacitor C1 over the frequency
Harmonic Number
range of 100 kHz to 1 MHz is modeled by the Equivalent Series
Resistance or ESR. The bridge rectifier is assumed to be Figure 30. Envelope of Typical Primary Current Fourier Spectrum.
3-15
Rev. B 04/05
At the fundamental and harmonics of switching frequency fS, VSN (s) 1 1

equivalent series resistance (ESR) of bulk input capacitor CIN is H( s ) = = ×
VPRI (s) 2
much lower impedance compared with the LD differential mode
chokes. Primary current IPRI flows almost completely through
(2 × L D × CD × s
2
) + ⎛⎜⎝ LR D
S
⎞
× s⎟ + 1
⎠
bulk energy storage capacitor CIN which creates an effective
trapezoidal (or triangular) differential mode voltage source 1 1
proportional to ESR. Differential mode chokes and the ≈ ×
2
differential mode capacitor form a simple low pass filter to
attenuate the effective voltage source to a level below the
(2 × L D × CD × s
2
) + ⎛⎜⎝ LR
D
S
⎞
× s⎟
⎠
desired specification. Figure 31 shows the final simplified
model where the RMS source voltage for each nth current 1
harmonic (given in peak value) is given by:
1 CD × s
VSN ( s) = VPRI ( s) × × × RS
1 2 × LD × s (2 × R ) + 1
VPRI (n) = ESR × IPRI (n) × S
CD × s
2
(RMS) (Peak)
For EMI filter design, only the magnitude of the most important
frequency components are examined which allows simple
magnitude expressions in terms of the harmonic integer n to be
LD IL(n) used (rather than the complex variable s). Filter design begins
by identifying a target sense voltage VSNdBµV(n) below the
specification limits at the appropriate nth harmonic frequency.
RS For FCC testing, the specification begins at 450 kHz with the fifth
+ harmonic (n = 5) while excluding TOPSwitch 100 kHz
CD VPRI(n) fundamental (n = 1) and second through fourth harmonic
_ frequencies (n = 2, 3, 4). For European test limits, the 100 kHz
fundamental (n = 1) and the second harmonic at 200 kHz
RS
(n = 2) should be examined because the limit changes
LD significantly at 150 kHz. As an example and referring to
European EN55022 average limit for class B (Figure 2), the
PI-1643-111695 average limit value is 74 dBµV at 100 kHz (n=1) and 53.5 dBµV
at 200 khz (n=2) while the quasi-peak limit values are 10 dB
Figure 31. Simplified Differential Mode Model. higher. In most low frequency conducted emission
3 measurements, the measured quasi-peak value is slightly less
(1 dB to 3 dB) than the peak value. The average value, however,
can be 12 dB below the peak value which means that if the filter
Attenuation is determined by the differential between the is designed to meet the average limit, the quasi-peak limit will
magnitude of the effective voltage source in dBµV and the also be met and with greater margin. In this example and for
desired conducted emissions specification. The voltage transfer 12 dB margin overall, the peak value should be designed to touch
function H(s) is given in terms of LD, CD, and RS. the average limit and average detection will provide the
remaining 12 dB attenuation. The target sense voltages are
At high levels of attenuation normally required at the switching therefore equal to the average limit or 74 dBµV at 100 kHz
frequency, the denominator of H(s) is dominated by the frequency (VSNdBµV(1)) and 53.5 dBµV at 200 kHz (VSNdBµV(2)). VSNdBµV(n)
dependent terms and can be simplified as shown. Simple is converted from dBµV to an absolute value sense voltage
algebra reveals a very useful frequency domain formula VSN(n).
consisting of the product of three separate terms. The first term
converts the effective ESR voltage source VPRI(s) back into
VSNdBµV (n)
differential inductor current ID(s), the second term splits the VSN (n) = 1.e −6 × 10
current between differential mode capacitor CD and LISN sense 20
resistors, and the third term senses the LISN current component
to create a voltage to be measured with a detector or receiver to VSN(1) is 5.01 mVRMS and VSN(2) is 473 µVRMS. Sense voltage
compare with limits in dBµV. This is a general result with VSN(n) is then converted into an RMS current magnitude IL(n)
equivalent ESR voltage source VPRI(n) of each nth harmonic flowing through each differential mode inductor LD.
shown (temporarily) in the frequency domain as VPRI(s) which
is a function of the complex frequency variable s.
3-16
Rev. B 04/05
1 LD
I L (n) = VSN (n) × + ( 4 × π × n × fs × CD )2
Rs2
CW ESL
RS
RMS differential current IL(1) is 638µA and IL(2) is 119µA. CD
The target differential inductance LD can now be calculated. CIN
CW
ESL
VPRI (n) RS ESR
LD =
I L (n) × 4 × π × n × fs
LD PI-1860-050796
The ST202A power supply operating from 115 VAC and

Figure 32. High Frequency Model of the Differential Mode Filter.
delivering 15 Watts is found to operate in the discontinuous
mode with a triangular drain current waveform. Peak Drain
current IP is 0.8 A and duty cycle is 0.3. C6 (0.1 µF) is
differential capacitor CD. ESR of input capacitor C1 is 0.375 Ω. harmonics of the trapezoidal (or triangular) TOPSwitch Drain
From simulation, calculation, or measurement with the power current waveform are also decreasing above 1 MHz, which
supply connected to the LISN but without an EMI filter, the tends to offset the degradation in filter performance. Above
equivalent source voltage fundamental VPRI(1) is 59.3 mVRMS 1 MHz, current emissions which exceed the desired specification
and second harmonic VPRI(2) is 43.0 mVRMS. Differential are usually common mode emissions caused by either ringing
inductance LD is found to be 74µH in each leg for attenuation of waveforms identified earlier or resonances caused by parasitic
the fundamental but the second harmonic requires a higher components themselves.
inductance value of 144µH in each leg to achieve the desired
attenuation because the EN55022 specification is more stringent Physical component layout becomes increasingly critical above
at 200 kHz. The higher inductance value is used in the design. 1 MHz. Improper layout can lead to increased capacitor ESL.
Note also that different combinations of L and C are possible but It is also possible for noise voltages or currents to couple around
the LC product will remain the same. Note also that, in common the EMI filter directly into the mains.
mode chokes, total measured differential inductance is twice
the value calculated for each leg (288µH in this example). Common Mode Filter Analysis
Common mode conducted emissions are caused by common
Peak load current normally limits the size of discrete chokes mode currents that do not circulate between the AC mains and
to between 100µH and 1 mH (especially in mains applications power supply input. Balanced common mode currents flow
with peak-charging capacitive input filters). Practical discrete
chokes are cost effective only at the lower output power levels
simultaneously in power supply line and neutral input wires
such that common mode line current is equal in magnitude and
3
(5 Watts and below). Single discrete chokes attenuate the in phase with common mode neutral current. Unbalanced
differential mode but have little effect on common mode common mode currents flow in either power supply line or
emission currents. These limitations for discrete, differential neutral input wires separately. Common mode conducted
mode chokes can be overcome by selecting a common mode emissions are caused by TOPSwitch Drain Voltage VDRAIN and
choke with parasitic leakage or differential inductance equal to output Diode Voltage VDIODE as shown in Figure 33.
or greater than the differential choke inductance value calculated
above. (Note: with a common mode choke, measure inductance TOPSwitch Drain voltage VDRAIN drives displacement current
of one winding with the other winding shorted for total leakage through various stray parasitic capacitance terms. CS1 is stray
or differential inductance. The effective differential inductance TOPSwitch Drain capacitance to earth ground. COSS is
in each leg is half the measured value.) TOPSwitch output capacitance. CBD1 through CBD4 are the
effective capacitance terms across each bridge diode. CAC is the
Filter effectiveness decreases as parasitic elements of the filter capacitive coupling across the AC mains input (which is very
components themselves become significant. The effective low when testing with LISNs). Note that secondary is shown
circuit model above 1 MHz is shown in Figure 32. Note the connected directly to earth ground. Transformer capacitance is
additional ESL terms in both energy storage capacitor CIN and distributed but can be modeled with the following six discrete
differential capacitor CD. Note also the shunt winding capacitance terms:
capacitance CW across each differential mode filter choke LD.
As the frequency increases, the parasitic components begin to CW1: Winding capacitance from “noisy” or switching side
dominate, reducing filter effectiveness. Fortunately, the of the transformer primary to “noisy” side of the secondary.
3-17
Rev. B 04/05
CW3
CW5 VDIODE
CBD1 CBD2
V+
ESL CW6
VAC CAC VDRAIN
CIN + CW4
C
W1
-
CW2
CBD3 ESR
CBD4 COSS
V-
CS2
CS1
PI-1644-111695
Figure 33. Circuit Origin for Common Mode Emissions.
CW2: Winding capacitance from “noisy” or switching side common mode emission currents as follows:
of the transformer primary to “quiet” side of the secondary.
ICS1: Splits into earth ground component and secondary
CW3: Winding capacitance from “quiet” side of the component. Secondary current component returns to the
transformer primary to the “noisy” or switching side of the TOPSwitch Drain through transformer capacitance. Earth
secondary. ground component returns up from ground into the neutral
wire (and is sensed by the LISN), AC couples into the Line
wire (and is sensed by the LISN), flows back through bridge
CW4: Winding capacitance from “quiet” side of the diodes (either superimposing on line frequency current
3 transformer primary to the “quiet” side of the secondary. during bridge diode conduction or through effective bridge
(This is actually a “good” stray capacitance term which is diode capacitance when diodes are not conducting), to V+
usually augmented with an additional, Y-capacitor to return and V- bus wires, and returns to the TOPSwitch Drain pin
displacement currents back to the driving source). through CW5 and COSS.
CW5: Winding capacitance across the primary. ICW1: Splits between CW3 returning to primary, CS2 to
earth ground, and CW6. Splits again between CW2 and earth
CW6: Winding capacitance across the secondary (CW5 and ground. Earth ground components returns through neutral
CW6 combine to cause a transformer resonant frequency of and line wires (as explained above) and is sensed by the
400 kHz to 2 MHz above which each winding impedance is LISN.
capacitive rather than inductive).
ICW2: Splits between CW6 and earth ground. Earth ground
The TOPSwitch Drain node directly drives displacement current component returns through neutral and line wires (as
into each of the following stray capacitance terms: CS1, CW1, explained above) and is sensed by the LISN.
CW2, COSS, and CW5. Each displacement current (ICS1, ICW1, ICW2,
ICOSS, and ICW5) must eventually return to the driving node ICOSS: Splits between CIN (note that CIN Equivalent Series
(TOPSwitch Drain pin). Each current splits many times but Inductance or ESL will choke off high frequencies) andV-.
some fraction of each displacement current may flow through V- component flows out the bridge rectifier, down through
the power supply AC input conductors and be measured as line and neutral wires (and is sensed by the LISN) to earth
3-18
Rev. B 04/05
ground, up to secondary, and couples back to TOPSwitch The ferrite bead or toroid(21) should have an effective impedance
through transformer winding capacitance. of 100 Ω in the 15 to 25 MHz range. The bead is placed over
the safety ground wire between the enclosure power entry
ICW5: Splits between CIN (with ESL) and V+. V+ component connector and the internal safety ground attachment point of the
flows out the bridge rectifier, down through line and neutral enclosure. The toroid is installed in similar fashion but can
wires (and is sensed by the LISN) to earth ground, up to accommodate up to 5 or 6 turns of the insulated safety ground
secondary, and couples back to TOPSwitch through wire.
transformer winding capacitance.
Transformer Construction
Superposition of all these different displacement currents will
lead to some cancellation but there will always be “leftover” Flyback transformers use gapped ferrite cores which may have
high frequency current components measured as common fringing fields as shown in Figure 34. Gaps should be confined
mode conduction emissions. The asymmetries in various to the center leg of either one or both core halves so that the
parasitic capacitance terms also explain how common mode fringing field can be effectively shielded by the windings. End
emission currents can become “unbalanced” creating net current gaps “leak” magnetic flux due to the fringing field which can
flowing only in the line or neutral wire. A similar analysis can produce common mode emissions.
be performed using the output rectifier anode as the driving
point voltage source. For obvious reasons, common mode
emission currents are best measured because analysis is quite
difficult.
Common mode filters require relatively high values of inductance

because safety standards restrict common mode Y-capacitor END GAP
size to limit leakage current as previously discussed. Common WITH NO
mode chokes between 10 mH and 33 mH are used in most FRINGING END GAP
applications because inductance normally required is unaffected FIELD
by the circulating differential mode current. Discrete chokes
can also be used in some low power applications if the peak
current is taken into account and a discrete choke is placed in
each leg for balanced high frequency impedance. PI-743-032392
Physical component layout becomes increasingly critical above Figure 34. End Gap Magnetic Flux Leakage.
1 MHz. Improper layout can lead to increased capacitor ESL.
It is also possible for noise voltages in close proximity to the Proper transformer construction techniques are necessary for 3
EMI filter to couple around the filter directly into the mains. reducing common mode emissions. Figure 35 shows a typical
Common mode capacitors must have extremely short traces insulated wire wound transformer cross section. The transformer
connecting directly to the transformer pins and to each other as primary connects between the relatively quiet high voltage DC
well. bus and the noisy TOPSwitch Drain pin (which has the high
voltage switching waveform). When the primary is wound with
Power Cord Damping two layers, the primary half with the dot mark is connected to
TOPSwitch which is then buried or shielded under the primary
Applications with 3-wire power cords require special attention. half connected to the high voltage DC bus as shown. One layer
A six foot power cord can be modeled as a transmission line of 2 mil tape separates the two primary halves to reduce
with distributed inductance and capacitance, characteristic capacitance and high frequency ringing. Another layer of tape
impedance of approximately 100 Ω, and little damping which separates the primary winding from the insulated wire wound
leads to a sharp, well defined resonance, typically between 15 secondary. The combination of tape and insulation thickness
and 25 MHz. This resonance can amplify existing common reduces capacitance between primary and secondary which
mode emission currents to levels in excess of the desired limit. reduces common mode emission currents. One more layer of
A small, lossy ferrite bead or toroid placed over the earth ground tape separates the secondary from the primary referenced bias
lead wire reduces the resonant peak by adding series damping. winding.
3-19
Rev. B 04/05
connected to each core half (manganese zinc ferrite normally

used in 100 kHz flyback transformers is conductive) and the foil
ends are electrically connected to create a shorted turn. The flux
BIAS
SECONDARY
} TAPE
band can usually be left floating without making additional
bobbin changes to meet reinforced insulation requirements for
safety. The flux band (and core) may also be connected back to
TAPE { (INSULATED) primary or to secondary but bobbin construction must be
examined to ensure creepage distance is sufficient to meet
reinforced insulation requirements for safety.
PRIMARY
PI-1646-111695
Figure 35. Insulated Wire Wound Transformer Cross Section. TRANSFORMER FLUX BAND
Figure 36 shows a typical margin wound transformer cross COPPER
section. Each winding is placed between symmetric margins as FOIL
shown while the safety insulation extends beyond the margins
up to the walls of the bobbin flange. The split primary STRAP
construction shown reduces leakage inductance in higher power
applications. The primary half connected to TOPSwitch is the
first layer followed by one wrap of 2 mil polyester film tape for
basic insulation. The bias winding is wound next in a single
layer. The bias winding is usually just a few turns but wound
using up to three parallel wires to cover more of the bobbin
width and effectively shield the noisy TOPSwitch Drain
connected primary half. Three wraps of 2 mil polyester film PI-1648-111695
tape (3M 1298 or equivalent UL recognized tape) provide the Figure 37. Transformer Flux Band.
necessary reinforced insulation for safety as well as reducing
capacitance between primary and secondary to minimize
common mode emission currents. Secondary is now wound
In most TOPSwitch power supplies, a transformer shield is not
between margins followed again by three wraps of 2 mil
necessary because TOPSwitch has controlled turn on which
polyester film tape for reinforced insulation. The second half
limits high voltage dv/dt and reduces common mode emission
of the primary is wound followed by three wraps of 2 mil
3 polyester film tape as final insulation.
currents. For those few applications where further reduction in
common mode emission currents is desired, Figure 38 shows
proper shield placement within the transformer. The shield
intercepts interwinding capacitive displacement currents and
returns them to the primary circuitry. Figure 38 shows the
SECOND PRIMARY HALF shield connected to V+ but the shield can also be connected to
REINFORCED INSULATION V- if more convenient for construction or layout reasons. Note
MARGINS
SECONDARY (BOTH that safety insulation or creepage distance is required between
SIDES)
REINFORCED INSULATION the primary connected shield and SELV secondary outputs.
BIAS The foil shield width is selected to fit between primary safety
FIRST PRIMARY HALF
margins. Length is precut for one full turn with slight overlap
PI-1647-111695
at the ends. The termination lead wire is soldered to the copper
foil shield in the center (equidistant from each end). Tape
Figure 36. Margin Wound Transformer Cross Section.
insulation is usually applied to the copper foil shield before
placing on the transformer. The ends must be insulated such
In some applications, a copper foil “flux band” over the outside that the foil shield does not form a shorted turn inside the
of the completed transformer as shown in Figure 37 may reduce transformer (compared with the external “belly band” described
some common mode emissions. The copper foil wraps one earlier which has a shorted turn but is physically located outside
complete turn over the exposed (but insulated) windings and the transformer).
each core end gap. Foil width is cut to fit between bobbin
flanges while maintaining required creepage distance for Refer to AN-18 for more information on transformer
reinforced insulation. For best effect, the foil is electrically construction.
3-20
Rev. B 04/05
TRANSFORMER SHIELD PLACEMENT
Insulated Wire Transformer Margin Transformer
SECOND PRIMARY HALF
SHIELD
SECONDARY
BIAS
PRIMARY
} TAPE
SECONDARY
BIAS
SHIELD
FIRST PRIMARY HALF

MARGINS
PI-1649-111695
Figure 38. Transformer Shield Placement.
General Purpose TOPSwitch

EMI Filters
attenuate differential mode emission currents. C7 (Y1-safety
2-Wire AC Input capacitor) and the common mode inductance of common mode
A typical TOPSwitch power supply and EMI filter for 2 wire AC choke L2 attenuate common mode emission currents. Note that
input applications is shown in Figure 39. X-capacitor C6 and C7 can be replaced by two series connected Y2-safety capacitors,
the differential mode inductance of common mode choke L2 each with twice the value shown.
D2 L1
T1 UG8BT 3.3 µH
8 7.5 V
1 R1
39 Ω
R2
68 Ω
VR1
P6KE200
C2
680 µF
C3
120 µF
3
25 V 25 V
U2
D1 NEC2501-H
VR2
UF4005
1N5995B
BR1 2 6.2 V
C1 7
400 V RTN
L2 33 µF
22 mH 400 V D3
1N4148
3
C6 C5
0.1 µF 4
47µF
X2
DRAIN
F1 SOURCE
C7
3.15 A CONTROL
1.0 nF
L Y1
U1 C4
TOP202YAI 0.1 µF
N
J1
PI-1650-111695
Figure 39. Typical 2-Wire TOPSwitch Power Supply and EMI Filter.
3-21
Rev. B 04/05
3-Wire AC Input mode emission currents. C7 (Y1-safety capacitor), the common

A typical EMI filter for 3 wire AC input applications is shown mode inductance of common mode choke L2, and small, lossy
in Figure 40. X-capacitor C6 and the differential mode ferrite toroid L3 attenuate common mode emission currents(21).
inductance of common mode choke L2 attenuate differential L3 also damps power cord resonances as previously described.
D2 L1
T1 UG8BT 3.3 µH
8 7.5 V
V+ 1 R1
39 Ω
R2
68 Ω
VR1 C2 C3
P6KE200 680 µF 120 µF
25 V 25 V
U2
D1 NEC2501-H
VR2
UF4005
1N5995B
BR1 2 6.2 V
C1 7
400 V RTN
L2 33 µF
22 mH 400 V D3
1N4148
V- 3 C8
0.1 nF
C6 C5
0.1 µF 4
47µF
X2
DRAIN
F1 SOURCE
C7
3.15 A CONTROL
1.0 nF
L Y2
U1 C4
TOP202YAI 0.1 µF
N
J1 L3
3 PI-1651-111695
Figure 40. Typical 3-Wire TOPSwitch Power Supply and EMI Filter.
3-22
Rev. B 04/05
Enhanced EMI filter design for Video Applications and decoders). These techniques can also reduce radiated emissions
Reduced Radiated Emissions by keeping high frequency conducted emission currents (30
Figures 41 and 42 show typical EMI filters for 2-wire input MHz to 200 MHz) out of the power cable which may act like an
video applications (such as television set-top cable and satellite antennae and broadcast radiated emissions.
D2 L1
T1 UG8BT 3.3 µH
8 7.5 V
V+ 1 R1
1000 pF 39 Ω
R2
68 Ω
CA VR1 C2 C3
1000 pF P6KE200 680 µF 120 µF
500 V 25 V 25 V
U2
D1 NEC2501-H
VR2
UF4005
1N5995B
BR1 2 6.2 V
400 V C1 7
L2 RTN
33 µF
22 mH 400 V D3
1N4148
V- 3
C6 C5
0.1 µF 4
47µF
X2
DRAIN
F1 SOURCE
C7
3.15 A CONTROL
1.0 nF
L Y1
U1 C4
TOP202YAI 0.1 µF
N
J1
PI-1653-111695 3
Figure 41. Typical 2-Wire TOPSwitch Power Supply and EMI Filter for Video Applications and Reduced Radiated Emissions.
Figures 41 and 42 both show a low cost, ceramic, 1000 pF additional capacitor should be placed directly from TOPSwitch
capacitor across output diode D2 to help control dv/dt and diode source pin to transformer V+ pin.
ringing voltages. Higher output voltages may require reducing
the size of the capacitor and increasing the voltage rating. Figure 42 shows an alternate circuit using three Y2-capacitors
to balance the high frequency common mode impedance to V+
In Figure 41, another 1000 pF, 500 V capacitor (CA) is added and V-. Note that two Y2-capacitors (CA and C7) are essentially
in parallel with input energy storage capacitor C1 for high in series and effectively provide high frequency bypass across
frequency bypass in the 30 MHz to 200 MHz range. This C1.
3-23
Rev. B 04/05
D2 L1
T1 UG8BT 3.3 µH
8 7.5 V
V+ 1 R1
1000 pF 39 Ω
R2
68 Ω
VR1 C2 C3
P6KE200 680 µF 120 µF
25 V 25 V
U2
D1 NEC2501-H
VR2
UF4005
1N5995B
BR1 2 6.2 V
C1 7
400 V RTN
L2 33 µF CA
22 mH 400 V D3
1N4148 2.2 nF
3 Y2 C8
V- 2.2 nF
Y2
C6 C5
0.1 µF 4
47µF
X2
DRAIN
F1 SOURCE
C7
3.15 A CONTROL
2.2 nF
L Y2
U1 C4
TOP202YAI 0.1 µF
N
J1
PI-1654-111695
Figure 42. 2-Wire TOPSwitch Power Supply and EMI Filter with Three Y-Capacitors For Video Applications and
Reduced Radiated Emissions.
Alternative Filter Approach Without Common Mode Choke to capacitor C1. Differential mode attenuation is provided by
An alternative filter for lower power (below 5 watt) applications C1, C4, L2, and L3. The secondary is AC coupled back to the
3 is shown in Figure 43. This filter splits the high voltage energy primary by Y1-safety capacitor C7. Note that C7 can be
storage capacitor to create a filter. Peak current in L2 and L3 is replaced by two series connected Y2-safety capacitors with
approximately half the peak current in bridge rectifier BR1 due twice the value as shown.
L2
V+ 1 D4 L1
1N5822 (Bead)
1 mH 8
D1 5V
BZT03-C200 C2 C3
200 V 330 µF 150 µF
1.5 W 25 V 25 V
5 RTN
D2
UF4005 R1
C1 C4 22 Ω
2.2 µF 2.2 µF 4
BR1 400 V 400 V U1 2
400V
D C
C6 C7
0.047 µF TOP 3 1.0 µF
T1
X2 210 Y1
T1200
S S
L
C5 D3
47 µF 1N4148
N 1 mH V- 10 V
L3 PI-1652-111695
Figure 43. Low Power (Below 5W) TOPSwitch Supply Using Discrete Normal Mode Chokes.
3-24
Rev. B 04/05
Enclosure Shielding metal enclosures, plastic enclosures with a conductive coatings

Many applications, such as cellular phone battery chargers, on the internal surfaces, stamped and formed metal shapes,
printers, portable computer adapters and chargers, and video deep drawn cans, and metal foil. Low-impedance connections
games are packaged in plastic enclosures with no additional to the shield are important. Long wires, which degrades
shielding. Conducted and radiated emissions are controlled performance, must be avoided.
with proper selection of EMI filter components, careful
transformer construction, and tight PC layout practices. Figure 44 shows a typical 3 wire implementation with the
enclosure shield connected directly to the third wire earth
Some applications, such as desktop computers and other ground. The enclosure is AC coupled with Y2-capacitor C7
information technology equipment, have increased sensitivity back to primary circuitry. The enclosure is connected to
to conducted and radiated emissions and have a conductive secondary through low voltage, ceramic capacitor C8 or may be
enclosure connected to the AC mains third wire earth ground. directly connected depending on the system configuration.
Other applications, including distributed neural networks and Electrical safety is maintained under single component failure
consumer electronic devices such as VCRs and TV set-top conditions such as a short circuit failure of C7 or open circuit
decoders, also have a conductive enclosure but are powered failure of the connection to third wire earth ground. The third
from 2 wire AC input and have no earth ground connection. wire earth ground connection to the enclosure safely shunts
fault current to provide protection if C7 fails short. C7 safely
The enclosure forms a conductive shell which intercepts and limits fault current flow to less than 3.5 mA (IEC950 limit for
returns displacement currents back to the primary circuitry as three wire, 250 VAC) if the third wire earth ground fails open
shown in Figures 44-46. Practical implementations include circuit.
D2 L1
T1 UG8BT 3.3 µH
8 7.5 V
V+ 1 R1
39 Ω
R2
68 Ω
VR1 C2 C3
P6KE200 680 µF 120 µF
25 V 25 V
U2
NEC2501-H
D1
UF4005
VR2
1N5995B
3
BR1 2 6.2 V
C1 7
400 V RTN
L2 33 µF
22 mH 400 V D3
1N4148
V- 3 C8
0.1 µF
C6
0.1 µF C5 4
X2 47µF
DRAIN
F1 SOURCE
C7
3.15 A CONTROL
1.0 nF
L Y2
U1 C4
TOP202YAI 0.1 µF
N
L3
J1
PI-1657-111695
Figure 44. Typical 3-Wire TOPSwitch Power Supply and EMI Filter with AC Coupled SELV Potential Shielded Enclosure.
3-25
Rev. B 04/05
Figure 45 shows a typical 2 wire implementation with the circuitry. Another common approach is to use a series
enclosure shield connected to secondary RTN which places the combination of two Y2-safety capacitors which meets electrical
enclosure at SELV potential. PC board creepage distance safety requirements because each capacitor will safely limit
between primary circuits and the SELV shielded enclosure fault current to under 250 µA (IEC950 limit for two wire, 250
must meet reinforced insulation requirements. The enclosure is VAC) if the other capacitor fails short.
AC coupled with a small Y1-capacitor (C7) back to primary
D2 L1
T1 UG8BT 3.3 µH
8 7.5 V
V+ 1 R1
39 Ω
R2
68 Ω
VR1 C2 C3
P6KE200 680 µF 120 µF
25 V 25 V
U2
D1 NEC2501-H
VR2
UF4005
1N5995B
BR1 2 6.2 V
C1 7
400 V RTN
L2 33 µF
22 mH 400 V D3
1N4148
V- 3
C6 C5
0.1 µF 4
47µF
X2
DRAIN
F1 SOURCE
C7
3.15 A CONTROL
1.0 nF
L Y1
U1 C4
3 N
TOP202YAI 0.1 µF
J1
PI-1656-111695
Figure 45. Typical 2-Wire TOPSwitch Power Supply and EMI Filter with SELV Connected Shield.
3-26
Rev. B 04/05
Figure 46 shows a typical 2 wire implementation with the reinforced insulation requirements. The enclosure is AC coupled
enclosure shield at primary potential (usually connected to the with a small reinforced insulation, Y1-capacitor (C7) back to
TOPSwitch Source pin). This technique is used for partial SELV output circuitry. Another common approach is to use a
enclosures (which may actually be the TOPSwitch heat sink) series combination of two Y2-safety capacitors which meets
which are safely isolated from the SELV output voltages. PC electrical safety requirements because each capacitor will safely
board creepage distance between primary connected shield and limit fault current to under 250µA (IEC950 limit for two wire,
the circuits connected to SELV output voltages must meet 250 VAC) if the other capacitor fails short.
D2 L1
T1 UG8BT 3.3 µH
8 7.5 V
V+ 1 R1
39 Ω
R2
68 Ω
VR1 C2 C3
P6KE200 680 µF 120 µF
25 V 25 V
U2
D1 NEC2501-H
VR2
UF4005
1N5995B
BR1 2 6.2 V
C1 7
400 V 33 µF RTN
L2
22 mH 400 V D3
1N4148
V- 3
C6 C5
0.1 µF 4
47µF
X2
DRAIN
F1 SOURCE
C7
3.15 A CONTROL
1.0 nF
L Y1
U1
TOP202YAI
C4
0.1 µF 3
N
J1
PI-1655-111695
Figure 46. Typical 2-Wire TOPSwitch Power Supply and EMI Filter with Primary Connected Partial Shield.
3-27
Rev. B 04/05
EMI Filter Layout Issues
Filter layout is extremely important to obtain the desired

attenuation. Poor layout practice can cause conducted emissions
to actually couple around the filter components directly into the
AC mains conductors or cause radiated emissions.
Keep power stage and output components away from the EMI
filter to prevent coupling around the filter. The best approach
is to place the EMI filter at one end of a rectangular power
supply shape and place the output at the other end as shown in
Figure 47. Square power supply shapes should be avoided if
possible since the power stage and the output components will (a) (b)
be in close proximity to the EMI filter, allowing noise to couple WRONG RIGHT
directly into the mains. PI-275-081090
Figure 48. Bending the Bus to Minimize Resistive Effects.
been described in detail. The EMI filter must attenuate the

Power (a) emissions below the specification limit. Implementing a
EMI Stage Output RIGHT
successful EMI filter is an iterative process. The basic steps
include:
• Identify and attenuate the differential mode fundamental

EMI
(b) • Identify and attenuate the common mode fundamental
Power
Stage WRONG
Output • Identify other emissions over the spec limit.
• Determine whether each emission is differential mode or

PI-745-032392
common mode.
3 Figure 47. Power Supply Layout to Minimize Noise Coupling.

• Use average or quasi-peak measurements on peak emissions
to verify that the emission actually has insufficient margin
Capacitor lead length must be minimized as much as possible compared to the EMI standard.
to reduce ESL. This includes the traces on the PC board leading
up to the capacitor pads. Y-capacitor lead lengths and trace • Determine whether each emission is coupling around or
lengths are the most critical because the Y-capacitors couple passing through the EMI filter.
high frequency currents (10 MHz to 200 MHz) back to primary
circuitry. Figure 48 shows the right and wrong way to route PC • Change the filter design or control the circuit source to
traces to capacitors. attenuate each emission below the specification limit.
Locate the differential mode filter capacitor across the AC input • Go back and check the earlier emission levels to make sure
conductors as close as possible to the power entry point. a change did not cause a different problem to occur.
Practical Considerations Differential Mode Versus Common Mode

The first frequency sweep for EMI conducted emissions on a
Successful EMI filter design begins with knowledge of the power supply with no EMI filter will usually produce a spectrum
switching power supply noise sources generating differential as shown in Figure 49. The fundamental is outside the
mode and common mode conducted emissions which have specification limit as well as some of the harmonics. Each
3-28
Rev. B 04/05
harmonic is composed of both differential mode and common will have to be employed to reduce this harmonic any further.
mode emissions.
Using Splitters
80 Splitters combine the output signals of the two LISNs to
PI-746-032392
determine if a specific emission is common mode or differential
Conducted Emissions (dBµV)
mode. Two splitters are required: an in-phase splitter (Mini

60 Circuits Lab ZSC-2-2) where VOUT is the sum of the two LISN
signals and a 180 degree out-of-phase splitter (ZSCJ-2-2)
where VOUT is the differential between the two LISN signals(22).
40 The splitter setup is shown in Figure 51.
Splitter units are also available which allow switching between

20 differential mode and common mode tests.
0 ID
0 1 2 To
Frequency (MHz) L Power
+Vn Supply
Figure 49. Typical Conducted Emissions Data without EMI Filter.
+Vcb
In Figure 50, a differential mode component with magnitude Icb

70 dBµV is shown relative to a common mode component with
magnitude 50 dBµV. 20 dB differential between the two Splitter Spectrum
components is actually an order of magnitude between the G In Analyzer
absolute values of the two components. The signals will add
dB/µV
and superimpose if the phasing is correct but the overall effect
on the measured signal level is slight (10% increase, or less than Icu Icb f
1 dB).
-Vn
+Vcb
+Vcu To
N Power
70 dB(µV) ID
Supply
PI-1728-121895
3
40 dB(µV) Figure 51. Separating Differential Mode from Common Mode
Using a Splitter.
30 dB
DM Filter
Differential Mode Splitter Measurement
Differential mode emission current (ID) circulates from the
Differential-mode power supply through the first LISN sense resistor (producing
an in phase sense voltage), through the second LISN sense
Common-mode resistor (producing an out of phase sense voltage), and back to
PI-1727-121895
the power supply. The output voltage of the in-phase splitter
Figure 50. Superimposed Common Mode and Differential Mode will have no differential mode component because the opposite
Harmonics. phased sense voltages effectively cancel. The output voltage of
the 180 degree out-of-phase splitter will have differential mode
A differential mode filter with 30 dB attenuation at the harmonic components 6 dB higher than those measured directly at the
frequency of interest will not attenuate the measured peak by LISN as the sense voltages are now effectively in phase and
30 dB. The differential mode component will be attenuated sum.
from 70 dBµV to 40 dBµV, but the 50 dBµV common mode
peak will now dominate the measurement. Further differential Balanced Common Mode Splitter Measurement
mode attenuation will have no effect on the measured harmonic Balanced common mode currents (ICB) are defined as currents
because the signal is common mode. Common mode filtering with similar amplitude and phase that flow from ground through
3-29
Rev. B 04/05
each LISN sense resistor (producing sense voltages with the frequency (above which the choke behaves like a capacitor) and
same phase) and through the AC input to the power supply. The effective Q. Identify multi-resonant behavior due to multiple
output voltage of the in-phase splitter will have balanced layer winding.
common mode components 6 dB higher than those measured
directly at the LISN because the in phase sense voltages
effectively add. The output voltage of the 180 degree out-of-
phase splitter will have no balanced common mode components Spectrum
as the sense voltages are now effectively out of phase and Analyzer
cancel.
dBµV
Unbalanced Common Mode Splitter Measurement f
Unbalanced common mode currents (ICU) flow from ground

through either LISN sense resistor. Unbalanced common mode
currents are found when the EMI filter does not have balanced L LISN
impedance in each leg or when noise from the power path
returns from the AC mains asymmetrically through one side of POWER
the EMI filter (typically caused by asymmetric parasitic EMI SUPPLY
G
capacitance). The output voltage of the in-phase splitter will FILTER &
have unbalanced common mode components equal to those LOAD
measured directly at the LISN because there is no cancellation. N LISN
The output voltage of the 180 degree out-of-phase splitter will
also have unbalanced common mode components equal to
those measured directly at the LISN for the same reason. GROUNDED BOX
PI-749-032392
The results of using the two splitters on each of the three types Figure 52. Typical Conducted Emissions System Test Set-Up with
of emissions is shown in Table 5. Grounded Box.
Spatial Coupling
LISN IN 180° OUT As power supplies get smaller the EMI filter gets physically
OUTPUT PHASE OF PHASE closer to circuitry acting as noise generators. High dv/dt
voltage waveforms and high di/dt current loops generate fields
Differential (VD) 0 VD + 6 dB which may spatially couple around the EMI filter and induce
3 Balanced
emission currents directly in the mains. Noise currents which
couple around the filter must be distinguished from the noise
Vcb + 6 dB 0
Common-mode (Vcb) currents which are passing through the filter.
Unbalanced One way to separate conducted emission currents is to place the

Vcu Vcu
Common-mode (Vcu) power supply power circuitry and load within a grounded box
as shown in Figure 52. The EMI filter is connected between the
Table 5. Splitter Signal Levels. enclosed power supply and AC mains. The box will contain the
fields, allowing conducted emission currents to be directly
measured. This is especially effective when analyzing the
EMI Filter Component Measurements fundamental. (Note that this technique is for investigative
No EMI filter component is perfect. At some frequency all purposes only and must not be used for final test data).
components “give up” their basic characteristic to the effects of
parasitics. The spatial coupling emissions can be reduced by containing
the fields at their sources with local shields. Local shields over
Measure all capacitors. Identify specifically the self-resonant primary power circuitry such as the flyback transformer, primary
frequency (above which the capacitor looks like an inductor) damper, clamp diode, and TOPSwitch can be used to contain
and effective Q. fields. Local shields can also be used over secondary circuitry
such as output rectifiers. Shields can also be applied around the
Measure all chokes. Identify specifically for the self resonant EMI filter although the preferred approach is to contain the field
3-30
Rev. B 04/05
at the source. Heat sinks can also be used as shields. methods only when the measured peak value is close to or
exceeds the target specification.
Another type of shield is a conductive plate approximately the
same size as the printed circuit board. This plate can be Recommended Step-by-Step Procedure
connected to earth ground, primary reference, or secondary 1) Determine differential mode fundamental (and low frequency
reference (depending on the safety insulation system chosen). harmonics).
This is attractive for applications connecting to the third wire
ground but without a conductive enclosure. 2) Calculate and select filter X-capacitance and target differential
inductance. Select bobbin style common mode choke with
Lossy Beads sufficient differential mode inductance and AC current rating
Small beads can be used in circuit leads to damp or eliminate (use discrete chokes only for low power, under 5 Watts).
high frequency ringing. Ferrite beads from Fair-Rite(21) are
available in a variety of shapes. These beads feature low 3) Measure impedance versus frequency for each component.
impedance at low frequency for minimal effect on the current Select components with resonant frequencies that do not coincide
waveform but have high impedance at high frequency with with waveform ringing frequencies in the power supply.
significant parallel resistance to damp and reduce ringing
voltage waveforms. 4) Use a nominal value AC source through the LISNs to
provide power to the power supply. Use the 180 degree splitter
Grounding to extract the differential mode fundamental current component.
Some applications connect the output voltage to earth ground. Measure the fundamental with slow sweep speed and measure
Others have no connection at all to earth ground. It is important peak value using maximum hold. Compare the measured
to identify the earth ground connection expected for each differential mode fundamental with the calculated value. Use
application and to test in that configuration. EMI testing should average or quasi-peak detection as required to properly compare
be performed in both grounded and ungrounded configurations. measured reading with limits of the chosen standard. Increase
X2-capacitance or select common mode choke with higher
Power Cord differential inductance if necessary.
The power cord resonance previously described can interfere
with conducted emissions testing. Switch between two power 5) Examine entire frequency range for differential mode
cords of different lengths to separate power cord resonances components close to or in excess of the specification limit.
from other conducted emissions. Make measurements on both Line and Neutral LISN. Pay
special attention to frequency ranges around measured
Miscellaneous Test Tricks component resonances and identified circuit ringing frequencies.
Terminate opposite LISN with 50 ohm terminator. The LISN Use average or quasi-peak detection as required to properly
sense impedance is actually determined by the termination and compare measured reading with limits of the chosen standard. 3
will change if not properly terminated. Modify differential mode filter design if necessary.
Warm up equipment including Device Under Test (DUT) for at 6) Use in-phase splitter to extract the balanced common mode
least 1 hour before testing so results will be repeatable. fundamental and low frequency harmonic current components.
For 2-wire applications, place the largest value Y1-safety
Make sure analyzer sweep speed is low enough to capture the capacitor (subject to leakage current limitations but typically
peaks of each harmonic. The bridge rectifier conducts current 1 nF) to output return. Two series connected Y2-safety capacitors
(both power and emission currents) for a short time compared (typically each with 2.2 nF value) can also be used. For 3-wire
with the full line cycle which effectively “pulse width modulates” applications, place the largest value Y2-safety capacitor (subject
the emission currents. Slower sweep speeds will collect enough to leakage current limitations but typically 1 nF up to 33 nF)
data to accurately measure the peak of each current emission. A from the power supply high voltage return to earth ground and
peak hold test can also be used to fill in the peaks in a few then connect a 0.1 uF low voltage ceramic capacitor from earth
sweeps. ground to secondary return. Y-capacitor leads must be very
short to attenuate high frequency current emissions. Measure
Peak measurements take the least amount of time but balanced common mode fundamental and low frequency
specifications are given in quasi-peak or average limits. Both harmonics. Increase size of common mode choke if necessary.
quasi-peak and average measurement techniques give lower Select the smallest, widest bandwidth common mode choke
readings when compared to the peak value. If the peak value (with sufficient RMS current ratings) that attenuates the balanced
meets the average or quasi peak limit specification, there is no common mode fundamental to the desired level. Measure
need to take further data with the average or quasi peak impedance versus frequency for each component. Select
methods. To save test time, use the quasi-peak and average test components with resonant frequencies that do not coincide with
3-31
Rev. B 04/05
waveform ringing frequencies in the power supply. 8) Remove splitters. Measure signals from both Line and
Neutral over the entire frequency range. Emissions above 1
7) Examine entire frequency range for balanced or unbalanced Mhz are usually common mode. Solve spatial coupling effects
common mode components close to or in excess of the using additional Y-capacitors (see Figures 41 and 42), improved
specification limit. Make measurements on both Line and transformer construction (see Figures 35 and 36), higher
Neutral LISN. Pay special attention to frequency ranges around bandwidth two section common mode choke (see Figure 21),
measured component resonances and identified circuit ringing additional high frequency common mode choke (see Figure 27)
frequencies. Use average or quasi-peak detection as required to or shielding techniques (Figures 44-46).
properly compare measured reading with limits of the chosen
standard. Modify common mode filter design if necessary. 9) Perform final test with secondary connected to ground and
also with secondary isolated from LISN ground.
BIBLIOGRAPHY
(1) FCC Harmonizes Its ITE Rules with C.I.S.P.R. (9) M. Engelson, “Measures of EMC, A Review of Basic
Requirements, Compliance Engineering, pp 7, January/ EMC Measurement Techniques and Standard Practices”,
February, 1994. EMC Test and Design, November/December 1990.
(2) European Standard EN55022, “Limits and Methods of (10) Elliott Laboratories, 684 W. Maude Avenue, Sunnyvale,
Measurement of Radio Interference Characteristics of CA, 94086 (408-245-7800).
Information Technology Equipment”, Cenelec, 1994.
(11) IEC1950, “Safety of Information Technology Equipment
(3) “Limits and Methods of Measurement of Radio Including Electrical Business Equipment”, Second
Interference Characteristics of Information Technology Edition, International Electrotechnical Commission, 1991.
Equipment”, C.I.S.P.R Publication 22, 1993.
(12) Evox Rifa, “Capacitors 1995”, Catalogue, Evox- Rifa
(4) Dash, D. and Straus, I.; “EMC Regulations in Germany”; Inc., 100 Tri-State International, Suite 290, Lincolnshire,
Compliance Engineering 1994 Reference Guide, pp. 85- Illinois 60069, (1-708-948-9511).
96, Compliance Engineering, Boxborough, MA.
(13) European Standard EN 132400, “Sectional Specification:
(5) Regulation Vfg 243/1991, “Radio Interference Fixed Capacitors for Electromagnetic Interference
3 Suppression of Radio-Frequency Equipment for
Industrial, Scientific, Medical (ISM) and Similar Purposes
Suppression and Connection to the Supply Mains”,
(Assessment Level D), Cenelec, 1994.
and Equipment used in Information Processing Systems;
General License”, German Federal Minister for Post and (14) Murata Electronics, North America, Inc., “Disk Ceramic
Telecommunications. Capacitor Catalog no. C-OS-C 1991”, Murata Erie North
America, 2200 Lake Park Drive, Smyrna, Georgia
(6) Amending Regulation Vfg 46/1992, German Federal 30080, (1-800-831-9172).
Minister for Post and Telecommunications.
(15) Roederstein, "EMC Radio Interference Suppression
(7) “Meeting the EC Emissions Requirement”, Handbook of Components", 1991, (704-872-8101).
EC EMC Compliance, Compliance Design Incorporated,
1993, pp 7-15. (16) Tokin, “EMC Line Filters Vol. 2 CD-07JE”, Tokin
America Inc., 155 Nicholson Lane, San Jose, CA 95134
(8) M. Engelson, “EMI Applications using the Tektronix (1-408-432-8020).
2712 Spectrum Analyzer”, Application Note, Tektronix,
1993.
3-32
Rev. B 04/05
(17) Tamura , “Tamura Common Mode Coils for AC Line & (19) TDK Corporation of America, "TDK EMI Prevention
EMI Filtering, 0.1 to 50 Mhz”, Electronic Engineers Components", EVE-005B, 1993, (708-803-6100).
Master Catalogue (EEM), 1995, Tamura Corporation of
America, P.O. Box 892230, Temecuca, CA 92589, (20) Murata Erie, "EMI/RFI Filter Catalog", E-06-A, 1993,
(1-909-699-1270). (1-800-831-9172).
(18) Panasonic Industrial Company, “Panasonic Line Filters”, (21) Fair-Rite, “Fair-Rite Soft Ferrites” Catalogue, 12th edition,
Digikey Catalog 961, January-February 1996 (1-800- Fair-Rite Products Corporation, P.O. Box J, 1 Commercial
344-4539). Also “Panasonic Inductors/Transformers 94/ Row, Wallkill, NY 12589, (914-895-2055).
95” #9404155S1, Panasonic Industrial Co., 2 Panasonic
Way (7H-3), Secaucus, New Jersey 07094 (1-201-348- (22) Mini-Circuits Laboratories, 13 Neptune Ave., P.O. Box
4630). 350166, Brooklyn, NY 11235, (718-934-4520).
Revision Notes Date

A - 6/96
B 1) Corrected transfer function H(s) equation. 4/05
3-33
Rev. B 04/05
®
TOPSwitch
Flyback Transformer Construction Guide
Introduction Ferrite Core Manufacturer’s Catalogs
This application note is a design and construction guide for Ferrite core manufacturers publish catalogs supplying core
margin wound or triple insulated wire wound flyback dimensions and electrical characteristics used in transformer
transformers suitable for use with TOPSwitch. Margin wound design. Some manufacturers also provide additional engineering
and triple insulated wire transformer designs are derived in information for the more popular core sizes, such as AL vs. gap
Appendix B for a 12 V, 15 W universal input power supply with and core loss curves. The catalogs for the manufacturers listed
secondary regulation, using the step-by-step procedure in Appendix A supply basic electrical data for common US,
developed in application note AN-16. It is assumed that the Asian, and European core types. For core sizes common to
reader is already familiar with TOPSwitch and the fundamental several manufacturers, the electrical characteristics given by
principles of flyback power supplies. This information can be one core manufacturer can be used for a core of the same
found in the TOPSwitch data sheets, and application notes physical dimensions from another manufacturer.
AN-14 and AN-16. More details on flyback transformer theory
and design can be found in AN-17. Bobbin Manufacturer’s Catalogs
Required Reference Materials Bobbin manufacturer's catalogs are used to provide mechanical
dimensions for transformer design. The bobbin manufacturers
This application note, AN-16, and AN-17 provide the necessary in Appendix A offer a wide variety of bobbin styles for standard
techniques for design and construction of flyback transformers ferrite core sizes in materials suitable for high volume production.
for TOPSwitch applications. In addition, the following reference Many ferrite core manufacturers also carry bobbins for their
materials are required to provide dimensional and electrical standard core sizes.
data for cores, bobbins, and wire. Sources for these reference
materials are listed in Appendix A.
3
PRIMARY
SECONDARY
BIAS
PI-1907-061896
Figure 1. Typical Flyback Transformer Using EE Core.
3-34
Rev. A 07/96
Wire Table Insulating Materials
A wire table provides dimensional and electrical characteristics A common insulating material used in transformers is polyester
for magnet wire, and is used to select appropriate wire sizes for or Mylar, available in sheet or tape form. This material is also
transformer design. There are three major wire sizing systems: manufactured as an adhesive tape that is particularly useful in
AWG, SWG and metric. All wire sizes used in this application transformer construction. US manufacturers of this tape
note are based on AWG sizing. A wire table is provided in include 3M, Tesa, and CHR. For creepage margins in
Appendix A with data on AWG wire sizes from 18 gauge transformers, it is desirable to use a thick tape so that the
through 44 gauge. SWG and metric equivalents to AWG wire required build for a margin can be achieved using relatively few
sizes are also shown. A wire table is also available in layers. Several manufacturers make a polyester film/mat tape
reference 5. Wire tables can be obtained from some of the that is useful for this application.
magnet wire manufacturers listed in Appendix A.
Magnet Wire
Transformer Construction Materials
Some typical domestic manufacturers of magnet wire are
The following paragraphs describe the basic materials needed Belden, Phelps Dodge, and Rea. The preferred insulation for
to construct switching power supply transformers. magnet wire is a nylon/polyurethane coating. This coating
burns off in contact with molten solder, allowing the transformer
Ferrite Cores to be terminated by dip tinning in a solder pot. This type of
insulated magnet wire is available from almost all manufacturers
Appropriate ferrite materials for 100KHz flyback transformers under various trade names: Solderon, Nyleze, Beldsol, etc. The
are TDK PC40, Philips 3C85, Siemens N67, Thomson B2, insulating coating should be “heavy” or “double” to better
Tokin 2500 or other similar materials. A wide variety of core withstand the stress of handling and the winding process.
shapes are available. E cores are the best choice for transformer Ordinary enameled wire or polyimide wire insulation should
cores for reasons of low cost, wide availability, and lower not be used, as these types of insulation must be stripped
leakage inductance. Other core shapes and styles such as the mechanically or with chemical stripping agents in order to
ETD, EER and EI are also usable. A chart of suitable ferrite core terminate the wire to the transformer pins.
types for various power levels and transformer construction
types can be found in Appendix A. Triple Insulated Wire
Bobbins Triple insulated wire can be used to simplify and reduce the size
of transformers where safety isolation is required. The type of
Bobbins for off-line flyback transformers should be chosen triple insulated wire useful for transformer construction consists
with regard to the safety creepage distances required by the of a solid wire core with three distinct and separable layers of 3
applicable safety regulations. Particular areas of consideration insulation. Three manufacturers of triple insulated wire are
are the total creepage distance from primary pins to secondary listed in Appendix A.
pins through the core, and the creepage distance from primary
pins to the secondary winding area. With some bobbin styles, Sleeving
extra insulation may be necessary to meet the creepage
requirements. Bobbins should preferably be made from Insulating tubing is used to insulate the start and finish leads of
thermosetting materials such as phenolic resin in order to windings in a margin wound transformer. The tubing should be
withstand soldering temperatures without deformation. recognized by the applicable safety agencies, with a minimum
Polybutylene or polyethylene terphthalate (PBT, PET) and wall thickness of 0.4 mm to meet thickness requirements for
polyphenylene sulfide (PPS) are also acceptable materials, reinforced insulation. The tubing should also be heat resistant,
though more sensitive to high temperatures than phenolic so that it does not melt when exposed to the temperatures
resins. Nylon should be avoided if possible, as it melts easily required to solder the transformer lead wires to the pins on the
at the temperatures required to effectively terminate the bobbin. Materials commonly used for sleeving include Teflon
transformer windings to the pins on the bobbin. If Nylon tubing or polyolefin heat shrink tubing.
bobbins are used, they should be made with glass reinforced
resin with a temperature rating of 130˚C.
3-35
Rev. A 07/96
Varnish
SECONDARY
Many transformer manufacturers impregnate their finished
transformers with a suitable electrical varnish. By filling the REINFORCED
INSULATION
voids inside the transformer, the varnish improves heat transfer BIAS
from the windings to the environment, and enhances the voltage
withstand capability of the transformer insulation. It also locks MARGIN PRIMARY
the core and windings in place to help prevent audible noise and (Z WOUND)
protects the finished transformer from moisture. One
disadvantage of varnish impregnation is that it adds a slow extra
step to transformer construction. Some manufacturers of (a) MARGIN WINDING
electrical varnishes are listed in Appendix A.
ALTERNATE
Transformer Construction Methods PRIMARY
WINDING
In order to meet international safety regulations, a transformer
for use in an off-line power supply must have adequate insulation (b) C WINDING
PI-1828-041696
between the primary and secondary windings. For transformers
using standard cores and bobbins, there are two basic transformer Figure 2. Margin Wound Transformer Cross Section.
insulation methods: margin wound construction and triple
insulated wire construction.
Margin Wound Construction
International safety regulations require the following for

transformers using magnet wire: CREEPAGE
DISTANCE SECONDARY
WINDING
• Reinforced insulation between primary and secondary
windings. M
• Guaranteed creepage distance between primary and

} REINFORCED
INSULATION
3
secondary windings where reinforced insulation is not
used.
A cross-section of a typical margin wound transformer designed

M
} PRIMARY AND
BIAS WINDINGS
to meet these requirements is shown in Figure 2. PI-1867-053196
The creepage distance required between primary and secondary Figure 3. Interwinding Creepage Distance for Margin Wound
windings by safety regulations is typically 2.5 to 3 mm for Transformers.
supplies with 115 VAC input, and 5 to 6 mm for 230 VAC or
universal input supplies. This creepage distance is maintained
by physical barriers called margins. In most practical transformer VRMS for 230 VAC input supplies. The tape layers should
designs, these margins are built up on each side of the bobbin cover the entire width of the bobbin from flange to flange, as
using electrical tape, with the windings placed between them as shown in Figure 2. A polyester film tape with a base film
shown in Figure 2. The total minimum creepage distance thickness of at least 0.025mm is sufficient for use in this
between primary and secondary windings is equal to twice the application. The secondary windings are effectively "boxed in"
margin width M, as shown in Figure 3. This sets the minimum by the margins and the reinforced insulation, isolating them
margin width at one half the required creepage distance, or 1.25 from the primary. Since the start and finish leads of each
to 1.5 mm for 115 VAC input supplies, and 2.5 to 3 mm for 230 winding pass through the margins to reach the transformer pins,
VAC or universal input supplies. they may require extra insulation to maintain the integrity of the
margin insulation. Insulating tubing with a wall thickness of at
The necessary reinforced insulation between primary and least 0.4 mm is used to cover all start and finish leads of a margin
secondary windings is provided using three layers of electrical wound transformer to meet this requirement. This insulation
tape, any two of which can withstand the full safety test voltage, should extend from the transformer pin to inside of the margin
which is 2000 VRMS for 115 VAC input supplies, and 3000 barrier, as shown in Figure 4.
3-36
Rev. A 07/96
Use of margin winding techniques allows the construction of a Transformer Construction Techniques
transformer with ordinary magnet wire and readily available
insulating materials. However, the necessity for margins, start Figure 7 shows four styles of transformer construction for both
and finish sleeving, and reinforced insulation results in a primary and secondary regulated flyback power supplies, using
complex and labor-intensive transformer. The margins waste margin wound and triple insulated wire techniques. These four
space inside the transformer, making it necessary to use a much styles are sufficient for almost all switching power supply
larger core and bobbin size than could be used if the margins requirements. The following paragraphs describe the
were not required. One alternative to margin wound construction considerations involved in selecting a particular construction
is the use of triple insulated wire. style for an application, as well as additional considerations for
reducing EMI, stray capacitance, and leakage inductance.
Triple Insulated Wire Construction
Winding Sequence
Triple insulated wire (Figure 5) has three separate layers of
insulation, any two of which can withstand a safety hipot test Figure 7 shows optimum winding sequencing for transformers
voltage of 3000 VRMS. Triple insulated wire thus satisfies the for primary and secondary regulation schemes using margin
requirements for a reinforced insulation per VDE/IEC wound and triple insulated wire construction. The factors
regulations, and can be used to construct a transformer without involved in determining optimum winding sequencing and
the creepage margins required in a design using conventional insulation placement are discussed below.
magnet wire. A cross-section of a triple insulated wire
transformer design is shown in Figure 6. The triple insulated
wire design uses magnet wire for primary and bias windings,
with a triple insulated secondary. This is generally the most
cost effective and space-efficient way to utilize the benefits of
triple insulated wire, as it is larger in diameter and more costly Solid Wire Core
3 Separate
Insulation
Margin Layers
Margin
PI-1795-030895 3
Insulating
Figure 5. Triple Insulated Wire.
Sleeving
PI-1810-032896
BIAS
Figure 4. Use of Insulating Sleeving. (ALTERNATE
SECONDARY LOCATION)
than the equivalent size of magnet wire. The secondary winding (INSULATED)
will usually require fewer turns of larger diameter wire than the
BIAS (MAGNET
primary, so the cost and space impact of the triple insulated wire WIRE)
is minimized. In a triple insulated wire design, the full width of PRIMARY
the transformer bobbin is usable, due to the reinforced insulation (MAGNET
provided by the triple insulated wire. A transformer using a WIRE)
triple insulated wire design will generally be 1/2 to 2/3 of the
size of a transformer of the same power capability using a
magnet wire design. Leakage inductance varies inversely with
the width of the transformer windings, so leakage inductance
for a triple insulated wire transformer will usually be less than PI-1678-091395
that of an equivalent margin wound design, due to more
efficient use of space on the transformer bobbin. Figure 6. Triple Insulated Wire Wound Transformer Cross Section.
3-37
Rev. A 07/96
PRIMARY FINISH LEAD PRIMARY FINISH LEAD

(WITH SLEEVING) (WITH SLEEVING)
PIN PIN
REINFORCED
INSULATION SECONDARY REINFORCED PRIMARY BIAS
INSULATION
PRIMARY BIAS SECONDARY
BASIC
PRIMARY FINISH
INSULATION PRIMARY FINISH
PRIMARY START
PRIMARY START
BASIC
INSULATION
MARGIN (4x)
MARGIN (6x)
PI-1799-030896 PI-1800-030896
Figure 7A. Margin Wound Secondary Regulated Transformer. Figure 7B. Margin Wound Primary Regulated Transformer.
PRIMARY FINISH LEAD PRIMARY FINISH LEAD

(WITHOUT SLEEVING) (WITHOUT SLEEVING)
PIN REINFORCED PIN
REINFORCED
INSULATION TRIPLE INSULATED INSULATION PRIMARY BIAS
SECONDARY TRIPLE INSULATED
BASIC PRIMARY BIAS BASIC
SECONDARY
INSULATION PRIMARY FINISH INSULATION PRIMARY FINISH
PRIMARY START PRIMARY START
PI-1801-030896 PI-1802-030896
3 Figure 7C. Triple Insulated Secondary Regulated Transformer. Figure 7D. Triple Insulated Primary Regulated Transformer.
Primary Winding a factor of four. This is especially important for low power
In all the transformer construction styles depicted in Figure 7, applications using TOP200 and TOP210 to prevent spurious
the primary winding (or a portion of it) is always the first or triggering of the TOPSwitch current limit by the initial current
innermost winding on the bobbin. This keeps the mean length spike generated when TOPSwitch turns on and discharges the
of wire per turn as short as possible, reducing the primary transformer winding capacitance.
winding parasitic capacitance. Also, if the primary winding is
the innermost winding on the transformer, it will be shielded by Primary Bias Winding
the other transformer windings, helping to reduce noise coupling The optimum placement of the primary bias winding will
from the primary winding to adjacent components. The driven depend on whether the power supply uses a primary referenced
end of the primary winding (the end connected to the TOPSwitch or secondary referenced regulation scheme. If the power supply
drain) should be at the start of the winding. This allows the half is regulated from the secondary side, the bias winding should be
of the primary winding with the largest voltage excursion to be placed between the primary and secondary, as shown in Figures
shielded by other windings or by the second half of the primary 7A and 7 C. When placed between the primary and secondary,
winding, reducing EMI coupled from the primary side of the the bias winding acts as an EMI shield connected to the primary
transformer to other parts of the supply. The primary winding return, reducing the conducted EMI generated by the power
should be designed for two winding layers or less. This supply. In margin wound designs for secondary regulated
minimizes the primary winding capacitance and the leakage supplies, placing the primary bias winding between the primary
inductance of the transformer. Adding a layer of tape between and secondary also minimizes the number of margins and
primary layers can reduce the primary winding capacitance by reinforced insulation layers in the transformer.
3-38
Rev. A 07/96
For power supplies using a primary regulation scheme, the bias

winding should be the outermost winding on the transformer, as ⎛ ⎛ N + N2 ⎞ ⎞
V2 = ⎜ (V1 + VD1 ) × ⎜ 1 ⎟ − VD 2
shown in Figures 7B and 7D. This maximizes the coupling of ⎝ ⎝ N1 ⎠ ⎟⎠
the primary bias winding with the secondary, and minimizes
coupling to the primary, improving the output regulation of the
supply in two ways. With better coupling to the secondary, the VD1 and VD2 are the rectifier forward voltage drops for D1 and
bias winding responds more accurately to output voltage changes, D2, respectively. N1 and N2 are the winding turns for the V1 and
improving regulation. Also, the resultant poor coupling of the V2 outputs.
bias winding to the primary helps to improve regulation by
reducing peak charging of the bias output due to the primary The wire for each output must be sized to accommodate its
leakage spike. If the bias winding is only loosely coupled to the output current plus the sum of the output currents of all the
primary, the leakage spike can be filtered by using a small outputs stacked on top of it.
resistor in series with the primary bias winding, improving the
load regulation of the supply. This is discussed in greater detail Insulation Requirements
in design note DN-8.
Figure 7, in addition to showing optimum winding sequencing,
The primary bias winding should ideally form one complete also shows placement of basic and reinforced insulation to meet
layer across the width of the bobbin. If the bias winding has safety requirements and to improve consistency of the finished
relatively few turns, this can be accomplished by increasing the transformer.
size of the wire used in the bias winding, or using multiple
parallel strands of wire. Increasing the fill factor of the bias For the margin wound secondary regulated transformer
winding in this manner improves the shielding capability of the (Figure 7A), basic insulation (1 layer of electrical tape) is used
winding in the case of the secondary regulated supply, and between primary layers and between the primary and the bias
improves the secondary to bias coupling in the case of the winding. A layer of tape can also be useful between secondary
primary regulated supply. windings to provide a smooth winding surface from one winding
layer to the next. Reinforced insulation (three layers of tape) is
Secondary Windings used between the primary bias winding and the secondary. A
If a transformer has multiple secondary windings, the highest three layer finish wrap completes the reinforced insulation for
power secondary should be the closest to the primary of the the secondary. There are four margins in this transformer: two
transformer, in order to reduce leakage inductance. If a secondary for the primary and bias windings, and two for the secondary
winding has relatively few turns, the turns should be spaced so windings. Insulating sleeving is used on the start and finish
that they traverse the entire width of the winding area, for leads of all windings. In Figures 7A and 7B sleeving is shown
improved coupling. Using multiple parallel strands of wire will only on the primary finish lead for purposes of clarity. In
also help to increase the fill factor and coupling for secondaries practice, sleeving is used on the start and finish leads of all 3
with few turns. For multiple output secondary regulated supplies, windings. The sleeving should extend as shown from the inside
auxiliary outputs with tight regulation requirements should be edge of the margin to the transformer pin.
wound directly on top of the regulated secondary to improve
coupling. For the margin wound primary regulated transformer
(Figure 7B), basic insulation is used between primary winding
Multiple Output Winding Techniques layers. As in the secondary regulated transformer, a layer of
Instead of providing separate windings for each output in a tape can be used between secondary windings to smooth the
multiple output supply, a common technique for winding winding surface. Reinforced insulation is required between the
multiple output secondaries with the same polarity sharing a primary and secondary windings, between the secondary and
common return is to stack the secondaries, as shown in Figure primary bias windings, and as a finish wrap on top of the
8. This arrangement will improve the load regulation of the primary bias winding. In this transformer, there are three pairs
auxiliary outputs in a multiple output supply, and reduce the of margins: one pair for the primary winding, one pair for the
total number of secondary turns. The windings for the lowest secondary winding, and one pair for the bias winding. Start and
voltage output provide the return and part of the winding turns finish of each winding are sleeved as described above.
for the next higher voltage output. The turns of both the lowest
output and the next higher output provide turns for succeeding For the triple insulated secondary regulated transformer
outputs. For the two output stacked winding example shown in (Figure 7C), basic insulation is used between primary layers,
Figure 8, the relation between output voltages V1 and V2 is between primary and bias, and between bias and secondary.
given below: The insulation reduces the capacitance of the primary winding
3-39
Rev. A 07/96
D2
V2
I2
V+ N2
I2 D1
NP V1
I1
TOPSwitch
Drain N1
I1+I2
COMMON
RETURN
PI-1798-030896
Figure 8. Stacked Secondary Windings for Multiple Outputs.
and smooths the surface between windings. The finish wrap of coupling and lowest leakage. For higher power applications
three layers is more for cosmetic reasons than for safety. There (40 watts and above), a split primary “sandwich” construction
3 are no margins and no sleeving. is recommended to minimize leakage inductance. Using a split
primary will in general cut the leakage inductance to half that of
In the triple insulated primary regulated transformer a transformer with a single primary winding. Split primary
(Figure 7D), basic insulation is used between primary layers, construction for secondary regulated transformers is shown for
between primary and secondary, and between secondary and the margin wound and triple insulated case in Figures 10A and
bias. A three layer outer wrap is required on the outside for 10B. A split winding construction is not recommended for
reinforced insulation. Again, no margins or sleeving are primary regulated designs, as it will result in poor load regulation.
required.
High power secondary windings consisting of only a few turns
Reducing Leakage Inductance should be spaced across the width of the bobbin window instead
of being bunched together, in order to maximize coupling to the
The winding order in a transformer has a large effect on the primary. Using multiple parallel strands of wire is an additional
leakage inductance. Transformer windings should be arranged technique of increasing the fill factor and coupling of a winding
in concentric fashion for minimum leakage inductance. Offset with few turns. In such cases, the wire size may be determined
or split bobbin construction (shown in Figure 9) should be more by the requirement for a good fill factor rather than the
avoided, as these techniques will result in high leakage inductance RMS current rating of the wire. Where cost permits, using foil
and unacceptable primary clamp circuit dissipation. windings is also a good way of increasing coupling, although
this method is usually practical only for low voltage, high
In a multiple output transformer, the secondary with the highest current secondary windings.
output power should be placed closest to the primary for the best
3-40
Rev. A 07/96
MARGIN
SECONDARY
BIAS BIAS
PRIMARY MARGIN PRIMARY
SECONDARY
OFFSET WINDING CONSTRUCTION SPLIT BOBBIN CONSTRUCTION
(NOT RECOMMENDED) (NOT RECOMMENDED)
PI-1829-041696
Figure 9. Offset and Split Bobbin Construction Techniques (Not Recommended).
EMI Reduction Techniques
The following transformer construction techniques help to noise between primary and secondary. The shield can be
reduce EMI: referenced either to the primary high voltage supply or to the
primary return. Typical shielded transformer constructions are
• Make the primary winding the innermost winding on the shown in Figure 11. The most economical form of shield is a
bobbin. wire shield. This type of shield can be added to the transformer
with very few extra steps, since it consists of a winding
• The start of the primary winding should be connected to the traversing the full width of the bobbin. One end of the shield
TOPSwitch drain. winding is terminated to the primary return or primary V+
supply, while the other end of the winding is left floating,
• For a secondary regulated transformer design, place the insulated with tape, and buried inside the transformer instead of
bias winding between primary and secondary to act as a being terminated to a pin. The wire size used for a wire shield
shield. is a compromise between a large size to minimize the number
of shield turns, and a relatively small wire size for ease of
Additional EMI/RFI reduction techniques include shielding termination. 24-27 AWG wire is a reasonable compromise for
between primary and secondary windings, and the addition of small to medium size transformers.
a “flux band” to reduce the stray field around the transformer.
Shields are placed between the primary and secondary of a

In some cases, the stray magnetic field around a switching
power supply transformer can interfere with adjacent circuitry
3
transformer to reduce the capacitive coupling of common mode and contribute to EMI. To reduce this stray field, a copper “flux
PRIMARY FINISH LEAD PRIMARY SECOND

(WITH SLEEVING) 1/2 FINISH
PRIMARY
PIN SECOND 1/2 START
REINFORCED PIN
PRIMARY SECOND 1/2 FINISH INSULATION PRIMARY FINISH LEAD
REINFORCED PRIMARY SECOND 1/2 START
(WITHOUT SLEEVING)
INSULATION TRIPLE INSULATED
SECONDARY
PRIMARY BIAS SECONDARY
BASIC SLEEVING
INSULATION PRIMARY BIAS
PRIMARY FIRST 1/2 FINISH BASIC PRIMARY FIRST 1/2 FINISH
PRIMARY FIRST 1/2 START INSULATION PRIMARY FIRST 1/2 START
MARGIN (6x)
PI-1803-030896 PI-1804-030896
Figure 10A. Margin Wound Secondary Regulated Transformer Figure 10B. Triple Insulated Secondary Regulated Transformer
with Split Primary. with Split Primary.
3-41
Rev. A 07/96
TRANSFORMER SHIELD PLACEMENT

Insulated Wire Transformer Margin Wound Transformer
SECONDARY
SHIELD
SECONDARY
BIAS
PRIMARY
} TAPE
SHIELD
BIAS
PRIMARY
MARGINS
PI-1814-032796
Figure 11. Transformer Shield Placement.
band” can be added around the outside of the transformer, as the information required to specify a transformer can be read
shown in Figure 12. The “flux band” acts as a shorted turn for directly from the completed spreadsheet. Other parameters
stray flux outside the magnetic circuit formed by the transformer must be calculated using numbers from the spreadsheet and
windings and core. Opposing currents are induced in the flux information from other sources, such as a wire table. The
band by the stray fields, partially canceling their influence. If spreadsheet parameters listed below provide information used
necessary, the flux band can also be connected to primary return to specify a transformer. The number in parentheses indicates
to help reduce electrostatically coupled interference. If a flux the cell location in the spreadsheet.
band is used, care must be taken to make sure that there is
sufficient total creepage distance from the primary pins to the • Core Type (B23)
secondary pins through the flux band. Refer to AN-15 for more • Bobbin Physical Winding Width (BW) (B27)
information on EMI reduction techniques. • Safety Margin Width (M) (B28)
• Number of Primary Layers (L) (B29)
Transformer Construction • Number of Secondary Turns (NS) (B30)
• Primary Inductance (LP) (D44)
Two transformer design and construction examples are shown • Primary Number of Turns (NP) (D45)
3 in Appendix B for margin wound and triple insulated
transformers for use with TOPSwitch. The design procedure for
the two examples utilizes computer spreadsheet techniques
described in application notes AN-16 and AN-17. The detailed
step-by-step flyback power supply design procedure for using
the spreadsheet is shown in AN-16, while the spreadsheet itself
is described in detail in AN-17. The paragraphs below describe COPPER
the procedures needed to apply the information generated by FOIL
the power supply design spreadsheet to a practical transformer
STRAP
design. These procedures are used to complete the two design
examples in Appendix B. In this application note, two completed
spreadsheet design examples are presented. Information derived
from these spreadsheets is used in the construction examples.
Spreadsheet Parameters Used for

Transformer Specification
Once a power supply design spreadsheet has been completed PI-1648-111695
and optimized, information from the spreadsheet can be used to
complete a specification for transformer construction. Much of Figure 12. Transformer Flux Band.
3-42
Rev. A 07/96
• Bias Winding Turns (NB) (D46) conductor varies as the square root of the frequency, so for a
• Gapped Core Inductance Coefficient (ALG) (C47) higher frequency, currents will flow closer to the surface of the
• Primary Wire Gauge (AWG ) (D56) conductor and leave the interior relatively unutilized. The
• Primary Winding Current Capacity (CMA) (D58) result is a higher effective resistance for AC current versus DC
• Secondary Circular Mils (CMS) (C66) current. To minimize the AC copper losses in a transformer, no
• Secondary RMS Current (ISRMS) (D62) conductor should be used that has a thickness greater than 2
• Secondary Wire Gauge (AWGS) (D67) times the skin depth at the operating frequency of the supply. A
graph of usable wire gauge as a function of frequency is shown
Transformer Construction Steps in Figure 13. At 100 KHz, the nominal operating frequency of
TOPSwitch, 26 AWG is the largest wire size that allows full
Once the transformer parameters have been determined from a utilization of the cross-section of the wire. High current windings
spreadsheet design, the following steps are required to determine at 100 KHz should be constructed using several strands of 26
the remaining information needed for transformer construction: AWG or smaller wire rather one large diameter conductor, in
order to allow full utilization of the conductor. This is usually
• Calculate and select wire sizes using spreadsheet more of a concern for selecting the wire size for a secondary
information and wire table output winding than for a primary winding.
• Pick transformer construction style
• Determine insulating tape sizes Secondary Wire Size
• Determine insulating sleeving size The minimum secondary bare wire cross-sectional area is
• Choose method of core gapping determined by the spreadsheet from the secondary RMS current,
and is sized for the same current capacity (CMA) as the primary
Wire Sizes winding. The resulting minimum wire area (in circular mils) is
displayed in cell (C66) of the spreadsheet, and is used by the
Wire sizes for the primary, secondary, and bias windings are spreadsheet to calculate a secondary wire size. If the secondary
determined from the information provided by the power supply wire size falls between two standard AWG sizes, the spreadsheet
design spreadsheet. Some extra steps may be necessary to will automatically round the wire size up to the next larger
determine the wire size for a given winding. The wire size AWG size. The resulting secondary AWG wire size is displayed
selection process is described below. in cell (D67) of the spreadsheet. In many cases, the wire size
picked by the spreadsheet will be too large to satisfy the size
Primary Wire Size requirements for 100 KHz operation described above. In these
The power supply design spreadsheet calculates the insulated cases, it will be necessary to use several parallel strands of
wire diameter for the primary based on the number of primary
turns, the number of winding layers, and the available winding
space on the bobbin. The calculated maximum insulated wire 3
diameter is shown in cell (D53) of the spreadsheet. The
spreadsheet uses this value to choose an AWG wire size that
comes closest to fitting the bobbin. If the wire size falls between MAXIMUM AWG vs. FREQUENCY
two standard AWG wire gauges, the spreadsheet will
40
PI-1906-061768
automatically round down the primary wire size to the next

smaller wire gauge. The resulting primary AWG wire size is Full
Utilization
displayed in cell (D56) of the spreadsheet. The spreadsheet 35
calculates the current capacity of the primary wire (CMA) in
AWG Wire Gauge
circular mils per ampere and displays the result in cell (D58).
30
The CMA value should be between 200 to 500 circular mils per Partial
ampere for a practical design. If the CMA is not within these Utilization
limits, the design should be adjusted to bring the primary CMA 25
within limits.
20
Wire Size vs. Frequency
In some cases, the wire size determined by the spreadsheet will
be too large for use at 100KHz. The wire size that can be 15
effectively used in a power transformer depends on the operating 104 105 106 107
frequency. High frequency currents tend to flow close to the Frequency (Hz)
surface of a conductor rather than its interior. This phenomenon
is called the skin effect. The penetration of AC current into a Figure 13. Skin Depth vs. Frequency.
3-43
Rev. A 07/96
26 AWG or smaller wire to construct a secondary winding that Choosing a Transformer Construction Type
satisfies both the CMS requirement and the 100KHz maximum
wire size requirement. The total bare area of the paralleled The transformer construction types shown in Figures 7 and 10
secondary conductors should be close to the CMS value calculated are optimized for margin wound and triple insulated wire
by the spreadsheet in cell (C66). If the total bare area is greater transformer designs for both secondary and primary regulated
than or equal to the calculated value, the wire size for the power supply designs. These construction types are suitable for
paralleled secondary winding can be used without further the majority of TOPSwitch flyback supply applications. These
checking. If the total bare area is less than the calculated value figures should be used as examples for specifying the order of
from cell (C66), the current capacity should be checked to make the transformer windings and the placement of the margins and
sure that it remains within the design limits. The current insulating sleeving (if used), and insulating tape. The
capacity of the paralleled wires can be calculated from the construction type is chosen on the basis of the supply regulation
formula: scheme (primary or secondary) and insulation type (margin
wound or triple insulated wire). Applications requiring the
lowest transformer cost but not the smallest possible transformer
N × CM size can use a margin wound transformer. Applications requiring
CMAS =
ISRMS the smallest possible transformer size should use a triple insulated
wire design.
CMAS is the current capacity of the parallel secondary winding The construction types shown in Figure 10 are low-leakage split
in circular mils per ampere, N is the number of strands in the primary designs, and should be used if the output power of the
secondary winding, CM is the bare area of a single secondary supply is greater than 40W. These designs can also be used to
conductor in circular mils (from the wire table in Appendix A), increase efficiency for a lower power supply, but will be higher
and ISRMS is the secondary RMS current from cell (D62) of the cost than a design with a one piece primary winding.
spreadsheet.
Choosing Insulation Tape Width
Bias Winding Design
The wire size for the bias winding will be determined mainly by For a margin wound transformer construction, three different
space-filling considerations rather than current capacity, as insulation tape widths are required. A tape width equal to the
described in the previous sections on transformer construction. width of the bobbin from flange to flange (BW) is required for
The wire size of the bias winding should be selected to form as reinforced insulation. This information can be read directly
complete a layer as possible. Usually, it will be necessary to use from cell (B27) of the spreadsheet. A tape width equal to the
a parallel bifilar winding in order to fill the largest possible width of the bobbin minus the width of the margins is needed for
space with a manageable wire size. In the Appendix A wire basic insulation between winding layers and adjacent primary
3 table, turns per centimeter (TC) values are given for AWG wire or secondary windings. This width can be calculated with the
sizes. This data can be used to select a bias winding wire size for equation:
a bifilar winding for a given number of turns and available
bobbin width. The required TC value can be calculated from the
equation:
WTB = BW − (2 × M )
WTB is the width of the basic insulation tape, BW is the width of
2 × N B × 10 the bobbin from cell (B27) of the spreadsheet, and M is the
TC = margin width from cell (B28). The third tape width required is
BW − (2 × M ) for the margin layers on each side of the bobbin. The width of
this tape is picked to satisfy applicable safety regulations and
TC is the turns per centimeter capability of the bias winding. NB entered in cell (B28). Triple insulated wire transformers require
is the number of bias turns from cell (D46) of the spreadsheet, one size of tape for basic insulation, with a width equal to BW.
BW is the bobbin physical winding width in mm from cell (B27)
of the spreadsheet, and M is the margin width in mm from cell Insulating Sleeving
(B28). Once the required TC is calculated, a wire size is
selected from the Appendix A wire table with a TC greater than In margin wound transformer designs, insulating sleeving is
or equal to the calculated value. The largest recommended wire required on all winding start and finish leads, so that the primary
size is 24 AWG, for ease of winding and termination. If the wire to secondary isolation provided by the margins is preserved.
size used does not form one complete layer, the winding turns The sleeving should have a wall thickness of at least 0.4 mm.
should be wound evenly across the width of the bobbin winding Sleeving for this purpose can be obtained in sizes equivalent to
area. AWG wire sizes. Usually one size of sleeving, equal to the
3-44
Rev. A 07/96
largest wire size, is sufficient for a transformer design. This size • Transformer parts list, including:
of sleeving can then be used for all other wire sizes in the
transformer. Sleeving is not required for triple insulated wire Core part number and ALG
designs. Bobbin part number
All wire types and sizes used
Transformer Gapping , Primary Inductance Tolerance All insulating tape types and widths
Insulating sleeving type and size (if used)
In standard practice, transformer cores for flyback transformer Varnish type (if used)
applications are gapped to a specified value of ALG rather than
a precise gap length. The center value of ALG can be read from • Transformer specifications:
cell (C47) of the spreadsheet. ALG is customarily specified to a
tolerance of +/- 5-6%. The gap length shown in cell (D 51) of Primary inductance and tolerance
the spreadsheet is useful mainly for checking transformer peak Primary leakage inductance and tolerance (determined
flux density and for determining the practicality of the design, from prototype)
and should not be used in a transformer specification. Applicable safety standards, or hipot test voltage and
Transformer gaps smaller than 0.051 mm (0.002 in) should be minimum creepage distances
avoided, as it is difficult to maintain tolerance on this small a
gap. Transformer primary inductance tolerance should be • Detailed construction drawing and instructions (optional)
specified at +/- 10% to +/- 15%. Tighter tolerances offer no
performance advantages, and can be unnecessarily costly. Design Summary
For high volume transformer applications, the transformer core 1) Load Design Spreadsheet with Application Variables and
is commonly gapped by grinding down the center leg of one of TOPSwitch Variables per instructions in AN-16.
the ferrite core halves to introduce a single air gap in the
magnetic path of the core. An alternate technique for small 2) Choose a core from Appendix A, and determine core and
production runs and prototypes is to use non-conducting spacers bobbin parameters needed for spreadsheet from
between the core halves. If spacers are chosen rather than manufacturer’s catalog data. Load these values into
grinding the core center leg, the spacer thickness should be half the spreadsheet.
the value used for the center leg gap, as the magnetic path is
divided twice by the spacers: once at the core center leg, and 3) Complete spreadsheet per AN-16 procedure and iterate
once at the core outer legs. until all parameters meet recommended design limits.
Completion of Transformer Specification 4) From spreadsheet values and Appendix A wire table,
calculate primary, secondary, and bias wire sizes. 3
Once the above information has been determined, there is
sufficient information to complete a specification for 5) Pick a transformer construction style depending on supply
construction of the transformer. The specification should contain regulation scheme (primary or secondary) and insulation
the following information: type (margin wound or triple insulated).
• Transformer schematic, showing all windings, order of 6) Calculate tape widths needed for transformer insulation.
windings, pin assignments, dots indicating winding starts,
turns of each winding, and wire types and sizes 7) Pick insulation sleeving size (if necessary).
8) Complete transformer specification using spreadsheet

values and information from steps 4-7.
3-45
Rev. A 07/96
Appendix A
Appendix A contains a wire table (Table 1) and a table of cores listed in Table 2 can be obtained from the ferrite core
suggested core sizes (Table 2) for use in the flyback transformer manufacturers listed in this appendix. These manufacturers
design and construction procedures described in this document. also carry a selection of bobbins for their more popular core
Also included is a list of manufacturers for transformer sizes. Additional sources for transformer bobbins are also listed
construction materials. Electrical and mechanical data on the in this appendix.
AWG SWG Metric Bare Wire Cross-Sectional TC

Wire Wire Size Area (CM)
Size Size (mm) cm210-3 CIR-MIL Turns/cm Turns/Inch
18 19 1.00 8.228 1624 9.13 23.2
19 20 0.900 6.531 1289 10.19 25.9
20 21 0.800 5.188 1024 11.37 28.9
21 0.750 4.116 812.3 12.75 32.4
22 22 0.700 3.243 640.1 14.25 36.2
23 23 0.600 2.588 510.8 15.82 40.2
24 24 0.550 2.047 404.0 17.63 44.8
25 0.450 1.623 320.4 19.80 50.3
26 28 0.400 1.280 252.8 22.12 56.2
27 29 0.350 1.021 201.6 24.44 62.1
28 30 0.320 0.8046 158.8 27.32 69.4
29 0.280 0.6470 127.7 30.27 76.9
30 33 0.250 0.5067 100.0 33.93 86.2
31 0.220 0.4013 79.21 37.48 95.2
3 32 0.200 0.3242 64.00 41.45 105.3
33 0.180 0.2554 50.41 46.33 117.7
34 0.160 0.2011 39.69 52.48 133.3
35 0.140 0.1589 31.36 58.77 149.3
36 39 0.130 0.1266 25.00 65.62 166.7
37 41 0.110 0.1026 20.25 71.57 181.8
38 42 0.100 0.08107 16.00 80.35 204.1
39 43 0.090 0.06207 12.25 91.57 232.6
40 44 0.080 0.04869 9.61 103.6 263.2
41 45 0.070 0.03972 7.84 115.7 294.1
42 46 0.060 0.03166 6.25 131.2 333.3
43 0.02452 4.84 145.8 370.4
44 0.0202 4.00 157.4 400.0
Table 1 Wire Table.
3-46
Rev. A 07/96
FERRITE CORES
Output Power
Triple Insulated Wire Construction Margin Wound Construction
0-10W EPC17 EEL16
EFD15 EF20
EE16 or EI16 EEL19
EF16 EPC25
E187 EFD25
EE19 or EI19
10-20W EE19 or EI19 EEL19
EPC19 EPC25
EF20 EFD25
EFD20 EF25
EE22 or EI22
20-30W EPC25 EPC30
EFD25 EFD30
E24/25 EF30
EI25 EI30
EF25 ETD29
EI28 EER28
30-50W EI28 EI30
EF30 ETD29
3
EI30 EER28
ETD29 EER28L
EER28 EER35
50-70W EER28L EER28L
ETD34 ETD34
EI35 EER35
EER35 ETD39
70-100W ETD34 EER35

EI35 ETD39
EER35 EER40
E21 E21
Table 2 Ferrite Core Selection Table for Transformer Construction.
3-47
Rev. A 07/96
Transformer Material Vendors EIS, 41444 Christy Street, Fremont, CA 94538 (510) 490-5855
(510) 490-2956 (FAX)
The contact numbers below are listed for information purposes
only. Please refer to local authorized representatives and Tesa Tape Inc. 5825 Carnegie Bl., Charlotte, NC 28209
distributors for pricing and ordering information. (704) 554-0707 (800) 852-8831 (FAX)
Ferrite Cores Magnet Wire
TDK Corporation, of America, 1600 Feehanville Dr. Mount Belden Wire and Cable Company, P.O. Box 1980, Richmond,
Prospect IL 60056 (847) 803-6100 (847) 803-6296 (FAX) IN 47375 (317) 983-5200 (317) 983-5656 (FAX)
Siemens Matsushita Components, Special Products Division, MWS Wire Industries 31200 Cedar Valley Dr., Westlake
186 Wood Ave, South Iselin, NJ 08830 (908) 906-4300 Village, CA 90404 (818) 991-8553 (818) 706-0911 (FAX)
(908) 632-2830 (FAX)
Phelps Dodge Magnet Wire, 2131 S. Coliseum Blvd. Fort
Philips Components, Discrete Products Division, Magnetic Wayne, IN 46803 (219) 421-5400 (219) 421-5564 (FAX)
Products, 1033 Kings Highway, Saugerties, NY 12477
(914) 246-2811 (914) 246-0486 (FAX) Rea Magnet Wire Co., Inc. 3600 E. Pontiac St. Fort Wayne, IN
46896 (219) 424-4252 (219) 421-7349 (FAX)
Tokin America, Inc.,155 Nicholson Lane, San Jose, CA 95134
(408) 432-8020 (408) 434-0375 (FAX) Triple Insulated Wire
Thomson Passive Components Corporation, 2211-H Furukawa Electric America, Inc. 200 Westpark Drive, Suite
Distribution Center Drive, Charlotte, NC 28269 190, Peachtree City, GA 30269 (770) 487-1234
(704) 597-0766 (704) 597-0553 (FAX) (770) 487-9910 (FAX)
Bobbins Furukawa Electric Co. Ltd. 6-1, Marunouchi 2-chome, Chiyoda-

ku, Tokyo 100, Japan (PH) 81-3-3286-3226
Many of the ferrite core vendors above offer compatible bobbins (FAX) 81-3-3286-3747
for their cores. Additional bobbin suppliers are listed below:
Rubudue Wire Company 5150 E. La Palma Av., Suite 108
Yih Hwa Enterprises Co., Ltd., 2 Floor, No. 2, Alley 4, Lane Anaheim Hills, CA 92807 (714) 693-5512
222 Lien Cheng Rd. Chung Ho City, Taipei, Taiwan, R.O.C. (714) 693-5515 (FAX)
3 886-2-2483366 886-2-2406919 (FAX)
Belden Wire and Cable B.V., Edisonstraat 9, P.O. Box 9, NL
Taiwan Shu Lin Enterprise Co., Ltd., 760 Chung Cheng Road, 5900 AA Venlo, Netherlands (PH) 31 773 878 442 (
Chung Ho City, Taipei Tsien, Taiwan, R.O.C. 886 2 2231500 FAX) 31 773 878 448
886 2 2224646 (FAX)
Transformer Varnishes
B&B Products Corp., 2190 Ironwood Crest Dr., Tucson, AZ
85745 (520) 743-3389 (520) 743-8000 (FAX) John C. Dolph, Co. Box 267, Monmouth Junction, NJ 08852
(908) 329-2333 (908) 329-1143 (FAX)
Miles-Platts, Inc. 901 Touhy Av., Elk Grove Village, IL 60007
(847) 364-0363 (847) 364-0614 (FAX) Schenectady Chemicals, Inc. Box 1046, Schenectady, NY
12301 (518) 370-4200 (518) 382-8129 (FAX)
Insulating Materials
P.D. George, 9 Ohio River Boulevard, Sewickley, PA 15143
3M Electrical Specialties Division, Bldg. 130-4N-40, 3M Austin (800) 999-5700 (412) 741-8892
Center, P.O. Box 2963, Austin TX 78769 (800) 364-3577
(800) 713-6329 Epoxylite Corp., 9400 Toledo Way, P.O. Box 19671, Irvine,
CA 92713 (714) 951-3231 (714) 472-0980 (FAX)
CHR/Furon, 407 East St., P.O. Box 1911, New Haven, CT
06509 (203) 777-3631 (203) 787-1725 (FAX)
3-48
Rev. A 07/96
Appendix B transformer with an EF20 core. The power supply design shown
in Figure 1 was used as a starting point for both transformer
Transformer Construction Examples design/construction examples. Target specifications for this
power supply design are shown in Table 2. Specifications and
Two transformer design and construction examples using margin selected component values from Table 2 are loaded into the
wound and triple insulated wire construction techniques are application variables section of the spreadsheets. Table 3 shows
described below. These designs are based on the 12V, 15W TOPSwitch and output rectifier operating conditions used in the
universal input power supply shown in Figure 1. The design TOPSwitch variable section of the spreadsheets. Since both of
procedure for the two examples utilizes computer spreadsheet the transformer designs are for the same power supply, the
techniques described in application notes AN-16 and AN-17. values loaded into the application variables section and
The detailed step-by-step flyback power supply design procedure TOPSwitch variable section for both spreadsheets are exactly
for using the spreadsheet is shown in AN-16. Two completed the same, with the exception of the value used for reflected
spreadsheet design examples are shown in this appendix output voltage (VOR, cell B16). For the triple insulated wire
(Table 1 and Table 6). Information derived from these transformer design shown in Table 6, VOR is adjusted to a value
spreadsheets is used in the construction examples. slightly lower than the default value recommended in AN-16 in
order to reduce the number of primary turns. This is discussed
Spreadsheet Input Parameters in the paragraphs devoted to the triple insulated wire design
example.
Two power supply design spreadsheets are shown in Tables 1
and 6. Table 1 details a power supply design utilizing a margin The transformer construction variables in the design spreadsheet
wound transformer with an EF25 core. Table 6 shows a design are determined by the core, bobbin and transformer construction
for the same power supply utilizing a triple insulated wire type, and are therefore different for the two design examples.
D2 L1
T1 VO = 12 V
MBR360 3.3 µH
9,10
PO = 15 W
1 R1
39 Ω
R2
68 Ω
C2 C3
VR1
P6KE200 680 µF 120 µF 3
25 V 25 V
U2
D1 NEC2501-H
VR2
UF4005
1N6001B
BR1 2 11 V
C1 6,7
600 V 47 µF RTN
L2
22 mH 400 V D3
1N4148
5
VB = 12 V
IB = 10 mA
C5
C6 47 µF
0.1 µF 4
10 V
X2
DRAIN
F1 SOURCE
C7
3.15 A CONTROL
1.0 nF
L Y1
U1 C4
TOP201YAI 0.1 µF
N
J1 VIN = 85-265 VAC
50/60 Hz PI-1809-031896
Figure 1. Typical TOPSwitch Power Supply for 12V, 15W Output.
3-49
Rev. A 07/96
A B C D E F
1 INPUT OUTPUT
2 ENTER APPLICATION VARIABLES
3 VACMIN 85 Volts Minimum AC Input Voltage
4 VACMAX 265 Volts Maximum AC Input Voltage
5 fL 50 Hertz AC Mains Frequency
6 fS 100000 Hertz TOPSwitch Switching Frequency
7 VO 12 Volts Output Voltage
8 PO 15 Watts Output Power
9 n 0.8 Efficiency Estimate
10 Z 0.5 Loss Allocation Factor
11 VB 12 Volts Bias Voltage
12 tC 3 mSeconds Bridge Rectifier Conduction Time Estimate
13 CIN 47 uFarads Input Filter Capacitor
14
15 ENTER TOPSWITCH VARIABLES
16 VOR 135 Volts Reflected Output Voltage
17 VDS 10 Volts TOPSwitch on-state Drain to Source Voltage
18 VD 0.4 Volts Output Winding Diode Forward Voltage Drop
19 VDB 0.7 Volts Bias Winding Diode Forward Voltage Drop
20 KRP 0.60 Ripple to Peak Current Ratio (0.4 < KRP < 1.0)
21
22 ENTER TRANSFORMER CORE/CONSTRUCTION VARIABLES
23 EF25 Core Type
24 AE 0.525 cm^2 Core Effective Cross Sectional Area
25 LE 5.75 cm Core Effective Path Length
26 AL 1800 nH/T^2 Ungapped Core Effective Inductance
27 BW 15.1 mm Bobbin Physical Winding Width
28 M 3 mm Safety Margin Width (Half the Primary to Secondary Creepage Distance)
29 L 2 Number of Primary Layers
30 NS 6 Number of Secondary Turns
31
32 DC INPUT VOLTAGE PARAMETERS
33 VMIN 9 4 Volts Minimum DC Input Voltage
34 VMAX 3 7 5 Volts Maximum DC Input Voltage
35
36 CURRENT WAVEFORM SHAPE PARAMETERS
37 DMAX 0.62 Duty Cycle at Minimum DC Input Voltage (VMIN)
38 IAVG 0.20 Amps Average Primary Current
39 IP 0.46 Amps Peak Primary Current
40 IR 0.28 Amps Primary Ripple Current
41 IRMS 0.26 Amps Primary RMS Current
42
43 TRANSFORMER PRIMARY DESIGN PARAMETERS
44 LP 1884 uHenries Primary Inductance
45 NP 65 Primary Winding Number of Turns
46 NB 6 Bias Winding Number of Turns
47 ALG 441 nH/T^2 Gapped Core Effective Inductance
48 BM 2537 Gauss Maximum Flux Density (2000 < BM < 3000)
49 BAC 761 Gauss AC Flux Density for Core Loss Curves (0.5 X Peak to Peak)
50 ur 1569 Relative Permeability of Ungapped Core
3 51
52
LG
BWE 18.2
0.11 mm
mm
Gap Length (Lg >> 0.051 mm)
Effective Bobbin Width
53 OD 0.28 mm Maximum Primary Wire Diameter including insulation
54 INS 0.05 mm Estimated Total Insulation Thickness (= 2 * film thickness)
55 DIA 0.23 mm Bare conductor diameter
56 AWG 32 AWG Primary Wire Gauge (Rounded to next smaller standard AWG value)
57 CM 64 Cmils Bare conductor effective area in circular mils
58 CMA 245 Cmils/Amp Primary Winding Current Capacity (200 < CMA < 500)
59
60 TRANSFORMER SECONDARY DESIGN PARAMETERS
61 ISP 5.03 Amps Peak Secondary Current
62 ISRMS 2.25 Amps Secondary RMS Current
63 IO 1.25 Amps Power Supply Output Current
64 IRIPPLE 1.87 Amps Output Capacitor RMS Ripple Current
65
66 CMS 550 Cmils Secondary Bare Conductor minimum circular mils
67 AWGS 2 2 AWG Secondary Wire Gauge (Rounded up to next larger standard AWG value)
68 DIAS 0.65 mm Secondary Minimum Bare Conductor Diameter
69 ODS 1.52 mm Secondary Maximum Insulated Wire Outside Diameter
70 INSS 0.44 mm Maximum Secondary Insulation Wall Thickness
71
72 VOLTAGE STRESS PARAMETERS
73 VDRAIN 6 7 8 Volts Maximum Drain Voltage Estimate (Includes Effect of Leakage Inductance)
74 PIVS 4 6 Volts Output Rectifier Maximum Peak Inverse Voltage
75 PIVB 4 7 Volts Bias Rectifier Maximum Peak Inverse Voltage
76
77 ADDITIONAL OUTPUTS
78 VX 12 Volts Auxiliary Output Voltage
79 VDX 0.7 Volts Auxiliary Diode Forward Voltage Drop
80 NX 6.15 Auxiliary Number of Turns
81 PIVX 4 7 Volts Auxiliary Rectifier Maximum Peak Inverse Voltage
82
Table 1. Design Spreadsheet for 15W Margin Wound Transformer.
3-50
Rev. A 07/96
APPLICATION VARIABLES
(INPUT TO TABLE 1 AND TABLE 6 SPREADSHEETS)
DESCRIPTION SYMBOL VALUE SOURCE CELL #
Minimum AC Input Voltage VACMIN 85 VAC Supply Specification B3
Maximum AC Input Voltage VACMAX 265 VAC Supply Specification B4
AC Mains Frequency fL 50 Hz Supply Specification B5
TOPSwitch Switching fS 100,000 Hz AN-16 Default Value B6

Frequency
Output Voltage VO 12 V Supply Specification B7
Output Power PO 15 W Supply Specification B8
Estimated Efficiency η 0.8 AN-16 Default Value B9
Loss Allocation Factor Z 0.5 AN-16 Default Value B10
Bias Voltage VB 12 V Supply Specification B11
Bridge Rectifier tC 3 msec AN-16 Default Value B12

Conduction Time Estimate
Input Filter Capacitor (C1) CIN 47 µF AN-16 Default Value B13
Table 2. Application Variables for Design Spreadsheets for Figure 1 Power Supply .
The spreadsheets for the two designs diverge at this point. The the spreadsheet design are Ae, Le, and AL, and are loaded into
following paragraphs will describe completed construction spreadsheet cells (B24), (B25), and (B26) respectively. A 3
examples; first for the margin wound design, then the triple margin width (M) of 3 mm (0.118 in) is chosen for the margin
insulated wire design. wound design to meet international safety regulations for
universal input voltage range, and loaded into cell (B28). The
Margin Wound Construction Example number of primary layers (B29) is set at 2 to optimize the core
size and to reduce the transformer leakage inductance and stray
In order to carry the margin wound example to completion, the capacitance.
remainder of the design parameters needed to complete the
Table 1 spreadsheet input section are described. The construction The variable BW (Bobbin Physical Winding Width), required
example is then completed with the information from the for the transformer design spreadsheet, represents the width of
spreadsheet. the bobbin available for winding. This value can be read directly
from many bobbin specifications. However, in some cases it is
Determining Transformer Construction Variables not given directly, and must be calculated from the minimum
In order to complete the input portion of the Table 1 spreadsheet, total bobbin width and the maximum width of the bobbin end
information is needed for the transformer/core construction flanges. The EF25 bobbin drawing shown in Figure 3 does not
variable section. Table 4 shows the transformer core/construction show a value for BW. Instead, the total bobbin width (WT) and
variables chosen for this margin wound transformer construction flange width (WF) are given, including tolerances. BW can be
example. The EF25 core is chosen from the transformer core calculated from these values using the equation:
chart in Appendix A as representative for the power level and
construction type. Dimensional and electrical characteristics
for the core and a compatible bobbin are shown in [
BW = WT ( MIN ) − 2 × WF ( MAX ) ]
Figures 2 and 3. The core electrical parameters necessary for
3-51
Rev. A 07/96
TOPSwitch VARIABLES
(INPUT TO TABLE 1 AND TABLE 6 SPREADSHEETS)
Reflected Output Voltage VOR 135 V*/130V** *AN-16 Default Value B16
**(See Text)
TOPSwitch Drain to Source VDS 10 V AN-16 Default Value B17

Voltage with MOSFET on
Output Diode (D2) VD 0.4 V Estimated B18

Forward Voltage Drop
Bias Diode (D3) VDB 0.7 V Estimated B19

Forward Voltage Drop
Primary Current Ripple KRP 0.6 Optimized Through B20

to Peak Ratio Iteration
Table 3. TOPSwitch Variables for Design Spreadsheets.
WT(MIN) is the minimum total bobbin width, and WF(MAX) is the Primary Wire Size
maximum flange width. For the bobbin in Figure 3, WT(MIN) is From cell (D56) of the Table 1 spreadsheet, the wire size is
16.7 mm and WF(MAX) is 0.8 mm. For these values, BW is: given as 32 AWG. The primary winding current capacity is
given in cell (D58) as 245 circular mils/ampere, and meets the
current capacity guideline of 200-500 circular mils/ampere.
BW = 16.7 − (2 × 0.8) = 15.1mm This wire size is also suitable for use at 100 KHz, as its diameter
is smaller than twice the 100KHz skin depth, as shown by
Figure 13.
3 This BW value is entered into cell B27 of the spreadsheet.
Secondary Wire Size
The optimum number of secondary turns, NS (B30), for a Looking at cell (B66) of the spreadsheet, a secondary bare wire
transformer design is a function of the power supply input area of 550 circular mils is required to make the secondary
voltage range, the desired KRP, and the effective core cross- CMA equal to the primary CMA. From cell (D67) of the
sectional area Ae. Using the spreadsheet, it is a simple matter to Table 1 spreadsheet, the closest AWG wire size that can satisfy
iterate the value for NS until a design is reached that fits on the this requirement with a single wire is 22 AWG. This wire size
desired transformer core and bobbin and results in satisfactory is too large for use at 100KHz, and several parallel wires, size
values for primary winding current capacity (CMA), Gap 26 AWG or smaller, should be used instead to allow full
Length (LG), and maximum flux density (BM). Suggested starting utilization of the wire cross-sectional area. From the wire table
values for NS in terms of volts per turn are found in AN-16. For in Appendix A, it can be seen that two parallel strands of 26
this design using the EF25 core, the optimum NS after iteration AWG wire (CM of 252.8 circular mils per wire) have a total
is 6 turns. At this point the spreadsheet design is complete, and bare wire area of 505.6 circular mils, which is within 10% of
the transformer construction example can proceed using the the required CM of 550 circular mils. The current capacity of
output data from the completed and optimized spreadsheet. the parallel winding can be calculated from the formula:
Margin Wound Example Completion N × CM

CMAS =
The parameters needed to specify the margin wound transformer ISRMS
design are shown in Table 5. The spreadsheet parameters from
Table 1 are used to determine the transformer wire size, tape CMAS is the current capacity of the secondary winding in
sizes, and sleeving size. circular mils per ampere, N is the number of strands in the
3-52
Rev. A 07/96
TRANSFORMER CONSTRUCTION VARIABLES

(INPUT TO TABLE 1 SPREADSHEET)
Core Type - EF25 Core Specifications B23
Core Effective Cross Ae 0.525 cm2 Core Specifications B24

Sectional Area
Core Effective Path Length Le 5.75 cm Core Specifications B25
Core Ungapped AL 1800 nH/T2 Core Specifications B26

Inductance Coefficient
Bobbin Physical BW 15.1 mm Calculated from Bobbin B27

Winding Width Specifications
Margin Width M 3 mm Default Value from B28

AN-16
Number of Primary L 2 Default Value from B29

Winding Layers AN-16
Number of NS 6t See Text B30

Secondary Turns
Table 4. Transformer Construction Variables for EF25 Margin Wound Transformer Design.
+0.5 (WT)
8.7 27.5 -0.3
12.8 (WF)
-0.5 17.3 17
-0.25 -0.3 0.7 ±0.1
7.7 0.7 ±0.1
Electrical +0.15
Characteristics
+0.8 Ae =0.525 cm2

7.7 +0.2
25
17.8 max
-0.25
-0.7
+0.8
9.4
17.5 le = 5.75 cm
7.5
-0.5 AL= 1800 nH/T2
3.5 -0.5
2.2 -0.1
7.5
-0.6
0.7
All Dimensions are in mm All Dimensions are in mm PI-1797-030896

PI-1796-030896
Figure 2. EF25 Core. Figure 3. EF25 Bobbin.
3-53
Rev. A 07/96
MARGIN WOUND DESIGN TRANSFORMER CONSTRUCTION

PARAMETERS FROM TABLE 1 SPREADSHEET
DESCRIPTION SYMBOL VALUE CELL #
Core Type, Material - EF25, Siemens N67 -

Part# B66317-G-X130
Bobbin Type - EF25, 10 PIN, Siemens PIN -

B66208-A 1110-T1
Number of Primary Turns NP 65 T D45
Number of Secondary Turns NS 6T B30
Number of Bias Winding Turns NB 6T D46
Primary Wire Size AWG 32 AWG D56
Secondary Wire Size AWGS 26 AWG D67 (See Text)
Bias Winding Wire Size AWGB 24 AWG See Text
Core Gapped Inductance ALG 441 nH/T2 ±5% C47

Coefficient
Primary Inductance LP 1884 µH +/-10% D44
Reinforced Insulation BW 15.1 mm B27

Tape Width
Basic Insulation WTB 9.1 mm See Text

3 Tape Width
Margin Tape Width M 3 mm B28
Sleeving Size - 24 AWG See Text
Table 5. Construction Parameters for Margin Wound Design Example.
secondary winding, CM is the bare area of a single secondary 2 × 252.8

conductor in circular mils (from the wire table in Appendix A), CMAS = = 224.7 circular mils/ampere
and ISRMS is the secondary RMS current from cell (D62) of the
2.25
spreadsheet. 26 AWG wire has a bare area of 252.8 circular
mils. Two parallel strands of 26 AWG wire have a current This value is close to the primary current capacity (within
capacity of: 10%), and satisfies the CMA design limits.
3-54
Rev. A 07/96
Bias Wire Size Tape Sizes

The bias winding wire size is chosen to fill as much of the For a margin wound design, three sizes of tape are required for
bobbin width as possible. Since there are usually relatively few reinforced insulation, basic insulation, and margins. The tape
primary bias winding turns, this is best accomplished by using width required for the reinforced insulation layers on this
a bifilar winding rather than a large diameter wire, effectively transformer is equal to BW. From cell (B27) of the Table 1
doubling the number of physical turns. The required TC can be spreadsheet, this is 15.1 mm. The width WTB of the basic
calculated as follows: insulation tape is calculated as:
2 × N B × 10 2 × 6 × 10 WTB = BW − (2 × M ) = 15.1 − (2 × 3) = 9.1mm

TC = =
BW − (2 × M ) 15.1 − (2 × 3) The margin tape width (M) is read from cell (B28) of the
= 13.2turns / cm spreadsheet, and is set at 3 mm to meet international safety
regulations for creepage distance for universal input.
From the wire table in Appendix A, the closest wire size with
TC greater than or equal to 13.2 turns/cm is 22 AWG, with a TC Insulating Sleeving Size
of 14.25 turns/cm. This is too large a wire size to use with an The insulating sleeving size required for this transformer deign
EF25 core and bobbin. As a compromise, 24 AWG wire is used is equivalent to the largest wire size in the transformer, or
instead. This wire size will not completely cover the available 24 AWG. The sleeving should have a wall thickness of at least
bobbin width, but is an acceptable compromise for the sake of 0.4 mm to meet international safety regulations.
manufacturability. Since the output current of this winding is
10 mA or less, there is no need to consider the current capacity Gapped Core Inductance Coefficient
of the wire or high frequency skin effect. The wire size in this The ALG for this transformer design is given in cell (C47) of the
case is determined by space-filling requirements rather than design spreadsheet, and should be used as the center value for
current capacity. specifying the core ALG on the transformer specification.
Transformer Construction Style Finished Margin Wound Transformer Design

Since this transformer is a margin wound design for a secondary The information required to assemble a transformer specification
regulated application, appropriate construction styles are for the margin wound transformer example is summarized in
Figures 7A and 10A. Because this design is for a 15W Table 5. A completed transformer schematic diagram and parts
application, the split primary winding shown in Figure 10A is list are shown in Figure 4. A construction drawing is shown in
not necessary, and more cost effective single section primary Figure 5.
design of Figure 7A should be used.
3
3-55
Rev. A 07/96
Pin 1
Primary
65T Pin 9, 10
#32 AWG
Bifilar SPECIFICATIONS
Pin 2 12V Secondary
Pin 4 6T Primary Inductance - 1884 µH ±15%
2x #26 AWG Leakage Inductance < 45 µH
Bifilar
Primary Bias Pin 6, 7
6T
2x #24 AWG
Pin 5
PARTS LIST FOR EF25 TRANSFORMER DESIGN EXAMPLE
Item Amt. Description Part # Manufacturer
1 1pr. Core, EF25 N67 Mat'l B66317-G-X167* Siemens
2 1ea. Bobbin, EF25, 10 pin B66208-A1110-T1 Siemens
3 3 A/R Wire, 32 AWG Heavy Nyleze
4 A/R Wire, 24 AWG Heavy Nyleze
6 A/R Tape, Polyester 3.0 mm wide #44 3M
9 A/R Tubing, Teflon, 24 AWG, 0.4 mm

minimum wall thickness
2
*Gap for ALG of 441 nH/T ± 5%
PI-1805-031196
Figure 4. Parts List for EF25 Transformer Design Example.
3-56
Rev. A 07/96
MARGIN WOUND TRANSFORMER CONSTRUCTION
6,7
9,10
4
5 MARGINS
1
2
WINDING INSTRUCTIONS
Margins Apply 3mm tape margins as shown.
Two-layer "C" Wound Primary Start at pin 2. Wind 33 turns of 32 AWG heavy nyleze
magnet wire from left to right. Apply 1 layer of polyester
tape, 9.1 mm wide, for basic insulation. Continue
winding 32 turns from right to left. Finish at pin 1.
Sleeve start and finish leads.
Basic Insulation Apply 1 layer of 9.1 mm wide tape for basic

insulation.
Primary Bias Start at pin 5. Wind 6 bifilar turns of 24 AWG heavy

(Bifilar) nyleze magnet wire in a single layer, from left to right.
Finish at pin 4. Sleeve start and finish leads.
Reinforced Insulation Apply 3 layers of 15.1 mm wide polyester film tape, 3

for reinforced insulation.
Margins Apply 3 mm tape margins as shown.
Parallel Bifilar Secondary Start at pins 9 & 10. Wind 6 bifilar turns of 26 AWG
heavy nyleze magnet wire in 1 layer from left to right.
Finish at pins 6 & 7. Sleeve start and finish leads.
Outer Insulation Apply 3 layers of 15.1 mm wide tape for outer

insulation.
Final Assembly Assemble and secure core halves.

Impregnate uniformly with varnish.
PI-1806-030896
Figure 5. EF25 Margin Wound Construction Example.
3-57
Rev. A 07/96
Triple Insulated Wire Construction Example 200-500 circular mils/ampere. The CMA and resulting AWG
values in the spreadsheet are dependent variables and cannot be
In the following paragraphs, the design parameters needed to adjusted directly. The number of primary turns in the spreadsheet
complete the Table 6 spreadsheet input section will be described. cannot be manipulated directly, as it is a function of the number
A triple insulated wire transformer construction example will of secondary turns. Gross adjustments can be made indirectly
then be completed with the information from the spreadsheet. to the primary CMA value by changing the number of secondary
turns (NS) or the core size (see AN-16). Adjusting the number
Determining Transformer Construction Variables of secondary turns changes the number of primary turns
In order to complete the input portion of the Table 6 spreadsheet, proportionally to maintain the reflected output voltage, VOR, at
information is needed for the transformer/core construction its specified value. Changing the core size changes the available
variable section. Table 7 shows the transformer core/construction bobbin width (BW). The spreadsheet will change the primary
variables chosen for the triple insulated transformer construction wire size to fill the available bobbin width using the specified
example. The EF20 core was chosen from the transformer core number of primary winding layers.
chart in Appendix A. Dimensional and electrical characteristics
for the core and a compatible bobbin are shown in Figures 6 and In some cases, changing the number of secondary turns results
7. The core electrical parameters necessary for the spreadsheet either in too large a change in primary wire size or has a
design are Ae, Le, and AL, and are loaded into spreadsheet cells deleterious effect on other parameters, such as maximum flux
(B24), (B25), and (B26), respectively. Margin width (M) was density or transformer gap length. Also, it may not be desirable
set to zero for the triple insulated wire design and loaded into to change the core size for reasons of cost, availability, or size
cell (B28). The number of primary layers (B29) is set at 2 to constraints. The following techniques are useful for fine
optimize the core size and to reduce the transformer leakage adjustment of the AWG and CMA of the primary winding
inductance and stray capacitance. BW (Bobbin Physical Winding without changing the core/bobbin size or the number of
Width) is calculated as in the margin wound example, since it secondary turns:
is not directly available from the Figure 7 bobbin drawing.
WT(MIN) is 13.4 mm and WF(MAX) is 0.7 mm, so BW for the EF20 • To reduce the primary wire size to a slightly smaller value,
bobbin is: adjust the number of primary layers to a value less than the
default value of 2 layers in increments of 0.1 layer (for
[
BW = WT ( MIN ) − 2 × WF ( MAX ) ] example, try 1.9 layers, 1.8 layers, etc.).
= 13.45 − (2 × 0.7) ≅ 12.0 mm • To increase the primary wire size to a slightly larger value,
adjust the reflected voltage VOR downward in increments
This BW value is entered into cell (B27) of the Table 6
of 1-2 volts. This will slightly reduce the number of
spreadsheet. The optimum number of secondary turns, NS
primary turns. Maximum duty cycle (DMAX) will be reduced
3 (B30), is determined as 9 turns after iteration. The number of
primary layers (B29) is set at 2 to optimize the core size and to
slightly, LG will become smaller and BM will rise slightly.
Do not adjust the reflected primary voltage more than 10%
reduce the transformer leakage inductance and stray capacitance.
below the maximum recommended value suggested in
AN-16. If more adjustment is needed, reduce the number
Completion of Triple Insulated Wire
of secondary turns instead or use a larger core size.
Transformer Example
Initially, the Table 6 spreadsheet used the default value of 135V
Information necessary to specify the triple insulated wire
for VOR in cell (B16). For NS = 9 turns, this resulted in NP = 96
transformer example is shown in Table 8. The entries in
turns, and a primary wire size of 33 AWG, which for this design,
Table 8 were taken directly from the Table 6 spreadsheet or
is slightly too small (CMA of 196 circular mils/ampere) to
calculated from the spreadsheet values. Unlike the Table 1
satisfy the CMA requirement of 200-500 circular mils/ampere.
spreadsheet design for the EF25 transformer, the Table 6
Adjusting the number of primary turns by reducing the secondary
spreadsheet requires one additional iteration cycle to optimize
turns resulted in a transformer design with a maximum flux
the primary wire size. This iteration cycle and the remaining
density larger than the design limit of 3000 Gauss. To avoid this
steps in the transformer design are described below.
condition, the number of primary turns was instead reduced
from 98 turns to 94 turns by reducing VOR from 135V to 130V
Adjusting Primary Wire Size and CMA
in small steps. This allowed the primary wire size, AWG (D56),
The design spreadsheet adjusts the primary wire size to the
to change from 33 AWG to 32 AWG and brought the primary
closest AWG value that will fit within the available bobbin
winding CMA (D58) up to 243 circular mils/ampere. Maximum
width. In some cases the AWG wire size given by the spreadsheet
duty cycle and maximum flux density were only slightly
may result in a CMA value outside of the desired range of
affected by this change.
3-58
Rev. A 07/96
A B C D E F
1 INPUT OUTPUT
2 ENTER APPLICATION VARIABLES
6 fS 100000 Hertz TOPSwitch Switching Frequency
7 VO 12 Volts Output Voltage
8 PO 15 Watts Output Power
9 n 0.8 Efficiency Estimate
10 Z 0.5 Loss Allocation Factor
11 VB 12 Volts Bias Voltage
12 tC 3 mSeconds Bridge Rectifier Conduction Time Estimate
13 CIN 47 uFarads Input Filter Capacitor
14
15 ENTER TOPSWITCH VARIABLES
16 VOR 130 Volts Reflected Output Voltage
17 VDS 10 Volts TOPSwitch on-state Drain to Source Voltage
18 VD 0.4 Volts Output Winding Diode Forward Voltage Drop
19 VDB 0.7 Volts Bias Winding Diode Forward Voltage Drop
20 KRP 0.60 Ripple to Peak Current Ratio (0.4 < KRP < 1.0)
21
22 ENTER TRANSFORMER CORE/CONSTRUCTION VARIABLES
23 EF20 Core Type
24 AE 0.335 cm^2 Core Effective Cross Sectional Area
25 LE 4.49 cm Core Effective Path Length
26 AL 1470 nH/T^2 Ungapped Core Effective Inductance
27 BW 12 mm Bobbin Physical Winding Width
28 M 0 mm Safety Margin Width (Half the Primary to Secondary Creepage Distance)
29 L 2 Number of Primary Layers
30 NS 9 Number of Secondary Turns
31
33 VMIN 9 4 Volts Minimum DC Input Voltage
34 VMAX 3 7 5 Volts Maximum DC Input Voltage
35
36 CURRENT WAVEFORM SHAPE PARAMETERS
37 DMAX 0.61 Duty Cycle at Minimum DC Input Voltage (VMIN)
38 IAVG 0.20 Amps Average Primary Current
39 IP 0.47 Amps Peak Primary Current
40 IR 0.28 Amps Primary Ripple Current
41 IRMS 0.26 Amps Primary RMS Current
42
43 TRANSFORMER PRIMARY DESIGN PARAMETERS
44 LP 1829 uHenries Primary Inductance
45 NP 94 Primary Winding Number of Turns
46 NB 9 Bias Winding Number of Turns
47 ALG 205 nH/T^2 Gapped Core Effective Inductance
48 BM 2712 Gauss Maximum Flux Density (2000 < BM < 3000)
49 BAC 814 Gauss AC Flux Density for Core Loss Curves (0.5 X Peak to Peak)
50 ur 1568 Relative Permeability of Ungapped Core
51
52
LG
BWE 24
0.18 mm
mm
Gap Length (Lg >> 0.051 mm)
Effective Bobbin Width
3
53 OD 0.25 mm Maximum Primary Wire Diameter including insulation
54 INS 0.05 mm Estimated Total Insulation Thickness (= 2 * film thickness)
55 DIA 0.21 mm Bare conductor diameter
56 AWG 32 AWG Primary Wire Gauge (Rounded to next smaller standard AWG value)
57 CM 64 Cmils Bare conductor effective area in circular mils
58 CMA 243 Cmils/Amp Primary Winding Current Capacity (200 < CMA < 500)
59
60 TRANSFORMER SECONDARY DESIGN PARAMETERS
61 ISP 4.91 Amps Peak Secondary Current
62 ISRMS 2.22 Amps Secondary RMS Current
63 IO 1.25 Amps Power Supply Output Current
64 IRIPPLE 1.84 Amps Output Capacitor RMS Ripple Current
65
66 CMS 540 Cmils Secondary Bare Conductor minimum circular mils
67 AWGS 2 2 AWG Secondary Wire Gauge (Rounded up to next larger standard AWG value)
68 DIAS 0.65 mm Secondary Minimum Bare Conductor Diameter
69 ODS 1.33 mm Secondary Maximum Insulated Wire Outside Diameter
70 INSS 0.34 mm Maximum Secondary Insulation Wall Thickness
71
72 VOLTAGE STRESS PARAMETERS
73 VDRAIN 6 6 8 Volts Maximum Drain Voltage Estimate (Includes Effect of Leakage Inductance)
74 PIVS 4 8 Volts Output Rectifier Maximum Peak Inverse Voltage
75 PIVB 4 9 Volts Bias Rectifier Maximum Peak Inverse Voltage
76
77 ADDITIONAL OUTPUTS
78 VX 12 Volts Auxiliary Output Voltage
79 VDX 0.7 Volts Auxiliary Diode Forward Voltage Drop
80 NX 9.22 Auxiliary Number of Turns
81 PIVX 4 9 Volts Auxiliary Rectifier Maximum Peak Inverse Voltage
82
Table 6. Design Spreadsheet for 15 W Triple Insulated Wire Transformer.
3-59
Rev. A 07/96
TRANSFORMER CONSTRUCTION VARIABLES

(INPUT TO TABLE 6 SPREADSHEET)
Core Type - EF20 Core Specification B23
Core Effective Cross Ae 0.335 cm2 Core Specification B24

Sectional Area
Core Effective Path Length Le 4.49 cm Core Specification B25
Core Ungapped AL 1470 nH/T2 Core Specification B26

Inductance Coefficient
Bobbin Physical Winding Width BW 12.0 mm Calculated from Bobbin B27

Specification
Margin Width M 0 Default Value from B28

AN-16
Number of Primary L 2 Default Value from B29

Winding Layers AN-16
Number of NS 9t See Text B30

Secondary Turns
Table 7. Transformer Construction Variables for EF20 Triple Insulated Wire Design.
+0.5 (WT)
7 22 -0.3 (WF)
10.2 13.7
-0.4 13.9
-0.25 -0.25 0.6 ±0.1
6.1 0.6 ±0.1
Electrical +0.15
Characteristics
20.4 Ae = 0.335 cm2

6.1 +0.2
14.6 max
-0.15
-0.8
+0.6
7.6
14.1 le = 4.49 cm
5.9
-0.4 AL = 1470 nH/T2
3.5 -0.5
2 -0.1
5.9
-0.5
0.45
All Dimensions are in mm PI-1821-040296 All Dimensions are in mm PI-1822-040296
Figure 6. EF20 Core. Figure 7. EF20 Bobbin.
3-60
Rev. A 07/96
TRIPLE INSULATED WIRE TRANSFORMER CONSTRUCTION

PARAMETERS FROM TABLE 6 SPREADSHEET
DESCRIPTION SYMBOL VALUE CELL #
Core Type, Material, - EF20, Siemens N67 -

Part # Part# B66311-G-X130
Bobbin Type, - EF20, 10 PIN, Siemens PIN -

Part # B66206-A 1110-T1
Number of Primary Turns NP 94 turns D45
Number of Secondary Turns NS 9 turns B30
Number of Bias Winding Turns NB 9 turns D46
Primary Wire Size AWG 32 AWG D56
Secondary Wire Size AWGS 26 AWG Triple Insulated D67 (See Text)
Bias Winding Wire Size AWGB 24 AWG See Text
Core Gapped Inductance ALG 205 nH/T2 ±5% C47

Coefficient
Primary Inductance LP 1829 µH +/-10% D44
Reinforced Insulation BW N/A B27

Tape Width
Basic Insulation 12.0 cm See Text

Tape Width 3
Margin Tape Width M N/A B28
Sleeving Size - N/A N/A
Table 8. Construction Parameters for Triple Insulated Wire Design Example.
Secondary Wire Size circular mils. The current capacity of the parallel winding can
From cell ( B66) of the Table 6 spreadsheet, a secondary bare be calculated from the formula:
wire area of 540 circular mils is required to make the secondary
CMA equal the primary CMA. From cell (D67), the closest N × CM
AWG wire size that can satisfy this requirement with a single CMAS =
wire is calculated as 22 AWG. This wire size is too large for use ISRMS
at 100KHz, and several smaller parallel wires should be used
instead to allow full utilization of the wire cross-sectional area. CMAS is the current capacity of the secondary winding in
From the wire table in Appendix A, it can be seen that two circular mils per ampere, N is the number of strands in the
parallel strands of 26 AWG triple insulated wire (CM of 252.8 secondary winding, CM is the bare area of a single secondary
circular mils per wire) have a total bare wire area of 505.6 conductor in circular mils (from the wire table in Appendix A),
circular mils, which is within 10% of the required CM of 540 and ISRMS is the secondary RMS current from cell (D62) of the
3-61
Rev. A 07/96
spreadsheet. 26 AWG wire has a bare area of 252.8 circular or less, there is no need to consider the current capacity of the
mils. Two parallel strands of 26 AWG triple insulated wire have wire. The wire size in this case is determined by fill factor
a current capacity of: requirements rather than current capacity.
Transformer Construction Style

2 × 252.8 Since this transformer is a triple insulated wire design for a
CMAS = = 224.7 circular mils/ampere
2.25 secondary regulated application, appropriate construction styles
are Figure 7B and 10B. Because this design is for a 15W
This value is within 10% of the primary CMA of 243 circular application, a split primary winding as shown in Figure 10B is
mils/ampere, and satisfies the CMA limit of 200-500 circular not necessary, and the more cost effective single section primary
mils per ampere. design of Figure 7B should be used.
Bias Wire Size Tape Sizes

The bias winding wire size is chosen to fill as much of the Since this is a triple insulated design, one size of tape is required
bobbin width as possible. Since there are usually relatively few for basic insulation, with a width equal to BW. From cell (B27)
turns on the primary bias winding, this is best accomplished by of the Table 6 spreadsheet, this is 12.0 mm.
using a bifilar winding rather than a large diameter wire,
effectively doubling the number of physical turns. The required Insulating Sleeving Size
TC to fill a single layer can be calculated as follows: Since this is a triple insulated wire design, no sleeving is
required
2 × N B × 10 2 × 9 × 10 Gapped Core Inductance Coefficient

TC = = The ALG for this transformer design is given in cell (C47) of the
BW − (2 × M ) 12 − (2 × 0)
design spreadsheet, and should be used as the center value for
= 15turns / cm specifying the core ALG on the transformer specification.
From the wire table, the closest wire size with a TC greater than Finished Triple Insulated Wire Transformer Design
or equal to this value is 23 AWG, with a TC of 15.82 turns/cm. The information required to assemble a transformer specification
This wire is too large to use with a small bobbin. A compromise for the triple insulated wire transformer example is summarized
is to use the next smallest size, 24 AWG, which will not fill the in Table 8. A completed transformer schematic diagram and
bobbin width completely, but is easier to terminate to the parts list are shown in Figure 8. A construction drawing is
bobbin pins. Since the output current of this winding is 10 mA shown in Figure 9.
3-62
Rev. A 07/96
Pin 1
Primary
94T Pin 9, 10
#32 AWG
Bifilar
12V Secondary SPECIFICATIONS
Pin 2 9T
Pin 4 2x #26 AWG Primary Inductance - 1829 µH ±15%
Bifilar Triple Insulated Leakage Inductance < 40 µH
Primary Bias Pin 6, 7
9T
2x #24 AWG
Pin 5
PARTS LIST FOR EF20 TRANSFORMER DESIGN EXAMPLE
Item Amt. Description Part # Manufacturer
1 1pr. Core, EF20 N67 Mat'l B66311-G-X167 Siemens* 3

2 1ea. Bobbin, EF20, 10 pin B66206-A1110-T1 Siemens
5 A/R Wire, 26 AWG Triple Insulated
*Gap for ALG of 205 nH/T2 ±5%
PI-1815-040896
Figure 8. Parts List for EF20 Transformer Design Example.
3-63
Rev. A 07/96
TRIPLE INSULATED TRANSFORMER CONSTRUCTION
6,7
9,10
4
5
1
2
WINDING INSTRUCTIONS
Two-layer "C" Wound Primary Start at pin 2. Wind 47 turns of 32 AWG heavy nyleze
wire from left to right. Apply 1 layer of polyester film
tape, 12.0 mm wide, for basic insulation. Continue
winding 47 turns from right to left. Finish at pin 1.
Basic Insulation Apply 1 layer of 12.0 mm wide tape for basic

insulation.
Primary Bias Start at pin 5. Wind 9 bifilar turns of 24 AWG heavy

(Bifilar) nyleze wire in a single layer, from left to right. Finish at
pin 4.
3 Basic Insulation Apply 1 layer of 12.0 mm wide tape for basic insulation.
Parallel Bifilar Triple Start at pin 9 & 10. Wind 9 bifilar turns of 26 AWG
Insulated Secondary triple insulated wire in approximately 1 layer from
left to right. Finish at pin 6 & 7.
Outer Insulation Apply 3 layers of 12.0 mm wide tape for outer

insulation.
Final Assembly Assemble and secure core halves.

Impregnate uniformly with varnish.
PI-1816-032896
Figure 9. EF20 Triple Insulated Design Example.
3-64
Rev. A 07/96
References 6) Col. William McLyman, Magnetic Core Selection for

Transformers and Inductors, New York, Marcel Dekker, Inc.,
1) Power Integrations, Inc., AN-15, "Power Supply Design 1982
Techniques for EMI and Safety"
7) Abraham I. Pressman, Switching Power Supply Design (2nd
2) Power Integrations, Inc., AN-16, "TOPSwitch Flyback ed.), New York, McGraw-Hill, Inc., 1991
Fundamentals"
8) Ferdinand C. Geerlings, “SMPS Power Inductor and
3) Power Integrations, Inc., AN-17, “Flyback Transformer Transformer Design, Part 1”, Powerconversion International,
Design for TOPSwitch Power Supplies” November/December 1979, pp. 45-52
4) Power Integrations, Inc. DN-8, “Simple Bias Supplies Using 9) Ferdinand C. Geerlings, “SMPS Power Inductor Design and
the TOP200” Transformer Design, Part 2”, Powerconversion International,
January/February 1980, pp. 33-40
5) Col. William McLyman, Transformer and Inductor Design
Handbook, New York, Marcel Dekker, Inc., 1978 10) Coilcraft, Inc., Technical Note Number 8110, “V.D.E.
Transformer Safety Requirements”
3-65
Rev. A 07/96
®
TOPSwitch-GX
Flyback Quick Selection Curves
Introduction
QUICK START
This application note is intended for engineers starting a flyback
power supply design with TOPSwitch-GX. It offers a quick
method to select the proper TOPSwitch-GX device from 1) Determine which graph (Fig. 1, 2, 3 or 4) is closest to
parameters that are usually not available until much later in the your application. Example: Use Figure 1 for Universal
design process. Input, 12 V output.
Curves estimating the efficiency of the power supply and the 2) Find your power requirement on the X-axis.
corresponding TOPSwitch-GX device dissipation are provided.
They form a powerful tool for estimating cost and project 3) Move vertically from your power requirement until
requirements before even committing to or starting development. you intersect with a TOPSwitch-GX curve (solid line).
This application note is similar to both AN-21 for
TOPSwitch-II and AN-26 for TOPSwitch-FX. 4) Read the associated Efficiency on the Y-axis.
Overview of Quick Selection Curves 5) Determine if this is the appropriate Efficiency for your
application. If not, continue to the next TOPSwitch-GX
The TOPSwitch-GX Quick Selection Curves (Figures 1-4) curve.
show the expected power supply efficiency and TOPSwitch-GX
dissipation for typical flyback applications. Power supplies 6) Read the TOPSwitch-GX power dissipation from the
with either a 5 V or a 12 V output, operating with either dashed contours to determine heatsink requirements.
‘Universal Input’ (85 VAC-265 VAC) or ‘Single 230 VAC
Input’ (195 VAC-265 VAC) are described. 7) If the device dissipation is 0.85 W then the lower cost
P/G packages can be considered.
The solid lines in the Quick Selection Curves give a typical
3 efficiency figure for a given load, depending upon the 8) Start the design. Use the TOPSwitch-GX Transformer
TOPSwitch-GX device used. Each solid line efficiency curve Design Spreadsheet or PI Expert.
extends to the maximum power capability of the device, limited
by device current limit. The superimposed dashed lines are Note: See ‘Selection Curve Assumptions’ for limits of use.
contours of constant TOPSwitch-GX device dissipation, the
intersections of these dashed lines with the solid lines provide
the corresponding dissipation at different loads. Interpolation have lower current limits than their Y packaged counterparts to
or extrapolation can find the dissipation at intermediate points. match device dissipation to package capability.
The shaded region indicates the output power where a flyback When using the curves for different output voltages the reader
design at the given output voltage is no longer practical. This should be aware that altering the output voltage will give
limit has been shown at an output current of 10 A and above. dramatic changes in efficiency.
Higher output currents are possible but such a design is typically
not cost effective due to the size of the output diode and For voltages between 5 V and 12 V the data from both curves
capacitors. Higher output power can be obtained if the output can be used to extrapolate an intermediate point. Lower
voltage is higher. voltages will give lower efficiencies and limit maximum power
capability. Higher voltages will give higher efficiencies and
The curves can be used for both P (DIP-8), G (SMD-8) and Y greater power. For example from the curves a 12 V, 70 W
(TO-220) packaged devices, however for the P and G parts the universal design using the TOP249 has an estimated efficiency
dissipation must be limited to 0.85 W. This is due to the thermal of 79.5%. If the output voltage were increased to 19 V this
constraints of the P package. The P and G parts intentionally would increase to approximately 85%. Similarly an open frame
3-66
Rev. D 02/03
230 VAC, 250 W design is possible with the TOP249 at an 0.4 V. The 12 V output curves use a Schottky diode with a
output voltage of 48 V with an efficiency of 84.5%. Note that forward voltage drop of 0.54 V.
curves for 19 V and 48 V are not provided.
Besides the design criteria above, typical power supply
Selection Curve Assumptions component parameters used in generating the data for the Quick
Selection Curves are provided in Tables 1 to 4. For 5 V designs
The Selection Curves are based on specific design assumptions using the TOP246 or larger the secondary trace inductance must
that are detailed below: be reduced as the output power increases to limit clamp
dissipation. This is reflected in the table data.
• The switching frequency is 132 kHz in all cases.
The efficiency curves are valid only when using the component
• For Universal Input the input bulk capacitor is sized at values shown in Tables 1 to 4. Changes to these parameters may
3 µF/W of the maximum load. For single voltage input the give different results.
input bulk capacitor is sized at 1 µF/W.
Selecting the Correct TOPSwitch-GX
• A VOR (reflected voltage) of 135 V is assumed for all the
curves. This is the output voltage reflected by the turns ratio This section explains how to select the correct TOPSwitch-GX
to the primary side. using the curves (Figures 1-4). The procedure uses the curves
to estimate efficiency of the power supply and the corresponding
• A Zener primary clamp used to limit the leakage inductance dissipation in the TOPSwitch-GX device.
spike is assumed to provide a constant clamping level of
200 V. Practical implementation may require a parallel RC Start with the output power of the application on the X-axis.
network to limit Zener dissipation. Move vertically to the intersection with the first TOPSwitch-GX
curve (solid line) and then read the efficiency directly from the
• All curves assume a Schottky output diode. The 5 V output Y-axis. From the same intersection point on the TOPSwitch-GX
curves use a 45 V Schottky diode with a forward drop of
TYPICAL 12 V OUTPUT POWER SUPPLY COMPONENT PARAMETERS

UNIVERSAL INPUT (85-265 VAC)
PARAMETER Units 242Y 243Y 244Y 245Y 246Y 247Y 248Y 249Y
Maximum Transformer µH 2780 1385 923 693 462 346 277 231
Primary Inductance Lp 3
Transformer Leakage %/Lp 1.5 1.0 1.0 1.0 1.0 1.0 1.0 1.0
Inductance
Secondary Trace nH 30 30 30 30 30 30 30 30
Inductance
Transformer Resonant kHz 750 800 850 900 950 1000 1050 1100
Frequency (secondary
open)
Transformer Primary mΩ 2400 1200 800 700 600 500 400 300
AC Resistance
Transformer Secondary mΩ 30 15 10 8 6 4 2 1
AC Resistance
Output Capacitor mΩ 24 18 15 12 10 8 6 4
Equivalent Series
Resistance @100 kHz
Output Inductor DC mΩ 32 25 20 15 13 10 7.5 5
Resistance
Common Mode Inductor mΩ 370 340 310 280 250 220 190 160
DC Resistance (both legs)
Core Loss %/PIN 2 2 2 2 2 2 2 2
Table 1. Typical Power Supply Component Parameters for a TOPSwitch-GX Flyback Power Supply with a Universal Input (12 V output).
3-67
Rev. D 02/03
curve, interpolate the TOPSwitch-GX power dissipation from deliver 30 W (X-axis) with an estimated efficiency (Y-axis) of
the constant power dissipation contours (dashed lines). about 67.5%. The projected TOPSwitch-GX dissipation is
approximately 3.5 W.
Some output power levels can be delivered by more than one
TOPSwitch-GX device. When moving vertically from the Alternatively continuing the TOP245 could be used with an
X-axis, the first curve encountered will be the smallest, lowest efficiency of 70.5% and a device disspation of approximately
cost TOPSwitch-GX device, while the last curve encountered 2.5 W. As the dissipation is above 0.85 W, Y packaged devices
will be the largest, most efficient TOPSwitch-GX device suitable should be used.
for the desired output power.
The thermal environment and the available heatsinking must
Thermal requirements and packaging of the proposed power still be evaluated to confirm the choice of device in this
supply may call out for a more efficient device rather than the application.
smallest or lowest-cost possibility. In addition the P and G
packages (8 pin DIP) have a practical dissipation limit of around Example 2: 12 W Adapter Application
0.85 W in a 50 °C ambient, giving a device junction temperature Consider a 12 W, 12 V supply with universal input range. From
of ~100 °C. This ensures that there is adequate margin to the curves in Figure 1 we see that a TOP243 or TOP244 could
thermal shutdown including device variation. Typical be used, TOP243 with an efficiency of 82% and a device
temperatures above 110 °C are not recommended. The TO-220 dissipation of 0.7 W or a TOP244 with an efficiency of 83% and
package does not have this limit due to the ability to mount the a device dissipation of 0.5 W. The TOP242 is ruled out as we
tab to a suitably sized heatsink. require to use the P package and therefore are limited to a
dissipation of less than 0.85 W
Example 1: 30 W Universal Application
This is an adapter design in an enclosed plastic box, so the
Consider a 5 V / 30 W power supply with universal input range. maximum power available from the supply is limited by thermal
From the curves in Figure 2, we can see that the TOP244 can considerations. The worst-case external ambient (TA_EXT ) is

UNIVERSAL INPUT (85-265 VAC)
3 Primary Inductance Lp
Inductance
Inductance
open)
AC Resistance
Transformer Secondary mΩ 12 6 4 3 2 1 0.75 0.5
AC Resistance
Equivalent Series
Resistance @100 kHz
Output Inductor DC mΩ 6 4.5 3.5 3 2.5 2 1.5 1
Resistance
Core Loss %/PIN 2 2 2 2 2 2 2 2
Table 2. Typical Power Supply Component Parameters for a TOPSwitch-GX Flyback Power Supply with a Universal Input (5 V output).
3-68
Rev. D 02/03
50 °C with an estimated temperature rise of 20 °C inside the junction temperature of 100 °C provides sufficient margin for
plastic box, giving an internal ambient (TA_INT) of 70 °C. device-to-device RDS(ON) variation.
As a TOPSwitch-GX in a P-package is desired, from the Example 3: 70 W Universal Application

datasheet we obtain the thermal impedance from junction-to- Consider a 70 W, 12 V power supply with Universal input
ambient (θJA) of 60 °C/W (645 mm2 / 1.0 sq. inch of 2 oz. copper range. From the curves in Figure 2 we see that there are four
clad for heatsinking). possible device choices:
We first perform the following calculation for the most cost- a) TOP246Y: The projected efficiency is 73.8% and the
effective device. If found unsuitable, we must repeat the device dissipation is 8 W.
calculation for the more expensive device.
b) TOP247Y: The projected efficiency is 77% and the
TJ = TA − INT + (θ JA × PD ) device dissipation is 5.5 W.
c) TOP248Y. The projected efficiency is 78.5% and the

For the TOP243P, device dissipation is 4.5 W.
TJ = 70 + (60 × 0.7) = 112 °C d) TOP249Y: This is the least cost effective device but has
the highest projected efficiency of 79.5% and the lowest
We see that thermally the TOP243P design is not acceptable. device dissipation of 3.9 W.
Recalculating using the TOP244P.
The thermal environment and the available heatsinking must
TJ = 70 + (60 × 0.5) = 100 °C now be evaluated to confirm the final choice of device in this
application from the short list above. Again increasing the
With a smaller dissipation the TOP244P is just acceptable. A output voltage would increase the efficiency and decrease
dissipation (e.g. 70 W, 19 V, 85-265 VAC gives 85% efficiency).

SINGLE VOLTAGE INPUT (230 VAC ± 15%)
Primary Inductance Lp 3
Inductance
Inductance
open)
AC Resistance
Transformer Secondary mΩ 30 15 10 8 6 4 2 1
AC Resistance
Equivalent Series
Resistance @100 kHz
Output Inductor DC mΩ 32 25 20 15 13 10 7.5 5
Resistance
Core Loss %/PIN 2 2 2 2 2 2 2 2
Table 3. Typical Power Supply Component Parameters for a TOPSwitch-GX Flyback Power.
3-69
Rev. D 02/03
Other Key Considerations • The Quick Selection Curves assume that the AC Input
voltage waveform is a pure sine wave. If the input voltage
We have seen how to use the information provided by the waveform is distorted, the resultant peak voltage on the input
TOPSwitch-GX Quick Selection Curves. However there are bulk capacitor may be much lower than anticipated. This
other key factors to consider when completing the power supply causes the TOPSwitch-GX device to reach current limit or
design. These can produce results that differ from the predictions duty cycle limit at less than the maximum possible load.
of the Quick Selection Curves.
Therefore, in locations where significant line distortion is
Factors That Can Lower Performance expected, the designer should provide a suitable design margin.
This can be accomplished by derating maximum output power
• Input capacitor tolerance and aging should be taken into or increasing the input capacitance.
account. Lower capacitance decreases the DC input voltage,
increasing primary RMS currents and hence giving larger • Some wattmeters give erroneous readings when the current
conduction losses in the device chosen. has a high crest factor. It is important to use an instrument
designed for the purpose. The Voltech PM100 is an example.
• In production, the primary inductance of the transformer
will also have a significant tolerance. Inductances higher • Minimum line frequency is important. A low line frequency
than those in Tables 1 to 4 will cause the power supply to requires larger carryover periods for the input bulk capacitor,
operate beyond recommended design guidelines (KRP too causing high voltage ripple across it. If the line frequency
low). Values of primary inductance significantly lower than expected to be lower than 50 Hz, the input capacitor should
those in Tables 1 to 4 would lead to higher peak and RMS be sized appropriately or the maximum output power be
drain current in the TOPSwitch-GX MOSFET. This causes derated.
an increase in device dissipation and also causes the device
to reach current limit at less than maximum load.

SINGLE VOLTAGE INPUT (230 VAC ± 15%)
3 Primary Inductance Lp
Inductance
Inductance
open)
AC Resistance
Transformer Secondary mΩ 12 6 4 3 2 1 0.75 0.5
AC Resistance
Equivalent Series
Resistance @100 kHz
Output Inductor DC mΩ 6 4.5 3.5 3 2.5 2 1.5 1
Resistance
Core Loss %/PIN 2 2 2 2 2 2 2 2
Table 4. Typical Power Supply Component Parameters for a TOPSwitch-GX Flyback Power Supply with a Single Input (5 V output).
3-70
Rev. D 02/03
• The choice of VOR can affect the efficiency greatly. For However in an adapter application for example, the output
example increasing the VOR (turns ratio) may allow a Schottky power is limited by thermal considerations to a value much
diode on the output, for higher efficiency, by reducing the less than the maximum power capability of the
diode inverse voltage. However it will increase secondary TOPSwitch-GX device. This presents an opportunity to
reflected leakage and therefore clamp dissipation. improve efficiency and lower device dissipation by increasing
the primary inductance while ensuring that the KRP at the
Lowering the VOR reduces secondary reflected leakage, reducing actual power requirement stays within recommended design
clamp dissipation but at the expense of higher primary RMS limits.
currents, increasing the TOPSwitch-GX conduction losses.
• Since the Quick Selection Curves are based on a
• For low voltage outputs, the secondary currents and their TOPSwitch-GX junction temperature of 100 °C at low line,
associated losses can become significant. Close attention full load, better performance is possible if the
must be paid to the ‘ESR’ (Equivalent Series Resistance) of TOPSwitch-GX runs cooler. Good heatsinking will help in
the output capacitor in particular. The values in Tables 2 and achieving higher efficiency.
4 for the 5 V Quick Selection Curves (Figures 2 and 4) use
capacitors with very low-ESR. • Increasing the VOR can be helpful in some cases. A high VOR
decreases the reverse voltage stress on the output diodes.
• Energy stored in the leakage inductance is dumped into This may allow the use of 45 V Schottky output diodes for
primary clamp (RCD clamp or Zener clamp) when the high voltage outputs, resulting in a significant improvement
TOPSwitch-GX turns off. Therefore the efficiency will fall in the efficiency.
significantly if the leakage inductance is too high. Refer to
Example 3 of AN-26 to see how the effective in-circuit This step should be taken only after considering the overall
leakage should be measured and how secondary trace impact. It should be mentioned that increasing the VOR
inductance reflects into the primary. For low voltage outputs causes an increase in the duty cycle and a corresponding
at high power, it is critical to minimize leakage inductance. reduction in the RMS currents and conduction losses in the
TOPSwitch-GX device provided the overall efficiency is not
Factors That Can Improve Performance adversely affected due to increased clamp loss.
For more experienced designers, there are ways to improve the Conclusions
performance indicated by the Quick Selection curves. Some of
these are now mentioned briefly: The TOPSwitch-GX devices may be considered to be an
extension of the TOPSwitch-FX family. The P-package options
• The recommended capacitance per Watt is based on the have reduced current limits to match the device current limit to
optimum cost to performance ratio. Better performance can the thermal dissipation capability of the package. This allows 3
certainly be obtained in terms of efficiency, TOPSwitch-GX for a smaller transformer in adapter designs. However for the
dissipation and life expectancy of the input bulk capacitor, same conditions both the P/G and Y packaged devices will
by using a higher capacitance per Watt than recommended. dissipate the same power. Therefore the Quick Selection curves
are valid for either package (up to the point where current
• If the intended application is for 100/115 VAC only, the limiting takes place).
clamp voltage and VOR may be raised by a calculated amount
provided no voltage doubler is being used at the input of the
power supply. This will enhance the overall efficiency and
lower the device dissipation.
• The recommended primary inductances in Tables 1 to 4 are

based on the minimum permissible KRP at the maximum
power capability of the device. In other words, the primary
inductance along any given solid curve corresponding to a
particular device has been kept a constant.
3-71
Rev. D 02/03
UNIVERSAL INPUT (85 VAC TO 265 VAC) 12 V OUTPUT

85
PI-2678-100900
84
≥ 10 A output current*
83
82 TOP249
81
3W
Efficiency (%)
80
4W
0.5W
79 5W
78 2W 6W
TOP242 7W
77
8W
1W TOP243
76 9W
10 W
75
11 W
74 1.5 W TOP244 12 W
73 14 W
TOP245 TOP246
72 16 W
TOP247 18W
71 TOP248
70
4 10 20 30 50 100 200
Output Power (W) *See "Overview of Quick Selection Curves"
Figure 1. Efficiency vs. Output Power with Contours of Constant TOPSwitch-GX Power Loss for Universal Input and 12 V Output.
UNIVERSAL INPUT (85 VAC TO 265 VAC) 5 V OUTPUT

80
PI-2676-100900
79
78
3 77
76
75
0.5 W 1.5 W 2 W
74
3W
Efficiency (%)
73
4W
72
TOP242 1W 5W
71
2W 6W
70 7W
69 8W
1.5 W
68 TOP243 9W
10 W
67
11 W
66 TOP244 12 W
65
13 W
64 TOP249
TOP245
63
TOP246 TOP248
62
TOP247
61
60
4 6 8 10 20 30 50 100 200
Figure 2. Efficiency vs. Output Power with Contours of Constant TOPSwitch-GX Power Loss for Universal Input and 5 V Output.
3-72
Rev. D 02/03
SINGLE VOLTAGE INPUT (230 VAC ± 15%) 12 V OUTPUT

86
PI-2677-100900
85
84
3W
83 1.5 W 4W
0.5 W
5W
Efficiency (%)
82 2W 6W
TOP242 7W
81 8W
1W TOP243
9W
80 TOP244 10 W
TOP245 11 W
79 12 W
TOP246
14 W
78 TOP247
TOP248
77
TOP249
76
75
6 10 20 100 120 200 300
Figure 3. Efficiency vs. Output Power with Contours of Constant TOPSwitch-GX Power Loss for Single Voltage Application and 12 V Output.
SINGLE VOLTAGE INPUT (230 VAC ± 15%) 5 V OUTPUT

80
PI-2675-100900
79
78 0.5 W
77
3
2W 3W
76 TOP242 4W
1W 1.5 W
5W
Efficiency (%)
75
2W 6W
74
7W
73 8W
TOP243 9W
72
10 W
71 TOP244 11 W
13
12 W
W
70
TOP245 14 W
69
68 TOP246 TOP249
67
≥ 10 A output current* TOP247
66 TOP248
65
6 10 20 50 100 200 300
Figure 4. Efficiency vs. Output Power with Contours of Constant TOPSwitch-GX Power Loss for Single Voltage Application and 5 V Output.
3-73
Rev. D 02/03
®
TOPSwitch-GX
Forward Design Methodology
Introduction Scope
This application note is for engineers designing an AC-DC
The single-ended forward converter topology is often the best power supply using TOPSwitch-GX TOP248-TOP250 devices
solution for AC-DC applications that require higher powers and in a single-ended forward converter. It addresses single input
higher output currents than are practical from flyback converters. voltage 230 VAC or doubled 115 VAC input, but does not
The forward converter extends the power capability of address universal input (85 V to 265 V) designs. The document
TOPSwitch-GX to greater than 200 W for high current outputs. highlights design parameters that are fundamental to the use of
TOPSwitch-GX in a single-ended forward converter. It offers
The feature set of TOPSwitch-GX offers the following advantages a procedure to compute transformer turns, output inductance
in single-ended forward designs: and other design parameters. This procedure enables designers
to build an operational prototype in the shortest possible time.
• Built-in soft-start Refinement of the prototype hardware after bench evaluation
• Built-in under-voltage lockout will lead to a final design.
• Built-in adjustable current limit
• Programmable duty cycle reduction to limit duty cycle The design methodology presented here is sufficiently general
excursion at high line and transient load conditions to cover a variety of single-ended forward designs, including
• Higher efficiency (typically >70%) power supplies for personal computers. It provides for multiple
• Very good light-load efficiency outputs with coupled inductors, independent multiple outputs,
• Voltage mode control for simpler loop designs with and outputs with both linear or magnetic amplifier post
magnetic amplifier post-regulators regulators.
• Built-in remote on-off
• Low component count
• Improved EMI
Snubber
3 Output
Inductor
+
Output
2CIN Capacitor VO
Clamp
Primary Diode
Non-Doubled
Clamp –
Circuit + VDB –
AC +
INPUT RA RB TL431 with
Doubled VDB +
– Bias Frequency
+ Voltage Compensation
Under-Voltage VZ –
Lockout Sense –
RC CVS
RD
D L
TOPSwitch-GX
CONTROL
2CIN C
FEEDBACK
U1 CIRCUIT
S F
PI-2817-121201
Figure 1. Typical Configuration of TOPSwitch-GX in a Single-Ended Forward Converter.
3-74
Rev. C 04/05
IAUX
VAUX
NAUX
LMAIN
NP
IMAIN
VAUXREF
Optional +
Choose LC
Connection Post Filter
NMAIN VMAIN
DC Stacked
or
Conventional –
Output
Return
MAG MAG AMP

AMP Control
IMAINMA
NB LMAINMA Optional VMAINMA

LC
Post Filter
IIND
LIND +
NIND VIND
–
+
ILOAD
Linear Post
ILOAD
+
3
Regulator
Input Voltage from VAUX, Any Output Voltage
VMAIN, VMAINMA or VIND Less Than Input
Voltage
– –
PI-2818-121201
Figure 2. General Output Options for the Forward Converter Described in the Methodology.
This document does not address the design of magnetic Design Methodology Overview
amplifiers nor linear regulators. It determines design parameters
for the transformer and the inductors, but does not give The methodology assumes the reader knows the theory of
construction details for those magnetic components. Such operation of the forward converter and the fundamentals of
details are deferred to other application notes and component power supply design. It is a companion to the PI Expert
suppliers. References [1] through [6] are good sources of software for forward converter design (available from the
information for the design of transformers and inductors. Power Integrations Web site). Designers are advised to check
Software for design of magnetic amplifiers is available from Power Integrations’ Web site at www.powerint.com for the
[5]. Reference [1] is also an excellent resource for other latest application information.
important topics in power electronics.
This presentation uses a typical combination of output options
for illustration of the methodology (see Figure 2). This document
3-75
Rev. C 04/05
gives the basic expressions illustrating the methodology. The response. The frequency compensation will in general require
PI Expert software uses more complex versions of these two zeros and two poles to obtain the phase margin desired for
expressions containing additional parameters to account for most applications. While the design of the feedback circuit is
non-ideal effects. Thus, results from the software may not a separate topic beyond the scope of this application note, the
exactly match the computations from expressions in this general topology of the circuit is discussed.
document.
Output Options
This document assumes a non-doubled input configuration. Salient features of the output circuits are illustrated in
PI Expert includes modified expressions for both doubler and Figure 2. Multiple secondary windings of the transformer may
non-doubler input configurations. To simplify the expressions, be configured in many different ways to give several options for
all outputs are assumed to operate in continuous conduction regulated and unregulated output voltages.
mode, consistent with the worst case design at maximum load.
At lower load conditions it is possible for individual outputs to All applications will have only one main output. This is the
operate in discontinuous conduction mode. voltage that is regulated directly by TOPSwitch-GX through the
optically isolated feedback circuit. In general, any number of
The methodology begins with an explanation of the general auxiliary outputs may be derived from other secondary windings
converter topology. It then presents the design flow, showing and regulated indirectly by means of a coupled inductor that
the major tasks in a high level flowchart. After a review of the they share with the main output.
nomenclature and definitions of variables, it discusses the
details of the design procedure. Rationale, assumptions and The secondary windings for the auxiliary outputs may be
expressions are given to help the designer enter parameters and configured in two different ways. The conventional
interpret results. A complete list of variables used in the configuration connects one side of the auxiliary winding to the
expressions follows in Appendix A. Appendix B offers a main output return. This connection is used when the auxiliary
procedure for hardware verification. output is the opposite polarity of the main output. An alternative
configuration, sometimes known as the DC stacked connection,
General Converter Topology has one side of the auxiliary winding referenced to the main
output instead of the output return. It has the advantage of better
Figure 1 shows a typical single-ended forward converter using regulation of the auxiliary output voltage than the non-stacked
TOPSwitch-GX. Detail is focused on the primary side of the arrangement, but is limited to outputs that are greater in
transformer because the circuits on the secondary are magnitude and of the same polarity as the main output voltage.
conventional and covered in other literature.
Any number of unregulated output voltages may be derived
Resistors RA and RB set the under-voltage lockout threshold. from circuits that do not share an inductor with any other
3 Resistor network RA, RB , RC, and RD with capacitor CVS adjusts outputs. They are related to the main output only through
the maximum duty ratio as a function of the input voltage. This separate secondary windings on the transformer. Their inductors
methodology gives the procedure to determine proper values are independent of the others. These outputs typically are
for the resistors and the capacitor. referenced to the output return, but alternatively they may be
referenced to any potential that the isolation of the transformer
Another key element in the use of TOPSwitch-GX is the will tolerate.
primary clamp (CCP, D1, VR1, VR2 and VR3 in Figure 10)
which resets the transformer flux and limits the maximum drain Multiple tightly regulated voltages may be obtained with
voltage. This methodology assumes use of this Zener-capacitor either linear or switching post regulators. These external
clamp circuit. Guidance for selection of components for this regulators may be added to any output, including the main
particular clamp is included in this application note. output. They are simply additional loads on those output
voltages.
The topic of clamp circuits is deferred to a separate application
note. Designers may choose to use their own clamp circuits A particularly useful type of switching post regulator is the
with the restriction that resonant clamps, (for example, LCD magnetic amplifier, which uses a saturating magnetic element
clamps–inductor/capacitor/diode) and reset windings are not as an independently controlled switching device. While a
recommended. The internal current sense of TOPSwitch-GX magnetic amplifier can in theory be operated from any output,
does not allow the high reset current of a resonant clamp to be this methodology restricts the connection to the main output
excluded from the sensed drain current. only.
This methodology uses an ordinary optically isolated feedback Since it is not possible to treat every combination of output
circuit that is common in voltage mode systems with a two-pole options in this presentation, the methodology will be restricted
3-76
Rev. C 04/05
to those that are typical for power supplies in personal computers.

Therefore, this methodology allows the following options:
Start
• One main output

Get system requirements • A maximum of one auxiliary output that may be DC
Select output topology stacked to the main output or referenced to output return
Choose design parameters
• A maximum of one independent output
• A maximum of one magnetic amplifier post regulator that
Estimate peak primary current operates from the secondary winding for the main output
Select TOPSwitch-GX from • Any number of linear post regulators that may operate
current and power guidelines
from any output
Design Flow
Are parameters
No within TOPSwitch-GX Figure 3 is an abbreviated flowchart of the major tasks in the
boundaries?
design methodology. The important decision blocks involve
the selection of the proper TOPSwitch-GX device for the
application, and the designer’s satisfaction with the overall
Yes
design.
Design transformer
Compute operational parameters All designs begin with the definition of requirements. The next
section discusses the parameters a designer needs to know
before the design can start.
TOPSwitch-GX
Parameters for the forward converter are dominated by the
No output specifications. The designer will have to choose a
selection OK?
topology that is appropriate for the application. An application
that calls for only one output is simplest, while a requirement
Yes for several outputs with complex loading needs careful
consideration. It may be necessary to go through several
Determine component stress designs to select the most satisfactory configuration.
Compute output inductance
Knowledge of system requirements and selection of the output
topology allow the designer to compute the magnetic parameters. 3
These are turns ratios for the transformer and the coupled
Design inductor (if the design has an auxiliary output), plus values of
No
satisfactory? inductance for independent outputs and the output inductor for
the magnetic amplifier (also called mag amp). The output
inductor for the mag amp is different from the inductive
Yes switching element (sometimes called a saturable reactor,
saturable core, or saturable choke), that is not addressed in this
Determine control and note.
clamp components
The peak primary current can be computed from the turns
ratios established for the transformer along with the ripple
Evaluate prototype
on bench current in the output inductors. This allows selection of the
appropriate TOPSwitch-GX. It must have sufficient current
limit to handle the maximum steady-state load and must have
enough additional margin to accommodate peak loads and
Check Assumptions No Performance Yes Design
transients. Another consideration in the selection of the
Adjust Design satisfactory? complete TOPSwitch-GX is power dissipation in the device. A device
parameters
that can handle the steady-state and peak primary currents does
not guarantee ability to meet thermal limitations – this is an
PI-2819-121301
independent consideration.
Figure 3. Flowchart Showing Major Tasks in the Design of
Forward Converters with TOPSwitch-GX.
3-77
Rev. C 04/05
The efficiency of the power system is an important consideration

in every design. The designer should have a goal for the Name Description
efficiency of the system at the start of the design, based on η Total system efficiency
reasonable allowances for power lost in the specific areas of the fL AC mains frequency
power supply.
fS TOPSwitch-GX switching frequency
The efficiency goal should take into account losses in the IAUX Current from auxiliary output
transformer, inductors, output rectifiers, and clamp circuits. IIND Current from independent output
Most high power designs have some form of power factor IMAIN Current from main output
correction (PFC). The type of PFC will affect the efficiency.
For example, the voltage drop on a passive PFC (a large IMAINMA Current from magnetic amplifier
inductor in series with the AC line input) will reduce the tH Holdup time
minimum input voltage at the converter, and will also reduce VACMAX Maximum AC input voltage
system efficiency.
VACMIN Minimum AC input voltage
Total system efficiency should consider losses in the AC input VACNOM Nominal AC input voltage
circuit, including the EMI filter, that are not part of this design VACUV AC under-voltage threshold
methodology. Only a bench evaluation can determine the
VAUX Auxiliary output voltage
actual efficiency of the power supply. If the efficiency is not
satisfactory, the designer must revise the values of component VAUXREF Auxiliary output reference voltage
parameters or change the output topology for a repeat design. VDROPOUT Lowest DC bus voltage for regulation
VDSOP Maximum drain-to-source voltage
If the requirements call for a holdup time, the designer must
determine the amount of bulk input capacitance that is required VHOLDUP DC bus voltage at start of tH
to achieve the specified holdup time from the designated input VIND Independent output voltage
voltage. It is often necessary to adjust parameters by iteration VMAIN Main output voltage
to meet the objectives of the design.
VMAINMA Magnetic amplifier output voltage
PI Expert performs the calculations to allow the designer to see Table 1. System Parameters Needed to Start a Design.
the interactions of the variables immediately.
After the values of the major power components are determined, These conventions are used to identify voltages, currents, and
the designer needs to check voltage and current stress to select components.
3 components with the proper ratings. Then the designer can
choose values for small signal components that set voltage When there is more than one output in a category, the individual
detection thresholds and other control parameters. members are distinguished by numbers appended to the subscript,
as in IND1, IND2 and IND3 for three independent outputs. Quantities
The final step is an evaluation of a prototype on the bench. This related to the magnetic amplifier have MA appended to the
is the only way to confirm that the design is satisfactory, and to subscript, as in MAINMA referring to the magnetic amplifier on the
get necessary information to adjust the parameters if a redesign secondary winding for the main output. This notation has the
is necessary. generality necessary to expand the allowable output options.
Definition of Variables Turns ratios on magnetic components are designated by lower

case n with appropriate subscripts, while actual numbers of
Table 1 gives a set of system parameters that should be known turns are distinguished by upper case N with identifying
at the start of the design. The list is general, so all the parameters subscripts.
will not necessarily be relevant to all applications. Some values
will be given by the system specification, while others are the There are a few other variables and notations that need definition.
designer’s choice. Figure 4 shows a section of output circuitry that identifies some
important electrical quantities. Each output of a forward
The notation in this document uses descriptive subscripts to converter has two diodes. One is designated the forward diode
keep track of variables. Quantities that refer to the main output and the other is the catch diode. Associated quantities have
are designated with the subscript MAIN. Variables associated F
or C appended to their respective subscripts.
with an auxiliary output are identified by the subscript AUX, and
those related to an independent output have the subscript IND.
3-78
Rev. C 04/05
The peak DC bus voltage (non-doubled) is
VDMAINF RLMAIN LMAIN VMAX = VACMAX 2 (1)

+ –
+
Forward while the DC bus voltage at the valley of the ripple at the
Diode minimum steady state AC input is
RSMAIN –
NP
VDMAINC VMAIN
NMAIN + ⎛ 1 ⎞
RP Catch 2 PO ⎜ − tC ⎟
Diode 2 ⎝ 2 fL ⎠ (2)
–
VMIN = 2VACMIN −
ηDC CIN
PI-2820-121301
where PO is the total output power, tC is the conduction time of
Figure 4. Output Circuit with Parameter Definitions. the bridge rectifier, ηDC is the efficiency exclusive of losses in
the AC input circuit, and CIN is the capacitance at the input to the
converter. Use 3 ms for tC and use the total system efficiency
Voltage drops on diodes have subscripts with the prefix D for the η for ηDC if no better estimates are available. A good initial
conduction drop and PIV for the reverse blocking voltage. The value for CIN is 1 µF per watt multiplied by PO.
only exception to this convention is for drain-to-source voltages,
which will be obvious from context. The designer should carefully choose the value of tC when
using passive PFC input (a large inductor in the AC line), since
Figure 4 also shows series resistances that the designer can this approach significantly increases the diode conduction time.
include to get better predictions of performance. Also, the voltage waveform will deviate from a sinusoid,
causing some error in the prediction of Equations (1) and (2).
Detailed Design Procedure
Remember to use the input voltage to linear regulators, not the
This methodology guides the designer through a procedure that regulated output voltage, to compute the total output power.
determines parameters for prototype hardware. After bench The dissipation in the linear regulator is part of the load on the
evaluation, the designer refines the parameters to meet all converter.
requirements.
The nominal DC bus voltage is defined to be
The design can start with knowledge of only the most basic
system requirements. For example, the forward voltage drops ⎡ ⎛ 1 ⎞⎤ 3
on diodes and the resistances of transformer windings are ⎢ PO ⎜ − tC ⎟ ⎥
seldom known very accurately at the beginning of a new design. 2⎢ 2 ⎝ 2 fL ⎠⎥
VNOM = V + V −
Results of the design with default values will guide the designer 2 ⎢ ηDC CIN ⎥
ACNOM ACNOM
to select particular components with known parameters. ⎢ ⎥
Figure 5 gives an expanded flowchart that includes the detailed ⎢⎣ ⎥⎦
steps which follow. (3)
Step 1 – Establish System Requirements This is simply the midpoint between the peak and valley of the
Determine the parameters in Table 1. These should be available ripple voltage on the input capacitor (non-doubled).
from a system specification of the power supply’s application.
Step 2 – Set Ripple Current in the Output Inductors
The software will compute and display the maximum and Choose the ripple current factor K∆I. Figure 6 shows how it is
minimum DC bus voltages to the converter from the AC inputs. related to the average output current. K∆I is a useful parameter
The need to know maximum and minimum voltages is obvious. for design because it directly influences the size of the output
The optional nominal input voltage VACNOM helps determine the inductor. It also affects the peak primary current and the RMS
turns ratios of the transformer. The goal is to set the unregulated current in the output capacitors.
output voltages at their nominal values when the input is at its
nominal value. The designer may choose any value between
VACMAX and VACMIN to be the nominal value.
3-79
Rev. C 04/05
1. Establish system requirements

(specifications & output topology)
Review requirements
2. Set inductor current ripple Check assumptions
Adjust design parameters
3. Calculate transformer turns ratios
4. Estimate primary current

No
5. Choose TOPSwitch-GX
14. Inductor size

satisfactory?
Operation within
TOPSwitch-GX guidelines? No
Yes
Yes 15. Calculate component values for

external DCMAX reduction
6. Design transformer
16. Calculate resistor values for

optional external UVLO circuit
7. Check peak primary current
17. Choose components for

clamp circuit
Operation within
No TOPSwitch-GX guidelines?
18. Choose components for

Yes feedback circuit
3
8. Determine input capacitance
Construct hardware prototype
Evaluate thoroughly on bench
Determine limits of operation
9. Calculate stress on rectifiers
10. Calculate RMS ripple current in

Is performance satisfactory? No
output capacitors
Yes
11. Calculate parameters for
coupled inductor Design complete
12. Calculate inductance for

independent outputs
13. Calculate output inductance for

magnetic amplifier
PI-2831-020502
Figure 5. Expanded Flow Chart Showing Detailed Steps in Forward Design Methodology.
3-80
Rev. C 04/05
I
∆I
K∆I =
IO
IO
∆I
DTS (1-D) TS
TS = 1
fS
PI-2821-121401
Figure 6. Inductor Current Showing Definition of K∆I.
The ripple current in the inductor depends on the converter’s across multiple outputs at minimum load is obtained when
operating point. In general, K∆I will change with the duty ratio
according to the relationship ⎛I ⎞
K∆I ≤ 2⎜ MINIMUM ⎟ (6)
(4) ⎝ I MAXIMUM ⎠ 3
K∆I = K∆I 0 (1 − D)
where K∆I0 is the limit as the duty ratio approaches zero. The where IMINIMUM and IMAXIMUM are the respective minimum and
expression that relates K∆I0 to the inductance L for a given maximum average output currents.
generic output is
The common K∆I at full load allows calculation of the inductance.
VOUTPUT + VD( OUTPUT )C (5) The designer has the option to change any value of any inductor
K ∆I 0 = to suit particular requirements. The change in inductance will
LIOUTPUT fS change the K∆I for that particular inductor.
where VD(OUTPUT)C is the voltage on the catch diode when it is For coupled inductors, K∆I indicates the ripple component of the
conducting. total ampere turns, not ripple current on any individual winding.
K∆I will be between 0.15 and 0.3 for most practical designs. The Step 3 – Calculate Turns Ratios for the Transformer
K∆I corresponding to the highest input voltage is used for Turns ratios on the transformer are computed with respect to the
calculations. All dependent quantities should then be computed main output winding. The primary-to-main turns ratio is fixed
for the designer’s inspection. Since the duty ratio at the highest by the input and output voltages and the maximum duty ratio,
input voltage will usually be very small, K∆I0 is usually a very which is limited by the maximum drain-to-source voltage that
good approximation to the worst case K∆I. is set by the designer. The maximum duty ratio to guarantee
reset of the transformer is
If any outputs have nonzero minimum load, use the minimum VDROPOUT
load as a guide for the upper limit on K∆I. The best regulation DMAX _ RESET ≤ 1 − ≤ 0.74 (7)
VDSOP
3-81
Rev. C 04/05
where VDROPOUT is the DC bus voltage at the end of the holdup from DMAX in Equation (8). In Equation (10), LMAINLK is the
time and VDSOP is the maximum drain-to-source voltage on the leakage inductance of the secondary winding of the main
TOPSwitch-GX during operation. The minimum recommended output, IMAINSEC is the winding current required to turn off the
value for VDROPOUT is 130 V, while VDSOP is usually less than the catch diode of the main output, and fS is the switching frequency.
breakdown voltage of 700 V by a comfortable safety margin. A Note that in the DC stacked connection for the auxiliary output,
safety margin of 15% is typical, giving 600 V for VDSOP. the winding for the main output carries the current of the main
output plus the current of the stacked auxiliary outputs.
The maximum duty ratio for the converter occurs at VDROPOUT.
This must be reduced as a function of line voltage from the Next, compute the duty ratio DNOM that corresponds to the
DCMAX of TOPSwitch-GX by external circuitry in Step 15. The nominal input voltage.
recommended maximum duty ratio DMAX for the forward
converter application depends on the operating input voltage VMAIN + VDMAINC (11)
DNOM =
range. For a 3:1 operating range (VMAX:VDROPOUT) 70% is typical. VNOM
− VDMAINF + VDMAINC
As the operating range reduces so does the value of DMAX. nP
For a 2:1 operating range a value of 50% would be selected.
This allows a better estimate of the turns ratio that will produce
First, compute the turns ratios for the primary and the auxiliary the desired independent output voltage.
winding. The turns ratio on the primary of the transformer is
VIND + VDINDF DNOM + VDINDC (1 − DNOM )
nIND =
VDROPOUT − VDS VMAIN + VDMAINF DNOM + VDMAINC (1 − DNOM )
nP =
⎛ 1 − DMAX ⎞ (12)
(VMAIN + VDMAINC )⎜ ⎟ + VMAIN + VDMAINF
⎝ DMAX ⎠
(8a) Finally, compute the turns ratio for the bias winding so that the
bias voltage is greater than eight volts. This value is the
Where VDS is the average drain-to-source voltage during the CONTROL pin voltage, 5.8 V, plus the 2.2 V saturation voltage
on-time of TOPSwitch-GX: of the optocoupler’s phototransistor at VDROPOUT.
When VDMAINF and VDMAINC are the same value VDMAIN, this The turns ratio for the bias winding is then
equation simplifies to:
⎛ 8 volts + VDB ⎞
n B ≥ nP ⎜ ⎟ (13)
(V
nP = DROPOUT
− VDS ) DMAX ⎝ VDROPOUT ⎠
3 VMAIN + VDMAIN (8b)
where VDROPOUT is the minimum DC bus voltage for regulation
The turns ratio for the auxiliary winding is and VDB is the voltage drop on the rectifier for the bias voltage.
Check that the breakdown voltage on the phototransistor of the
VAUX + VDAUXC − VAUXREF optocoupler is higher than the bias voltage at the highest
nAUX = (9) transient input voltage.
VMAIN + VDMAINC
Step 4 – Calculate the Primary Current
Equation (8) is valid for systems where the leakage inductance Find the peak and RMS values for the primary current. This is
of the transformer is negligible. This is a reasonable assumption a preliminary estimate from the system parameters. It allows
because the leakage inductance must be minimized for low the designer to assess the suitability of his application for
power dissipation and proper operation of the clamp TOPSwitch-GX as early as possible.
circuit. Leakage inductance reduces the effective duty ratio on
the secondary circuits by delaying the turn-off of the catch Figure 7 shows typical primary current waveforms for forward
diodes. The effect can be significant in designs with very high converters with and without a magnetic amplifier post regulator.
output currents. To compute the turns ratio for the primary Figure 7(a) is without a magnetic amplifier, whereas
winding when leakage inductance is a consideration, subtract Figure 7(b) shows the effect of one magnetic amplifier post
the constant regulator. TOPSwitch-GX determines the duty ratio D to
LMAINLK I MAINSEC regulate the main output, whereas the post regulator sets DMA
δD = DMAX fS (10) independently by its own local feedback to regulate the output
VMAIN voltage from the magnetic amplifier.
3-82
Rev. C 04/05
IP IP
IPP
DMA TS
IPP
DTS (1-D) TS DTS (1-D)TS
0 t 0 t
TS = 1 TS = 1
fS fS
(a) (b)
PI-2822-121401
Figure 7. Typical Primary Current Waveforms for a Converter Without Magnetic Amplifier (a) and with a Mag Amp (b).
The computation is simply the reflection of peak currents in the inductance and current. The RMS current is computed at the
secondary circuits by the ideal turns ratios of the transformer. duty ratio that corresponds to VACMIN because worst case steady-
Using the principle that the sum of the ampere turns for an ideal state resistive losses occur at that operating point.
transformer is zero, the instantaneous primary current for a
transformer with W secondary windings is just Step 5 – Choose the Appropriate TOPSwitch-GX Device
Select a TOPSwitch-GX according to the requirements for peak
1 W (14) primary current and acceptable power dissipation. For operation
IP = ∑ ij n j
nP j = 1
of the converter in continuous conduction mode it is 3
recommended to operate the device at no more than 80% of its
current limit for ordinary thermal design. To reduce device
where ij is the current in the secondary winding with turns dissipation it is possible to use a TOPSwitch-GX device that has
ratio nj. Thus, for a transformer with three secondary windings, a lower RDS(ON) when the current limit is adjusted accordingly.
the primary current would be the sum i 1n 1+i 2n 2+i 3n 3 Lowering ILIMIT externally (using a programming resistor to the
divided by the turns ratio of the primary. Note that since all X pin), takes advantage of the lower RDS(ON) of the larger device
turns ratios are defined with respect to the main output winding, while maintaining the same level of overload protection.
the turns ratio of the main output winding is 1. Equation (14)
may also be used with the actual number of primary turns NP The external current limit reduction factor is
substituted for the turns ratio nP, and the actual secondary turns
Nj substituted for the turns ratios nj. External Current Limit (15)
KI =
This estimate does not include the effect of magnetizing
Data Sheet Current Limit
current in the transformer, which will be determined after the
transformer is designed. The magnetization current will raise where 0.4 ≤ KI ≤ 1.0, and is set by the value of a resistor
the peak value of this estimate by typically less than 10% worst connected between the X pin and SOURCE pin. Refer to the
case. TOPSwitch-GX data sheet for details.
The computation in PI Expert includes the ripple current in the With external current limit reduction, the actual (external)
output inductors to find the peak primary current. Ripple current limit is
current is ignored to calculate the RMS value. The resulting I XLIMIT = I LIMIT K I
error in the RMS current is less than 1% for practical values of (16)
3-83
Rev. C 04/05
Remember to check the maximum and minimum tolerance on Compute the turns for the other power windings.
ILIMIT from the data sheet for the selected device. Allow margin
to guarantee that the peak primary current IPP is less than the N P = nP N MAIN
minimum value of IXLIMIT at high temperature. With minimum
device ILIMIT, check that N AUX = nAUX N MAIN (21)
IPP ≤ 0.96 I LIMIT for K I = 1 N IND = nIND N MAIN
(17)
IPP ≤ 0.86 I XLIMIT for K I < 1
Round NP downward to the next integer. Round NAUX and NIND
Adjust the system specifications if the peak current is too high to the nearest integer.
for the largest device. While some specifications are fixed,
others are adjustable at the discretion of the designer. Raising Compute the turns for the bias winding.
the minimum input voltage will give lower peak current.
⎛ 8 volts + VDB ⎞ (22)
Step 6 – Design the Transformer NB = NP ⎜ ⎟
The transformer design can be either completed in-house or ⎝ VDROPOUT ⎠
delegated to a qualified supplier of custom magnetics. An
outside supplier needs to know the turns ratios and the Round NB upward to the nearest integer value.
recommended restrictions on flux density to start a design. Even
if the ultimate design will be done outside, it is beneficial to do Designers should use copper foil instead of wire for windings
a rough design in-house. A proposed design with actual of few turns that carry high current. It is very important to the
numbers of turns on each winding will reduce the time required success of the design to minimize leakage inductance.
to obtain a satisfactory transformer.
Compute an estimate of the peak magnetizing current.
The maximum recommended flux density for this application is
The primary inductance in henries is
BPEAK ≤ 0.3 tesla (3000 gauss) (18) 2
µ AN (23)
LP = 0 e P
and the recommended maximum change in flux density per e
switching period (AC flux density) is + g
µr
BM ≤ 0.2 tesla (2000 gauss) (19) where µ0 is the permeability of free space, Ae is the effective
area, e is the effective path length in the core and g is the length
3 The constraint on BM sets the minimum number of turns for a of the air gap (see Zero Gap Transformer section). The
particular core, while the limit on BPEAK restricts the maximum dimensionless relative permeability µr is given by
transient duty ratio. Although peak flux density under steady-
state conditions can be calculated, the designer should allow AL e
µr =
sufficient margin to avoid saturation under transient conditions. 400πAe (24)
To start the design, select a core that is likely to meet the size and Units in the above two expressions are the SI basic units with the
efficiency requirements of the application. Since the voltages exception of inductance coefficient AL, which has the
and turns ratios are determined, all that remains is to find the conventional units of nH/turn2.
actual number of turns and the size of wire for each winding.
With no gap, the primary inductance in henries is simply
Compute the minimum turns for the main output.
2 −9
LP⏐NO GAP = AL N P × 10 (25)
V + VDMAINF
N MAIN ≥ MAIN (20) Now the peak magnetizing current is given by
BM Ae fs
where Ae is the effective area of the core. Units in the above VMIN DMAX (26)
I MP =
expression are volts, tesla, meter2 and hertz. Round NMAIN LP fS
upward to the next integer value.
Units in the above expression are amperes, volts, henries and
hertz. The magnetizing current should be less than 10% of the
primary current for reasonable power dissipation in the clamp
circuit.
3-84
Rev. C 04/05
Estimate the power lost in the core from the manufacturer’s data where PO is the total output power that corresponds to the
on the core material, operating frequency and BM. Copper losses efficiency at the DC bus, ηDC and tH is the holdup time.
may be estimated from the resistance and RMS current in each
winding. If the estimates indicate excessive loss, repeat the If an AC voltage VACHOLDUP is specified to mark the beginning of
design with a larger core. the holdup time, the minimum required input capacitance (no
doubler) is
Zero Gap Transformers
For highest efficiency in this application with the simple Zener ⎛ 1 ⎞
clamp circuit, it is recommended that the transformer core have
2( t H − t C ) +
2P ⎜ fL ⎟
no air gap. While an air gap reduces the remnant flux density CIN ≥ O ⎜ 2 (28)
ηDC ⎜ 2VACHOLDUP − VDROPOUT ⎟⎟
2
and stabilizes the primary inductance, it increases the stored
energy that must be processed by the clamp circuit. ⎝ ⎠
With the use of a suitable reset scheme, transformer saturation where tC is the conduction time of the AC input rectifiers and fL
is not a problem in the absence of an air gap. Using this is the frequency of the AC power line. Again, note that tC will
methodology and the recommended clamp scheme, the design increase significantly if the design has passive PFC.
restricts peak flux density and the clamp circuit produces
negative magnetizing current during reset. The efficiency ηDC excludes losses in the AC input circuit and
EMI filter. No power is dissipated in the AC input circuit during
The negative magnetizing current during reset prevents flux the holdup time because the AC input is disconnected. The
build-up in the transformer during successive switching periods. lower system efficiency η that includes the AC input losses
Even with no intentional gap in the transformer core, mechanical would give a value of CIN that is larger than required.
imperfections will always give a finite effective gap (when
calculating with PI Expert a value of 0.02 mm is used). If an air Compare the value from Equation (27) or (28) with the estimate
gap is desired for other reasons, it should be as small as possible. for CIN in Step 1. Adjust CIN in Step 1 and repeat the calculations
until the computed value is approximately the same as in
Step 7 – Check Primary Current Step 1.
Use the actual number of turns from the design of the transformer
to compute the peak and RMS current on the primary. Primary Step 9 – Calculate Stress on Rectifiers
current was estimated in Step 4 with an ideal turns ratio before PI Expert calculates voltage and current stress on rectifiers for
the transformer was designed. Add the peak of the magnetizing guidance in selection of appropriate components. The
current to obtain actual peak of the primary current under recommended derating factor for peak inverse voltage is 80%.
steady-state conditions. Derating for the currents is generally not necessary.
3
Designers should be aware that the primary current observed on Thus, the recommended voltage rating for the input bridge
prototype hardware may be lower than predicted because the rectifier is
circuit that resets the flux in the transformer allows a negative
VPIVAC = 1.25 2VACMAX
average magnetizing current, as mentioned previously in (29)
Step 6 in the section on Zero Gap Transformers. The design,
however, must allow for conditions when the magnetizing Current ratings for rectifiers are average values, not RMS. The
current adds to the reflected secondary currents. current rating for the bridge rectifier is computed from
PO
Step 8 – Determine the Input Capacitance for Holdup Time I DAVBR = (30)
The holdup time must be specified at a minimum voltage
ηDC VLL
VHOLDUP. This is often, but not always VMIN. For maximum where VLL is the average DC bus voltage at the lowest steady-
flexibility, this methodology allows the designer to determine state line voltage (no doubler).
the value of input capacitance required to obtain a given holdup
time from an arbitrary input voltage. ⎡ ⎛ 1 ⎞⎤
⎢ PO ⎜ − tC ⎟ ⎥
If a DC voltage is specified to mark the beginning of the holdup 2⎢ 2 ⎝ 2 fL ⎠⎥
time, the minimum required input capacitance is VLL = ⎢ VACMIN + VACMIN − ⎥
2 ηDC CIN
⎢ ⎥
2 POt H ⎢⎣ ⎥⎦
CIN ≥
( 2
ηDC VHOLDUP − VDROPOUT
2
) (27) (31)
3-85
Rev. C 04/05
Calculations of the peak inverse voltage on the output rectifiers Inductance is computed for the winding that is on the main
use VMAX, VDSOP, and the output voltages with the turns on the output. The computation is based on K∆I, which considers the
transformer windings. total ampere turns of the coupled inductor, not just the current
in one winding. The inductance of the winding for the main
Calculations of worst case average current in the catch diodes output, valid for only the DC stacked configuration, is
are with the duty ratio that corresponds to the maximum input
voltage. A very good approximation to the average rectifier
current is then just the output current. Current in the forward
VMAIN + VDMAINC
LMAIN =
diodes is computed with DMAX. Note that with DC stacked ⎛ ⎛N ⎞⎞
outputs, the rectifiers on the main output must conduct the sum K∆I 0 ⎜ I MAIN + I AUX ⎜ LAUX + 1⎟ ⎟ fS
of the currents of the main and auxiliary outputs. ⎝ ⎝ N LMAIN ⎠⎠
(34)
In general, the stress will be different for the forward diode and
the catch diode on the same output. Designers will have to PI Expert gives the designer the turns ratio, the total ampere
consider the one with the greater stress when choosing turns, and the peak energy stored in the inductor. The designer
components that contain both diodes in the same package. has the option to change these parameters by adjustment of the
K∆I for each inductor.
Step 10 – Calculate RMS Ripple Currents in Output
Capacitors. These quantities assist the designer to obtain an appropriate
Currents in the output capacitors are computed at the maximum inductor of either his own design or one from a qualified
loads. In continuous conduction mode, the RMS ripple current supplier. Bench evaluation of the prototype will determine if
is given by fine adjustment of the turns is necessary in the final configuration.
K∆I IOUTPUT
I RMS = (32) Step 12 – Calculate Inductance for Independent Outputs
2 3 Calculation of the inductance for independent outputs is
where K∆I is for the particular output under consideration. This straightforward and similar to the computation of the parameters
expression is reliable for independent outputs and for a main for the coupled inductor. Design of the component is simplified
output with no coupled inductors. For converters with auxiliary because there is no turns ratio associated with an inductor that
outputs, Equation (32) is only an estimate. Ripple currents in has only one winding. PI Expert computes the inductance and
the individual windings of coupled inductors depend on magnetic the peak stored energy. This information is useful for selection
coupling coefficients, parasitic voltage drops, and other of magnetic cores from catalogs.
quantities in the circuit that are difficult to predict. Therefore,
designers must evaluate prototype hardware on the bench to Step 13 – Calculate Output Inductance for the
3 confirm that the assumptions of the design are valid for a Magnetic Amplifier
particular application. PI Expert computes the output inductor for a magnetic
amplifier post regulator in the same way as for an independent
Step 11 – Calculate Parameters for the Coupled Inductor output. It does not address the magnetic switching element.
The coupled inductor allows the auxiliary outputs to have better
regulation than independent outputs, with the penalty of increased Step 14 – Adjust Output Inductors if Necessary
complexity of the inductor. The designer may modify the K∆I of any inductor to accommodate
special requirements. If the value or the estimated physical size
PI Expert allows two options for the topology of the auxiliary of the computed inductor is not satisfactory, adjust the individual
output. The auxiliary output may be referenced to the main K∆I to achieve the desired result.
output voltage for the best regulation or to output return when
necessary. The reference must be at output return to obtain a Step 15 – Calculate Component Values for External
negative auxiliary output with a positive main output. Reduction of DCMAX
The maximum duty ratio (DCMAX) of TOPSwitch-GX must be
Turns ratios for the coupled inductor are the same as the ratios restricted to avoid saturation of the transformer during transient
for the transformer. The turns ratio of a coupled inductor for a loading. A network of four resistors and a capacitor (RA, RB, RC,
converter that has one auxiliary output is, in terms of the actual VZ, RD and CVS in Figure 1 and Figure 1 of Appendix B)
number of turns, determines a variable upper limit on the duty ratio. Adjustment
of the maximum duty ratio with input voltage allows enough
N LMAIN N MAIN (33) deviation beyond the steady-state operating point to respond to
=
N LAUX N AUX transients while maintaining enough time in every switching
cycle for the transformer to reset.
3-86
Rev. C 04/05
100%
DMAX_RESET 74% DCMAX

DUTY RATIO (%)
DXDO
DLL_RESET
DRESET
DMAX_ACTUAL
DXMAX DHL_RESET
D
DXHL
DLL_ACTUAL
DHL_ACTUAL
0% VIN
VDROPOUT VUVLO VMIN VMAX
PI-2823-121701
Figure 8. Boundaries of Voltages and Duty Ratio Related to the Selection of RA, RB, RC and RD with CVS in Figure 1.
The resistor network also sets the threshold for line under- The lowest curve is the duty ratio D that corresponds to steady-
voltage lockout. Protection from over-voltage is generally not state operation at a given input voltage. The straight line with
a concern for this topology since it uses a Zener clamp to negative slope is the maximum duty ratio DRESET that will still
provide a hard limit on the drain-to-source voltage. guarantee reset of the transformer for a given VDSOP. The
converter must always operate with D less than DRESET to avoid
The resistors are matched to the capacitor to form an integrator
with an appropriate time constant to give a cycle-by-cycle duty
saturation of the transformer. The curved line between the D
and DRESET lines is the external duty ratio limit DXMAX that is set
3
ratio limit. The integration of the voltage on the bias winding by the resistors.
gives the external duty ratio limit a desirable relationship to the
flux in the transformer. The circuit adjusts the duty ratio limit The designer must choose the components to set the curve of
to set an upper bound on the volt-second product, and to balance DXMAX at a desired position between the boundaries of DRESET
the volt-second product during TOPSwitch-GX on and off and D for a given set of specified voltages.
times. The dynamic nature of the circuit allows greater freedom
and precision in the design without interference from the line PI Expert prompts the user to enter several parameters that are
over-voltage threshold limit. important to the computation of the resistor values. Some
parameters are from the TOPSwitch-GX data sheet while others
Figure 1 shows the locations of resistors RA, RB, RC and RD with are design choices. The software suggests default and typical
capacitor CVS. Several important quantities related to their values. The designer can enter maximum and minimum values
values are illustrated in Figure 8. The broken vertical lines in to check worst case situations.
Figure 8 mark the boundaries of the DC bus voltage for
minimum and maximum operating voltages, the line under- The components are calculated to satisfy the constraints of four
voltage lockout threshold, and the lowest input voltage that will parameters: DXDO (external duty ratio limit at VDROPOUT), DXHL
guarantee regulation of the output. (external duty ratio limit at VMAX), VUVLO (input voltage where
the TOPSwitch-GX starts switching), and the maximum transient
The broken horizontal line shows the maximum guaranteed input voltage VOV that is greater than VMAX.
duty cycle of TOPSwitch-GX. A value of 74% is recommended
for design.
3-87
Rev. C 04/05
While there are four resistors, only three are unknown because The voltages VDB, VZ and VL are respectively the forward drop
RA and RB are identical by definition. They are connected in of the rectifier in series with the Zener diode and RC, the Zener
series to keep the voltage across each one below its maximum voltage, and the voltage on the L pin as shown in Figure 1. The
rating. The three unknown resistors and one capacitor make Zener diode is chosen as required to raise the curve of DXMAX at
four unknown quantities that are determined by the four the low input voltages. It may not be necessary in all applications.
constraints. The Zener voltage is 6.8 V in this example.
Figure 8 illustrates the general case where DXDO is between the Next, select a value for DXHL that is between DHL_ACTUAL and
actual duty ratio DMAX_ACTUAL and DMAX_RESET at the input voltage DHL_RESET.
VDROPOUT. If the converter is not required to respond to transient
loads at the end of the holdup time, DXDO and DMAX_ACTUAL can VMAIN + VDMAINC
DHL _ ACTUAL =
be set to DMAX_RESET. Since response to transient loads is usually N
required at VMAX, the designer will want to set DXHL at a (VMAX − VDS ) S − VDMAINF + VDMAINC
NP
comfortable margin between DHL_ACTUAL and DHL_RESET.
(40)
VMAX
Begin with the computation of values for RA and RB to set the DHL _ RESET = 1 −
line under-voltage threshold VACUV. VDSOP (41)
VACUV 2 (35) Find the range of permissible values for DXDO. To compute the
RA = RB =
2 IUV upper and lower bounds on DXDO, define the intermediate
variable KXDO.
where VACUV is the AC input voltage (non-doubled) required for ⎛V NB
the converter to start, and IUV is the line under-voltage threshold DROPOUT − VBZL ⎞
current of the L pin of TOPSwitch-GX from the datasheet.
⎛ V D ⎞⎜ NP ⎟
K XDO ≡ mIL ⎜ I LD 0 − MAX − XHL ⎟ ⎜ ⎟
Choose the nearest standard resistor value for RA and RB. ⎝ RAB mIL ⎠ V N
⎜ MAX B − VBZL ⎟
⎝ NP ⎠
Define intermediate variables to make the expressions easier to
write and interpret. (42)
D − DIL 2
mIL ≡ IL1 (36) The upper bound for DXDO is then
I L 2 − I L1
⎛ V ⎞
D DXDO < mIL ⎜ I LD 0 − DROPOUT ⎟ − K XDO
I LD 0 ≡ IL + I L (37) ⎝ RAB ⎠
3 mIL (43)
RAB ≡ RA + RB (38) and the lower bound for DXDO is
VBZL ≡ VDB + VZ + VL (39) ⎛ V ⎞

mIL ⎜ I LD 0 − DROPOUT ⎟
⎝ RAB ⎠ (44)
DXDO >
In Equation (36), DIL1 and DIL2 are respectively the values of K XDO
1+
DCMAX at currents IL1 and IL2 into the L pin. Obtain these values DXHL
from the data sheet. (Note these are specified only for the
TOP248-TOP250 devices.) Use the typical values at first. Then
check that the circuit will perform properly at the high and low Choose an appropriate value for DXDO between DMAX_RESET and
ends of the tolerance range. DMAX_ACTUAL that also satisfies the boundaries of (43) and (44).
In Equation (37), DIL is the value of DCMAX at current IL into the Next, compute the intermediate constants r1 and r2.
L pin. Use the same DIL1 with IL1 or DIL2 with IL2 as in
Equation (36). Either pair will give the same result. ILD0 has a ⎛ NB ⎞
physical interpretation that cannot be realized: if the duty ratio ⎜ VDROPOUT − VBZL ⎟ DXDO
⎝ NP ⎠
reduction characteristic continued along its linear slope, it r1 ≡ (45)
V D
would reach zero at the current ILD0. I LD 0 − DROPOUT − XDO
RAB mIL
3-88
Rev. C 04/05
TOPSwitch-GX 2
VIN VB CONTROL Pin v + vB + 4vA vC
DMAX = B (50)
2vA
RUVA RUVB
where
Q1 2N3906 RD
vA = (51)
mIL
3.3 K
TOPSwitch-GX RC ⎛R N ⎞
X Pin vB = VBZL + I LD 0 RD − − VIN ⎜ D + B ⎟
RUVC mIL ⎝ RAB N P ⎠
(52)
5K ⎛ V ⎞
vC = RC ⎜ I LD 0 − IN ⎟ (53)
⎝ RAB ⎠
Remote
ON/OFF Now choose an appropriate value for the capacitor. Proper
choice of the capacitor allows the converter to operate safely
with transient input voltages greater than VMAX. The line
overvoltage feature of TOPSwitch-GX is not used in the
TOPSwitch-GX conventional fashion in this application. The circuit operates in
SOURCE Pin
an over-voltage mode that reduces the maximum duty ratio
PI-2824-121701
further by reduction of the switching frequency. The value of
the capacitor CVS is chosen to give the desired behavior in the
Figure 9. External Under-Voltage Lockout Circuit.
over-voltage mode.
⎛ NB ⎞ Select an input voltage VOV greater than VMAX that marks the
⎜ VMAX − VBZL ⎟ DXHL onset of over-voltage operation. Then compute the maximum
⎝ NP ⎠ duty ratio DXOV that corresponds to the specification in the
r2 ≡
V D TOPSwitch-GX data sheet for the Line Over-Voltage Threshold
I LD 0 − MAX − XHL Current IOV.
RAB mIL (46)
3
Compute the values for the resistors RD and RC.
DXOV = DIL − mIL ( IOV − I L ) (54)
r1 − r2 (47) Here DIL, mIL and IL are the same as in Equations (36) and (37).
RD =
DXDO − DXHL Finally, compute the capacitor value as
RC = r1 − DXDO RD (48)
⎛ VOV ⎞
Select the nearest standard resistor values for RC and RD.
⎜ IOV −
⎝ RAB ⎠
(
⎟ (1 − DXOV )TS − t R( ON ) )
CVS =
KOVHYS IOVHYS RD
Verify that the parameters are within the desired range with the (55)
actual component values.
where
IUV
VACUV = ( RA + RB ) (49)
2 TS is the switching period 1/fS in normal operation
tR(ON) is the Remote ON Delay
This is the AC input voltage (non-doubled) where the converter IOVHYS is the hysteresis of the IOV threshold
will begin to operate. KOVHYS is a constant selected by the designer.
The external duty ratio limit at any DC bus voltage VIN may be The first three parameters are taken from the data sheet. The
computed from the expression constant KOVHYS is selected to provide sufficient ripple voltage
3-89
Rev. C 04/05
on the capacitor for reliable operation of the circuit. The

recommended range for KOVHYS is 3 to 5. Choose the nearest RCS CCS
standard value for capacitor CVS. VIN
These expressions to compute the component values have been

simplified for ease of presentation. Some variables related to
parasitic elements have been ignored. NP NMAIN
CCP
If any of the results are not satisfactory, choose different

standard values for the resistors or a different voltage for the D1
Zener diode. Gross deviations from the desired results may
require different values for the parameters chosen at the
beginning of this step, since some sets of parameters may not be
compatible. VR1
D TOPSwitch-GX
Step 16 – Calculate Values for Resistors in Optional External VR2 CONTROL
Under-voltage Lockout Circuit C
The resistor network that determines the characteristics of the VR3

external duty ratio limit sets the minimum voltage where the S
converter begins to operate. The contributions of current from

the bias voltage create too much hysteresis for the circuit to be
useful as an under-voltage detector after the converter begins to
operate. Therefore, the external under-voltage circuit in Primary
Return
Figure 9 is recommended for applications where a positive turn- PI-2825-121701
off threshold is desired.
Figure 10. Recommended Clamp Circuit.
Choose a value VACUVL for the turn-off threshold and a value
VACUVX that is approximately midway between VACUVL and resistor that can dissipate PRUVA watts.
VACUV: 2
2V
VACUVL < VACUVX < VACUV RUVA = MAX (61)
(56) PRUVA
The corresponding DC bus voltages (non-doubled) are A typical resistor for this purpose will have a power rating of
3 PRUVA = 125 mW. Choose the nearest standard value for RUVA.
VUVX = VACUV 2 (57) Then compute RUVB and RUVC.
VUVX = VACUVX 2 (58)

⎛ NB V − v ⎞
⎜ N UVL 1 ⎟
RUVB = RUVA ⎜ P (62)
⎛ 1 ⎞ V − VUVL ⎟
2 PO ⎜ − tC ⎟ (59)
⎜ UVX ⎟
2 ⎝ 2 fL ⎠ ⎝ ⎠
VUVL = 2VACUVL −
ηDC CIN
⎛ v ⎞ (63)
RUVC = RUVA ⎜ 1 ⎟
Define the intermediate variable v1 that considers the voltage ⎝ VUVX ⎠
VC(SHUNT) on the CONTROL pin and the base-emitter voltage on
the transistor.
v1 = VC ( SHUNT ) − VBEQ1 Choose the nearest standard values for RUVB and RUVC. Then
(60) check VACUVL and VACUVX with the actual resistor values.
Compute the approximate value of RUVA to meet the constraint

of maximum power dissipation. Assume a 50% derating for a
3-90
Rev. C 04/05
VAUX
LF VMAIN
R3 C1
R5 R6
R1
NP NMAIN CF
C2 R4
R2
U1
TL431 R7
RTN
U2
PI-2826-121901
Figure 11. General Configuration of Feedback Circuit for Forward Converter with TOPSwitch-GX.
⎛R ⎞ This arrangement limits the voltage on the drain of the

v1 ⎜ UVB + 1⎟ TOPSwitch-GX to approximately the sum of the voltages of the
⎝ RUVC ⎠ (64) string of Zener diodes. It also recovers most of the energy from
VUVL =
RUVB N B leakage inductance and magnetization inductance, and returns
+ it to the input or delivers it to the output.
RUVA N P
Select the Zener diodes to limit the drain voltage to VDSOP.
3
Choose the voltage, size and number of diodes in the string to
⎛ 1 ⎞ achieve the desired VDSOP and to handle the power dissipation.
PO ⎜
2 − tC ⎟ This arrangement is adequate for applications where the clamp
V ⎝ 2 fL ⎠
VACUVL = UVL + (65) circuit dissipates less than 5 W.
2 ηDC CIN
Capacitor CCP supplements the natural stray capacitance on the
drain node to absorb energy that comes mostly from the leakage
v1 ⎛ RUVA ⎞ (66) inductance. The value must be selected empirically because it
VACUVX = ⎜1 + ⎟
2⎝ RUVC ⎠ is difficult to predict natural stray capacitance and leakage
inductance accurately enough to calculate a proper value.
Energy not absorbed by the capacitance will be dissipated in the
If VACUVL and VACUVX are not satisfactory, adjust the values of Zener string, so CCP cannot be too small. If CCP is too large, its
the resistors. voltage will change too slowly to allow the transformer to reset
during transients. Typical values for CCP are in the neighborhood
Step 17 – Choose Components for the Clamp Circuit of 2 nF.
Figure 10 shows connections for the elements of a Zener clamp
circuit that is suitable for many applications. Capacitor CCP, Diode D1 must be a slow recovery type such as a 1N5407. The
diode D1 and the string of Zener diodes are on the primary side recovery of D1 removes enough charge from CCP to stabilize its
of the transformer. Resistor RCS and capacitor CCS are on the voltage and to discharge some of its stored energy into the
secondary side of the transformer. primary of the transformer. This energy returns to the input on
the next switching cycle.
3-91
Rev. C 04/05
The remaining components are connected across the forward voltage of the TL431 when VMAIN and VAUX are at their desired
diode on the main output. Energy from leakage inductance on values.
the secondary and magnetization inductance of the transformer
charges CCS when the TOPSwitch-GX turns off. The energy High frequency information that is most important in the
from CCS is delivered to the output during the next switching transient response comes through the path formed by the
cycle. Resistor RCS provides damping for oscillations that optocoupler’s diode and R2. This same technique is commonly
would otherwise occur from the resonance of CCS with stray used with TOPSwitch-GX in flyback converter applications.
inductance.
The values of R1, R3, R4, C1 and C2 are chosen to shape the
Typical values are in the neighborhood of 0.1 µF for CCS and frequency response. The choices are influenced by the
1 Ω for RCS. The resistor must dissipate power that corresponds components on the CONTROL pin and equivalent series
to the charge and discharge of CCS each cycle. It typically will resistance of the output capacitor, which can be important
dissipate less than 1 watt. Proper values must be determined features of the loop gain. Designers must make proper
empirically from evaluation of prototype hardware. measurements of loop gain and transient response on prototype
hardware to confirm that the converter performs as desired
Step 18 – Choose Components for the Feedback Circuit under all specified conditions.
The pulse width modulator in TOPSwitch-GX sets the duty
ratio according to the current into the CONTROL pin. Evaluation of Prototype Hardware
TOPSwitch-GX senses the drain current for protection only, and
does not use it for control purposes. Thus, forward converters The design that results from the steps of the previous section
with TOPSwitch-GX operate with a voltage-mode control that contains the uncertainties of the initial assumptions. Performance
modulates the converter’s duty ratio directly according to an must be validated with measurements on prototype hardware
error signal from the regulated output voltage. Voltage mode before the design is complete.
control provides sufficient loop bandwidth and is fully able to
meet all the specifications for PC Main and other high power At this stage in the procedure, the designer will have enough
applications. information to build a circuit that will operate at nominal
conditions for evaluation on the bench. The designer must test
The general configuration of the feedback circuit for a forward the circuit at all the limits of specified performance.
converter with TOPSwitch-GX is illustrated in Figure 11. It Measurements will indicate which changes to the original
shows a typical connection of a TL431 voltage regulator with assumptions are necessary. A successful design is obtained
an optocoupler and components for frequency compensation. after repetition of the procedure with parameters adjusted from
There is an optional connection to VAUX to improve the regulation measurements on the hardware.
of the auxiliary output by sharing regulation with the main
3 output. This general technique is common in all types of The evaluation should include observation of the drain-to-
multiple output regulators. source voltage on TOPSwitch-GX under steady state operation
and transient conditions. Apply power to the converter slowly
While the design of the feedback loop is beyond the scope of with minimum loads. Then exercise the loads on the outputs in
this application note, it is useful to consider the general circuit different combinations, first at the nominal input voltage and
of Figure 11. The components are chosen to provide regulation then at the extremes of input voltage.
of output voltages and to shape the frequency characteristics of
the control loop. Proper design of the feedback components is Observe the behavior at various static loads before going to
important not only for the stability of the system, but also for transient loading. Check for excessive power dissipation in the
transient response of the output. clamp circuit. A useful technique is to monitor the average
current in the string of Zener diodes in the clamp circuit with a
Inductor LF with capacitor CF reduces high frequency noise on low value resistor in series. A capacitor in parallel with the
the main output. As such, it introduces phase shift in the small resistor will develop a voltage proportional to the average
signal response that would make loop compensation difficult if current through the diodes. The product of this voltage and the
the only feedback for the main output were taken from the clamp voltage gives an indication of the power dissipation in the
voltage on CF. To avoid difficulties with the feedback loop, Zener diodes.
information about the main output is taken from two places.
Monitor the drain current when the output has steady-state
Low frequency information that is most important to the DC overload and during transient loading. The waveform will
regulation comes mainly through the path formed by resistor provide important information about the operation of the
divider of R5, R6 and R7. The voltage on R7 is the reference converter and the limits of the design. Check that the current
3-92
Rev. C 04/05
limit of the TOPSwitch-GX is sufficient for all the specified • Confirm in bench evaluations that CCP in the clamp circuit on
conditions. the primary is not too large. Perform transient load tests at
low and high input voltages. Monitor the drain voltage
Check that the transformer does not saturate under all steady- waveform for volt-second balance to be certain that the
state combinations of line and load. Verify the proper design of transformer does not saturate.
the circuit to limit maximum duty ratio with the procedure in
Appendix B. • Check the temperature of the Zener diodes VR1, VR2 and
VR3 in the clamp circuit under maximum load at low input
Check the ripple on all the output voltages with several voltage and with repetitive transient loading. If the power
combinations of input voltage and output loading, particularly supply does not have a latching shutdown for fault conditions,
if the design uses a coupled inductor. Verify that the under- check it under a sustained short circuit on the output. There
voltage thresholds are within design limits for startup and for could be excessive heating if CCP is too small, the primary
shutdown. inductance of the transformer is too low, or if the leakage
inductance it too high.
Key Design Considerations
• Match the current limit to the load. Use the X pin to program
While the design of forward converters with TOPSwitch-GX the current limit lower, especially if a larger TOPSwitch-GX
has much in common with designs that use discrete transistors is selected for thermal or efficiency reasons.
and controllers, some important differences must be considered.
Attention to these items will significantly reduce the time to References
arrive at a successful design.
[1] R. W. Erickson and D. Maksimovic, ´ Fundamentals of
• A proper clamp circuit is required to control the maximum Power Electronics, Second Edition. Kluwer Academic
drain voltage. Resonant clamp circuits are not recommended. Publishers, 2001. ISBN 0-7923-7270-0.
While the example clamp circuit in this document is suitable
for moderate power levels, the circuit will need modification [2] Colonel Wm. T. McLyman, Transformer and Inductor
to adapt to applications that require the dissipation of more Design Handbook, Second Edition. Marcel Dekker, Inc., 1988.
power. ISBN 0-8247-7828-6.
• Leakage inductance of the transformer affects the power [3] Colonel Wm. T. McLyman, Magnetic Core Selection for
dissipation in the clamp circuit. High leakage inductance Transformers and Inductors, A User’s Guide to Practice and
will prohibit the use of simple clamp circuits. Be aware that Specification, Second Edition. Marcel Dekker, Inc, 1997.
a magnetic amplifier post regulator will greatly increase the ISBN 0-8247-9841-4.
effective leakage inductance of the transformer. 3
[4] Colonel W. T. McLyman, Designing Magnetic Components
• The primary inductance of the transformer affects the power for High Frequency dc-dc Converters. Kg Magnetics, Inc.,
dissipation in the clamp circuit. Maximize the primary 1993. ISBN 1-883107-00-8.
inductance to reduce the magnetizing current and the energy
that must be processed by clamp circuit. [5] Micrometals Inc., 5615 E. La Palma Avenue, Anaheim, CA
92807 USA; www.micrometals.com.
• Use a slow diode for the rectifier D1 in the clamp circuit. A
fast diode will greatly increase the amount of energy that the [6] MAGNETICS, P.O. Box 391, Butler, PA 16003-0391 USA,
clamp must dissipate. www.mag-inc.com.
• Remember that the components RCS and CCS on the secondary

are important components of the clamp circuit. Failure to
include this network will cause excessive power dissipation
in the clamp components on the primary.
3-93
Rev. C 04/05
Appendix A
Table of Nomenclature
Name in AN-30 Description
δD Difference between actual and effective duty ratio that results from leakage inductance in
the transformer.
η Total system efficiency (lower case Greek letter eta).
Efficiency excluding losses in AC input circuit and EMI filter. Used in computation of input
ηDC
capacitance required for holdup time. ηDC η.
µ0 Permeability of free space (4π x 10-7 H/m).
µr Relative permeability of ferrite core material (lower case Greek letter mu). Dimensionless.
Ae Effective cross-sectional area of transformer core.
AL Inductance coefficient of ungapped transformer core.
BM Maximum AC flux density in transformer core.
BPEAK Maximum flux density in the power transformer.
CIN Total bulk capacitance at the DC input to the converter.
CVS Capacitor in circuit for external reduction of DCMAX.
D1 Diode in primary clamp circuit.
D Duty ratio of TOPSwitch-GX at a given operating point.
DHL_ACTUAL Duty ratio at the highest operational DC input voltage VMAX.
DHL_RESET Maximum duty ratio to guarantee reset of the transformer at DC input voltage VMAX.
DIL Maximum duty ratio at current IL.
DIL1 The DCMAX at current IL1 into the L pin of TOPSwitch-GX.
DIL2 The DCMAX at current IL2 into the L pin of TOPSwitch-GX.
DLL_ACTUAL Duty ratio at lowest steady state DC input voltage VMIN.
DLL_RESET Maximum duty ratio to guarantee reset of the transformer at DC input voltage VMIN.
DMA The duty ratio of the magnetic amplifier.
3 DMAX The maximum duty of TOPSwitch-GX at the lowest operational DC input voltage VDROPOUT.
DMAX_ACTUAL Actual duty ratio of TOPSwitch-GX at the lowest operational DC input voltage VDROPOUT.
Maximum duty ratio to guarantee reset of the transformer at DC input voltage VDROPOUT.
DMAX_RESET
This is less than maximum duty cycle DCMAX.
DNOM Duty ratio at nominal input voltage.
DRESET Maximum duty ratio to guarantee reset of the transformer at a given operating point.
Highest maximum duty cycle as set by current into the L pin of TOPSwitch-GX with external
DXDO
components. Occurs at DC input voltage VDROPOUT.
The lowest maximum duty cycle as set by current into the L pin of TOPSwitch-GX with
DXHL external components at DC input voltage VMAX.
DXOV The maximum duty ratio that corresponds to IOV.
DCMAX Maximum default duty cycle of TOPSwitch-GX (see Data Sheet).
fL AC line frequency.
fS TOPSwitch-GX switching frequency.
ij Instantaneous current in secondary winding j of the transformer.
IAUX Output current of the auxiliary output
IDAVBR Current rating for the bridge rectifier.
IL Current into the L pin of TOPSwitch-GX.
3-94
Rev. C 04/05

IL1 Current into the L pin of TOPSwitch-GX to give DCMAX of DIL1.
IL2 Current into the L pin of TOPSwitch-GX to give DCMAX of DIL2.
Intermediate variable to compute values of components in circuit for external reduction of
ILD0
DCMAX.
IMAIN Output current of the main output.
IMAINMA Output current of the magnetic amplifier on the secondary winding for the main output.
Current in the secondary winding of the main output required to stop conduction of the main
IMAINSEC
catch diode.
IMAXIMUM Maximum average output current for a specific output.
IMINIMUM Minimum average output current for a specific output.
IMP Peak value of the magnetizing current of the transformer referred to the primary winding.
IIND Output current of the independent output.
IOUTPUT Average current on a given output.
IOV Line over-voltage threshold current for the L pin of TOPSwitch-GX (see data sheet).
IOVHYS Hysteresis of the IOV threshold (see data sheet).
IP Instantaneous current in the primary of the transformer.
IPP Peak current in the primary of the transformer.
IRMS RMS current in an output capacitor. .
IUVHYS Hysteresis in line under-voltage threshold current (see data sheet).
IXLIMIT TOPSwitch-GX current limit with external current limit reduction.
KI External current limit reduction factor.
K∆I0 Maximum theoretical value of the ripple current factor for an output inductor, approached as
D goes to zero.
K∆I Ripple current factor for an output inductor at a given operating point.
KOVHYS Constant used to compute value of capacitor in circuit for external reduction of DCMAX.
KXDO
DCMAX.
e Effective path length of transformer core.
3
g Length of air gap in transformer core.
Inductance of the coupled inductor measured at the winding for the main output with other
LMAIN
windings open.
LMAINLK Leakage inductance of the transformer on the secondary winding for the main output.
Output inductor in the magnetic amplifier regulator on the secondary winding for the main
LMAINMA
output.
mIL Maximum Duty Cycle Reduction Slope (a positive number).
LP Inductance of the primary of the transformer with all other windings open.
nAUX Turns ratio of the auxiliary output winding with respect to the main output winding.
nIND Turns ratio of the independent output winding with respect to the main output winding.
nj Turns ratio of secondary winding j of the transformer with respect to the main output winding.
nP Turns ratio of the primary winding with respect to the main output winding.
Nj Actual number of turns for secondary winding j on the transformer.
NAUX Number of turns for the auxiliary winding on the transformer.
NB Number of turns for the bias winding on the transformer.
NIND Number of turns for the independent winding on the transformer.
NMAIN Number of turns for the main output winding on the transformer.
3-95
Rev. C 04/05

NP Number of turns for the primary winding on the transformer.
PO Total output power of the power supply.
PRUVA Power dissipation in the resistor RUVA.
r1
DCMAX.
r2
DCMAX.
RA Resistor in the network that sets the line under-voltage threshold VACUV.
RAB DCMAX.
RB Resistor in the network that sets the line under-voltage threshold VACUV.
RC Resistor in circuit for external reduction of DCMAX.
RD Resistor in circuit for external reduction of DCMAX.
RLMAIN Resistance of the winding of the output inductor for the main output.
RP Resistance of the primary winding of the transformer.
RSMAIN Resistance of the secondary winding for the main output.
RUVA Resistor in optional external under-voltage lockout circuit.
RUVB Resistor in optional external under-voltage lockout circuit.
RUVC Resistor in optional external under-voltage lockout circuit.
tC Conduction time of the bridge rectifier.
tH Holdup time.
tR(ON) Remote ON Delay of TOPSwitch-GX. (See data sheet).
TS Switching period of TOPSwitch-GX, equal to 1/fS.
v1 Intermediate variable to compute resistors in optional external under-voltage lockout circuit.
vA Intermediate variable to compute values of DXMAX.
3 vB Intermediate variable to compute values of DXMAX.
vC Intermediate variable to compute values of DXMAX.
VACHOLDUP Steady state AC input voltage that corresponds to the beginning of the holdup time.
VACMAX Maximum steady-state AC input voltage.
VACMIN Minimum steady-state AC input voltage.
VACNOM AC input voltage where independent output voltages should be at their nominal values.
VACUV Minimum AC input voltage where converter must start.
VACUVL AC input voltage where the converter shuts off with optional external UVLO circuit.
AC input voltage where the optional external UVLO circuit enables the TOPSwitch-GX when
VACUVX
input voltage is rising from zero.
VAUX Voltage on the auxiliary output.
VAUXREF Reference voltage for the auxiliary output in the DC stacked topology. This is usually VMAIN.
VBZL Intermediate variable in the computation of components for DCMAX reduction circuit.
VDAUXC Voltage drop on the catch diode of the auxiliary output when the diode is conducting.
VDB Voltage drop on the diode of the bias winding when the diode is conducting.
VDINDC Voltage drop on the catch diode of the independent output when the diode is conducting.
VDINDF Voltage drop on the forward diode of the independent output when the diode is conducting.
VDMAIN Voltage drop on the catch diode and the forward diode of the main output when the two are
identical.
3-96
Rev. C 04/05
VDMAINC Voltage drop on the catch diode of the main output when the diode is conducting.
VDMAINF Voltage drop on the forward diode of the main output when the diode is conducting.
VDROPOUT Lowest DC input voltage that will guarantee a regulated output.
VDS Average drain-to-source voltage on the TOPSwitch-GX during its on-time.
VDSOP Maximum drain-to-source voltage on the TOPSwitch-GX during operation.
VHOLDUP DC input voltage that marks the beginning of the holdup time tH.
VIN Voltage on the bulk input capacitance CIN.
VIND Voltage on the independent output.
VL Voltage on the L pin of TOPSwitch-GX with positive current.
VLL Average DC input voltage at VACMIN .
VMAX Maximum DC input voltage, equivalent to the peak value of VACMAX.
VMAIN Regulated DC voltage on the main output.
VMAINMA Regulated DC voltage from the magnetic amplifier derived from the secondary winding for the
main output.
VMIN Valley of the rectified AC input voltage at VACMIN.
Nominal DC input voltage. Midpoint between peak and valley of the ripple voltage on CIN
VNOM
when the AC input voltage is VACNOM.
VPIVAC Recommended voltage rating for the bridge rectifier.
VUVH DC input voltage corresponding to VACUV.
VUVL DC input voltage corresponding to VACUVL.
VUVLO Minimum DC input voltage for TOPSwitch-GX to start, set by resistor on from DC input
voltage to L pin.
VUVX DC input voltage corresponding to VACUVX.
VZ Voltage of the Zener diode in the DCMAX reduction circuit.
W Number of secondary windings on the transformer.
3-97
Rev. C 04/05
Appendix B
Procedure for Verifying
Duty Ratio Reduction Circuit
Predictions from analytic expressions are only as accurate as of the input voltage and the regulated main output voltage while
their inputs. It is always advisable to confirm the desired monitoring the current into the L pin.
operation of circuits with actual hardware before they are
released to production. Reduction of the maximum duty ratio 1. Connect the AC input section in the non-doubling
of TOPSwitch-GX is particularly important in the forward configuration. Add enough extra bulk capacitance in parallel
converter application. Therefore, users are strongly advised to with CIN to make the ripple voltage negligible. Alternatively,
follow this simple procedure to confirm the correct operation of the converter may be operated from a high voltage DC
the circuit to reduce the maximum duty ratio. power supply instead of from the AC source. Insert the
parallel combination of a 100 Ω resistor and a 0.1 µF
Add the circuits and instrumentation as shown in Figures B1 capacitor in series with the L pin. Monitor the voltage across
and B2 to the forward converter under evaluation as described the resistor with a digital voltmeter. Place a 1 kΩ resistor in
in the steps below. This setup allows independent adjustment each lead of the voltmeter to avoid interference from common
VIN
RA
CCP
Added NP
Bulk RB
Cap
1800 µF
400 V CIN
0.1 µF 50 V
U1 RC RD VZ
TOP248Y
D L
100 Ω
CONTROL
C NB
CVS
3 S X F
To PWM
Regulator
Circuit
RTN
1 kΩ 1 kΩ
To On/Off
Circuit Digital Voltmeter
Monitor Drain Current with L pin Current Monitor Circuit

Oscilloscope to Determine (190 µA is 19 mV)
Duty Ratio
PI-3987-042205
Figure B1. Setup to Measure Current into LINE-SENSE (L) Pin.
3-98
Rev. C 04/05
mode noise. Monitor the current in the DRAIN pin of where DIL is the minimum DCMAX at the IL of 190 µA, and
TOPSwitch-GX with a current probe and an oscilloscope. the other terms are as they are defined in the text and
Connect an adjustable low voltage DC power supply to the Appendix A.
feedback circuit as shown in Figure B2.
5. Adjust the duty ratio to DIL by forcing the main output to
2. Set the oscilloscope to read the duty ratio from the waveform regulate at a higher voltage. To do this, reduce the voltage
of the TOPSwitch-GX drain current. Most digital of the bench power supply from 15 V until the duty ratio
oscilloscopes will provide a direct readout of the numerical measured from the drain current is DIL.
value.
6. Verify that the current into the L pin is within 5% of IL. The
3. Adjust the low voltage DC power supply to 15 V. voltmeter should read 19 mV when IL is 190 µA.
4. Operate the converter at full load. Adjust VIN to the value If it is not possible to adjust the circuit to meet these conditions,
that corresponds to the duty ratio limit specified in the data the circuit is not guaranteed to operate properly with all devices
sheet for a device at the low end of the tolerance range. The in the specified range of tolerance. Repeat the design with
DC input voltage for these conditions is given by revised parameters.
⎛ R ⎞
VBZL + I L ⎜ RD + C ⎟
⎝ DIL ⎠
VIN = (B1)
NB 1 ⎛ RC ⎞
+ ⎜ RD + ⎟
N P RAB ⎝ DIL ⎠
VMAIN
Main Output Regulator
Added Network to Adjust

Regulated Output
OPTO
3
+
1N4148 3.3 kΩ 0 VDC to +15 VDC

Adjustable Power Supply
_
3.3 kΩ
TL431
RTN
Start with the adjustable power supply at 15 V. By lowering the

output of the external supply a threshold will be reached where the
diode will become forward biased. Lowering the adjustable supply
further will force the main output to a higher regulation voltage.
PI-2846-041502
Figure B2. Circuit to Adjust Main Regulated Output Voltage to Higher Value.
Revision Notes Date

B - 12/02
C 1) Simplified to TOP248-250. 4/05
3-99
Rev. C 04/05
DPA-Switch®
DC-DC Forward Converter Design Guide
Introduction • Selectable 300 kHz or 400 kHz operation

• Lossless integrated cycle-by-cycle current limit
The single-ended forward converter topology is usually the
best solution for DC-DC applications in industrial controls, The example circuits in this design guide illustrate the use of
Telecom central office equipment, digital feature phones, and these and other features of DPA-Switch.
systems that use distributed power architectures.
The feature set of DPA-Switch offers the following advantages Scope

in DC-DC single-ended forward converter designs: This document gives guidance for the design of a single-
ended forward converter with DPA-Switch in applications
• Low component count that require a single output voltage. It is intended for systems
• High efficiency (typically >91% with synchronous engineers and circuit designers who wish to become familiar
rectification) with the capabilities and requirements of DPA-Switch in
• Built in soft-start to minimize stress and overshoot DC-DC applications. This application note provides background
• Built in accurate line under-voltage detection material that will assist users of the DPA-Switch DC-DC forward
• Built-in accurate line overvoltage shutdown protection converter design utility that is included in the software design
• Built in adjustable current limit tool, PI Expert. Subsequent application notes will provide
• Built-in overload and open loop fault protection comprehensive procedures for designs of greater complexity.
• Built-in thermal shutdown Designers are advised to check Power Integrationsʼ website at
• Programmable duty cycle reduction to limit duty cycle www.powerint.com for the latest application information and
excursion at high line and transient load conditions design tools.
• Very good light-load efficiency
Snubber
3 Power
Transformer
Output
Inductor
+ +
CCLAMP Bias Output

Voltage Capacitor VO
+ –
DC RUVLO
INPUT TL431 with
Drain Frequency
Clamp DPA-Switch Compensation
D L
CONTROL
U1
C FEEDBACK CIRCUIT
S F CBYPASS RFC
CFC
Input
Return
PI-2873-062204
Figure 1. Typical Configuration of DPA-Swtich in a Single-Ended DC-DC Forward Converter with One Output.
3-100
Rev. C 07/04
Description Symbol Min Typ Max Units Comment

Input
Input Voltage VIN 36 48 75 VDC Typical operational range
Input Voltage UV Turn ON 36 VDC
Input Voltage UV Turn Off 29 VDC
Input Voltage OV Turn On 72 VDC
Input Voltage OV Turn Off 90 VDC
Output
Output Voltage VOUT 4.8 5.00 5.2 V ±4%
Output Ripple and Noise VRIPPLE 50 mV 20 MHz Bandwidth
Output Current IOUT 0 6.00 A
Line Regulation ±0.2 %
Load Regulation ±0.5 %
Transient Response Peak 3 % of 50-75% Load step, 100 mA/µs
Deviation VOUT 48 VDC input
Transient Response Recovery 200 µs To 1% of final output voltage,

50-75% load step, 48 VDC input
Total Output Power
Continuous Output Power POUT 30 W
Efficiency
Low-Cost Design ηCost 84 % Measured at POUT (30 W),
Enhanced (non-sync rect.) ηEnhanced 87 % 25 °C, 48 VDC Input
. Synchronous Rectified Design ηSyncRect 91 %
t
d Environmental
Input-Output Isolation Voltage 1500 VDC
Ambient Temperature TAMB -40 85 °C Free convection, sea level
Table 1. Typical Specifications for a Single Output DC-DC Converter.
Figure 1 shows a typical implementation of DPA-Switch in

a power supply with a single regulated output. This design
designer must guarantee that the converter becomes active and
fully functional at a voltage that is lower than the minimum.
3
guide discusses considerations for selection of components
for a practical implementation of the circuit in Figure 1. It Tolerance variations of the Line Undervoltage Threshold of
also addresses options and tradeoffs in cost, efficiency and DPA-Switch with prudent design margin put the practical
complexity that include the substitution of synchronous rectifiers minimum operating voltage closer to 30 V. Similarly, the
and alternative generation of the bias voltage. converter must be designed to operate at voltages higher than
the maximum specified input. The actual input voltage range
System Requirements should be considered to be from about 30 V to 90 V for the
typical nominal input voltage of 48 VDC.
The design begins with an evaluation of the requirements.
Table 1 gives the specifications for the example converters Output Characteristics
described here, that have been constructed and evaluated as
engineering prototypes. Variants of the basic design achieve The output voltage can be maintained to ±4% over the range of
higher efficiencies with minor increases in complexity. line, load and operational temperature range with an ordinary
feedback circuit that uses a TL431 regulator. Transient response
Input Voltage Range is controlled with proper frequency compensation. The design of
the feedback network with guidance for selection of component
The actual input voltage range required for operation of the values is addressed in a separate section. Ripple and noise are
converter is greater than that indicated by the specification. The strongly influenced by the size of the output inductor and the
specification requires the converter to operate and to deliver choice of output capacitors. These topics are discussed more
full performance at a minimum input of 36 V. Therefore, the thoroughly later in this document.
3-101
Rev. C 07/04
+ +
U2
DPA-Switch
DPA-Switch U2
D L D L
CONTROL CONTROL
C C
S X F S X F
PI-3468-042303 PI-3469-042303
DC Input Derived Transformer Bias (unregulated)
(a) (b)
+ +
U2
3
U2 DPA-Switch
DPA-Switch
D L D L
CONTROL CONTROL
C C
S X F S X F
Output Coupled Inductor Bias PI-3470-042303 Transformer Bias (regulated) PI-3471-042303

(c) (d)
Figure 2. Methods for Generation of Bias Voltage.
Output Rectifiers
Output rectification may be accomplished with discrete Schottky in greater detail in a separate section. Ultra-fast PN junction
diodes for lowest cost or synchronous rectifiers for highest diodes are not suitable at DPA-Switch operating frequencies.
efficiency. This document discusses synchronous rectification
3-102
Rev. C 07/04
Efficiency because the voltage across the optocoupler is controlled. This

is countered by increased complexity. Optocoupler dissipation
Designing a DC-DC converter with DPA-Switch involves can be significant and should be verified. Maximum optocoupler
several engineering tradeoffs that weigh efficiency against cost phototransistor current is equal to the maximum CONTROL
and complexity. The circuit configuration in Figure 1 achieves pin current (IC(SKIP)) for the selected DPA-Switch. Maximum
efficiencies greater than 85% over the range of input voltage dissipation therefore occurs at the highest bias voltage (highest
at medium loads. In typical applications without synchronous input voltage for (a) and (b)) and minimum load. Table 2
rectifcation, approximately 25% of the total power loss will be in provides a comparison of complexity vs performance for all
the DPA-Switch (see DPA-Switch data sheet), 40% in the output the solutions.
rectifiers, and 30% in the magnetic devices. The remainder is
distributed among other devices and circuit traces. a) The DC input derived bias is the simplest of the three
solutions. It uses a Zener diode between the positive DC input
Higher efficiencies of approximately 91% can be obtained and the collector of the phototransistor of the optocoupler to
when Schottky rectifiers are replaced by synchronous rectifiers, reduce the maximum collector-to-emitter voltage, and more
allowing lower voltage drops. The efficiency can be raised importantly, to limit the dissipation in the optocoupler. The
even higher with the use of the next larger device in the penalty for simplicity is a reduction in efficiency that can
DPA-Switch family that has lower RDS(ON). Further increases in be significant at high input voltages. This alternative is best
device size may not improve the efficiency due to increased for industrial applications where the input voltage is low
device switching losses. Losses in the magnetic devices can (18 V to 36 V). The input voltage in industrial applications
be reduced by using larger cores and by switching at 300 kHz is usually low enough to eliminate the Zener diode because
instead of 400 kHz. All these alternatives have compromises in the breakdown voltages for standard optocouplers can be as
size, cost and complexity that the designer must evaluate. high as 70 V. Designers must check the maximum power
dissipation in the optocoupler in either case.
Temperature
b) The transformer bias (unregulated) is created from a winding
DC-DC converters usually must operate over an extended on the power transformer. The forward bias winding
range of temperature that goes beyond the limits for ordinary should be connected to the rectifier in a polarity such that it
consumer electronics. Designers should be aware that the conducts when the DPA-Switch is on. Since the bias voltage
characteristics of passive components are likely to change is proportional to the input voltage, efficiency is reduced at
significantly with temperature. Attention to these effects to high input voltages, but the effect is less than with the direct
choose suitable components can prevent unexpected and connection to the input. Again, the designer needs to check
undesirable behavior. the power dissipation in the optocoupler at the maximum bias
voltage. For this bias type, worst case is minimum output
Designers must pay particular attention to the selection of the load and high input voltage. Flyback bias windings are not 3
output capacitors and the components in the feedback circuit recommended for DPA-Switch applications since they will
to guarantee specified performance throughout the temperature affect the transformer reset.
range. The details are addressed later in the sections on Output
Capacitor Selection and Feedback Design. c) Output coupled inductor bias uses a winding on the output
inductor to develop the bias voltage. This technique
Bias Voltage provides a well regulated bias voltage when the converter
operates in the continuous conduction mode. Regulation
There are four ways to generate the bias voltage required for is accomplished by phasing the winding such that the bias
operation of DPA-Switch: voltage is proportional to the output voltage by transformer
action when the DPA-Switch turns off. The penalty for the
(a) DC input derived higher efficiency is the cost and complexity of a custom output
(b) Transformer bias (unregulated) inductor. The bias voltage can be adjusted by modifying turns
(c) Output coupled inductor winding ratio, bias capacitor size and minimum load on the main
(d) Transformer bias (regulated) output. The designer should verify a minimum bias voltage
of 8 V at minimum load and maximum input voltage.
Figure 2 illustrates the four alternatives. Each one must provide
a minimum of 8 V at the collector of the optocoupler under worst d) The transformer bias (regulated) solution peforms the
case operating conditions (minimum input voltage and minimum same function as the output coupled inductor bias (c). The
load). The lowest bias voltage under typical conditions should be bias voltage regulation is not quite as good as with the
12 V. The output coupled inductor and the regulated transformer output coupled inductor bias. However, the solution does
bias techniques give the highest efficiency of the four solutions provide a reasonably constant bias voltage over a variety
3-103
Rev. C 07/04
Input Voltage
Bias Type Efficiency Cost Complexity Comment
Range (V)
DC Input Recommended
18 to 36 ⇓ ⇓
Derived Bias for 18 to 36 V only
Transfer Bias Recommended for
36 to 72 ⇔ ⇓
(unregulated) low-cost design
Only recommended if
Output Coupled
36 to 72 ⇑ ⇑ supply already requires
Inductor Bias
coupled output inductor
Transformer Bias Recommended for high
36 to 72 ⇑ ⇔
(regulated) efficiency designs
Table 2. Bias Voltage Solution Comparison.
of input voltage and output load conditions. This solution 50% because DPA-Switch uses a voltage mode control. The
works best if the independent inductor is maintained in quotient is the upper limit for the turns ratio.
the continuous conduction mode. The solution can be
implemented with a low current, low cost (off-the-shelf) Core and Copper
inductor, but the inductance value will be high enough to
ensure continuous conduction mode over the majority of The actual number of turns for the transformer will depend
operating conditions. on the dimensions of the particular core. The core material
should be low loss at the DPA-Switch operating frequencies.
Technical data on properties of ferrite cores are available from
Transformer Design several suppliers. See references [1], [2] and [3]. Skin effect
The power transformer is critical to the success of the converter and proximity effect will set a practical limit for wire size. Foil
design. Requirements for efficiency, component height and windings become attractive when the output current is higher
footprint will determine the details of construction. System than about 6 A.
engineers and circuit designers may choose to specify the
electrical parameters and mechanical limits, and delegate the Thermal considerations often dominate selection of the core.
construction details to a supplier of custom transformers. Use the The selection of the core is a complex trade-off between winding
3 PI Expert design tool to determine the proper parameters. This
section gives guidance for specification of the transformer.
area, core cross-section and ratio of core surface area to core
volume. These parameters determine the power loss as well
as the thermal resistance of the transformer. A small core may
Turns Ratio meet the requirements in every respect except temperature
rise, forcing the use of a larger core. The only practical
The most important parameter for the power transformer is way to check temperature rise is with bench evaluation of a
the primary-to-secondary turns ratio. It must be low enough prototype. Temperature must be measured at the hottest spot
to provide the regulated output voltage at the minimum input in the transformer, which is usually next to the center of the
voltage. Determine the minimum input voltage from the system core under the windings. Wire temperatures above 110 °C need
specification and the tolerance of the line under-voltage lockout special considerations and UL Class F materials.
circuit.
Other Practical Considerations
Whereas the minimum input voltage may be specified at
36 V, worst case tolerances of the under-voltage circuit are Minimize the number of turns within the limits of other
likely to allow the DPA-Switch to operate at an input as low as constraints. Resistive losses depend on the length of the wire.
29 V. From this voltage, subtract the estimated drain-to-source Maximize the amount of copper (wire) that can be fitted within
voltage of DPA-Switch at the maximum load. Reduce it further the winding window. Leakage inductance must be kept low to
by an estimate of the voltage drop from the high frequency AC reduce losses associated with clamp components. This is best
resistance of the transformer windings at full load. accomplished with a split primary construction that has the
secondary between the layers of the primary winding. Also,
Multiply the result by the maximum guaranteed duty ratio and all transformers should have no air gap.
divide by the sum of the output voltage and the drop on the
output rectifier at full load. The duty ratio can be greater than
3-104
Rev. C 07/04
90% lower ripple and a larger inductor. Recommended values for
PI-2886-042204
K∆I are between 15 and 20 percent. The choice of K∆I involves a
88% trade-off between the size of the inductor, the number and type
of output capacitors, efficiency, and cost. Higher values of K∆I
Efficiency (%)
are not recommended, as these higher ripple currents increase

86% both the stress and the ripple voltage on the output capacitor.
84% Whether the inductor is standard off-the-shelf or custom, the

design should minimize the number of turns to reduce the
resistive loss. The construction should also use a low loss core
82% DPA424
DPA425 material.
DPA426
80% With user input, the PI Expert design tool computes the
35 40 45 50 55 60 65 70 75 inductance, the RMS current and the peak stored energy to aid in
DC Input Voltage the selection or specification of the inductor. Peak stored energy
Figure 3. Efficiency of the Low Cost EP-21 Prototype with Different is a useful parameter to select designs that use a closed toroid
Devices in the DPA-Switch Family (Synchronous core, where magnetic saturation is generally a concern.
Rectification Would Improve Efficiency).
Additional Winding for Bias Voltage
If the transformer has a winding for the bias voltage, be sure
that it has enough turns to maintain a minimum of 8 V bias at If the configuration in Figure 2 (c) is chosen for generation of the
the lowest input voltage. Perform bench verification to confirm bias voltage, choose the number of turns on the bias winding to
that the converter shuts off at low input voltages by virtue of give 12 V at the optocoupler under nominal conditions. Compute
the under-voltage lockout circuit, and not because the bias the required number of turns from the lowest regulated output
voltage is too low. voltage and the highest forward voltage drops for the output
rectifier and the bias rectifier. Check the bias voltage at minimum
With the actual number of turns on the transformer, verify that load, maximum line, and add a preload if necessary to maintain
the duty ratio to regulate the output at the minimum input voltage the bias voltage at 8 V minimum. It may also be necessary to
is less than the minimum DCMAX specified for DPA-Switch. increase the bias winding turns to meet the minimum voltage
requirement with a reasonably small pre-load.
The AC flux density contributes to the core losses. For this
reason the AC flux density should be maintained in the range DPA-Switch Selection
between 1000 and 1500 gauss (0.1 to 0.15 tesla).
The first criterion for the selection of the DPA-Switch is peak 3
current capability. From the turns ratio of the transformer and
Output Inductor the peak current in the output inductor, estimate the peak current
For a single output application with no bias winding, the in the primary of the transformer. The magnetization current of
inductor can be a standard off-the-shelf component. Inductors the transformer should be negligible for this estimate. For lowest
with multiple windings are typically custom designs. cost, select the smallest DPA-Switch that has a minimum current
limit that is at least 10% greater than the maximum primary
The inductor value is determined chiefly by the amount of current current. The allowance of 10% greater current gives design
ripple that the designer is willing to tolerate. Higher ripple margin with the ability to respond to transient loading.
current will allow an inductor that is smaller both electrically
and physically. The consequence of higher ripple current is the The second criterion for the selection is power dissipation. The
requirement for more output capacitance with lower equivalent smallest DPA-Switch that will handle the current may dissipate
series resistance (ESR) to meet the specification for output ripple. too much power to meet the efficiency requirements. Even if
Higher current ripple in the inductor also translates to higher efficiency is not a concern, the smallest device may get too hot if
peak current in the DPA-Switch for a given output power. It also system constraints prevent good thermal design. Multiplication
leads to generally greater loss and lower efficiency because the of the RDS(ON) by the square of the RMS current in the primary
RMS value of all the currents will be higher. gives a reasonable estimate of the power dissipation in the
DPA-Switch. The DPA-Switch dissipates approximately 25%
A convenient design parameter for selection of the inductor is of the total system loss in designs without synchronous
K∆I, defined as the ratio of the peak-to-peak ripple current to rectifiers.
the average current in the inductor. Smaller K∆I corresponds to
3-105
Rev. C 07/04
If power dissipation is a problem with the smallest device, select need for this clamp capacitor. Bench tests will determine
the next larger device and program the current limit with the whether the capacitor is required to maintain safe drain-to-
X pin to 10% above the peak primary current. This is done to source voltages. In normal steady-state operation, the capacitor
limit overload power capability. Refer to the DPA-Switch data CCP across the primary of the transformer absorbs energy from
sheet to determine the value of the resistor on the X pin that leakage inductance to keep the drain-to-source voltage below
corresponds to the desired current limit. the Zener voltage. There is an optimum value for CCP that
typically ranges between 10 pF and 100 pF for converters in
Figure 3 illustrates how the efficiency is related to the selection the range of 10 W to 40 W.
of the DPA-Switch. Devices with lower RDS(ON) dissipate less
power where resistive voltage drop dominates the loss. Thus, The value of CCP depends on the leakage inductance and the
the efficiency is higher for larger devices at low input voltage. peak current. The proper value of capacitance will allow most
At higher input voltages the RMS current in the DPA-Switch of the energy in the leakage inductance to be recovered during
decreases and the loss from capacitance on the drain increases, the next switching cycle. Too little capacitance will cause the
so the lower RDS(ON) has virtually no effect on efficiency. Zener diode to conduct. Dissipation in the Zener will reduce
efficiency. Too much capacitance will also reduce efficiency
Clamp Circuit because it will increase turn-on losses in the DPA-Switch and
may also interfere with the reset of the transformer.
All applications must protect the DPA-Switch from excessive
drain voltage. Figure 1 shows a simple and effective solution. The Zener diode does not conduct during normal steady-state
A Zener diode from the drain to source provides a hard clamp. operation, but it is required to limit the drain voltage during
The 30 W prototype example (Table 1), uses a 150 V Zener to start-up, transient loading and overload conditions.
guarantee substantial margin from the breakdown voltage of
220 V. A small capacitor across the primary of the transformer At higher powers, the clamp capacitor value (CCP), becomes a
may be necessary in conjunction with the Zener clamp (see limiting factor on the efficiency of the power supply. Different
Figure 4). techniques can be used for these higher power applications
(above approximately 40 W). Figures 5 and 6 show a non-
The designer should put a placeholder for this capacitor on dissipative clamp technique that also resets the transformer.
the initial prototype. In some designs there is sufficient stray See references [4] and [5] for a description of this technique.
capacitance on the primary of the transformer to remove the
Transformer Reset Circuit
CS RS The flux in the magnetizing inductance of the transformer
must be reset in each switching cycle to maintain volt-seconds
3 DC INPUT
CCP +
D2
C1
DPA-Switch
U1 DC
D Input L1
Voltage VDS
CONTROL D
VR1 C
V1 CONTROL
S
DPA-Switch
D1
DC INPUT
PI-2875-062204 PI-3474-032603
Figure 4. Components of the Transformer Clamp and Reset Circuit. Figure 4. LC (Inductor Capacitor) Reset and Clamp.
3-106
Rev. C 07/04
C7
1 nF
C3, C4, 1.5 kV
C5, C6
+VIN 1 µF,
36-72 VDC 100 V (x4)
1 T1
L1
J1-1 1 µH C13, C14,
2.5 A C12 D4 L3 C15, C16, C17 L4 C18 C19 C20
4.7 nF 42CT030S 3.3 µH 100 µF, 100 nH 100 µF 100 µF 1 µF
9, 10 50 V 20 A 10 V (x5) 20 A 10 V 10 V 10 V 5 V, 14 A
D1 R1 2
619 kΩ J2-2
UF4003
D5
R5 R6 42CT030S
6.8 Ω 6.8 Ω J1-1
3
6, 7 RTN
C8
470 pF
200 V
D3
C1 C2 BAV19 C9
1 µF 1 µF WS 4.7 µF
100 V 100 V 25 V U2
L2 U2
100 µH PC357N3T R8
10 kΩ R13
DPA-Switch 10.0 kΩ
D L U1 1%
DPA426R
CONTROL
C D5 C23
BAV19WS 68 nF
R10 R11
S X F 220 Ω 5.1 Ω
R4 R9
1.0 Ω 220 Ω
VR1 C10
SMBJ C21
220 nF C11 10 µF C22
150
R3 68 µF 10 V 1 µF
D2 10 V U3
UF4003 6.8 kΩ
J1-2 1% LM431AIM3 R14
10.0 kΩ
1%
INPUT RTN
PI-2882-062204
Figure 6. A 70 W DC-DC Converter that uses an Alternative Circuit to Reset the Transformer.
balance and prevent saturation. Since real transformers have conditions. The resistor in the reset network damps oscillations
finite inductance, they store parasitic energy that is represented from the interaction of the capacitor with parasitic inductance.
as a magnetizing current. The value of the resistor is typically between 1 Ω and 5 Ω.
The magnetizing inductance cannot store very much energy A different reset circuit is required for applications higher than
before it saturates. Since a saturated transformer behaves like about 40 W. Figure 6 shows an example of a 70 W converter
a short circuit, external circuitry must manage the removal that uses the circuit of Figure 5 to reset the transformer and to
of the energy from the magnetization inductance (reset the limit the voltage on the DPA-Switch. 3
transformer) on each switching cycle.
Verification of Transformer Reset
This transformer reset will require the voltage on the DRAIN
pin to rise above the input voltage. The designer needs to be Users should confirm that the transformer resets under worst
sure that the transformer reset does not cause voltage overstress case conditions at the lowest and highest input voltages with
on the DRAIN pin of the DPA-Switch. measurements on the bench. Figure 7 illustrates three situations
that show proper transformer reset with the reset circuit in
Figure 4 shows the components for the circuit that resets the Figure 4. Three examples of improper transformer reset are
magnetizing energy in the transformer to a safe value at the shown in Figure 8.
end of each switching cycle. The heart of the circuit is the
series RC network (RS and CS) that is connected across the The best way to assess the reset characteristics is to observe the
output rectifier. drain-to-source voltage on the DPA-Switch. Figure 7 (a) shows
the voltage on the prototype example when it operates from an
When the DPA-Switch turns off, current in the magnetizing input of 72 VDC. It is operating at full load with a reset capacitor
inductance leaves the transformer through the secondary (CS) of 2.2 nF across the output rectifier. The clamp capacitor
winding. The capacitor charges as the magnetizing current on the primary is 47 pF. See Design Idea DI-24 (available on
reduces to zero. The capacitor must be small enough to allow www.powerint.com) for a circuit example.
the magnetizing current to go to zero within the minimum
offtime. An additional restriction on the size of the capacitor is The figure shows the important intervals of the waveform
that it must be large enough to keep the drain-to-source voltage within one switching period TS. DPA-Switch is conducting
below the voltage of the Zener clamp under normal operating during the time tON = D TS, where D is the duty ratio. Flux in
3-107
Rev. C 07/04
300 300
250 TS 250
200 200
tON tRZ tRN tV0
150 150
Voltage (V)
Voltage (V)
100 100
50 50
0 0
-50 -50
-100 -100
0 2.5 5 0 2.5 5
Time (µs) Time (µs)
(a) (a)
300 300
250 250
200 200
150 150
Voltage (V)
Voltage (V)
100 100
50 50
0 0
-50 -50
-100 -100
0 2.5 5 0 2.5 5
3
Time (µs) Time (µs)
(b) (b)
300 300
250 250
200 200
150 150
Voltage (V)
Voltage (V)
100 100
50 50
0 0
-50 -50
-100 -100
0 2.5 5 0 2.5 5
Time (µs) Time (µs) PI-2885-061002
(c) PI-2884-061002 (c)
Figure 7. Normal DPA-Switch Drain Waveforms Showing Correct Figure 8. Illustration of Three Situations with Improper
Transformer Reset. a) VIN = 72 V, b) VIN = 48 V, Transformer Reset. a) VIN = 72 V, b) VIN = 36 V,
c) VIN = 36 V. c) VIN = 36 V.
3-108
Rev. C 07/04
the transformer increases in the positive direction during tON, original value of 47 pF, but the reset capacitor is increased to
and resets to zero during the interval tRZ. All the energy stored 47 nF. The converter is operating at 36 VDC. The drain voltage
in the magnetizing inductance is removed during tRZ to charge shows clearly that the transformer is not resetting completely.
the reset capacitor and the clamp capacitor to maximum voltage. The DPA-Switch turns on within the interval tRZ. The flux in
The flux increases in the negative direction during the interval the transformer has not returned to zero. A small change in
tRN as the reset capacitor and the clamp capacitor discharge operating conditions could cause the transformer to saturate
into the magnetizing inductance. The flux remains a constant on every cycle or to run so close to saturation that it could not
negative value during the interval tV0, where the voltage on the accommodate change in duty ratio from a load step.
transformer windings is zero. It is easy to see that the primary
voltage is zero during tV0 because the drain voltage is the same Output Capacitors
as the input of 72 V. The negative magnetizing current circulates
in the secondary winding during tV0. The ripple current in the output inductor generates a voltage ripple
on the output capacitors. Part of the ripple voltage comes from
Figure 7(b) shows the drain voltage on the same circuit when the integration of the current by the capacitance, and part comes
5 it operates at the nominal input of 48 VDC. The larger duty from the voltage that appears across the capacitorʼs equivalent
ratio is consistent with the lower input voltage. Note that the series resistance (ESR). The capacitor must be selected such that
intervals tRZ and tRN are the same as at 72 V input, but now tV0 the capacitance is high enough and the ESR is low enough to
is nearly zero. give acceptable voltage ripple with the chosen output inductor.
Usually most of the ripple voltage comes from the ESR. Ripple
Figure 7(c) shows the situation at input voltage of 36 VDC, with voltage that is dominated by ESR has a triangular waveform
a corresponding larger duty ratio. The transformer has reset to like the ripple current in the inductor. Ripple voltage that is
zero flux because the drain voltage has reached its peak during dominated by the capacitance has a waveform with segments
the interval tRZ. The drain voltage is in the region of negative that are parabolic instead of linear.
flux when the DPA-Switch turns on.
Output capacitors in DC-DC converters are typically solid
Peak drain voltage under normal operating conditions should be tantalum. They are a good choice because of their low ESR and
less than 150 V. This includes peaks in the drain voltage from the low impedance at the frequencies used in these converters. The
reset of both leakage inductance and magnetizing inductance. ESR is also an important element in the design of the feedback
loop. In this regard, a moderate amount of ESR is desirable.
Figure 8 shows three cases of improper transformer reset. The The section on Feedback Design elaborates on the values of
prototype example has been modified to create these illustrations. the components in the feedback circuit.
5 The RC network has been removed from the output rectifier to
obtain the waveform in Figure 8(a). The clamp capacitor CCP on It is important for designers to know that the value of ESR
the primary is 47 pF. The magnetizing energy resets into only may change significantly over the specified temperature range. 3
the clamp capacitor and other stray capacitance. Consequently, The output ripple and the stability of the control loop can be
at 72 V input the drain voltage goes higher than desired. The affected by the change in ESR. It is necessary to evaluate
figure shows the maximum drain voltage at 152 V, in contrast prototype hardware at the extremes of temperature to confirm
to 140 V in Figure 7(a) with a proper reset network. The Zener satisfactory performance.
clamp voltage of 150 V is specified at a current of 1 mA.
Although the Zener clamp just barely conducts at 152 V, there The voltage rating for the capacitors is typically 25% higher
is not sufficient margin in this design to tolerate a transformer than the maximum operating voltage for reliability. The derating
with lower primary inductance. factor is thus 80%. For example, a 5 V output would have a
capacitor that is rated for either 6.3 V or 10 V. The lower voltage
Figure 8(b) illustrates the situation of too much capacitance. The capacitor would be smaller, whereas the higher voltage capacitor
RC reset network has been restored with a proper capacitance would have a lower failure rate in the application.
of 2.2 nF, but CCP is increased to 470 pF, ten times the original
value. The waveform shows operation at 36 VDC input and Feedback Design
full load. The flux in the transformer has just barely reset to
5 zero, as the DPA-Switch turns on at the end of the tRZ interval. Stability is an important consideration for a switching power
A larger magnetizing inductance or a lower input voltage would supply. Three parameters that describe the characteristics of the
2
not allow the transformer to reset. control loop are crossover frequency, phase margin and gain
margin. The crossover frequency is the frequency where the
The final example of an improper transformer reset is magnitude of the loop gain passes through 0 dB. It is a measure
Figure 8(c). Primary clamp capacitor CCP is restored to its of the systemʼs bandwidth.
3-109
Rev. C 07/04
L2 OUTPUT
+
U2 R10 C10 C11
C16
DPA-Switch
R6
U1 R12
D
CONTROL
C
C14 R9
U3
S R4 TL431
C5
R11 OUTPUT
C6 RETURN
Input
Return
PI-2876-062204
Figure 9. Essential Components of the Feedback Circuit. The Schematic Does Not Show ESR of the Output Capacitors (Component
Designators are the Same as in the EP-21 Prototype).
The phase margin is specified at the crossover frequency. It mode control to allow operation at duty ratios greater than 50%
is the difference between the phase of the loop gain and 180 without the need for the stabilizing ramp (“slope compensation”)
degrees. A stringent specification will call for a phase margin required with current-mode control. The fundamental system
of at least 60 degrees under worst case conditions. In no case characteristics of the forward converter in continuous conduction
should the phase margin be less than 45 degrees. This means the mode with voltage mode control call for a compensation
3 phase would have to decrease by that amount for the system to circuit with multiple poles and zeros to achieve the desired
become unstable. Phase margin is also related to the dynamic loop response.
characteristics of the system. A low phase margin suggests an
oscillatory response to a load step or other disturbance. The crossover frequency for a control loop that uses
DPA-Switch in a forward converter with an optocoupler should
It is also important that the loop gain decrease in magnitude be limited to 10 kHz or less at maximum input voltage and
beyond the crossover frequency. This requirement is generally room temperature. The DPA-Switch has one internal pole at
specified as gain margin. Gain margin is the difference between approximately 30 kHz to filter switching noise. Other poles at
0 dB and the magnitude of the loop gain at the frequency where higher frequencies contribute additional phase shift at 30 kHz.
the phase is 180 degrees. An acceptable gain margin is greater The optocoupler has two poles at approximately 100 kHz. The
than 10 dB. This means the magnitude would have to increase by phase shift from these poles, combined with the phase shift
that amount for the system to become unstable. Loop gain should introduced by the LC filter at the output of the converter, is
be measured at worst case conditions (generally maximum difficult to compensate above 10 kHz.
input voltage with maximum load) and at the extremes of the
specified ambient temperature, since important component The objective of the feedback design is to reduce the magnitude
parameters (especially capacitor ESR) can change greatly with of the loop gain to zero dB at a frequency of 10 kHz or less with
temperature. a phase margin near 60 degrees. Although system requirements
and the DPA-Switch fix some quantities that determine loop
Stabilizing a high frequency forward DC-DC converter presents characteristics, the designer can manipulate many components
some challenges due to the inherently high bandwidth of this in the feedback circuit to optimize loop stability. Figure 8
topology. Many DC-DC converter designs use cycle-by-cycle shows the essential components of a feedback circuit that uses
current-mode control. The DPA-Switch uses classic voltage an ordinary TL431 regulator to achieve the high loop gain
3-110
Rev. C 07/04
PI-2878-032603
60 270
1-Gain
56 dB Loop Gain
50 240
Z1 Z2 Z3 Z4
40 210
0 Degrees Phase
30 180
1-Phase 180 Degrees Phase Margin
20 150
Phase Margin (degrees)

10 Gain Margin 120
20 dB
Gain (dB)
0 0 dB Gain 90
-10 60
Phase Margin 30
-20
60 Degrees
180 Degrees Phase 0

-30
0 Degrees Phase Margin
-40 P3 -30
P1 P2 P4 P5 P6
-50 -60
-60 -90
0.1 1 10 100 1k 10 k 100 k
Frequency (Hz)
Figure 10. Gain and Phase of a Typical Feedback Loop for DC-DC Forward Converter with DPA-Switch. Markers Show Locations of Major
Poles and Zeros.
required for tight DC voltage regulation. Not shown in the The output capacitor ESR contributes a zero that compensates for
circuit diagram is the ESR of the output capacitors. The ESR one of the poles from the filter. However, for low ESR tantalum
is also an important element in the frequency compensation of or organic electrolyte capacitors, this zero usually occurs too
high in frequency to substantially offset the effects of the filter
3
the feedback loop.
within the desired loop bandwidth. In the prototype example, the
Output LC Filter output filter capacitors are 100 µF, with a maximum specified
ESR of 100 milliohms. The ESR zero is thus at approximately
The filter formed by the output inductor and the output capacitors 16 kHz, well beyond the 4 kHz LC filter resonant frequency.
contributes two poles to the loop response at the filterʼs resonant Actual ESR is approximately 80 milliohms, placing the zero
frequency. Since the filter is a resonant circuit with relatively typically at 20 kHz. In situations where standard low ESR
low loss, the gain and phase change rather abruptly near the electrolytic capacitors can be used, the higher ESR may place
resonant frequency. Consequently, the poles and zeros for the ESR zero at a sufficiently low frequency to add significant
shaping the loop response should either avoid this region or additional phase margin.
compensate for the resonance.
DPA-Switch Compensation
Proper placement of the resonant frequency of the output
filter will avoid complications in the design of the feedback The network of C6 and R4 at the CONTROL pin of DPA-Switch
loop. The position of the resonant frequency should allow the provides compensation for the feedback loop in addition to
designer to shape the desired response with a limited number of other functions. The capacitance of C6 with R4 and its own
compensation components of reasonable size. The recommended ESR plus the impedance of the CONTROL pin impedance
resonant frequency for an output filter that uses low ESR provide a pole in the loop gain, followed by a zero from R4
tantalum capacitors in a forward converter with DPA-Switch and the ESR of C6.
and optocoupler feedback is between 4 kHz and 6 kHz. This
value is consistent with the inductor and capacitor values for Suggested values of C6 are between 47 µF and 100 µF. This
desirable ripple current and ripple voltage. range of values will generally be sufficient to provide desirable
3-111
Rev. C 07/04
adjustments to the loop gain and to allow the capacitor to perform Another zero, local to the TL431, is formed by C14 and R9
its other functions in the system. at about 720 Hz. The location of this zero is not critical for
normal operation in continuous conduction mode, and does not
The zero introduced by R4 and the ESR of C6 should be at appear in the loop gain of this example. It becomes important at
approximately 25% of the output filter resonant frequency. This very light loads where the converter operates in discontinuous
placement allows maximum gain reduction while minimizing the conduction mode. The loop gain characteristic for discontinuous
phase lag introduced by this network at the resonant frequency. conduction mode is fundamentally different from this example
In the prototype example, C6 is 68 µF with an ESR of about of continuous conduction mode. The most significant effect is
1.6 Ω. The impedance at the CONTROL pin of DPA-Switch that the loop gain will generally have a much lower crossover
is typically 15 Ω. These values put the pole at approximately frequency that depends on the load. The crossover frequency
130 Hz and the zero at approximately 900 Hz. High frequency could easily fall into the region where the TL431 contributes
bypass capacitor C5 is small enough to have a negligible effect significantly to the loop gain.
on the loop gain.
Loop Gain of Prototype Circuit
Optocoupler Compensation
Figure 10 shows the magnitude and phase of the loop gain of the
The current transfer ratio (CTR) of the optocoupler is a major prototype circuit for an input voltage of 72 V at a load current
contributor to the magnitude of the loop gain near the crossover of 5 A. The highest input voltage is typically the worst case in
frequency. Equally important is the resistor R6 in series with forward converters because that is the condition for highest gain,
the optocoupler LED. Selection for either of these elements yielding the highest bandwidth and lowest phase margin.
is not arbitrary, as the optocoupler provides power to the
DPA-Switch during normal operation. The upper curve in Figure 10 is the magnitude of the loop
gain in units of dB. The lower curve is the phase in units of
The combination of optocoupler and series resistor must degrees, with the scale shifted by 180 degrees to give the phase
deliver the maximum specified CONTROL pin current for the margin directly. The markers Z1 through Z4 and P1 through
DPA-Switch at minimum specified CTR. In most cases, an P6 show respectively the frequencies of the significant zeroes
optocoupler with a CTR between 100% and 200% will suffice. and poles.
The designer then selects R6 to provide the LED current required
at minimum CTR with a saturated TL431. The network of The integrator formed by C14, R9 and R10 reduces the gain
R12 and C16 in parallel with R6 creates a zero that boosts from its DC value such that the TL431 makes essentially no
the gain and phase to compensate one of the poles from the contribution to the gain at frequencies higher than Z1. The
output filter. The position of the zero is generally determined asymptotes of the DC value and the 20 dB per decade slope of
empirically to achieve the desired phase margin. It is typically the integrator create the pole at P1.
3 set at a frequency between one and three times the resonant
frequency of the output filter. Resistor R12 limits the boost in Gain is reduced by the pole at P2 that is formed by capacitor
gain at high frequencies. C6 with its ESR, resistor R4, and the internal impedance of
the CONTROL pin of the DPA-Switch. The phase receives
TL431 Compensation a boost from the zero formed by C6 and R4 with the ESR of
C6 at Z2. The resistor R4 augments the ESR of the capacitor.
The purpose of the TL431 is to provide high loop gain at Use a tantalum capacitor for C6 so that the total resistance
low frequencies. Its contribution is not necessary at higher can be adjusted by R4. The ESR of an aluminum capacitor
frequencies where the optocoupler provides adequate gain. will generally be too large to allow the desired shaping of the
Therefore, the feedback circuit has compensation around the frequency response. Capacitor C5 provides a low impedance
TL431 to maximize its contribution at very low frequencies source for pulses of current into the CONTROL pin. Its effect
and to remove its influence at higher frequencies. on the control loop is minor, appearing at P6, well beyond the
0 dB crossover frequency.
The connection of C14 and R9 between the cathode and the
reference terminal of the TL431 allows maximum loop gain at The zero at Z2 provides partial cancellation of the pair of poles P3,
DC for the best voltage regulation. In the prototype example, P4 that originate from the output inductor and output capacitors
capacitor C14 forms an integrator that reduces the contribution of the forward converter. The network of C16, R6 and R12 gives
of the TL431 by 20 dB per decade. Resistor R9 with R10 sets the additional cancellation with a zero at Z3. The ESR of the output
minimum gain from the TL431 and introduces a zero in the loop capacitors gives a final zero at Z4. The internal high frequency
gain. The zero in the prototype example is at about 16 Hz. filter of the DPA-Switch provides the pole at P5.
3-112
Rev. C 07/04
C7
1 nF R14
L1 1.5 kV 10 Ω
+ VIN 1 µH C10 C11 C12
2.5 A 100 µF 100 µF 1 µF
36-75 VDC L2 10 V 10 V 10 V 5 V, 6 A
C17
R1 3300 pF
R15
619 kΩ 10 Ω R16
1% D1
R17 10 kΩ D2 BAV
10 Ω Q1
Si4888 19WS
DY
RTN
T1 Q2 D4
Si4888 C4
BAV19WS 4.7 µF
DY U2
20 V
R7
C1, C2 & C3 10 kΩ R10
1 µF 10.0 kΩ
100 V 1%
DPA-Switch D3 C16
U1 U2 100 nF
D L
PC357N1T BAV19WS
DPA425R
CONTROL R6 R12
C 150 Ω 5.1 Ω
R9
220 Ω
S X F
R4 C13
10 µF C14
VR1 1.0 Ω 1 µF
R3 10 V
SMBJ C5 U3
150 18.2 kΩ 220 nF C6
1% 68 µF LM431AIM3 R11
10 V 10.0 kΩ
VIN 1%
PI-3472-040903
Figure 11. Example of DPA-Switch in a Single-Ended DC-DC Forward Converter with Synchronous Rectification.
The magnitude of the gain at frequencies greater than Z1 is related The two modes have different control characteristics. The
directly to the current transfer ratio (CTR) of the optocoupler. converter in discontinuous conduction mode will usually have
Therefore, the CTR must be controlled to maintain a stable and a slower response to transients and higher ripple voltage at the
well-behaved system. Designers should choose an optocoupler output than in continuous conduction mode. In extreme cases, a
that has a CTR in the range of 100% to 200% at the maximum converter that is well-behaved in continuous conduction mode
CONTROL pin current of 12 mA. The phototransistor of the may actually become unstable at light load or with no load
optocoupler must also have a breakdown voltage greater than
the maximum bias voltage.
unless correctly designed. Many commercial DC-DC converter
modules specify a large minimum load to prevent operation in
3
discontinuous conduction mode.
Figure 10 shows that this example has a desirable phase margin
of 60 degrees and a comfortable gain margin of 20 dB. Sufficient A converter that operates deeply in discontinuous conduction
margin is required in the design of the feedback loop to allow mode requires a very small duty ratio. Operation at very light
for tolerances in the CTR of the optocoupler, changes in ESR loads is not a problem for DPA-Switch because it automatically
of the output capacitor, and the change in gain with operating reduces the effective switching frequency by skipping cycles
voltage. The ESR can change significantly with temperature. to give duty ratios less than about 5%.
This should be a primary consideration in the selection of output
capacitors. The design must also allow for tolerance variations Operation at small duty ratios requires a larger capacitor to
in all other components. keep the bias voltage above its minimum required value of
8 V. In a trade-off with size, cost and efficiency, the best solution
to a requirement to operate with no load is to include a small
Operation at No-Load preload in parallel with the output capacitors. The amount of
Those who design or specify DC-DC converters should the load is determined empirically to supplement the natural
pay particular attention to requirements for minimum load. loading from the other small-signal circuits that get their power
The control characteristics are different for operation in the from the output.
continuous conduction mode (moderate to heavy loads) and
discontinuous conduction mode (light loads). The boundary Synchronous Rectification
between the two modes occurs at the load where K∆I = 2 (without
synchronous rectification). The use of synchronous rectification can yield a substantial
increase in efficiency over passive Schottky rectifiers on the
3-113
Rev. C 07/04
Efficiency Gain Over Diode

L2 Output Voltage
Rectification
5V +3%
R15
3.3 V +6%
Q1 D3 2.5 V +8%
Q2
PI-2989-062204 Table 3. Efficiency Gain vs. Output Voltage for Synchronous
(a) Rectification.
L2
C17
The forward rectifier MOSFET Q2 turns on when the
R15
DPA-Switch turns on to apply the DC input voltage across the
R16 Q1 D3 primary winding. The direction of current in Q2 is from source
D4 to drain. When the DPA-Switch turns off, the reset voltage on
Q2 PI-3475-062204
the transformer forces a negative gate-to-source voltage on Q2
(b) and a positive gate-to-source voltage on Q1. Schottky diode D3
conducts until the gate-to-source voltage on Q1 rises sufficiently
to exceed the threshold voltage.
Figure 12. Synchronous Rectification (a) Winding Driven DC
Coupled. (b) Winding Driven AC Coupled.
Suitable MOSFETs for this application have threshold voltages
typically between 4 V and 5 V. The permissible maximum gate-
output. For a 5 V output, an efficiency of 85% with Schottky to-source voltage is usually 15 V to 20 V. These restrictions
rectifiers would typically go to 90% or higher with synchronous limit the range of input voltage for converter operation.
rectifiers. Synchronous rectification gives the benefit of greater
efficiency at lower output voltages as shown in Table 3. The integrated line overvoltage feature of DPA-Switch simplifies
the design of winding driven synchronous rectifiers. In most
DPA-Switch has features that can simplify the design of cases it eliminates the need for Zener diodes to protect the gates
synchronous rectifier circuits that are in common use. Circuits of the MOSFETs from excessive voltage. Excess voltage will
for synchronous rectification with DPA-Switch fall into three not appear on the secondary of the transformer because the
categories of increasing complexity. DPA-Switch will not operate when the input voltage is too
high.
3 a) Winding Driven DC Coupled
DC coupling of the gates in this configuration permits a mode
b) Winding Driven AC Coupled
c) Actively Driven of operation that may not be desirable in some applications.
During shutdown, the voltage across the output inductor will go
The first two are shown in Figures 11 and 12. MOSFETs Q1 to zero after its current decays to zero. The remaining output
and Q2 conduct at appropriate times to reduce the voltage drops voltage will then appear across Q1 and D3.
associated with the output rectifiers of a forward converter. Q2
performs the function of the forward rectifier. Q1 operates as the If the output voltage is high enough (above the gate threshold
catch rectifier with a parallel Schottky diode. The voltage drop of Q2) it will turn on Q2, allowing reverse current to flow
of each synchronous rectifier is dominated by the on-resistance through L2 and the transformer secondary. The voltage on the
of the MOSFETs multiplied by the RMS load current, rather secondary winding will saturate the transformer, abruptly turning
than by the average current times the minimum voltage of a off Q2 and generating a voltage spike on the gate of Q1. This
Schottky barrier. voltage spike may exceed the rated gate voltage for Q1. This
behavior can occur in any design using this form of synchronous
Winding Driven DC Coupled Synchronous Rectifier rectification with an undervoltage lockout. It is not specific to
DPA-Switch. A solution to this issue is offered below.
The simplest way to drive synchronous rectifiers with
DPA-Switch is shown in Figure 12 (a). The gate-to-source Winding Driven AC Coupled Synchronous Rectifier
voltage that turns on the MOSFETs is essentially the voltage
at the secondary winding of the transformer. The channel of the The AC coupled circuit of Figure 12 (b) eliminates the high
MOSFET will conduct as long as the gate-to-source voltage voltage spike by limiting the on-time of Q2 such that significant
exceeds the threshold voltage. reverse current cannot flow through L2 and the secondary
3-114
Rev. C 07/04
Complexity
Synchronous Rectifier Type Efficiency Comment
and Cost
Winding Driven DC Coupled ⇑ ⇓ Check Gate Voltage at Power Down
Winding Driven AC Coupled ⇑ ⇔ Gate Voltage Controlled at Power Down
Active Drive ⇑ ⇑⇑⇑ High Complexity
Table 4. Comparison of Synchronous Rectification Techniques.
winding. Capacitor C17 should be chosen to capacitively divide Primary Side Connections
the winding voltage between C17 and the CGS of MOSFET
Q2, to provide a voltage on CGS that exceeds the Q2 threshold The tab of DPA-Switch is the intended return connection for the
voltage. The time constant of C17 and R16 should be about high switching currents. Therefore, the tab should be connected
10 µs for 300 kHz operation. R15 is typically about 10 Ω. by wide, low impedance traces to the input capacitor. The
SOURCE pin should not be used to return the power currents;
Figure 11 shows the DPA-Switch in a single-ended DC-DC incorrect operation of the device may result. The SOURCE pin
forward converter that uses winding driven AC coupled is intended as a signal ground only. The device tab (SOURCE)
synchronous rectification. In this example, the gate of Q1 is the correct connection for power currents.
has enough capacitance to eliminate the need for the discrete
capacitor CS in the transformer reset circuit. Although this The bypass capacitor on the CONTROL pin should be located
is often the case with synchronous rectifiers that are winding as close as possible to the SOURCE and CONTROL pins. The
driven, designers should follow the guidance in the section on circuit trace of its connection to SOURCE should not contain
Verification of Transformer Reset to confirm that the transformer any switching current from the primary or bias voltages.
resets properly. All SOURCE pin referenced components connected to the
LINE-SENSE (L) or EXTERNAL CURRENT LIMIT (X)
Actively Driven Synchronous Rectifiers pins should also be located closely between their respective
pins and SOURCE. Once again, the SOURCE connection
The third category of synchronous rectifier circuits uses trace of these components should not conduct any of the main
independent active components that may include discrete devices MOSFET switching currents. It is critical that tab (SOURCE)
and integrated circuits to lock onto the switching frequency of power switching currents are returned to the negative terminal
the power supply and to drive the MOSFETs. This solution of the input capacitor through a separate trace that is not shared
relaxes the restriction on the range of input voltage because the by the components connected to the SOURCE, CONTROL,
driver can regulate the gate voltage to be independent of the L or X pins. 3
voltage on the secondary winding. Circuits for actively driven
synchronous rectifiers are much more complex than the other Any traces to the L or X pins should be kept as short as possible
solutions, and are beyond the scope of this application note. and away from the drain trace to prevent noise coupling. Line-
Table 4 gives a comparison of the techniques for synchronous sense resistor (R1 in Figure 11) should be located close to the L
rectification. pin to minimize the trace length on the L pin side. In addition
to the CONTROL pin capacitor (C5 in Figure 11), a 220 nF
In general, DPA-Switch with synchronous rectifiers should high frequency bypass capacitor in parallel is recommended
operate at the lower switching frequency of 300 kHz. The as close as possible between SOURCE and CONTROL pins
synchronous rectifier catch MOSFETs typically have gate- for better noise immunity. The feedback optocoupler output
source capacitance values such that the transformer would have should also be located close to the CONTROL and SOURCE
insufficient time to reset at 400 kHz. Connect the F pin to the pins of DPA-Switch.
CONTROL pin to select the lower switching frequency.
Heat Sinking
Layout Considerations
To maximize heat sinking of the DPA-Switch and the other
Figure 13 shows an example of a proper circuit board layout for power components, special thermally conductive PC board
a forward converter with DPA-Switch. Since the DPA-Switch material (aluminum clad PC board) is recommended. This
can operate with large drain current, designers should follow has an aluminum sheet bonded to the PC board during the
these guidelines carefully. manufacturing process to provide heat sinking directly or to
allow the attachment of an external heat sink. If normal PC
3-115
Rev. C 07/04
Solder Side
Component Side
TOP VIEW Output

Diode
V
Transformer
+
D Inductor
(Coupled)
V
DPA-Switch
S
X
L
V
C +
Opto- DC
coupler Out
- -
V

PI-2883-060602
Figure 13. Layout Considerations for DPA-Switch Using R Package.
board material is used (such as FR4), providing copper areas on 1. Maximum drain voltage – Verify that peak drain-to-source
3 both sides of the board and using thicker copper will improve voltage does not exceed minimum BVDSS at highest input
heat sinking. voltage and maximum overload output power. It is normal,
however, to have additional margin of approximately 25 V
If an aluminum clad board is used, then shielding of switching below BVDSS to allow for other power supply component
nodes is recommended. This consists of an area of copper placed unit-to-unit variations. Maximum overload output power
directly underneath switching nodes such as the drain node occurs when the output is loaded to a level just before the
and output diode to provide an electrostatic shield to prevent power supply goes into auto-restart (loss of regulation).
coupling to the aluminum substrate. These areas are connected
to input negative in the case of the primary and output return 2. Transformer reset margin – Drain voltage should also be
for secondary. This reduces the amount of capacitive coupling checked at highest input voltage with a severe load step
into the insulated aluminum substrate that can then appear on (50% to 100%) to verify adequate transformer reset margin.
the output as ripple and high frequency noise. This test slews the duty cycle at high input voltage, placing
the most demand on the transformer reset circuit.
Quick Design Checklist
As with any power supply design, all DPA-Switch designs maximum input voltage and maximum output load, verify
should be verified on the bench to make sure that component drain current waveforms at start-up for any signs of
specifications limits are not exceeded under worst case transformer or output inductor saturation and excessive
conditions. The following minimum set of tests for DPA-Switch leading edge current spikes. DPA-Switch has a leading edge
forward converters is strongly recommended: blanking time of 100 ns to prevent premature termination
of the cycle. Verify that the leading edge current spike does
not extend beyond the blanking period.
3-116
Rev. C 07/04
4. Thermal check – At maximum output power, minimum References

input voltage and maximum ambient temperature, verify
that temperature specifications are not exceeded for the [1] Ferroxcube (formerly Philips) core supplier –
transformer, output diodes, output inductors and output www.ferroxcube.com.
capacitors. The DPA-Switch is fully protected against
overtemperature conditions by its thermal shutdown [2] TDK cores supplier – www.component.tdk.com/ components/
feature. It is recommended that sufficient heat sinking is ferrite.asp.
provided to keep the tab temperature at or below 115 °C
under worst case continuous load conditions (at low input [3] AVX (Thompson) core supplier - www.avxcorp.com.
voltage, maximum ambient and full load). This provides
adequate margin to minimum thermal shutdown temperature [4] M. Domb, R. Redl, and N.O. Sokal. “Nondissipative turn-off
(130 °C) to account for part-to-part RDS(ON) variation. When snubber in a forward converter: analysis, design procedure, and
monitoring tab temperature, note that the junction-to-case experimental verification,” Official Proceedings of the Tenth
thermal resistance should be accounted for when estimating International PCI ʻ85 Conference, pp. 54-68.
die temperature.
[5] T. Ninomiya, T. Tanaka, and K. Harada, “Analysis and
Design Tools optimization of a nondissipative LC turn-off snubber,” IEEE
Transactions on Power Electronics, Vol. 3, No. 2, April 1988,
Up-to-date information on design tools is available at the Power pp. 147-156.
Integrations website: www.powerint.com.
Revision Notes Date

A 1) – 6/02
B 1) Added new information: Bias circuits and Synchronous rectification. 4/03
C 1) Minor error corrections in the text. 7/04
3-117
Rev. C 07/04
®
TOPSwitch-GX
Flyback Design Methodology
Designing an off-line power supply involves many aspects of and a step-by-step design procedure. The flow chart shows the
electrical engineering: analog and digital circuits, bipolar and design sequence at a conceptual level for TOPSwitch-GX
MOS power device characteristics, magnetics, thermal flyback power supply design. The step-by-step procedure gives
considerations, safety requirements, control loop stability, etc. details within each step of the design flow chart, including
This represents an enormous challenge involving complex empirical design guidelines and look-up tables. All key equations
trade-offs with a large number of design variables. As a result, and guidelines are provided wherever possible to assist the
new off-line power supply development has always been tedious readers in better understanding and/or further optimization.
and time consuming even for the experts in the field. This
application note introduces a simple, yet highly efficient Basic Circuit Configuration
methodology for the design of TOPSwitch-GX family based
off-line power supplies. For TOPSwitch-GX Flyback designs, Because of the high level integration of TOPSwitch-GX, many
Power Integrations recommends the use of PI Expert which power supply design issues are resolved in the chip. Far fewer
implements this design methodology and also includes a issues are left to be addressed externally, resulting in one
knowledge base and optimization feature for making key design common circuit configuration for all applications. Different
choices, further reducing design time. output power levels may require different values for some
circuit components, but the circuit configuration stays
Introduction unchanged. TOPSwitch-GX is a feature-rich product family.
Advanced features like under-voltage, overvoltage, external
The design of a switching power supply, by nature, is an ILIMIT, line feed forward, and remote ON/OFF are easily
iterative process with many variables requiring adjustment to implemented with a minimal number of external components,
optimize the design. The design method described in this but do involve additional design considerations. Please refer to
document consists of two major sections: A design flow chart the TOPSwitch-GX data sheet for details. Other application
3 Blocking Diode Clamp Zener

+VD-
Output Capacitor
Output Post Filter L, C
+
VO
Line Sense -
Resistor +
+ +VDB- VB
VAC -
Bias Capacitor
CIN
D L TOPSwitch-GX
CONTROL
C
S X F
Feedback Circuit
fS = 132 kHz if connected as shown. External ILIMIT Resistor CONTROL Pin Capacitor
For fS = 66 kHz, connect "F" Pin to "C" Pin (optional) and Series Resistor
(fS option not available with P or G package)
PI-3038-091102
Figure 1. Typical TOPSwitch-GX Flyback Power Supply.
3-118
Rev. C 07/04
1. System Requirements
VACMIN, VACMAX, fL, VO, PO, η, Z
Step 1-2
Determine System Level Requirements
and Choose Feedback Circuit
2. Choose Feedback Circuit & VB
3. Determine CIN, VMIN, VMAX
4. Determine VOR, VCLO
5. Set KP
6. Determine DMAX
Step 3-11
Choose The Smallest TOPSwitch-GX
7. Calculate Primary Peak Current IP For The Required Power
8. Calculate Primary RMS Current IRMS
9. Choose TOPSwitch-GX & fS Using AN-29
10. Set ILIMIT Reduction Factor KI

From Step 23
Calculate ILIMIT (min) & ILIMIT (max)
N
11. IP ≤ ILIMIT (min)
To Step 12
3
PI-3039-080502
Figure 2A. TOPSwitch-GX Design Flow Chart. Step 1 to 11.
specific issues such as constant current, constant power outputs, Design Flow
etc. are beyond the scope of this application note. However,
such requirements may be satisfied by adding additional circuitry Figures 2A, 2B and 2C present a design flow chart showing the
to the basic converter configuration. The only part of the circuit complete design procedure in 37 steps. With the basic circuit
configuration that may change from application to application configuration shown in Figure 1 as its foundation, the logic
is the feedback circuitry. Depending on the power supply output behind this design approach can be summarized as follows:
specifications, one of the four feedback circuits, shown in
Figures 3, 4, 5 and 6, will be chosen for the application. 1. Determine system requirements and decide on feedback
circuit accordingly.
The basic circuit configuration used in TOPSwitch-GX flyback 2. Choose the smallest TOPSwitch-GX capable of the
power supplies is shown in Figure 1, which also serves as the required output power.
reference circuit for component identifications used in the 3. Design the smallest transformer for the TOPSwitch-GX
description throughout this application note. chosen.
4. Select all other components in Figure 1 to complete the
design.
3-119
Rev. C 07/04
From Step 11
12. Determine LP
13. Choose Core & Bobbin

Y Determine Ae, Le, AL, BW
N 14. Set NS, L

22. NS, L Iterated
15. Calculate NP, NB
16. Calculate OD, DIA, AWG
17. Calculate BM
N
18. BM ≤ 3000
19. Calculate Lg, CMA

Step 12-28
Design the Smallest Transformer
to work with the TOPSwitch-GX Chosen
N
20. Lg ≥ 0.10 mm
N 21. 200 ≤ CMA ≤ 500
3 Y
N
To Step 10 23. BP ≤ 4200
24. Calculate ISP
25. Calculate ISRMS
26. Calculate ODS, DIAS, AWGS
27. Calculate IRIPPLE
To StepPIV
28. Calculate 28 , PIV
S B
To Step 29
PI-3040-091802
Figure 2B. TOPSwitch-GX Design Flow Chart. Step 12 to 28.
3-120
Rev. C 07/04
From Step 28
29. Select Clamp Zener & Blocking Diode
30. Select Output Rectifier
31. Select Output Capacitor
32. Select Output Post Filter L, C
33. Select Bias Rectifier
34. Select Bias Capacitor

Step 29-37
Select Other Components
35. Select CONTROL Pin Capacitor
& Series Resistor
36. Select Feedback Circuit Compenents

According to Reference Feedback Circuits
in Figures 3, 4, 5 and 6
37. Select Bridge Rectifier
Design
Complete
3
PI-2584-091402
Figure 2C. TOPSwitch-GX Design Flow Chart. Step 29 to 37.
The overriding objective of this procedure is “design for cost strike a compromise between cost and specific design
effectiveness.” Using smaller components usually leads to a requirements in order to achieve the optimum cost effectiveness
less expensive power supply. However, for applications with for the end product.
stringent size or weight limitations, the designer may need to
3-121
Rev. C 07/04
Step-by-Step Design Procedure • Power supply efficiency, η: 0.8 if no better reference data
available. (Refer to AN-29)
This design procedure uses the PI Expert design software (available • Loss allocation factor, Z: If Z = 1, all losses are on the
from Power Integrations), which contains all the important secondary side. If Z = 0, all losses are on the primary side.
equations required for a TOPSwitch-GX flyback power supply Set Z = 0.5 if no better reference data is available.
design, and automates most calculations. Designers are, therefore,
relieved from the tedious calculations involved in the complicated Step 2 – Choose feedback circuit and bias voltage VB based
and highly iterative design process. Look-up tables and empirical on output requirements
design guidelines are provided in this procedure where appropriate
to facilitate the design task. Feedback VB Circuit Load* Line Total
Circuit (V) Tolerance Reg. Reg. Reg.
Step 1 – Determine system requirements:
VACMAX, VACMIN, fL, VO, PO, η, Z Pri./Basic 5.8 ±10% ±5% ±1.5% ±16.5%
Pri./Enhan. 27.8 ±5% ±2.5% ±1.5% ±9%
• Minimum AC input voltage, VACMIN: in volts.
• Maximum AC input voltage, VACMAX: in volts. Opto/Zener 12 ±5% ±1% ±0.5% ±6.5%
• Recommended AC input ranges:
Opto/TL431 12 ±1% ±0.2% ±0.2% ±1.4%
Input (VAC) VACMIN (VAC) VACMAX (VAC) Table 2. Output Requirements.
*Over 10% to 100% Load Range.
Universal 85 265
• Use primary feedback for lowest cost (for low power
230 or 115 with doubler 195 265 applications only).
• Use Opto/Zener for low cost, good output accuracy.
Table 1. Recommended AC Input Range.
• Use Opto/TL431 for best output accuracy.
• Line frequency, fL: 50 Hz or 60 Hz. • Set bias voltage VB according to Table 2.
• Output voltage, VO: in Volts. • Choose optocoupler from Table 3.
• Output power: PO: in Watts.
+ +
3 VAC VO
-
CIN
Feedback Circuit
TOPSwitch-GX 15 Ω
D L
CONTROL
C
S X F CIRCUIT PERFORMANCE
Circuit Tolerance ±10%
Load Regulation ±5%
Line Regulation ±1.5%
PI-3331-112202
Figure 3. Primary/Basic Feedback Circuit.
3-122
Rev. C 07/04
+ +
VO
VAC
-
CIRCUIT PERFORMANCE
CIN
Circuit Tolerance ±5%
Load Regulation ±2.5%
15 Ω Line Regulation ±1.5%
TOPSwitch-GX
D L 1N5251D
22 V
CONTROL 1%
C
Feedback Circuit
S X F
100 nF
50 V
PI-3330-091102
Figure 4. Primary/Enhanced Feedback Circuit.
+ +
VAC VO
-
CIN 47 Ω∗
CIRCUIT PERFORMANCE
470 Ω∗∗ Circuit Tolerance ±5%
Load Regulation ±1%
TOPSwitch-GX Line Regulation ±0.5%
D L LTV817A
CONTROL
C
3
Feedback Circuit
S X F
Zener, 2%
∗47 Ω is suitable for V up to 7.5V. For V > 7.5V, a higher value may be required for optimum transient response.
O O
∗∗470 Ω is good for Zeners with I = 5 mA. Lower values are needed for Zeners with higher I . (E.g. 150 Ω for I = 20 mA).
ZT ZT ZT
PI-3328-112202
Figure 5. Opto/Zener Feedback Circuit.
3-123
Rev. C 07/04
+ +
VAC VO
-
CIN 470 Ω (VO = 12 V) CIRCUIT PERFORMANCE

100 Ω (VO = 5 V) Circuit Tolerance ±1%
Load Regulation ±0.2%
UTV817A Line Regulation ±0.2%
TOPSwitch-GX
D L 1 kΩ
CONTROL
C VO - 2.5
100 nF R= X 10 kΩ
3.3 kΩ 2.5
S X F
TL431
10 kΩ
Feedback Circuit
PI-3329-112202
Figure 6. Opto/TL431 Feedback Circuit.
P/N CTR(%) BVCEO Manufacturer Step 3 – Determine minimum and maximum DC input
voltages VMIN, VMAX and input storage capacitance CIN
4 Pin DIP
based on AC input voltage and PO (Figure 7)
PC123Y6 80-160 70 V Sharp
PC817X1 80-160 70 V Sharp
• Choose input storage capacitor, CIN per Table 4.
SFH615A-2 63-125 70 V Vishay, Isocom
Input (VAC) CIN (µF/Watt of PO) VMIN (V)
ISP817A 80-160 35 V Vishay, Isocom
Universal 2~3 ≥ 90
LTV817A 80-160 35 V Liteon
LTV816A 80-160 80 V Liteon
3 LTV123A 80-160 70 V Liteon
230 or 115 with doubler 1 ≥ 240
K1010A 60-160 60 V Cosmo
Table 4. Input Storage Capacitor.
6 Pin DIP
LTV702FB 63-125 70 V Liteon
• Set bridge rectifier conduction time, tC = 3 ms.
LTV703FB 63-125 70 V Liteon
• Derive minimum DC input voltage VMIN
LTV713FA 80-160 35 V Liteon
K2010 60-160 60 V Cosmo
PC702V2NSZX 63-125 70 V Sharp ⎛ 1 ⎞
PC703V2NSZX 63-125 70 V Sharp 2 × PO × ⎜ − tC ⎟
2 ⎝ 2 × fL ⎠
PC713V1NSZX 80-160 35 V Sharp VMIN = (2 × VACMIN ) −
PC714V1NSZX 80-160 35 V Sharp η × CIN
MOC8102 73-117 30 V Vishay, Isocom
where units are volts, watts, Hz, seconds and farads
• Calculate maximum DC input voltage VMAX:
CNY17F-2 63-125 70 V Vishay, Isocom,
Liteon
VMAX = 2 × VACMAX
Table 3. Optocoupler
3-124
Rev. C 07/04
Step 4 – Determine reflected output voltage VOR and clamp TOPSwitch-GX when and only when current limit is set
Zener voltage VCLO (Figure 8) externally with current limit reduction as a function of line
voltage. Compared to Zener clamps, designs using RCD
• Set reflected output voltage, VOR = 100 V for multiple clamps usually have lower efficiency at light load. In
output, 120 V for single output. These values optimize addition, great care must be taken in RCD clamp design.
cross-regulation and efficiency. To obtain the maximum Because of its inherent variation in clamp voltage across
output power from a given TOPSwitch-GX device, set load range, if not designed properly, an RCD clamp may
VOR = 135 V. fail to protect TOPSwitch-GX, especially under startup or
• RCD (Resistor/Capacitor/Diode) clamp may be used with output overload conditions.
VACMIN × 2
V+
VMIN
tC
PO = Output Power
fL = Line Frequency
(50 or 60 Hz)
tC = Conduction Angle
Use 3 ms if unknown
η = Efficiency
PI-2585-012500
Figure 7. Input Voltage Waveform.
BVDSS 700 V
Margin = 53 V (95 V)
Blocking Diode Forward Recovery = 20 V
647 V (605 V) 3
627 V (585 V)
555 V (525 V)
VCLM
495 V (475 V)
VCLO
VOR = 120 V (100 V)
VMAX 375 V
VCLO = 1.5 x VOR = 180 V (150 V)
VCLM = 1.4 x VCLO = 252 V (210 V)
0V 0V
Universal/230 VAC Input

Use VOR = 120 V (100 V) and 180 V (150 V) Zener Clamp
For Single (Multiple) Output
PI-3336-091402
Figure 8. Reflected Voltage VOR and Clamp Zener Voltage VCLO.
3-125
Rev. C 07/04
Step 5 – Set current waveform parameter KP for desired

IR mode of operation and current waveform: KP ≡ KRP for
KP ≡ KRP = KP ≤ 1.0 and KP ≡ KDP for KP ≥ 1.0 (Figures 9 and 10)
IP
• For KP ≤ 1.0, KP ≡ KRP, continuous mode (see Figure 9)

IR
Primary IP IR
K P ≡ K RP = where IR is primary ripple current and IP
IP
(a) Continuous, KP < 1 is primary peak current.
• For KP ≥ 1.0, KP ≡ KDP, discontinuous mode (see Figure 10)
V OR × (1 − D MAX )
IR IP K P ≡ K DP =
Primary (V MIN −VDS ) × D MAX
• For continuous mode design, set
(b) Borderline Continuous/Discontinuous, KP = 1 KP = 0.4 for universal input
0.6 for 230 VAC or 115 VAC with doubler.
PI-2587-011400
• For discontinuous mode design, set KP = 1.0.
Figure 9. Continuous Mode Current Waveform, KP ≤1. • KP must be kept within the range specified in Table 5.
KP ≡ KDP = (1-D) x T
t
T = 1/fS
Primary
DxT (1-D) x T
3
Secondary
(a) Discontinuous, KP > 1
T = 1/fS
Primary
DxT (1-D) x T = t
Secondary
(b) Boarderline Discontinuous/Continuous, KP = 1

PI-2578-011800
Figure 10. Discontinuous Mode Current Waveform, KP ≥1.
3-126
Rev. C 07/04
Step 9 – Choose TOPSwitch-GX based on AC input

KP
voltage, VO, PO and η using AN-29 selection curves
Input (VAC)
Continuous Discontinuous
Mode Mode • Choose the smallest TOPSwitch-GX using TOPSwitch-GX
Universal 0.4~1.0 ≥1.0 Selection Curves in AN-29.
• Identify appropriate selection curves according to AC
230 0.6~1.0 ≥1.0 input voltage and output voltage, VO.
• Continuous mode: Use selection curves as is.
Table 5. KP Range. • Discontinuous mode: Use selection curves with the output
power derated by 33%. This effectively makes a 10 W
Step 6 – Determine DMAX based on VMIN and VOR discontinuous design equivalent to a 15 W continuous
design in TOPSwitch-GX selection.
• Continuous mode • Switching Frequency fS: For DIP and SMP packages, set
fS = 132 kHz. For TO-220 package, choose between
V OR 66 kHz and 132 kHz.
DMAX =
(VMIN − VDS ) + V OR
Step 10 – Set ILIMIT reduction factor KI for External ILIMIT
• Discontinuous mode external I LIMIT where 0.3 ≤ K ≤ 1.0
• KI = I
V OR default I LIMIT
DMAX = • KI is set by the value of the resistor connected between M
K P × (VMIN − VDS ) + V OR
pin and SOURCE pin (Refer to TOPSwitch-GX data sheet).
• Set TOPSwitch-GX Drain to Source voltage, VDS = 10 V. • For applications demanding very high efficiency, a
TOPSwitch-GX bigger than necessary may be used by
Step 7 – Calculate primary peak current IP lowering ILIMIT externally to take advantage of the lower
RDS(ON).
• Continuous mode (KP ≤ 1.0) • If no special requirement, set KI = 1.0.
• Calculate ILIMIT(min) and ILIMIT(max)
I AVG
IP = I LIMIT (min) = default ⋅I LIMIT (min) × K I
⎛1 − K P ⎞ × D
MAX
⎝ 2 ⎠ I LIMIT (max) = default ⋅I LIMIT (max) × K I
• Discontinuous mode (KP ≥ 1.0)
Step 11 – Validate TOPSwitch-GX selection by checking 3
2 × I AVG IP against ILIMIT(min)
IP =
D MAX
• For KI = 1.0, check IP ≤ 0.96 x ILIMIT(min).
PO • For KI < 1.0, check IP ≤ 0.94 x ILIMIT(min).
• Input average current I AVG =
η ×V MIN • Choose larger TOPSwitch-GX if necessary.
Step 8 – Calculate primary RMS current IRMS Step 12 – Calculate primary inductance LP
• Continuous mode • Continuous mode

6
⎛ K P2 ⎞ 10 × PO Z × (1 − η) + η
LP = ×
I RMS = IP × DMAX ×⎜ − K P +1⎟ K η
IP × K P × ⎛1 − P ⎞ × fS (min)
2
⎝ 3 ⎠ ⎝ 2 ⎠
• Discontinuous mode where units are µH, watts, amps and Hz
2 • Discontinuous mode.
I
I RMS = DMAX × P 6
10 × PO Z × (1 − η) + η
3 LP = ×
2 1 η
IP × × fS (min)
2
where units are µH, watts, amps and Hz
3-127
Rev. C 07/04
• Z is loss allocation factor and η is efficiency from Step 1. Step 14 – Set value for number of primary layers L and
number of secondary turns NS (may need iteration)
Step 13 – Choose core and bobbin based on fS and PO using
Table 6 and determine Ae, Le, AL and BW from core and • Starting with L = 2 (Keep 1.0 ≤ L ≤ 2.0 throughout
bobbin catalog iteration).
• Starting with NS = 0.6 turn/volt.
• Core effective cross-sectional area, Ae: in cm2. • Both L and NS may need iteration.
• Core effective path length, Le: in cm.
• Core ungapped effective inductance, AL: in nH/turn2. Step 15 – Calculate number of primary turns NP and
• Bobbin width, BW: in mm. number of bias turns NB
• Choose core and bobbin based on fS, PO and construction
type. • Diode forward voltages: 0.7 V for ultra-fast P/N diode and
0.5 V for Schottky diode.
66 kHz 132 kHz • Set output rectifier forward voltage, VD.
Output • Set bias rectifier forward voltage, VDB.
Triple Triple • Calculate number of primary turns.
Power
Insulated Margin Insulated Margin
Wire Wound Wire Wound
V OR
EF12.6 EI22 EF12.6 EI22 N P = NS ×
EE13 EE19 EE13 EE19 VO + VD
EF16 EI22/19/6 EF16 E122/19/6
• Calculate number of bias turns NB.
0-10 W EE16 EEL16 EE16 EEL16
EE19 EF20
EI22 EI25 VB + VDB
EI22/19/6 EEL19
N B = NS ×
VO + VD
EF20 EI28 EE19 EF20
10 W- EEL22 EI22 EI25 Step 16 – Determine primary winding wire parameters OD,
20 W EF25 EI22/19/6 EEL19 DIA, AWG
EF20
20 W- EF25 EI30 E128 • Primary wire outside diameter in mm.
EPC30
30 W EEL25
EI28 E30/15/7 EF25 EEL22
L × ( BW − 2 × M )
OD =
EI30 EER28 EF25 NP
E30/15/7 ETD29 EI30
3 30 W- EER28 EI35 EPC30 where L is number of primary layers,
50 W EI33/29/ BW is bobbin width in mm,
13-Z M is safety margin in mm.
EER28L
ETD29 EF32 EI28 EEL25 • Determine primary wire bare conductor diameter DIA and
50 W-
EI35 ETD34 E30/15/7
70 W primary wire gauge AWG.
EF32 EER28
ETD34 EI40 EI30 ETD29
E36/18/11 E36/18/11 E30/15/7 EI35 Step 17 to Step 22 – Check BM, CMA and Lg. Iterate if
70 W- EI40 EER35 EER28 EI33/29/ necessary by changing L, NS or core/bobbin until within
100 W ETD29 13-Z specified range
EER28L
EF32 • Set safety margin, M. Use 3 mm (118 mils) for margin
ETD39 ETD39 EI35 ETD34 wound and zero for triple insulated secondary.
100 W- EER40 EER40 EF32 EI40 • Maximum flux density: 3000 ≥ BM ≥ 2000, in gauss or
150 W E42/21/15 ETD34 E36/18/11
0.3 ≥ BM ≥ 0.2, in tesla.
EER35
E42/21/15 E42/21/20 E36/18/11 ETD39
E42/21/20 E55/28/21 EI40 EER40 100 × IP × L P
BM =
>150W
E55/28/21 ETD39 E42/21/15 N P × Ae
EER40 E42/21/20
E42/21/15 E55/28/21 where units are gauss, amps, µH and cm2
E42/21/20
E55/28/21
Table 6. Transformer Core.
3-128
Rev. C 07/04
• Gap length in mm: Lg ≥ 0.1 Step 26 – Determine secondary winding wire parameters
ODS, DIAS, AWGS
2
⎛ NP 1 ⎞
L g = 40 × π × Ae × ⎜ − ⎟ • Secondary wire outside diameter in mm
⎝ 1000 × L P A L ⎠
where Lg in mm, Ae in cm2, AL in nH/turn2 and BW − (2 × M )
ODS =
LP in µH NS
• Secondary wire bare conductor diameter in mm
• Primary winding current capacity in circular mils per amp:
500 ≥ CMA ≥ 200 4 × CMAS × I SRMS 25.4
π 2
DIAS = ×
1.27 × DIA × 2 1.27 × π 1000
4 ⎛ 1000 ⎞
CMA = × where CMAS is secondary winding current capacity
I RMS ⎝ 25.4 ⎠
in circular mils per amp. Minimum wire diameter is
where DIA is the bare conductor diameter in mm calculated by using a CMAS of 200.
• Iterate by changing L, NS, core/bobbin according to Table 7. • Determine secondary winding wire gauge AWGS based on
DIAS. If the bare conductor diameter of the wire is larger
BM Lg CMA than that of the 27 AWG for 132 kHz or 25 AWG for
66 kHz, a parallel winding using multiple strands of thinner
L ↑ - - ↑ wire should be used to minimize skin effect.
↑ ↑
NS ↑ ↑ Step 27 – Determine output capacitor ripple current IRIPPLE
core ↑
size ↑ ↑ ↑ • Output capacitor ripple current
2 2
Table 7. Transformer Parameter Interactions. I RIPPLE = ISRMS − IO
Step 23 – Check BP ≤ 4200 . If necessary, reduce current where IO is the output DC current
limit by lowering ILIMIT reduction factor KI
Step 28 – Determine maximum peak inverse voltages PIVS,
I LIMIT (max) PIVB for secondary and bias windings
• BP = × BM 3
IP • Secondary winding maximum peak inverse voltage.
• Check BP ≤ 4200 gauss (0.42 tesla) to avoid transformer
saturation at startup and output over load.
NS
PIVS = VO + (VMAX × )
• Decrease KI, if necessary, until BP ≤ 4200. NP
• Bias winding maximum peak inverse voltage.
Step 24 – Calculate secondary peak current ISP
NB
N PIVB = VB + (VMAX × )
• I SP = I P × P NP
NS
Step 29 – Select clamp Zener and blocking diode per Table 8
Step 25 – Calculate secondary RMS current ISRMS for primary clamping based on VOR and the type of output
• Continuous mode Blocking Clamp

PS Output VOR
Diode Zener
⎛ K P2 ⎞ BYV26C
ISRMS = ISP × (1 − DMAX ) × ⎜ − K P + 1⎟ Multiple Output 100 V MUR160 P6KE150
⎝ 3 ⎠ UF4005
• Discontinuous mode BYV26C
Single Output 120 V MUR160 P6KE180
1 − D MAX UF4005
ISRMS = ISP ×
3 ×K P Table 8. Clamp Zener and Blocking Diode Options.
3-129
Rev. C 07/04
Step 30 – Select output rectifier per Table 9 Step 31 – Select output capacitor
• VR ≥ 1.25 x PIVS; where PIVS is from Step 28 and VR is the • Ripple current specification at 105 °C, 100 kHz: Must be
rated reverse voltage of the rectifier diode. equal to or larger than IRIPPLE, where IRIPPLE is from Step 27.
• ID ≥ 3 x IO; where ID is the diode rated DC current and • ESR specification: Use low ESR, electrolytic capacitor.
IO = PO / VO. Output switching ripple voltage is ISP x ESR , where ISP is
from Step 24.
Rec. Diode VR(V) ID(A) Package Manufacturer • Examples:
Schottky
1N5819 40 1 Axial General Semi Output Output Capacitor
SB140 40 1 Axial General Semi
SB160 60 1 Axial General Semi 5 V to 24 V, 1 A 330 µF, 35 V, low ESR, electrolytic
MBR160 60 1 Axial IR UnitedChemicon
11DQ06 60 1.1 Axial IR LXZ35VB331M10X16LL
1N5822 40 3 Axial General Semi Rubycon 35YXG330M10x16
SB340 40 3 Axial General Semi Panasonic EEUFC1V331
MBR340 40 3 Axial IR
SB360 60 3 Axial General Semi 5 V to 24 V, 2 A 1000 µF, 35 V, low ESR, electrolytic
MBR360 60 3 Axial IR
United Chemicon
LXZ35VB102M12X25LL
Rubycon 35YXG1000M12.5x25
MBR745 45 7.5 TO-220 General Semi
Panasonic EEUFC1V102
IR
MBR760 60 7.5 TO-220 General Semi
Step 32 – Select output post filter L, C
MBR1045 45 10 TO-220 General Semi
IR
• Inductor L: 2.2 µH to 4.7 µH. Use ferrite bead for low
current (≤1A) output and standard off-the-shelf choke for
higher current output. Increase choke current rating or wire
size, if necessary, to avoid significant DC voltage drop.
IR
• Capacitor C:100 µF to 330 µF, 35 V, electrolytic
MBR2045CT 45 20(2x10) TO-220 General Semi Examples for 100 µF, 35 V, electrolytic:
IR United Chemicon KMG35VB101M6X11LL
3 MBR2060CT 60 20(2x10) TO-220 General Semi Rubycon 35YXA100M6.3x11
MBR20100 100 20(2x10) TO-220 General Semi Panasonic ECA1VHG101
IR
UFR Step 33 – Select bias rectifier from Table 10
UF4002 100 1 Axial General Semi
UF4003 200 1 Axial General Semi • VR ≥ 1.25 x PIVB; where PIVB is from Step 28 and VR is the
MUR120 200 1 Axial General Semi rated reverse voltage of the rectifier diode.
EGP20D 200 2 Axial General Semi
BYV27-200 200 2 Axial General Semi Rectifier VR (V) Manufacturer
Philips BAV21 200 Philips
UF5401 100 3 Axial General Semi UF4003 200 General Semi
UF5402 200 3 Axial General Semi 1N4148 75 Motorola
EGP30D 200 3 Axial General Semi
Table 10. Bias Rectifier Options.
BYV28-200 200 3.5 Axial General Semi
Philips Step 34 – Select bias capacitor
MUR420 200 4 TO-220 General Semi
BYW29-200 200 8 TO-220 General Semi • Use 0.1 µF, 50 V, ceramic.
Philips
BYV32-200 200 18 TO-220 General Semi Step 35 – Select CONTROL pin capacitor and series resistor
Philips
Table 9. Output Diode Options. • CONTROL pin capacitor: 47 µF, 10 V, low cost electrolytic
(Do not use low ESR capacitor).
3-130
Rev. C 07/04
• Series resistor: 6.8 Ω, 1/4 W (Not needed if KP ≥ 1, i.e.

discontinuous mode).
Step 36 – Select feedback circuit components according to

applicable reference feedback circuits shown in Figures 3,
4, 5 and 6
• Applicable reference circuit: Identified in Step 2.
Step 37 – Select input bridge rectifier
• VR ≥ 1.25 x 2 x VACMAX; where VACMAX is from Step 1.

• ID ≥ 2 x IAVE; where ID is the bridge rectifier rated current
and IAVE is average input current.
POUT
Note: I AVE = ;
VMIN × η
where VMIN is from Step 3 and η from Step 1.
3-131
Rev. C 07/04
Appendix A: where ISRMS(n) and IO(n) are the secondary RMS current and
output average current of the nth output and ISRMS and IO are the
Multiple Output Flyback Power secondary RMS current and output average current for the
Supply Design lumped single output equivalent design.
The only difference between a multiple output flyback power Customization of Secondary Designs for Each Output
supply and a single output flyback power supply of the same The turns for each secondary winding are calculated based on
total output power is in the secondary side design. Instead of the respective output voltage VO(n):
delivering all power to one output as in the single output case,
a multiple output flyback distributes its output power among VO (n) + VD (n)
several outputs. Therefore, the design procedure for the primary N S ( n) = NS ×
side stays the same, while that for the secondary side demands
V + VD
further considerations. Output rectifier maximum inverse voltage is
Design with Lumped Output Power NS ( n)

PIVS (n) = VMAX × + VO (n)
One simple way of doing multiple output flyback design is NP
described in detail in AN-22, “Designing Multiple Output
Flyback Power Supplies with TOPSwitch”. The design method With output RMS current ISRMS(n), secondary number of turns
starts with a single output equivalent by lumping output power NS(n) and output rectifier maximum inverse voltage PIVS(n)
of all outputs to one main output. Secondary peak current ISP and known, the secondary side design for each output can now be
RMS current ISRMS are derived. Output average current IO carried out exactly the same way as for the single output design.
corresponding to the lumped power is also calculated.
Secondary Winding Wire Size
Assumption for Simplification The TOPSwitch-GX design spreadsheet assumes a CMA of 200
The current waveforms in the individual output windings are when calculating secondary winding wire diameters. This gives
determined by the impedance in each circuit, which is a function the minimum wire sizes required for the RMS currents of each
of leakage inductance, rectifier characteristics, capacitor value output using seperate windings. Designers may wish to use
and most importantly, output load. Although this current larger size wire for better thermal performance. Other
waveform may not be exactly the same from output to output, considerations such as skin effect and bobbin coverage may
it is reasonable to assume that, to the first order, all output suggest the use of a smaller wire by using multiple strands
currents have the same shape as for the single output equivalent wound in parallel. In addition, practical considerations in
of lumped power. transformer manufacturing may also dictate the wire size.
3 Output RMS Current vs. Average Current
The output average current is always equal to the DC load
current, while the RMS value is determined by current wave
shape. Since the current wave shapes are assumed to be the
same for all outputs, their ratio of RMS to average currents must
also be identical. Therefore, with the output average current
known, the RMS current for each output winding can be
calculated as
I SRMS
I SRMS (n) = I O(n) ×
IO
Revision Notes Date

A 1) Final release. 9/02
B 1) Minor revision. 12/02
C 1) Minor revision: Corrected VMAX equation. 7/04
3-132
Rev. C 07/04
LinkSwitch®
Design Guide
Introduction output characteristic as shown in Figure 2. In charger applications,

a discharged battery operates on the CC portion of the curve
Integrated switching power supply technology, offering small until almost fully charged and then naturally transitions to the
size, low weight and universal AC input voltage operation, has CV portion of the curve. Below an output voltage of
finally evolved to cost-effectively replace linear transformer- approximately 2 V (consistent with a failed battery pack), the
based power supplies for low power applications. LinkSwitch supply enters auto-restart, reducing the average output current
reduces the cost of switching battery chargers and AC adapters to approximately 8% of nominal.
to the level of linear transformer power supplies. LinkSwitch
also easily meets standby and no-load energy consumption In an AC adapter, normal operation occurs only on the CV
guidelines specified by worldwide regulatory programs such as portion of the curve, the CC portion providing overload
the USA’s Presidential 1 W Standby Executive Order and the protection and auto-restart short circuit protection.
European Commission’s 2005 requirement for 300 mW
no-load consumption. LinkSwitch is a fixed frequency PWM controlled device,
designed to operate with flyback converters in discontinuous
The feature set of LinkSwitch offers the following advantages mode. In the CV portion of the curve, the device operates using
over other solutions: voltage mode control and changes to a current limit mode
during the CC portion of the curve. Total system CV accuracy
• Lowest cost and component count for a constant voltage, is typically ±10% at the peak power point, including all device
constant current (CV/CC) solution tolerances and line input voltage variations. The total system
• Extremely simple circuit – only 14 components required CC accuracy is typically ±20% (LNK501), ±25% (LNK500)
for a production-worthy design and ±24% (LNK520).
• Primary based CV/CC solution eliminates 10 to 20
components for low system cost During CV operation, the output voltage is sensed on the
• Up to 75% lighter power supply reduces shipping costs primary side and controls the duty cycle. For LNK500/501 the
• Fully integrated auto-restart for short circuit and open device is placed in the high-side rail as shown in Figure 1. This
loop fault protection allows the reflected output voltage (VOR) to be sensed directly,
• 42 kHz operation simplifies EMI filter design requiring no additional subtraction of the input voltage
3
• 3 W output with EE13 core for low cost and small size component. For LNK520, the device is placed in the low-side
as shown in Appendix B, Figure B1, with an auxiliary/bias
LinkSwitch is designed to produce an approximate CV/CC winding to sense the output voltage.
L1 U1 CCP
680 µH - 2.2 mH, LinkSwitch 0.22 µF/1 µF, + VRSEC + VDOUT + VRCABLE
≥80 mA RMS 10 V NP:NS
D S
C RSEC DOUT RCABLE
0.15 Ω 0.7 V/ 0.3 Ω
RF1 1.1 V IO
10 Ω IDCT CCLAMP VFB
C1+C2
Fusible 3 µF/W 0.1 µF, 100 V +
RFB
or 1 µF/W + +
AC INPUT VOR VSEC COUT Load VO
+
DCLAMP
D1-D4 1N4937
IN4005 ISEC(RMS) ~
~ 2 x IO
1 A, 600 V VLEAK
RLF ISEC(PEAK) ~
~ 4 x IO
+
100 Ω
LP PI-2957-081602
Figure 1. Key Parameters for an Initial LinkSwitch Design.
3-133
Rev. D 08/06
During CC operation, duty cycle is controlled by the peak drain

current limit (ILIM). The device current limit is designed to be a LNK500/501 QUICK START
function of reflected voltage such that the load current remains
approximately constant as the load impedance is reduced. When
Figure 1 shows the key parameters and components
the output voltage falls to approximately 30% of nominal value
needed to generate an initial LinkSwitch design.
(normally associated with a failed battery), LinkSwitch enters the
Where initial estimates can be used, they are shown
auto-restart mode of operation to safely limit average fault current
below the parameter they refer to.
(typically 8% of IO).
1) Let VOR equal 50 V.
With discontinuous mode design, maximum output power is
independent of input voltage and is a simple function of primary 2) Define the transformer turns ratio according to
inductance, peak primary current squared and switching Equation 5. If no better estimates or measure-
frequency (Equation 6). LinkSwitch controls and cancels out ments are available, then let VDOUT equal 0.7 V
variations normally associated with frequency and peak current for a Schottky or 1.1 V for a PN diode, RCABLE equal
by specifying a device I2f term. This allows users to easily 0.3 Ω, RSEC equal 0.15 Ω, ISEC(RMS) equal 2 x IO, and
design for a specific corner point where CV mode transitions to ISEC(PEAK) equal 4 x IO, where IO is the desired CC
CC mode. output current and VO is the desired output
voltage at the CV/CC transition point.
Scope 3) Calculate PO(EFF) according to Equation 13. As an
This application note is for engineers designing an AC-DC initial estimate for PCORE use 0.1 W.
power supply using the LinkSwitch LNK500/501 or LNK520 4) Calculate LP according to Equation 14 and
devices in a discontinuous mode flyback converter. The main other transformer parameters from Equations
document focuses on the LNK500/501 devices. However, as 15, 16, 17, 18 and 19.
much of the information is also applicable to LNK520, it is
recommended this section be read regardless of the device 5) Calculate value for feedback resistor RFB accord-
selected for the design. For a detailed comparison of LNK500 ing to Equations 20, 21, 22, 23 and 24.
vs. LNK520 please see Table B2. Appendix A provides a This should be a 1/4 W, 1% part.
detailed tolerance analysis for LNK500/501 designs while
Appendix B provides specific guidance when designing with 6) Set clamp capacitor CCLAMP as a 0.1 µF, 100 V
LNK520 devices. metalized plastic film type.
7) Set clamp resistor RLF as 100 Ω, 1/4 W.

Since LinkSwitch is designed to replace linear transformer
3 based power supplies, the output characteristic provides an 8) Set CONTROL pin capacitor CCP to be 0.22 µF,
approximate CV characteristic, offering much better line and 10 V for battery loads or 1 µF, 10 V for resistive
load regulation than an equivalent linear transformer. The very loads.
simple nature of the LinkSwitch circuit allows an initial paper
design to be completed quickly using simple design equations. 9) Select input and output components. See
It is then recommended that the circuit performance be tuned Figure 3 and relevant sections.
with a prototype power supply to finalize external component 10) Construct prototype.
choices.
11) Iterate design (see Hints and Tips section).
This document therefore highlights the key design parameters
and provides expressions to calculate the transformer turns Table 1. LNK500/501 Quick Start.
ratio, primary inductance and clamp/feedback component values.
This enables designers to build an operating prototype and
iterate to reach the final design. examples showing typical transformer construction techniques.
Further details of support tools and updates to this document
For readers who want to generate a design as quickly as can be found at www.powerint.com.
possible, the Quick Start tables (Table 1 for LNK500/501 and
Table B1 for LNK520) provide enough information to generate CV/CC Circuit Design
an initial prototype.
The LinkSwitch circuit shown in Figure 3 serves as a CV/CC
This document does not address transformer construction. charger example to illustrate design techniques. Nominal output
Please see LinkSwitch DAK Engineering Prototype Reports for voltage is 5.5 V and nominal CC output current is 500 mA.
3-134
Rev. D 08/06
10
PI-2956-032403
9 115 VAC
230 VAC
8 Limits (LNK501)
Limits (LNK500)
Auto-restart
7
Output Voltage (V)
0
0 100 200 300 400 500 600 700
Output Current (mA)
Figure 2. Typical Output Characteristic for LinkSwitch LNK500/501 Based 5.5 V, 0.5 A Charger with Specification Limits.
LinkSwitch design methodology is very simple. Transformer voltage VO, the secondary winding voltage drop VRSEC, and
turns ratios and bias component values are selected at the output diode forward voltage drop VDOUT. Figure 1 shows the
nominal peak power point output voltage VO, while transformer sources of secondary side voltage drops. Since CCLAMP charges
primary inductance is calculated from the total output power. to the peak value of VOR plus an error due to leakage inductance,
Few components require computations, while the balance are the value of VRSEC and VDOUT are defined at the peak secondary
selected from the included recommendations. current. The output cable drop VRCABLE is defined at the nominal
CC output current IO. 3
Design and selection criteria for each component are described
starting with the transformer. Once set, transformer parameters Curves of VDOUT versus instantaneous current can be found in
and behavior are used to design clamp, bias and feedback the diode manufacturer’s data sheet. Peak secondary current is
components for proper supply operation. Output capacitors and defined as:
the input circuitry can then be determined. N
ISEC ( PEAK ) = I PRI ( PEAK ) × P (1)
NS
Transformer T1
The value for IPRI(PEAK) is equal to the typical value of the
Transformer design begins by selecting the reflected output LinkSwitch data sheet parameter ILIM.
voltage (VOR). For most LinkSwitch designs, VOR should be
between 40 V and 60 V. A good starting point is 50 V allowing As an initial estimate the ISEC(PEAK) can be approximated as
for optimization later. 4 x IO. Once the first prototype has been built this can be refined
as the final turns ratio is known or alternatively, the peak diode
VOR values over 60 V are recommended only for those forward voltage can be measured directly using an oscilloscope.
applications allowed to consume over 300 mW at no-load.
VRCABLE = IO × RCABLE (2)
To calculate the transformer turns ratio, the voltage required
across the secondary winding VSEC is first calculated. This is a VRSEC = ISEC ( PEAK ) × RSEC (3)
function of output cable voltage drop VRCABLE, nominal output VSEC = VO + VRCABLE + VDOUT + VRSEC (4)
3-135
Rev. D 08/06
U1
L1
LinkSwitch
1 mH T1
D S 1 5 5.5 V,
C3 500 mA
C
0.22 µF 15 T
116 T 4 C5
50 V #30 AWG
BR1 #34 AWG 470 µF
RF1 TIW 10 V
1 A, 600 V R1 C4
10 Ω 1 W 20.5 kΩ 0.1 µF
Fusible 1% 100 V RTN
C1 C2 3 6
D6
85-265 4.7 µF 4.7 µF
VAC 11DQ06
400 V 400 V D5 EE13
1N4937 LP = 2.55 mH
R2
100 Ω PERFORMANCE SUMMARY
Efficiency: ≥72%
No Load
200 mW, 115 VAC
PI-3476-032403
Figure 3. Example Schematic for a Typical LinkSwitch Charger.
The transformer turns ratio is given by: Note that IP and fS are enclosed in brackets as the LinkSwitch data
sheet specifies an I2f coefficient equal to the I2PfS product,
NP V normalized to IDCT. By normalizing to IDCT (the CONTROL pin
= OR (5)
N S VSEC current at 30% duty cycle), the effect of IDCT tolerance is
included and does not need to be considered separately. Output
If no better estimates or measurements are available, use power is therefore dependent primarily on transformer primary
0.15 Ω as an initial value for the transformer secondary winding inductance tolerance (typically ±10% for low cost high volume
resistance RSEC, 0.7 V for the forward voltage (VDOUT) of a production methods).
3 Schottky diode or 1.1 V for a PN diode and 0.3 Ω for the cable
resistance RCABLE. As shown above, effective output power PO(EFF) is calculated
from the total energy stored in the transformer and is therefore
The next transformer design step is to calculate the nominal the sum of actual output power PO and the following loss terms:
primary inductance LP. LP tolerance should be within ±10% (to cable power PCABLE, diode power PDIODE, bias power PBIAS(the
meet peak power CC tolerance of ±20% for LNK501, ±25% for power required to drive the LinkSwitch CONTROL pin),
LNK500). The simple LinkSwitch feedback circuit is designed transformer secondary copper loss PS(CU) , and transformer core
specifically for discontinuous mode operation. Continuous loss PCORE.
mode designs result in control loop instability and are therefore 2
not recommended. For proper CC operation, the LinkSwitch PCABLE = RCABLE × IO (7)
transformer must therefore be designed for discontinuous PDIODE = VDOUT × IO (8)
operation under all line/load conditions.
PBIAS = VOR × 2.3 mA (9)
At the peak power point, the power processed by the core or KCORE × VE
PO(EFF) is given by: PCORE = (10)
2
2
1
PO( EFF ) =
2 [ 2
× LP × I P × f S ] (6)
PS ( CU ) = ISEC ( RMS ) × RSEC (11)
RCABLE is the total cable DC resistance, IO is the nominal CC

LP is the nominal transformer primary inductance, IP is equal to output current, VDOUT is output diode forward voltage drop, VOR
the LinkSwitch parameter ILIM and fS is the switching frequency. is reflected output voltage, ISEC(RMS) is secondary RMS current,
3-136
Rev. D 08/06
RSEC is output winding DC resistance, VE is core effective minimum gap length is 0.08 mm (3.2 mils) at a peak flux density
volume and KCORE is core loss per unit volume. As before, if no of 3300 gauss to 3500 gauss (330 mT to 350 mT).
better estimates or measurements are available, use 0.15 Ω for
RSEC, 0.7 V for the forward voltage (VDOUT) of a Schottky diode The number of secondary turns for small E cores is typically 2
or 1.1 V for a PN diode, 0.3 Ω for RCABLE and ISEC(PEAK) equal to to 3 turns per volt across the secondary winding (including
4 x IO. Both VE and KCORE can be read from the ferrite core cable, secondary and diode voltage drops). The actual number
manufacturer’s material curves. To find KCORE, use the core flux is adjusted to meet gap size and flux density limits.
swing BM. In discontinuous mode operation, AC Flux Density
BAC is equal to BM: Once an estimate for the number of secondary turns NS has been
BAC = BM (12) made, the primary turns is found from:
The division by two in the expression for PCORE is required since VOR
NP = × NS (15)
a flyback transformer only excites the core asymmetrically and VSEC
the core loss curves are typically specified assuming a
symmetrical excitation.
KCORE is then read directly from material core loss curves at the
Primary Inductance (%)

LinkSwitch switching frequency (typically 42 kHz). A figure 100
for BM of approximately 3300 gauss (330 mT) is a good initial
estimate. A figure for PCORE of 0.1 W is a good initial estimate. 80
PO(EFF) is calculated from: Area compensated

by ∆L term
PCORE
PO( EFF ) = PO + PCABLE + PDIODE + PBIAS + PS ( CU ) +
2
(13) 250 330
Flux Density (mT)
PO here is defined as the output power seen by the load. Note PI-3148-081502
the core loss term is divided in half as only the loss associated
with transferring energy to the output during the off time needs Figure 4. Typical Reduction in Primary Inductance with Flux
to be compensated for in the primary inductance value. Density for Small E Cores with Small Gap Sizes.
Nominal primary inductance LP(NOM) is calculated from: At this point the core size should be selected. Common core
sizes suitable for a LinkSwitch design include EE13, EF12.6, 3
2 × PO( EFF ) EE16 and EF16. With the core selected and the number of
LP( NOM ) = × ∆L transformer turns known, the core peak flux density BP (gauss)
[I 2
P × fS ] (14)
can be found using the effective cross sectional area of the core
Ae (cm2), the primary inductance (µH) and the LinkSwitch peak
The typical data sheet value for the I2f coefficient should be used current limit ILIM(MAX) (A):
to replace I2fS, this defining the nominal primary inductance at
the nominal output peak power point. 100 × I LIM ( MAX ) × LP
BP = (16)
N P × Ae
As the flux density increases, the inductance falls slightly due
to the BH characteristic of the core material as shown in BP should be in the range of 3000 gauss to 3500 gauss
Figure 4. This drop in inductance is compensated by increasing (300 mT to 350 mT).
the inductance at zero flux density by a factor ∆L. This is
typically in the range of 1 to 1.05 for common low cost ferrite The relative permeability µr of the ungapped core must be
materials. This effect can be minimized by increasing the gap calculated to estimate the gap length Lg. The relative
size, reducing the flux density or using ferrite materials with a permeability, µr is found from core parameters Ae (cm2), the
higher saturation flux density. effective core path length Le (cm), and ungapped effective
inductance AL(nH/t2):
Transformer inductance tolerance is most affected by the
transformer core gap length. Inductance must also be stable AL × Le
µr = (17)
over temperature and as a function of current. Recommended 0.4 × π × Ae × 10
3-137
Rev. D 08/06
Gap length Lg is the air gap ground into the center leg of the NP
ISEC ( PEAK ) = × I PRI ( PEAK )
transformer core. Grinding tolerances and AL accuracy place a NS
minimum limit of approximately 0.08 mm on Lg. If Lg is smaller
116
than this then either the core size (Ae) or NP must be increased. = × 0.254
15 (20)
Lg (mm) is calculated from primary turns NP, core effective
cross sectional area Ae (cm2), primary inductance LP (µH), core = 1.96 A
effective path length Le (cm) and relative permeability µr:
The secondary diode peak voltage was measured as 0.7 V, the
⎡ 0.4 × π × N 2 × A secondary winding resistance as 0.15 Ω and the cable resistance
P e L ⎤ (18)
Lg = ⎢ − e ⎥ × 10 as 0.23 Ω. Therefore VSEC is defined as:
⎢⎣ LP × 100 µ r ⎥⎦
VSEC = VO + VRCABLE + VDOUT + VRSEC

The gapped effective inductance ALG (nH/t2), required by the
transformer manufacturer, is calculated from the primary = VO + ( IO × RCABLE ) + VDOUT
inductance LP (µH) and the number of primary turns NP: + ( ISEC ( PEAK ) × RSEC )
(21)
LP = 5.5 V + (0.5 A × 0.23 Ω) + 0.7 V
ALG = 1000 × 2 (19) + (1.96 A × 0.15 Ω)
NP
= 6.61 V
Clamp, Bias, Bypass and Feedback
Voltage VSEC allows the exact VOR to be calculated:
An RCD clamp, formed by R FB, C CLAMP, and D CLAMP
(Figure 1), safely limits transformer primary voltage, due to
transformer leakage inductance, to below the LinkSwitch internal NP
VOR = × VSEC
MOSFET breakdown voltage BVDSS each time LinkSwitch NS
turns off. Leading-edge voltage spikes (caused by transformer (22)
116
leakage inductance) are filtered by RLF and CCLAMP, such that = × 6.61 V
15
CCLAMP effectively charges to the transformer reflected voltage.
= 51.1 V
Feedback is derived from the reflected voltage, that approximates
closely the transformer secondary winding output voltage Resistor RFB, a 1%, 0.25 W resistor, converts clamp voltage to
(VSEC in Figure 1) multiplied by the transformer turns ratio. Due LinkSwitch bias and control current.
to effects of leakage inductance (causing peak charging),
3 calculated VOR may be slightly different from actual voltage Feedback voltage VFB is calculated from VOR and the error due
measured across CCLAMP. Since LinkSwitch is in the upper rail, to leakage inductance, VLEAK.
reflected voltage information is now relative to the LinkSwitch
SOURCE pin and independent of the input voltage. The value for VLEAK varies depending on the value of leakage
inductance, the size of the clamp capacitor and the type of clamp
Reflected voltage is directly converted by RFB to LinkSwitch diode selected. For a leakage inductance of 50 µH, a value of
CONTROL pin current for duty cycle control and bias. The 5 V is a good initial estimate.
CONTROL pin capacitor CCP provides bypass filtering, control
loop compensation, and the energy storage required during VFB = VOR + VLEAK (23)
start-up and auto-restart.
Once a prototype has been constructed, the value of VFB can be
Feedback Resistor (RFB) found directly, by measuring the voltage across CCLAMP at the
power supply peak output power point, using a battery powered
Clamp and feedback circuit design begins by first considering digital voltmeter. These have sufficient common mode rejection
reflected voltage. Using the schematic in Figure 3 as an to be unaffected by the switching waveform and provide
example. With primary turns NP = 116 and secondary turns accurate results. The voltage measured is VFB. By subtracting
NS = 15 the peak secondary current can be calculated from VOR the value for VLEAK can be determined, useful as an estimate
Equation 20, where IPRI(PEAK) is equal to the LinkSwitch in future designs. For the design in Figure 3, VFB was measured
typical current limit ILIM(TYP). as 56.7 V, giving VLEAK as 5.6 V.
3-138
Rev. D 08/06
V V
Peak Power Peak Power

Curve Curve
Reduced RLF or Increased RLF or

increased leakage Reference reduced leakage Reference
inductance inductance
Reduced RLF Higher RLF
or increased or lower
leakage leakage
inductance inductance
Auto-restart Auto-restart
I I
PI-2958-081602
Figure 5. Effect on Output Characteristic when RLF or Leakage Inductance Changes.
An initial value for RFB is calculated from the feedback voltage

VFB, the CONTROL pin voltage VC(IDCT) and current IDCT at the V
CC/CV transition point, specified in the LinkSwitch

data sheet. Peak Power
Curve
VFB − VC ( IDCT )
RFB =
I DCT
56.7 V − 5.75 V (24)
=
2.3 mA Increased RFB Reference
= 22 kΩ Increased
RFB to adjust
Select the nearest standard value. Resistor RFB can then be

for LLEAK
Auto-restart
3
adjusted to center the output voltage. The example in
Figure 3 uses a 20.5 kΩ value for RFB (R1), centering the output I PI-2959-071902
voltage VO near 5.5 V at nominal output current IO.
Figure 6. Increasing RFB to Adjust for High Leakage Increases No-
Note that RFB power dissipation, a significant component of Load Voltage and Consumption.
LinkSwitch standby power, should always be calculated:
Note that normal recovery diodes (1N400X or similar types),
PRFB = (2.3 mA)2 × RFB = 111 mW (25)
which may allow excessive drain voltage ringing, should not be
used.
For applications that do not need to comply with strict standby
power requirements, higher values of VOR can be used, also
Clamp Resistor (RLF)
increasing the power capability of LinkSwitch.
The value for RLF, which effectively filters the leakage inductance
Clamp Diode (DCLAMP)
spike from the reflected voltage waveform, is verified empirically
through iteration. RLF has a direct effect on both the average
Diode DCLAMP should be an ultra-fast or fast recovery diode with
value and slope of both the CV and CC curves as shown in
at least 600 V breakdown voltage. Fast types typically offer a
Figure 5 and can therefore be used to tune the output characteristic
slight cost advantage and also reduce EMI, so they are preferred.
to some extent.
3-139
Rev. D 08/06
CCLAMP must have a stable value over temperature and also over
the operating voltage range. Metalized plastic film capacitors
RCABLE are the best choice, since the higher voltage ceramic capacitors
RLOAD with stable dielectrics (NPO or COG, for example) are higher
RINT_RES RCABLE = 0.23 Ω cost. The value of low cost ceramic capacitors varies significantly
RINT_RES = 0.5 Ω with voltage and temperature (Z5U dielectric, for example) and
should not be used since they may cause output oscillation.
2 x 1N4001 10,000 µF RLOAD= 11 Ω
CONTROL Pin Capacitor (CCP)
PI-2975-072402
CCP sets the auto-restart period and also the time the output has
to reach regulation before entering auto-restart at power supply
Figure 7. Example of Battery Model Load (Values for a Typical start-up. If the load is a battery, then a value of 0.22 µF is
3 W, 5.5 V Battery Charger). typical. However, if the supply is required to start into a
resistive load or constant current load (such as a bench electronic
In the CV region, increasing RLF increases the average output load) at the peak output power point, then this should be
voltage, while reducing the slope of the CV region (the change increased to 1 µF. This ensures enough time during start-up to
in output voltage with the change in output current). In the CC bring the output into regulation. The type of capacitor is not
region, increasing RLF makes the average output current lower, critical. Either a small ceramic or electrolytic may be used with
while tending to “bend” the curve inward slightly (fold back). a voltage rating of 10 V or more.
At no-load, increasing RLF slightly increases the no-load voltage Output Rectifier and Filter (DOUT, COUT)
since the primary leakage inductance is filtered more effectively,
but the same peak charging due to secondary leakage inductance The output diode should be selected with an adequate peak
occurs. Although the no-load voltage is slightly higher, there is inverse voltage (PIV) rating. Either PN or Schottky diodes can
only a minor effect on no-load consumption. be used. Schottky diodes offer higher efficiency at higher cost
but provide the most linear CC output characteristic. Both fast
In a design that has high leakage, the value of RFB can be or ultra fast PN diodes may be used, but ultra fast (tr r~50 ns)
increased to raise the overall output voltage (Figure 6). However, are preferred giving CC linearity close to the performance of a
this will also increase no-load voltage and therefore no-load Schottky.
input power consumption.
⎛ N ⎞
To iterate RLF: PIV DOUT ≥ ⎜ VDC ( MAX ) × S ⎟ + (VO × 1.5) (26)
3 ⎝ NP ⎠
• Start with typical value of 100 Ω and a transformer with

nominal inductance. The output diode voltage rating should be calculated from
• Verify CC portion of the curve and increase or decrease Equation 26. VDC(MAX) is the maximum primary DC rail voltage
RLF until CC curve is approximately vertical (current at (375 V for universal or 230 VAC and 187 V for 115 VAC only
start of CC and end are approximately the same) designs). The output voltage VO is multiplied by 1.5 to allow for
• Verify CV portion of the curve. increased output voltage at no-load. An output diode current
- For minor adjustment, change value of RFB. rating of 2 x IO is a good initial estimate.
Clamp Capacitor (CCLAMP) The output diode may be placed in either the upper or lower leg
of the secondary winding. However, placement in the lower leg
With small values of clamp capacitor CCLAMP, the output voltage may provide lower conducted EMI with a suitably constructed
tends to be slightly higher. With larger values for CCLAMP, output transformer.
voltage will be slightly lower. Further increases in CCLAMP will
not change the output voltage. For battery charger applications, the size and cost of the output
capacitor COUT can be significantly reduced. High ripple current
CCLAMP is therefore chosen empirically as the smallest value that flows through COUT for only the short time a fully depleted
does not significantly change the output voltage when compared battery charges. The designer should take into account that
to the next larger value. For most designs, 100 nF is typical and COUT ripple current rating can be exceeded for short periods of
standard device tolerances will have a negligible effect on the time without reducing lifetime significantly. When the battery
output voltage. This capacitor should be rated above the VOR, is close to fully charged, the LinkSwitch circuit transitions to
typically 100 V. CV mode, where capacitor ripple current is much smaller.
3-140
Rev. D 08/06
Peak Power
Curve
Increasing cable
Reference
resistance
Increased
output cable
resistance
Auto-restart
PI-2961-072202 I PI-2962-072202
Figure 8. Uneven Core Gapping Makes CC Portion Nonlinear and Figure 9. Effect on Output Characteristic Due to Increased Output
Should be Avoided. Cable Resistance.
For adapter applications drawing rated load current in steady To meet certain safety agency requirements RF1 should fail
state, COUT should be a low ESR type, properly rated for ripple open without emitting smoke, fire or incandescent material,
current. that might damage the primary-to-secondary insulation barrier.
Consult with a safety engineer or local safety agency for
Designs for battery charging usually do not require an additional specific guidance.
output L-C stage (π filter) to reduce switching noise. The
battery itself will filter this noise and output ripple. However, Diodes D1-D4 should be rated at 400 V or above and be
if the load is resistive, then this stage may be required to meet standard recovery types to minimize EMI.
ripple and noise specifications. For evaluation of a battery
charger during design, a battery load can be simulated using a The combined value of C1 and C2 should be selected to give
circuit similar to that shown in Figure 7, which models both the 3 µF per watt (of output power), giving acceptable voltage
battery and output cable. ripple for universal designs. For high single input voltage
ranges (185 VAC to 265 VAC), this recommendation can be
Bridge Rectifier, Energy Storage, and EMI Filter reduced to 1 µF/W, however ripple current ratings and
differential mode line transient performance should be verified.
3
Figure 1 shows a typical input stage for a low cost design. D1-
D4 rectifies universal AC input voltage. C1 and C2 provide L1, which is effective for low frequencies, is typically in the
energy storage, smoothing, and EMI filtering. RF1 reduces range of 680 µH to 2.2 mH and should have a current rating of
surge current, EMI and will also safely open, like a fuse, if ≥80 mA RMS.
another primary component fails in a short circuit.
Hints and Tips
The conducted emissions EMI filter has effectively two
differential mode stages. RF1 and C1 form the first differential Transformer Construction
mode stage. The second differential mode filter stage is formed
by L1 and C2. Since the primary inductance is crucial in setting the peak
output power, the tolerance of this parameter should be well
RF1 should be a 10 Ω low cost wire-wound fusible resistor or controlled. For a CC tolerance at the peak power point of ±20%/
be replaced by a fuse. A resistor is preferable to a fuse as it also ±25% (LNK501/LNK500, respectively) the primary inductance
limits inrush current and protects against input voltage transients tolerance should be ±10% or better.
and surges (differential or normal mode). Lower values increase
dissipation (V2/R power term) during transients and inrush, Tolerance of ungapped core permeability limits minimum gap
while higher values increase steady state dissipation (I2R) and size for center leg gapping. For an EE13 core size, the practical
lower overall efficiency. Metal film types should not be used minimum center leg gap size, for an overall primary inductance
since they do not have a high enough transient power capability tolerance of ±10%, is ~0.08 mm. This varies with core supplier,
to survive line transient and inrush current and may fail so this should be verified before committing to a design.
prematurely in service.
3-141
Rev. D 08/06
Other gapping techniques allow tighter tolerances, but may not Reducing No-load Voltage with a Pre-load
be universally supported, so again, this should be verified with
the preferred magnetics vendor. Film gapping, where thin At very light loads (< ~5 mA), the output voltage rises due to
material spaces all three legs of the core, allows better mechanical secondary peak charging. This can be significantly reduced by
tolerance and improves overall primary inductance tolerance to the addition of a small pre-load resistor. Figure 10 shows the
±7% with a 0.05 mm gap. Since a gap now appears on the outer effect of a 1 mA and 2 mA pre-load on a 9 V output design,
legs of the core, flux spraying may result, causing pick up in the reducing the no-load voltage by 1.3 V. This level of pre-load has
input filter components and resulting in poorer than expected minimal effect on no-load consumption (~10 mW to 20 mW).
conducted EMI. This can be prevented, if necessary, by adding
a single shorted turn of copper foil around the outside of the Minimizing No-Load Consumption
transformer core also known as a “belly band.”
The major factors for no-load or standby consumption are PBIAS
Core gaps should be uniform. Uneven core gapping (see and the capacitive switching loss PC(LOSS) (Equations 9 and 28). If
Figure 8), especially with small gap sizes, may cause variation no-load consumption is too high, then the transformer may be
in the primary inductance with flux density (partial saturation) redesigned with a lower VOR.
and make the constant current region nonlinear. To verify
uniform gapping, it is recommended that the primary switching Total parasitic capacitance of device and transformer, typically
current waveshape be examined while feeding the supply from 25 pF to 30 pF, causes a switching loss that increases with input
a DC source. The slope is defined as di/dt = V/L and should voltage and has a significant effect on standby or no-load output
remain constant throughout the MOSFET on time. Any change power consumption.
in slope of the current ramp is an indication of uneven gapping.
2
C × VMAX × fS
PC ( LOSS ) = TOT (28)
Verifying Discontinuous Mode Operation 2
To verify a design will remain discontinuous conduction mode VMAX is typically 340 V for universal or 230 VAC applications
under worst case condition use Equation 27: and fS is 30 kHz at light or no load. Parasitic capacitance loss
PC(LOSS) is typically 40 mW to 100 mW. This loss is not included
2 × IO( MAX ) × fS ( MAX ) × LP( MAX ) NP in the LP calculation as this power is not processed through the
< (27)
D × (1 − D) × VDC ( MIN ) NS core.
To minimize transformer capacitance, double coated magnet

where IO(MAX) is the output current (A) at maximum CC tolerance wire should be used for the primary winding. The technique of
(typically IO(NOM) + 20%), fS(MAX) is the maximum LinkSwitch vacuum impregnation should not be used since the varnish acts
3 switching frequency (Hz), LP(MAX) is the primary inductance (H) as a dielectric, increasing winding capacitance. Dip varnishing
at maximum tolerance, D is duty cycle at minimum input does not cause this problem.
voltage (typically 0.3 at 85 VAC or 0.13 at 195 VAC) and
VDC(MIN) the minimum DC voltage at lowest input line voltage An RC snubber placed across the output diode also increases
(typically 100 VDC for 85 VAC and 230 VDC for 195 VAC). no-load consumption. If necessary, minimize the value of the
Effect of Output Cable
Factors such as leakage inductance, the value for RLF, RFB and 15
CCLAMP have been covered. However, there are other parameters
Output Voltage (V)
No pre-load
that should be considered when designing with LinkSwitch. 1 mA pre-load
2 mA pre-load
If the gauge of wire selected for the output cable is reduced, then 12
the voltage drop across the cable resistance will increase. As
seen at the load, this appears as poorer CV operation and lower
efficiency, but with the CV/CC transition at the same output
current (see Figure 9). Ensure that the voltage drop or resistance 9
of the output cable is acceptable. 0 4 8 12
Output Current (mA)
PI-3227-082202
Figure 10. A Small Pre-load can Significantly

Reduce No-load Voltage.
3-142
Rev. D 08/06
capacitor used. If an ultra-fast diode has been selected, try a fast feedback resistor RFB is split into two to form a divider which
diode as this may allow the snubber to be removed. limits the voltage across the optocoupler phototransistor. The
optocoupler therefore effectively adjusts the resistor divider
Correct Oscilloscope Connection ratio to control the DC voltage across R2 and the current into the
CONTROL pin. For an output tolerance ≤ ±5%, VR1 should be
To prevent the additional capacitance of an oscilloscope probe replaced by a reference IC (TL431).
from triggering the LinkSwitch current limit, do not connect the
scope ground to the SOURCE pin. The scope should be connected A full description of the operation with an optocoupler can be
as shown in Figure 11 to measure source to drain voltage. Since found in the LinkSwitch data sheet.
the scope is referenced to the DC rail, an isolation transformer
must be used. Single Point Failure Testing
Improving CV Tolerance with Optocoupler The LinkSwitch circuit requires few considerations for single
point failure testing. Breaking the feedback loop by opening
The schematic in Figure 12 shows an example of adding a either RLF, DCLAMP or RFB results in LinkSwitch entering auto-
secondary reference and optocoupler to improve CV tolerance restart. Under this condition, the secondary output voltage will
across the entire load range. The voltage drop (sense voltage) rise but the output power is limited to ~8% of normal. This
across VR1, U1 and R3 sets the nominal output voltage. The prevents the output capacitor from failing catastrophically. If
Isolation
Transformer
PI-3164-032403
Figure 11. Correct Method of Connecting an Oscilloscope to Measure Switching Waveform.
LinkSwitch
D S VOUT
C C1
R3
C2
R1 U1
R R4
R1 = R2 = FB
2 D1
VR1
U1
R2 C3
RTN
PI-3222-082202
3-143
Rev. D 08/06
desired, a 0.5 W Zener can be added across the output to clamp Random Biases +
this voltage rise. The Zener voltage should be set above the Variable Biases Random ∆I/∆V
+ ∆I/∆V Random
normal maximum output voltage at no-load. Short circuiting or
Primary
opening CCP safely prevents LinkSwitch operation. – ±10% ±2.5% ±12.5%
Inductance
2
However, on opening of CCLAMP, LinkSwitch does not enter If – ±6% ±1.5% ±7.5%
auto-restart. The output voltage may rise unacceptably high Input Line ±3.2% ±3% – ±3%
under this condition and cause the failure of the output capacitor.
CC Linearity – ±2% – ±2%
As the supply delivers full power, output clamping requires a
Zener power rating equal to or above the nominal output power. Tj
±1.5% – – –
(25-65 °C)
Adding a second capacitor in parallel to CCLAMP prevents this Totals ±4.7% ±15% ±19.7%
problem. When CCLAMP is open circuited the second capacitor
acts as CCLAMP. This second capacitor can be a small value Table A1. Sources of CC Tolerance.
ceramic (0.01 µF) capacitor since during normal operation
CCLAMP dominates the parallel combination. Additional variations are summarized in Table A1, as both
random (unit-to-unit) or statistically independent variations
Appendix A: and biases or deterministic variations (apparent in a single unit
LinkSwitch LNK500/501 when tested). This distinction is made since random variations
are added using the root-sum-squares method, whereas biases
Tolerance Analysis add directly. A further column (∆I/∆V), applicable to the I2f and
Output Characteristic Tolerances LP terms, contains the value including the effect of the change
in output current with output voltage. This is necessary because
Both the device tolerance and external circuit govern the overall the CV slope is nonzero. Therefore, for example, if the peak
tolerance of the LinkSwitch power supply output characteristic. power increases, the voltage at the new peak power point tends
For a typical design, the peak power point tolerances are ±10% to be lower, further increasing the output current.
for voltage and ±20% (LNK501) / ±25% (LNK500) for current
limit. This is the estimated overall variation due to LinkSwitch, The figure of ±19.7% in Table A1 is the overall variation of the
transformer tolerance and line variation in high volume CC region.
manufacturing.
It is important to note that the figure of ±2% for constant current
This appendix provides expressions to allow the calculation of linearity (the straightness of the constant current characteristic)
3 expected circuit variation when in high volume manufacturing is only valid for designs close to 3 W output power, with a
primary inductance of ~3 mH. This is due to the internal
for a design employing a LNK501 as shown in Figure 3.
compensation for drain current di/dt variations over line voltage.
The same analysis can be extended to the LNK500. The only This compensation was arranged to correctly compensate, over
significant difference is a wider I2f tolerance (±12% compared a line voltage range of 85 VAC to 265 VAC, with a primary
to ±6% for LNK501) and associated increase in ∆I/∆V to ±3%. inductance of 3 mH. In lower power designs, where the primary
inductance is lower, an error results which increases the non-
Constant Current Limit linearity in the CC curve.
The peak power point prior to entering constant current operation Output diode of choice also effects CC linearity. The value in
is defined by the maximum power transferred by the transformer. Table A1 is based on a Schottky diode. The slower forward
Since LinkSwitch is designed to operate in discontinuous mode, recovery time of a PN diode can cause the CC characteristic to
the power transferred is given by the expression bend outwards with falling output voltage.
P = 1/2 L I2f, where L is the primary inductance, I is the primary
peak current and f is the switching frequency. Constant Voltage Operation at Peak Power Point
To simplify analysis, the data sheet parameter table specifies an During CV operation, the output characteristic is controlled by
I2f coefficient. This is the product of current limit squared and adjusting the duty cycle, based on the voltage VFB across
switching frequency, normalized to the feedback parameter capacitor CCLAMP (Figure 1). A number of parameters define the
IDCT. This provides a single term that specifies the variation of actual output voltage, and therefore, the tolerance of the output
the peak power point in the power supply due to LinkSwitch. voltage at the peak power point. The key parameters to consider
are:
3-144
Rev. D 08/06
• Current variation through RFB due to line voltage variation and +0.025 V for Schottky diode. For device-to-device
• CONTROL pin voltage - VC(IDCT) variations, please consult diode manufacturer.
• Output diode forward voltage - VDOUT
• Current variation through RFB due to CONTROL pin Any change in the current through RFB, due to the tolerance of
voltage tolerance at 30% Duty Cycle (IDCT) the CONTROL pin current at 30% duty cycle, IDCT, will also
• Feedback resistor tolerance - ∆%RFB cause a change in the output voltage. The change in the voltage
across RFB (kΩ) due to the tolerance of IDCT (mA) is given by:
Each of the key parameters above is examined in turn.
I DCT ( MAX ) − I DCT ( MIN )
The most significant variation in the output voltage is the ∆VRFB( IDCT ) = ± × RFB (A5)
2
change with input line.
Expressed as a percentage of the voltage across VFB, the
The voltage across RFB is defined at IDCT, corresponding to a variation is:
30% duty cycle at low line voltage. At higher line voltage, the ∆VRFB( IDCT )
CONTROL pin current increases and the voltage across RFB ∆% IDCT = ± × 100% (A6)
VFB
increases. The change in voltage across RFB, ∆VFB(LINE), depends
on the change in duty cycle ∆DC, the corresponding change in The overall variation can then be estimated using the expression:
CONTROL pin current ∆IC (mA) and the value RFB (kΩ). The
change in CONTROL pin current for a given change in duty ∆%CV = ± ∆% LINE ± ∆%VDOUT
cycle can be found from a curve in the LinkSwitch data sheet.
2
∆%VC ( IDCT ) + (A7)
∆VRFB( LINE ) = ∆IC × RFB (A1) ±
2 2
∆% IDCT + ∆% RFB
For a universal input voltage design, ∆DC from low line to high
line is typically 0.2 (0.09 for a single input design) giving a Using the design shown in Figure 3 as an example:
change in CONTROL pin current of typically 0.15 mA.
6 V − 5.75 V
The value of ∆VRFB(LINE) should be expressed as a percentage of ∆%VC ( IDCT ) = ± × 100% = ±0.46%
VFB to give the variation at the power supply output. The 54.2 V
(A8)
expression for line variation (at the peak power point) is
therefore: 0.025 V
∆VRFB( LINE ) ∆%VDOUT = ± × 100% = ±0.23%
∆% LINE = ± × 100% (A2) 2 × 5.5 V
2 × VFB (A9)
3
The CONTROL pin voltage VC(IDCT) is specified at a current ∆VRFB( LINE ) = 0.15 mA × 20.5 kΩ = 3.1 V
equal to IDCT, giving a duty cycle of 30% for a typical design at (A10)
the peak power point, at 85 VAC input. The tolerance of this
parameter includes temperature variation and can be read from 3.1 V
∆% LINE = ± × 100% = ±2.9%
the data sheet directly. Since the output voltage is actually 2 × 54.2 V
(A11)
controlled using VFB, the variation of VC(IDCT) must be expressed
as a percentage of VFB. The expression for this is given by:
2.36 mA − 2.24 mA
∆VRFB( IDCT ) = ± × 20.5 kΩ
2
VC ( IDCT )( MAX ) − VC ( IDCT )( TYP ) (A12)
∆%VC ( IDCT ) = ± × 100% = ±1.23 V
VFB
(A3) 1.23 V
∆% IDCT = ± × 100% = ±2.27% (A13)
Any variation in the output diode forward drop with temperature 54.2 V
will cause a change in the output voltage. Expressing as a
percentage of VO gives the expression:
The tolerance of R1 (RFB) is 1%.
∆V
∆%VDOUT = ± DOUT × 100% (A4)
2 × VO 2 2 2
∆%CV = ±2.9% ± 0.23% ± (0.46 + 2.27 + 1 )
Typical values for the change in forward voltage for a temperature = ±2.9% ± 0.23% ± 2.52% (A14)
change of +50 °C are +0.1 V for a silicon PN diode
= ±5.65%
3-145
Rev. D 08/06
The overall tolerance is the sum of the deterministic variation area to be maximized without EMI penalty. In addition, the
due to the change in line voltage and the change in the output switching characteristic of the LNK520 has been optimized,
diode forward voltage with temperature, together with the root- reducing radiated EMI by up to 5 dB. A summary of the
sum-square addition of the statistically independent circuit and comparisons between the two families is shown in Table B2.
device variables.
In Equation A14 the ∆%LINE term (±2.9%) is the expected LNK520 QUICK START
change in output voltage for a change of ±90 VAC at 175 VAC,
the mid point of the specified input voltage range of 85 VAC to Figure B1 shows the key parameters and components
265 VAC. needed to generate an initial LinkSwitch LNK520
design. Where initial estimates can be used, they are
Equivalently, starting with the reference as 85 VAC, the output shown below the parameter they refer to.
voltage would increase +5.8% (twice 2.9%) when the input
increases to 265 VAC. 1) Let VOR equal 50 V.
Standby losses increase with increasing VOR due
The analysis above is for a specific example, factors such as to primary parasitic capcitance (see Equation 28)
diode choice, temperature range and output voltage can result 2) Let VBIAS equal 15 V to 25 V.
in a larger tolerance. However, for most cases the designer can CC regulation improves but standby losses
be confident the overall tolerance will be <±10%. increase with increasing bias voltage.
3) Define the transformer turns ratio according to
Note that all of the above tolerances other than RFB and VC(IDCT)
Equation 5. If no better estimates or measure-
are compensated or accounted for in the previous analysis of CC
ments are available, then let VDOUT equal 0.7 V
tolerance. The contributions of RFB and VC(IDCT), since they are
for a Schottky or 1.1 V for a PN diode, RCABLE equal
unit-to-unit tolerances, have a very small influence (<0.1% on
0.3 Ω, RSEC equal 0.15 Ω, ISEC(RMS) equal 2 x IO, and
the total sum of unit-to-unit tolerances).
ISEC(PEAK) equal 4 x IO, where IO is the desired CC
output current and VO is the desired output voltage
Constant Voltage Operation Below Peak Power Point
at the CV/CC transition point.
As the output load reduces from the peak power point, the 4) Calculate PO(EFF) according to Equation 13. As an
output voltage will tend to rise due to tracking errors compared initial estimate for PCORE use 0.1 W.
to the load terminals. Sources of these include the output cable 5) Calculate LP according to Equation 14 and other
drop, output diode forward voltage and leakage inductance, transformer parameters from Equations 15, 16,
which is the dominant cause. 17, 18 and 19. Increase value from Equation 14
3 by 4%.
As the load reduces, the primary operating peak current reduces, 6) Calculate value for feedback resistor R FB
together with the leakage inductance energy, which reduces the according to Equations B3, B4, B5, B6, and B7.
peak charging of CCLAMP. With a primary leakage inductance This should be 1/4 W, 1% part.
figure of 50 µH, the output voltage typically rises 40% from full
7) Set bias capacitor CBIAS as 1.0 µF, 50 V aluminum
to no-load.
electrolytic type.
8) Set RCLAMP2 as 100 Ω, 1/4 W, select the largest
Appendix B: RCLAMP1 and smallest CCLAMP to keep VDS < BVDSS at
Considerations When Designing maximum line voltage, peak output power.
With Low-Side LinkSwitch LNK520 9) Set RLF as 200 Ω for high leakage inductance or
Devices 15 Ω for low transformer leakage values.
10) Set CONTROL pin capacitor CCP to be 0.22 µF,
Introduction 10 V for battery loads or 1 µF, 10 V for resistive
loads.
The LNK500/501 and LNK520 differ in the circuit location of
11) Select input and output components. See Figure
the LinkSwitch device. The LNK500/501 is designed for high-
B1 and relevant sections.
side operation and the LNK520 is designed for low-side operation
with a bias winding. The low-side configuration reduces common 12) Construct prototype.
mode EMI as the source is connected to the quiet primary 13) Iterate design (see Hints and Tips section).
return. This reduces the variation in EMI performance as the
PCB layout is altered and allows the source heatsinking PCB Table B1. LNK520 Quick Start.
3-146
Rev. D 08/06
(Optional)
RSNUB CSNUB
10-100 Ω 10-100 pF
L1
D1-D4 680 µH - 2.2 mH
1N4005 ≥80 mA RMS + VRSEC + VDOUT + VRCABLE
1 A, 600 V NP:NS
RCLAMP1 CCLAMP RSEC RCABLE
DOUT
100 kΩ- 100-2000 pF 0.1 Ω/ 0.7 V / 1.1 V 0.2 Ω/
500 kΩ 500 V + 0.15 Ω 0.3 Ω +
1/4 W V
LP OR VSEC COUT Load
+ VO
RF1 RCLAMP2
8.2 Ω RPRELOAD
L 2W
100 Ω ISEC(RMS) ~
~ 2 x IO (Optional)
ISEC(PEAK)~
~ 4 x IO
DCLAMP
1N4007GP
AC
Input C1+C2
3 µF/W VBIAS NB
N or 1 µF/W +
+ VDBIAS CBIAS
LinkSwitch VLEAK 1 µF
+ DBIAS RLF 50 V
U1
D LNK520
+ 0-300 Ω
C IDCT 1N4937 + VFB
VDS
RFB
S CCP
220 nF/1 µF
PI-3699-021904
Figure B1. Key Parameters for an Initial LinkSwitch LNK520 Design.
Family LNK500/501 LNK520
• Lowest cost CV/CC implementation • Very low cost CV/CC implementation

• Source is connected to the switching • Source connected to quiet low-side
node – simple circuit configuration & low primary return - easy layout & low noise 3
component count (low-side configuration only)
• Fast switching speeds minimize losses • Optimized switching speed – reduces
for best efficiency radiated EMI by up to 5 dBµV
• Source PCB copper heatsink connected (Figure B2)
Considerations to switching node – size should be • Source PCB copper heatsink connected
minimized to limit noise to primary return – area can be
maximized for higher power without
• No bias winding required – simplest noise (low-side configuration only)
circuit configuration • Bias winding required – allows higher
VOR, increasing power capability (low-
• Perfect for linear replacement in side configuration only)
applications where additional system EMI • Perfect for systems where no additional
shielding or filtering exists filtering or shielding exists
The LNK500/501 is recommended for cost The LNK520 is recommended for both
sensitive applications in larger systems stand-alone charger and adapter
Summary with existing EMI filtering (e.g. white applications, and larger systems where
goods). EMI reduction is required (e.g. emergency
lighting).
Table 2. Comparison of LNK500/501 and LNK520.
3-147
Rev. D 08/06
80 configuration requires the addition of a primary side bias
PI-3733-021904
70 winding and filtering components to allow the output voltage to
60 be sensed. Bias turns (NB) are selected to maintain approximately
QP: LNK500 20 V at the nominal constant voltage (CV) peak power point.
Amplitude (dBµV)
50
40 QP: LNK520
Adjustment of the bias voltage and filtering components is
30 required to compensate for leakage inductance imbalance
20 between secondary and bias windings, which varies according
10 AV: LNK500
to transformer construction. See the following sections for
AV: LNK520 details on selection of clamp and feedback components required
0
in the Low-side configuration. An output pre-load of a few
-10 milliamps may be necessary to reduce the no-load output
-20 voltage.
30.0 100.0 200.0
Frequency (MHz) Transformer Design
Figure B2. Comparison of LNK520 and LNK500 Showing an
Approximate 5 dBµV Reduction in Radiated EMI. Follow LNK520 guidelines with the following exceptions:
Scope 1) VOR range is 40 V to 80 V.

2) To correctly center the output peak power point over
This appendix is for engineers designing an AC-DC flyback temperature increase the calculated LP value by +4% at
power supply using the LNK520 device, expanding on the 85 VAC, -3% at 195 VAC.
information already presented. Unless noted, designing with 3) Primary inductance tolerance (LP) should be within ±7.5%
the LNK520 is consistent with the LNK500. (to meet CC tolerance of ±20% for LNK521, ±24% for
LNK520).
For readers who want to generate a design as quickly as 4) Use an initial value for secondary turns of 1 to 3 turns per
possible, the Quick Start section provides enough information volt across the secondary winding. Calculate the number
to generate an initial prototype. of bias turns, rounding to the nearest integer, according to
equation B1, using an initial estimate for the bias voltage
CV/CC Circuit Design of 20 V and VSEC(EST) = VO+VDOUT.
VBIAS
The LNK520 circuit shown in Figure B3 serves as a CV/CC NB = × NS (B1)
VSEC
charger example to illustrate design techniques. The low-side
3
5.5 V, 500 mA
L1 1 7
R1 D7 C6
1 mH 390 kΩ C4
D1 D2 0.15 A 330 pF 8T 11DQ06 330 µF
1N4005 1N4005 1/4 W 16 V
1 kV
RTN
2 6
RF1
8.2 Ω R2 100T
100 Ω J1
L 2W
D5 4
1N4007GP C3
85 - 265 26T
D6B R3 1 µF
VAC 1N4937 15 Ω 50 V
C1 C2 5
4.7 µF 4.7 µF
N 400 V 400 V LinkSwitch T1
EE16
U1 LP = 2.52 mH
D LNK520P
D3 D4 C
1N4005 1N4005
R4
S C5 6.81 k
220 nF 1%, 1/4 W
PI-3723-120203
Figure B3. Example LNK520 Schematic for a Typical LinkSwitch Charger.
3-148
Rev. D 08/06
Using the design in figure B3 as an example: VSEC = VO + VRCABLE + VDOUT + VRSEC

= VO + ( IO × RCABLE ) + VDOUT + ( ISEC ( PEAK ) × RSEC )
VBIAS
NB = × NS = 5.5 V + (0.5 A × 0.2 Ω) + 0.7 V + (3.175 A × 0.1 Ω)
VSEC ( EST )
20 V = 5.5 V + 0.1 V + 0.7 V + 0.3175 V
= ×8 (B2)
(5.5 V + 0.7 V) = 6.62 V (B4)
= 25.8 Voltage VSEC allows the exact VBIAS to be calculated:
= 26 turns
NB
VBIAS = × VSEC
Clamp, Bias, Bypass and Feedback NS
26 (B5)
An RCD clamp network is formed by RCLAMP1, CCLAMP, DCLAMP = × 6.62
8
and RCLAMP2 (Figure B1), safely limits the maximum drain
= 21.5 V
voltage to below the BVDSS of LinkSwitch.
Resistor RFB, a 1% 0.25 W resistor converts the bias voltage to
Feedback is derived from the bias winding voltage (VBIAS), that LinkSwitch bias and control current.
closely approximates the secondary winding voltage (VSEC)
multiplied by the bias winding to secondary winding turns ratio Feedback voltage VFB is calculated from VBIAS, the error due to
(NB:NS). Due to the effects of leakage inductance (VLEAK) the leakage inductance VLEAK and the voltage drop across DBIAS.
actual VSEC may be slightly different than calculated, causing an
error in the output voltage. To minimize this effect a bias The value for VLEAK varies depending on the value of the
voltage higher than the output voltage is used (limited by no- leakage inductance, the size of the filter resistor RLF and the
load consumption) and RLF together with CBIAS filter leakage forward drop of DBIAS. For the first prototype use a value of
inductance generated voltage spikes. between 0 V and 2 V for V LEAK and 1 V for V DBIAS .
The bias voltage is converted by RFB to LinkSwitch CONTROL VFB = VBIAS + VLEAK − VDBIAS (B6)
pin current for duty cycle control and bias. The CONTROL pin
capacitor CCP provides decoupling, control loop compensation, Once a prototype has been constructed, the value of VFB can
and the energy storage required during start-up and auto restart. be found directly, by measuring the voltage across CBIAS at the
power supply peak power point using a DVM. By subtracting
The location of DBIAS may be on the positive or return side of the V BIAS and V DBIAS from V FB the value for V LEAK can be
bias winding depending on if and how the bias winding is determined, useful as an estimate in future designs. For the
configured as primary side core cancellation winding. Similar design shown in Figure B3, VFB was measured as 20.7 V, giving 3
considerations apply to DOUT if a shield winding is used between VLEAK as 0.2 V.
primary and secondary windings.
An initial value for RFB is calculated from VFB, the CONTROL
Feedback Resistor (RFB) pin voltage VC(IDCT) and current I DCT, as specified in the
LinkSwitch data sheet.
To calculate the feedback resistor value the value of the feedback VFB − VC ( IDCT )
voltage must be determined. Using the schematic shown in RFB =
Figure B3 as an example. With primary turns NP = 100 and I DCT
secondary turns NS = 8 the peak secondary current can be 20.7 V − 5.75 V (B7)
=
calculated from equation B3, where IPRI(PEAK) is equal to the 2.15 mA
LinkSwitch typical current limit ILIM(TYP). = 6.9 kΩ
NP Select the nearest standard value and adjust to center the output
ISEC ( PEAK ) = × I PRI ( PEAK )
NS voltage. The example in Figure B3 uses a value of 6.81 kΩ
100 (B3) for RFB, centering the output voltage at the peak power point.
= × 0.254
8
= 3.175 A Note that RFB power dissipation should be taken into account
when calculating the no load power consumption.
The secondary diode peak voltage was measured as 0.7 V, the
2
secondary winding resistance as 0.1 Ω and the cable resistance PRFB = (2.15 mA) × RFB = 31 mW (B8)
as 0.2 Ω. Therefore VSEC is defined as:
3-149
Rev. D 08/06
Bias Filter Resistor (RLF) and Capacitor (CBIAS) Hints and Tips
Follow guidance for LNK520 with the following exceptions: Improving CV Tolerance with Optocoupler
A secondary reference and optocoupler may be added to reduce
1) The value for bias series resistor RLF is sized between 0 Ω and the CV tolerance, maintained over the full output load range.
300 Ω, depending on leakage characteristics of the Figure B4 shows an example using a Zener (VR1) as the
transformer. Larger resistor sizes are necessary to filter secondary reference. During CV operation, RFB is bypassed by
leakage spike on the bias winding but will reduce the slope U1 and the output voltage is defined by the voltage across VR1,
in the CV region. Increased RLF will result in a slight RA and the LED of U1.
reduction in auto-restart and “discharged battery” minimum
start-up voltage. Resistor RB is selected to bias VR1 close to its specified test
2) CBIAS capacitor is a 1 µF, 50 V Aluminum electrolytic type. current. It may also be used to center the output voltage.
The voltage rating is consistent with the 20-30 V maximum Resistor RA is optional and limits the current through U1 when
seen across the bias winding. This forms an effective filter there is a large output ripple.
with RLF for bias leakage voltage spikes and improves
CV/CC performance. Beyond the peak power point, the output voltage falls and no
3) DBIAS can be a signal diode such as the 1N4148 or BAV20 current flows through VR1 or U1. The power supply is therefore
with suitable voltage rating. For lower radiated EMI a in CC operation and CONTROL pin current is provided through
slower diode such as the 1N4937 may be considered, which feedback resistor RFB.
also improves regulation.
The initial value of RFB is calculated using Equation B9, the
Primary Clamp Resistors (RCLAMP1, RCLAMP2), Diode same calculation whether or not an optocoupler is used.
(DCLAMP) and Capacitor (CCLAMP) *
Appendix C:
Diode DCLAMP can be a normal, fast or ultra-fast recover type
with at least a 600 V breakdown voltage. Slow recovery diodes Low Side LinkSwitch LNK520
(1N400X) are preferred as they offer better light and no load CV Tolerance Analysis
regulation and reduce EMI. However they should be glass
passivated and used with a series resistor (RCLAMP2) to damp Output Characteristic Tolerances
ringing and prevent reverse pull out current, this also further
reduces EMI. The tolerance analysis for the LNK520 follows the same
approach as used for the LNK500/501, as described in Appendix
The clamp resistor RCLAMP1 is required to dissipate stored A. As such only a summary of the analysis is presented here,
3 leakage energy between subsequent switching cycles. highlighting differences between the LNK520 and
LNK500/501 devices. Table C1 and C2 provide the overall
CCLAMP limits the peak drain voltage and should be sized constant current tolerance values and Equation C8 provides the
between 100 and 2000 pF, 500 V. CCLAMP capacitor can be low voltage tolerance of the peak power point, for the design in
cost disc ceramic-type. As a general rule the value of the CCLAMP Figure B3.
should be minimized and the value of RCLAMP1 maximized while
still keeping the peak drain voltage (at highest line voltage) Constant Current Limit (CC)
below BVDSS. Key differences from LNK500/501 analysis.
• Primary inductance tolerance
Secondary Snubber Resistor (RSNUB) and Based on feedback from customers and transformer vendors
Capacitor (CSNUB) * the primary inductance has been reduced.
• ∆I∆V terms
A secondary diode snubber may be required to attenuate Improved regulation when using a bias winding has reduced
conducted EMI, especially in the high frequency band. CSNUB ∆I∆V terms.
should be in the range 10 and 100 pF and RSNUB between 10 and • Biases due to temperature, CC linearity and temperature
100 Ω, 1/8 Ω. Device biases have been lumped into a single term of ±7.9%.
Note: variation due to temperature has a larger negative
*Sizing of primary clamp and secondary snubber components coefficient than positive but has been centered here for
may require iterative analysis to minimize no-load consumption simplicity. In practice when optimizing the design at room
and no-load output voltage. ambient and 85 VAC the peak power point should be
adjusted to 4% higher than the desired nominal CC output
current.
3-150
Rev. D 08/06
T1 5.5 V, 0.5 A
VR1
5.1 V
2% RTN
RA
120 Ω
DBIAS RLF CBIAS RB

AC 680 Ω
Input
LinkSwitch U1
LNK520 S
U1
C
RFB
D
PI-3749-021904
Figure B4. Example of LNK520 with Optocoupler Feedback.

∆%CV = ± ∆% LINE ± ∆%VDOUT ±
2 2 2 C1
Random Biases + ∆%VC ( IDCT ) + ∆% IDCT + ∆% RFB
Variable Biases Random ∆I/∆V
+ ∆I/∆V Random
Primary
Inductance
– ±7% ±1.1% ±8.1% 6 V − 5.75 V
∆%VC ( IDCT ) = ± × 100% = ±1.25% C2
2 20 V
If – ±11% ±1.7% ±12.7%
∆VRFB( LINE ) = 0.15 mA × 6.81 kΩ = 1.02 V C3
Input Line ±3% – ±3%
CC Linearity ±7.9% ±2% – ±2% 0.025
Tj (25-65°C) ∆%VDOUT = ± × 100% = ±0.23% C4
– – – 2 × 5.5
Totals ±7.9% ±15.5% ±23.4%
1.02 V
3
Table C1. Sources of LNK520 CC Tolerance. ∆% LINE =± × 100% = ±2.55% C5
2 × 20 V
Constant Voltage Operation at Peak Power Point 2.15 mA - 2.06 mA

∆VRFB( IDCT ) = ± × 6.81 kΩ = ±0.31 V
During CV operation, the output characteristic is controlled by 2
C6
adjusting the duty cycle, based on the voltage VFB across
0.31 V
capacitor CBIAS (Figure B1). The key parameters defining the ∆% IDCT = ± × 100% = ±1.53% C7
output voltage are the same for LNK500/501 and LNK520 and 20 V
therefore the analysis provided earlier (equations A1 through The tolerance of R4 (RFB) is 1%
A7) is valid. Using the design in Figure B3 as an example and
values from the LNK520 data sheet parametric table:
∆%CV = ±2.55% ± 0.23% ± (1.46 2 2
+ 1.53 + 1
2
)
= ±2.55% ± 0.23% ± 2.34% C8
= ±5.12%
Revision Notes Date
A – 8/02
B 1) Added support for LNK500. 4/03
C 1) Added support for LNK520. 3/04
D 1) Corrected Table 2 to indicate Figure B2. 8/06
3-151
Rev. D 08/06
®
LinkSwitch-TN
Design Guide
Introduction • Universal input – the same power supply/product can be

used worldwide
LinkSwitch-TN combines a high voltage power MOSFET switch • High power density – smaller size, no µF’s of X class
with an ON/OFF controller in one device. It is completely self- capacitance needed
powered from the DRAIN pin, has a jittered switching frequency • High efficiency – full load efficiencies >75% typical for
for low EMI and is fully fault protected. Auto-restart limits 12 V output
device and circuit dissipation during overload and output short • Excellent line and load regulation
circuit (LNK304-306) while over temperature protection • High efficiency at light load – ON/OFF control maintains
disables the internal MOSFET during thermal faults. The high high efficiency even at light load
thermal shutdown threshold is ideal for applications where the • Extremely energy efficient – input power <100 mW at no
ambient temperature is high while the large hysteresis protects load
the PCB and surrounding components from high average • Entirely manufacturable in SMD
temperatures. • More robust to drop test mechanical shock
• Fully fault protected (overload, short circuit and thermal
LinkSwitch-TN is designed for any application where a non- faults)
isolated supply is required such as appliances (coffee machines, • Scalable – LinkSwitch-TN family allows the same basic
rice cookers, dishwashers, microwave ovens etc.), nightlights, design to be used from <50 mA to 360 mA
emergency exit signs and LED drivers. LinkSwitch-TN can be
configured in all common topologies to give a line or neutral Scope
referenced output and an inverted or non-inverted output
voltage – ideal for applications using triacs for AC load control. This application note is for engineers designing a non-isolated
Using a switching power supply rather than a passive dropper power supply using the LinkSwitch-TN family of devices. This
(capacitive or resistive) gives a number of advantages, some of document describes the design procedure for buck and buck-
which are listed below.
3 RFB DFB
CBP
RBIAS CFB
RF DIN2 LIN FB BP
D S L +
AC LinkSwitch-TN
Input DFW CO RPL VO
DIN2 CIN1 CIN2
PI-3764-121003
1 (a)
RFB DFB
CBP
RBIAS CFB
RF DIN1 LIN FB BP
D S
DFW
AC LinkSwitch-TN L
CO RPL VO
Input DIN2 CIN1 CIN2 +
PI-3765-121003
1 (b)
Figure 1 (a). Basic Configuration using LinkSwitch-TN in a Buck Converter. Figure 1 (b) Basic Configuration using LinkSwitch-TN in a
Buck-Boost Converter.
3-152
Rev. E 05/05
boost converters using the LinkSwitch-TN family of integrated Quick Start

off-line switchers. The objective of this document is to provide
power supply engineers with guidelines in order to enable them Readers wanting to start immediately can use the following
to quickly build efficient and low cost buck or buck-boost information to quickly select the components for a new design,
converter based power supplies using low cost off-the-shelf using Figure 1 and Tables 1 and 2 as references.
inductors. Complete design equations are provided for the
selection of the converter’s key components. Since the power 1) For AC input designs select the input stage (Table 9).
MOSFET and controller are integrated into a single IC the 2) Select the topology (Tables 1 and 2).
design process is greatly simplified, the circuit configuration - If better than ±10% output regulation is required,
has few parts and no transformer is required. Therefore a quick then use optocoupler feedback with suitable reference.
start section is provided that allows off-the-shelf components to 3) Select the LinkSwitch-TN device, L, RFB or VZ, RBIAS, CFB,
be selected for common output voltages and currents. RZ and the reverse recovery time for DFW
(Table 4: Buck, Table 5: Buck-Boost).
In addition to this application note a design spreadsheet is 4) Select freewheeling diode to meet trr determined in Step 3
available within the PIXls tool in the PI Expert design software (Table 3).
suite. The reader may also find the LinkSwitch-TN DAK 5) For direct feedback designs, if the minimum load < 3 mA
engineering prototype board useful as an example of a working then calculate RPL = VO / 3 mA.
supply. Further details of support tools and updates to this 6) Select CO as 100 µF, 1.25 • VO, low ESR type.
document can be found at www.powerint.com. 7) Construct prototype and verify design.
High-Side 1) Output referenced to input

Buck – 2) Positive output (VO) with respect to -VIN
Direct FB BP
3) Step down – VO < VIN
Feedback D S
4) Low cost direct feedback (±10% typ.)
+ +
LinkSwitch-TN
VIN VO
PI-3751-121003
High-Side 1) Output referenced to input 3

Buck-Boost – 2) Negative output (VO) with respect to -VIN
Direct 3) Step down – VO > VIN or VO < VIN
Feedback FB BP 4) Low cost direct feedback (±10% typ.)
+ D S 5) Fail-safe – output is not subjected to input
VIN
LinkSwitch-TN
VO
+ 6) Ideal for driving LEDs – better accuracy and
PI-3794-121503 temperature stability than low-side buck
constant current LED driver
Notes
1. Low cost, directly sensed feedback typically achieves overall regulation tolerance of ±10%.
2. To ensure output regulation, a pre-load may be required to maintain a minimum load current of 3 mA (buck and buck-boost only).
3. Boost topology (step up) also possible but not shown.
Table 1. LinkSwitch-TN Circuit Configurations Using Directly Sensed Feedback.
3-153
Rev. E 05/05
High-Side 1) Output referenced to input

Buck – FB BP 2) Positive output (VO) with respect to -VIN
Optocoupler + D S +
3) Step down – VO < VIN
Feedback LinkSwitch-TN RZ 4) Optocoupler feedback
VIN VO - Accuracy only limited by reference choice
VZ
- Low cost non-safety rated optocoupler
- No pre-load required
PI-3796-121903 5) Minimum no-load consumption
Low-Side + + 1) Output referenced to input

Buck – RZ 2) Negative output (VO) with respect to +VIN
LinkSwitch-TN
Optocoupler 3) Step down – VO < VIN
VIN VO
Feedback 4) Optocoupler feedback
VZ - Accuracy only limited by reference choice
BP FB
- Low cost non-safety rated optocoupler
S D
PI-3797-121903 - No pre-load required
Low-Side + 1) Output referenced to input

Buck-Boost – VZ 2) Positive output (VO) with respect to +VIN
Optocoupler LinkSwitch-TN 3) Step up/down – VO > VIN or VO < VIN
VIN VO
Feedback 4) Optocoupler feedback
RZ - Accuracy only limited by reference choice
BP FB + - Low cost non-safety rated optocoupler
D
S
PI-3798-121903 - No pre-load required
5) Fail-safe – output is not subjected to input
6) Minimum no-load consumption
Notes
1. Performance of opto feedback only limited by accuracy of reference (Zener or IC).
2. Optocoupler does not need to be safety approved.
3 3. Reference bias current provides minimum load. The value of RZ is determined by Zener test current or reference IC bias current,
typically 470 Ω to 2 kΩ, 1/8 W, 5%.
4. Boost topology (step-up) is also possible but not shown.
5. Optocoupler feedback provides lowest no-load consumption.
Table 2. LinkSwitch-TN Circuit Configurations Using Optocoupler Feedback.
VRRM IF t rr
PART NO. PACKAGE MANUFACTURER
(V) (A) (ns)
MUR160 600 1 50 Leaded Vishay
Leaded
UF4005 600 1 75 Vishay
Leaded
BYV26C 600 1 30 Leaded Vishay/Philips
Leaded
FE1A 600 1 35 Vishay
SMD
STTA10 6 600 1 20 ST Microelectronics
SMD
STTA10 6U 600 1 20 ST Microelectronics
US1J 600 1 75 Vishay
Table 3. List of Ultra-Fast Diodes Suitable for Use as the Freewheeling Diode.
3-154
Rev. E 05/05
INDUCTOR
VOUT IOUT(MAX) LNK30X MODE DIODE tr r RFB* VZ
µH IRMS (mA) TOKIN COILCRAFT
65 1200 70 - RFB0807-122 MDCM 75 ns
LNK302
80 1200 80 - RFB0807-122 CCM 35 ns
120 680 220 SBC2-681-211 RFB0807-681 MDCM 75 ns
5 160 680 230 SBC2-681-211 RFB0807-681 LNK304 CCM 35 ns
3.84 kΩ 3.9 V
175 680 320 SBC3-681-211 RFB0810-681 MDCM 75 ns
225 680 340 SBC4-681-211 RFB0810-681 LNK305 CCM 35 ns
280 680 440 SBC4-681-211 RFB0810-681 MDCM 75 ns
360 680 430 SBC4-681-211 RFB0810-681 LNK306 CCM 35 ns
60 1800 70 - RFB0807-222 MDCM 75 ns
LNK302
80 2700 80 - RFB0807-272 CCM 35 ns
85 680 180 SBC2-681-211 RFB0807-681 MDCM 75 ns
120 1000 230 SBC3-102-281 RFB0807-102 LNK304 MDCM 75 ns
12 160 1500 320 SBC3-152-251 RFB0810-152 CCM 35 ns 11.86 kΩ 11 V
225 1000 440 SBC4-102-291 RFB0810-102 CCM 35 ns
280 680 430 SBC4-681-431 RFB0810-681 MDCM 75 ns
LNK306
360 1500 400 SBC6-152-451 RFB1010-152 CCM 35 ns
65 2200 70 SBC3-222-191 RFB0807-222 MDCM 75 ns
LNK302
80 3300 80 SBC3-332-151 RFB0807-332 CCM 35 ns
70 680 160 SBC2-681-211 RFB0807-681 MDCM 75 ns
120 1200 210 - RFB0807-122 LNK304 MDCM 75 ns
15 160 1800 210 - RFB0810-182 CCM 35 ns 15.29 kΩ 13 V
175 820 310 - RFB0810-821 MDCM 75 ns
225 1200 310 - RFB1010-122 LNK305
CCM 35 ns
280 820 390 - RFB1010-821 MDCM 75 ns
360 1500 390 SBC6-152-451 RFB1010-152 LNK306
CCM 35 ns
65 3300 70 SBC3-332-151 RFB0807-332 MDCM 75 ns
LNK302 CCM 35 ns
80 4700 80 SBC3-472-181 RFB0807-472
50 680 130 SBC2-681-211 RFB0807-681 MDCM 75 ns 3
24 160 2200 180 SBC4-222-211 RFB0810-222 35 ns 25.6 kΩ 22 V
CCM
175 1200 280 - RFB0810-122 MDCM 75 ns
225 1500 280 SBC6-152-451 RFB1010-152 LNK305
CCM 35 ns
280 1200 350 - RFB1010-122 MDCM 75 ns
360 2200 360 SBC6-222-351 - LNK306
CCM 35 ns
Other Standard Components
RBIAS: 2 kΩ, 1%, 1/8 W
CBP: 0.1 µF, 50 V Ceramic
CFB: 10 µF, 1.25 • VO
DFB: 1N4005GP
RZ: 470 Ω to 2 kΩ, 1/8 W, 5%
Table 4. Components Quick Select for Buck Converters. *Select nearest standard or combination of standard values.
3-155
Rev. E 05/05
INDUCTOR
VOUT IOUT(MAX) LNK30X MODE DIODE trr RFB* VZ
µH IRMS (mA) TOKIN COILCRAFT
65 1200 70 - RFB0807-122 MDCM 75 ns
LNK302
80 1500 80 SBC3-152-251 RFB0807-152 CCM 35 ns
160 680 230 SBC2-681-211 RFB0807-681 CCM 35 ns
5 3.84 kΩ 3.9 V
225 680 320 SBC4-681-431 RFB0810-681 CCM 35 ns
280 680 440 SBC4-681-431 RFB0810-681 MDCM 75 ns
LNK306
360 680 430 SBC4-681-431 RFB0810-681 CCM 35 ns
55 2200 70 SBC3-222-191 RFB0807-222 MDCM 75 ns
LNK302
80 3300 90 SBC3-332-151 RFB0807-332 CCM 35 ns
70 680 180 SBC2-681-211 RFB0807-681 MDCM 75 ns
120 1200 220 - RFB1010-122 LNK304 MDCM 75 ns
12 160 1800 210 - RFB0807-182 CCM 35 ns 11.86 kΩ 11 V
175 820 320 - RFB0807-821 MDCM 75 ns
LNK305
225 1200 310 - RFB0810-122 CCM 35 ns
280 820 410 - RFB0810-821 MDCM 75 ns
360 1800 410 - RFB1010-182 LNK306 35 ns
CCM
55 2200 70 SBC3-222-191 RFB0807-222 MDCM 75 ns
LNK302
80 3900 90 - RFB0807-392 CCM 35 ns
50 680 180 SBC2-681-211 RFB0807-681 MDCM 75 ns
15 160 2200 220 SBC4-222-211 RFB0810-222 CCM 35 ns 15.29 kΩ 13 V
175 1000 320 SBC4-102-291 RFB0810-102 MDCM 75 ns
225 1500 320 SBC4-152-251 RFB0810-152 LNK305 35 ns
CCM
280 1200 400 - RFB0810-122 MDCM 75 ns
360 2200 410 SBC6-222-351 RFB1010-222 LNK306
CCM 35 ns
45 3300 70 SBC3-332-151 RFB0807-332 MDCM 75 ns
LNK302 CCM 35 ns
80 6800 100 SBC3-682-111 RFB0807-682
3 35 680 180 SBC2-681-211 RFB0807-681
LNK304
MDCM
MDCM
75 ns
75 ns
120 2200 210 SBC3-222-191 RFB0810-222
24 160 3300 210 SBC4-332-161 RFB0810-332 CCM 35 ns 25.6 kΩ 22 V
175 1800 300 - RFB0810-182 MDCM 75 ns
LNK305
225 2200 290 SBC4-222-211 RFB1010-222 CCM 35 ns
280 1800 370 - RFB1010-182 MDCM 75 ns
LNK306
360 3300 410 - - CCM 35 ns
Other Standard Components

RBIAS: 2 kΩ, 1%, 1/8 W
CBP: 0.1 µF, 50 V Ceramic
CFB: 10 µF, 1.25 • VO
DFB: 1N4005GP
RZ: 470 Ω to 2 kΩ, 1/8 W, 5%
Table 5. Components Quick Select for Buck-Boost Converters. *Select nearest standard or combination of standard values.
3-156
Rev. E 05/05
LinkSwitch-TN Circuit Design To regulate the output, an ON/OFF control scheme is used as
illustrated in Table 6. As the decision to switch is made on a
LinkSwitch-TN Operation cycle-by-cycle basis, the resultant power supply has extremely
good transient response and removes the need for control loop
The basic circuit configuration for a buck converter using compensation components. If no feedback is received for
LinkSwitch-TN is shown in Figure 1(a). 50 ms, then the supply enters auto-restart (LNK304-306 only).
Reference = MOSFET
FB BP Enabled
Schematic D S
+ +
and Key LinkSwitch-TN
VIN VO = MOSFET
Disabled -
Cycle Skipped
PI-3784-121603
ID
At the beginning of each cycle, the
FEEDBACK (FB) pin is sampled.
• If IFB < 49 µA then next cycle occurs
• If IFB > 49 µA then next switching cycle
Is IFB is skipped
>49 µA? No No Yes No No Yes Yes No
Normal
Operation
High load – few cycles skipped
Low load – many cycles skipped 3

PI-3767-121903
IFB < 49 µA, > 50 ms

Auto-Restart = Auto-Restart If no feedback (IFB < 49 µA) for > 50 ms,
(LNK304-306 then output switching is disabled for
only) approximately 800 ms.
50 ms 800 ms
Auto-Restart = 50 ms ON / 800 ms OFF
PI-3768-083004
Table 6. LinkSwitch-TN Operation.
3-157
Rev. E 05/05
To allow direct sensing of the output voltage without the need freewheeling diode and the average current through the output
for a reference (Zener diode or reference IC), the FB pin voltage inductor are slightly lower in the buck topology as compared to
is tightly toleranced over the entire operating temperature the buck-boost topology.
range. For example, this allows a 12 V design with an overall
output tolerance of ±10%. For higher performance, an opto- Selecting the Operating Mode –
coupler can be used with a reference as shown in Table 2. Since MDCM and CCM Operation
the optocoupler just provides level shifting, it does not need to
be safety rated or approved. The use of an optocoupler also At the start of a design, select between mostly discontinuous
allows flexibility in the location of the device, for example it conduction mode (MDCM) and continuous conduction mode
allows a buck converter configuration with the LinkSwitch-TN (CCM) as this decides the selection of the LinkSwitch-TN
in the low-side return rail, reducing EMI as the SOURCE pins device, freewheeling diode and inductor. For maximum output
and connected components are no longer part of the switching current select CCM, for all other cases MDCM is recommended.
node. Overall, select the operating mode and components to give the
lowest overall solution cost. Table 7 summarizes the trade-offs
Selecting the Topology between the two operating modes.
If possible, use the buck topology. The buck topology maximizes Additional differences between CCM and MDCM include
the available output power from a given LinkSwitch-TN and better transient response for DCM and lower output ripple (for
inductor value. Also, the voltage stress on the power switch and same capacitor ESR) for CCM. However these differences, at
COMPARISON OF CCM AND MDCM OPERATING MODES

OPERATING MODE MDCM CCM
IL
IL
IO IO
Operating
Description
t t
tON tOFF tIDLE tON tOFF
3 PI-3769-121803 PI-3770-121503
Inductor current falls to zero during tOFF, Current flows continuously in the inductor for
borderline between MDCM and CCM when the entire duration of a switching cycle.
tIDLE = 0.
Lower Cost Higher Cost
Inductor
Lower value, smaller size. Higher value, larger size.
Lower Cost
Freewheeling Higher Cost
75 ns ultra-fast reverse recovery type
Diode 35 ns ultra-fast recovery type required.
( 35 ns for ambient >70 °C).
Potentially Higher Cost Potentially Lowest Cost
LinkSwitch-TN May require larger device to deliver required May allow smaller device to deliver required
output current–depends on required output output current–depends on required output
current. current.
Higher Efficiency Lower Efficiency
Efficiency
Lower switching losses. Higher switching losses.
Overall Typically Higher Cost
Table 7. Comparison of Mostly Discontinuous Conduction (MDCM) and Continuous Conduction (CCM) Modes of Operation.
3-158
Rev. E 05/05
the low output currents of LinkSwitch-TN applications, are Output Power, PO: in Watts.
normally not significant. Power supply efficiency, η: 0.7 for a 12 V output, 0.55 for a
5 V output if no better reference data available.
The conduction mode CCM or MDCM of a buck or buck-boost
converter primarily depends on input voltage, output voltage,
Total Capacitance CIN(TOTAL)
output current and device current limit. The input voltage,
µF/POUT (CIN1 + CIN2)
output voltage and output current are fixed design parameters,
therefore the LinkSwitch-TN (current limit) is the only design AC Input Half Wave Full Wave
parameter that sets the conduction mode. Voltage (VAC) Rectification Rectification
100/115 6-8 3-4
The phrase “mostly discontinuous” is used as with on-off 230 1-2 1
control, since a few switching cycles may exhibit continuous
Universal 6-8 3-4
inductor current, the majority of the switching cycles will be in
the discontinuous conduction mode. A design can be made Table 10. Suggested Total Input Capacitance Values for Different
fully discontinuous but that will limit the available output Input Voltage Ranges.
current, making the design less cost effective.
Step 2 – Determine AC Input Stage
Step-by-Step Design Procedure
The input stage comprises fusible resistor(s), input rectification
Step 1 – Determine System Requirements VACMIN, diodes and line filter network. The fusible resistor should be
VACMAX, PO, VO, fL, η chosen as flameproof and, depending on the differential line
input surge requirements, a wire-wound type may be required.
Determine the input voltage range from Table 8. The fusible resistor(s) provides fuse safety, inrush current
limiting and differential mode noise attenuation.
Input (VAC) VACMIN VACMAX
100/115 85 132 For designs ≤1 W, it is lower cost to use half-wave rectification;
>1 W, full wave rectification (smaller input capacitors). The
230 195 265 EMI performance of half-wave rectified designs is improved by
Universal 85 265 adding a second diode in the lower return rail. This provides
Table 8. Standard Worldwide Input Line Voltage Ranges. EMI gating (EMI currents only flow when the diode is
conducting) and also doubles differential surge withstand as the
Line Frequency, fL: 50 or 60 Hz, for half-wave rectification surge voltage is shared across two diodes. Table 9 shows the
use fL/2. recommended input stage based on output power for a universal
Output Voltage, VO: in Volts. input design while Table 10 shows how to adjust the input 3
capacitance for other input voltage ranges.
POUT 0.25 W 0.25-1 W >1W

DIN1-4
+ + RF1 DIN1
LIN + LIN +
RF1 DIN1 RF1 DIN1 RF2 RF1
AC **
CIN AC **
CIN1 CIN2 AC **
CIN1 CIN2 AC IN **
IN IN IN CIN1 CIN2
*
RF2 DIN2* DIN2* DIN2*
85-265 VAC PI-3771-121603 PI-3772-121603 PI-3773-121603 PI-3774-121603
Input Stage
RF1, RF2: 100-470 Ω, RF1: 8.2 Ω, 1 W Fusible RF1: 8.2 Ω, 1 W Fusible RF1: 8.2 Ω, 1 W Fusible
0.5 W, Fusible RF2: 100 Ω, 0.5 W, LIN: 470 µH-2.2 mH, LIN: 470 µH-2.2 mH,
CIN: 2.2 µF, 400 V Flameproof 0.05 A-0.3 A 0.05 A-0.3 A
DIN1, DIN2: 1N4007, 1 A, CIN1, CIN2: 3.3 µF, CIN1, CIN2: 4 µF/WOUT, CIN1, CIN2: 2 µF/WOUT,
1000 V 400 V each 400 V each 400 V each
DIN1, DIN2: 1N4007, 1 A, DIN1, DIN2: 1N4007, 1 A, DIN1, DIN2: 1N4005, 1 A,
1000 V 1000 V 600 V
*Optional for improved EMI and line surge performance. Remove for designs requiring no impedance in return rail.
Comments **Increase value to meet required differential line surge performance.
Table 9. Recommended AC Input Stages For Universal Input.
3-159
Rev. E 05/05
Step 3 – Determine Minimum and Maximum DC Step 5 – Select the Output Inductor
Input Voltages VMIN and VMAX Based on AC Input
Voltage Tables 4 and 5 provide inductor values and RMS current ratings
for common output voltages and currents based on the
Calculate VMAX as calculations in the design spreadsheet. Select the next nearest
higher voltage and/or current above the required output
VMAX = 2 ⋅ VACMAX (1) specification. Alternatively, the PIXls spreadsheet tool in the
PI Expert software design suite or Appendix A can be used to
Assuming that the value of input fusible resistor is small, the calculate the exact inductor value (Eq. A7) and RMS current
voltage drop across it can be ignored. rating (Eq. A21).
Assume bridge diode conduction time of tc = 3 ms if no other It is recommended that the value of inductor chosen should be
data available. closer to LTYP rather than 1.5 • LTYP due to lower DC resistance
and higher RMS rating. The lower limit of 680 µH limits the
Derive minimum input voltage VMIN maximum di/dt to prevent very high peak current values.
Tables 3 and 4 provide reference part numbers for standard
inductors from two suppliers.
⎛ 1 ⎞
2 ⋅ PO ⎜ − tC ⎟
⎝ 2 ⋅ fL ⎠ (2) 680 µH < LTYP < L < 1.5 ⋅ LTYP (5)
VMIN = (2 ⋅ VACMIN 2 ) −
η ⋅ C IN ( TOTAL )
For LinkSwitch-TN designs, the mode of operation is not
If VMIN is ≤70 V then increase value of CIN(TOTAL). dependent on the inductor value. The mode of operation is a
function of load current and current limit of the chosen device.
Step 4 – Select LinkSwitch-TN Device Based on The inductor value merely sets the average switching frequency.
Output Current and Current Limit
Figure 2 shows a typical standard inductor manufacturer’s data
Decide on the operating mode - refer to Table 7. sheet. The value of off-the-shelf “drum core / dog bone / I core”
inductors will drop up to 20% in value as the current increases.
For MDCM operation, the output current (IO) should be less The constant KL_TOL in equation (A7) and the design spreadsheet
than or equal to half the value of the minimum current limit of adjusts for both this drop and the initial inductance value
the chosen device from the data sheet. tolerance.
I LIMIT _ MIN > 2 ⋅ IO (3) For example if a 680 µH, 360 mA inductor is required, referring
3 to Figure 2, the tolerance is 10% and an estimated 9.5% for the
For CCM operation, the device should be chosen such that the reduction in inductance at the operating current (approximately
output current IO, is more than 50%, but less than 80% of the [0.36/0.38] • 10). Therefore the value of KL_TOL = 1.195 (19.5%).
minimum current limit ILIMIT_MIN.
If no data is available, assume a KL_TOL of 1.15 (15%).
0.5 ⋅ I LIMIT _ MIN < IO < 0.8 ⋅ I LIMIT _ MIN (4) Not all the energy stored in the inductor is delivered to the load,
due to losses in the inductor itself. To compensate for this, a loss
Please see the data sheet for LinkSwitch-TN current limit values.
Inductance and Current Rating Current Rating Current Rating

Tolerance for 20 °C Rise for 40 °C Rise for Value -10%
SBC3 Series (SBC3- - )
Inductance Rdc Rated Current Current (Reference Value)
Model (Ω) (A) (A)
L(mH/ at 10 kHz max. ∆T = 20 °C ∆T = 40 °C L change rate -10%
681-361 680±10% 1.62 0.36 0.50 0.38
102-281 1000±10% 2.37 0.28 0.39 0.31
152-251 1500±10% 3.64 0.25 0.35 0.26
222-191 2200±10% 5.62 0.19 0.26 0.21
332-151 3300±10% 7.66 0.15 0.21 0.17
PI-3783-121404
Figure 2. Example of Standard Inductor Data Sheet.
3-160
Rev. E 05/05
factor KLOSS is used. This has a recommended value of between Let the value of RBIAS = 2 kΩ; this biases the feedback network
50% and 66% of the total supply losses as given by Equation 6. at a current of ∼0.8 mA. Hence the value of RFB is given by
For example, a design with an overall efficiency (η) of 0.75
would have a KLOSS value of between 0.875 and 0.833. VO − VFB (V − VFB ) ⋅ RBIAS = (VO − 1.65 V) ⋅ 2 kΩ
RFB = = O
+ I FB VFB + ( I FB ⋅ RBIAS )
VFB 1.748 V
⎛ (1 − η) ⎞ ⎛ 2(1 − η) ⎞ RBIAS
K LOSS = 1 − ⎜ ⎟ to 1 − ⎜ ⎟ (6) (10)
⎝ 2 ⎠ ⎝ 3 ⎠
Step 9 – Select the Feedback Diode and Capacitor
Step 6 – Select Freewheeling Diode
For the feedback capacitor, use a 10 µF general purpose
For MDCM operation at tAMB ≤70 °C, select an ultra-fast diode electrolytic capacitor with a voltage rating ≥1.25 • VO.
with trr ≤75 ns. At tAMB >70 °C, trr ≤ 35 ns.
For the feedback diode, use a glass passivated 1N4005GP or
For CCM operation, select an ultra-fast diode with trr ≤35 ns. 1N4937GP device with a voltage rating of ≥1.25 • VMAX.
Allowing 25% design margin for the freewheeling diode, Step 10 – Select Bypass Capacitor
VPIV > 1.25 ⋅ VMAX (7) Use 0.1 µF, 50 V ceramic capacitor.
The diode must be able to conduct the full load current. Thus Step 11 – Select Pre-load Resistor
I F > 1.25 ⋅ IO (8) For direct feedback designs, if the minimum load <3 mA, then
calculate RPL = VO / 3 mA.
Table 3 lists common freewheeling diode choices.
Other information
Step 7 – Select Output Capacitor
Startup Into Non-Resistive Loads
The output capacitor should be chosen based on the output
voltage ripple requirement. Typically the output voltage ripple If the total system capacitance is >100 µF or the output voltage
is dominated by the capacitor ESR and can be estimated as: is >12 V, then during startup the output may fail to reach
regulation within 50 ms, triggering auto-restart operation. This
VRIPPLE
ESRMAX = (9) may also be true when the load is not resistive, for example, the
I LIMIT output is supplying a motor or fan. This is not applicable for the 3
where VRIPPLE is the maximum output ripple specification and LNK302 as it does not have the auto-restart function.
ILIMIT is the LinkSwitch-TN current limit. The capacitor ESR
value should be specified approximately at the switching To increase the startup time, a soft-start capacitor can be added
frequency of 66 kHz. across the feedback resistor, as shown in Figure 3. The value of
this soft-start capacitor is typically in the range of 0.47 µF to
Capacitor values above 100 µF are not recommended as they 47 µF with a voltage rating of 1.25 • VO. Figure 4 shows the effect
can prevent the output voltage from reaching regulation during of CSS used on a 12 V, 150 mA design driving a motor load.
the 50 ms period prior to auto-restart. If more capacitance is
required, then a soft-start capacitor should be added (see Other
Information section). CSS
Step 8 – Select the Feedback Resistors RFB
The values of RFB and RBIAS are selected such that, at the FB BP
regulated output voltage, the voltage on the FEEDBACK pin D S
+ +
(VFB) is 1.65 V. This voltage is specified for a FEEDBACK pin LinkSwitch-TN
VIN VO
current (IFB) of 49 µA.
PI-3775-121003
Figure 3. Example Schematic Showing Placement of Soft-Start

Capacitor.
3-161
Rev. E 05/05
14
PI-3785-010504
12 No soft-start capacitor. Output
never reaches regulation (in FB BP
auto-restart). +7 V
10 + D S
VIN LinkSwitch-TN 6.8 V

8
Voltage (V)
RTN
6
5.1 V
4
-5 V
PI-3776-083004
2
0 Figure 5. Example Circuit – Generating Dual Output Voltages.

-2
0 2.5 5 Generating Negative and Positive Outputs
Time (s)
14 In appliance applications there is often a requirement to generate

PI-3786-010504
both an AC line referenced positive and negative output. This

12 can be accomplished using the circuit in Figure 5. The two
Zener diodes have a voltage rating close to the required output
10
voltage for each rail and ensure that regulation is maintained
8 when one rail is lightly and the other heavily loaded. The
Voltage (V)
LinkSwitch-TN circuit is designed as if it were a single output

6 voltage with an output current equal to the sum of both outputs.
4 The magnitude sum of the output voltages in this example being
Soft-start capacitor value too
small – output still fails to reach 12 V.
2 regulation before auto-restart.
Constant Current Circuit Configuration (LED Driver)

0
-2 The circuit shown in Figure 6 is ideal for driving constant

0 2.5 5 current loads such as LEDs. It uses the tight tolerance and
Time (s) temperature stable FEEDBACK pin of LinkSwitch-TN as the
3 14
reference to provide an accurate output current.
PI-3787-010503
12
RFB
10 300 Ω
Optional
Correct value of soft-start See Text
capacitor – output reaches VRFB DFB
8 RBIAS
Voltage (V)
regulation before auto-restart.

2 kΩ
FB BP RSENSE IO
6 D S
+ DFW
LinkSwitch-TN
4 CSENSE
VIN L
CO
2
0 PI-3795-072204
-2
Figure 6. High-Side Buck-Boost Constant Current Output
0 2.5 5 Configuration.
Time (s)
To generate a constant current output, the average output
current is converted to a voltage by resistor RSENSE and capacitor
Figure 4. Example of Using a Soft-Start Capacitor to Enable
Driving a 12 V, 0.15 A Motor Load. All Measurements CSENSE and fed into the FEEDBACK pin via RFB and RBIAS.
were made at 85 VAC (Worst Case Condition).
With the values of RBIAS and RFB as shown, the value of RSENSE
should be chosen to generate a voltage drop of 2 V at the
3-162
Rev. E 05/05
required output current. Capacitor CSENSE filters the voltage Recommended Layout Considerations
across RSENSE, which is modulated by inductor ripple current.
The value of CSENSE should be large enough to minimize the Traces carrying high currents should be as short in length and
ripple voltage, especially in MDCM designs. A value of CSENSE thick in width as possible. These are the traces which connect
is selected such that the time constant (t) of RSENSE and CSENSE is the input capacitor, LinkSwitch-TN, inductor, freewheeling
greater than 20 times that of the switching period (15 µs). The diode, and the output capacitor.
peak voltage seen by CSENSE is equal to RSENSE • ILIMIT(MAX).
Most off-the-shelf inductors are drum core inductors or dog-
The output capacitor is optional; however with no output bone inductors. These inductors do not have a good closed
capacitor the load will see the full peak current (ILIMIT) of the magnetic path, and are a source of significant magnetic coupling.
selected LinkSwitch-TN. Increase the value of CO (typically in They are a source of differential mode noise and, for this reason,
the range of 100 nF to 10 uF) to reduce the peak current to an they should be placed as far away as possible from the AC input
acceptable level for the load. lines.
If the load is disconnected, feedback is lost and the large output Appendix A:
voltage which results may cause circuit failure. To prevent this,
a second voltage control loop, DFB and VRFB, can be added as Calculations for Inductor Value for Buck
shown if Figure 6. This also requires that CO is fitted. The and Buck-Boost Topologies
voltage of the Zener is selected as the next standard value above
the maximum voltage across the LED string when it is in There is a minimum value of inductance that is required to
constant current operation. deliver the specified output power, regardless of line voltage
and operating mode.
The same design equations / design spreadsheet can be used as
for a standard buck-boost design, with the following additional VIN-VO
considerations.
VL
1. VO = LED VF • Number of LEDs per string
2. IO = LED IF • Number of strings t
3. Lower efficiency estimate due to RSENSE losses (enter
RSENSE into design spreadsheet as inductor resistance) VO
4. Set RBIAS = 2 kΩ and RFB = 300 Ω

5. RSENSE = 2/IO ILimit
6. CSENSE = 20 • (15 µs/RSENSE) IL
7. Select CO based on acceptable output ripple current IO

3
through the load t
8. If the load can be disconnected or for additional fault
protection, add voltage feedback components DFB and tON tOFF tIDLE PI-3778-121803
VRFB, in addition to CO. Figure 7. Inductor Voltage and Inductor Current of a Buck
Converter in DCM.
Thermal Environment
As a general case, Figure 7 shows the inductor current in
To ensure good thermal performance, the SOURCE pin discontinuous conduction mode (DCM). The following
temperature should be maintained below 100 °C, by providing expressions are valid for both CCM as well as DCM operation.
adequate heatsinking. There are three unique intervals in DCM as can be seen from
Figure 7. Interval tON is when the LinkSwitch-TN is ON and the
For applications with high ambient temperature (>50 °C), it is freewheeling diode is OFF. Current ramps up in the inductor
recommended to build and test the power supply at the maximum from an initial value of zero. The peak current is the current limit
operating ambient temperature and ensure that there is adequate ILIMIT of the device. Interval tOFF is when the LinkSwitch-TN is
thermal margin. The figures for maximum output current OFF and the freewheeling diode is ON. Current ramps down to
provided in the data sheet correspond to an ambient temperature zero during this interval. Interval tIDLE is when both the
of 50 °C and may need to be thermally derated. Also, it is LinkSwitch-TN and freewheeling diode are OFF, and the inductor
recommended to use ultra-fast (≤35 ns) low reverse recovery current is zero.
diodes at higher operating temperatures (>70 °C).
3-163
Rev. E 05/05
In CCM, this idle state does not exist and thus tIDLE = 0. ⎛1⋅ I I RIPPLE ⋅ LMIN ⎞
⎜2
( LIMIT _ MIN + I INITIAL ) VMIN − VDS − VO ⎟
1
Neglecting the forward voltage drop of the freewheeling diode, IO = ⎜ ⎟
TSW _ MAX ⎜+ 1 ⋅ I I RIPPLE ⋅ LMIN ⎟
we can express the current swing at the end of interval tON in a (
⎜ 2 LIMIT _ MIN
⎝
+ I INITIAL ) VO ⎟
⎠
buck converter as
(A5)
VMIN − VDS − VO
∆I (tON ) = I RIPPLE = ⋅ tON
LMIN 2 ⋅ (VO ⋅ IO ) ⋅ (VMIN − VDS − VO )
LMIN =
(
I RIPPLE = 2 ⋅ I LIMIT _ MIN − IO ) t IDLE = 0 ( for CCM ) ( I LIMIT _ MIN 2 − I INITIAL 2 ) ⋅ FSMIN ⋅ (VMIN − VDS )
I RIPPLE = I LIMIT _ MIN , t IDLE > 0 ( for DCM ) (A6)
(A1) For output voltages greater than 20 V, use VMAX for calculation
of LMIN (Equation A6). For output voltages less than 20 V, use
where VMIN for calculation of LMIN to compensate for current limit
IRIPPLE = Inductor ripple current delay time overshoot.
ILIMIT_MIN = Minimum current limit
VMIN = Minimum DC bus voltage This however does not account for the losses within the inductor
VDS = On state drain to source voltage drop (resistance of winding and core losses) and the freewheeling
VO = Output voltage diode, which will limit the maximum power delivering capability
LMIN = Minimum inductance and thus reduce the maximum output current. The minimum
inductance must compensate for these losses in order to deliver
specified full load power. An estimate of these losses can be
Similarly, we can express the current swing at the end of made by estimating the total losses in the power supply, and
interval tOFF as then allocating part of these losses to the inductor and diode.
VO This is done by the loss factor KLOSS which increases the size of
∆I (tOFF ) = I RIPPLE = ⋅ tOFF (A2) the inductor accordingly.
LMIN
The initial current through the inductor at the beginning of each Furthermore, typical inductors for this type of application are
switching cycle can be expressed as bobbin core or dog bone chokes. The specified current rating
refer to a temperature rise of 20 °C or 40 °C and to an inductance
I INITIAL = I LIMIT _ MIN − I RIPPLE (A3) drop of 10%. We must incorporate an inductance tolerance
factor KL_TOL within the expression for minimum inductance, to
3 The average current through the inductor over one switching account for this manufacturing tolerance. The typical inductance
cycle is equal to the output current IO. This current can be value thus can be expressed as
expressed as
⎛V ⋅I ⎞
2 ⋅ K L _ TOL ⋅ ⎜ O O ⎟ ⋅ (VMIN − VDS − VO )
⎛1⋅ I 1
⋅ ⎞ ⎝ K LOSS ⎠
1 ⎜2
( )
LIMIT _ MIN + I INITIAL ⋅ tON +
2 ⎟ LTYP =
IO =
TSW _ MAX ⎜ ⎟ ( I LIMIT _ MIN 2 − I INITIAL 2 ) ⋅ FSMIN ⋅ (VMIN − VDS )
( )
⎝ I LIMIT _ MIN + I INITIAL ⋅ tOFF + 0 ⋅ t IDLE ⎠
(A7)
(A4)
where
where
KLOSS is a loss factor, which accounts for the off-state total losses
IO = Output current. of the inductor.
TSW_MAX = The switching interval corresponding to minimum
switching frequency FSMIN. KL_TOL is the inductor tolerance factor and can be between 1.1
and 1.2. A typical value is 1.15.
Substituting for tON and tOFF from equations (A1) and (A2) we
have
3-164
Rev. E 05/05
With this typical inductance we can express maximum output The current through the LinkSwitch-TN as a function of time is
power as given by
1
PO _ MAX =
2
(
⋅ LTYP ⋅ I LIMIT _ MIN 2 − I INITIAL 2 ⋅ ) iSW (t ) = I INITIAL +
VMIN − VDS − VO
⋅ t , 0 < t ≤ tON
L
VMIN − VDS K
FSMIN ⋅ ⋅ LOSS (A8)
VMIN − VDS − VO K L _ TOL iSW (t ) = 0 , tON < t ≤ tON (A14)
Similarly for buck-boost topology the expressions for LTYP and The current through the freewheeling diode as a function of
PO_MAX are time is given by
⎛V ⋅I ⎞ iD (t ) = 0, 0 < t ≤ tON
2 ⋅ K L _ TOL ⋅ ⎜ O O ⎟
⎝ K LOSS ⎠ VO
LTYP = (A9) iD (t ) = I LIMIT _ MIN −
, tON < t ≤ t SW (A15)
( I LIMIT _ MIN 2 − I INITIAL 2 ) ⋅ FSMIN L
V
iD (t ) = 0, I LIMIT _ MIN − O ⋅ t < 0 (A16)
L
1
PO _ MAX = ⋅ LTYP ⋅ ( I LIMIT _ MIN 2 − I INITIAL 2 ) (A10) And the current through the inductor as a function of time is
2
given by
Average Switching Frequency iL (t ) = iSW ( t ) + iD (t ) (A17)
Since LinkSwitch-TN uses an on-off type of control, the frequency From the definition of RMS currents we can express the RMS
of switching is non-uniform due to cycle skipping. We can currents through the switch, freewheeling diode and inductor as
average this switching frequency by substituting the maximum follows
power as the output power in Equation A8. Simplifying, we have t ON
1
iSW _ RMS = ∫ iSW (t )2 ⋅ dt (A18)
2 ⋅ VO ⋅ IO ⋅ K L _ TOL TAVG 0
VMIN − VDS − VO
FSAVG = ⋅
( 2 2
L ⋅ I LIMIT − I INITIAL K LOSS ) VMIN − VDS
(A11) 1
t ON + t OFF
iD _ RMS = ∫ iD (t )2 ⋅ dt (A19)
TAVG t ON
Similarly for buck-boost converter, simplifying Equation A9
we have 3
2 ⋅ VO ⋅ IO K TAVG
FSAVG = ⋅ L _ TOL 1 2
iL _ RMS = ∫ (iSW (t ) + iD (t )) ⋅ dt (A20)
( 2 2
)
L ⋅ I LIMIT − I INITIAL K LOSS K LOSS TAVG 0
(A12)
Since the switch and freewheeling diode currents fall to zero
Calculation of RMS Currents during the turn off and turn on intervals respectively, the RMS
inductor current is simplified to
The RMS current value through the inductor is mainly required
to ensure that the inductor is appropriately sized and will not iL _ RMS = iSW _ RMS 2 + iD _ RMS 2 (A21)
overheat. Also, RMS currents through the LinkSwitch-TN and
freewheeling diode are required to estimate losses in the power
supply.
Assuming CCM operation, the initial current in the inductor in

steady state is given by
VO
I INITIAL = I LIMIT _ MIN − ⋅ tOFF (A13)
L
For DCM operation this initial current will be zero.
3-165
Rev. E 05/05
Table A1 lists the design equations for important parameters

using the buck and buck-boost topologies.
PARAMETER BUCK BUCK-BOOST
LTYP ⎛ V ⋅I ⎞ ⎛ V ⋅I ⎞
2 ⋅ K L ⋅ ⎜ O O ⎟ ⋅ (VMIN − VDS − VO ) 2 ⋅ KL ⋅ ⎜ O O ⎟
⎝ K L _ LOSS ⎠ ⎝ K L _ LOSS ⎠
LTYP = LTYP =
( I LIMIT _ MIN 2 − I INITIAL 2 ) ⋅ FSMIN ⋅ (VMIN − VDS ) ( I LIMIT _ MIN 2 − I INITIAL 2 ) ⋅ FSMIN
FAVG 2 ⋅ VO ⋅ IO ⋅ K L V − VDS − VO 2 ⋅ VO ⋅ IO KL
FSTYP = ⋅ MIN FSAVG = ⋅
( 2
)
L ⋅ I LIMIT − I INITIAL ⋅ K L _ LOSS VMIN − VDS ( 2
L ⋅ I LIMIT − I INITIAL 2 K )
L _ LOSS
iSW(t) VMIN − VDS − VO VMIN − VDS

iSW (t ) = iINIT + ⋅ t , t ≤ tON iSW (t ) = iINIT + ⋅ t , t ≤ tON
LinkSwitch-TN L L
Current iSW (t ) = 0 , t > tON iSW (t ) = 0 , t > tON
VO VO
id(t) iD (t ) = I LIMIT _ MIN − ⋅ t , t > tON iD (t ) = I LIMIT _ MIN − ⋅ t , t > tON
L L
Diode V
V iD (t ) = 0 , I LIMIT _ MIN − O ⋅ t < 0
Forward iD (t ) = 0 , I LIMIT _ MIN − O ⋅ t < 0
L L
Current
iD (t ) = 0 , t ≤ tON iD (t ) = 0 , t ≤ tON
iL(t) Inductor
iL (t ) = iSW (t ) + iD (t ) iL (t ) = iSW (t ) + iD (t )
Current
Max Drain VMAX + VO

VMAX
Voltage
Table A1. Circuit Characteristics for Buck and Buck-Boost Topologies.
Revision Notes Date

A – 1/04
B Corrected Tables 3 and 4. 4/04
C Added LNK302. 7/04
D Added supplementary information to Tables 4 and 5. 12/04
E Corrected equation 2. 5/05
3-166
Rev. E 05/05
LinkSwitch-LP
®
Flyback Design Guide
Introduction thus, dramatically reduces component count and total system

cost. Figure 1 shows a LinkSwitch-LP based 2 W power supply
The LinkSwitch-LP family is designed to replace inefficient without a primary-side clamp. The LinkSwitch-LP family
line frequency linear transformer based power supplies with has been optimized to give an approximate CV/CC output
output powers < 2.5 W in applications such as cell/cordless characteristic when feedback is provided from an auxillary or
phones, PDAs, digital cameras, and portable audio players. bias winding on the transformer. This is ideal for applications
LinkSwitch-LP may also be used as auxiliary supplies employed replacing a line frequency transformer, providing a compatible
in applications such as white goods. output characteristic but with reduced overload, short circuit
current and variation with input line voltage.
LinkSwitch-LP combines a high voltage power MOSFET switch
with an ON/OFF controller in one device. It is completely
self-powered from the DRAIN pin, has a jittered switching
Scope
frequency for low EMI and is fully fault protected. Auto-restart This application note is for engineers designing an isolated
limits device and circuit dissipation during overload and output AC-DC flyback power supply using the LinkSwitch-LP family of
short circuit conditions while hysteretic over-temperature devices. It provides guidelines to enable an engineer to quickly
protection disables the internal MOSFET during thermal select key components and complete a transformer design for an
faults. EcoSmart® technology enables designs to easily attain application requiring either a constant voltage (CV) or constant
< 150 mW no-load consumption, meeting worldwide energy voltage and constant current (CV/CC) output. To simplify the
efficiency requirements. task of transformer design, this application note refers directly
to the PI Xls design spreadsheet that is part of the PI Expert™
LinkSwitch-LP is designed to operate without the need for a design software suite.
primary-side clamp circuit for output powers below 2.5 W and
3
C5
D1 L1 T1 D6 220 µF R4 6 V,
L 1N4937 3.3 mH 2 EE16 7 UF4002 25 V 2 kΩ 0.33 A
C1
90-265 10 µF
VAC 400 V 1 6
4 RTN
N D5
D4
1N4007 5 1N4005
R1
37.4 kΩ
D C4
LinkSwitch FB
0.33 µF
U1 BP 50 V
LNK564P R2
C3
S 0.1 µF 3 kΩ
50 V
PI-4063-101005
Figure 1. Basic Circuit Schematic Using LinkSwitch-LP in a Clampless™ Design.
3-167
Rev. B 07/06
Quick Start
Start design
Enter power supply specifications:

Input voltage range and frequency, output voltage,
output current and VI characteristic, feedback type,
loss allocation factor, diode conduction time and
input capacitance
Select LinkSwitch-LP based on Table 4

(see data sheet) and reflected
output voltage (VOR) to 80 V
Yes Select a standard transformer design

4 V ≤ VO ≤ 12 V (Table 8). See appendices for
PO ≤ 2 W Transformer and bobbin drawings
No
Select transformer core and bobbin

based on Table 5 and 6
Ensure that flux density BM < 1500

Gauss (150 mT). Adjust by
increasing number of secondary turns NS
3 Select input stage filter and rectifier

based on Table 7
Select BYPASS pin capacitor. Use

0.1 µF / 50 V capacitor. See Step 6
Select output diode based on

Table 8 and calculate preload
resistor
Select output capacitor based on

secondary ripple current and
output voltage (see Step 8)
PI-4137-101005
Finish design
Figure 2. LinkSwitch-LP Flyback Design Flowchart.
3-168
Rev. B 07/06
Step-by-Step Design procedure VOUT

Step 1 – Enter Application Variables: VACMIN, VACMAX, Nominal Peak
Power Point Maximum Peak
fL, VO, IO, CV/CC spec, PO, Clamp and Feedback type, Power Point
η, Z, tC and CIN.
VOUT(TYP)
Determine the input voltage range (VACMIN and VACMAX) from

Table 1.
Nominal Input Voltage VACMIN VACMAX IOUT

PI-4152-100705 IOUT IOUT
100/115 85 132 (TYP) (MAX)
(a)
230 195 265
VO
Universal 85 265 Maximum Peak
Power Point
Table 1. Standard Worldwide, Input Line Voltage Ranges. Nominal Peak

VOUT(TYP)
Power Point
Line Frequency, fL
Enter the worst-case line frequency under which the supply
should operate normally.
Output Voltage, VO IOUT(TYP) IO

Enter the output voltage. For loose CV/CC designs, this should PI-4172-101005
be the typical output voltage at the nominal peak power point in (b)
the output characteristic. For CV only outputs this should be the
specified output voltage. For designs with an output cable enter Figure 3. Diagram Showing Correct Values of IO and VO to enter
the voltages at the load. For multiple output designs enter the in the spreadsheet for (a) Optocoupler Feedback and (b)
voltage for the main output from which feedback is taken. Bias Winding Feedback
Output Current, IO CC portions of the spec. This arrangement uses bias winding
For loose CV/CC designs, this should be the typical output current feedback to regulate the output. During normal operation
at the nominal peak power point in the output characteristic. switching cycles are enabled or disabled to maintain the voltage
For CV only outputs, this should be the maximum specified at the FEEDBACK pin. This, via the turns ratio between the
output current. In multiple output designs, the output current bias and secondary windings regulates the output. However 3
of the main output (typically the output from which feedback as the secondary output voltage is not directly sensed, errors
is taken) should be increased such that PO matches the sum caused by leakage inductance and resistive drops result is
of the output powers from all the outputs in the design. The only moderate load regulation (however still better than an
individual output voltages and currents should then be entered unregulated line frequency linear transformer based supply).
at the bottom of the spreadsheet. Once the maximum power point is reached (determined by the
primary inductance, current limit and switching frequency) the
Figure 3 shows a diagram with correct values of IO and VO to voltage on the bias winding begins to fall and the switching
enter in the spreadsheet for both Optocoupler based feedback frequency of LinkSwitch-LP is reduced to limit the maximum
and Bias Winding Feedback. output current as an output overload increases toward a short
circuit.
CV/CC Output Specification
If the output specification is loose constant voltage and constant For improved performance, Figure 4 shows an arrangement
current (charger) CV/CC type enter ʻYESʼ in cell B8, otherwise using an optocoupler and high gain voltage reference IC (U2)
enter ʻNOʼ for Constant voltage (adapter) CV only. For CV/CC to regulate the output voltage. Once the maximum power
designs, the typical value of I2f is used in the computation of point is reached and the output voltage falls, the output current
primary inductance, while for CV only designs, the minimum is controlled via the bias winding, sensed via RX and RY
value of I2f is used to guarantee power delivery. (Figure 4). As shown in Table 3 the high gain of the system
gives an output voltage with minimal variation during CV
A CV/CC characteristic can be achieved by using either one operation and good linearity, maintaining an almost vertical CC
of the arrangements shown in Figures 1 or 4. Figure 1 shows characteristic. As the output is being sensed indirectly via the
a low cost primary side control scheme for both the CV and bias winding during CC operation, the CC characteristic is still
3-169
Rev. B 07/06
T1
+ +
CO R3
DS
R1
CB
0.33 µF
DC BUS 50 V
or DB U2 VO
HV DC
RX
D
LinkSwitch-LP FB R2
U1 BP
LNK564P
S
0.1 µF RY
50 V
PI-4138-070706
Figure 4. Circuit Schematic for High Performance CV/CC Output Characteristic.
subject to unit-to-unit variation caused by the difference in the For designs using Filterfuse™ use the values in parenthesis,
transformer (bias to secondary coupling and leakage inductance. these take into account the additional primary side losses due
Also see Enter Feedback, Bias Type and Clamp Information to a typical value of ~50 Ω for the resistance of the Filterfuse
section). Note that the reference IC U2 may be replaced by a inductor
lower cost zener diode in applications where increased tolerance
is acceptable during CV operation. Bridge Diode Conduction Time, tC (ms)
Enter the bridge diode conduction time. Use 3 ms if no other
Finally for improved CC performance a secondary CC sense data is available.
circuit can be used. This removes variation in the CC due to
3 the transformer and FEEDBACK pin. Total Input Capacitance CIN (µF)
Enter total input capacitance using Table 2 for guidance.
Power Supply Efficiency, η
Enter the estimated power supply efficiency measured at the Total Input Capacitance per Watt
point of load. For both CV/CC and CV only designs use 0.65 if of Output Power (µF/W)
no better data is available or until measurements can be made AC Input Half Wave Full Wave
on a prototype. Voltage (VAC) Rectification Rectification
Power Supply Loss Allocation Factor, Z 100/115 5-8 3-4
This factor represents the proportion of losses between the 230 1-2 1
primary and the secondary of the power supply. 85-265 5-8 3-4
Table 2. Suggested Total Input Capacitance for Different Input
Voltage Ranges.
If no better data is available then the following values are The capacitance should be selected to keep the minimum DC
recommended: input voltage, VMIN > 50 V and ideally > 70 V.
• Bias winding feedback designs (CV or CV/CC): 0.5 (0.35) Note: For designs that have a DC rather than an AC input, the
• Optocoupler CV feedback and/or bias winding CC value of the minimum and maximum DC input voltages, VMIN
feedback: 0.5 (0.35) and VMAX, may be entered directly into the gray override cells
• Optocoupler CV and CC feedback: 0.75 (0.6) on the design spreadsheet (see Figure 5).
3-170
Rev. B 07/06
Optocoupler with Zener

Bias Winding Feedback Optocoupler with TL-431 as
as Reference (Figure 4, U2
(Figure 1) Reference (Figure 4)
Replaced with Zener
9 9 9
PI-4139-092205
PI-4173-101305
PI-4140-101305
8 8 8
7 7 7
Output Voltage (V)
Output Voltage (V)
Output Voltage (V)

6 6 6
5 5 5
Typical Output 4 4 4
Characteristics 3 3 3
2 2 2
1 1 1
0 0 0
0 150 300 450 600 750 0 150 300 450 600 750 0 150 300 450 600 750
Load (mA) Load (mA) Load (mA)
Cost Low Higher Highest
Component count Lowest component count Higher component count Highest component count
Ease of Design High Medium Medium
CV/CC Tolerance Good Better Best
Table 3. Summary of Comparison Between Bias Winding Feedback and Optocoupler Feedback.
Enter Feedback, Bias Type and Clamp Information If optocoupler feedback is selected, the user still has the option
Select either bias winding feedback (primary-side feedback) to reduce overall power consumption by using a bias winding
as shown in Figure 1or optocoupler feedback (secondary-side to power the optocoupler transistor. That bias winding can also
feedback) as shown in Figure 4. Bias winding feedback makes be configured as a shield, for improved EMI performance.
use of a primary-side auxiliary winding to set the output voltage.
Optocoupler feedback directly senses the output voltage and Clampless™ designs typically exhibit a resonance between the
can provide any level of accuracy depending on the voltage
reference selected. Both primary-side feedback and secondary-
leakage inductance and primary capacitance, that is normally
damped by the primary clamp. As there is less damping in a 3
side feedback allow for a CV/CC output characteristic. See Clampless design this creates a peak in the conducted EMI
Table 3 for a summary of feedback types. measurements in 1-4 MHz range. It is generally the EMI
ENTER APPLICATION VARIABLES Customer

VACMIN 85 Volts Minimum AC Input Voltage
VACMAX 265 Volts Maximum AC Input Voltage
fL 50 Hertz AC Mains Frequency
Output Voltage (main) measured at the end of output cable (For CV/CC designs enter typical CV
VO 6.00 Volts tolerance limit)
IO 0.33 Amps Power Supply Output Current (For CV/CC designs enter typical CC tolerance limit)
Constant Voltage / Constant Current Output YES CVCC Volts Enter "YES" for approximate CV/CC output. Enter "NO" for CV only output
Output Cable Resistance 0.16 0.16 Ohms Enter the resistance of the output cable (if used)
PO 2.00 Watts Output Power (VO x IO + dissipation in output cable)
Bias
Feedback Type BIAS Winding Enter 'BIAS' for Bias winding feedback and 'OPTO' for Optocoupler feedback
Enter 'YES' to add a Bias winding. Enter 'NO' to continue design without a Bias winding. Addition of
Add Bias Winding YES Yes Bias winding can lower no load consumption
Clampless design YES Clampless Enter 'YES' for a clampless design. Enter 'NO' if an external clamp circuit is used.
n 0.64 Efficiency Estimate at output terminals. For CV only designs enter 0.7 if no better data available
Z 0.35 0.35 Loss Allocation Factor (Secondary side losses / Total losses)
tC 2.90 mSeconds Bridge Rectifier Conduction Time Estimate
CIN 9.40 uFarads Input Capacitance
Input Rectification Type F F Choose H for Half Wave Rectifier and F for Full Wave Rectification
DC INPUT VOLTAGE PARAMETERS

VMIN 99 Volts Minimum DC Input Voltage
VMAX 375 Volts Maximum DC Input Voltage
Figure 5. Application Variable Section of LinkSwitch-LP Design Spreadsheet.
3-171
Rev. B 07/06
performance and not the peak drain voltage that limits the use Reflected Output Voltage, VOR (V)
of Clampless designs to < 2 W. However if a bias winding is This parameter is the secondary winding voltage reflected
added which uses a slow diode (1N400x series) that peak in back to the primary through the turns ratio of the transformer
EMI is reduced as the bias acts as a clamp, damping out the (during the off time of the LinkSwitch-LP). The default
leakage inductance ringing. This extends the power range for value is 80 V, however this can be increased up to 120 V to
Clampless designs to ≤2.5 W. In addition, the use of a small achieve the maximum power capability from the selected
Y-Capacitor (100 pF) can be beneficial in containing this problem LinkSwitch-LP device. In general, start with the default value of
and making the EMI performance less variable. 80 V, increasing the value when necessary to maintain KP above
its lower limit of 0.9 at the minimum input voltage of 85 VAC.
For designs greater than 2.5 W, a Clampless solution is not For Clampless designs, there is less flexibility in selecting the
recommended. value of VOR. Increasing VOR directly increases the peak drain
voltage. Therefore for Clampless designs, a value of 80 V should
The guidance above applies to universal input or 230 VAC only be used and only increased once the peak drain voltage has been
designs. For 100/110 VAC only input designs it may be possible measured and adequate margin to BVDSS determined.
to use Clampless designs above 2 - 2.5 W but only after verifying
acceptable peak drain voltage and EMI performance. LinkSwitch-LP On-State DRAIN-to-SOURCE Voltage,
VDS (V)
All the variables described above can be entered in the Enter This parameter is the average on-state voltage developed across
Application Variables section of the LinkSwitch-LP design the DRAIN and SOURCE pins of LinkSwitch-LP. By default, if
spreadsheet in the PI Xls design software (see Figure5). the gray override cell is left empty, a value of 10 V is assumed.
Use the default value if no better data is available.
Step 2 – Enter LinkSwitch-LP, VOR, VDS, VD
Output Diode Forward Voltage Drop, VD (V)
Select the appropriate LinkSwitch-LP based on the input Enter the average forward voltage drop of the (main) output
voltage range and the corresponding maximum output power diode. Use 0.5 V for a Schottky diode or 1 V for a PN diode
(see Table 4 & 5). if no better data is available. By default, a value of 0.5 V is
assumed.
Maximum Power (W)
Calculated Ripple to Peak Current Ratio, KP
Device Universal Input 230 VAC
KP is a measure of the operating mode and primary current
LNK562 1.9 1.9 waveshape of the design. KP < 1 indicates a continuous design
LNK563 2.5 2.5 (the lower the KP, the more continuous the design) and a
KP > 1 indicates a discontinuous design (the higher the KP, the
3 LNK564 3 3
more discontinuous the design).
Table 4. Maximum Output Power Capability of LinkSwitch-LP
Devices. Below a value of 1, indicating continuous conduction mode,
KP is the ratio of ripple to peak primary current (KRP). Above
Power delivery from a given device also depends on the a value of 1, indicating discontinuous conduction mode, KP is
transformer core size selected. Table 5 provides examples of the ratio of primary MOSFET off time to the secondary diode
the output power possible from each device and 3 common conduction time (KDP). The value of KP should be in the range
core sizes. These power numbers assume a flux density of of 0.9 < KP < 6 and guidance is given in the comments cell if
1500 Gauss, and can be increased for higher flux densities, the value is outside this range.
based on acceptable audible noise.
ENTER LinkSwitch-LP VARIABLES

LinkSwitch-LP LNK564 LinkSwitch-LP device
Chosen Device LNK564
ILIMITMIN 0.124 Amps Minimum Current Limit
ILIMITMAX 0.146 Amps Maximum Current Limit
fSmin 93000 Hertz Minimum Device Switching Frequency
I^2fMIN 1665 A^2Hz I^2f Minimum value (product of current limit squared and frequency is trimmed for tighter tolerance)
I^2fTYP 1850 A^2Hz I^2f typical value (product of current limit squared and frequency is trimmed for tighter tolerance)
VOR 80 Volts Reflected Output Voltage
VDS 10 Volts LinkSwitch-LP on-state Drain to Source Voltage
VD 0.5 Volts Output Winding Diode Forward Voltage Drop
KP 1.53 Ripple to Peak Current Ratio (0.9<KRP<1.0 : 1.0<KDP<6.0)
Figure 6. LinkSwitch-LP Variables Section of LinkSwitch-LP Design Spreadsheet.
3-172
Rev. B 07/06
Variables referenced in Step two are found in the Enter The gray override cells can be used to enter the core and bobbin
LinkSwitch-LP Variables section of the spreadsheet (see parameters directly. This is useful if a core is selected that is
Figure 6). not on the list or the specific core or bobbin information differs
from that recalled by the spreadsheet.
Step 3 – Choose Core and Bobbin Based on Output
Power and Enter Ae , Le, AL, BW, M, L, NS Safety Margin, M (mm)
For designs that require isolation but are not using triple
Core Effective Cross-Sectional Area, Ae (cm2), Core Effective insulated wire for the secondary winding, the width of the safety
Path Length, Le (cm), Core Ungapped Effective Inductance, AL margin to be used on each side of the bobbin should be entered
(nH/Turn2), Bobbin Width, BW (mm). here. Typically, for universal input designs, a total margin of
6.2 mm would be required. Therefore a value of 3.1 mm would
By default, if the Core Type cell is left empty, the spreadsheet be entered into the spreadsheet. For vertical bobbins, the margin
will select the EE16 core. The user can change this selection may not be symmetrical.
and choose an alternate core from a list of commonly available
cores (shown in Table 6). Table 5 provides guidance on the As the margin reduces the available area for the windings,
power capability of specific core sizes. margin construction may not be suitable for small core sizes.
If after entering the margin, more than 4 primary layers (L) are
required, it is suggested that either a larger core be selected or
Output Power Capability (W) switch to a zero margin design using triple-insulated wire for
Core Size LNK562 LNK563 LNK564 the secondary winding.
EE13 1.1 1.4 1.7
Primary Layers, L
EE16 1.3 1.7 2 By default, if the override cell is empty, a value of 2 is assumed.
EE19 1.95 2.55 3 Primary layers should be in the range of 1 < L < 4 and in general,
it should be the lowest number that meets the primary current
Table 5. Typical Output Power Capability of LinkSwitch-LP density limit (CMA) of 150 Cmils per amp. Values above 4
Devices vs. Core Sizes (1500 Gauss/150 mT). layers are possible, but the increased leakage inductance and
physical fit of the windings should be considered.
Transformer Core For Clampless designs, 2 primary layers must be used. This is
to ensure sufficient primary capacitance to limit the peak drain
EE8 EE1616 voltage below the BVDSS rating of the MOSFET internal to the
EP10 EF16 LinkSwitch-LP.
EE10 EE19 3
Secondary Turns, NS
EF12.6 EF20
By default, if the gray override cell is left blank, the minimum
EE13 EF25 number of secondary turns is calculated such that the maximum
EE16 operating flux density, BM, is kept below the recommended
maximum. In general, it is not necessary to enter a number in
Table 6. List of Cores Provided in LinkSwitch-LP Spreadsheet. the override cell except in designs where a higher operating flux
density is acceptable (see Minimizing Audible Nose section for
an explanation of BM limits).
ENTER TRANSFORMER CORE/CONSTRUCTION VARIABLES

Core Type EE16 Suggested smallest commonly available core
Core EE16 P/N: PC40EE16-Z
Bobbin EE16_BOBBIN P/N: EE16_BOBBIN
AE 0.192 cm^2 Core Effective Cross Sectional Area
LE 3.5 cm Core Effective Path Length
AL 1140 nH/T^2 Ungapped Core Effective Inductance
BW 8.6 mm Bobbin Physical Winding Width
M 0 mm Safety Margin Width (Half the Primary to Secondary Creepage Distance)
L 2 Number of primary layers
NS 12 Number of Secondary Turns
NB 37 Number of Bias winding turns
VB 19.77 Volts Bias Winding Voltage
R1 32.95 k-ohms Resistor divider component between bias wiinding and FB pin of LinkSwitch-LP
R2 3.00 k-ohms Resistor divider component between FB pin of LinkSwitch-LP and primary RTN
Place this diode on the return leg of the bias winding for optimal EMI. See LinkSwitch-LP Design guide
Recommended Bias Diode 1N4003 for more information
Figure 7. Transformer Core and Construction Variables Section of LinkSwitch-LP Spreadsheet.
3-173
Rev. B 07/06
Calculated Bias Winding Turns and Voltage NB, VB 1500 Gauss (150 mT) may produce audible noise from the
When a bias winding is used, the number of turns and voltage transformer and for such designs the acceptability should be
developed by the winding are displayed. The relatively large verified. To minimize audible noise all transformers should be
default number of turns allows the bias to be used as a shield dip varnished. Vacuum impregnation is not recommended due
winding for reduced EMI. to the resultant increase in winding capacitance. Flux densities
above 3000 Gauss (300 mT) are not recommended.
The variables described in Step 3 are found in the Enter
Transformer Core/Construction Variables section of the Other transformer parameters calculated in the spreadsheet
spreadsheet (see Figure 7). are:
B
P
Step 4 – Iterate Transformer Design and Generate NP - Primary Winding Number of Turns
Transformer Design Output ALG (nH/T2) - Gapped Core Effective Inductance
BAC (Gauss) - AC Flux Density for Core Loss Curves
Iterate the design, making sure that no warnings are displayed. (0.5 × Peak-to-Peak)
Any parameters outside the recommended range of values can µr - Relative Permeability of Ungapped Core
be corrected by following the guidance given in the right hand LG (mm) - Gap Length (LG > 0.1 mm).
column. BWE (mm) - Effective Bobbin Width (accounts for margin
tape, if used)
Once all warnings have been cleared, the transformer design OD (mm) - Maximum Primary Wire Diameter (including
parameters can be used to either wind a prototype transformer insulation)
or send to a vendor for samples. INS (mm) - Estimated Total Insulation Thickness (= 2 × film
thickness)
947)
The key transformer electrical parameters are: DIA (mm) - Bare Conductor Diameter
AWG - Primary Wire Gauge (rounded to next smaller
Primary Inductance, LP (µH) standard AWG value)
This is the target nominal primary inductance of the transformer. CM (Cmils) - Bare conductor effective area in circular mils
OR For designs that use bias winding feedback, there is no current CMA (Cmils/Amp) - Primary Winding Current Capacity
W to sense resistor, and the value of primary inductance (LP) (150 < CMA < 500)
Cxxx determines the onset of the constant current (CC) portion of
of suit- the CV/CC characteristic. Variables described in Step 4 can be found under the
“Transformer Primary Design Parameters” section of the
Primary Inductance Tolerance, LP_TOLERANCE (%) spreadsheet (see Figure 8).
This is the assumed primary inductance tolerance. A value of
3 ±10% is used by default, however if specific information is known Step 5 – Selection of Input Stage
from the transformer vendor, then this may be overridden by
entering a new value in the gray override cell. For designs that The input stage comprises a fusible element(s), input rectification
use bias winding feedback, the LP_TOLERANCE determines a large and line filter network. The fusible element can be either a
part of the total CC tolerance of the output characteristic. fusible resistor, a fuse or make use of Power Integrationʼs
Filterfuse technique. Here, the input inductor may also be
Maximum Operating Flux Density, BM (Gauss) used as a fuse, typically requiring the addition of a heatshrink
It is recommended that this value be below 1500 Gauss shroud to prevent incandescent material being ejected during a
(150 mT) during normal operation. Flux densities above fault. By using Filterfuse, the input stage can be simplified in
TRANSFORMER PRIMARY DESIGN PARAMETERS

LP 2857 uHenries Typical Primary Inductance. +/- 10%
LP_TOLERANCE 10 % Primary inductance tolerance
NP 148 Primary Winding Number of Turns
ALG 131 nH/T^2 Gapped Core Effective Inductance
BM 1471 Gauss Maximum Operating Flux Density, BM<1500 is recommended
BAC 581 Gauss AC Flux Density for Core Loss Curves (0.5 X Peak to Peak)
ur 1654 Relative Permeability of Ungapped Core
LG 0.16 mm Gap Length (Lg > 0.1 mm)

BWE 17.2 mm Effective Bobbin Width
OD 0.12 mm Maximum Primary Wire Diameter including insulation
INS 0.03 mm Estimated Total Insulation Thickness (= 2 * film thickness)
DIA 0.09 mm Bare conductor diameter
AWG 40 AWG Primary Wire Gauge (Rounded to next smaller standard AWG value)
CM 10 Cmils Bare conductor effective area in circular mils
CMA 197 Cmils/Amp Primary Winding Current Capacity (150 < CMA < 500)
Figure 8. Transformer Primary Design Parameters Section of LinkSwitch-LP Spreadsheet.
3-174
Rev. B 07/06
POUT ≤1W ≤3W

Suggested 85-265 + LIN + L1
DIN1-4
RF1 DIN1 RF2 RF1 DIN1 LIN +

VAC Input Stage DIN1 3.3 mH
C1**
RF1
AC **
CIN1 CIN2 AC **
CIN1 CIN2 10 µF AC IN **
IN IN CIN1 CIN2
400 V
DIN2 DIN2 DIN2
PI-3772-121603 PI-3773-121603 PI-4240-110305

PI-3774-121603
Component RF1: 8.2 Ω, 1 W RF1: 8.2 W, 1 W L1*: 3.3 µH, 0.06 A RF1: 8.2 W, 1 W
Selection Guide Fusible Fusible Filterfuse® Fusible
RF2: 100 Ω, 0.5 W, LIN: 470 µH-2.2 mH, C1: ≥ 5 µF/ WOUT, LIN: 470 µH-2.2 mH,
Flameproof (0.05 A-0.3 A) 400 V (0.05 A-0.3 A)
CIN1, CIN2: ≥ 3.3 µF, CIN1, CIN2: ≥ 4 µF/ WOUT, DIN1: 1N4937, 600 V CIN1, CIN2: ≥ 2 µF/ WOUT,
400 V each 400 V each DIN2: 1N4007, 1000 V 400 V each
DIN1, DIN2: 1N4007, DIN1, DIN2: 1N4007, DIN1-DIN4: 1N4007,
1 A, 1000 V 1 A, 1000 V 1 A, 1000 V
Comments **Increase value to **Increase value to *Check for safety **Increase value to
meet required differ- meet required differ- agencies approval meet required differ-
ential line ential line ential line surge
**Increase value to
meet required differ-
ential line surge
performance
Table 7. Input Filter Recommendation Based on Total Output Power.
saving the cost of a fusible resistor, but requires a larger single power for a universal input design while Table 2 shows how to
input capacitor. However, please verify with a safety engineer adjust the input capacitance for other input voltage ranges.
or agency if Filterfuse is acceptable.
Step 6 – Selection of Feedback Components and
If a fusible resistor is selected, it should be a flameproof type BYPASS Pin Capacitor
and, depending on the differential line input surge requirements,
a wire-wound type may be required. Care should be taken in
using metal or carbon film types as these can fail simply due to
LinkSwitch-LP requires a standard 0.1 µF / 50 V capacitor across
the BYPASS and SOURCE pins. This can be a 20% tolerance
3
the inrush current when AC is connected to the supply. Z5U multi-layer ceramic capacitor.
Designs using a Y capacitor require the EMI filter impedance The feedback components include the bias winding diode,
to be placed on the appropriate side of the input. Therefore capacitor and resistor divider network, which set the output
when the Y capacitor is returned to the DC rail, the fusible voltage. The bias winding diode plays a significant role in the
resistor(s)/Filterfuse should be placed on the opposite side of output regulation and this component should be a standard
the input. recovery diode like the 1N4007. The standard value for the
bias capacitor is 0.33 µF / 50 V. A higher value capacitor may
For designs ≤ 1 W, it is generally lower cost to use half-wave also be used for lower no-load consumption.
rectification; and > 1 W, full-wave rectification. However if
Filterfuse is used, even above 1 W, half-wave rectification may Resistors R1 and R2 in Figure 1 form a resistor divider network
lower cost and should be selected accordingly. and this sets the output voltage such that the FEEDBACK pin
voltage is maintained at 1.69 V. The initial value for these
The EMI performance of half-wave rectified designs is resistors is estimated by the spreadsheet, but these values are
improved by adding a second diode in the lower return rail. also dependent on the leakage inductance and any mismatch in
This provides EMI gating (EMI currents only flow when the the forward voltage drop across the diodes (standard, ultra-fast
diode is conducting) and also doubles the differential surge- or Schottky) used in the bias and output windings. Adjust these
withstand as the surge voltage is shared across two diodes. resistors based on empirical testing.
Table 7 shows the recommended input stage based on output
3-175
Rev. B 07/06
VR Range IF
Series Number Type Package Manufacturer
V A
1N5817 to 1N5819 Schottky 20-40 1 Leaded Vishay
SB120 to SB1100 Schottky 20-100 1 Leaded Vishay
11DQ50 to 11DQ60 Schottky 50-60 1 Leaded IR
MBR320 to MBR360 Schottky 20-60 3 Leaded IR
SS12 to SS16 Schottky 20-60 1 SMD Vishay
UF4002 to UF4006 Ultrafast 100-600 1 Leaded Vishay
ES1A to ES1D Ultrafast 50-200 1 SMD Vishay
Table 8. List of Recommended Diodes That May Be Used With LinkSwitch-LP Designs.
TRANSFORMER SECONDARY DESIGN PARAMETERS (MULTIPLE OUTPUTS)

1st output
VO1 6 Volts Main Output Voltage (if unused, defaults to single output design)
IO1 0.333 Amps Output DC Current
PO1 2.00 Watts Output Power
VD1 0.5 Volts Output Diode Forward Voltage Drop
NS1 12.00 Output Winding Number of Turns
ISRMS1 0.668 Amps Output Winding RMS Current
IRIPPLE1 0.58 Amps Output Capacitor RMS Ripple Current
PIVS1 36 Volts Output Rectifier Maximum Peak Inverse Voltage
SB150,
Recommended Diodes UF4001 Recommended Diodes for this output
Pre-Load Resistor 2 k-Ohms Recommended value of pre-load resistor
CMS1 134 Cmils Output Winding Bare Conductor minimum circular mils
AWGS1 28 AWG Wire Gauge (Rounded up to next larger standard AWG value)
DIAS1 0.32 mm Minimum Bare Conductor Diameter
ODS1 0.72 mm Maximum Outside Diameter for Triple Insulated Wire
Figure 9. Secondary Design Parameters. Includes a Recommended Diode Part.
3
Step 7 – Selection of Output Diode and Pre-load no-load losses so this value can be adjusted to trade-off lower
Resistor no-load input power with high no-load output voltage.
VR ≥ 1.25 × PIVS, where PIVS is taken from the Voltage Step 8 – Selection of Output Capacitors
Stress Parameters section of the spreadsheet and Transformer
Secondary Design Parameters. Ripple Current Specification at Maximum Capacitor
Operating Temperature
ID ≥ 2 × IO, where ID the diode rated DC current and IO is the This should be ≥ IRIPPLE value from the design spreadsheet (from
output current. the Transformer Secondary Parameters section or, in multiple
output designs, the Transformer Secondary Design Parameters
Additionally, Table 8 lists some of the suitable Schottky and (Multiple Outputs) section). Many capacitor manufacturers
ultra-fast diodes that may be use with LinkSwitch-LP circuits. provide factors that increase the ripple current rating as the
Priority should be given to lower reverse recovery times capacitor operating temperature is reduced from its data sheet
(tRR) while selecting the output diodes. The LinkSwitch-LP maximum. This should be considered to ensure that the capacitor
spreadsheet also recommends a diode based on the above is not oversized for cost reasons.
guidelines (see Figure 9).
ESR Specification
Select the pre-load resistor such that it will sink ~1-3 mA at the Use a low ESR electrolytic capacitor. Output switching ripple
specified voltage. Note that a pre-load resistor also increases the is a function of the ESR of the capacitor and is given by
3-176
Rev. B 07/06
ISP × ESR. ISP is the secondary peak current, which is calculated To illustrate this, Appendix A provides two reference
in the Transformer Secondary Design Parameters section of designs that in many cases may eliminate the need to design
the spreadsheet. a transformer. These two reference designs include Power
Integrationsʼ E-Shield windings to minimize EMI.
Tips for Clampless Designs
Table 9 lists a series of output voltages and current, which can
The mechanical construction of the transformer will play a be used to select the correct LinkSwitch-LP device, reference
crucial role in Clampless designs. Care should be taken to transformer design and feedback resistor values (assuming bias
reduce the leakage inductance and increase the intra-winding winding feedback).
capacitance of the primary winding. Intra-winding capacitance
is defined as the capacitance measured from one end of a The table also lists, for information, the effective VOR. As
winding to the other end while all other windings are open. the output voltage is reduced from the nominal design the
This is best achieved by using a 2-layer primary winding. It VOR reduces and conversely increases as the output voltage
is common to use a layer of tape between 2 primary layers. is increased. It is this that limits the effective output voltage
This should be avoided for Clampless designs, as this tends to range that one transformer can cover without either excessive
reduce intra-winding capacitance. For designs that do not use peak drain voltage or the design entering continuous conduction
a bias winding for damping the leakage ringing, there is no mode (KP < 1) with itʼs associated increase in EMI.
restriction on strictly using a 2-layer primary winding. However,
for Clampless designs that do not use a bias winding, a 2-layer Note: The standard transformer designs assume that a bias
primary winding must be used. winding is used. Therefore to implement a Clampless design
the bias winding must be used with slow diode (D5) as shown
Even with the increased winding capacitance, no-load power in Figure 10.
of < 150 mW is easily possible with LinkSwitch-LP.
For typical Clampless designs, the leakage inductance is below

Example Designs Using Standard
90 µH and the intra-winding capacitance is at least 30 pF. Transformers
Figure 1 shows an example design for a cell phone charger power
Minimizing Audible Noise supply. It is a universal input power supply with 6 V output at
a constant maximum current of 330 mA. The circuit uses no
The cycle skipping mode of operation used in LinkSwitch-LP
Y capacitor, no primary side clamp and relies on a slow diode
used in the bias winding for damping the leakage spike. The
To limit this audible noise generation, the transformer should
transformer uses a standard EE16 core and uses E-Shields to
be designed such that the peak core flux density BM is below
1500 Gauss (150 mT). Following this guideline and using the
meet the CISPR-22 EMI limits. Detailed transformer drawings
are shown in Appendix A and these can be used as a building
3
block for others. For slightly different output voltages (see
practically eliminates audible noise. Higher flux densities
Table 9), the resistor divider in the bias winding may be adjusted.
are possible, however careful evaluation of the audible noise
For power below 2 W, either a smaller LinkSwitch-LP part may
performance should be made using production transformer
be used or the primary inductance may be adjusted by changing
samples before approving the design.
the length of the air gap.
Ceramic capacitors that use dielectrics such as Z5U, when used
Figure 10 shows another example design for a cell phone
in clamp circuits, may also generate audio noise. If this is the
charger power supply which is also a universal input voltage
case, try replacing them with a capacitor having a different
range supply with an output voltage of 9 V at a maximum
dielectric, for example a polyester film type.
constant current of 220 mA. This is also a Clampless design,
which relies on the bias diode to damp out the leakage spike
Standard Transformer Designs during turn off. Use of E-Shields allows the design to pass the
The LinkSwitch-LP family members have the same primary CISPR-22 EMI limits with 10 dB of margin, without the use
current limit but different switching frequencies, which result of a Y capacitor. Detailed drawings for this transformer are
in different, output power capabilities. This allows additional shown in Appendix A.
flexibility in design by allowing the same transformer design to
be used for different output powers and output voltages.
3-177
Rev. B 07/06
C5
D1 L1 T1 D6 220 µF R4 9 V,
L 1N4937 3.3 mH 2 EE16 7 UF4002 25 V 3 kΩ 0.22 A
C1
90-265 10 µF
VAC 400 V 1 6
4 RTN
N D5
D4
1N4005 5 1N4005
R1
36.5 kΩ
D C4
FB
LinkSwitch 0.33 µF
U1 BP 50 V
LNK564P C3 R2
S 0.1 µF 3 kΩ
50 V
PI-4145-101005
Figure 10. 9 V, 220 mA Design Using the Standard Transformer Design Described in Appendix B.
These two transformers have been optimized for EMI Table 9 lists the transformer, reflected output voltage and the
performance and the rest of the circuit can be adjusted to bias winding resistor divider values for specific combinations of
meet most specifications, which can be addressed by the output voltages and currents. Note that layout changes tend to
LinkSwitch-LP familyʼs power range. The parameters to be affect the EMI performance and this should be verified before
adjusted are the LinkSwitch-LP device to adjust the output power finalizing any design.
and the resistors R1 and R2 to adjust the output voltage. Note
that the device will provide an approximate constant current
after the point of maximum power is reached.
3-178
Rev. B 07/06
VO (V) IO (A) PO (W) LNK-LP Transformer VOR (V) R1 (kΩ) R2 (kΩ)

4 0.325 1.3 LNK562 A 63.45 24.61 3
4 04.25 1.7 LNK563 A 63.45 24.61 3
4 0.5 2 LNK564 A 63.45 24.61 3
5 0.26 1.3 LNK562 A 76.95 30.75 3
5 0.34 1.7 LNK563 A 76.95 30.75 3
5 0.4 2 LNK564 A 76.95 30.75 3
6 0.21 1.3 LNK562 A 90.45 36.88 3
6 0.28 1.7 LNK563 A 90.45 36.88 3
6 0.33 2 LNK564 A 90.45 36.88 3
7 0.18 1.3 LNK562 A 103.95 43.02 3
7 0.24 1.7 LNK563 A 103.95 43.02 3
7 0.28 2 LNK564 A 103.95 43.02 3
7.5 0.17 1.3 LNK562 A 110.7 46.09 3
7.5 0.22 1.7 LNK563 A 110.7 46.09 3
7.5 0.26 2 LNK564 A 110.7 46.09 3
8 0.16 1.3 LNK562 B 78.3 31.12 3
8 0.21 1.7 LNK563 B 78.3 31.12 3
8 0.25 2 LNK564 B 78.3 31.12 3
9 0.14 1.3 LNK562 B 87.3 35.86 3
9 0.18 1.7 LNK563 B 87.3 35.86 3
9 0.22 2 LNK564 B 87.3 35.86 3
10 0.13 1.3 LNK562 B 96.3 40.77 3
10 0.17 1.7 LNK563 B 96.3 40.77 3
10 0.2 2 LNK564 B 96.3 40.77 3
3
11 0.11 1.3 LNK562 B 105.3 44.86 3
11 0.5 1.7 LNK563 B 105.3 44.86 3
11 0.18 2 LNK564 B 105.3 44.86 3
12 0.1 1.3 LNK562 B 114.3 48.95 3
12 0.14 1.7 LNK563 B 114.3 48.95 3
12 0.16 2 LNK564 B 114.3 48.95 3
Table 9. List of Output Voltage and Current That can be Addressed With Standard Transformers and the Associated Change in LinkSwitch-LP
Device and Feedback Resistors.
3-179
Rev. B 07/06
APPENDIX A: Input Voltage Range – Universal

Output Voltage – 6V
Reference LinkSwitch-LP Standard Output Current – 330 mA
Transformer Designs
The Transformer assumes a bias winding; hence there is no
Transformer A restriction on using a 2-layer primary winding.
Transformer A was optimized for the following specifications:
60 Hz 1 min.,
Electrical
5 from Pins 1-2 to 1000 VAC
Strength
WDG #1 7 Secondary WDG #4 Pins 4-5
Bias 0.5 mm
Primary
0.2 mm 8 Turns All windings 2.7 mH ± 5% at
25 Turns 6 Triple Insulated Wire Inductance
open 100 kHz
(Pin 1 to Pin 2)
4
Resonant All windings
2 300 kHz (min)
Frequency open
WDG #2 N/C WDG #3
Shield Primary Leak-
Primary Pins 7-6 shorted 70 µH (max)
0.14 mm 0.25 mm × 3 age Inductance
108 Turns 2 8 Turns
Table 10. Electrical Specifications of Transformer A.

1
Winding Turns Start Pin Finish Pin Direction of Winding

Bias 25 5 4 Counter-Clockwise
Primary 108 1 2 Clockwise
Shield 8 NC 2 Clockwise
Secondary 8 7 6 Clockwise
PI-4141-101005
Figure 11. Electrical Diagram of Transformer A.
3 Isolation Tape 3T
7
Secondary 6
0.5 mm Triple
Insulated Wire 8T Isolation Tape 2T
2
Cut
Shield
0.25 mm Tri-filar 8T Isolation Tape 2T
2
Key:
Primary Mechanical start
0.14 mm 108T of winding
1 (Also denotes
positive polarity end)
Isolation
Tape 2T Mechanical start of
4
reverse winding
5
Positive Polarity end of
Bias reverse winding
0.2 mm 25T
PI-4142-110705
Barrier Tape 2 mm
Figure 12. Mechanical Winding Build Diagram for Transformer A.
3-180
Rev. B 07/06
APPENDIX B: Input Voltage Range – Universal

Output Voltage – 9 V
Transformer B Output Current – 220 mA
Transformer B was optimized for the following specifications:
The Transformer assumes a bias winding; hence there is no
restriction on using a 2-layer primary winding.
60 Hz 1 min.,
Electrical
5
from Pins 1-2 to 1000 VAC
Strength
WDG #1 7 Secondary WDG #4 Pins 4-5
Bias 0.5 mm Primary
0.2 mm 12 Turns All windings 2.7 mH ± 5% at
25 Turns 6 Inductance
Triple Insulated Wire open 100 kHz
(Pin 1 to Pin 2)
4
Resonant All windings
2 300 kHz (min)
Frequency open
WDG #2 Cut WDG #3
Shield Primary Leak-
Primary Pins 7-6 shorted 70 µH (max)
0.14 mm 0.25 mm × 3 age Inductance
108 Turns 2 8 Turns
1 PI-4143-092205
Table 11. Electrical Specifications of Transformer B.
Winding Turns Start Pin Finish Pin Direction of Winding

Bias 25 5 4 Counter-Clockwise
Primary 108 1 2 Clockwise
Shield 8 NC 2 Clockwise
Secondary 8 7 6 Clockwise
PI-4143-101005
Figure 13. Electrical Diagram of Transformer B.
Isolation Tape 3T
3
7
6
Secondary
0.5 mm TTW 12T Isolation Tape 2T
2
Cut
Shield
0.25 mm × 3 8T Isolation Tape 2T
2
Key:
Primary
Mechanical start
0.14 mm 108T
of winding
1 (Also denotes
positive polarity end)
Isolation
Tape 2T Mechanical start of
4
reverse winding
5
Positive Polarity end of
Bias reverse winding
0.2 mm 25T
PI-4144-110705
Barrier Tape 2 mm
Figure 14. Mechanical Winding Build Diagram for Transformer B.
3-181
Rev. B 07/06
Bobbin Drawing
Figure 15. Bobbin Drawing for all the Transformers Used in Table 9. Uses a 5+5 Pin EE16 Bobbin With Extended Creepage to Allow Safety
Compliance
Revision Notes Date

A - 10/05
B Update Figure 4. 7/06
3-182
Rev. B 07/06
®
LinkSwitch-XT
Design Guide
Introduction primary-side clamp circuit (Clampless™) for output powers

below 2 W (and up to 2.5 W with a bias winding) and thus
The LinkSwitch-XT family is designed for low power adapters dramatically reduces component count and total system cost.
and chargers (cell/cordless phones, PDAs, digital cameras, Figure 1 shows a LinkSwitch-XT based 2 W power supply
portable audio etc), as well as auxiliary supplies employed without a primary-side clamp.
in applications such as white goods. The ICs combine a high
voltage power MOSFET switch with an ON/OFF controller
in one device. It is completely self-powered from the DRAIN
Scope
pin, has a jittered switching frequency for low EMI and is fully This application note is for engineers designing an isolated
fault protected. Auto-restart limits device and circuit dissipation AC-DC flyback power supply using the LinkSwitch-XT family of
during overload, output short circuit and open loop conditions devices. It provides guidelines to enable an engineer to quickly
while hysteretic over-temperature protection disables the select key components and complete a transformer design for an
internal MOSFET during thermal faults. EcoSmart® technology application requiring either a constant voltage (CV) or constant
enables designs to easily attain <150 mW no-load consumption. voltage and constant current (CV/CC) output. To simplify the
LinkSwitch-XT is ideal for linear charger replacement circuits task of transformer design, this application note refers directly
because of its low cost and also because it can meet the efficiency to the PI Xls design spreadsheet that is part of the PI Expert
standards set forth by the California Energy Commission (CEC). design software suite.
LinkSwitch-XT is designed to operate without the need for a
CY1
100 pF
250 VAC
L1
1 mH
T1
C4
330 µF 6.2 V, 3
4 EE16 9 16 V 322 mA
5 J3
D5
1N4934
3 8
NC NC J4
RF1 VR1
D1 D2 R1 BZX79-
8.2 Ω 1N4005 1N4005 3.9 k
J1 2.5 W B5V1
1/8 W 5.1 V, 2%
R2
390 Ω
85-265 C1 C2 1/8 W
400 V 400 V
R3
1k
J2 U2 1/8 W
D PC817A
LinkSwitch-XT FB
U1 BP
LNK362P
D3 D4 S
C3
1N4005 1N4005 L2 100 nF
1 mH 50 V
PI-4162-110205
Figure 1. Basic Configuration Using LinkSwitch-XT in a Clampless Design.
3-183
Rev. B 11/05
Step-by-Step Design Procedure CC Threshold Voltage (V)

For CV only designs, this is not applicable; enter 0. For
Step 1 – Enter Application Variables: VACMIN, VACMAX, CV/CC designs, this is the expected voltage developed across
fL, VO, IO, CC Threshold Voltage, PO, Clamp and Feed- the current sense resistor at the nominal CC point. Typically, this
back type, η, Z, tC and CIN. value is in the range of 0.3 V to 1.3 V, depending on the specific
circuit used. For designs using the VBE of a bipolar transistor
Determine the input voltage range (VACMIN and VACMAX) from (~ 0.65 V) as the CC reference voltage, to maintain CC control,
Table 1 below the optocoupler LED has to stay forward biased. This may
require an additional resistor to be added in series with the CC
Nominal Input Voltage VACMIN VACMAX sense resistor to increase the overall voltage drop (> ~1.1 V).
100/115 85 132 It is this overall voltage drop that should be entered as the CC
threshold. For the exact forward drop of the optocoupler LED,
230 195 265 consult the manufacturerʼs data sheet.
Universal 85 265
Output Cable Resistance (Ω)
Table 1. Standard Worldwide Input Line Voltage Ranges. Enter the output cable resistance. If there is no output cable
enter 0. This parameter is used as part of the total output power
calculation.
Line Frequency, fL (Hz)
Enter the worst-case line frequency under which the supply Power Supply Efficiency (η)
should operate normally. This is the complete power supply efficiency measured at the
point of load, therefore including any CC sense and cable losses.
Output Voltage, VO (V) For a CV/CC design with a nominal peak power point at a voltage
Enter the output voltage. For CV/CC designs this should be the of 5.5 V and current of 0.5 A, use a value of 0.57. Use a value
typical output voltage at the nominal peak power point in the of 0.64 for a 5.5 V CV only design if no better data is available,
output characteristic. For CV only outputs, this should be the or until measurements can be made on a prototype.
specified output voltage. For designs with an output cable, enter
the voltages at the load. For multiple output designs, enter the Power Supply Loss Allocation Factor, Z
voltage for the main output from which feedback is taken. This factor represents the proportion of losses between the
primary and the secondary of the power supply.
Output Current, IO (A)
For CV/CC designs this should be the maximum output current Secondary Side Losses
at the maximum peak power point in the output characteristic Z=
3
Total Losses
(see Figure 2). For CV only outputs, this should be the maximum
output current. In multiple output designs, the output current If no better data is available then the following values are
of the main output (typically the output from which feedback recommended:
is taken) should be increased such that PO matches the sum
of the output power from all the outputs in the design. The • Bias winding feedback designs (CV): 0.5 (0.35)
individual output voltages and currents should then be entered • Optocoupler CV feedback: 0.5 (0.35)
at the bottom of the spreadsheet. • Optocoupler CV and CC feedback: 0.75 (0.6)
For designs using Filterfuse™ use the values in parenthesis,

Output
Characteristic
these take into account the additional primary side losses due
VO Limits to a typical value of ~ 50 Ω for the resistance of the Filterfuse
Nominal Peak Maximum Peak inductor
Power Point Power Point
VO(TYP)
Bridge Diode Conduction Time, tC (ms)
Enter the bridge diode conduction time. Use 3 ms if no other
data is available or until a measurement can be made on a
prototype.
0 IO
IO(TYP) Total Input Capacitance, CIN (µF)
PI-3898-120105 Enter total input capacitance using Table 2 for guidance.
Figure 2. Diagram Showing Correct Values of IO and VO to Enter
for CV/CC Designs.
3-184
Rev. B 11/05
The capacitance should be selected to keep the minimum DC

Total Input Capacitance per Watt
input voltage, VMIN > 50 V and ideally > 70 V. Insufficient
of Output Power (µF/W)
input capacitance may cause excessive line output ripple and
AC Input Half-Wave Full-Wave reduce efficiency.
Voltage (VAC) Rectification Rectification
100/115 5-8 3-4 Note: For designs that have a DC rather than an AC input, the
230 1-2 1 value of the minimum and maximum DC input voltages, VMIN
85-265 5-8 3-4 and VMAX, may be entered directly into the gray override cells
on the design spreadsheet (see Figure 3).
Table 2. Suggested Total Input Capacitance for
Different Input Voltage Ranges.
Bias Winding Feedback Optocoupler Feedback

8.5 8.5
PI-4128-092105
PI-4129-092105
8 8
7.5 7.5
Output Voltage (V)
Output Voltage (V)

7 7
6.5 6.5
Typical Output 6 6
Characteristics
5.5 5.5
5 5
4.5 4.5
4 4
0 0.05 0.1 0.15 0.2 0.25 0.3 0.36 0 0.05 0.1 0.15 0.2 0.25 0.3 0.36
Load (A) Load (A)
Cost Lower cost Higher cost

Component count Lower component count Higher component count
3
CV/CC character- No Yes
istic possible
Table 3. Summary of Comparison Between Bias Winding Feedback and Optocoupler Feedback.
ENTER APPLICATION VARIABLES AN40 Example

VO 6.00 Volts Output Voltage (main) (For CC designs enter upper CV tolerance limit)
IO 0.33 Amps Power Supply Output Current (For CC designs enter upper CC tolerance limit)
CC Threshold Voltage 0.00 Volts Voltage drop across sense resistor.
Output Cable Voltage Resistance 0.17 Ohms Enter the resistance of the output cable (if used)
PO 2.00 Watts Output Power (VO x IO + CC dissipation)
Feedback Type Opto Opto Enter 'BIAS' for Bias winding feedback and 'OPTO' for Optocoupler feedback
Enter 'YES' to add a Bias winding. Enter 'NO' to continue design without a Bias winding. Addition of
Add Bias Winding No No Bias winding can lower no load consumption
Clampless design (LNK 362 only) Yes Clampless Clampless design selected. Verify peak Drain Voltage and EMI performance
n 0.64 Efficiency Estimate at output terminals.
Z 0.50 0.5 Loss Allocation Factor (suggest 0.5 for CC=0 V, 0.75 for CC=1 V)
tC 2.90 mSeconds Bridge Rectifier Conduction Time Estimate
CIN 9.40 uFarads Input Capacitance
Input Rectification Type F F Choose H for Half Wave Rectifier and F for Full Wave Rectification

Figure 3. Application Variable Section of LinkSwitch-XT Design Spreadsheet.
3-185
Rev. B 11/05
Enter Feedback, Bias type and Clamp information achieve the maximum power capability from the selected
Select between either bias winding feedback (primary-side LinkSwitch-XT device. In general, start with the default value
feedback), Figure 9, or optocoupler feedback (secondary-side of 80 V, increasing the value when necessary to maintain KP
feedback), Figure 10. Bias winding makes use of a primary- above its lower limit of 0.6. For Clampless designs, there is less
side auxiliary winding to set the output voltage. Optocoupler flexibility in selecting the value of VOR. Increasing VOR directly
feedback directly senses the output voltage and can provide any increases the peak Drain voltage. Therefore, for Clampless
level of accuracy depending on the voltage reference selected. designs, a value of 80 V should be used and only increased
Secondary-side feedback also allows for a CV/CC output once the peak Drain voltage has been measured and adequate
characteristic. See Table 3 for a summary of feedback types. margin to BVDSS determined.
Figure 1 shows a CV only optocoupler design, Table 9 LinkSwitch-XT On-State DRAIN to SOURCE Voltage,
provides guidance for component selection for both CV and VDS (V)
CV/CC configurations. Figure 9 shows a CV only bias winding This parameter is the average on-state voltage developed across
configuration. the DRAIN and SOURCE pins of LinkSwitch-XT. By default, if
the gray override cell is left empty, a value of 10 V is assumed.
If optocoupler feedback is selected, the user still has the option Use the default value if no better data is available.
to use a bias winding. It may be used to externally power the
LinkSwitch-XT device for lower no-load consumption. In Output Diode Forward Voltage Drop, VD (V)
addition, the bias winding can be configured as a shield for Enter the average forward voltage drop of the (main) output
reduced EMI. diode. Use 0.5 V for a Schottky diode or 1 V for a PN diode
if no better data is available. By default, a value of 0.5 V is
Designs below 2.5 W output power may be able to eliminate assumed.
the primary-side clamp circuit. Clampless circuits offer the
benefit of low cost and component count, but these circuits Calculated Ripple to Peak Current Ratio, KP
rely on specific transformer construction techniques. See the Below a value of 1, indicating continuous conduction mode,
section on transformer construction for details. KP is the ratio of ripple to peak primary current (KRP). Above
a value of 1, indicating discontinuous conduction mode, KP is
For designs greater than 2.5 W, a Clampless solution is not the ratio of primary MOSFET off-time to the secondary diode
recommended. See the section on clamp design for details. conduction time (KDP). The value of KP should be in the range
of 0.6 < KP < 6 and guidance is given in the comments cell if
All the variables described above can be entered in the “Enter the value is outside this range. A value above 1 will typically
Application variables” section of the LinkSwitch-XT design result in lower noise, discontinuous conduction mode at
spreadsheet in PI Xls design software (see Figure 3). 115 VAC, where EMI measurements are made.
3
Step 2 – Enter LinkSwitch-XT, VOR, VDS, VD Variables referenced in Step 2 are found in the “Enter
LinkSwitch-XT Variables” section of the spreadsheet (see
To select the correct LinkSwitch-XT device, refer to the Figure 4).
LinkSwitch-XT data sheet power table and select based on the
input voltage, enclosure type and output power of the design. Step 3 – Choose Core and Bobbin Based on Output
Power and Enter Ae, Le, AL, BW, M, L, NS
Reflected Output Voltage, VOR (V)
This parameter is the secondary winding voltage reflected Core Effective Cross-Sectional Area, Ae (cm2)
back to the primary through the turns ratio of the transformer Core Effective Path Length, Le (cm), Core Ungapped
(during the conduction time of the output diode). The default Effective Inductance, AL (nH/turn2), Bobbin Width,
value is 80 V, however this can be increased up to 120 V to BW (mm)
ENTER LinkSwitch-XT VARIABLES

LinkSwitch-XT LNK362 LNK362 User selection for LinkSwitch-XT
Chosen Device LNK362
I^2fmin 2199 A^2Hz I^2f (product of current limit squared and frequency is trimmed for tighter tolerance)
VOR 80 Volts VOR > 90V not recommended for Clampless designs with no Bias windings. Reduce VOR below 90V
VDS 10 Volts LinkSwitch-XT on-state Drain to Source Voltage
KP 1.03 Ripple to Peak Current Ratio (0.6 < KP < 6.0)
Figure 4. LinkSwitch-XT Variables Section of LinkSwitch-XT Design Spreadsheet.
3-186
Rev. B 11/05
By default, if the Core Type cell is left empty, the spreadsheet be entered into the spreadsheet. For vertical bobbins, the margin
will select the EE16 core. The user can change this selection may not be symmetrical however, the total margin divided by
and choose an alternate core from a list of commonly available 2 should still be entered.
cores suitable for the output power (shown in Table 4). The
values shown are based on an assumed output voltage of As the margin reduces the available area for the windings,
6 V, 4 primary winding layers and the default input margin construction may not be suitable for small core sizes.
parameters as described in Step 1. Changes to these If after entering the margin, more than 4 primary layers (L) are
values will change the power capability of a given core required, it is suggested that either a larger core be selected or
size, therefore Table 4 should be used for guidance only. switch to a zero margin design using triple insulated wire for
the secondary winding.
Suggested Power Range Primary Layers, L

Core Commonly
Size Used 100/115 or 230 VAC By default, if the override cell is empty, a value of 2 is assumed.
85-265 VAC Only Primary layers should be in the range of 1 < L < 4, and in general
EE8 No <1W <1W it should be the lowest number that meets the primary current
density limit (CMA) of 150 Cmils/Amp. Values above 4 layers
EP10 No < 1.75 W < 1.75 W are possible, but the increased leakage inductance and physical
EE10 No <2W <2W fit of the windings should be considered.
EF12.6 Yes < 3.3 W < 3.3 W
For Clampless designs without a bias winding, 2 primary layers
EE13 Yes <4W <4W
must be used. This is to ensure sufficient primary capacitance
EE16 Yes <5W <6W to limit the peak Drain voltage below the BVDSS rating of the
EE1616 Yes < 5.5 W <7W internal MOSFET.
EE19 Yes < 5.6 W < 7.1 W
Secondary Turns, NS
EF20 Yes <6W <8W By default, if the grey override cell is left blank, the minimum
EF25 Yes <6W <9W number of secondary turns is calculated such that the maximum
operating flux density, BM, is kept below the recommended
Table 4. Maximum Power Capability of Cores Used in Flyback maximum. In general, it is not necessary to enter a number in
Topology
3
Core Type EE16 Suggested smallest commonly available core
M 0 mm Safety Margin Width (Half the Primary to Secondary Creepage Distance)
L 2 L > 2 or L < 1 not recommended for Clampless designs with no Bias windings. Enter L = 2
NB N/A Bias winding not used
VB N/A Volts Bias winding not used
PIVB N/A Volts N/A - Bias Winding not in use
Figure 5. Transformer Core and Construction Variables Section of Spreadsheet.
The gray override cells can be used to enter the core and bobbin the override cell except in designs where a higher operating flux
parameters directly. This is useful if a core is selected that is density is acceptable (see Minimizing Audible Nose section for
not on the list or the specific core or bobbin information differs an explanation of BM limits).
from that recalled by the spreadsheet.
Calculated Bias Winding Turns and Voltage NB, VB
Safety Margin, M (mm) Where a bias winding is used, the number of turns and voltage
For designs that require isolation but are not using triple developed are displayed. The relatively large default number of
insulated wire for the secondary winding, the width of the safety turns allows the bias to be used as a shield winding for reduced
margin to be used on each side of the bobbin should be entered EMI. If desired, the number of turns can be adjusted by entering
here. Typically, for universal input designs, a total margin of a value into the gray override cell.
6.2 mm would be required; therefore a value of 3.1 mm would
3-187
Rev. B 11/05
The variables described in step 3 are found in the “Enter Z5U, when used in clamp circuits may also generate audio noise.
Transformer Core/Construction Variables” section of the If this is the case, try replacing them with a capacitor having
spreadsheet (see Figure 5). a different dielectric, for example a film type. Flux densities
above 3000 Gauss (300 mT) are not recommended.
Step 4 – Iterate Transformer Design and Generate
Transformer Design Output Other transformer parameters calculated in the spreadsheet
are:
Iterate the design making sure that no warnings are displayed.
Any parameters outside the recommended range of values can NP - Primary Winding Number of Turns
be corrected by following the guidance given in the right hand ALG (nH/T2) - Gapped Core Effective Inductance
column. BAC (Gauss) - AC Flux Density for Core Loss Curves (0.5 x
Peak to Peak)
Once all warnings have been cleared, the output transformer ur - Relative Permeability of Ungapped Core
design parameters can be used to either wind a prototype LG (mm) - Gap Length (LG > 0.1 mm).
transformer or send to a vendor for samples. BWE (mm) - Effective Bobbin Width (Accounts for Margin
tape if used)
The key transformer electrical parameters are: OD (mm) - Maximum Primary Wire Diameter including
insulation
Primary Inductance, LP (µH) INS (mm) - Estimated Total Insulation Thickness (= 2 * film
This is the target nominal primary inductance of the thickness)
transformer. DIA (mm) - Bare conductor diameter
AWG - Primary Wire Gauge (Rounded to next smaller
Primary Inductance Tolerance, LP_TOLERANCE (%) standard AWG value)
This is the assumed primary inductance tolerance. A value of CM (Cmils) - Bare conductor effective area in circular mils
±10% is used by default, however if specific information is CMA (Cmils/Amp) - Primary Winding Current Capacity
known from the transformer vendor, then this may be overridden (150 < CMA < 500)
by entering a new value in the gray override cell.
Variables described in step 4 can be found under the
Maximum Operating Flux Density, BM (Gauss) “Transformer Primary Design Parameters” section of the
The cycle skipping mode of operation used in LinkSwitch-XT spreadsheet (see Figure 6).
To limit this audible noise generation the transformer should Step 5 – Selection of Input Stage
be designed such that the peak core flux density is below
3 1500 Gauss (150 mT). Following this guideline, and using the The input stage comprises a fusible element(s), input rectification
standard transformer production technique of dip varnishing, and line filter network. The fusible element can be either
practically eliminates audible noise. Vacuum impregnation of a fusible resistor, fuse or make use of Power Integrationʼs
the transformer should not be used due to the high primary Filterfuse technique. Here, the input inductor may also used as
capacitance and increased losses that result. Higher flux densities a fuse, typically requiring the addition of a heatshrink shroud
are possible, however careful evaluation of the audible noise to prevent incandescent material being ejected during a fault.
performance should be made using production transformer By using Filterfuse, the input stage can be simplified in saving
samples before approving the design. Audible noise may also the cost of a fusible resistor, but requiring a larger single input
be created by ceramic capacitors that use dielectrics such as capacitor. However, please verify with a safety engineer or

LP 2563 uHenries Typical Primary Inductance. +/- 10%

BM 1479 Gauss Maximum Operating Flux Density, BM<1500 is recommended
AWG 39 AWG Primary Wire Gauge (Rounded to next smaller standard AWG value)
Figure 6. Transformer Primary Design Parameters Section of Design Spreadsheet.
3-188
Rev. B 11/05
POUT ≤1W ≤3W

Suggested 85-265 + LIN + L1
DIN1-4
LIN +
VAC Input Stage
RF1 DIN1 RF2 RF1 DIN1 DIN1 3.3 mH RF1
C1**
AC C ** CIN2 AC **
CIN1 CIN2 10 µF AC IN **
IN IN1
IN CIN1 CIN2
400 V
DIN2 L2†
DIN2 DIN2 3.3 mH
PI-3772-121603 PI-3773-121603 PI-4134-110305 PI-3774-121603
Component RF1: 8.2 Ω, 1 W RF1: 8.2 W, 1 W L1, L2*: 3.3 µH, 0.06 A RF1: 8.2 W, 1 W
Selection Guide Fusible Fusible Filterfuse® Fusible
RF2: 100 Ω, 0.5 W, LIN: 470 µH-2.2 mH, C1: ≥ 5 µF/ WOUT, LIN: 470 µH-2.2 mH,
Flameproof (0.05 A-0.3 A) 400 V (0.05 A-0.3 A)
CIN1, CIN2: ≥ 3.3 µF, CIN1, CIN2: ≥ 4 µF/ WOUT, DIN1: 1N4937, 600 V CIN1, CIN2: ≥ 2 µF/ WOUT,
400 V each 400 V each DIN2: 1N4007, 1000 V 400 V each
DIN1, DIN2: 1N4007, DIN1, DIN2: 1N4007, DIN1-DIN4: 1N4007,
1 A, 1000 V 1 A, 1000 V 1 A, 1000 V
Comments **Increase value to **Increase value to *Check for safety **Increase value to
meet required differ- meet required differ- agencies approval meet required differ-
ential line ential line ential line surge
**Increase value to
meet required differ-
ential line surge
performance
Second inductor
†
may be required in
Clampless designs
Table 5. Input Filter Recommendation Based on Total Output Power.
agency if Filterfuse is acceptable. Clampless designs ≥ 2 W Designs using a Y-capacitor require the EMI filter impedance to
without a bias winding may require an additional inductor for be placed on the appropriate side of the input. Therefore when
acceptable conducted EMI. Y capacitor is returned to the DC rail, the fusible resistor(s)/
Filterfuse should be placed in the opposite side of the input. 3
If a fusible resistor is selected, it should be a flameproof type
and, depending on the differential line input surge requirements, For designs < 1 W, it is generally lower cost to use half-wave
a wire-wound type may be required. Care should be taken in rectification; and ≥ 1 W, full-wave rectification. However if
using metal or carbon film types as these can fail simply due to Filterfuse is used, even above 1 W, half wave rectification may
the inrush current when AC is connected to the supply. lower cost and should be selected accordingly.
Clampless External Clamp

≤2 W 2 W < PO ≤ 2.5 W
Bias winding required N Y N
Device LNK362 only Any
= 2 (no bias winding)
Primary layers ≤4 ≤4
≤ 4 (with bias winding)
VOR (V) ≤ 90 ≤ 130 ≤ 130
Recommended Leakage inductance < 90 µH
No restriction
Transformer Parameters Primary capacitance ≥ 50 pF
Leakage ring effect on EMI High Medium Low
Table 6. Factors to be Considered While Deciding Between a Clampless or External Clamp Design.
3-189
Rev. B 11/05
P I-3 7 7 2 -1 2 1 6 0 3 P I-3 7 7 2 -1 2 1 6 0 3
Type RCD Zener
RCLAMP CCLAMP VRCLAMP
RCLAMP2
RCLAMP2 DCLAMP DCLAMP

Suggested Primary Clamp
D D
FB FB
LinkSwitch-XT BP LinkSwitch-XT BP
S S
PI-4135-092105 PI-4136-092105
• Lower cost • Lower parts count

Advantages
• Lower EMI • Lower no-load consumption
• DCLAMP (1 A, 600 V)
- UF4005, 1N3947 or 1N4007GP
- 1N4007 improves EMI and efficiency but must be glass passivate
type (1N4007GP)
• RCLAMP2
- Not necessary when using ultra-fast (UF4005) or fast diode (1N4937)
- A value in the range of 50 Ω to 330 Ω, 1/4 W should be used with
Component Selection Guide a slow diode (1N4007GP) to limit reverse pull out current
• RCLAMP • VRCLAMP
- 47 kΩ to 200 kΩ, 1/4 W or 1/2 W - Select voltage to be 1.5 • VOR
• CCLAMP with a power rating of 0.5 W to
- 390 pF to 2.2 nF, ≥ 400 V ceramic 1 W (P6KExxx and BZY97Cxxx
or film (Note ceramic capacitors series are good examples of suit-
may create audible noise) able Zener diodes)
Table 7. Primary Clamp Recommendation (for Output Power > 2.5 W).
3
The EMI performance of half-wave rectified designs is is possible to eliminate external clamp components by careful
improved by adding a second diode in the lower return rail. This design of the transformer and bias winding. For Clampless
provides EMI gating (EMI currents only flow when the diode designs, a 2-layer primary should be used. The resultant increase
is conducting) and also doubles the differential surge-withstand in the intra-winding capacitance limits the peak drain voltage
as the surge voltage is shared across two diodes. In designs at turn off. For output powers greater than 2 W, the winding
using a single input capacitor at least one of the input diodes capacitance is not sufficient to limit peak drain voltage. Therefore
should be a fast type (trr ≤ 200 ns). This reduces ringing and a bias winding should be added to the transformer and rectified
associated increase in EMI. Table 5 shows the recommended with a standard recovery (rectifier) diode. Suitable diodes
input stage based on output power for a universal input design for the bias winding include 1N4003–1N4007. The addition
while Table 2 shows how to adjust the input capacitance for of a bias winding acts as a clamp and also reduces leakage
other input voltage ranges. inductance ringing and improves EMI. Table 6 summarizes the
requirements between Clampless designs and designs using an
Step 6 – Selection of LinkSwitch-XT external clamp.
External Components
Clampless designs should only be attempted with the LNK362
LinkSwitch-XT requires a 0.1 µF / 50 V capacitor across the device. The higher current limit of the larger family members
BYPASS and SOURCE pins. make it impractical to limit the peak drain voltage without an
external clamp.
Step 7 – Selection of Primary Clamp Circuit
For output powers > 2.5 W, either an RCD or Zener clamp is
For output powers of 2.5 W or below and using the LNK362, it suggested. Select the initial clamp components using Table
3-190
Rev. B 11/05
VR Range IF
Series Number Type Package Manufacturer
V A
11DQ50 to 11DQ60 Schottky 50-60 1 Leaded IR
MBR320 to MBR360 Schottky 20-60 3 Leaded IR/On Semi
MUR110 to MUR160 Ultrafast 100-600 1 Leaded On Semi
Table 8. List of Recommended Diodes That May Be Used With LinkSwitch-XT Designs.

1st output
VO1 6.00 Volts Main Output Voltage (if unused, defaults to single output design)
PIVS1 36.45 Volts Output Rectifier Maximum Peak Inverse Voltage
UF4001,
Recommended Diodes SB150 Recommended Diodes for this output
Pre-Load Resistor 2 k-Ohms Recommended value of pre-load resistor
CMS1 136.99 Cmils Output Winding Bare Conductor minimum circular mils
AWGS1 28.00 AWG Wire Gauge (Rounded up to next larger standard AWG value)
Figure 7. Secondary Design Parameters. Includes a Recommended Diode Part.

3
as guide. If an RCD clamp is selected, then some empirical Additionally, Table 8 lists some of the suitable Schottky and
adjustment of the values is normally required to take account ultra-fast diodes that may be use with LinkSwitch-XT circuits.
of the actual VOR and transformer leakage inductance of the The LinkSwitch-XT spreadsheet also recommends a diode based
design. As a general rule, minimize the value of the capacitor on the above guidelines (see Figure 7).
and maximize the value of the resistor. For both RCD and
Zener clamps, verify that the peak drain voltage does not Select the pre-load resistor such that it will sink 3 mA at the
exceed 650 V at the highest input voltage and peak (overload) specified voltage. Note that a pre-load resistor also increases the
output power. no-load losses, so verify acceptable no-load consumption.
Step 8 – Selection of Output Diode and Pre-Load Step 9 – Selection of Output Capacitors
Resistor
Ripple Current Rating
VR ≥ 1.25 • PIVS, where PIVS is taken from the Voltage Select the output capacitor(s) such that the ripple rating is greater
Stress Parameters section of the spreadsheet and Transformer than the calculated value, IRIPPLE from the spreadsheet.
Secondary Design Parameters.
Many capacitor manufacturers provide factors that increased
ID ≥ 2 • IO, where ID the diode rated DC current and IO is the the allowable ripple current as the capacitor temperature is
output current. reduced or the frequency of the ripple is increased from the
3-191
Rev. B 11/05
Output Type CV/CC CV Only

IO LA
(Bead)
RA RB VRFB VO
(6.8 Ω) (220 Ω) (4.3 V)
CA
QFB (100 µF
RA
16 V)
(MMST3906) (100 Ω)
RB
UFB
(390 Ω)
200%-600%
RC
Suggested Feedback (390 Ω)
VRFB (PC817D)
(5.1 V)
RD PI-3896-062504
(200 Ω)
UFB
200%-600%
(PC817D)
RSENSE
(2.4 Ω)
1W
PI-3895-070604
RSENSE: VF(UFB)/IO VRFB: VO-VF(UFB) (Use a Zener with a low

VRFB: VO-VBE(QFB) (Use a Zener with a low IZT such as the BZX79 series)
IZT such as the BZX79 series) RB: VF(UFB)/IZT(VRFB)
RB: VBE(QFB)/IZT(VRFB) RA: Limits UFB current during transients
RA: Limits base-emitter current of QFB and allows small output voltage
RC and RD: Limits UFB current adjustments.
UFB: Use high CTR device (200% - 600%) UFB: Use high CTR device (200% -
Notes QFB: Any small signal PNP transistor 600%)
(Values shown for a 5.5 V, 500 mA LA: Optional for lower output switching
output) noise (Use ferrite bead or low value
(1-3 µH) inductor rated for IO)
CA: Optional for lower output switching
3 noise (Use low ESR, 100 µF with
voltage rating >1.25 • VO)
(Values shown are for a 5 V output)
Table 9. Examples of Feedback Configurations.
data sheet specified values. This should be considered to ensure Step 10 – Choose Feedback Scheme and Select
the capacitor is not oversized, increasing the cost. Two or more Feedback Components
capacitors may be used in parallel to given a combined ripple
current rating equal to the sum of the individual capacitor Two separate feedback schemes are recommended with the
ratings. LinkSwitch-XT. The first is primary-side regulated feedback (also
called bias winding feedback), shown in Figure 9. This scheme
ESR Specification relies on the bias winding to regulate the output voltage. The
Select a low ESR type, which gives acceptable output switching bias winding voltage is divided down by a resistor divider such
ripple. The switching ripple voltage is equal to the peak secondary that the feedback pin is 1.65 V at the specified output voltage.
current multiplied by the ESR of the output capacitor. Generally The output voltage is then regulated through the turns ratio of
the selection the capacitor for ripple current rating will also the secondary and bias windings.
result in an acceptable ESR
In bias winding feedback, the bias winding may be placed
Voltage Rating closer to the secondary winding for tighter coupling and thus
Select a voltage rating such that VRATED ≥ 1.25 • VO. better regulation or it may be placed away from the secondary
winding for loose regulation of output voltage. Bias winding
3-192
Rev. B 11/05
FEEDBACK COMPONENTS
1N4003 - Recommended diode is 1N4003. Place diode on return leg of bias winding for optimal EMI. See
Recommended Bias Diode 1N4007 LinkSwitch-XT Design Guide
R1 500 - 1000 ohms CV bias resistor for CV/CC circuit. See LinkSwitch-XT Design Guide
R2 200 - 820 ohms Resistor to set CC linearity for CV/CC circuit. See LinkSwitch-XT Design Guide
Figure 8. Feedback Components Section.
feedback (for a CV only output characteristic) is shown in

Figure 9 and involves selection of two resistors R1 and R2, which T1
VO
form a divider network to regulate the bias winding. Resistors + +
R1 and R2 are also calculated in the design spreadsheet (see
Figure 8). As these resistors also draw current from the bias
winding, a combined value of 8 kΩ results in a good compromise
between no-load consumption and prevention of peak charging VB
due to leakage inductance to improve load regulation. From
DC BUS
OR
The alternate choice is secondary side optocoupler feedback. HVDC R1
Here the output signal is directly sensed and fed back to the D
FB 1.65 V
LinkSwitch-XT FEEDBACK pin via an optocoupler (see
LinkSwitch-XT BP
Figure 10). Secondary-side feedback eliminates the need for
R2
a bias winding and is more accurate then primary-side (bias S
0.1 µF
winding) feedback. However, it requires additional components
and is higher cost compared to bias winding feedback. Both of PI-4131-111605
these schemes are also summarized in Table 3.

Figure 9. Primary-Side Feedback (Bias Winding Feedback)
Tips for Clampless Designs Scheme Used in a CV Only Output Characteristic
Design.
The mechanical construction of the transformer plays a crucial
role in Clampless designs. Care should be taken to reduce the
leakage inductance and increase the intra-winding capacitance This should be avoided for Clampless designs, as this tends
of the primary winding. Intra-winding capacitance is defined as to reduce intra-winding capacitance. Even with the increased
the capacitance measured from one end of a winding to the other winding capacitance, no-load power of < 300 mW is easily
end while all other windings are open. This is best achieved possible with LinkSwitch-XT. For typical Clampless designs,
by using a 2-layer primary winding as noted in Figure 12. It the leakage inductance is below 90 µH and the intra-winding
is common to use a layer of tape between 2 primary layers. capacitance is greater than 40 pF. 3
T1 VO
+ +
6.8 Ω
220 Ω
Q1
From
DC BUS 390 Ω
OR
HVDC
D VRFB
FB
200 Ω
LinkSwitch-XT BP
S
OPTO RI_SENSE PI-4132-111605
0.1 µF
Figure 10. Secondary-Side Feedback Scheme Used for a CV/CC Output Characteristic Design.
3-193
Rev. B 11/05
Figure 11 shows the factors to be considered while deciding

the mechanical structure of the transformer.
Start design
Clampless No
LNK362
Design?
Yes
Clampless designs No Output Power

not recommended ≤2.5 W
Yes
Output Power No
≤2 W
Yes
3
Use configuration Yes Opto Coupler
shown in Figure 12 (a) Feedback?
No
Use configuration Need best Use configuration

Yes No
shown in Figure 12 (c) possible output shown in Figure 12 (b)
with slow diode for bias regulation? with slow diode for bias
PI-4133-112805
Figure 11. Flowchart For Deciding Mechanical Structure of Transformer.
3-194
Rev. B 11/05
SECONDARY BIAS
SECONDARY PRIMARY SECONDARY
PRIMARY BIAS PRIMARY

(a)
(a) (b) (c)
• No bias winding • For Clampless LNK362 designs • For Clampless LNK362 designs,
• For Clampless designs use 2 and ≤ 2.5 W only 2 primary layers and ≤ 2 W only
primary layers, LNK362 and ≤ 2 W • Bias winding feedback ideal for • Provides best output voltage
only designs that require loosely regulation with bias winding feed-
regulated output voltage back
• Improved EMI performance over
(a) & (c) due to reduction in leak-
age inductance ringing
Figure 12. Mechanical Structure of the Transformer in LinkSwitch-XT Designs.
Revision Notes Date

A - 11/05
B Formatting 11/05
3-195
Rev. B 11/05

PeakSwitch
Design Guide
Introduction modulated (jitter) to lower EMI. In addition, the ICs have

integrated functions that provide system level protection. The
The PeakSwitch family is a highly integrated, monolithic, off-line auto-restart function limits the dissipation in the MOSFET, the
switcher IC designed for use in power supplies that have to deliver transformer and the output diode during overload, output short
peak loads for short durations. Example applications include circuit and open loop conditions, while the auto-recovering
inkjet printers, audio amplifiers and DVRs. When peak power hysteretic thermal shutdown function disables MOSFET
is required, the effective switching frequency can approach switching during a thermal fault. On-time extension enables
277 kHz, allowing a transformer with a small core size to be used. more power to be delivered at low line and extends hold-up
Innovative proprietary features, such as adaptive switching cycle time. The smart AC line sense and under-voltage lockout
on-time control, adaptive current limit, AC line sense and fast (UVLO) functions enable the IC to latch-off whenever a fault
AC reset greatly simplify the design. This reduces engineering activates the auto-restart function and be reset quickly after
design time and system cost while providing complete system AC power is removed.
level protection and robust functionality.
Power Integrationsʼ EcoSmart® technology enables supplies
Each member of the family has a high-voltage power MOSFET designed around PeakSwitch family members to consume
and its controller integrated onto the same die. Internal start- <300 mW of no-load power and to meet harmonized energy
up bias current is drawn from a high-voltage current source efficiency standards such as the California Energy Commission
connected to the DRAIN pin, eliminating the need for external (CEC), EU and ENERGY STAR.
start-up components. The internal oscillator is frequency
C10 R8
1 nF 68 Ω C11
250 VAC 1/2 W 330 pF
C13 R9 C14 30 V @
D9 47 µF 0.33 Ω L2 220 nF 1.07 A Cont.
1N4148 16 V 2W 5.3 µH 50 V 2.7 A Peak
3
C17 C5 VR1 9,10 D8
4.7 nF 2.2 nF 1N4764A Q1
STPS3150 C12
1 kV 1 kV 100 V 2N3906
330 µF R10
1 50 V VR2
C4 R11 1.5 kΩ
D1-D4 1N5255B
1N4007 150 µF 3 kΩ
7,8 28 V
400 V
R3
10 kΩ RTN
R15 1/2 W 3
2.2 Ω
4
D10
R4 UF4003 VR3
C15
22 Ω C6 R12 1N5258B
2 100 nF
1/2 W 47 µF 1 kΩ 36 V
L1 50 V
5.3 mH 35 V R7
D6 4.7 kΩ
5 Q2
FR106
R2 R1 FS202DA
1.3 MΩ 1.3 MΩ D7
T1
D5 R5 R6 EE25 1N4148
1N4007 2.2 MΩ 2.4 MΩ
C3 R16
680 nF t
O
2.7 MΩ C16
X1 RT1 100 nF
PeakSwitch
10 Ω D
U1 EN/UV
PKS606Y R14
BP 100 Ω
C7
C1-C2 C8 U2 R13
F1 100 nF
3.15 A 400 V
250 VAC 50 V
J1
L J3
PE
PI-4170-060706
N
Figure 1. PeakSwitch PKS606Y, 32 W Average, 81 W Peak, Universal Input Power Supply.
3-196
Rev. D 06/06
Scope • Enter CIN input capacitance [B14]:
This application note is intended for engineers designing an Use 2 µF/WPK for universal (85-265 VAC) or single
isolated AC-DC flyback power supply using the PeakSwitch (100/115 VAC) line voltage, if output voltage droop
family of devices. It provides guidelines to enable the engineer is acceptable, or 3 µF/WPK if output voltage droop is
to quickly select key components and also complete a suitable unacceptable.
transformer design. To simplify the task, this application note
refers directly to the PI Xls design spreadsheet that is part of Use 1 µF/WPK single 230 VAC for a single (185-
the PI Expert™ power supply design software suite. 265 VAC) high-line voltage.
In addition to this application note, the reader may also find • Select PeakSwitch from drop down list or enter directly
the PeakSwitch Reference Design Kit (DAK) (containing an [B17]:
engineering prototype board, engineering report and device
samples) useful as an example of a working power supply. Select the device in the table below according to output power
Further details on downloading PI Expert, obtaining a DAK and line input voltage.
and updates to this document can be found at www.powerint.
com.
OUTPUT POWER TABLE
Quick Start 230 VAC ±15% 85-265 VAC
Readers can use the following information to quickly design a PRODUCT3 Adapter Adapter Adapter Adapter
transformer and select the components for a first prototype. Only Cont.1 Peak2 Cont.1 Peak2
the information described below needs to be entered into the
PKS603 P 13 W 32 W 9W 25 W
PI Xls spreadsheet; other parameters will be automatically
selected by the spreadsheet, based on a typical design. References PKS604 P 23 W 56 W 16 W 44 W
to spreadsheet cell locations are provided in square brackets PKS604 Y/F 35 W 56 W 23 W 44 W
[cell reference]. PKS605 P 31 W 60 W 21 W 44 W
PKS605 Y/F 46 W 79 W 30 W 58 W
• Enter AC input voltage range VACMIN, VACMAX and
PKS606 P 35 W 66 W 25 W 46 W
minimum line frequency fL [B3, B4, B5]
• Enter Nominal Output Voltage VO [B6] PKS606 Y/F 68 W 117 W 45 W 86 W
• Enter Minimum Output Voltage at Peak Load assuming an
output drop is acceptable (if applicable) [B7] Table 1. Output Power Table (See Data Sheet for Notes 1, 2 and 3).
• Enter Maximum Output Current at Peak Load or
maximum continuous load as applicable [B5] • Enter VD – forward voltage drop of the output diode 3
• Enter continuous (average) output power [B9] [B25]:
• Enter efficiency estimate:
0.5 V for Schottky diode
0.7 for universal input voltage (85-265 VAC) or single 0.7 V for PN diode
100/115 VAC (85-132 VAC) line voltage, and 0.75 for
single 230 VAC (185-265 VAC) line voltage designs. • Enter core type (if desired) from drop down menu [B43]:
Adjust the efficiency estimate accordingly, after
measuring the efficiency of the first prototype-board at A suggested core size will be selected automatically by the
peak load and VACMIN. [B11] spreadsheet if none is entered.
• Enter loss allocation factor Z [B12]: • Build transformer

• Select key components (see Steps 5 through 10)
0.65 for typical application (adjust the number • Build prototype, test and iterate the design as necessary,
accordingly after first proto-board evaluation) entering measured values into the spreadsheet where
estimates were initially used (e.g. efficiency, VMIN)
3-197
Rev. D 06/06
Step-by-Step Transformer Design Power (W)
Procedure P3
Introduction
PeakSwitch devices have current limit values that allow the

supply to deliver the specified peak power given in the power
table. With sufficient heatsinking, these power levels could P2
PI-4329-030906
be provided continuously. However, PeakSwitch is optimized
for use in applications that demand short duration, high peak
power, while delivering a significantly lower continuous or
average power. Typical peak-to-continuous ratios would be P1
PPEAK ≥ 2 × PAVE. The high switching frequency of PeakSwitch
allows a small core size to deliver the peak power but the short
duration prevents the transformer windings from overheating
∆t1 ∆t2 Time (t)
and reduces heatsinking requirement for the device.
T
As the average power increases, based on the measured transformer
Figure 2. Continuous (Average) Output Power Calculation Example.
temperature, it may be necessary to select a larger transformer so
that the current density of its windings can be decreased.
The design procedure requires both peak and continuous powers
The power table provides some guidance for peak and continuous to be specified. The peak power is used to select the PeakSwitch
(average) power levels in sealed adapters, although specific device and design the transformer for power delivery at minimum
applications may vary. For example, if the peak power condition input line voltage while continuous power (or average power if
is of very low duty cycle, say a 2 second peak occurring only at the peak load is periodic) is used for thermal design and may
power up to accelerate a hard disk drive, then the thermal rise affect the size of the transformer and the heat sink.
of the transformer is only a function of the continuous average
power. However if the peak power occurs every 200 ms for Step 1 – Enter Application Variables VACMIN, VACMAX,
50 ms, then it would need to be considered. fL, VO, IO, VO at Peak Load, η, Z, tC, CIN
Figure 2 shows how to calculate the average power requirements Determine the input voltage range from Table 2.
for a design with two different peak load conditions.
Nominal Input Voltage
3 (VAC)
VACMIN VACMAX
100/115 85 132
230 195 265
Where Px are the different output power conditions, ∆tx are the
durations of each peak power condition and T is the period of Universal 85 265
one cycle of the pulsed load condition.
Table 2. Standard Worldwide Input Line Voltage Ranges.
ENTER APPLICATION VARIABLES AN41 Example

Nominal Output Voltage (VO) 24.00 Volts Nominal Output Voltage (at continuous power)
Maximum Output Current (IO) 0.75 Amps Power Supply Output Current (corresponding to peak power)
Minimum Output Voltage at Peak Power (Assuming output droop
Minimum Output Voltage at Peak Load 24.00 Volts during peak load)
Continuous Power 6.00 6.00 Watts Continuous Output Power
Peak Power 18.00 Watts Peak Output Power
Efficiency Estimate at output terminals and at peak load. Enter
n 0.70 0.7 if no better data available
Z 0.60 Loss Allocation Factor (Z = Secondary side losses / Total losses)

tC Estimate 3.00 mSeconds Bridge Rectifier Conduction Time Estimate
CIN 47.00 47 uFarads Input Capacitance
Figure 3. Application Variable Section of PeakSwitch Design Spreadsheet.
3-198
Rev. D 06/06
PAVE = P1
Dt
d1 = T 1 ,
Line Frequency, fL with a value of 0.7 (typical) for a design where the majority
47 Hz for universal or 100/115 VAC input. 47 Hz for single of the output power is drawn from an output voltage of 12 V
230 VAC input. For half-wave rectification use fL/2. For DC or greater, and no current sensing is present on the secondary.
input enter the voltage directly into Cells B55 and B56. Once a prototype has been constructed, the measured efficiency
should be entered and the design of the transformer should be
Nominal Output Voltage, VO (V) iterated.
Enter the nominal output voltage of the main output during the
continuous load condition. Generally, the main output is the Power Supply Loss Allocation Factor, Z
output from which feedback is derived. This factor represents the proportion of losses between the
primary and the secondary of the power supply. Z factor is
Output Current, IO (A) used together with the efficiency number, to determine the
Enter the maximum output current under peak load conditions. actual power that must be delivered by the power stage. For
If the design does not have a peak load condition, then enter example, losses in the input stage (EMI filter, rectification, etc)
the maximum continuous output current. In multiple output are not processed by the power stage (transferred through the
designs, the output current of the main output (typically, the transformer), and therefore, although they reduce efficiency,
t) output from which feedback is taken) should be increased the transformer design is not impacted.
such that the peak power (or maximum continuous power as
applicable) matches the sum of the output powers from all of the
supplyʼs outputs. The individual output voltages and currents
should then be entered at the bottom of the spreadsheet [cells For designs that do not have a secondary current sense circuit,
B98 to B131] enter 0.65. For those designs that do have a secondary current
sense circuit, use a value of 0.7 until measurements can be made
Minimum Output Voltage at Peak Load (V) on a prototype. The higher number indicates larger secondary
The output voltage may be specified in PeakSwitch designs based side losses associated with the secondary side current sense
on whether or not the output voltage is allowed to droop during resistor.
peak loads. If the application requires the output to remain the
same under continuous and peak load conditions, leave this cell Bridge Diode Conduction Time, tC (ms)
empty. The spreadsheet then assumes that the output voltage Enter a bridge diode conduction time of 3.75 ms, if there is no
under peak load conditions is equal to the nominal output voltage, better data available.
i.e. the output is not allowed to droop under peak load.
Total Input Capacitance, CIN (µF)
If the application allows the output voltage to droop under peak Enter the total input capacitance, using Table 3 for guidance.
load conditions, enter the minimum acceptable voltage at peak
load. The peak power is then calculated based on the output Total Input Capacitance per 3
current and the minimum acceptable output voltage. In multiple Watt Output Power (µF/W)
output designs, if the main output is allowed to droop then all
AC Input Voltage Full Wave
the other output voltages will also droop proportionally under
(VAC) Rectification
peak load conditions.
100/115 3
Continuous Output Power (W) 230 1
Enter the continuous output power. If this entry is left blank the
85-265 3
design spreadsheet assumes that the continuous power is equal
to the peak output power. This value is used by the spreadsheet Table 3. Suggested Total Input Capacitance for Different Input
to suggest a core size. Voltage Ranges.
Peak Power (W) The capacitance is used to calculate the minimum DC voltage
This is a calculated value based on the Minimum Output Voltage and should be selected to keep the minimum DC input voltage
at Peak Load, and Maximum Output Current. It is used to (VMIN) >70 V.
calculate the required value of the primary inductance.
For designs that have a DC rather than an AC input, the value
Power Supply Efficiency, η of the minimum and maximum DC input voltages, VMIN and
Enter the estimated efficiency of the complete power supply, VMAX, may be entered directly into the override cells on the
measured at the output terminals under peak load conditions design spreadsheet shown below.
and worst-case line (generally lowest input voltage). Start
3-199
Rev. D 06/06

Figure 4. DC Input Voltage Parameters Showing Grey Override Cells for DC Input Designs.
Step 2 – Enter PeakSwitch Variables: PeakSwitch 3. Higher VOR increases the leakage inductance of the transformer,
Device, VOR, VDS, VD, VDB, VCLO, KP(STEADY STATE), KP(TRANSIENT) which reduces efficiency of the power supply.
4. Higher VOR increases the peak and RMS currents on the
Select the correct PeakSwitch device secondary side, which may increase secondary side copper
Refer to Table 1 and first select a device based on the peak and diode losses.
output power of the design. Then compare the continuous
power rating to the continuous numbers in the power table. Optimal selection of the VOR value should be based on a
If the continuous power exceeds the value given in the power reasonable engineering compromise of the factors mentioned
table, then the next largest device should be selected. Similarly, above.
if the continuous power is close to the power tableʼs power
levels, then it may be necessary to switch to a larger device PeakSwitch On-State Drain to Source Voltage, VDS (V)
based on the measured thermal performance of the prototype. This parameter is the average On-state voltage developed across
ENTER PeakSwitch VARIABLES

PeakSwitch PKS603P PKS603P PeakSwitch device
Chosen Device PKS603P
I^2f (product of current limit squared and frequency is trimmed
I^2fmin 164 A^2kHz for tighter tolerance)
VOR 110 Volts Reflected Output Voltage (VOR <= 135 V Recommended)
VDS 10 Volts PeakSwitch on-state Drain to Source Voltage
VDB 0.7 Volts Bias Winding Diode Forward Voltage Drop
VCLO 200 Volts Nominal Clamp Voltage
KP (STEADY STATE) 0.60 Ripple to Peak Current Ratio (KP < 6)
Ripple to Peak Current Ratio under worst case at peak load
KP (TRANSIENT) 0.38 (0.25 < KP < 6)
Figure 5. PeakSwitch Section of Design Spreadsheet.
3 Peak Load Switching Frequency, fs(min) (Hz) the DRAIN and SOURCE pins of the PeakSwitch device. By
This parameter is the worst-case minimum switching frequency default, if the grey override cell is left empty, a value of 10 V
based on minimum data sheet I2f is assumed for Y/F package devices, and 5 V for P package
devices. Use the default value if no better data is available.
Reflected Output Voltage, VOR (V)
This parameter is the secondary winding voltage during the Output Diode Forward Voltage Drop, VD (V)
diode conduction time, which is reflected back to the primary Enter the average forward voltage drop of the (main) output
through the turns ratio of the transformer. The default value diode. Use 0.5 V for a Schottky diode or 0.7 V for a PN diode,
is 110 V, however the acceptable range for VOR is between if no better data is available. The spreadsheet uses a default
80 V and 135 V, providing that no warnings are produced by the value of 0.7 V.
spreadsheet. For design optimization purposes, the following
should be kept in mind: Nominal Clamp Voltage, VCLO (V)
Enter the nominal clamp voltage. The clamp is used to ensure
1. Higher VOR allows increased power delivery at VMIN, which that maximum voltage developed across the DRAIN and
minimizes the value of the input capacitor and the droop of SOURCE pins of the internal MOSFET remains below the
the output voltage when the on-time extension feature is used, BVDSS specification (700 V) limit, with sufficient margin. It is
and maximizes the power delivery from a given PeakSwitch recommended that a Zener diode with a value of 200 V be used
device. in the clamp circuit. Even if an RCD clamp is used, a Zener
2. Higher VOR reduces the voltage stress on the output diodes, should be placed in parallel with the RCD circuit to provide
which in some cases may allow a Schottky diode to be used, hard clamping during fault conditions. By default, if the grey
and will thus give higher efficiency. override cell is left empty, a value of 200 V is assumed, which
is also the maximum value recommended. Lower values can
3-200
Rev. D 06/06
be used, as the VOR is reduced from 135 V, and/or in designs

with low effective (primary and reflected secondary) leakage
inductance values. Above a value of 1, indicating discontinuous conduction mode,
KP is the ratio of primary MOSFET off time to the secondary
Ripple to Peak Current Ratio, KP (STEADYSTATE) and KP (TRANSIENT) diode conduction time.
Below a value of 1, indicating continuous conduction mode, KP
is the ratio of ripple to peak primary current (Figure 6).
IR
KP ≡ KRP =
IP The value of KP should be in the range of 0.25 < KP < 6 and
guidance is given in the comments cell if the value is outside Co
IR this range. S
Primary IP
KP (STEADY STATE) is the calculated KP value under the condition E
where several switching cycles have occurred consecutively.
(a) Continuous, KP < 1 EP
KP (TRANSIENT) is the calculated minimum KP value that occurs EE
after a switching cycle has been skipped. When the drain EF
IR IP current starts from zero and ramps to the current limit, the On- EE
Primary
time for this first cycle is much longer than during steady state
operation. This reduces the Off time, reducing the time for the EE
(b) Borderline Continuous/Discontinuous, KP = 1 magnetizing inductance to reset, and causing the next cycle to EE1
start with a much higher initial current, a lower ripple current EE
PI-2587-011400 and a lower value of KP.
EF
Figure 6. Continuous Mode Current Waveform, KP ≤1.
EF
KP ≡ KDP = (1-D) x T
t
T = 1/fS
3
Primary
DxT (1-D) x T
Secondary
(a) Discontinuous, KP > 1
T = 1/fS
Primary
DxT (1-D) x T = t
Secondary
(b) Boarderline Discontinuous/Continuous, KP = 1

PI-2578-011800
Figure 7. Discontinuous Mode Current Waveform, KP ≥1.
3-201
Rev. D 06/06
Figure 8 provides an illustration of the difference between Step 3 – Enter Under-Voltage Lock Out (UVLO)
transient and steady state KP. It shows a series of drain current Variables, V_UV_TARGET (V)
waveforms for a design that does not meet KP (TRANSIENT)
limits. The line under-voltage lockout feature of PeakSwitch sets the
minimum startup voltage of the supply, prevents the power
In region (a) the KP is stable with a value of 0.38. In region (b) supply output from glitching when the input voltage is below
the control loop has caused a switching cycle to be skipped, the normal operating range, and is used to determine if the
allowing the flux in the transformer core to be completely supply should latch off during a fault. Connecting a resistor
reset as the output diode is allowed to conduct for a much from an input capacitor to the EN/UV pin enables this feature.
longer duration than in region (a). On the next switching cycle Enter the desired DC voltage across the input capacitor, at
(c), the feedback loop has enabled a switching pulse and the which the power supply should start operating. The spreadsheet
current ramps from zero rather than some initial value. This calculates both the ideal resistor value and closest standard value,
means that the on-time for switching cycle (c) is much longer together with the typical start-up voltage based on the closest
than for (a), allowing less off-time (the time during which the standard value (Figure 9). Either a resistor with a voltage rating
output diode conducts), yielding less resetting of the core flux. >375 V or two series resistors whose voltage rating sum is
Therefore, cycle (d) starts with a much larger initial current >375 V should be used.
pedestal than during the steady state conditions of (a). In the
following cycles, (e) and (f), the value of KP settles again to Step 4 – Choose Bias Winding Output Voltage, VB (V)
the KP (STEADY STATE) of 0.38.
By default, if the grey override cell is left empty, a value
The sequence of skipped cycle (b) followed by a cycle of 15 V is assumed. The user can override this value as
that gives the minimum possible off time (c) is where the needed. However, the value should be in the range of 8 V <VB
spreadsheet calculates the value of KP(TRANSIENT). In this example, <20 V. The lower value ensures adequate headroom for supplying
KP(TRANSIENT) is 0.19, below the 0.25 limit and is thus unacceptable. current into the BYPASS pin. The upper value limits the no-load
To address this problem a larger device could be selected, the input power consumption caused by high power consumption
VOR increased, or the output power reduced. in the bias winding. The number of bias winding turns, NB,
is to be used for transformer construction. An ultra-fast diode
KP(TRANSIENT) should be above a value of 0.25 to prevent the large with a voltage rating above the calculated PIVB value should
initial current pedestal from falsely triggering current limit at be selected. Select the value of resistor from the bias supply
the end of the leading edge blanking time and limiting power to the BYPASS pin to provide the maximum data sheet supply
delivery. Similar guidance is given in the comment cell on current for the selected PeakSwitch device.
how to maintain KP (TRANSIENT) within acceptable limits.
3 IR = 0.3 A
IP = 0.8 A
IR = 0.3 A
IP = 0.8 A
IR = 0.8 A IR = 0.15 A
IP = 0.8 A IP = 0.8 A
IR = 0.38 A
IP = 0.8 A
IR = 0.28 A
IP = 0.8 A
IR = 0.3 A
IP = 0.8 A
KP = 0.38 KP = 0.38 KP = 1 KP = 0.19 KP = 0.48 KP = 0.35 KP = 0.38
(a) (b) (c) (d) (e) (f)
PI-4337-031706
Drain Current
Secondary (Diode) Current
Skipped Cycle
Figure 8. Drain Current Waveform Illustrating KP(STEADY STATE) and KP(TRANSIENT).
ENTER UVLO VARIABLES

Target DC under-voltage threshold, above which the power
V_UV_TARGET 88 Volts supply with start
Typical DC start-up voltage based on standard value of
V_UV_ACTUAL 85 Volts RUV_ACTUAL
RUV_IDEAL 3.45 Mohms Calculated value for UV Lockout resistor
RUV_ACTUAL 3.30 Mohms Closest standard value of resistor to RUV_IDEAL
Figure 9. Under-Voltage Variables Section of Design Spreadsheet.
BIAS WINDING VARIABLES

VB 15.00 Volts Bias winding Voltage
NB 10 Number of Bias Winding Turns
PIVB 68 Volts Bias rectifier Maximum Peak Inverse Voltage
Figure 10. Bias Winding Variables Section of Design Spreadsheet.
3-202
Rev. D 06/06
Step 5 – Choose Core and Bobbin Based on Output required, either a larger core should be selected, or consider a
Power, and Enter AE, LE, AL, BW, M, L, NS zero margin design using triple insulated wire.
Core effective cross-sectional area, AE: (cm2) Primary Layers, L

Core effective path length, LE: (cm). By default, if the override cell is empty, a value of 3 is assumed.
Core ungapped effective inductance, AL: (nH/turn2). Primary layers should be in the range of 1 < L < 3 and in
Bobbin width, BW: (mm) general it should be the lowest number that meets the primary
Tape margin width equal to half the total margin, M (mm) current density limit of 100 Cmils/Amp (CMA). More than 3
Primary Layers, L layers are possible, but the increased leakage inductance and
Secondary Turns, NS physical fit of the windings should be considered. Due to the

Transformer Core (Verify acceptable thermal rise under
Core Type Auto EE13 continuous load conditions)
Safety Margin Width (Half the Primary to Secondary Creepage
M 0.00 mm Distance)
L 3 Number of Primary Layers
Figure 11. Transformer Variables Section of Design Spreadsheet.

high switching frequency of PeakSwitch designs, it is important
Core Type to minimize transformer leakage inductance. Therefore
By default if the core type cell is left empty, the spreadsheet split primary construction is recommended for all designs
will select the smallest commonly available core suitable for the regardless of power level. In split primary construction,
continuous output power. Available cores can be selected from half of the primary winding is placed on either side of the
the drop down list in the tool bar of the PI Xls design software. secondary and bias windings, in a sandwich arrangement.
The grey override cells can be used to enter the core and bobbin
parameter directly by a user. This is useful if the user wants to Secondary Turns, NS
use a core that is not on the list, or the specific core or bobbin By default, if the grey override cell is left blank, the minimum
information differs from that recalled by the spreadsheet. number of secondary turns is calculated such that the maximum
operating flux density BM is kept below the recommended 3
Safety Margin, M (mm) maximum of 3000 Gauss (300 mT). In general it is not necessary
For designs that require isolation but are not using triple to enter a number in the override cell except in designs where
insulated wire, the width of the safety margin to be used on a lower operating flux density is desired (see the explanation
each side of the bobbin should be entered here. For universal of BM limits).
input designs, a total margin of 6.2 mm would be required, and
a value of 3.1 mm would be entered into the spreadsheet. For Step 6 – Iterate Transformer Design and Generate
vertical bobbins, the margin may not be symmetrical. However Initial Design
if a total margin of 6.2 mm were required, then 3.1 mm would
still be entered even if the physical margin is only on one side Iterate the design making sure that no warnings are displayed.
of the bobbin. Any parameters outside the recommended range of values can
be corrected by following the guidance given in the right hand
For designs using triple insulated wire, it may still be necessary column.
to enter a small margin in order to meet the required safety
creepage distances. Many bobbins exist for each core size, Once all warnings have been cleared, the output transformer
and each will have different mechanical spacing. Refer to the design parameters can be used to either wind a prototype
specific bobbin data sheet or seek guidance from your safety transformer or sent to a vendor for samples.
expert or transformer vendor to determine what specific margin
is required. The key transformer electrical parameters are:
As the margin is reduced, the available area for the windings, Primary Inductance, LP (µH)
margin construction may not be suitable for small core sizes. This is the target nominal primary inductance of the
If after entering the margin, more than 3 primary layers (L) are transformer.
3-203
Rev. D 06/06
Primary Inductance Tolerance, LP_TOLERANCE(%) The cycle skipping mode of operation used in PeakSwitch
This is the assumed primary inductance tolerance. A value of can produce audio frequency displacements in the
12% is used by default. However, if specific information is transformer. To limit this noise, the transformer should
known from the transformer vendor, then this may be entered be designed such that the peak core flux density is below
in the grey override cell. 3000 Gauss (300 mT). Following this guideline and using the
Number of Primary Turns, NP practically eliminates audible noise. A careful evaluation of the
Total number of primary turns. For low leakage inductance it audible noise performance should be made, using production
is recommended that split primary construction be used. transformer samples before approving the design. When
ceramic capacitors that have Z5U dielectrics are used in clamp
Gapped core effective inductance, ALG (nH/T2) used by the circuits, they too may produce audible sound. They should be
transformer vendor to specify the core gap. replaced with capacitors that have a different dielectric, such
as polyester film.
Target BM (Gauss)
The value entered here is used to calculate the number of Maximum Primary Wire Diameter, OD (mm)
secondary turns. By default, a value of 2800 Guass is used, By default, if the override cell is empty, double coated wire is
slightly below the recommended maximum BM value of assumed and the standard wire diameter is chosen. The grey
3000 Gauss. This accounts for the rounding down of the number override cells can be used to enter the wire diameter directly.
of calculated secondary turns in some designs.
Primary wire size, DIA: (mm)
Maximum Operating Flux Density, BM (Gauss) Primary wire gauge, AWG
A maximum value of 3000 Gauss during normal operation is Number of primary layers, L
recommended to limit the maximum flux density under start Estimated core center leg gap length: Lg: (mm)
up and output short circuit. Under these conditions, the output Number of secondary turns, NS
voltage is low and little reset of the transformer occurs during Secondary wire size, DIAS: (mm)
the MOSFET Off-time. This may allow the transformer flux Secondary wire gauge, AWGS
density to staircase above the normal operating level. A value
of 3000 Gauss at the peak current limit of the selected device, In multiple output designs NSx, CMSx, AWGSx (where x is the
together with the built-in protection features of PeakSwitch output number) should also be used.
provides sufficient margin to prevent core saturation under
startup or output short circuit conditions.
3 LP 367 uHenries
Typical Primary Inductance. +/- 12% to ensure a minimum
primary inductance of 328 uH
Target BM 2800 Gauss Target Peak Flux Density at Maximum Current Limit
Calculated Maximum Operating Flux Density, BM < 3000 is
BM 2624 Gauss recommended
Primary Wire Gauge (Rounded to next smaller standard AWG
AWG 30 AWG value)
Figure 12. Transformer Primary Design Section of Design Spreadsheet.
TRANSFORMER SECONDARY DESIGN PARAMETERS

Lumped parameters
ISP 3.34 Amps Peak Secondary Current
ISRMS 1.74 Amps Secondary RMS Current
IRIPPLE 1.57 Amps Output Capacitor RMS Ripple Current
CMS 349 Cmils Secondary Bare Conductor minimum circular mils
Secondary Wire Gauge (Rounded up to next larger standard
AWGS 24 AWG AWG value)
Figure 13. Transformer Secondary Primary Parameters Section of Design Spreadsheet – Lumped into Single Output.
3-204
Rev. D 06/06

1st output
VO1 24 Volts Main Output Voltage (if unused, defaults to single output design)
BYV27-
Recommended Diodes 200 Recommended Diodes for this output
AWGS1 24 AWG Wire Gauge (Rounded up to next larger standard AWG value)
2nd output
VO2 Volts Output Voltage
IO2 Amps Output DC Current
Recommended Diode Recommended Diodes for this output
AWGS2 N/A AWG Wire Gauge (Rounded up to next larger standard AWG value)
DIAS2 N/A mm Minimum Bare Conductor Diameter
ODS2 N/A mm Maximum Outside Diameter for Triple Insulated Wire
3rd output
VO3 Volts Output Voltage
IO3 Amps Output DC Current
Recommended Diode Recommended Diodes for this output
3
AWGS3 N/A AWG Wire Gauge (Rounded up to next larger standard AWG value)
DIAS3 N/A mm Minimum Bare Conductor Diameter
ODS3 N/A mm Maximum Outside Diameter for Triple Insulated Wire
Total power 18 Watts Total Output Power
If negative output exists enter Output number; eg: If VO2 is

Negative Output N/A negative output, enter 2
Figure 14. Transformer Secondary Design Parameters Section of Spreadsheet – Multiple Outputs.
Step 7 – Select PeakSwitch External Components For example, if regulation is lost due to a short circuit, an open
loop or an output overload condition, and the input voltage is
Bypass Pin Capacitor sufficient to support normal operation (>25 µA into the EN/UV
For the BYPASS pin, use a 0.33 µF, 50 V ceramic capacitor or pin), then PeakSwitch will latch off. To reset the latch, the AC
a 1 µF, 50 V electrolytic, whichever is lower cost. input has to be removed long enough so that the current into
the EN/UV pin falls below the 25 µA UV threshold. Once
Step 8 – Select Under-Voltage or AC Line Sense AC is reapplied, the next time the EN/UV pin current exceeds
Components 25 µA, the supply will attempt to restart.
UVLO prevents the supply from starting up prematurely, while For some applications, the time for the EN/UV pin current to
latching shutdown protects the IC, the supply and the load from fall below 25 µA may be excessive due to the time for the bulk
fault conditions. The rectified AC input voltage that forces the input capacitor to discharge. In such cases, a fast AC reset circuit
current into the EN/UV pin to exceed 25 µA sets the UVLO can be used allowing latching shutdown to be independent of
threshold. the load and voltage on the bulk input capacitor. This prevents
3-205
Rev. D 06/06
race conditions that could cause unwanted triggering during Step 9 – Select Primary Clamp Components
brownout or on removal of the AC input.
It is recommended that either a Zener clamp or an RCD combined
Referring to Figure 1, the fast AC reset circuit is comprised with a Zener clamp be used in PeakSwitch designs. This is to
of D5, C7, R5 and R6. The incoming AC is rectified by D5 ensure that the peak drain voltage is limited to below the BVDSS
and filtered by C7 with R5 and R6 providing the line sensing of the internal MOSFET while still maximizing efficiency and
current into the EN/UV pin. When AC power is removed (after minimizing no-load consumption.
a fault has occurred and the unit has latched off), C7 discharges
quickly via R5 and R6. The value of C7 is selected so that the A standard RCD clamp designed to limit the peak drain voltage
current through R5 and R6 has fallen below the UV threshold under peak load conditions represents a significant load as the
(25 µA) after the desired reset time (~3 seconds as shown) has output power is reduced, resulting in low light load efficiency
elapsed. The capacitor should have a voltage rating greater and high no-load consumption.
than VACMAX × √2, with 400 V metal film capacitors being a
suitable choice. Figure 1 shows an example of an optimized clamp arrangement.
The addition of VR1 in series with R3 prevents C5 from
If the line UVLO function and latching shutdown are desired discharging below 100 V as the effectively switching frequency
and fast AC reset is not required, then the resistor value from reduces as the load is reduced. The value of R3 is selected so
step 3 can be connected from the UV/EN pin to the positive that the peak drain voltage is limited to an acceptable level under
side of the input bulk capacitor. worst case conditions of maximum input voltage, maximum
overload power or output short circuit and maximum ambient
If no resistors are fitted then the PeakSwitch device senses this temperature.
condition and the UV function is disabled.
The peak drain voltage should be limited to a maximum voltage
The sense resistor should be rated above 400 V, generally of 650 V under these conditions to provide margin due to
requiring either a single 0.5 W or two 0.25 W devices connected component variation. In this design the peak drain voltage was
in series. limited to 600 V. The clamp diode (D6) must be a fast or an
VR Range ID Package Manufacturer

Series Number Type
V A
IN5817 to 1N5819 Schottky 20-40 1 Leaded Vishay
SB120 to SB1100 Schottky 20-100 1 Leaded Vishay/Fairchild
3 11DQ50 to 11DQ60 Schottky 50-60 1 Leaded IR
MBR320 to MBR360 Schottky 20-60 3 Leaded IR/On Semi
MUR110 to MUR160 Ultrafast 100-600 1 Leaded On Semi
BYV28-200 Ultrafast 200 3.5 Leaded Vishay
MBR745 to MBR760 Schottky 40-60 7.5 TO220 Vishay
MBR1045 to MBR10100 Schottky 45-100 10 TO220 Vishay
BYW29-100 to BYW29-200 Ultrafast 100-200 8 TO220 Vishay
Table 4. List of Diodes Suitable For Use as the Output Rectifier.
3-206
Rev. D 06/06
ultra-fast recovery type with a reverse recovery time <500 ns. ID ≥ 2 × IO: where ID is the rated DC current and IO is the average
Under no circumstances should a slow recovery rectifier diode output current. Depending on the thermal rise and duration of
be used. The high dissipation that may result during startup or the peak load condition, it may be necessary to increase the
an output short circuit can cause failure of the diode. Resistor diode current rating once a prototype has been built. This also
R4 damps ringing for reduced EMI. applies to the amount of heatsinking necessary.
Supplies using different devices in the PeakSwitch family will Step 11 – Select Output Capacitor
have different peak primary current, leakage inductances and
therefore leakage energy. Capacitor C5 and R3 will therefore Ripple Current Rating
be optimized for each design. As a general rule minimize the The spreadsheet calculates the output capacitor ripple current
value of capacitor C5 and maximize the value of resistor R3. at peak load. Therefore the actual rating of the capacitor will
depend on the peak to average power ratio of the design. For
Step 10 – Select Output Rectifier Diode conservative design select the output capacitor(s) such that
the ripple rating is greater than the calculated value, IRIPPLE
For each output use the values of peak inverse voltage (VR) from the spreadsheet, calculated at the peak load condition.
and output current (IO) provided in the design spreadsheet However in designs with high peak to continuous (average)
to select the output diodes. Table 4 shows some commonly power ratios, the capacitor rating can be reduced based on the
available types. measured temperature rise under worst case load and ambient
temperature. If a suitable individual capacitor cannot be found
VR ≥ 1.25 × PIVS: where PIVS is taken from the Voltage then two or more capacitors may be used in parallel to achieve a
Stress Parameters section of the spreadsheet and Transformer combined ripple current rating equal to the sum of the individual
Secondary Design Parameters (Multiple Outputs). capacitor ratings.
LPF +VOUT
DFB
VRFB
COUT CPF
RFB1 CFB1
3
RBIAS
UFB1
RTN
PI-4338-031606
Feedback Bias Opto Series Feedback

Output Voltage Zener Value, Series Diode
Resistor, RBIAS Resistor, RFB1 Capacitor, CFB1
(V) VRFB (V) DFB Required?
(kΩ) (Ω) (nF)
5 4.3
8 7.5 No
12 11
1 220 100
18 16
24 22 Yes
30 28
Table 5. Zener Feedback Arrangement and Typical Component Values.
3-207
Rev. D 06/06
Many capacitor manufacturers provide factors that increase Due to the high switching frequency a high gain optocoupler
the ripple current rating as the capacitor operating temperature of 300-600% is recommended to minimize feedback delay.
is reduced from its data sheet maximum value. This should Adding a capacitor across the DC gain setting resistor further
be considered in order to ensure that the capacitor is not increases high frequency gain.
oversized.
Table 5 shows a typical implementation of Zener feedback. The
ESR Specification series drops across DFB, VRFB, RFB1 and the forward drop of the
The switching ripple voltage is equal to the peak secondary LED UFB1 determine the output voltage. Diode DFB is optional
current multiplied by the ESR of the output capacitor. It is depending on the availability of a suitable zener voltage. Resistor
therefore important to select low ESR capacitors to reduce the RBIAS provides a 1 mA bias current so that VRFB is operating
ripple voltage. In general, selecting a high ripple current rated close to its knee voltage. Resistor RFB1 sets the DC gain of
capacitor results in an acceptable value of ESR. the feedback. Both these resistors can be 0.125 W or 0.25 W,
5%. To increase high frequency gain a ceramic capacitor CFB1
Voltage Rating is placed across RFB. Selecting a Zener with a low test current
Select a voltage rating such that VRATED ≥1.25 VO. (5 mA) will minimize the current needed to bias the feedback
network, reducing no-load input power consumption.
Step 12 – Select Feedback Circuit Components
Table 6 shows a typical implementation using a reference
The feedback loop is arranged to draw the disable current IC for improved accuracy. Reference UFB2 is used to set the
(240 µA) from the ENABLE pin when the output voltage output voltage programmed via the resistor divider RS1 and RS2.
reaches regulation. Ideally the feedback loop should be able Resistor RBIAS provides the minimum operating current for UFB2
to respond to the ripple on the output capacitor cycle by cycle. while RFB1 sets the DC gain. Capacitor CFB2 rolls off the gain
LPF +VOUT
RFB1 CFB1
UFB1 RS1
RBIAS
COUT CPF
3 CFB2
UFB2
TL431
RS2
RTN
PI-4339-060506
Feedback Bias Opto Series Feedback Feedback

Output Series Resistor Sense Resistor
Resistor, RBIAS Resistor, Capacitor, Capacitor,
Voltage (V) 1, RS1 (kΩ) 1% 2, RS1 (kΩ) 1%
(kΩ) RFB1 (Ω) CFB1 (nF) CFB2 (nF)
5 27 330 10
8 91 150 22.1
12 160 100 38.3
1 100 10
18 430 100 86.6
24 470 100 102
30 510 47 110
Table 6. Example of Reference IC Feedback Configuration.
3-208
Rev. D 06/06
of UFB2 so that it does not respond to the cycle-by-cycle output +VOUT

ripple voltage. AC feedback is provided directly through the
R1
optocoupler with CFB1 increasing the gain. C1
R2 VR1
If necessary a post filter (LPF and CPF) can be added to reduce Q1
high frequency switching noise and ripple. Inductor LPF should
Q2
be in the range of 1 µH – 3.3 µH with a current rating above R3
the peak output current. Capacitor CPF should be in the range
of 100 µF to 330 µF with a voltage rating ≥1.25 × VOUT. If a R4 C2
post filter is used the optcoupler should be connected as shown RTN
before the post filter inductor and the sense resistors after the
PI-4340-031706
post filter inductor (when applicable).
Figure 15. Example of Combined Secondary Over Current and
Design Tips Overvoltage Protection Circuit.
Overcurrent and Overvoltage Protection Circuits

In some applications it may be necessary to protect the load in VR1 to be above the normal output voltage tolerance range
fault conditions such as output overcurrent (OCP) or overvoltage including the tolerance of VR1 itself. Resistor R4 is a
(OVP). For example, if the load is a motor then overcurrent 0.25 W, 100 Ω part and C2 is a small 100 nF ceramic. SCR Q2
protection can prevent the motor from overheating if it is stalled. should be selected with a current rating above the continuous
Similarly, if the feedback loop is opened then the load can be output current of the supply. For example for a 1 A output a
protected from excessive voltage by overvoltage shutdown. 2 A SCR would be a good choice. The anode of Q2 can be
directly connected to the anode of the output diode so that
The smart AC sense feature of PeakSwitch simplifies when fired, the secondary winding is shorted. This removes
implementation of such protection by providing the latching the need for the SCR to discharge the output capacitor and may
function on the primary side. Figure 15 shows a combined allow a smaller current rating device to be selected. However,
overcurrent and overvoltage shutdown circuit. The circuit is an additional ultra-fast diode must be placed in series with the
arranged so that if either overcurrent or overvoltage occurs SCR to block reverse current.
then SCR Q2 is turned on, shorting the output. Normally, this
component would have to be sized to dissipate significant power. In designs where the latching feature is not used, a larger current
However, when the arrangement is used with PeakSwitch, rating SCR may be required.
the smart AC sense and latch-off feature will shut down the
supply. Transformer Core Sizing
The high switching frequency of PeakSwitch allows the selection 3
For OCP, resistor R1 senses the output current, turning on of small core sizes that will adequately process the peak power.
transistor Q1 when the voltage drop across R1 exceeds the However, the small core size reduces the amount of winding
VBE of Q1. Resistor R2 and C1 set a time constant allowing window area available. This reduces the amount of copper for
short term peak current but triggering the OCP in a true fault. the windings, increasing winding losses.
Resistor R3 limits the current into the gate of Q2.
In designs where the ratio of peak to continuous power is low
For OVP, Zener diode VR1 is selected such that it conducts (<~2) the transformer size may need to be increased to reduce
when the output voltage exceeds the acceptable range, turning losses and transformer heating. Acceptable temperature rise
on Q2. Resistor R4 limits the Zener current and determines of the transformer should be verified at worst-case ambient
the turn-on point for Q2. Capacitor C2 provides decoupling, temperature and maximum load.
preventing false triggering of Q2 due to noise.
On-Time Extension
Transistor Q1 can be any small signal PNP bipolar transistor. The The On-time extension feature of PeakSwitch maximizes the
value of R1 is given by VBE(Q1) / IOCP, and power rating VBE(Q1) × power delivered to the load when the DC input (bulk capacitor)
IOCP where IOCP is the desired overcurrent trip point and VBE(Q1) voltage is low. This may allow the use of a smaller input
is the base-emitter drop of Q1. The initial values of R2 and C1 capacitor in designs where the output can droop under peak
are selected such that 3τ ≥ tTRIP where τ = R2 × C1 and tTRIP is the load, especially in applications where the supply must pass
minimum trip time in seconds. Use a starting value of 1 kΩ for R2 line brown-out or missing AC cycle tests. On-time extension
then optimize based on measured trip time as peak to continuous also increases the typical hold-up time.
current levels affect actual timing. Select R3 to exceed the worst
case gate trigger current of Q2 when Q1 conducts. Values of Figure 16 is an example showing the effect of On-time extension
1 kΩ to 4.7 kΩ are typical. Select the voltage rating of during a line brownout event.
3-209
Rev. D 06/06
All 50 ms/div
PI-4342-0317064
PI-4341-0317064
(A) (B)
VAC (350 V/div)
IDRAIN (2 A/div)
VOUT (15 V/div)
Figure 16. Effect of On-Time Extension Operation During Line Brown-Out. (A) Without On-Time Extension Regulation is Lost. (B) With
On-Time Regulation is Maintained.
If the ENABLE pin has not been pulled low for a period of
PI-4343-031706
IDRAIN 0.5 A/div 5 µs/div
750 µs and 1.2 ms the On-time extension feature is enabled. The
maximum duty cycle limit is then disabled and switching cycles 10%
are terminated by current limit alone. Therefore the MOSFET
On-time is only determined by the time for the primary current to
reach current limit. The Off-time of the MOSFET remain fixed
at (1-DMAX) × 1/fS, where DMAX is the maximum duty cycle and
fS the switching frequency. Once the ENABLE pin has been
pulled low, indicating the output is again in regulation, on-time
extension is disabled and the MOSFET on-time is terminated
either by current limit or maximum duty cycle.
As On-time extension is only enabled after the ENABLE pin

has not been pulled low for up to 1.2 ms the output may also
3 have been out of regulation for this duration. Therefore verify
Figure 17. Example of Adaptive Current Limit.
the output voltage ripple is acceptable.
Other Information
Adaptive Current Limit Layout Guidelines
PeakSwitch incorporates an adaptive current limit feature. If See data sheet for layout guidelines.
the current limit is reached before maximum duty cycle then the
current limit is reduced by 10%. Once a cycle is skipped the
current limit is returned to the normal maximum value. This Quick Design Checklist
simplifies compliance to power limited source safety testing See data sheet for quick design checklist.
by limiting the overload power at high line.
Revision Notes Date

A - 3/06
B Corrected formatting and text errors. 4/06
C Revised device symbol in Figure 1 to be consistent with other PI documentation (added second ground 5/06
connection).
D Revised grounding in Figure 1 to match actual implementation. 6/06
3-210
Rev. D 06/06
3-211
Rev. D 06/06
APPLICATION NOTE DI-12
Design Idea DI-12
®
TOPSwitch-GX
16 W, Universal Input, Lead Acid Battery Charger
Application Device Power Output Input Voltage Output Voltage Topology

Battery Charger TOP244P 16 W 85-265 VAC 13.55 V at 25 ˚C Flyback
Design Highlights TOP244P requires no external heatsink, using the PC board

instead.
• Lowest cost and low component count solution
• Universal input voltage replaces the need for multiple linear During the first 10 ms of operation, internal soft-start is
based designs enabled, lowering stresses on the internal power MOSFET,
• High efficiency: >75% clamp and output rectifier. Built-in switching frequency jitter
• Integrated line undervoltage detection (UV) and overvoltage reduces conducted EMI, allowing the design to meet EN55022B
(OV) power system surge protection limits with simple input filtering. Diode D1 and Zener VR1
• Constant voltage / constant current (CV/CC) output clamp the leading edge drain voltage spike caused by transformer
• Temperature compensated output voltage leakage inductance.
• Monitor input to allow state of charge measurements
Lead acid batteries for standby use are normally charged at
Operation ~2.3 V per cell and 0.1 A per Ah of capacity. Resistor R1, U2,
C9, Q1, R3, R4 and R5 form the current limit circuit. Resistor
The circuit shown in Figure 1 provides a CV/CC output for R3 controls the current limit (1.2 A typical). Resistor R5
charging lead-acid batteries in applications such as fire/burglar ensures sufficient voltage to drive the opto LED, even with the
alarms and emergency lighting. output shorted. Capacitor C9 and R4 provide compensation
and limit Q1 base current. The output voltage is controlled
The design utilizes many of the features of the TOPSwitch-GX using a TL431 voltage reference (U3). Resistors R7, R8, R9
family. Line undervoltage and overvoltage (100 V and 450 V, and RT1 program output voltage as a function of temperature
respectively) are implemented using a single resistor (R13). (Figure 3) to approximate that required by the lead-acid battery.
3 Line undervoltage detection eliminates power-up/down output
glitches, while overvoltage shutdown provides protection for
During CV operation, DC gain is set by R6. Capacitor C8, C5
and R10 provide loop compensation. Bias for U3 is provided
short line transients and longer duration power system surges, by R2.
removing the need for an input MOV. The DIP8 package of the
C7 D2 L2
D1-D4 1 nF UG4D 3.3 µH +13.55 V
1N4007V Y1
1 A, 1000 V 1 7,8
VR1 C3
P6KE 8T C2 220 µF
200 24 AWG 560 µF 35 V
Triple Insulated 35 V
5,6 R2 R7 RT1 t° R11
1 kΩ 11.8 kΩ 4.7 kΩ 27 kΩ
D1 D3
UF4005 BAV20 R1
4.7 Ω
4
2 C4
L1 C1 8T Q2
30 AWG 0.1 µF U2
22 mH 47 µF 50 V
2N4401
400 V R13 PC817A
U1 2 MΩ 3 R8 MON
TOP244P 52.7 kΩ
D M TOPSwitch-GX R6
R12
10 kΩ
C6 CONTROL 470 Ω
0.1 µF C
250 VAC C8
0.1 µF
F1 S R10
3.15 A 6.8 Ω C9
0.47 µF
Q1
C5 2N4401 R4
L U3
47 µF 470 Ω TL431
85-265 VAC 10 V R9
R3 R5 12.7 kΩ
N 0.5 Ω 0.6 Ω
1W 1W RTN
PI-3404-112502
Figure 1. TOPSwitch Lead Acid Battery Charger.
3-212
Rev. A 11/02
DI-12 APPLICATION NOTE
For battery detection and monitoring, R11, R12 and Q2 reduce

the output voltage to approximately 8 V when a 5 V signal is TRANSFORMER PARAMETERS
applied to R12. This allows the battery voltage to be measured, TDK PC40 EE22/29/6-Z,
Core Material 2
giving the state of charge. Gap for ALG = 145 nH/T
Bobbin YC 2204 (Ying Chin)

Key Design Points Primary: 56T, 30 AWG
Bias: 8T, 2 x 30 AWG
• The value of R3 sets the typical output current limit threshold Winding Details
Secondary: 8T, 28 AWG T.I.W.
given by: R3 = 0.6 / ILIMIT. (T.I.W. = Triple Insulated Wire)
• Rate R3 and R5 accordingly for power dissipation (1 W). Winding Order Primary (2-1), tape, Bias (4-3),
• Ensure total voltage across R3 and R5 is greater than (Pin Numbers) tape, Secondary (7,8-5,6)
1.5 V at ILIMIT if control to 0 V (output shorted) is required. Primary: 475 µH 10%,
• Ensure voltage at cathode of D3 is >6 V at ILIMIT. Add Inductance
Leakage: 35 µH (maximum)
additional bias winding turns, if necessary, to maintain Primary Resonant Frequency 300 kHz (minimum)
output current control to 0 V (output shorted).
• RT1: Philips part # 2322-640-54472. Table 1. Transformer Construction Information.
• Select tolerance of U2, R7, R8 and R9 to give the desired
overall CV tolerance (R7, R8 and R9 as 0.1%; R10 as 1%
2.45
PI-2267-062598
and U2 as 0.5% gives overall tolerance <2%).
2.40
16
PI-2265-040401
Charging Voltage (V/cell)

Ambient Temperature = 30 °C
2.35
14
Output Voltage (V)
Typical Limit
2.30
12
2.25
8
2.20
4
230 VAC 2.15
90 VAC -10.0 0.0 10.0 20.0 30.0 40.0 50.0 60.0
0 Temperature (°C)
0 0.2 0.4 0.6 0.8 1.0 1.2
Figure 3. Cell Charging Voltage vs Temperature.
Output Current (A) 3
Figure 2. Output Characteristic (VOUT vs IOUT)
3-213
Rev. A 11/02
Design Idea DI-16
®
TOPSwitch-GX
57 W, 230 VAC, Multi-output Set-top Box
Power Supply
Set-top Box TOP246Y 43 W cont./57 W peak 180-265 VAC 3.3 V / 5 V / 12 V / 18 V / 33 V Flyback
Design Highlights down, the drain voltage does not exceed the DC input
• High efficiency, >75% at 180 VAC voltage (drain does not switch), allowing the AC rail to rise
• Good cross-regulation with no linear regulators to 495 VAC (700 VDC BV DSS rating) without
• Line undervoltage detection (UV) and overvoltage (OV) damaging the TOPSwitch-GX.
power system surge protection • Transformer T1 is constructed using a slotted bobbin, enabling
• Meets CISPR22B/EN55022B conducted EMI limits automated transformer winding and assembly.
• Differential and common mode surge immunity to 4 kV • The transformer turns ratio is optimized (including output
(EN61000-4-5) diode forward drops) to minimize the output voltage error
• 100 kHz ring wave immunity to 4 kV (IEEE C62.41) between the 3.3 V and 5 V outputs.
• Feedback is taken from both the 3.3 V and 5 V outputs to the
reference (U3) via R10, R11 and R13. Other output voltages
Key Design Points are set by the transformer turns ratio. The 12 V, 18 V, and
• R1 (2 MΩ, 0.5 W) sets UV at 100 VDC and OV at 33 V outputs are DC-stacked on the 5 V output for enhanced
450 VDC. A 0.5 W resistor is required to give a voltage regulation and voltage centering. Pre-load resistor R14 is
rating greater than 350 VDC. required to maintain regulation of the 33 V output when
• Integrated OV shut-down protects against long duration line lightly loaded.
voltage surges (common in some countries). During shut-
PERFORMANCE SUMMARY T1 R6 D7 L6
10 Ω UF4003 33 µH, 0.2 A 33 V, 0.03 A
Output Power: 45 W Cont./ 18
57 W Peak C7 C8
D8 47 µF L2 10 µF
Regulation:
3 3.3 V:
5 V:
± 5%
± 5%
17
UF5402 50 V
C9
1000 µF
3.3 µH, 5 A
C10
50 V 18 V, 0.5 A
D9 L3 100 µF 12 V,
12 V: ± 7% UF5402 25 V 3.3 µH, 5 A 25 V 0.6 A/1.8 A pk
16
18 V: ± 7%
33 V: ± 8%
4 Efficiency:
No-Load Consumption:
≥75%
0.6 W
10
L7
Bead
C11
390 µF
35 V C12
100 µF
R14
2.7 kΩ
C24
R15 0.1 µF 25 V 0.5 W
10 Ω 50 V L4
R2 C5 3.3 µH
68 kΩ 1 nF C6 5A 5 V, 3.2 A
11
2 W 1 kV 2.2 nF
Y1 C13, C14 L5 C15
D10 1000 µF 3.3 µH 220 µF
1 BYV32-200 35 V 5A 16 V
D1-D4 14, 15
3.3 V, 3 A
1N4007V VR1
1 A, 1000 V P6KE200 C18
D11 C16, 17
MBR1045 220 µF
1000 µF 16 V RTN
D2 D1 3, 4 12, 13 35 V
D5
UF4005
D4 D3 C2 5 R7
68 µF 150 Ω
8
L1 400 V C3
D6 1 µF
20 mH 1N4148 U2
0.8 A R1 50 V LTV817
2 MΩ 9
C1 1/2 W R10
0.1 µF R8 R13
1 kΩ 9.53 kΩ 15 kΩ
X2 1% 1%
C19
RV1 D L TOPSwitch-GX 0.1 µF
275 V CONTROL 50 V
14 mm U1 C
F1 TOP246Y R9
3.15 A R3 3.3 kΩ
C3 6.8 Ω C20
RT1 R4 S X F
0.1 µF
9.09 k 22 µF
L t° 10 Ω 50 V C5 50 V U3
R11
1.7 A 1% 47 µF TL431CLP
180 - 265 10 kΩ
VAC 16 V
1%
N
PI-3395-100102
Figure 1. TOPSwitch-GX 60 W Set-top Box Output Power Supply.
3-214
Rev. B 12/02
• A soft-finish capacitor (C20), eliminates start-up output

overshoot. TRANSFORMER PARAMETERS
• Second stage LC post-filtering was used on all outputs for Orega SMT 18 core/bobbin set,
Core & Bobbin gappped for 180 nH/T2
low output ripple (L2-6 and C8, 10, 12, 15 and 18).
• Primary clamp components VR1 and D5 limit the leakage Primary Inductance
inductance induced peak drain voltage to a safe value. R2 (pins 1-5, with pins 3-4
shorted together, all other 487 µH ±10%
and C5 reduce power dissipation in VR1. windings open)
• Frequency jitter provides large EMI margins with simple
filtering. Primary Resonant
Frequency (same test 2 MHz (minimum)
conditions as above)
Leakage Inductance
WINDING INSTRUCTIONS (pins 1-5 with pins 3-4 15 µH (maximum)
Slot 1 – Start Pin 5 26T 0.25 mm Finish Pin 3 shorted, pins 10-18 shorted)
Slot 2 – Start Pin 11 1T 0.25 mm Finish Pin 14
Start Pin 14 2T 0.25 mm Finish Pin 12 Table 2. Transformer Electrical Specifications.
Start Pin 16 4T 0.25 mm Finish Pin 10
Start Pin 18 6T 0.25 mm Finish Pin 17 80
PI-2891-062502
QP Limit Line
Slot 4 – Start Pin 11 1T 0.25 mm Finish Pin 14 60
Amplitude (dBµV)
AV Limit Line
Slot 6 – Start Pin 11 1T 0.25mm Finish Pin 15
30
Start Pin 15 2T 0.25mm Finish Pin 13
-10
Quasi-Peak Scan
Average Scan EN_V_QP
-10 EN_V_AV
Start Pin 17 3T 0.25 mm Finish Pin 16 -20
Start Pin 18 6T 0.25 mm Finish Pin 17 0.15 1 10 30
Table 1. Transformer Build Information.

Frequency (MHz)
Figure 2. Conducted EMI (230 VAC, 43 W).
3
3-215
Rev. B 12/02
Design Idea DI-17
®
TOPSwitch-GX
17 W, PC Standby

PC Standby TOP242Y 17 W 200-375 VDC 3.3 V / 5 V Flyback
Design Highlights voltage, the supply is disabled until 195 VDC is reached (this
threshold is typically the lowest operating DC input voltage for
• Meets Blue Angel efficiency requirements providing output a PC main power supply with a doubler input configuration).
power of 3.9 W with 5 W input power On decreasing input voltage the supply continues to operate
• Input undervoltage (UV) detect eliminates power-up/down until regulation is lost, even if this is below the UV threshold.
output glitches Once regulation is lost the input voltage has to exceed the UV
• 132 kHz switching frequency allows small, low cost EEL19 threshold again before the supply is enabled.
based transformer to deliver 17 W
• Regulation derived from 3.3 V and 5 V outputs ensuring During the first 10 ms of operation internal soft-start is enabled.
±5% regulation on both outputs The duty cycle is linearly increased from 0% to 78% and the
• 15 V output for primary side circuitry current limit from 70% to 100%, lowering stresses on the
• Primary soft-start minimizes start-up component stresses internal power MOSFET, clamp and output rectifier. Diode D1
and Zener VR1 are used to clamp the leading-edge drain-
Operation voltage spikes caused by transformer leakage inductance. At
light load, a Zener clamp provides higher efficiency than an
The design in Figure 1 utilizes the TOP242Y and takes advantage
RCD clamp, maximizing available output power for the Blue
of many of the device’s features. Input UV is set at 195 VDC
Angel 5 W input power limit.
using a single 3.9 MΩ resistor (R1). On increasing input
CY1
1 nF
L1
+VIN 10 µH 5 V, 2 A
3 200 - 375 VDC 5
D3 C10 C11
2 1000 µF L2 100 µF
SB540 10 µH
10 V 10 V 3.3 V, 2 A
VR1
BZY97C-200 7,8
D4 C12 C13
R1 SB540 1000 µF 100 µF
3.9 10 V 10 V
MΩ 6 RTN
D1 15 V, 30 mA
UF4005
3
D2 C6 (primary
BAV21 1 µF referenced)
50 V R6
C1* 4 300 Ω
U2
0.01 µF 1 LTV817
1 kV T1 R7
510 Ω
R9 R10
D L TOPSwitch-GX 16.2 kΩ 12.1 kΩ
U1 CONTROL 1% 1%
TOP242Y C
S R5 C7
X F
6.8 Ω 0.33 µF
C2
0.1 µF C8
C5 4.7 µF U3
47 µF 10 V TL431 R11
10 kΩ
1%
PI-2963-092402
* Optional
Figure 1. TOPSwitch-GX 17 W PC Standby.
3-216
Rev. A 11/02
A secondary shunt regulator (U3) together with R6, R7, R9,

R10 and R11 are used to sense both the 3.3 V and 5 V outputs. TRANSFORMER PARAMETERS
Control loop compensation is accomplished with capacitor EEL19 (Nippon Ceramic NC-2H)
Core Material ALG = 720 nH/T
2
C7, R5 and C5. Resistor R6 sets the DC gain while R7
provides bias to the TL431 (U3). The values shown provided Bobbin EEL19 8 pin
satisfactory phase margin and bandwidth. (TDK BE-9-118CPH or equivalent)
Primary: 147T x 34 AWG
Key Design Points Winding Details
Bias: 17T x 34 AWG
3.3 V: 4T x 3 x 27 AWG T.I.W.
• Decoupling capacitor (C1) should be used if the standby 5.0 V: 2T x 3 x 27 AWG T.I.W.
(T.I.W. = Triple Insulated Wire)
supply is far from the main input bulk capacitor.
• The value of R1 is set according to the equation: Primary (1-2), tape,
Winding Order
3.3 V (7, 8-6), 5 V (5-7, 8), tape
R1 = (VUV - 2.5)/50 µA. (Pin Numbers)
Bias (3-4), tape
• Minimize secondary trace leakage inductance to improve
Primary: 2.3 mH 10%,
output cross regulation. Inductance
• Y1 capacitor (CY1) should be connected between secondary
Primary Resonant Frequency 650 kHz (minimum)
return and primary positive DC rail to minimize potential
coupling into the TOPSwitch-GX SOURCE pin during Table 1. Transformer Construction Information.
common mode line surge events.
• Connect bias winding return past SOURCE pin to route
common mode surge currents away from TOPSwitch-GX.
• A soft-finish capacitor (C8) eliminates output start-up
overshoot.
• Capacitor C2 should be located close to U1.
3-217
Rev. A 11/02
Design Idea DI-18
®
LinkSwitch
Low Cost 2.75 W CV/CC Charger or Adapter

Charger/Adapter LNK501 2.75 W 85-265 VAC 5.5 V Flyback
Design Highlights LinkSwitch derives all feedback information from the primary.
During output diode conduction, the output voltage transformed
• Replaces a linear transformer based supply at the same or through the turns ratio is sampled and held by C4. The feedback
lower cost but with much higher performance voltage across C4 (VOR) is converted into feedback current by
• <0.3 W consumption at zero load meets worldwide guidelines R1 and fed into the CONTROL pin. This feedback current
(EC’s 0.3 W, USA’s 1 W for example) regulates the output by PWM control during CV operation, and
• Extremely simple circuit – only 17 components (14 with by reducing the internal current limit during CC operation.
integrated bridge) for production-worthy design Below an output voltage of ~2 V LinkSwitch enters auto-restart,
• Primary based CV/CC output – no secondary sense limiting average output current to <50 mA. The nominal
components required transition from CV to CC occurs at 5.5 V, 0.5 A. The output
• ±10% output voltage and ±20% output current tolerances at envelope characteristic and specification limits are shown in
peak power point Figure 2.
• Fully protected for thermal, short circuit and open loop faults
• >70% efficiency Together with D5, C4 and R1 are also part of the primary clamp,
• Meets CISPR22B/EN55022B and FCC B EMI limits limiting the peak drain to source voltage due to leakage
• Meets 2.5 kV EN61000-4-5 differential surge inductance. Resistor R2 filters the leading edge leakage
• Ultra-low leakage current design <5 µA inductance spike, reducing the error in the feedback voltage.
• EE13 core for low cost and small size The CONTROL pin capacitor C3 provides energy storage for
supply startup and sets auto-restart timing during fault conditions.
Operation
The AC input is rectified and filtered by D1-D4, C1 and C2.
Key Design Points
3 Conducted EMI filtering is provided both by a π filter (C1, L1 • Select transformer turns ratio to give a VOR of 40-60 V.
and C2) and a differential filter (RF1 and C1). Together with Lower values reduce power capability, higher values
a shield in the transformer (formed from part of the primary) the increase no-load consumption.
design meets conducted EMI limits with no Y-capacitor between • R1 provides 2.3 mA into the CONTROL pin at the peak
primary and secondary. Resistor RF1 also functions as a fuse. power point at 85 VAC. The value can be adjusted to
center the output voltage.
D1, D2, D3, D4 L1
LinkSwitch
1N4005 X 4 1 mH T1
D S
5 5.5 V, 0.5 A
U1 C3 1
C 104 T 15 T C5
LNK501 0.22 µF 30 AWG 470 µF
34 AWG
50 V 4 T.I.W. 10 V
RF1 6
C4 12 T RTN
10 Ω 1 W R1
20.5 kΩ 0.1 µF 2 x 30 AWG D6
Fusible
1% 100 V 3 11DQ06
C1 C2 1A, 60 V
85 - 265 4.7 µF 4.7 µF EE13
VAC LP = 2.55 mH
400 V 400 V
D5
1N4937
R2
100 Ω
PI-3364-091602
Figure 1. LinkSwitch 2.75 W Charger Power Supply: 85 VAC to 265 VAC Input, 5.5 V, 0.5 A Output.
3-218
Rev. A 09/02
• To maintain the ±20% CC tolerance the primary inductance

tolerance should be tighter than ±10%. TRANSFORMER PARAMETERS
• Minimize zero load consumption by reducing drain node TDK PC40 EE13,
Core ALG=190 nH/T2
capacitance: Use double coated/grade 2 wire for primary
and do not vacuum impregnate. Avoid using an RC snubber Bobbin EE13 Horizontal 8 pin
across the output diode. Primary: 104T, 34 AWG
• For resistive loads increase C3 to 1 µF (electrolytic) to allow Winding Details Shield: 12 T, 2 x 30 AWG
adequate time for start-up at full load. Secondary: 15T, 30 AWG T.I.W.
Flux Band: 1T, 6 mm Cu foil
• For battery loads an output π filter is typically not required (T.I.W.: Triple Insulated Wire)
but can be added for resistive loads to reduce switching Secondary (5-6), tape, Shield
ripple. Winding Order (3-4), tape, Primary
• L1 can be replaced with a 22 Ω to 100 Ω fusible resistor for (pin numbers) (4-1), tape, Flux band
lower cost but lower efficiency (~10% reduction). (3-NC)
• Adding a 1 mA to 2 mA pre-load reduces zero load voltage Inductance Primary: 2.55 mH ±10%, Leakage: 50 µH (max.)
by ~1V but increases power consumption by ~10 mW. Primary Resonant
Frequency 300 kHz (minimum)
• Diode D6 can be replaced with a PN diode for lower cost but
reduced efficiency.
Table 1. Transformer Construction Information.
• See AN-35 and EPR-16 for more information.
0.3
PI-3362-091602
No-Load Power Consumption (W)
10
PI-3363-091402
VIN=85 V VIN=115 V
VIN=185 V VIN=265 V
0.25
8
Output Voltage (V)
0.2
6
0.15
4
0.1 85 VAC: 174 mW
115 VAC: 179 mW
185 VAC: 211 mW
2 0.05 230 VAC: 229 mW
265 VAC: 250 mW
0 0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 50 100 150 200 250 300 3
Output Current (A) Input Voltage (VAC)
Figure 2. Load Regulation - CV/CC Characteristics Figure 3. No-load Input Power Consumption.
with Limits.
3-219
Rev. A 09/02
Design Idea DI-19
®
LinkSwitch

During output diode conduction, the output voltage transformed
• Extremely simple circuit – only 15 components for by reducing the internal current limit during CC operation.
production-worthy design Below an output voltage of ~2 V, LinkSwitch enters auto-
• Primary based CV/CC output – no secondary sense restart, limiting average output current to <50 mA. The
components required nominal transition from CV to CC occurs at 5.5 V, 0.27 A. The
• ±10% output voltage and ±22% output current tolerances at output envelope characteristic and specification limits are
peak power point shown in Figure 2.
• >62% efficiency (>70% with R1 replaced by an inductor) Together with D3, C4 and R2 are also part of the primary clamp,
• Meets CISPR22B/EN55022B EMI limits with low cost limiting the peak drain to source voltage due to leakage inductance.
resistive input filter Resistor R3 filters the leading edge leakage inductance spike,
• Ultra-low leakage current design <5 µA reducing the error in the feedback voltage. The CONTROL pin
• EE13 core for low cost and small size capacitor C3 provides energy storage for supply start-up and sets
auto-restart timing during fault conditions.
Operation
Key Design Points
3 The AC input is rectified and filtered by D1, D2, C1 and C2.
Conducted EMI filtering is provided both by a π filter (C1, R1 • Select transformer turns ratio to give a VOR of 40 V
and C2) and a differential filter (RF1 and C1). Together with to 60 V. Lower values reduce power capability; higher
a shield in the transformer (formed from part of the primary) the values increase no-load consumption.
primary and secondary. Resistor RF1 also functions as a fuse. power point at 85 VAC. The value can be adjusted to center
the output voltage.
R1
68 Ω LinkSwitch
Flameproof T1 5.5 V, 0.27 A
D S
1
C U1 C3 104T 5
LNK501 0.22 µF 34 AWG
D1 15 T C5
1N4007 4 30 AWG 220 µF
RF1 C4 12T T.I.W.
2 x 30 AWG 16V
10 Ω R2 0.1 µF 6
Fusible 21 kΩ 100 V
FILM 3 RTN
85-265 C1, C2
VAC 2.2 µF EE13 D4
400 V D3 LP = 1.36 mH UF4002
1N4937 1A 100V
D2 R3
1N4007 100 Ω
PI-3367-091602
3-220
Rev. A 09/02

Core ALG= 101 nH/T2
capacitance: Use double coated/grade 2 wire for primary
and do not vacuum impregnate. Avoid using an RC snubber Bobbin EE13 Horizontal 8 pin
• For resistive loads, increase C3 to 1 µF (electrolytic) to Shield: 12T, 2 x 30 AWG
Winding Details Secondary: 15T, 30 AWG T.I.W.
allow adequate time for start-up at full load.
• For battery loads, an output π filter is typically not required (T.I.W.: Triple Insulated Wire)
• R1 can be replaced with an inductor for higher efficiency (pin numbers) (4-1), tape, Flux band
(~10% increase). (3-NC)
by ~1 V but increases power consumption by ~10 mW. Primary Resonant
300 kHz (minimum)
• Diode D4 can be replaced with a Schottky for higher Frequency
efficiency.
• See AN-35 for more information.
10 0.3
PI-3373-091402
PI-3372-091502
VIN = 85 VAC
VIN = 265 VAC
0.25
8
Output Voltage (V)
0.2
6
0.15
4
0.1
85 VAC: 180 mW
2 0.05 110 VAC: 190 mW
230 VAC: 264 mW
265 VAC: 270 mW
0
0
0 0.09 0.18 0.27 0.36 50 100 150 200 250 300 3
Input Voltage (VAC)
Output Current (A)
with Limits.
3-221
Rev. A 09/02
Design Idea DI-21
®
TOPSwitch-GX
45 W, Universal Input, LCD Monitor External Adapter

LCD Monitor TOP247Y 45 W 90-265 VAC 12 V Flyback
Design Highlights line. The larger TOPSwitch-GX selection reduces conduction

losses, raising efficiency (without circuit changes or increased
• High efficiency, >82% at 90 VAC overload power), and permits a high inductance design with a
• Low part count solution small EE30 core for higher efficiency.
• Extremely low EMI – frequency jitter helps meet EN55022B
and FCC B limits with output return grounded
• Low zero load power consumption, <250 mW at 115 VAC Key Design Points
• Line undervoltage detection (UV) and overvoltage (OV) • Nominal UV and OV set points are calculated according to
power system surge protection the equations:
• Differential and common mode surge immunity to VUV = (50 µA x R1) + 2.5 V, VOV= (R1 x 225 µA) + 2.9 V
4 kV (EN61000-4-5) • C2 provides high frequency bypass for high voltage DC bus,
• 100 kHz ring wave immunity to 4 kV (IEEE C62.41) reducing high frequency EMI.
• C3 reduces clamp Zener temperature and increases
Operation efficiency. R18 in series with C3 damps drain ringing.
• Ferrite beads, instead of RC snubbers are used on output
The design in Figure 1 utilizes the TOP247Y and takes advantage rectifier D7 to reduce zero load power consumption.
of many of the device’s features. Line UV and OV (100 V and • L5 and L6 reduce common mode conducted interference at
450 V, respectively) are implemented using a single 2 MΩ high frequencies (>10 MHz).
resistor (R1). Undervoltage eliminates power-up/down output • T1 shield winding (pins 2-3) reduces EMI. R7 damps
glitches and overvoltage provides protection for both short ringing caused by shield capacitive currents.
duration transients and long duration power system surges, • Capacitor C12 is added to eliminate output start-up overshoot.
3 removing the need for an input MOV. Resistor R8 programs the • Feedback compensation is accomplished with C11 and R12
internal current limit of the TOP247Y to 50% of nominal. The across TL431 reference amplifier U3 and correct choice of
current limit is further reduced as a function of line voltage by optocoupler series resistor R10.
R4-R6 to provide approximately constant overload power vs.
Note: Beads L3 and L4
CY1 are placed on D7
R18 anode leads L6
R4-R6 R7 2.2 nF L3 L2 1T Through
68 Ω 220 Ω Y1 Bead 3.3 µH, 5 A
2.7 MΩ 0.5 W Ferrite Bead 12 V, 3.75 A
D1 D2 VR1 L4 C10
R4 P6KE T1 Bead C7, C8 C9 100 nF
D1-D4 200 680 µF 220 µF
RL205 2 7, 9 35 V 35 V
2 A, 600 V D7
MBR20100
F1 L1 3 10,12 RTN
R5 C3
L 3.15 A 10 mH C1 4.7 nF
C2
1.4 A 100 µF 20 nF 1 kV
1 5
CX1 400 V R1 U2
90-265 330 nF 1 kV D5 D6 C6
2 MΩ 1 µF LTV817A
VAC X2 UF4005 0.5 W 1N4148
50 V R13
N t° 4 6 R11 38.3 kΩ
R6 D L TOPSwitch-GX 1 kΩ 1%
RT1 CONTROL
CONTROL U1
5 Ω, 2.8 A D3 D4 C TOP247Y
R10
GND 470 Ω C11
R9
S X F
C4 6.8 Ω 47 nF
L5 100 nF
3T Ground Wire R8 R12
Through Ferrite Bead 15 kΩ C5
47 µF C12 4.7 kΩ
10 V 22 µF
25 V U3 R14
TL431 10 kΩ
1%
PI-3003-051303
Figure 1. TOPSwitch-GX 45 W LCD Monitor Adapter.
3-222
Rev. B 05/03
80
PI-3004-073102
70
TRANSFORMER PARAMETERS
QP Limit Line EE30
60
Core Material TDK PC40EE30-Z or equivalent,
Amplitude (dBµV)
AV Limit Line
50 Gap for ALG of 1045 nH/T2
40 E130 12 pin
Bobbin
(Yih Hwa YW-016 or equivalent)
30
Shield: 10T, 2 x 28 AWG
20
Primary: 22T, 25 AWG
-10 Winding Details Bias: 3T, 4 x 28 AWG
Quasi-Peak Scan Secondary: 3T, 5 x 25 AWG T.I.W.
0 (T.I.W. = Triple Insulated Wire)
-10 EN_V_AV Tape, Shield (2-3), Tape, Primary
Winding Order (4-1), Tape, Bias (6-5), Tape,
-20
(Pin Numbers) Secondary
0.15 1 10 30
(7,8,9-10,11,12), Tape
Frequency (MHz) Primary: 490 µH 10%,
Inductance
Figure 2. 115 V Conducted EMI for LCD Monitor Supply. Meets
FCC Part 15 Class B. Primary Resonant Frequency 2 MHz (minimum)
80 Table 1. Transformer Construction Information.

PI-3005-073102
70
QP Limit Line
60
Amplitude (dBµV)
AV Limit Line
50
40
30
20
-10
Quasi-Peak Scan
0
-10 EN_V_AV
-20
0.15 1 10 30 3
Frequency (MHz)
Figure 3. 230 V Conducted EMI for LCD Monitor Supply. Meets
EN55022 EMI spec.
3-223
Rev. B 05/03
Design Idea DI-22
®
TOPSwitch-GX
70 W, 19 V External Laptop Adapter

Laptop Adapter TOP249Y 70 W 85-265 VAC 19 V Flyback
Design Highlights Operation

• High efficiency: 84% at 85 VAC (with 50 °C external The design utilizes a TOP249Y in a flyback converter providing
ambient temperature) a 70 W output in a sealed enclosure at an external ambient of
• Low component count and high power density, 7 W/in.3 50 °C. Line UV and OV (100 V and 450 V, respectively) are
• Very compact design (4.1 in. × 2.225 in. × 1.06 in.) implemented using a single 2 MΩ resistor (R1). Undervoltage
• No surface mount components required eliminates power-up/down glitches and overvoltage provides
• Low zero load power consumption, <370 mW at 115 VAC line transient and long duration power system surge protection.
• Approximately constant overload power with line voltage Resistor R10 programs the internal current limit to 75% of
• Line undervoltage detection (UV) and overvoltage (OV) nominal at the UV threshold. As a function of input voltage the
shutdown current limit is further reduced by R9 to provide approximately
• Low EMI - switching frequency jitter helps meet CISPR22B/ constant overload power. The larger TOPSwitch-GX selection
EN55022B limits reduces conduction losses, raising efficiency (without circuit
• Fully protected for overload, short circuit and thermal faults changes or increased overload power) and permits a higher
inductance design for reduced primary RMS currents, further
increasing efficiency.
C7 2.2 nF D2
C13 C12 C11
0.33 µF 0.022 µF 0.01 µF MBR20100
400 V 400 V 400 V Y1 Safety
3 1 2
D3
VR1 9
P6KE- MBR20100
C3 C14
200 2 820 µF L1 0.1 µF
BR1 25 V 200 µH 50 V 19 V, 3.6 A
RS805 D1
UF4006 11
8 A 600 V RTN
3 8
C2 C4
D4 820 µF R1 820 µF
L2 R11 1N4148 25 V 270 Ω 25 V
820 µH 2 MΩ U2
R4
6 R8 31.6 kΩ
2A 1/2 W PC817A
C1 5 4.7 Ω 1%
T1 R2
150 µF C15 R13
1 kΩ
C6 400 V TOPSwitch-GX 1 µF 562 Ω
0.1 µF D L 50 V C9 1%
X2 L3 TOP249Y 4.7 nF 50 V
CONTROL
RT1 75 µH R9 C U1
10 Ω t° 2A 13 MΩ C10
1.7 A R3 0.1 µF
R7
F1 S X F 6.8 Ω 56 kΩ 50 V
3.15 A R10 C8 U3
20.5 kΩ 0.1 µF TL431 R6
50 V C5 4.75 kΩ
85-265 VAC 47 µF 1%
16 V
PI-2691-033001
Figure 1. TOPSwitch-GX 70 W Laptop Adapter Schematic.
3-224
Rev. A 09/02
To reduce winding and diode dissipation the secondary is split

into two windings and diode OR’ed into the output capacitors TRANSFORMER PARAMETERS
(C2, 3). Regulation is provided by a secondary side reference Core Material
FPQ26/20-A
2
(U3), the output voltage sensed by R4, R13 and R6. TDK PC40 gappped for ALG = 843 nH/T
Bobbin TDK BPQ26/20-1112CP
Key Design Points Primary: 9T + 9T, 2 x 26 AWG
Shield: 1T, 8 mm x 0.015 mm Cu foil
• D1 and VR1 clamp leakage inductance spikes. A Zener Secondary 1: 3T, 3 x 26 AWG T.I.W.
Winding Details
clamp provides lower zero load consumption than an RCD Secondary 2: 3T, 3 x 26 AWG T.I.W.
clamp and higher efficiency below full load. Bias: 2T, 8 mm x 0.015 mm Cu foil
(T.I.W. = Triple Insulated Wire)
• C11 reduces VR1 dissipation, raising efficiency.
• Additional differential filtering is provided by C13 and L3. Primary (2-1), Shield (1-NC),
• C12 provides high frequency bypass, reducing high frequency Winding Order tape, Secondary 1 (12-9),
(Pin Numbers) Secondary 2 (11-8),
EMI. Bias (6-5), tape, Primary (3-2), tape
• Use foil windings to reduce dissipation and reduce leakage
inductance. Primary: 273 µH 10%,
Inductance
Leakge: 3 µH (maximum)
• Sandwich secondary winding between two halves of primary
to reduce leakage inductance. Primary Resonant
1.5 MHz (minimum)
Frequency
• High core temperature reduces saturation flux density. Keep
flux density below 3000 gauss (0.3 T) to prevent saturation.
• Use 100 V Schottky diodes for highest efficiency.
• Good layout practices should be followed:
- Locate C8, R3, C5, R9, R10 and R11 close to U1.
- Power and signal source currents should be separated,
joined using a Kelvin connection at the SOURCE pin.
- Minimize the primary and secondary loop areas to reduce
parasitic leakage and EMI.
• Consult DAK-11 and EPR-11 for more information.
3-225
Rev. A 09/02
Design Idea DI-24
®
DPA-Switch
30 W DC-DC Converter

DC-DC Converter DPA424R 30 W 36-75 VDC 5V Forward
Design Highlights Resistor R3 programs the internal DPA424R current limit to

85% of nominal, just above the level needed at full load,
• Extremely low component count limiting overload power. This feature also allows a larger
• High efficiency – 85% using Schottky rectifiers DPA-Switch to be selected, without requiring any other
• No current sense resistor or current transformer required circuit changes. A larger DPA-Switch reduces conduction losses,
• Output overload, open loop and thermal protection raising efficiency.
• Accurate input under/over voltage meets ETSI standards
• Operates to zero load Capacitors C8 and C9 provide transformer core reset; C8 also
• 400 kHz operation minimizes size of magnetics limits the leakage inductance spike on the DRAIN. Resistor R5
• Available for prototyping in DAK-21 in series with C9 damps ringing. Zener diode VR1 provides a
hard voltage clamp to limit DRAIN voltage, but is only active
Operation during transients and overload conditions.
DPA-Switch greatly simplifies the design compared to a discrete
The bias supply for U1 is provided from an auxiliary winding
implementation. Resistor R1 programs the input under/over
on output inductor L2. This gives higher efficiency than a
voltages to 33 V and 86 V, respectively, and linearly reduces the
transformer winding, since it provides a fixed voltage
maximum duty cycle with input voltage to prevent core saturation
independent of input voltage. Pre-load R13 maintains the bias
during load transients. These thresholds have tolerances that
voltage ≥8 V at zero load.
guarantee the converter is operational at 36 V, without the cost
of additional line sense components.
On the secondary, a soft finish network, C13, D3 and R7,
eliminates output turn-on overshoot. The remaining components
3 C7 1 nF R14
1.5 kV 10 Ω
provide output voltage regulation and loop compensation.
+VIN L1
36-75 VDC 1 µH 2.5 A C9
T1 2.2 nF R5
1 50 V 1.0 Ω
L2 C10 C11 C12
8 µH 6 A 100 µF 100 µF R13 1 µF
7,8 5,6 10 V 10 V 160 Ω 10 V 5 V, 6 A
C8 R1
47 pF 619 kΩ 3 7,8
200 V 1%
2 1
D2
MBRB2545CT D1
4 5,6 BAV19WS RTN
C4 U2
4.7 µF
C1 C2 20 V R7
C3 10 kΩ R10
1 µF 1 µF 1 µF
100 V 100 V 100 V
DPA-Switch 10.0 kΩ
1%
U1
DPA424R C16
U2 D3
D L BAV19WS 100 nF
CONTROL R6 R12
C 150 Ω 5.1 Ω
R9
220 Ω
C13
S X F R4 10 µF C14
R3 1.0 Ω
VR1 8.25 kΩ C5 10 V 1 µF
SMBJ 1% 220 nF U3
150 C6 LM431AIM3 R11
68 µF 10.0 kΩ
-VIN 10 V 1%
PI-2993-090602
Figure 1. DPA-Switch 30 W DC-DC Converter.
3-226
Rev. A 09/02
Key Design Points • Good layout practices should be followed:

- Locate C5, C6 and R4 close to U1, with grounds returned
• For nominal under-voltage set point VUV: to the SOURCE pin.
R1 = (VUV-2.35 V)/50 µA. VOV = (R1×135 µA)+2.5 V. - Primary return should be connected to the DPA-Switch
• Select C9 such that the core resets at VUV and the DRAIN tab, not the SOURCE pin.
voltage ≤170 V at VOV. To reduce leakage spike, C8 may - Minimize the primary and secondary loop areas to reduce
be added, adjusting C9 accordingly. parasitic leakage inductance.
• Zener VR1 safely limits the DRAIN voltage below BVDSS • Consult AN-31 and EPR-21 for additional design tips and
and guarantees transformer reset. information.
• Opto U2 should have a CTR of between 100% and 200% for
optimum loop stability.
• At zero load, maximum input voltage, the bias voltage
across C4 should be ≥8 V (12 V to 15 V under nominal TRANSFORMER PARAMETERS
conditions). PR1408
Core Siemens N87 material, ungapped
Bobbin P1408 8 pin (B&B B-096 or equivalent)
90
PI-2995-073002
Winding Details Primary: 7T + 8T, 27 AWG

Secondary: 4T x 27 AWG
85 Winding Order Primary (4-3), tape, Secondary
(pin numbers) (5,6-7,8), Tape, Primary (3-1),tape
Efficiency (%)
80 Inductance Primary: 450 µH ± 25%, Leakage 1 µH (max)
Primary Resonant
75 3.8 MHz (minimum)
Frequency
70 VIN = 36 V Table 1. Transformer Construction Information.

VIN = 48 V
VIN = 60 V
65 VIN = 72 V
OUTPUT INDUCTOR PARAMETERS
60 PR1408 Siemens N87 material
Core Gap for AL of 163 nH/T2
0 10 20 30 40
Bobbin P1408 8 pin (B&B B-096 or equivalent)
Output Power (W)
Figure 2. Efficiency vs. Output Power.
Winding Details Bias: 18T, 32 AWG, Main: 7T, 2x24 AWG 3
Winding Order
Bias (1-2), tape, Main winding (7,8-5,6), tape
(pin numbers)
Inductance
Pins 5,6-7,8 8 µH ± 10%
Table 2. Output Inductor Construction Information.
3-227
Rev. A 09/02
Design Idea DI-25
®
DPA-Switch
30 W DC-DC Converter with Synchronous Rectification

Design Highlights DRAIN voltage clamping and core reset is provided by VR1
and the gate capacitance of Q1. The bias supply for U1 is
• Extremely low component count generated from an auxiliary winding on L2, providing higher
• High Efficiency – 90% using synchronous rectification efficiency than a winding on T1.
• Accurate UV/OV allows self-driven synchronous
rectification Capacitor C17 and R15 drive the gate of Q2, C17 providing DC
• No current sense resistor or current transformer required isolation to prevent Q1 gate overstress during power down.
• Output overload, open loop and thermal protection Diode D4 resets the voltage on C17 before the next switching
• 300 kHz switching frequency – optimizes efficiency when cycle. Resistor R17 filters voltage spikes at the gate of Q1 and
simple self-driven synchronous rectification is used D2 prevents the body diode of Q1 from conducting. MOSFETs
Q1 and Q2 are connected as self-driven synchronous rectifiers.
Operation
DPA-Switch greatly simplifies the design compared to a discrete Key Design Points
implementation. Resistor R1 programs the input under/over • For nominal undervoltage set point VUV:
voltages to 33 V and 86 V, respectively, and linearly reduces the R1 = (VUV-2.35 V)/50 µA. VOV = (R1×135 µA) + 2.5 V.
maximum duty cycle with input voltage to prevent core saturation • Select time constant of R16 and C17 to be much longer than
during load transients. Tight tolerances of the UV/OV thresholds the period of one switching cycle.
determine the secondary MOSFETs gate voltage range, allowing • Zener VR1 safely limits the DRAIN voltage below BVDSS
low cost, self-driven synchronous rectification. Resistor R3 and guarantees transformer reset.
programs the internal current limit of the DPA425R to 45% of • Opto U2 should have a CTR range of 100% to 200% for
nominal. The larger DPA-Switch selection reduces conduction
3 losses, raising efficiency without design or overload penalty.
optimum loop stability.
C7
1 nF R14
L1 1.5 kV 10 Ω
+ VIN 1 µH C10 C11 C12
2.5 A 100 µF 100 µF 1 µF
36-75 VDC L2 10 V 10 V 10 V 5 V, 6 A
C17
R1 3300 pF
R15
619 kΩ 10 Ω R16
1% D1
R17 10 kΩ D2 BAV
10 Ω Q1
Si4888 19WS
DY
RTN
T1 Q2 D4
Si4888 C4
BAV19WS 4.7 µF
DY U2
20 V
R7
C1, C2 & C3 10 kΩ R10
1 µF 10.0 kΩ
100 V 1%
DPA-Switch D3 C16
U1 U2 100 nF
D L
PC357N1T BAV19WS
DPA425R
CONTROL R6 R12
C 150 Ω 5.1 Ω
R9
220 Ω
S X F
R4 C13
10 µF C14
VR1 1.0 Ω 1 µF
R3 10 V
SMBJ C5 U3
150 18.2 kΩ 220 nF C6
1% 68 µF LM431AIM3 R11
10 V 10.0 kΩ
VIN 1%
PI-3472-040903
Figure 1. DPA-Switch 30 W, 5 V, 6 A DC-DC Converter.
3-228
Rev. D 12/04
• At zero load, maximum input voltage, the bias voltage across

C4 should be ≥8 V (12 V to 15 V under nominal conditions). OUTPUT INDUCTOR PARAMETERS
• Good layout practices should be followed: RM6ILP
- Locate C5, C6 and R4 close to U1 with grounds returned Core Ferroxcube 3F3 material
Gap for ALG of 278 nH/T2
to the SOURCE pin.
- Primary return should be connected to the DPA-Switch Main: 6T, 4x26 AWG
Winding Details
Bias: 15T, 32 AWG
tab, not the SOURCE pin.
RM6ILP 8 pin
- Minimize the primary and secondary loop areas to reduce Bobbin
(EPCOS B-65821-A6008-T1 or equivalent)
parasitic leakage inductance.
Winding Order Bias (1-2), tape,
• Consult AN-31 for additional design tips and information. (pin numbers) Main Winding (7,8-5,6), tape
• Choose C17 to provide adequate gate charge to Q2 at low
Inductance 8 µH ±10%
line (typically 5 V) and to limit Q2 gate to a safe voltage at
high line (typically less than 20 V). Table 2. Output Inductor Construction Information.
100
PI-3489-040303
90 EFD20 Ungapped
Core
Ferroxcube EFD20-3F3
Efficiency (%)
EFD20 10 pin
80 Bobbin
(B&B B-052 or equivalent)
VIN = 36 VDC
Primary: 8T + 8T, 25 AWG
VIN = 48 VDC Winding Detail
Secondary: 4T, 0.002" Cu Foil
70 VIN = 72 VDC
Primary (5-3), tape,
Winding Order
Secondary (6,7-9,10), tape,
(pin numbers)
60 Primary (3-1), tape
Inductance Primary: 307 µH ±25%, Leakage: 1 µH (max.)
50 Primary Resonant
Frequency 3 MHz (minimum)
0 5 10 15 20 25 30
Output Power (W) Table 1. Transformer Construction Information.
Figure 2. DPA-Switch 30 W, 5 V Synchronous
Rectifier Efficiency vs. Output Power.
3
3-229
Rev. D 12/04
Design Idea DI-26
®
TOPSwitch-GX
7 W Digital Video Broadcast-Terrestrial (DVB-T) Supply

DVB-T TOP242P 7W 195 to 265 VAC 2.5 V / 3.3 V / 6.2 V / 30 V Flyback
Design Highlights Resistor R12, C10 and L2 filter conducted EMI; R12 is a flame-
proof fusible type, also functioning as a fuse. For lower cost, if
• Meets CISPR22B/EN55022B conducted EMI limits with
the supply does not have to meet conducted EMI with the output
output return grounded
connected to earth ground, the common mode choke can be
• <0.5 W input power at zero load
replaced with a π filter. A Zener clamp (D11 and VR1) was
• 132 kHz operation and programmable current limit allows
selected over an RCD clamp to minimize zero load consumption.
small, low cost EF16 transformer for 7 W output
Secondary side feedback is taken from the 3.3 V ±5% output
• Low component count design occupies 80 x 30 x 16 mm
since this has the tightest tolerance requirement. The 2.5 V ±5%
• Integrated soft-start reduces start-up component stresses
output is derived directly from the 3.3 V output using D4. A
60 V Schottky was selected for D1, since the slightly higher
Operation forward drop centers the 6.2 V and 30 V outputs.
The TOPSwitch-GX flyback supply provides 4 outputs,
delivering 7 W from a 230 VAC ±15% input. The TOP242P Post-filters (L1/C3, L2/C12 and R1/C5) reduce output noise
was selected for low cost, the DIP-8 package removing the need and ripple to <±1% of the respective output voltage. A soft-
for an external heat sink. Resistor R7 programs the internal finish capacitor (C7) eliminates output turn-on overshoot.
TOP242P current limit to 78% of nominal, just above the level
needed for full load at low line. This feature allows a more Key Design Points
continuous transformer design for better efficiency and cross-
• The transformer is designed to operate in continuous mode
regulation, without requiring a larger core size.
for tight secondary cross-regulation.
C15 2.2 nF
3 Y1
D3
UF4002
R1
T1 150 Ω 30 V, 5 mA
8
C5
L2 10 µF
1 D2 4.7 µH
SB140 50 V
1.8 A 6.2 V, 0.4 A
7
D7-D10 VR1
1N4005 P6KE200
C4 C12
L1 47 µF
D1 470 µF 4.7 µH 35 V
SR506 10 V 1.8 A
D11 3.3 V, 0.5 A
BYW95C 6
C1, C2 2.5 V, 1 A
C9 220 µF C3
2 47 µF
6.8 µF 35 V D4
400 V 35 V 1N5400 RTN
5
R6
L3 3 75 Ω
D6 U3
10 mH PC817
0.1 A 1N4148 C8
1 µF R2
50 V R5
TOPSwitch-GX 4 1 kΩ 15 kΩ
U1 1%
TOP242P
C10 D M R7
10 kΩ C6
47 nF 0.1 µF
X2 CONTROL
C
R12 R11 R4
8.2 Ω 6.8 Ω C7 3.3 kΩ
Fusible S C13 10 µF
C14 U2
100 nF 47 µF 16 V R3
LMV431 9.1 kΩ
10 V
195-265 1%
VAC
PI-3023-0916102
Figure 1. TOPSwitch-GX 7 W Multiple Output Supply for DVB-T.
3-230
Rev. A 09/02
• Safety Y1 capacitor C15 is connected between secondary 5
PI-3021-080202
return and primary DC rail to minimize noise coupling 4 2.5 V
3.3 V
during AC common mode line transients. 6.2 V
3
Line Regulation (%)

• Good layout practices should be followed: 3.0 V
- Locate C13, R11 and C14 close to U1, with grounds 2
returned to the SOURCE pin. 1
- Minimize the primary and secondary loop areas to reduce 0
parasitic leakage inductance, improve EMI and cross-
-1
regulation.
-2
-3
TRANSFORMER PARAMETERS -4
Core Material EF16 gapped for 190 nH/T2 -5

190 210 230 250 270
Bobbin EF16-8 pin
Line Voltage (VAC)
Bias: 17T, 35 AWG Figure 2. Full Power Line Regulation.
3.3 V Secondary: 4T, 4 x 26 AWG T.I.W.
Winding Details
6.2 V Secondary: 3T, 26 AWG T.I.W.
30 V Secondary: 29T, 30 AWG T.I.W. 80
PI-3022-080202
(T.I.W. = Triple Insulated Wire) 70
Winding Order Primary (1-2), Tape, Bias (3-4), QP Limit Line
60
(Pin Numbers) Tape, 3.3 V (5-6), 5 V (6-7), 30 V (7-8)
Amplitude (dBµV)
AV Limit Line
Inductance Primary: 2.1 mH 10%, Leakge: 50 µH (max.) 50
Primary Resonant 40
650 kHz (minimum)
Frequency
30
Table 1. Transformer Construction Information. 20
-10
Voltage Load Regulation (%) 0

Range EN_V_QP
(V) (%) -10 -7 -4 -3 -2 -1 0 1 2 3 4 7 -10 Quasi-Peak Scan EN_V_AV
Average Scan
2.5 10-100 -20
3.3 10-100 0.15 1 10 30
6.2
30
10-100
100 Frequency (MHz) 3
Table 2. Worst Case Output Cross-Regulation-all Outputs Taken Figure 3. Conducted EMI, 230 VAC, Full Power, Output Earth
from Minimum to Maximum Load. Grounded.
3-231
Rev. A 09/02
Design Idea DI-29
®
DPA-Switch
25 W Flyback DC-DC Converter

DC-DC Converter DPA425R 25 W 36 - 75 VDC 7V Flyback
Design Highlights Resistor R3 programs the internal current limit of the DPA425R
to 50% of nominal. The larger DPA-Switch selection reduces
• Extremely low component count conduction losses, raising efficiency without circuit changes or
• High efficiency – 85% using Schottky rectifiers increased overload power.
• No current sense resistor or transformer required
• Accurate input under/over voltage meets ETSI standards Zener VR1 clamps leakage inductance spikes, keeping the
• Operates to zero load with no pre-load required DRAIN voltage below BVDSS. The bias supply for U1 is provided
• Output overload, open loop and thermally protected from an auxiliary flyback transformer winding.
• 400 kHz operation minimizes size of magnetics
On the secondary, a snubber across D2 (C9, R5 and R13) limits
Operation the secondary leakage inductance spikes generated by diode
reverse recovery. Inductor L2, C13 and C14 form a post-filter
to reduce high frequency output switching ripple. A soft-finish
implementation. Resistor R1 programs the input under/over
network, C18, D3 and R7, eliminates output turn-on overshoot.
voltages to 33 V and 86 V, respectively. Including tolerances
The remaining components provide output voltage regulation
these thresholds guarantee the converter is operational between
and loop compensation.
36 V and 75 V, without the cost of additional line sense
components.
R5
6.8 Ω
C9
C7 1 nF 2.2 nF R13
R14 50 V 6.8 Ω
1.5 kV 10 Ω
3 + VIN L1
C10 C11 C12
100 µF 100 µF 100 µF
L2
300 nH C13 C14
100 µF 100 µF C15
36-75 VDC 1 µH 2.5 A 10 V 10 V 10 V 6A
10 V 10 V 1 µF 7 V, 3.57 A
T1
1 7,8
D2 MBRB2545CT RTN
FL 5,6
D1 BAV19WS
2
C23
4.7 µF
4 3 20 V
R1 R7 U2 R10
619 kΩ U2 10 kΩ 18.2 kΩ
1% 1%
C1 C2 C3
1 µF 1 µF 1 µF
100 V 100 V 100 V
DPA-Switch C16
U1 D3 100 nF
DPA425R BAV19WS
D L R6 R12
150 Ω 5.1 Ω
CONTROL
C C17 R9
1 µF 220 Ω
C18
S X F R4 10 µF
R3 1.0 Ω
VR1 15 kΩ C5 10 V
SMBJ 1% 220 nF U3
130 C6 R11
68 µF LM431AIM3 10.0 kΩ
-VIN 10 V 1%
PI-3012-120902
Figure 1. DPA-Switch Flyback DC-DC Converter Schematic.
3-232
Rev. B 12/02
Key Design Points

Transformer Parameters
• For nominal under-voltage set point VUV:
R1 = (VUV-2.35 V)/50µA. VOV = (R1×135 µA)+2.5 V. PR1408
Core Material Siemens N87
• Zener VR1 voltage is 130 V to safely limit the DRAIN Gap for 340 nH/T
2
voltage below VDSS of 200 V. Bobbin P1408 8 pin (B&B B-096 or equivalent)
• Opto U2 should have a CTR of between 100% and 200% for
Primary: 6T + 6T, 2 x 27 AWG
optimum loop stability. Winding Details Secondary: 3T, 4 x 25 AWG
• Set resonance of L2 and C13 + C14 to beyond loop crossover Bias: 6T, 32 AWG
frequency (typically 5% to 10% of switching frequency). Primary (4-FL), tape, Bias (2-3), tape,
Winding Order
• Good layout practices should be followed: Secondary (5,6-7,8), tape,
(pin numbers)
- Locate C5, C6 and R4 close to U1, with grounds returned Primary (FL-1), tape
to the SOURCE pin. Inductance Primary: 49 µH ±10%, Leakage: 1 µH (max)
- Primary return should be connected to the DPA-Switch Primary Resonant 3.8 MHz (minimum)
tab, not the SOURCE pin. Frequency
- Minimize the primary and secondary loop areas to reduce
parasitic leakage inductance. Table 1. Transformer Construction Information.
100
PI-3033-081402
80
Efficiency (%)
60
40
36 VDC
20 48 VDC
60 VDC
72 VDC
0
0 5 10 15 20 25
Output Current (W)

3-233
Rev. B 12/02
Design Idea DI-30
®
TOPSwitch-GX
180 W PC Main SFX Supply

PC Main TOP249Y 180 W 90-130 VAC / 180-265 VAC 3.3 V / 5 V / 12 V / -12 V Forward
Design Highlights C3) balancing circuit, operating only as needed to minimize

zero-load power consumption.
• 180 W cont. (200 W peak) in PC SFX form factor
• Includes passive power factor correction (PFC) Resistors R3, R5 and R6 implement start-up undervoltage
• TOPSwitch-GX integrated features enable extremely low lockout, which prevents the supply from starting below
component count 180 VDC. Components R4, R14, Q1 and R30 implement an
• Meets 1 W standby spec (0.91 W input, 0.5 W output) independent undervoltage using the X pin, which allows the
• High efficiency (71% minimum) supply to continue delivering power all the way down to
• Integrated line undervoltage and overvoltage detection 140 VDC (increasing holdup time). Resistor R7 provides
• Low EMI due to frequency jitter additional hysteresis.
• SOURCE referenced TO-220 tab lowers conducted EMI
• Maximum duty cycle reduction (DCMAX) prevents transformer The primary side components D1, VR3-5 and C4, along with
saturation for fault and transient loads secondary side C9 and R30, implement the Zener/capacitor
• Uses conventional magamp for 3.3 V output reset/clamp circuit. This circuit provides reset voltage for the
• Meets CISPR22B/EN55022B conducted EMI transformer and clamps the DRAIN pin voltage to a safe level
(<~600 V) under all conditions.
Operation
The reset circuit works in conjunction with the DCMAX reduction
TOPSwitch-GX integrates many features designed for use with circuit (R8, R36, C22, VR19 and D18) to limit the maximum
forward converters. Passive power factor correction (PFC) is duty cycle and prevent transformer saturation under fault and
implemented using inductors LPFC1 and LPFC2. Transistors transient conditions.
3 Q4, Q6, R1, R2, R3, R5, and R6 form an active capacitor (C2, C10
1 nF
50 V
Coupled
choke
L1
13 µH
5 4
+12 V
2 14 C11
C4 D7 7, 8 1, 2
R1 R3 1000 µF
2.2 nF 2.2 MΩ MBR3045 C9
330 kΩ 1 kV 16 V L2
R4 47 nF 0.5 µH
2.2 MΩ 13 50 V 6 3
R5 +5 V
D1 R30
BR1 1N5407 180 kΩ 1Ω
Q4 1 1W
KBL06 C2 MPSA42 C13
470 µF C12 R21 220 µF
8, 9, 10 63 V
200 V D8 2200 µF 270 Ω
CY3 LPFC1 MBR6045 6.3 V
R6 C20 TO
2.2 nF 330 pF
(Safety) 2.2 MΩ MAGAMP OUT
50 V (3.3 V)
LPFC2 11,12
CY4 RTN
JP9 TOPSwitch-GX C27 C24
2.2 nF 3 D6 330 pF 330 µF
(Safety) U1 R13 BAV20 C5 25 V C25
TOP249 10 Ω 50 V
1 µF R18 1 µF
CX1 Q6 D18 100 V R11 4.74 kΩ 50 V
0.047 µF R8 R36 4 BAV20 330 Ω
MPSA92 43.2 kΩ 1% LM
250 VAC 130 kΩ - 12 V
To AC Selector 1% 1% R15 320
L7 Switch D20 1.8 kΩ
8.2 mH R7 VR19 UF4002
VR3 D L C22 560 kΩ 1N5229 C17
CX2 BZY97C- 100 pF R20
CONTROL 100 nF 270 kΩ
0.33 µF C3 200 50 V 50 V
250V C
470 µF R16
200 V VR4 U2
BZY97C- R11 SFH615A-2 1 kΩ
R10 300 Ω
RT1 560 K 180 S X F C8 C16
10 Ω R9
1/2 W 0.033 µF 47 Ω Q1 100 nF R17
VR5 50 V 2N3908 50 V 15 kΩ
RV1 R2 BZY97C- D105
275 V, 14 mm 330 kΩ 180 R30 1N4148
C6 R14 U5
3.3 kΩ 47 µF R19
75 kΩ TL431
16 V 4.12 kΩ
1%
PI-3384-120902
R12 +12 V STBY
12 kΩ R38 R106
5.1 kΩ 27 kΩ
U3 Remote
LTV817 ON/OFF
F1 C7 Q7
4A 100 nF 2N3904
50 V C23 R37
33 nF 10 kΩ
50 V
L G N
Figure 1. 180 W (200 W pk.) PC Main Power Supply Schematic (Note: Schematic does not include transformer Y-capacitor).
3-234
Rev. C 03/05
The components R12, C7, R38, Q7, C23, R37, U3, R106 and reset circuit to maintain drain voltage < 600 V and DCMAX
D105 implement the remote ON/OFF drive circuit. During the reduction to prevent transformer saturation.
ON state, U3 and hence Q7 conduct, pulling the X pin to • Maintain maximum flux density on transformer (T1)
SOURCE via resistor R12 (which sets the current limit). < 2500 gauss.
• Check for balanced currents on coupled inductor (L1) for
During the OFF state, U3 and Q7 are off, allowing the X pin to all load combinations.
be pulled high by the +15 V standby supply via R38 and R12 • Use PI Expert (PIXls) Design Spreadsheet and refer to
and putting the TOPSwitch-GX into the OFF state. Components Application Note AN-30 for details on designing forward
R38 and D105 reduce device consumption to around 2mW by converters with TOPSwitch-GX.
supplying external current to the CONTROL pin from the
+15 V standby supply. Resistor R11 is required to allow This particular PC SFX 12 specification delivers a larger
external bias feed. proportion of power on the 12 V winding; efficiency would be
lower if that power were drawn from the 3.3 V output.
Key Design Points
Due to the complexity of this design it is not possible to include
• The passive PFC inductors (LPFC1 and LPFC2) are all details in this Design Idea. An Engineering Prototype Report
constrained by both thermal and efficiency requirements. (EPR-31) with additional information is available. For updates
Design of these inductors is not covered in this Design Idea. and all other information please refer to Power Integrations'
• Transformer reset: Use recommended Zener/capacitor clamp/ website.
D9
MBR2045 L4 L5
20 µH 0.5 µH
FROM MAIN 3.3 V
CONVERTER L3
5 V WINDING R22
Mag Amp 3Ω
6 Turns R23 R25 R24
Q2 1 kΩ 2.7 kΩ 3.84 kΩ
TIP32 1% C14 C15
R27 C18 1200 µF 1200 µF
R34 10 V 10 V
33 Ω 390 Ω 0.1 µF
D11 50 V
UF4002 C21
D10 1 µF U8 R26
UF4002 50 V TL431 10 kΩ
1%
RTN RTN
Figure 2. Magamp for Independent 3.3 V Secondary Regulation.

PI-3385-093002
3
3-235
Rev. C 03/05
Design Idea DI-31
®
DPA-Switch
5 V, 70 W DC-DC Converter with Synchronous Rectification

Design Highlights R1 programs the input UV/OV thresholds. The tight tolerance
of the UV/OV thresholds limits the range of gate drive voltages
• Extremely low component count applied to MOSFETs Q1 to Q6, eliminating the need for gate
• High efficiency, 90% using synchronous rectification voltage clamp circuitry. The self-driven synchronous
• No current sense resistor or current transformer required rectification configuration is therefore very simple, with R4 to
• Output overload, open loop and thermal protection R6 filtering voltage spikes at the gates of Q1, Q2 and Q3 and
• Accurate input under/overvoltage meets ETSI standards D4 preventing the body diodes of Q4, Q5 and Q6 from
• 300 kHz switching frequency – optimizes efficiency using conducting.
simple self-driven synchronous rectification
Capacitor C9, diodes D1-D2, and inductor L2 form a resonant
Operation snubber that recycles leakage and magnetizing energy stored in
T1, and also helps to reset T1. Zener diode VR1 provides a hard
The 70 W converter shown in Figure 1 benefits from many of
voltage limit and only conducts during output transient and
the DPA-Switch integrated features. In particular, no external
overload conditions. Capacitor C12 and Resistor R7 damp
current sense components are required. In a discrete
secondary switching spikes and help to reset T1.
implementation, an expensive current transformer and a number
of additional components would increase the cost of this
converter significantly.
C7 1 nF
1.5 kV C13, C14,
L1 L3 C15, C16, C17
100 µF 10 V C18, C19
+ VIN 1 µH Q4-Q6 3.8 µH 100 µF
R4-R6
3 36-75 VDC 2.5 A
1
T1
9,10
10 Ω SI4842DY 20 A (x5)
L4
10 V 5 V, 14 A
100 nH C20
20 A 1 µF
10 V
D1 6,7
ESD1 R1 2
619 kΩ D4 RTN
Q1-Q3 42CTQ30S
SI4842DY
C12 2.2 nF, 50 V U2

3
R7
C9 1Ω
150 pF 5 L5 R13 R15
C1, C2 C3, C4, 200 V D3 2.2 mH 10 kΩ 10.0 kΩ
1 µF C5, C6 BAV19WS 40 mA 1%
100 V 1 µF 100 V D5 D6
(x4) BAV19WS BAV19WS C22
4
100 nF
C8
D L DPA-Switch 1 µF R11 R10
25 V 150 Ω 5.1 Ω
L2 U1
CONTROL
CONTROL DPA426R
220 µH C R14
U2 220 Ω
PC357N1T C23
10 µF
S X F 10 V C21 1 µF
R3
VR1 1.0 Ω U3
SMBJ C10 LM431AIM3
150 220 nF C11 R16
R2 68 µF 10.0 kΩ
D2 10 V 1%
ESD1 6.8 kΩ
-VIN 1%
PI-3375-121602
Figure 1. DPA426 70 W, 5 V, 14 A DC-DC Converter.
3-236
Rev. B 12/02
Key Design Points TRANSFORMER PARAMETERS

• For nominal undervoltage set point VUV: EFD25, 3F3
R1 = (VUV - 2.35 V)/50 µA. VOV = (R1 x 135 µA) + 2.5 V. Core Material Gap for ALG = 1100 nH/T2
• Locate C10, C11, and R3 close to the U1 CONTROL pin, EFD25 10 pin
with ground connections returned to SOURCE pin. Bobbin
(B&B B-025 or equivalent)
• Minimize primary and secondary high current loop areas to
Bias: 5T, 30 AWG
reduce parasitic inductance. Winding Details Primary: 6T+ 5T, 4 x 26 AWG
• Optocoupler U2 should have a controlled CTR range of Secondary: 3T, 0.005" Cu foil
100 to 200% for optimum loop stability.
Primary (3-2), tape, Bias (4-5), tape,
• Size transformer reset components to ensure transformer Winding Order
Secondary (6,7-9,10), tape,
(Pin Numbers)
reset at minimum operating voltage without exceeding Primary (2-1), tape
170 V drain voltage at high line. It may be necessary to gap Primary: 130 µH 10%,
T1 to offset effect of Q4-Q6 gate capacitance. Inductance
Leakge: 10 µH (max)
• Set Zener VR1 clamp voltage to 150 V to both safely limit
Primary Resonant
the DRAIN below BVDSS and guarantee transformer reset. Frequency
3 MHz (minimum)
• Select number of bias turns to provide 12 V to 14 V at
minimum input voltage and full load. Table 1. Transformer Design Parameters.
• Main primary power return should be connected to the
DPA-Switch tab, not to the SOURCE pin.
• Scale time constant of C9 and L2 to allow C9 to reset OUTPUT INDUCTOR PARAMETERS
completely during minimum on-time conditions.
• Consult AN-31 for additional design tips and information. EE22, TDK PC40 Material
Core Gap for ALG of 250 nH/T2
92 Bobbin TDK BE-22-5116

PI-3376-091502
Winding Details 4T, 0.016" Cu foil

90
Inductance 4 µH 10%
Efficiency (%)
88
86
84 VIN = 36 VDC
VIN = 48 VDC
3
VIN = 60 VDC
82 VIN = 72 VDC
80
0 20 40 60 80
Output Power (W)
3-237
Rev. B 12/02
APPLICATION NOTE
Design Idea DI-35
®
TOPSwitch-GX
16 W Audio Amplifier Power Supply

Audio Amplifier TOP245P 16 W (35 W Peak) 85-265 VAC 16 V Flyback
Design Highlights The EMI filter has been significantly simplified to three
components (L1, CX1 and CY1), thanks to the built-in frequency
• No heatsinks required!
jitter function of the TOPSwitch-GX family.
• 77% efficiency (min), at 85 VAC input/35 W output
• Low no-load input power: < 0.7 W at 230 VAC input
The RCD network of C4, R3, R4, and D5 limits (clamps) the
• Low component count: 37, excluding I/O connectors
peak voltage that the U1-DRAIN sees. A glass-passivated
• Stable operation with or without 10,000 µF output buffer
normal recovery diode (D5) recycles stored leakage energy,
capacitor
increasing overall efficiency. DRAIN ringing is dampened by
• Robust transformer design enables 35 W peak power
R4 (necessary when a normal recovery diode is used).
• Meets CISPR22B EMI with >10 dB of margin
• Ideal for both class AB and class D audio amplifiers,
The bias winding provides operating power and feedback
6 channel Dolby Digital with 6 ohm speakers
current to the CONTROL pin of U1. The U2-LED, R8 and
VR1 comprise the feedback circuit that senses the output
Operation voltage. The current through the U2-LED regulates the output
Many of the built-in TOPSwitch-GX features have been used voltage by modulating the feedback current that flows into the
to reduce the component count, transformer size and overall CONTROL pin of U1.
cost of this universal input flyback power supply. Designed
around a TOP245P (DIP-8 package), the device uses PCB Key Design Points
copper for its heatsink, eliminating the costs of both a heatsink
and the installation labor. Output diode D7 is also cooled the • Ensure that the control loop has enough phase margin at
same way. the extremes of the rated input voltage and output load,
3 both with and without the output buffer capacitor.
• A 5% VR1 should be acceptable for an audio amplifier.
Resistors R1 and R2 set the nominal under-voltage (UV)
lockout and overvoltage (OV) shutdown limits to 84 V and Greater accuracy will require a 2% VR1.
378 V, respectively. UV lockout protects the supply from • OV and UV thresholds are determined by:
overheating at low line and eliminates power-up and power- VOV = 225 µA • (R1+R2) and VUV = 50 µA • (R1+R2).
down glitches. OV shutdown protects the power supply from CY1 R6 C6
line surges. 2.2 nF
(Safety)
33 Ω 470 pF
1/4 W 100 V
R3 C4 L2 C9
200 kΩ 1 nF 16 V, 1 A /
3.3 µH 100 µF 2.2 A
1/2 W 1 kV 1 9,10 25 V
D1-D4
1N4007
R1 D7
C1 1 MΩ SB5100
3 6,7
100 µF
400 V R7 C7 C8 RTN
10 Ω 470 µF 470 µF
4
R2 25 V 25 V
1 MΩ R4
33 Ω
1/4 W 5 C5 R8
D5 1 µF 150 Ω
L1 T1 50 V
6.8 mH 1N4007G D6
0.8 A BAV20
TOPSwitch-GX R10
D M
CX1 U1 1k
220 nF CONTROL TOP245P
250 VAC C U2
PC817A
R5
F1 S
C2 3.3 Ω
3.15 A VR1
250 V 100 nF C3 C10
50 V IN5244B 47 µF
100 µF 5%
16 V 25 V
85-265
L VAC N
PI-3731-070704
Figure 1. Audio Amplifier Power Supply.
3-238
Rev. B 07/04
• Keep power loop layouts (primary and secondary) tight to

minimize noise (EMI and output ripple) and power loss.
• At least 10 cm2 of PCB copper area should be used for Nippon Ceramic EF-25-NC-2H
Core Material
heatsinking. ALG of 247 nH/T2
• 10,000 µF output buffer capacitor, standard ESR, Miles-Platts FE0100 with
Bobbin
improves multi-channel audio transient capability. TBS-601 terminals
Primary: 65T, 2 layers, 28 AWG
16.1 Secondary: 9T, 2 x 26 AWG,
Winding Details
PI-3729-093003
16 triple insulated
15.9 Bias: 7T, 2 x 28 AWG
15.8 Primary: 3-1, tape
Winding Order
15.7 Secondary: 9, 10-6,7, tape,
(pin numbers)
VOUT (V)
15.6 Bias: 4-5, tape 3L

15.5 Primary
1059 µH ±10%
15.4 Inductance
15.3 Primary Resonant
0.75 MHz (min)
15.2 Frequency
15.1 Leakage
28 µH (max)
15 Inductance
0 0.5 1 1.5 2 2.5
IOUT (A)
Figure 2. 115 VAC V-I Curve.
THERMAL TEST RESULTS
7 Thermal test load current is 1 A for 30 ms, 2.2 A for 10 ms
PI-3730-012604
T (°C) at T (°C) at
6 Test Case
85 VAC 265 VAC
5 T1 (Transformer) 57 59
U1 (TOP245P) 64 51
4
Current (A)
D7 (Op Rectifier) 58 59
3 C8 (Op Capacitor) 41 40 3
2 Table 2. Thermal Test with Pulsed Load of Figure 3. 25 °C
Ambient, Open Frame, 85 VAC and 265 VAC Input.
1
0
1A 2.2 A
-1
0 50 100
Time (ms)
Figure 3. Load Current for Thermal Test (10 ms/div).
3-239
Rev. B 07/04
APPLICATION NOTE
Design Idea DI-37
®
DPA-Switch
16.5 W DC-DC Converter

Telecom DPA424R 16.5 W 36-75 VDC 3.3 V Forward Sync. Rec.
Design Highlights to prevent core saturation during load transients. Resistor R3

• Low cost programs the DPA-Switch current limit to 60% of nominal to limit
• 400 kHz synchronous rectification design fault and overload power. Drain voltage clamping is provided
• Low component count by Zener diode VR1. Transformer core reset is controlled by
• Efficiency – 87% at 48 VDC the gate capacitance of Q1.
• No current sense resistor or current transformer required
• Output overload, open loop and thermal protection Resistor R15 charges the gate of Q2, the forward synchronous
• Integrated UV meets ETSI standard rectifier MOSFET. The catch synchronous rectifier MOSFET
(Q1) is directly driven by the transformer (T1) reset voltage and
Operation operates only when Q2 is off. Diode D2 provides a conduction
path for the output inductor (L2) current when the transformer
DPA-Switch greatly simplifies the design compared to a discrete
reset is complete.
implementation. Resistor R1 programs the under/over voltages
and linearly reduces the maximum duty cycle with input voltage
C7
1 nF R14
L1 1.5 kV 10 Ω
+ VIN 1 µH C10 C11 C12 C13
2.5 A 100 µF 100 µF 100 µF 1 µF
36-75 VDC L2 6.3 V 6.3 V 6.3 V 0805 3.3 V, 5 A
3
R1 R15 D2
619 kΩ 10 Ω B540C
1% D1
Q1 BAV
Si4800 19WS
DY
RTN
T1 Q2
Si4800 C4
DY 4.7 µF U2
20 V
R7
C1, C2 10 kΩ R10
1 µF 3.24 kΩ
100 V 1%
DPA-Switch D3 C16
U1 U2 100 nF
D L
PC357N1T BAV19WS
DPA424R
CONTROL R6 R12
C 150 Ω 5.1 Ω
R9
220 Ω
S X F
R4 C15
10 µF C14
VR1 1.0 Ω 1 µF
10 V
SMBJ C5 U3
150 220 nF C6
R3 68 µF LM431AIM3 R11
11.1 kΩ 10 V 10.0 kΩ
VIN 1% 1%
PI-3650-072004
Figure 1. DPA424R–16.5 W, 3.3 V, 5 A DC-DC Converter.
3-240
Rev. B 07/04
Key Design Points

• Transformer core reset is critical in this design. MOSFET • Reduce transformer leakage inductance by filling each
gate loading will affect the transformer reset waveform. winding layer across the entire width of the bobbin.
Capacitor CQ1gs will load transformer reset. Choose Q1 • Choose a low-drop Schottky diode (such as Vishay
MOSFET such that CQ1gs provides sufficient reset at low line SL44 – Vf = 0.42 V), to increase high line efficiency.
and safe maximum drain voltage at high line. • Choose a larger DPA-Switch to increase efficiency at low
• Choose synchronous rectifier MOSFETs which have both and medium input voltages.
low RDS(ON) and also low Qg (combination of gate charge Qgs
and Miller capacitance Qgd).
TRANSFORMER PARAMETERS INDUCTOR PARAMETERS

Epcos P/N: P 14 x 8 N87, Epcos P/N: P 14 x 8 N87,
Core Material Core Material
ungapped gap for inductor
8-pin P 14 x 8 surface mount 8-pin P 14 x 8 surface mount
Bobbin Bobbin
bobbin bobbin
Primary 10T + 10T, 1 x 26 AWG Main 10T, 2 x 24 AWG
Winding Details Winding Details
3.3 V, 4 x 26 AWG Bias 30T, 1 x 32 AWG
Winding Order Primary-1 (4-NC), 3.3 V (5-6), Winding Order Main (7,8-5,6)
and Pin Numbers Primary-2 (NC-1) and Pin Numbers Bias (1-2)
Primary Pin (7,8-5,6): 16 µH ±10% at
600 µH ±25% at 400 kHz Inductance
Inductance 400 kHz
Primary Resonant
3.8 MHz (minimum) Table 2. Inductor Design Parameters.
Frequency
Leakage
1 µH (maximum)
Inductance
Table 1. Transformer Design Parameters.
3-241
Rev. B 07/04
Design Idea DI-39
®
TOPSwitch-GX
13 W, Universal Input DVD Supply with 70 mW No-load

DVD TOP244P 13 W (17 W pk) 85-265 VAC 3.3 V / 5 V / 12 V / -12 V Flyback
Design Highlights The supply operates at full frequency at high and medium power
and reduces frequency at light loads. Components D9 and C10
• High efficiency multi-ouptut flyback (77% minimum) rectify and filter the bias voltage.
• Topology scalable to higher powers
• Excellent cross-regulation TOPSwitch-GX frequency jitter allows conducted EMI
• Excellent input no-load consumption <70 mW input compliance without a common-mode choke, using only
• 132 kHz switching frequency allows smaller transformer capacitors C1, C4 and inductor L1 as an EMI filter.
• Frequency jitter eliminates common-mode EMI choke
• >10 dB margin against CISPR22-B conducted EMI with Components D5 and C2 form a capacitor clamp circuit absorbing
artificial hand grounding leakage inductance energy during normal operation. Zener VR1
clamps the voltage to a safe level during abnormal and transient
Operation conditions. After clamping, reverse current flows through D5,
recovering some of the energy. Resistor R5 limits the reverse
The TOPSwitch-GX uses current mode feedback to achieve
current and, with R7, improves EMI by limiting the ringing on
excellent no-load standby. Components C16, R1 and Q2 provide
the drain. Continuous mode operation allows reduced primary
a constant current powering the TOPSwitch-GX CONTROL
and secondary peak currents, optimizing cross regulation and
pin. Resistor R2 feeds the remainder of Q2 current to the M pin,
load regulation by minimizing leakage inductance induced
reducing TOPSwitch-GX current limit with increased current.
voltage shifts.
Resistor R11 sets the maximum current limit of the device.
Resistors R15 and R16 share the feedback from the 3.3 V
Components R6, Q1 and C13 implement slope compensation.
and 5 V outputs for good cross-regulation.
3 C8
1 nF
Y1
L2
D1-D4 3.3 µH
1N4005 12 V, 400 mA
F1 VR1 D7 C15 L3 C20
3.15 A P6KE180 R7 UF4003 470 µF 3.3 µH 150 µF
250 VAC 100 Ω 25 V 25 V 5 V, 1.6 A
C1 C4 C11
C3 33 µF 33 µF C2 D11 1800 µF L4
85 - 265 0.047 µF 400V 400V 0.01 µF 1N5822 25 V 3.3 µH 3.3 V, 700 mA
VAC x2 1 KV
C12 C17 C18
D10 1000 µF R9 470 µF
R5 1N5822 200 Ω 470 µF
47 Ω 10 V 10 V 10 V RTN
C9 C6
D5 D8 220 µF U2B
UF4003 220 µF PC817
1N4007 25 V 25 V
R8 R16
R12 1 kΩ 6.34 kΩ R15
1 1/2 W 20 kΩ
PC817
U2A
C14 R10
0.1 µF 3.3 kΩ
R1 R6 C7
C16 20 kΩ U3
270 Ω 10 µF TL431CLP R13
0.33 µF 50 V 10 kΩ
TOPSwitch-GX
U1
TOP244P
R2 Q2 Q1
20 kΩ 2N3906 2N3906
- 12 V, 100 mA
D M
D9
CONTROL C13 C10 1N4148
C 47 pF 47 µF
R11 50 V
7.5 kΩ R14
L1 6.8 Ω
S C19
1.4 µH C5
0.5 A 0.1 µF 47 µF
10 V
PI-3321-111902
Figure 1. TOPSwitch-GX DVD Player Schematic.
.
3-242
Rev. A 11/02

• Use of foil for the 3.3 V and 5 V windings also helps to EEL25
Core Material Himag MZ4 EEL25.4, Taiwan AL of
optimize cross-regulation.
• Optional capacitor C7 is the “soft-finish” capacitor and 344 nH/T2
prevents overshoot on startup. Bobbin EEL25 Vertical 14 Pins
• Compact layout for components D7, D10, D11, C11, Shield: 32T x 2 x 32 AWG
C12, C15 will improve cross-regulation and efficiency. Primary: 64T x 2 x 32 AWG
Bias: 10T x 4 x 32 AWG
Compact layout for L2, L3, L4, C17, C18, and C20 will Winding Details Shield: 2T x 8 x 32 AWG
achieve best output ripple. +3.3V: 4T x foil 0.052 x 14 mm
• Figure 2 shows conducted EMI at 230 VAC full load, with +5V: 1T x foil 0.052 x 14 mm
output “Artificial Hand” grounding. Floating output return +12V: 4T x 4 x 32 AWG
-12V: 7T x 4 x 32 AWG
gives lower results.
• Table 2 shows the cross regulation of the supply over load Shield (NC-5), tape, Primary (1-4), tape,
Winding Order Bias (7-6), tape, Shield (5-NC), tape,
for both 115 VAC and 230 VAC. +12 V (13-8), +3.3 V (11,12-9,10), +5 V
(Pin Numbers)
(9-10,13), tape, -12 V (14-11, 12), tape
80 PI-3408-112502 Primary Inductance

(Pins 1-4 all others 1.42 mH 10% at 132 kHz
70 open)
60 QP
Primary Resonant
300 kHz minimum
AV Frequency
50
Quasi Peak Leakage Inductance 30 µH maximum
40
dBµV

20
10 Output Load Cross Regulation (%)

Voltage Range
0 Average (V) (%) -4 -3 -2 -1 0 1 2 3 4
3.3 10-100
-10 5 10-100
12 10-100
-20
-12 100
0.15 1.0 10.0 -100.0
MHz
Figure 2. EMI at 230 VAC Full Load with "Artificial Hand"
Table 2. Worst Case Cross Regulation at 115 VAC and 230 VAC. 3
Grounding of Output.
3-243
Rev. A 11/02
Design Idea DI-40
®
DPA-Switch
2.5 V, 20 W DC-DC Converter with
Synchronous Rectification
DC-DC Converter DPA424R 20 W 36-75 VDC 2.5 V Forward
Design Highlights Capacitor C8 and the gate capacitance of Q1 reset T1 during

DPA-Switch off-time. Zener VR1 provides a hard voltage
• Extremely low component count clamp to limit DRAIN voltage under output transient and
• High efficiency - 86% using synchronous rectification overload conditions.
• No current sense resistor or current transformer required
• Output overload, open loop and thermal protection Since the output voltage is low, the U2 LED is supplied with a
• Accurate input under/overvoltage meets ETSI standards higher voltage derived from a winding on output choke L2.
• 300 kHz switching frequency - optimizes efficiency when
simple self-driven synchronous rectification is used The DPA-Switch bias supply is derived from a forward winding
on transformer T1. Flyback windings are not recommended for
Operation this purpose, since the bias capacitor C4 would create high
capacitive loading during DPA-Switch off- time, preventing the
DPA-Switch greatly simplifies the design compared to a discrete transformer from efficiently resetting.
implementation. Resistor R1 programs the input UV/OV
thresholds. The tight tolerance of the UV/OV thresholds limits
the range of gate drive voltages applied to MOSFETs Q1 and
Key Design Points
Q2, eliminating the need for gate voltage clamp circuitry. The • For nominal under-voltage set point V UV :
self-driven synchronous rectification configuration is therefore R1 = (VUV- 2.35 V)/50 µA. VOV = (R1 x 135 µA)+2.5 V.
very simple, with R13 filtering voltage spikes at the gate of Q2, • Locate C5, C6, and R4 close to U1 CONTROL pin, with
and D3 preventing the body diode of Q1 from conducting. ground connected to SOURCE pin.
• Minimize primary and secondary layout loop area to reduce
3 C7
1 nF
1.5 kV
R14
10 Ω
parasitic inductance.
+ VIN L2
D3 3.3 µH
36 - 75 VDC T1 12CWQ03FM 8 A 2.5 V, 8 A
L1 1 9, 10 7, 8 5, 6
1 µH 2.5 A 1 2
R13
10 Ω C9, C10 C11
100 µF 1 µF
D2 10 V 10 V
R1 Q1 BAV19WS
619 kΩ SI4842DY
6, 7 RTN
Q2
SI4842DY
C1, C2 C3 C8 R5
1 µF 1 µF 2.2 nF 1.0 Ω C12
100 V 100 V 4 4.7 µF
20 V
2 L3
D1 2.2 mH
BAV19WS 40 mA
D4 C4
BAV19WS 1 µF
3
D L DPA-Switch U2 U2
PC357 R7
U1 N1T
CONTROL DPA424R 10 kΩ R10
C 10.2 kΩ
VR1 1%
SMBJ150
S X F R4 D3 C13
1.0 Ω BAV19WS 100 nF
R6 R12
C5 150 Ω 5.1 Ω
R3 0.22 µF C6 R9
15 kΩ 68 µF 220 Ω
1% 10 V C15
10 µF C14
10 V 1 µF
VIN U3
LMV431 R11
AIM5X 10.0 kΩ
1%
Figure 1. DPA-Switch 20 W DC to DC Converter. PI-3264-051303
.
3-244
Rev. C 05/03
• Optocoupler U2 should have controlled CTR of 100-200%

for optimum loop stability. TRANSFORMER PARAMETERS
• Size transformer reset components C8 and R5, and the Q1 PR1408
Core Material EPCOS N87 material ungapped
gate capacitance to assure transformer reset at minimum
operating voltage without exceeding 170 V drain voltage at P1408 8 pin
Bobbin
high line. (B&B B-096 or equivalent)
• Set Zener VR1 clamp voltage to 150 V to guarantee both Bias: 6T, 32 AWG
transformer reset and limit DRAIN voltage below BVDSS. Turns Primary: 7T + 7T, 2 x 28 AWG
• Scale primary side forward bias winding to provide Secondary: 2T, 4 x 26 AWG
12 V to 15 V at minimum input voltage, nominal load. Bias: (3-2), Tape
• Secondary choke winding provides 5 V at nominal load. Winding Order Primary: (4-FL), Tape
• Main primary power return should be connected to the (Pin Numbers) Secondary: (6, 7-9, 10), Tape
DPA-Switch tab, not to the SOURCE pin. Primary: (FL-10), Tape
• Consult AN-31 for additional design tips. Primary Inductance 392 µH 25%
Primary Resonant
95 3 MHz (minimum)
Frequency
PI-3378-091702
90 Leakage Inductance 1 µH (maximum)

Efficiency (%)
80
75 OUTPUT INDUCTOR PARAMETERS

70 VIN = 36 VDC
VIN = 48 VDC EPCOS N87 material
Core Gap for AL of 206 nH/T2
65 VIN = 60 VDC
VIN = 72 VDC P1408 8 pin
Bobbin
60 (B&B B-096 or equivalent)
Bias: 10T, 32 AWG

Winding Details
0 5 10 15 20 Main: 4T, 4 x 26 AWG
Output Power (W) Winding Order Bias: (1-2), Tape
Figure 2. Efficiency vs. Output Power. (Pin Numbers) Main: (7,8-5,6), Tape
Inductance Pins 5,6-7,8 3.3 µH 10% 3

3-245
Rev. C 05/03
Design Idea DI-41
®
TOPSwitch-GX
43 W, 100/115 VAC Multi-output Set-top Box Power Supply

Set-top Box TOP247Y 43 W cont. / 57 W pk 90-132 VAC 3.3 V, 5 V, 12 V, 18 V, 33 V Flyback
Design Highlights Operation

• Low cost, low component count solution The design in Figure 1 utilizes the TOP247Y and takes advantage
• Excellent output voltage tracking and cross-regulation - no of many of the TOPSwitch-GX features. Line UV and OV
linear regulators required (100 V and 450 V, respectively) are implemented using a single
• High efficiency, >71% at 90 VAC 2 MΩ resistor (R1). Undervoltage eliminates output glitches
• Line undervoltage detection (UV) and power system surge and overvoltage provides protection for both short duration
protection (OV) transients and long duration power system surges. Resistor R4
• Meets CISPR22B/EN55022B conducted EMI limits programs the internal current limit of U1 to 80% of nominal,
• Differential and common mode surge immunity to 4 kV limiting overload power.
(EN61000-4-5)
• 100 kHz ring wave immunity to 4 kV (IEEE C62.41) The key performance characteristic of the circuit shown is the
excellent output voltage tracking and cross-regulation. Two
techniques are used to properly center the output voltages. The
extra voltage drop of the ultra-fast rectifier D10 (used instead of
T1 R6 D7 L6
10 Ω UF4003 33 µH, 0.2 A 33 V, 0.03 A
14
C7 C8
D8 47 µF L2 10 µF
UF5402 50 V 3.3 µH, 5 A 50 V 18 V, 0.5 A
13
C9 C10
D9 1000 µF L3 220 µF 12 V,
25 V 3.3 µH, 5 A 0.6 A/1.8 A pk
3 12
UF5402 25 V
L7 C11
8 Bead 390 µF C12
35 V R14
C24 100 µF 5.6 kΩ
R15 0.1 µF 25 V 0.5 W
10 Ω 50 V L4
R2 C5 3.3 µH
68 kΩ 1 nF C6 5A 5 V, 3.2 A
2 W 1 kV 2.2 nF 9
Y1 C13, C14 L5 C15
D10 1200 µF 3.3 µH 220 µF
1 BYV32-200 35 V 5A 16 V
D1-D4 3.3 V, 3 A
11
RL206 VR1
2 A, 800 V P6KE200 C22 C18
D11 C16, 17
MBR1045 0.1 µF 220 µF
1200 µF 16 V RTN
50 V 35 V
D2 D1 3, 4 10
D5
1N4937
D4 D3 C2 5 R7
150 µF 150 Ω C21
7
L1 200 V C3 0.1 µF
D6 1 µF 50 V
20 mH 1N4148 U2
1.3 A R1 50 V LTV817
2 MΩ 6
C1 1/2 W R10 R12
0.22 µF R8 R13
1 kΩ 9.53 kΩ 18 kΩ 15 kΩ
X2 1% 1%
C19
RV1 D L TOPSwitch-GX 0.1 µF
275 V CONTROL 50 V
14 mm U1 C
F1 TOP247Y R9
3.15 A R3 3.3 kΩ
C3 6.8 Ω C20
RT1 R4 S X F
0.1 µF
9.09 k 22 µF
L t° 10 Ω 50 V C5 50 V U3
R11
3.2 A 1% 47 µF TL431CLP
90 - 132 10 kΩ
VAC 16 V
1%
N
PI-3389-091702
Figure 1. TOPSwitch-GX 43 W Continuous, 57 W Peak Set-Top Box Power Supply.
3-246
Rev. A 09/02
a Schottky) centers the 5 V output at precisely 5 V and DC

stacking is used to improve the regulation of 12 V, TRANSFORMER PARAMETERS
18 V, and 30 V outputs. Ferrite bead L7 is placed in series with ERL28, Nippon ceramic
the 12 V, 18 V and 30 V output windings to improve centering Core Material NC-2H material or equivalent,
and cross-regulation of these outputs. gapped for ALG = 128 nH/T2
ERL28 vertical, 14 pins,
Frequency jittering provides large EMI margins with simple Bobbin Jinbo Industrial
JB-0039 or equivalent
filtering. Primary soft-start minimizes component stress during
start-up and a soft-finish capacitor (C20) eliminates start-up Primary: 30T + 23T, 25 AWG
output overshoot. Shield: 1T, 0.6" x 0.001" Cu foil
Bias: 7T, 2 x 27 AWG
3.3 V: 2T, 0.6" x 0.005" Cu foil
Key Design Points Winding Details 5 V: 1T, 0.6" x 0.005" Cu foil
12 V: 4T, 2 x 27 AWG
• Use KRP (Ripple-to-peak current ratio) in the range of 18 V: 3T, 2 x 27 AWG
33 V: 6T, 27 AWG
0.4-0.6 for higher efficiency, and tighter cross-regulation. (2 x 27 AWG = Bifilar 27 AWG)
Use VOR (reflected output voltage) of 90 V to 110 V for
optimum performance. Apply 3.2 mm tape margin to
both sides of bobbin
• PCB traces which carry high switching currents should be Primary (4-3), tape, Shield (1-NC),
Winding Order
short and wide to reduce EMI. tape, Bias (6-7), 3 x tape, 5 V (9-11),
(Pin Numbers)
• Reduce leakage inductance and improve cross-regulation 3.3 V (11-10), tape, 12 V (12-8),
by filling each winding layer across the entire width of the 18 V (13-12), 33 V (14-13),
3 x tape, Primary (3-1), 3 x tape
bobbin.
• Resistor R14 provides a small amount of pre-load on the Primary: 356 µH,
Inductance
33 V output to prevent peak charging due to leakage spikes.
• R5 and C5 reduce power dissipation in VR1. Primary Resonant
650 kHz (minimum)
Frequency
Voltage Load Regulation (%) Table 1. Transformer Design Parameters.

Range
(V) (Amp) -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3
3.3 1-3
5 1-3.2
12 0.3-0.6
30 0.01-0.03
Table 2. Worst Case Output Cross Regulation - Outputs Taken 3

from Minimum to Maximum Load and Line from 85 VAC
to 132 VAC.
3-247
Rev. A 09/02
Design Idea DI-43
®
TOPSwitch-GX
30 W, Universal Input, 12 V Supply with <250 mW No-load

Adapter TOP244Y 30 W 85-265 VAC 12 V Flyback
Design Highlights increases, limiting the maximum overload power of the supply.
The reduced current limit allows continuous conduction mode
• High efficiency (79% minimum) operation with a small transformer, reducing primary and
• Low component count secondary peak currents, optimizing efficiency, and reducing
• Excellent input no-load consumption <200 mW at 115 VAC component stress.
and <250 mW at 230 VAC input
• Rugged supply includes UV/OV shutdown, thermal and Diode D1 and VR1 form a clamp circuit that absorbs leakage
short circuit protection with auto-recovery inductance energy during normal operation, with Zener VR1
• Comfortably meets EN55022B and CISPR22B conducted clamping the voltage to a safe level. Capacitor C2 diverts some
EMI standards of the leakage energy from VR1, reducing its temperature and
• Overload power delivery at 265 VAC limited to 160% of increasing overall efficiency. After clamping, reverse current
rated load flows through D1, recovering some of the clamp energy. R3
limits the reverse current in D1 and improves EMI by limiting
Operation drain voltage ringing.
The TOPSwitch-GX integrates many features to implement low Resistors R9 and R10 set the output voltage. Components C10
cost, switched mode power supplies. and R8 provide compensation with R6 setting DC loop gain.
Using a TL431 error amplifier gives better regulation and
A single resistor (R1) implements input UV/OV protection output voltage tolerance than a Zener reference and also provides
using the L pin (UV typ. 100 VDC; OV typ. 450 VDC). better no-load performance due to lower (1 mA) bias current.
Resistor R4 programs the U1 current limit to 85% of nominal,
3 and resistor R2 reduces this current limit as input voltage
C7 C12 R11
2.2 nF 470 pF 33 Ω
Y1 100 V 1/4 W
D3 L2
T1 MBR10100 3.3 µH 12 V, 2.5 A
C2 1 6,7
4.7 nF C6 C7 C8
BR1 1 kV 680 µF 680 µF 100 µF
2 A, 600 V VR1 35 V 35 V 35 V
R3 P6KE RTN
47 Ω 200 9,10
1/2 W D2
1N4148
D1
UF4005 5
3 C3
L1
22 mH 1 µF
50 V R7
C1 R2 R1 4 15 kΩ
100 µF 8.2 MΩ 2 MΩ
400 V 1/2 W 1/2 W U2 R9
ISP817C 38.3 kΩ
CX1 TOPSwitch-GX 1%
D L
220 nF D4
250 VAC CONTROL 1N4148 R6
U1 C 1 kΩ R8
TOP244Y 4.7 kΩ
F1
3.15 A C11
S X F R5 10 µF
6.8 Ω C10
C4 35 V 47 nF
L R4 100 nF
C5 U3
85-265 VAC 8.25 kΩ 47 µF
1% TL431 R10
10 V 10 kΩ
N 1%
PI-3405-112702
Figure 1. TOPSwitch-GX 12 V, 30 W Universal Power Supply.
3-248
Rev. A 11/02
Optional components D4, C11, and R7 implement soft finish

to limit startup overshoot. Resistor R7 discharges this soft- TRANSFORMER PARAMETERS
finish capacitor at power down. EF25 Nippon Ceramic NC-2H
Core Material ALG of 264 nH/T2
Key Design Points Bobbin

EF25 10 pin
(Miles Platts FE0100 with TBS-601)
• Use reflected voltage from 90 V to 120 V Primary: 58T x 26 AWG
• Compact layout for components D3, C6 and C7 will improve Bias: 2T x 26 AWG
Winding Details
efficiency. Make sure the both capacitors C6 and C7 have 12 V: 6T 4 x 25 AWG T.I.W.
equal secondary loop areas to balance the ripple currents in (T.I.W. = Triple Insulated Wire)
each. Winding Order 1/2 Primary, tape, 1/2 primary (1-3),
• Clamp: for lowest cost use an RCD clamp replacing Zener (Pin Numbers) tape, Bias (5-4), tape,
VR1 with a power resistor. For best no-load performance, 12 V (9-10, 6-7), tape
use the Zener clamp as shown. Primary: 876 µH 10% at 132 kHz,
Inductance
• Reference voltage: Use low current Zener secondary Leakage: 28 µH (maximum)
reference with 5 mA bias current for lowest cost. Use TL431 Primary Resonant Frequency 570 kHz (minimum)
as shown for both better regulation accuracy and no-load
consumption (due to lower bias current 1 mA). Table 1. Transformer Construction Information.
.35
PI-3422-112602
.30
Input Power (W)
.25
.20
.15
.10
.05
0
80 120 160 200 240 280 3
AC Input Voltage
Figure 2. PIN vs VIN Curve.
3-249
Rev. A 11/02
Design Idea DI-51
®
DPA-Switch
5 W Flyback DC-DC Converter

DC-DC Converter DPA423R 5W 36-75 VDC 5V Flyback
Design Highlights and 75 V without the cost of additional line sense components.
Resistor R3 programs the internal current limit of the DPA423R
• Small footprint: 35 mm x 20 mm (1.4 in. x 0.8 in.) to 53% of nominal. This limits the overload power that can be
• High efficiency flyback (>80% min.) delivered in a fault condition.
• 8.8 W per cu. in.
• Low component count Zener VR1 clamps the leakage inductance spikes to keep the
• Accurate line OV and UV protection DRAIN voltage at a safe level. The bias supply for U1 is
• Thermal, short circuit and output overload protection provided from the auxiliary flyback transformer winding (pins
• No current sense components 2 and 4), rectified and filtered by diode D1 and capacitor C23.
Operation A snubber for diode D2 (capacitor and resistor) can be used, but
was not needed in this application. Inductor L2 and capacitor
DPA-Switch greatly simplifies the design compared to a discrete C12 form a post filter to reduce high frequency output switching
implementation. Resistor R1 sets the input under/over voltages ripple. A soft-finish network, C18, D3 and R7, eliminates
to 33 V and 86 V, respectively. Including tolerances, these output turn-on overshoot. The remaining components provide
thresholds guarantee the converter is operational between 36 V output voltage regulation and loop compensation.
C7 1 nF R14
1.5 kV 10 Ω
L1 C10 C11 L2 C12
+ VIN 10 µH D2 SL23 100 µF 100 µF 300 nH 100 µF
36-75 VDC 0.85 A 1A/30 V 10 V 10 V 6A 10 V 5 V, 1 A
3 1
T1
7,8
5,6 RTN
FL
D1 BAV19WS
2
C23
4.7 µF
4 3 20 V
R1 R7 U2 R10
619 kΩ U2 10 kΩ 18 kΩ
1% 1%
C1 C2
0.22 µF 1 µF
100 V 100 V DPA-Switch C16
U1 D3 220 nF
DPA423R BAV19WS
D L R6 R12
150 Ω 5.1 Ω
CONTROL
C C17 R9
1 µF 220 Ω
C18
S X F R4 10 µF
R3 1.0 Ω
VR1 14.4 kΩ C5 10 V
SMBJ 1% 47 nF U3
150 A C6 R11
68 µF LM431AIM3 18 kΩ
-VIN 10 V 1%
PI-3547-062403
Figure 1. DPA-Switch Flyback DC-DC Converter.
.
3-250
Rev. A 07/03

• For the nominal under-voltage set point VUV:
EFD-10
R1 = (VUV – 2.35) / 50 µA Core Material Ferroxcube 3F3
VOV = (R1 x 135 µA) + 2.5 V 2
AL of 100 nH/T
Bobbin EDF-10 8 pin

• For highest efficiency designs: use continuous conduction (or equivalent)
mode operation designed at approximately 0.4 KRP; minimize
1/2 Primary (1-FL), Tape, Bias
turns in the transformer while keeping AC flux density (BM) Winding Order
(4-3), 5 V (5-8),
< 3000 Gauss; fully fill a single layer for each winding to (pin numbers)
Tape, 1/2 Primary (FL-2), Tape
minimize leakage inductance and maximize copper fill
factor; use a Schottky rectifying diode (D2) with a low Primary Inductance 174 µH ± 10%
forward drop (in this case, the SL23 diode has a Primary Resonant
Vf = 0.320 V at 125 °C/2A). 4.7 MHz (minimum)
Frequency
• Resistor R3: the PIXls spreadsheet calculates the peak
current (IP) of the power supply. Resistor R3 is chosen to set Leakage Inductance 1.0 µH (minimum)
the internal current limit 10% to 15% above the calculated
IP value. This limits overload power (worst case is at high Table 1. Transformer Construction Information.
input line).
• Set resonant frequency of post-filter (L2, C12) beyond 85
PI-3548-060403
crossover frequency (typically 5% to 10% of switching 84
frequency).
83
• For main secondary current loop from transformer pin 8 to
diode D2 and capacitors C10, C11 and back to pin 6 of the 82
Efficiency (%)
transformer: ensure identical path length for C10 and C11 to 81

guarantee they equally share the ripple current. 80
• Due to the very tight size constraints on this power supply, 79 36 VDC
the drain voltage traces should be kept as short as possible
78 48 VDC
and where possible, shielded by surrounding them with 72 VDC
source potential traces. This will prevent noise coupling to 77
the low-voltage signal pins of the DPA-Switch. 76
75
1 2 3 4 5
3
Pout (W)
3-251
Rev. A 07/03
Design Idea DI-52
®
DPA-Switch

Telecom DPA426R 60 W 36-75 VDC 12 V Forward Sync. Rect.
Design Highlights still allowing passive MOSFET drive without gate overvoltage,
which would result from direct resistor drive.
• High efficiency: 91.5% at 36 VDC using synchronous Resistor R1 programs the under/over voltages and linearly
rectification reduces the maximum duty cycle with input voltage to prevent
• Capacitor coupled synchronous rectification allows core saturation during load transients. Components D1, D2,
higher output voltages without overstressing MOSFET C9, and L2 implement a resonant clamp circuit to catch and re-
gates circulate the transformer leakage energy during normal
• No current sense resistor or current transformer required operation, with Zener VR1 providing absolute clamping for
• Output overload, open loop and thermal protection transient conditions.
• 300 kHz switching frequency to allow sufficient
transformer reset time Capacitor C21 charges the gate of Q2, the forward synchronous
• 3.55 x 2.1 x 0.6 inch (approx. 13.4 W/cubic inch) rectifier MOSFET. Resistor R21 limits gate oscillation and
R22 provides gate pull down. Zener diode VR20 limits the Q2
Operation gate voltage during conduction and also reverse charges (resets)
C21 during the Q2 off time.
implementation. The capacitor coupled synchronous rectifier A similar drive technique is used for the catch synchronous
drive used in this design is useful for higher voltage outputs, rectifier MOSFET Q1 (with C22, R23, R24, and VR21).
C7 1 nF R14
1.5 kV L4
3 T1
10 Ω
C20 C21
10,9
40 µH
4,5
C23 C24
100 µF 100 µF
16 V 16 V
C25
1 µF
50 V 12 V, 5 A
1 nF 2.2 nF
6,7 VR20
+ VIN 15 V
36-75 VDC VR21 R23
1 R21 15 V 10 Ω
R22 D20
L1 R20 10 Ω 10 kΩ 12 CWQ
1 µH 0.5 Ω 10 FN
2.5 A 1W
D1 R24
R1 9,8 10 kΩ RTN
ESD1 619 kΩ
1% Q2 Q1
Si4486 Si4486
C22 L3
D3 1 nF 2.2 mH
4 BAV19WS
C9 40 mA
150 pF 5
C1-C4 200 V D4 R10
0.22 µF 2 BAV19WS R7 U2 38 kΩ
100 V 10 kΩ 1%
C8
L2 1 µF
220 µH U1 U2
DPA426R PC357
NT
D L DPA-Switch C13
D3 100 nF
CONTROL BAV19WS
D2 C R12
R6
ESD1 150 Ω 5.1 Ω
R4 C17 R9
S X F 1 µF
1.0 Ω 220 Ω
VR1 C5 C15
SMBJ R3 0.22 µF C6 10 µF
150 A 11 kΩ 68 µF 10 V
-VIN 1% 10 V U3 R11
LMV431 10 kΩ
AIM5X 1%
Figure 1. DPA426R - 60 W, 12 V, 5 A, DC-DC Converter. PI-3550-062403

.
3-252
Rev. A 07/03
MOSFET Q1 is driven by the transformer (T1) reset voltage and

operates only when Q2 is off. Diode D20 provides a conduction TRANSFORMER PARAMETERS
path for the output inductor (L4) current when the transformer Core Material Ferroxcube P/N: EFD25, ungapped
reset is complete.
Bobbin 10-pin EFD25 surface mount bobbin
Key Design Points Primary 5T + 5T, 4 x 26 AWG
Winding Details Bias 5T, 1 x 30 AWG
• Transformer core reset is critical in this design. MOSFET 12 V 6T, 4 x 26 AWG
gate loading will affect the transformer-reset waveform.
Winding Order and Bias (2-5), Primary-1 (4-NC),
Capacitors C20, C22 and CQ1GS will all load transformer Pin Numbers 12 V (9,10-6,7), Primary-2 (NC-1)
reset. Choose values to ensure sufficient reset at low line and
safe maximum drain voltage at high line. Also use Primary Inductance Pin (1-4): 190 µH 25% @ 300 kHz
300 kHz operation for longest reset time.
Primary Resonant
• Capacitors C20 and C22 will capacitively drive MOSFET 3.8 MHz (minimum)
Frequency
gate capacitances CQ2GS and CQ1GS, respectively. C20 and
C22 should be chosen to ensure that gate drive voltage Leakage Inductance 1 µH (maximum)
attains turn-on threshold of MOSFET (VgTH) at worst case
conditions (low line for forward MOSFET). Table 1. Transformer Construction Information.
• Reduce transformer leakage inductance by filling each
winding layer across the entire width of the bobbin.
INDUCTOR PARAMETERS
100 Ferroxcube P/N: EFD20-3F3
PI-3551-060503
Core Material
gap for inductance required
90 Bobbin 10-pin EFD20 surface mount bobbin
Winding Details Main 18T, 3 x 24 AWG

Efficiency (%)
80
Winding Order and
Main (4,5-9,10)
Pin Numbers
70 36 VDC Pin (4,5-9,10): 40 µH 10%
Inductance
48 VDC @ 300 kHz
72 VDC
60
Table 2. L4 Output Inductor Design Parameters. 3
50
0 1 2 3 4 5
Pout (W)
3-253
Rev. A 07/03
Design Idea DI-53
®
DPA-Switch
50 W DC-DC Dual Output Converter

Telecom DPA425R 50 W 36-75 VDC 5 V & 3.3 V Forward Sync. Rect.
and L2 implement a resonant clamp circuit to catch and

Design Highlights recirculate the transformer leakage energy during normal
• High efficiency: 90% at 36 VDC using synchronous operation, with Zener VR1 providing absolute clamping for
rectification transient conditions.
• Dual output with tight cross-regulation ±4% from zero to
full load on both outputs Capacitor C21 charges the gate of Q2, the forward synchronous
• Output overload, open loop and thermal protection rectifier MOSFET of the 5 V output. Resistor R21 limits gate
• 300 kHz switching frequency to allow sufficient oscillation and R22 provides gate pull-down. Zener diode
transformer reset time with sync rectification VR20 limits the Q2 gate voltage during conduction and also
• 3.85 x 2.25 x 0.6 inch (~9.62 W/in3) reverse charges C21 during the Q2 off time. The same drive
technique is used for the forward synchronous rectifier MOSFET
Operation (Q4) of the 3.3 V output (with C22, R24, R25, and VR21).
DPA-Switch greatly simplifies the design compared to a discrete MOSFETs Q1 and Q3 are driven via resistors R23 and R26
implementation. This design uses a coupled output inductor and from the transformer (T1) reset voltage and operate only when
synchronous rectification to achieve excellent cross-regulation Q2 and Q4 are off. Diodes D20 and D21 provide a conduction
and high efficiency. path for the output inductor (L4) current when the transformer
reset is complete.
Resistor R1 programs the under/over voltages and linearly
reduces the maximum duty cycle with input voltage to prevent A winding on the coupled inductor L4, along with diode D4 and
core saturation during load transients. Components D1, D2, C9 capacitor C9, provide the DPA-Switch bias voltage.
3 L4
3.5 µH 5 V, 6 A
(8 A pk)
9,10 7,8
T1
8,9 R23
10 Ω
Q1 D20 R26 3.3 V, 6 A
10 Ω 1,2 3,4 (8 A pk)
L1
+ VIN 1 µH 4,5
Q3
36-75 VDC 2.5 A
1 R25
C21-C22 10 kΩ
R20 4700 pF D21
3.3 Ω VR21
R1 R21 15 V
D1 619 kΩ 2,3 10 Ω
ES1D 1% Q4
R24 C23-C26 C27 C28 RTN
10 Ω 100 µF 1 µF 1 µF
10
C9 6,7 10 V
150 pF 5 6
200 V C20 Q2 R22 VR20
3.3 nF 10 kΩ 15 V D4
C7
1 nF R10 R12
L2 1.5 kV 8.66 kΩ 15.9 kΩ
U2
220 µH R7 1% 1%
10 kΩ
C1-C3 U2
1 µF C9
100 V DPA-Switch 4.7 µF PC267
16 V N1T C16
U1 D3 100 nF
DPA425R BAV19WS
D L R6 R12
150 Ω 5.1 Ω
CONTROL
C
D2 R9
ES1D 220 Ω
C15
S X F R4 10 µF
1.0 Ω C14
VR1 C5 10 V 1 µF
SMBJ 0.22 µF
150 A R3 C6 U3 R11
15 kΩ 68 µF LM431 10.0 kΩ
-VIN 1% 10 V AIM3X 1%
PI-3561-072203
Figure 1. DPA425R - 50 W, 5 V, 6 A and 3.3 V, 6 A DC-DC Converter.

.
3-254
Rev. A 07/03

• Capacitors C20, CQ1gs and CQ3gs will all load transformer Core Material Ferroxcube P/N: EFD25-3F3, ungapped
reset. Choose values to ensure sufficient reset at low line and
safe maximum drain voltage at high line. Also use Bobbin 10-pin EFD25 surface mount bobbin
300 kHz operation for longest reset time.
Primary 11T, 4 x 28 AWG
• Capacitors C21 and C22 will capacitively drive MOSFET Winding Details 3.3 V 2T, 2 x 4 x 26 AWG
gate capacitances CQ2gs and CQ4gs (respectively). C21 and 5 V 3T, 2 x 4 x 26 AWG
C22 should be chosen to ensure that gate drive voltage
Winding Order and 5 V (6, 7-8, 9), Primary (1-10), 3.3 V
attains turn-on threshold of MOSFET (VgTH), at worst case Pin Numbers (4.5-2.3)
conditions (low line for forward MOSFET).
• Reduce transformer leakage inductance by filling each Primary Inductance 250 µH 25% at 300 kHz
winding layer across the entire width of the bobbin.
Primary Resonant
• Higher efficiency (+1%) can be acheived by using a 3.8 MHz (minimum)
Frequency
DPA426R and increasing R3 to reduce the internal current
limit. Leakage Inductance 0.8 µH (maximum)

95
PI-3562-061603
90
85 INDUCTOR PARAMETERS
Efficiency (%)
80 Core Material Ferroxcube P/N: EFD25-3F3 ungapped
75 Bobbin 10-pin EFD20 surface mount bobbin

36 VDC
70 54 VDC 5 V 6T, 2 x 4 x 26 AWG
72 VDC Winding Details 3.3 V 4T, 2 x 4 x 26 AWG
65 Bias 12T, 1 x 30 TIW
Winding Order and 5 V (9, 10-7, 8), 3.3 V (1, 2-3, 4),
60 Pin Numbers Bias (FL1-FL2)
2 4 6 8 10 12
IOUT1 + IOUT2 (A) Inductance Pin (1, 2-3, 4): 3.5 µH 10% at 300 kHz
Figure 2. Efficiency vs. Output Power. Table 1. Inductor Design Parameters.

3
3-255
Rev. A 07/03
Design Idea DI-55
®
TOPSwitch-GX
20 W (25 W Peak) DVD Supply

DVD TOP245P 20 W (25 W pk) 85-265 VAC 3.3 V / 5 V / 12 V / -24 V Flyback
Design Highlights The external current limit programming and remote ON/OFF
(inhibit) functions of the M pin allow current mode control and
• Simple, low cost, low part count solution reduced switching frequency at light and no-load conditions.
• No heatsinks required Current mode control is implemented by R2, Q3, R3, C16, R4
• Low EMI-frequency jitter allows EN55022B/FCC B and R6.
compliance with simple EMI filter
• High efficiency, >75% at 90 VAC Feedback current above ~2 mA (U1 supply current) forward
• Low zero load power consumption, <100 mW at biases Q3 and pulls up R6. This adjusts the sink current out of
230 VAC the M pin, thereby allowing the output voltage feedback loop to
• Low standby power consumption, <1 W input at 0.5 W control the primary switch current.
output, 230 VAC
• Excellent cross-regulation Resistor R6 sets the maximum current limit, while R2 and C16
• Differential and common mode surge immunity to 3 kV provide slope compensation. The value of R4 is chosen to
(EN 61000-4-5) ensure that current does not flow into the M pin, enabling the
line sensing features of the pin. The current out of the M pin falls
Operation as the load is reduced until the M pin inhibit threshold is
reached. The supply then operates with a fixed 25% current
The TOP245P selected for the design in Figure 1 is ideal for limit, lowering the switching frequency to maintain regulation.
DVD and set-top box applications. The P package removes the This greatly reduces switching losses, maintaining high standby
need for a heatsink while still delivering 20 W/25 W peak at an efficiency and low no-load power consumption.
ambient temperature of 50 °C. VR1 C1 C4 C8 L5
L2
3 F1
RT1
33 µF
400 V
L1
33 µF P6KE
400 V 130
1
2.2 nFY1
T1
EE25L 8
D7
BEAD
3.3 µH +12 V, 500mA
3.15 A 1N5819
t° R1
J1-2 250 VAC 68 Ω
C15 C20
LINE 470 µF 180 µF OPTIONAL
C2
RV1 C3 0.01 µF 25 V 25 V
275 VAC 12
0.047 µF R7 1 kV C17 R14 R16
J1-1 X2 1N4007 x 4 L3 470 µF 1.13 kΩ 2.0 kΩ R15 Q1
5 mH 1 kΩ 3.3 µH
4 13 10 V 1% 1% 2.4 kΩ 2SA0885 +5 V, 2.5 A
NTRL CM Choke
D11 J2-3
SB540CT D8
1N4005
C12 Q5
1200 µF 2N3906
10 V Q4
2N3904
D9
D10 L4 1N4005
D5 SB540CT 3.3 µH +3.3 V, 2 A
1N4007GP 9
J2-6
C12 R17 C18
1200 µF 200 Ω 470 µF
10 V 10 V
10,11 RET
R13 J2-2, 4, 5, 7
2 kΩ
1%
C9 C6 R11
150 µF R12
150 µF 6.34 kΩ 20.0 kΩ
35 V 35 V 1%
1%
D12 R8
TOPSwitch-GX 1Ω
UF4003
U1
14 1/2 W -24 V, 50 mA
D TOP245P
C13 C16 7 J2-1
CONTROL 47 µF 0.1 µF
C 25 V
5 LTV817A
U2
S M
R3 R2 C14
18 kΩ R10
270 Ω 0.1 µF 10 kΩ
R4 Q3
10 kΩ 1N3906
R6
5.1 kΩ
C5
D6 47 µF U3
1N4148 25 V TL431 R9
10.0 kΩ
1%
PI-3648-071106
Figure 1. 20 W Multiple Output DVD Supply.
3-256
Rev. B 07/06

• For good cross-regulation, minimize transformer leakage – EEL25, N67 or equivalent,
Core Material
use foil for 3.3 V and 5 V outputs; minimize peak primary gap for ALG of 202 nH/T2
currents by designing transformer for continuous conduction
Bobbin 7 pin + 7 pin
mode.
• Shunt regulator (temperature compensated) between 5 V Shield 1: 32T, 2 x 32 AWG
and 3.3 V outputs in dotted box on schematic is optional. It Primary: 63T, 2 x 32 AWG
is only necessary where min and max load conditions do not Bias: 6T, 4 x 32 AWG
Winding Details Shield 2: 4T, 4 x 32 AWG
occur simultaneously on both outputs. 3.3 V/5 V foil: 2T + 1T, 0.12 mm foil
• Feedback is taken from both the 3.3 V and 5 V outputs to the -24 V: 13T, 2 x 32 AWG
reference (U3) via R9, R11 and R12. The 12 V output is DC +12 V: 4T, 4 x 32 AWG
stacked on the 5 V output for enhanced regulation and Shield (NC-1), tape, primary
voltage centering. (1-4), tape, bias (5-7),
Winding Order tape, shield 2 (13-NC),
• Primary clamp components VR1, D5, R7, R1 and C2 limit (pin numbers) foil (10,11-9-13), -24 V
the leakage inductance induced peak drain voltage spike. (14-10,11), 12 V (12-8).
• D5 is a slow recovery diode to recover some of the clamp
Primary: 800 µH 10%
energy. It must be a glass passivated type to guarantee a Inductance
Leakage: 80 µH (max.)
defined trr.
• Use a Zener clamp for lowest zero load input power Primary Resonant
300 kHz (minimum)
Frequency
consumption.
Load Regulation (%)

Voltage
Range
(V) (A) -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7
3.3 0.3-0.6
5 0.3-1.2
12 0.1-0.2
-24 0.03-0.05
Table 2. Worst Case Output Cross-Regulation - all Outputs Taken

from Minimum to Maximum Loads.
3-257
Rev. B 07/06
Design Idea DI-56
®
DPA-Switch
19.2 W DC-DC Converter

Telecom DPA425R 19.2 W 36-75 VDC ±12 V Flyback
Design Highlights minimize fault and overload power. Drain voltage clamping is
provided by Zener diode VR1.
• Low cost 400 kHz flyback design
• ±12 V outputs at ±5% accuracy Output regulation is taken from the +12 V output. The -12 V
• Highly efficient diode rectification design - 80% at 48 V output is magnetically coupled. Shared regulation of +12 V and
• Low component count -12 V may be used if better cross-regulation is required between
• Accurate line OV and UV protection the two outputs. Optional resistor R7, diode D3 and capacitor
• Thermal, short circuit and output overload protection C16 implement a soft-finish network to slow the rise of the
• No current sense components output voltage at start-up, preventing overshoot.
Operation The bias winding provides operating power to the

DPA-Switch. The regulation is fed back from the secondary
through the opto-transistor of U2. The DPA-Switch will go into
implementation. Resistor R1 programs the under/over voltages
auto-restart in the event of optocoupler (U2) failure, or output
and linearly reduces the maximum duty cycle with input voltage
short circuit. The optional resistor R5 and Zener diode VR2
to prevent core saturation during load transients. Resistor R3
provide a fail-safe output regulation path, limiting the
programs the DPA-Switch current limit at 77% of nominal to
instantaneous output overvoltage in the event of U2 failure.
C7
1 nF R14
1.5 kV 10 Ω
3 +VIN
L1
1 µH D30 C30 C31
100 µF 100 µF
L3 C32
300 nH 100 µF
C33 +12 V,
36-75 VDC 2.5 A MBR360 1 µF 0.8 A
16 V 16 V 16 V
1 8
7 RTN
NC RTN
6 C20
D20 100 µF C21 L2
MBR360 16 V 100 µF 300 nH -12 V,
4 16 V 0.8 A
5
D1 BAV19W5 C22 C23
R1 100 µF 1 µF
C1- C2 C3 619 kΩ 2 16 V
1 µF 1 µF U2
1% C4 R10
100 V 100 V 3 4.7 µF 38 kΩ
R7 1%
DPA-Switch 10 kΩ C13
R5
D L U1 180 Ω 100 nF
DPA425R R6
CONTROL 560 Ω R12
C 5.1 Ω
D3 1%
VR2
R4 5.1 V BAVAW5
S X F C5 1.0 Ω C14 R9
VR1 220 nF 1% 1 µF 220 Ω
SMBJ C16 U3
R3 C6 LM41 R11
130 10 µF 10.0 kΩ
-VIN 10 kΩ 68 µF 16 V AIM3
1% 10 V 1%
PI-3649-081103
Figure 1. DPA425R - 19.2 W, ±12 V, 0.8 A, DC-DC Converter.
3-258
Rev. A 09/03
Key Design Points • Good layout practices

- For length of +12 V secondary current loop from
• For the nominal under-voltage set point VUV: transformer pin 8, diode D30 and capacitors C30, C31 and
R1 = (VUV – 2.35) / 50 µA back to pin 7 of the transformer: ensure identical path
VOV = (R1 x 135 µA) + 2.5 V length for C30 and C31 to guarantee they equally share
• For highest efficiency designs: use continuous conduction the ripple current.
mode operation designed at approximately 0.4 KRP; - The same is also true for the layout of the -12 V output.
minimize turns in the transformer and at this (19 W) power • Choosing a larger DPA-Switch will increase efficiency at
level keep AC flux density (BM) <1500 Gauss; fully fill a low and medium input voltages.
single layer for each winding to minimize leakage inductance
and maximize copper fill factor; if possible use Schottky
rectifying diodes (D20 and D30) with a low-forward drop. TRANSFORMER PARAMETERS
• The transformer primary is split in order to minimize leakage
inductance and thus obtain better cross-regulation. Note: Core Material Epcos P/N: P 14x8 N87, ungapped
minimizing primary leakage inductance will improve output Bobbin 8-pin P 14x8 surface mount bobbin
cross-regulation at load extremes.
• The -12 V output is not directly sensed as part of the Primary 7T + 7T, 2 x 29 AWG
Bias 5T, 1 x 36 AWG
regulation loop. Cross-regulation may be improved by adding Winding Details
+12 V 5T, 2 x 29 AWG
a second sense resistor to work in conjunction with R10. -12 V 5T, 2 x 29 AWG
Both resistors R10 and the second sense resistor would be
changed to 76 kΩ each. Winding Order & Primary-1 (4-NC), -12 V (6-5), Bias (2-3),
Pin Numbers +12 V (8-7), Primary-2 (NC-1)
• Set resonant frequency of post-filter (L2, C22 or L3, C32)
beyond crossover frequency (typically 5% to 10% of Primary Inductance 22 µH 25% (at 400 kHz)
switching frequency).
Primary Resonant
3.8 MHz (minimum)
Frequency
Leakage Inductance 0.75 µH (maximum)
3-259
Rev. A 09/03
Design Idea DI-57
®
DPA-Switch

Telecom DPA426R 60 W 36-75 VDC 12 V Flyback
Design Highlights minimize fault and overload power. Drain voltage clamping is
provided by diode D4 and Zener diode VR1 with optional
• Low cost 400 kHz flyback design components C4 and R2 to provide high frequency snubbing.
• Simple Zener referenced 12 V output
• Efficiency – 82% at 36 VDC and full load The output is rectified by diode D2 with optional high frequency
• Low component count damping from components C9, R15 and R16. The output
• Accurate line OV and UV protection capacitors are alternated to share the ripple current evenly
• Thermal, short circuit and output overload protection between the Oscon capacitors (C10-14) and the ceramic
• No current sense components capacitors (C15-C18). A final decoupling ceramic capacitor
C19 is placed at the output pins of the power supply.
Operation
Output regulation is taken from the +12 V output. Zener diode
DPA-Switch greatly simplifies the design compared to a discrete VR2 is DC-biased by resistor R7 with the opto-diode of U2
implementation. Resistor R1 programs the under/over voltages providing feedback and resistor R6 programming the gain.
and linearly reduces the maximum duty cycle with input voltage Optional capacitor C8 implements a soft-finish network to slow
to prevent core saturation during load transients. Resistor R3 the rise of the output voltage at start-up.
programs the DPA-Switch current limit at 85% of nominal to
R15, R16
33 Ω
1/4 W
C9
C7 1 nF 2.2 nF
R14 50 V
3 + VIN L1
1.5 kV 10 Ω
C10-C14
C19
1 µF
36-75 VDC 1 µH, 2.5 A 100 µF, 16 V (OSCON) 16 V 12 V, 5 A
T1
2 9,10
VR1
SMCJ
100 A D2 SBG3045CT
6,7 RTN
NC
D1 BAV19WS C15-C18
D4 47 µF, 16 V (CERAMIC)
ES2D 1
C23
4.7 µF
4 5 20 V
R1 R7 U2
619 kΩ U2 1 kΩ PC 357N1T
1%
C1 C2 C3
1 µF 1 µF 1 µF
100 V 100 V 100 V
DPA-Switch
U1
DPA426R R6
150 Ω
C4
180 pF D L
200 V CONTROL
C
C8
S X F R4 1 µF
R3 1.0 Ω
R2 8.8 kΩ C5 16 V
68 Ω 1% 220 nF VR2
1/4 W C6 BTZ52C11
68 µF
-VIN 10 V
Figure 1. DPA426R - 60 W, 12 V, 5 A DC-DC Converter. PI-3662-082603
3-260
Rev. A 08/03
The bias winding is rectified and filtered by D1 and C23 and

provides operating power to the DPA-Switch. The regulation is TRANSFORMER PARAMETERS
fed back from the secondary through the opto-transistor of U2. Core Material Ferroxcubed P/N: EFD25 3F3
Key Design Points Bobbin 10-pin EFD25 surface mount bobbin
Primary 8T + 8T, 2 x 24 AWG

• For the nominal under-voltage set point VUV:
Winding Details Bias 5T, 1 x 34 AWG
R1 = (VUV – 2.35) / 50 µA +12 V 5T, 4 x 27 AWG
VOV = (R1 x 135 µA) + 2.5 V
• For highest efficiency designs: use continuous conduction Winding Order and Primary-1 (4-NC), Bias (1-5), + 12 V
Pin Numbers (9, 10-6, 7), Primary-2 (NC-2)
mode operation, this design uses approximately 0.5 KRP;
minimize turns in the transformer and at this (60 W) power Primary Inductance 21 µH 25% (at 400 kHz)
level, keep AC flux density BM <1100 Gauss; fully fill a
single layer for each winding to minimize leakage inductance Primary Resonant
3.0 MHz (minimum)
Frequency
and maximize copper fill factor; if possible use a Schottky
rectifier diode (D2) with a low-forward drop. Leakage Inductance 1 µH (maximum)
• The transformer primary is split in order to minimize leakage
inductance to obtain better efficiency. Table 1. Transformer Design Parameters.
• Tighter output voltage tolerance is possible by using a
TL431 (and associated components) in place of the Zener
diode VR2.
• Follow good layout practices:
- For length of the secondary current loop from transformer
pins 9 & 10, diode D2 and capacitors C10 to C18 and
back to pins 6 & 7 of the transformer: ensure identical
path length for each of the capacitors C10 to C18 to
ensure they equally share the ripple current.
3-261
Rev. A 08/03
Design Idea DI-58
®
LinkSwitch

During output diode conduction, the output voltage reflected
• Extremely simple circuit – only 15 components for by reducing the internal current limit during CC operation.
production-worthy design Below an output voltage of ~2 V, LinkSwitch enters auto-
• Primary based CV/CC output – no secondary sense restart, limiting average output current to less than 50 mA. The
components required nominal transition from CV to CC occurs at 5.5 V, 0.27 A. The
• ±10% output voltage and ±25% output current tolerances at output envelope characteristic and specification limits are shown
peak power point in Figure 2.
• >62% efficiency (>70% with R1 replaced by an inductor) Together with D3, C4 and R2 are also part of the primary clamp,
• Meets CISPR22B/EN55022B EMI limits with low cost limiting the peak drain to source voltage due to leakage inductance.
resistive input filter Resistor R3 filters the leading edge leakage inductance spike,
• Ultra-low leakage current design <5 µA reducing the error in the feedback voltage. The CONTROL pin
• EE13 core for low cost and small size capacitor C3 provides energy storage for supply start-up and sets
auto-restart timing during fault conditions.
Operation
3 The AC input is rectified and filtered by D1, D2, C1 and C2. Key Design Points
Conducted EMI filter is provided both by a π filter (C1, R1 and • Select transformer turns ratio to give a VOR of 40 V
C2) and a differential filter (RF1 and C1). Together with a to 60 V. Lower values reduce power capability; higher
shield in the transformer (formed from part of the primary), the values increase no-load consumption.
primary and secondary. Resistor RF1 also functions as a fuse. power point at 85 VAC. The value can be adjusted to center
the output voltage.
R1
68 Ω LinkSwitch
Flameproof T1 5.5 V, 0.27 A
D S
1
C U1 C3 104T 5
LNK500 0.22 µF 34 AWG
D1 15 T C5
1N4007 4 30 AWG 220 µF
RF1 C4 12T T.I.W.
2 x 30 AWG 16V
10 Ω R2 0.1 µF 6
L Fusible 21 kΩ 100 V
FILM 3 RTN
85-265 C1, C2
VAC 2.2 µF EE13 D4
400 V D3 LP = 1.36 mH UF4002
N 1N4937 1A 100V
D2 R3
1N4007 100 Ω
PI-3687-091903
3-262
Rev. A 09/03

Core ALG= 101 nH/T2
capacitance: Use double coated/grade 2 wire for primary and
do not vacuum impregnate. Avoid using an RC snubber Bobbin EE13 Horizontal 8 pin
• For resistive loads, increase C3 to 1 µF (electrolytic) to allow Shield: 12T, 2 x 30 AWG
Winding Details Secondary: 15T, 30 AWG T.I.W.
adequate time for start-up at full load.
• For battery loads, an output LC filter is typically not required (T.I.W.: Triple Insulated Wire)
• R1 can be replaced with an inductor for higher efficiency (pin numbers) (4-1), tape, Flux band
(~10% increase). (3-NC)
by ~1 V but increases power consumption by ~10 mW. Primary Resonant
300 kHz (minimum)
• Diode D4 can be replaced with a Schottky for higher Frequency
efficiency.
• See AN-35 for more information.
10 0.3
PI-3686-091803
PI-3373-091803
VIN = 85 VAC
VIN = 265 VAC
8 Low Limit 0.25
Output Voltage (V)
High Limit
0.2
6
0.15
4
0.1
2
0.05
0 0
0 0.1 0.2 0.3 0.4 50 100 150 200 250 300 3
Output Current (A) Input Voltage (VAC)
with Limits.
3-263
Rev. A 09/03
Design Idea DI-60
®
LinkSwitch
Low Cost 2.5 W Regulated Charger/Adapter

Charger/Adpater LNK501 2.5 W 85-265 VAC 5.5 V Flyback
Design Highlights The bias/feedback winding (T1, pins 3-4) provides U1 with
CONTROL pin current. In CV mode, that current is controlled
• Replaces a linear transformer based power supply at the by the U2-phototransistor. At start-up and in CC mode, when
same or lower cost, with better output regulation U2 is OFF, R5 provides the current path. Diode D6 is in the
• No-load input power consumption < 300 mW, at 230 VAC return leg of the winding, making it shield the core from the
input: meets worldwide energy conservation guidelines primary winding. The bias winding and the primary-to-secondary
• Extremely simple circuit – requires only 29 components! shield winding (T1, pin 1) both reduce EMI. Resistor R3 and
• Output voltage (CV) tolerance: ±10% at peak power point C4 reduce EMI.
• Output current (CC) tolerance: ±25% when L ≤ ±10%
• Features short-circuit, open loop and thermal protection CONTROL pin capacitor C6 stores energy and supplies it back
• Typically about 70% efficient! to U1 at start-up, determines the “restart attempt rate” in the
• Meets EN550022 B EMI without a Y-1 Safety capacitor auto-restart mode, shunts high frequency switching noise around
• Ultra-low leakage current: < 5 µA at 265 VAC input U1 and provides U1 with the instantaneous MOSFET gate-
drive current it requires. The combined voltages of VR1, R7
Operation and the U2-LED determine the output voltage. Resistor R8
provides bias current to VR1. The output voltage can be fine-
Fusible resistor RF1 gives short-circuit fault protection and
tuned by adjusting the values of R7 and R8.
limits start-up inrush current. Inductors L1 and L2 and capacitors
C1 and C2 form a low-cost pi (π) filter that attenuates conducted
LinkSwitch solutions must only operate in discontinuous
EMI. Transformer (T1) winding phasing and D7 orientation let
conduction mode. PO ~ 0.5 L I2f, where PO = Output Power,
no secondary winding current flow when the U1-MOSFET is
L = transformer primary inductance, I = LinkSwitch peak
3 ON, so the primary winding current stores its energy in the core
of T1. When the U1-MOSFET turns OFF, the energy stored in
current, f = Switching frequency and η = Efficiency. I2f is
accurately controlled for LinkSwitch; therefore, P O is
T1 drives current out of the secondary winding, forward biasing
proportional to L.
D7, charging C7 and developing/maintaining the output voltage
across C7. The RCD network of C3, D5, R1 and R2 clamps the
flyback voltage across the primary winding, as the U1-MOSFET
turns OFF. C3 T1 EE13 D7
D1-D4 L1 1 nF
1.0 mH Lp = 2.36 mH 11DQ06
1N4005 x 4 500 V 5.5 V, 0.45 A
8
12T
26 AWG TIW
1 RTN
5
1 4
114T
34 AWG 3
L
2
D5
85 - 265 1N4007G C4
VAC 100 pF
500 V
PC817A
PC817A
N
D U2 U2
C
LinkSwitch
L2 U1
S C6 VR1
Ferrite LNK501 D6
Bead 220 nF 5.1 V
BAV20 2%
PI-3695-103103
Figure 1. 2.5 W LinkSwitch Based Charger/Adapter.
3-264
Rev. B 12/04
Typical applications are chargers for cell phones, PDAs, portable 300
PI-3697-091003
audio devices and shavers or power sources embedded within
home appliances and consumer electronics, such as TV standby 250
and bias supplies.
Input Power (mW)

200
Key Design Points
150
• Set VOR within 36 V to 60 V (50 V being optimum)
• Transformer primary inductance tolerance must be 100
≤ ±10%, to maintain CC limit tolerances (±25/20%)
• To allow more time for reaching regulation at startup (or into 50
a fully resistive load), increase C6 to 1 µF
• If battery voltage is less than 2 V, then the LinkSwitch will 0
not come out of its auto-restart mode 60 90 120 150 180 210 240 270
• To lower the ripple voltage into non-battery loads, an LC Input Voltage (VAC)
filter or LDO must be added onto the output
Figure 3. No-load Input Power Consumption.
6.5
PI-3696-091003
6.0 TRANSFORMER PARAMETERS

5.5
Core Material TDK PC40 EE13, AL = 182 nH/T2
5.0
Output Voltage (V)
4.5 Bobbin EE13 Horizontal 8 pin

4.0 115 VAC
230 VAC Bias: 39T, 34 AWG
3.5 Low Limit Primary: 114T, 34 AWG
3.0 Winding Details
High Limit Shield: 13.5T, 2 x 31 AWG
2.5 Secondary: 12T, 26 AWG (TIW)
2.0 Bias (4-3), tape,
1.5 Primary (2-1), tape,
Winding Order (pin numbers)
1.0 Shield (1-open), tape,
0.5 Secondary (6-5), tape
0 Primary Inductance 2.36 mH ±10%
50 150 250 350 450 550
Primary Resonant Frequency 300 kHz (minimum)
Output Current (A) 3
Figure 2. Load Regulation – CV/CC Figure 4. Efficiency vs. Output Current.
Characteristics.
3-265
Rev. B 12/04
Design Idea DI-67
®
TOPSwitch-GX
Isolated, Power Factor Corrected (PFC), 17 W LED Driver
Application Device Power Output Input Voltage Output Current Topology

LED Arrays TOP246F 17.6 W max 108-132 VAC 60 Hz 700 mA (16-24 V) Flyback
Design Highlights The DC input capacitor (C3, 100 nF) was sized so that its
voltage approaches zero at the AC input zero crossings (see the
• 700 mA of output current regulated to within ± 5%
middle waveform of Figure 2).
• Power factor: > 0.98, THD: ≤ 9.6%
• No output current overshoot at power-on
A 220 µF capacitor (C6) was chosen for the bias supply to
• Temperature range: -40 °C to +80 °C
minimize the 120 Hz ripple current into the current source (Q1),
• Harmonics comply with IEC61000-3-2, Edition 2.1
which provides control current to U1. The output rectifier (D9)
• Conducted EMI complies with CISPR-22 B
must be rated for an average of 3.5 A. Capacitor C7’s value (680
µF) sets the magnitude of the output ripple current to 600 mA
Operation peak to peak, at 120 Hz.
This low-cost, TOP246F based PFC LED Driver takes advantage
Resistors R7, R8, R9 and U2’s LED set the 700 mA average
of built-in TOPSwitch-GX features. This supply is current (not
current limit. The U2 phototransistor drives the current source
voltage) regulated, except in the case of no-load. Without a
(Q1) and the PFC-loop filter capacitor (C8, 100 µF). Capacitor
load, the output voltage is limited to about 30 V (max), by R6
C8 was sized to provide the low loop bandwidth necessary for
and VR2. Configured as a flyback converter, this circuit operates
high power-factor. R4 is the power-off discharge path for C6
in the discontinuous conduction mode. It can deliver an average
and C8.
of 700 mA (1 A at the peak of output ripple) over a 16 V to
24 V range, which makes it ideal for driving high current LED
The CONTROL pin bypass capacitor (C5, 1 µF) is just large
arrays, such as the Luxeon 12 UP LED Ring.
enough to allow smooth start-up of the output load current, and
yet small enough to prevent output current overshoot. A larger
3 C4 value of C5 would increase start-up delay time.
2.2 nF 700 mA
Y CAP 16-24 V
D1-D4 VR1 D9
+
IN4004 L2 T1 8
P6KE200A BYV28-200 C7 R6
150 uH 680 uF 100 Ω
35 V 5%
1 7
C3
100 nF 5 6 D8
UF4002
D5 2 4
C2 UF4005
100 nF C6 R4 R2 R3
X2 CAP 220 uF 10 kΩ 499 Ω 1.00 kΩ
2 3 3 25 V 5% 1% 1%
L1 27 mH
Q1
1 4 D6 PN2907A VR2
C1 UF4005 1N5254B
100 nF
X2 CAP D L TOPSwitch-GX
R5
RV1 U1 D7 3.01 kΩ
150 V CONTROL TOP246F 1N4148 1%
C R7
100 Ω
F1 T1A 1%
250 V S X F
R1 C5 C8
10.0 kΩ 1.0 uF 100 uF R8 1.50 Ω, 1%
108-132 VAC 1% 25 V
60 Hz
L N U2
PC81711NSZ RETURN
R9 10.0 Ω, 1%
PI-3746-110303 Figure 1. Isolated Constant Current PFC LED Driver.
3-266
Rev. A 10/03

• To have high power factor, a constant duty factor must be EF-20 or Equivalent
maintained over the 8.33 ms half cycle period. Therefore, Core ALG of 1570 nH/T2
the bias supply voltage and the U1 CONTROL pin current
Miles-Platts EF0700 EF20
must remain extremely constant. The values of C6 and C8 Bobbin
8 Pin Horizontal
must be chosen accordingly.
Primary: 70T, 2 layers, 29 AWG
• Decreasing the value of C8 will reduce the turn-on delay Secondary: 13T, 2 x 32 AWG
Winding Details
time, but will also degrade the power factor. Triple Insulated Wire
• Because low-cost is the goal of this low-loop-gain design, Bias: 9T, 2 x 23 AWG
the tolerance of the output current depends on the CTR of the Primary: 2-5, tape
opto-coupler and the (unregulated) value of the bias voltage. Winding Order Secondary: 8-7, tape
The restricted AC input voltage range allows using the (pin numbers) Primary: 5-1, tape
Bias: 3-4, tape 3 layers
forward (not flyback) configuration for the bias winding. If
the AC input voltage range is extended, voltage regulation Primary Inductance 350 µH ±10%
of the bias supply circuit will be required. Primary Resonant
Frequency 2.0 MHz (Min)
Leakage Inductance 10 µH (Max)

PI-3747-110403
0.5 A/Div. Table 1. Transformer Construction Information.

0A
740
PI-3748-110303
Average Output Current (mA) +5% Upper Specification Limit
Voltage (V)
0V 720
100 V/Div.
700
LED Current must be maintained

680 within manufacturer's specified
0.5 A/Div.
temperature range.
0A
0 25 50 -5% Lower Specification Limit
3
Time (ms) 660
-40 -20 0 20 40 60 80
Figure 2. PFC LED Driver Waveforms.
Top: Input Current at 120 VAC 60 Hz. Ambient Temperature (°C)
Middle: C3 Capacitor Voltage. Figure 3. PFC Driver Current vs. Temperature.
Bottom: Output Current (with 20 V LED Load).
3-267
Rev. A 10/03
DI-89
Design Idea DI-69
®
DPA-Switch
15 W Multi-output DC-DC Coverter

VoIP Phone DPA424P 15 W 36-75 VDC 5 V / 7.5 V / 20 V Forward
Design Highlights capacitance provides optimum reset for transformer T1. Zener
VR1 clamps the peak drain voltage to a safe level during
transient conditions.
• Built-in accurate OV/UV with single resistor
programming
Resistors R21, R22, C21 and MOSFETs Q21 and Q22 form
• High efficiency (88%) using synchronous rectification
a capacitively coupled direct driven synchronous rectifier for
• Multiple outputs with good cross-regulation
the main (5 V) output. Zener diode VR21 acts both as a clamp
• Built-in output overload, open loop and thermal
and as a diode to quickly recharge the Q21 drive capacitor
protection
C21. Resistor R23 holds Q21 off when no switching signal
• 400 kHz switching frequency
is present.
• No primary current sense resistor required
The 20 V output is generated from a flyback winding on the
Operation L2 inductor, which is rectified and filtered by diode D41 and
Resistor R1 programs the input under/over voltages to 33 V and C41. Zener VR31 and diode D32 provide a pre-load on the
86 V. It also linearly reduces the maximum device duty cycle 7.5 V output to enhance regulation at light load.
(DCMAX) with increasing input voltage, helping to prevent core
saturation during transients. D41
BAV19WS 20 V, 10 mA
Capacitor C1, C2 and L1 provide line filtering. Resistor C41 J2-4
4.7 µF, 35 V
R2 programs the U1 current limit. The Q22 reflected gate VR31 D32
3
4 3 6.8 V IN4148
J1-1 L1 D31
36-75 VDC 1 µH 2.5 A 20CJQ060 7.5 V, 0.4 A
1 8
+ 7 6 C31 J2-3
Q22 100 µF
Si4804 10 V
3 7 C25
L2 C22-C24 R4 1 µF
6 C21 16 µH 4 A 100 µF 5 V
R1 2.2 nF 160 Ω 10 V 5 V, 2.4 A
619 kΩ 8 5
DC 1% R21 J2-2
Input 4 10 Ω 7 2
Voltage R22 D6
10 Ω BAV
5 19WS RTN
T1 Q21 VR21 D21 J2-1
Si4804 SL13
R23 15 V
C6 U2
C1 C2 10 kΩ 4.7 µF
1 µF R16
1 µF 20 V 10.0 kΩ
100 V 100 V R11
DPA-Switch U2 1%
10 kΩ
U1 PC357N1T
DPA424P R12 C12
D L 150 Ω 100 nF
CONTROL
R13
C 11 Ω
D11
BAV19WS
S X F R3 C11 C13 R14

VR1 1.0 Ω 2.2 µF
SMBJ 68 nF 1 kΩ
C4 10 V
150 220 nF C5 U3
R2 47 µF LM431AIM3 R15
13.3 kΩ 10 V 10.0 kΩ
1% 1%
RTN PI-3799-082404
J1-2
Figure 1. 15 W DC to DC Converter Using DPA424P.
3-268
Rev. B 08/04
Key Design Points VOUT

Voltage
Range
Load
Range
Cross-Regulation (%)
• Zener VR1 safely limits the DRAIN voltage below BVDSS. (VDC) (%) -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8
5 36-72 20-100
• At zero load, maximum input voltage, the bias voltage 7.5 36-72 0-100
across C6 should be >8 V (12 V to 15 V under normal 7 36-72 100
conditions).
Table 1. Worst Case Output Cross-Regulation - All Outputs
• The 5 V output is the regulated output. All other outputs Taken from Minimum to Maximum Load.
are derived from it. Therefore, tight transformer secondary
coupling and low PC board trace impedance from the
5 V output to the 7.5 V output are crucial to achieve good
cross-regulation. TRANSFORMER PARAMETERS
• The transformer must reset completely under all line and load Ferroxcube P/N: PTS14/8-3F3,
Core Material
conditions to prevent core saturation. The gate capacitance ungapped
of Q22 (with other parasitic circuit capacitances), determines 8-pin P1408 surface mount
the minimum reset period. The transformer core reset Bobbin
B&B B-096 or equivalent
voltage also drives the secondary synchronous rectifier Q22.
Efficiency is maximized when Q22 conduction period is Primary: 8T + 7T, 27 AWG,
maximized. This Q22 conduction period can be extended Winding Details 5 V, 4T, 4 x 28 AWG,
by adding more capacitance (an R-C snubber across the 7.5 V 2T, 4 x 28 AWG
5 V winding). The reset period should be set to give as long Primary-1 (4-3), 7.5 V (7-8),
Winding Order
a reset as possible when operating at low-line (maximum 5 V (5-6)
(pin numbers)
duty cycle) while still guaranteeing complete reset. Primary-2 (3-1)
• Good layout practices should be followed: Primary
- Locate C4, C5 and R3 close to U1 with grounds returned 434 µH ±25% at 100 kHz
Inductance
to the SOURCE pin.
- Minimize the primary and secondary loop areas to reduce Primary Resonant
3.8 MHz (minimum)
parasitic leakage inductance. Frequency
- Locate D21 and Q22 return connections very close to Leakage
1 µH (maximum)
each other to provide best cross-regulation between 5 V Inductance
and 7.5 V.
INDUCTOR PARAMETERS 3
Epcos N87, P/N: B65755-J-R87,
Core Material
Gap for AL = 160 nH/T2
8-pin P1408 surface mount B&B
Bobbin
B-096 or equivalent
Bias 26T, 34 AWG
5 V 6T, 2 x 28 AWG
Winding Details
7.5 V 12T, 28 AWG
20 V 40T, 34 AWG
Winding Order 7.5 V (7-6), 5 V (8-5), 20 V
(pin numbers) (1-2), Bias (4-3)
Pin (5-8): 16 µH ±10% at
Inductance
100 kHz
Table 2. Inductor Design Parameters.
3-269
Rev. B 08/04
DI-89
Design Idea DI-70
®
DPA-Switch
Power over Ethernet Interface Circuit and DC-DC Converter

PoE/VoIP DPA424P 15 W 28-57 VDC 5 V / 7.5V / 20 V Forward
Design Highlights When an input voltage is first applied to the PD, it must present
the correct Discovery Signature Impedance in the voltage range
• Simple Interface Circuit for Power over Ethernet (PoE)
of 2.5 VDC to 10 VDC. This impedance is provided by R51.
Powered Devices (PDs) using DPA424P
• Includes PoE Discovery Signature Impedance (24.9 kΩ from
The second “Classification” phase occurs at input voltages
2.5 VDC to 10 VDC)
15 VDC to 20 VDC. The PD must draw a specified current
• Includes “Class 0” Classification Circuit (0.5 mA to 4 mA
to identify the device class (“Class 0” specifies 0.5 mA to
from 15 VDC to 20 VDC)
4 mA). This is again accomplished by resistor R51.
• Low Cost with Bipolar Pass Switch (87% min. efficiency)
• Highest Efficiency with MOSFET Pass Switch (97% min.)
Bipolar Transistor Pass-Switch
Operation In the third phase the Bipolar pass-switch (Q51 in Figure 1)
Power over Ethernet (PoE) is becoming widely adopted for connects the input voltage to the power supply at voltages above
networking and (VoIP) telecom applications. A typical Powered approximately 30 VDC (28 V + VR52). Zener Diode VR51
Device (PD) solution is shown in Figure 1, having a PoE Interface conducts, driving current through resistor R52 to the base of
Circuit and a DPA-Switch DC-DC converter block (see DI-69 Q51. Resistor R53 prevents turn-on under other conditions.
for full details of operation of the DC-DC converter). Once the power supply has started, components D51, D52, C51
and R54 enhance the base-current drive by coupling power
The PoE specification requires the Powered Device (PD) to from the power supply bias winding.
provide three fundamental functions: Discovery, Classification, D41
BAV19WS 20 V, 10 mA
and Pass-Switch connection.
3 C41
4.7 µF, 35 V
VR41 D42
J2-4
4 3 6.8 V IN4148
L1 D31
J1-1 PoE Interface 1 µH 2.5 A 20CJQ060 7.5 V, 0.4 A
1 8
+ 7 6 C31 J2-3
Q22 100 µF
Si4804 10 V
VR51 3 7 C25
L2 C22-C24 R4 1 µF
28 V 6 C21 16 µH 4 A
5W 2.2 nF 100 µF 5 V 160 Ω 10 V 5 V, 2.4 A
R1 R21 8 5
J2-2
619 kΩ 4 10 Ω 7 2
R52 1% R22
20 kΩ D6
10 Ω BAV
5 19WS RTN
T1 Q21 VR21 D21 J2-1
C1 C2 Si4804 SL13
DC 1 µF 1 µF R23 15 V U2
R51 100 V C6
Input 100 V 10 kΩ 4.7 µF
24.9 kΩ R16
Voltage 1% 1/4 W 20 V 10.0 kΩ
R11 1%
U2 10 kΩ
DPA-Switch PC357N1T
U1 R12 C12
D L DPA424P 150 Ω 100 nF
C51
1 nF CONTROL
R13
50 V C 11 Ω
D11
BAV19WS
D51 S X F R3 C11 C13 R14
BAV19 D52 VR1
BAV19 1.0 Ω 2.2 µF 68 nF 1 kΩ
SMBJ C4
150 10 V
R53 220 nF C5
R54 47 µF U3 R15
20 kΩ R2 LM431AIM3
20 Ω 13.3 kΩ 10 V 10.0 kΩ
1% 1%
Q51
RTN TIP29C (100 V/1 A) PI-3824-082404
J1-2
Figure 1. PoE Interface Circuit–Using a Bipolar Transistor Pass-Switch and DPA424P.
3-270
Rev. C 08/04
MOSFET Pass-Switch • Choose R54 (typically 10-20 Ω) to limit the capacitively

coupled current spike during switching.
An alternative MOSFET-based third phase solution • Alternate transistor MMBTA06.
(Figure 2) connects the input to the power supply at input voltages
above approximately 30 VDC (28 V + VG(Q51)). Resistor R53 MOSFET Pass-Switch:
prevents turn-on under other conditions and Zener diode VR52 • Choose R52 to limit power dissipation in the Zener Diodes
limits the Q51 gate-source voltage when the input voltage is VR51 and VR52.
high (>43 VDC). • Choose R53 to ensure MOSFET turn-off below input voltages
of 28 VDC.
Key Design Points • Choose VR51 to block Q51 turn-on below desired levels
(<28 VDC).
Bipolar Transistor Pass-Switch: • Note higher values of R52, R53 and VR51 will limit
• Choose Q51 bipolar with sufficient current and voltage dissipation.
capability and highest available “DC-Current Gain.” • Choose VR52 to limit the maximum gate to source voltage
• Choose R52 to give sufficient base-drive at turn-on, to allow on Q51 (typically 15 VDC is a good choice).
the DC-DC converter to start. • Alternate MOSFET Si2328.
VIN DC-DC 2.0
PI-3827-013004
0 V to 57 V VR51 +
28 V
500 mW
R51 R52
51 k 1.5
Input Current (mA)

24.9 k/1%
1/4 W 1/8 W
IRF530N
R53 TIP29 Enhanced
VR52 249 k Q51
15 V 1/8 W IRF530N
RTN 200 mW DC-DC 1.0
(100 V / 0.11 Ω)
0V RTN
PI-3825-030304
0.5
Figure 2. PoE Interface Circuit–Using a MOSFET Pass-Switch. Classification
Voltage
Range
30 0
PI-3826-013004
Discovery 0 5 10 15 20 25 30 35
Voltage
Input Voltage (V)
3
Range
25 Figure 4. Classification Current (Class "0").

Resistance (kΩ)
20
PI-3828-032604
IRF530N
TIP29 Enhanced
100
15
Efficiency (%)
90
10
0 5 10 15 20 25 30 35 80
Input Voltage (V) IRF530N
TIP29 Enhanced
Figure 3. Discovery Impedance. 70
60
30 35 40 45 50 55 60
Input Voltage (V)
Figure 5. Pass-Switch Efficiency.
3-271
Rev. C 08/04
DI-89
Design Idea DI-74
®
LinkSwitch-TN
1.25 W Non-isolated Constant Current LED Driver

LED Driver LNK304P 1.25 W 85-265 VAC 12 V, 100 mA Buck-Boost
Design Highlights LinkSwitch-TN uses ON/OFF control to regulate the output

current. When the current into the FEEDBACK (FB) pin
• Universal AC input range – single design worldwide
exceeds 49 µA, MOSFET switching is disabled for the next
• Accurate and stable constant current output
switching cycle. The 49 µA threshold is specified at a pin voltage
• Small size and weight
of 1.65 V (±7%), allowing it to be used as a reference.
• Low cost, low component count solution replaces passive
capacitor or resistor droppers
The voltage developed across R3, which is averaged by C4,
• Fail safe topology – protects load
represents the output current. When this voltage exceeds 2 V,
• High efficiency (>60% at 85 VAC)
the voltage on the FB pin, via divider of R1 and R2, exceeds
• Scalable output power using larger LinkSwitch-TN devices
1.65 V and >49 µA current is fed into the pin. The 2 V across
• Meets EN55022 B EMI limits
R3 sets an output current of 100 mA, or 25 mA for each string
of LEDs. If the load is disconnected or the output is shorted,
Operation no feedback is provided and LinkSwitch-TN enters auto-restart
Using the Buck-Boost topology, the circuit shown in Figure 1 (5% on time). To prevent a high output voltage under no load
generates a non-isolated constant current (CC) output for the optional voltage feedback circuit can be included by adding
driving LEDs. Typical uses include night-lights, neon sign VR1 and D4. The voltage of VR1 is selected to be above the
replacements, emergency exit signs or any application utilizing normal output voltage.
LEDs for lighting.
Select the value of L1 following AN-37, LinkSwitch-TN Design
The AC input is rectified and filtered by D1, D2, C1, C2, RF1, Guide or using the PIXls design spreadsheet. Enter the output
and RF2. Two diodes improve both line surge withstand voltage as the voltage of the LED string and the output current
3 (2 kV) and conducted EMI. Resistor RF1 should be a fusible as the total combined LED current.
flameproof type, whereas RF2 can be flameproof only.
VR1
R2 BZX79C18 D4
300 Ω 18 V, 500 mW UF4005
1%
R1 R3
RF1 RF2 20 Ω C5
8.2 Ω, 1 W D1 47 Ω, 0.5 W 2 kΩ LED 1-20
1% 0.5 W 1 uF, 50 V
Fusible 1N4007 Flame Proof FB BP 1% 25 mA per String
low ESR
D S
C3 D3
0.1 uF UF4005
LinkSwitch-TN 50 V C4
U1 1 A, 600 V
47 uF Ultrafast
LNK304P 10 V
C1 C2 L1 12 V,
85-265 4.7 uF 4.7 uF 1.2 mH 100 mA
VAC 400 V 400 V 220 mA
D2
1N4007
PI-3846-021304
Figure 1. Schematic of a 1.25 W, 12.5 V, 100 mA constant current LED Driver, Using a Non-Isolated Buck-Boost Topology.
3-272
Rev. B 03/04
Key Design Points 80
PI-3847-020904
70
• The output is not safety isolated from the input.
QP
• The circuit shown in Figure 1 has a total output current 60
tolerance of ±12% (including ∆t of 50 °C). 50 AV
• To prevent noise coupling and to decrease EMI, place the Quasi-Peak
input filter components physically away from the source node 40
dBµV
of the LinkSwitch-TN and L1 inductor. The DC input filter 30
capacitors C1 and C2 can be placed, as a barrier, between 20
the AC input and U1/L1.
• Select C4 so that C4 ≥ 20 • (15 ms / R3), to provide 10 Average
adequate filtering of the current sense voltage. Values above 0
50 • (15 ms / R3) will yield little improvement in CC
-10
linearity.
• Select C5 based on the acceptable peak current through -20
the LEDs. Larger values of capacitance reduce peak LED 0.15 1.0 10.0 100.0
current. Typical values are 100 nF to 100 µF, low ESR. With MHz
no capacitor the peak output current is equal to the internal Figure 2. Conducted EMI Plot of the Schematic Shown in Figure 1
current limit of U1. for 3 Strings of 4 LED's (10 V, 66.6 mA).
• With the values of R1 and R2 shown, the value of R3 is
calculated by R3 = 2 V / IO.
• The supply's total required output current is determined by
25
the number of LED strings in the load, and is limited by the
PI-3848-021304
value of L1 and the current limit of U1. For this circuit, the
AC Input = 85 V
load should be ≤100 mA and ≤1.25 W total. Output Voltage (V) 20 AC Input = 265 V
15
10
3
0
0 20 40 60 80 100 120
Output Current (mA)
Figure 3. VI Characteristic of the Schematic Shown
in Figure 1.
3-273
Rev. B 03/04
DI-89
Design Idea DI-75
®
LinkSwitch
Low Cost 2.5 W Regulated Charger/Adapter

Charger/Adaper LNK520 2.5 W 85-265 VAC 5.0 V Flyback
Design Highlights clamps the flyback voltage across the primary winding, as the
U1-MOSFET turns OFF.
• Replaces a linear transformer based power supply at the
same or lower cost, with better output regulation
The bias/feedback winding provides U1 with CONTROL pin
• No-load input power consumption <300 mW at 230 VAC
current. In CV mode, that current is controlled by the U2-
input: meets worldwide energy efficiency guidelines
phototransistor. At start-up and in CC mode, when U2 is OFF,
• Extremely simple circuit – requires only 26 components!
R5 provides the feedback path. Diode D6 is in the return leg
• Output voltage (CV) tolerance: ±5% at peak power point
of the winding, making it shield the core from the primary
• Output current (CC) tolerance: ±25% when L ≤ ±10%
winding. The bias winding and the primary-to-secondary shield
• Features short-circuit, open loop and thermal protection
winding both reduce EMI.
• Greater than 70% efficient!
• Meets EN550022 B EMI without a Y-1 Safety capacitor
CONTROL pin capacitor C6 stores energy and supplies it to
• Ultra-low leakage current: <5 µA at 265 VAC input
U1 at start-up, determines the “restart attempt rate” in the auto-
restart mode, shunts high frequency switching noise around U1
Operation and provides U1 with the instantaneous MOSFET gate-drive
Fusible resistor RF1 gives short-circuit fault protection and limits current it requires. The combined voltages of VR1, R7 and the
start-up inrush current. Inductors L1 and L2 and capacitors C1 U2-LED determine the output voltage. Resistor R8 provides
and C2 form a low-cost pi (π) filter that attenuates conducted bias current to VR1. The output voltage can be fine-tuned by
EMI. Transformer (T1) winding phasing and D7 orientation let adjusting the values of R7 and R8.
no secondary winding current flow when the U1-MOSFET is
ON, so the primary winding current stores its energy in the core LinkSwitch solutions must only operate in discontinuous
3 of T1. When the U1-MOSFET turns OFF, the energy stored conduction mode. PO ~ 0.5 L I2f, where PO = Output Power,
in T1 drives current out of the secondary winding, forward L = transformer primary inductance, I = LinkSwitch
biasing D7, charging C7 and developing/maintaining the output peak current, f = Switching frequency. I2f is accurately
voltage across C7. The RCD network of C3, D5, R1 and R2 controlled for LinkSwitch; therefore PO is proportional to L.
C3 T1 EE13 D7 C7
D1-D4 L1 470 pF 330 µF
1.0 mH Lp = 2.40 mH 11DQ06
1N4005 x 4 500 V 16 V 5.0 V, 0.5 A
7
12T
R2 26 AWG TIW
150 kΩ RTN
3 8
3 1
R1 114T
100 Ω 35 AWG 2
L
4
D5
85 - 265 C1 C2 1N4007G
VAC 4.7 µF 4.7 µF
400 V 400 V PC817A
PC817A
N RF1 R5 R4
8.2 Ω 7.5 kΩ C5 15 Ω
1W D U2 U2 R8
1 µF
Fusible C 50 V 910 Ω
LinkSwitch R7
L2 U1
Ferrite S C6 120 Ω VR1
LNK520 D6 4.7 V
Bead 220 nF 1N4005G 2%
PI-3869-051204
Figure 1. 2.5 W LinkSwitch Based Charger/Adapter.
3-274
Rev. B 05/04
Typical applications are chargers for cell phones, PDAs, portable 300
PI-3871-050404
audio devices and shavers or power sources embedded within
home appliances and consumer electronics, such as TV standby 250
and bias supplies.
200
PIN (mW)
• Set VOR within 36 V to 60 V (50 V being optimum)
• Transformer primary inductance tolerance must be 100
≤ ±10%, to maintain CC limit tolerances (±25%)
• To allow more time for reaching regulation at startup 50
(or into a fully resistive load), increase C6 to 1 µF
• If battery voltage is less than 2 V, then the LinkSwitch will 0
not come out of its auto-restart mode 0 90 120 150 180 210 240 270
• To lower the ripple voltage into non-battery loads, an LC VIN (VAC)
filter or LDO must be added onto the output Figure 3. No Load Input Power Consumption.
• Adjust output voltage by changing R8 (and/or VR1) and
adjust constant current by changing R5.
7 TDK PC40 EE13,
PI-3870-043004
Core Material
AL = 185 nH/T2
6
Bobbin EE13 Horizontal 8 pin
5 Bias: 39T, 34 AWG
Voltage (V)

4 MIN Winding Details
MAX Shield: 13T, 2 x 31 AWG
85 VAC
3 115 VAC
Secondary: 12T, 26 AWG
230 VAC
265 VAC
Bias: (1-2), tape
2
Winding Order (pin Primary: (4-3), tape
1 number) Shield: (3-open), tape
Secondary: (7-6), tape
3
0 Primary Inductance 2.40 mH
0 100 200 300 400 500 600
Load (mA)
Primary Resonant
300 kHz (minimum)
Frequency
Figure 2. Load Regulation–CV/CC Characteristics.
3-275
Rev. B 05/04
DI-89
Design Idea DI-76
®
LinkSwitch
3.1 W Low Parts Count Power Supply

Appliance/Industrial Control LNK520P 3.1 W 100-375 VDC 12 V Flyback
Design Highlights restart (for hard short circuits) and thermal shutdown effectively
produce a very rugged design.
• Replaces a linear transformer based power supply at the
same or lower cost, but with much better performance
LinkSwitch derives all feedback information from the primary
• High Efficiency: >75% at >100 mA of load current
side, thus no optocoupler is required. During output diode
• Primary side regulated: requires no optocoupler
(D4) conduction, the output voltage is reflected through the
• <300 mW no-load power consumption at 375 VDC
transformer turns ratio, providing a primary feedback voltage
• Very low parts count: only 9 components!
(VOR), which is rectified by diode D3 and held by capacitor C4.
• 12 V output: ideal for driving motors, relays, or SCRs
Resistor R3 limits the effects of transformer leakage on the
feedback voltage. Resistor R2 feeds the VOR signal as a current
Operation to the CONTROL pin of the LinkSwitch, controlling duty cycle
The very low parts count LinkSwitch flyback circuit shown (and primary current limit during overload conditions). When
below can be used as a general-purpose power supply or linear there is little or no feedback signal (such as a short circuit) the
adapter replacement. LinkSwitch goes into auto-restart, limiting output current to
approximately 40 mA.
The design provides regulated output voltage during normal
loads as well as a soft output-current limit during overload Capacitor C3 provides device decoupling. The extra winding
conditions (such as a stalled motor or defective relay). Adding on pin 3 of T1 is a shield that reduces EMI.
to this, the other LinkSwitch self-protection features of auto-
3 LinkSwitch
T1 12 V, 260 mA
D S
+ C3 1 +
C U1 69T
LNK520 1 µF 5
10 V 34 AWG
C4 30T C5
4
0.1 µF 30 AWG 220 µF
R2 25 V
17.8 kΩ 100 V 43T T.I.W.
FILM 35 AWG
DC IN *C2 6
100-375 100 nF
400 V 3
VDC
D3 RTN
1N4937 D4
55T UF4003
38 AWG 1A
200 V
R3 EE13
150 Ω Lp = 2.484 mH
*Optional
Component
PI-3883-070604
Figure 1. DC-Input, Isolated LinkSwitch 3.12 W Flyback Converter.
3-276
Rev. A 07/04
Key Design Points • Output diode D4 needs a sufficient peak inverse voltage
(PIV) rating for high line withstand, requiring an ultra-
• The value of C3 (1 µF) allows time for the output voltage fast 200 V type (UF4003). For lower output voltages
to develop at startup. (PIV <100 V), Schottky diodes work well and enable
• A larger R3 value will provide flatter voltage regulation if improved efficiency.
a higher no-load voltage can be tolerated. • The LinkSwitch PIXls spreadsheet tool included in
• A lower R2 value will reduce the output voltage while PI Expert™ Design Software can be used to redesign the
proportionally increasing the maximum output current. transformer for different output voltages.
20
PI-3884-070104
18
TDK PC40 EE13,
16 Core Material
ALG = 199 nH/T2
14
Bobbin EE13 Horizontal 8-pin
Voltage (V)
12
10 Shield 1: 55 T, #38 AWG,
MIN 1 Layer
8 MAX
105 VDC
Primary-1: 69 T, #34 AWG,
6 150 VDC 2 Layers
Winding Details
4 315 VDC
370 VDC
Primary-2: 43 T, #35 AWG,
2 1 Layer
0
Secondary: 30 T, #30 T.I.W.,
0 100 200 300 400 2 Layers
Load (mA) Shield 1: (3-Float), Primary-1
Winding Order
Figure 2. Output Regulation vs. Load Current Curves. (1-4), Primary-2 (4-3),
(pin numbers)
Secondary (6-5)
Primary
2484 µH ±10%
PI-3885-070104
Inductance
80 Primary Resonant
500 kHz (minimum)
Frequency
Efficiency (%)
70
105 VDC
Leakage
Inductance
70 µH (maximum) 3
150 VDC
60 315 VDC
370 VDC
50
40
0 50 100 150 200 250 300
Load (mA)
Figure 3. Efficiency vs. Output Current Curves.
3-277
Rev. A 07/04
DI-89
Design Idea DI-80
®
LinkSwitch-TN
0.6 W Non-isolated Utility Meter Power Supply

Utility Meter LNK302 0.6 W 85-265 VAC, 47-63 Hz 12 V, 50 mA Buck
Design Highlights required holdup time to write the meter reading to non-volatile
memory after a power outage.
• Universal AC input voltage range
• Meets EN62053-21:2003 (<1 W real and <5 VA apparent LinkSwitch-TN uses on/off control to regulate the output voltage.
input power at 265 VAC) When the current into the FEEDBACK (FB) pin exceeds
• Long holdup time (140/580 ms at 115/230 VAC) 49 µA, MOSFET switching is disabled for the next switching
• High efficiency (>60 % at 265 VAC) cycle. The 49 µA threshold is specified at an FB pin voltage of
• Very low no-load consumption (0.15 W at 265 VAC) 1.65 V (±7% over the entire operating temperature range),
• EMI compliant (EN55022B, CISPR-22B) allowing it to be used as a reference.
• Extended line surge withstand with integrated 700 V
MOSFET The power processing stage is formed by the LinkSwitch-TN,
• Small size and light weight freewheeling diode D3, output choke L1, and the output capacitor
• Scalable output power using larger LinkSwitch-TN family C5. To a first order, the forward voltage drops of D3 and D4
members are equal. Therefore, the voltage across C4 tracks the output
voltage. The voltage across C4 is sensed and regulated via the
Operation resistor divider R4 and R3 connected to the LNK302 FB pin.
Using the buck topology, the circuit shown in The values of R3 and R4 are selected such that, at the desired
Figure 1 generates a non-isolated 12 V, 50 mA output. Typical output voltage, the voltage at the FB pin is 1.65 V. Resistor R5
uses include utility meter and industrial and motor control establishes a small 3.6 mA pre-load and is only necessary for
applications. applications where regulation to zero load is required.
3 The AC input is rectified and filtered by D1, D2, C1, C2, RF1, The value of L1 is selected according to the LinkSwitch-TN
R1, and R2. Two rectifiers improve both line surge withstand Design Guide (AN-37) or the PIXIs design spreadsheet (part of
(2 kV) and conducted EMI. Resistor RF1 should be a fusible PI Expert™ power supply design software). Both are available
flameproof type, whereas R1 and R2 can be flameproof only. at www.powerint.com.
In meter applications, capacitors C1 and C2 are sized for the
C3
100 nF R4
R3 11.0 kΩ C4
RF1 R1 1.82 kΩ 1 µF
8.2 Ω 220 Ω 1% D4 12 V,
1% 16 V 1N4005GP
2W 0.5 W FB BP 50 mA
D S L1
D1 1.5 mH
1N4007 LinkSwitch-TN C5
85-265 C1 C2 130 mA R5
VAC 4.7 µF 4.7 µF LNK302 D3 47 µF 3.3 kΩ
D2 400 V 400 V UF4005 16 V
1N4007 RTN
R2 PI-3918-081104
220 Ω
0.5 W
Figure 1. LinkSwitch-TN 0.6 W, 12 V, Universal Input Power Supply Using a Non-Isolated Buck Topology.
3-278
Rev. B 09/04
Key Design Points • Diode D3 should be an ultra-fast type. A reverse recovery

time trr ≤75 ns should be used at an ambient temperature of
• The output is not safety isolated from the input. +70 °C or below. If the ambient temperature is higher, then
• The circuit shown in Figure 1 has a total output a diode with trr ≤35 ns should be used.
voltage tolerance of ±10% (-20 °C to +85 °C ambient • Feedback diode D4 can be a low-cost slow diode such as
temperature). 1N400X series, however it should be specified as a glass
• To prevent noise coupling and to decrease EMI, place the passivated type to guarantee a specified reverse recovery
input filter components physically away from the source time.
node of the LinkSwitch-TN and L1 inductor. • Pre-load R5 is only required for output regulation down to
• The DC input filter capacitors C1 and C2 can be placed as zero load.
a barrier between the AC input and LNK302 and L1. Their • Use LNK304 for up to 110 mA output current (<2 W
size depends on the minimum operating input voltage and true input power and <6 VA apparent input power at
required holdup time. 265 VAC). Select output inductor L1 value and current
• Select ESR of output filter capacitor C5 based on the output rating accordingly.
voltage noise requirement. • See LinkSwitch-TN Design Guide for in-depth
information.
PI-3916-081004 PI-3917-081204
13.0 80 3.0 3.0
70
Apparent Input Power (VA)

2.5 2.5
Real Input Power (W)

12.5 60
Output Voltage (V)
Efficiency (%)
2.0 2.0
50
12.0 40 1.5 1.5
30
1.0 1.0
85 VAC Load Regulation
11.5 265 VAC Load Regulation
20
True Input Power (W)
85 VAC Efficiency 0.5 Apparent Input Power (VA)
0.5
265 VAC Efficiency 10
11.0 0 0.0 0.0

0 10 20 30 40 50 85 115 145 175 205 235 265
Output Current (mA) Input Voltage (VAC)
Figure 2. Output Regulation (left Y-axis) and Efficiency
(right Y-axis) Over Load Current at 85 VAC and
Figure 3. Real Input Power (left Y-axis) and Apparent Input
Power (right Y-axis) AC Input Voltage at 50 mA 3
265 VAC Input. Load Current (0.6 W Load).
3-279
Rev. B 09/04
Design Idea DI-85
®
LinkSwitch-LP
2 W Charger: Replaces Unregulated Linear Solutions

Charger LNK564P 2W 90-265 VAC 6V Flyback
Design Highlights Past the peak power point, cycle skipping ceases and U1
limits the supplyʼs output current by reducing its oscillator
• Low-cost, low parts-count solution: 14-17 components
(MOSFET switching) frequency, as the voltage on the FB pin
• Proprietary IC design and winding techniques enable a
drops. If the load demand causes the FB pin voltage to drop
Clampless™ design with simple Filterfuse™ input stage
below an auto-restart threshold voltage VFB(AR) of 0.8 V (1 V to
• ±5% over-temperature threshold – with hysteretic
1.5 V on the supply output) for more than 100 ms, the IC goes
recovery – keeps PCB temperatures below safety limits
into auto-restart mode. In auto-restart, MOSFET switching is
• Auto-restart: output short circuit and open loop protection
enabled for about 100 ms, approximately every 800 ms, until
• IC creepage distance >3.2 mm: no arcing in high
the FB pin voltage increases above 0.8 V.
humidity
• Easily meets all EPS energy efficiency standards
Due to the frequency jittering of the U1 internal oscillator and
• Meets CISPR-22 Class B EMI with good margin
the E-Shield™ winding techniques used in constructing the
transformer (T1), conducted EMI is adequately attenuated by
Operation the LC filter formed by L1 and C1. Inductor L1 serves as both
This LinkSwitch-LP based flyback converter (Figure 1) provides a differential mode choke and a fuse. This Filterfuse is sleeved
an output VI curve (Figure 2) similar to that of an unregulated with heat-shrink tubing, and its winding wire diameter was
line frequency transformer based supply, but with output selected so that it will open like a fuse if any single component
current that is limited past the maximum rated output power fails shorted. Thanks to the tight current limit tolerance of the
(peak power point). LinkSwitch-LP family and construction techniques used on T1,
the primary winding can be left Clampless, since the peak drain
3 From no-load to the 2 W peak power point, the LNK564P

(U1) regulates the output voltage by skipping switching
voltage does not approach the 700 V drain-to-source breakdown
voltage (BVDSS) of U1.
cycles, based on the current delivered into the FEEDBACK
(FB) pin. At the peak power point, the supply delivers With no optocoupler and such a low parts count, this supply is
>300 mA of load current at >5.7 VDC. cost competitive with the unregulated line frequency transformer
based solution it was designed to replace.
C5 VR1*
D1 RF1* L1 T1 D4 220 µF R3 1N5240B 6 V,
L 1N4937 8.2 Ω 3300 µH EE16 7 UF4002 25 V 2 kΩ 10 V 0.33 A
2
J-1 2.5 W J3-2
C1
90-265 10 µF J3-1
VAC 1 6
400 V
J-2 4 RTN
N
D2
1N4005 5
R1
D3 37.4 kΩ
1N4005 C4*
D C3 100 pF
FB 250 VAC
LinkSwitch-LP 330 nF
U1 BP 50 V
LNK564P C2 R2
S 0.1 µF 3 kΩ
*Optional components
50 V
PI-4106-101105
Figure 1. LNK564 Based 6 V, 330 mA, 2 W, Low-Cost, Flyback Charger Power Supply.
3-280
Rev. B 02/06
PI-4159-092905
140
• The PI Xls spreadsheet calculates all of the parameters
required to specify and build transformer T1. 120
Input Power (mW)

• This design uses one of two “standard” transformers (see
100
AN-39). With this transformer, the output voltage of the
supply can be set between 4 V and 7.5 V by selecting the 80
appropriate value of R1. 60
• Figure 1 contains three optional components: RF1,
VR1 and C4. A fusible resistor must be used if a safety 40
agency disapproves of using L1 as a fusible component. 20
The auto-restart function limits the output power
during open loop operation, so only a 1/2 W VR1 is 0
50 100 150 200 250 300
required if the open loop output voltage is unacceptable.
Y capacitor C4 improves EMI repeatability but is not required AC Input Voltage (VAC)
to meet EMI limits.
Figure 3. No-load Input Power vs. Line Voltage.
• For the IC to limit the supplyʼs output current past the point
of peak power delivery, the voltage on the FB pin must begin
to drop below 1.69 V as the load increases. Therefore, the 80
PI-4160-092905
value of R1 should be selected so the FB pin voltage is
1.69 V at the peak power point. 70
60
Efficiency (%)
10 90 VDC
50
PI-4158-092905
115 VDC
9 230 VDC
90 VDC
40
8 265 VDC
115 VDC
Output Voltage (V)
7 30
230 VDC
6 265 VDC 20
Min Limit
5 Max Limit 10
4
0
3
0.00 0.50 1.00 1.50 2.00 2.50 3.00
3
2
Output Power (W)
1
0 Figure 4. Efficiency vs. Output Power and Line Voltage.
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Average Output Current (A)
Figure 2. Output VI Characteristic Curves vs. Load & Line.
3-281
Rev. B 02/06
Design Idea DI-88
®
DPA-Switch
PoE Detection and Classification (Class 0-3)
Interface Circuit
PoE/VoIP DPA423G 6.49 W 36-57 VDC 3.3 V Flyback
Design Highlights Detection occurs as the input voltages rises from 2.5 to
10 VDC. Resistor R31 within the PD presents the detection
• Simple interface for Power Over Ethernet (PoE) Powered impedance to the PSE.
Devices (PDs)
• Includes PoE detection and classification circuits for all Classification occurs as the input voltages rises from 14.5 to
classes (0, 1, 2 and 3) 20.5 VDC. The sending device determines the class of the PD
• Compliance to IEEE802.3af PoE standards verified by by monitoring the amount of current drawn by the PD during
University of New Hampshire Interopability Consortium this phase. For classes 1, 2 and 3, the classification current (ICL),
(UNH-IOC)* is programmed by resistor R34, as per the table.
• Includes under voltage lockout (42 VDC on, 34 VDC off)
POUT POUT ICL ICL
Class R34
PoE Detection and Classification (min) (max) (min) (max)
PoE is becoming widely adopted for networking and VoIP W W mA mA Ohms
telecom applications. A typical PD solution is shown in 0 0.44 12.95 0.5 4 -
Figure 1 and has a PoE interface circuit and a DPA-Switch DC-
DC converter block (see EPR-68 for full details of operation 1 0.44 3.84 9 12 133
of the DC-DC converter). 2 3.84 6.49 17 20 69.8
3 6.49 12.95 26 30 45.3
The PoE specification requires the PD to implement
three functions: detection, classification and pass-switch Components R32, R33, R34, R35, Q31, Q32, Q33, Q34, VR31
3 connection. and U31 are not installed for Class 0 applications, and the
classification current is programmed by R31 (24.9 k).
C4
1000 pF R7
1500 V 10 kΩ
Ethernet L1
(RJ-45) C7 C8 C10
PoE Interface 10 µH D1 330 µF L2 J2-1
Connector D101 SL42 330 µF 1 µF
1A 6V 6V 1 µH, 2 A 10 V 3.3 V, 2 A
1 9,10
(1,2)
+
DL4002 C9
330 µF
R5 6V
D102 R31 2 6,7
VR31 R36 R4 649 kΩ
24.9 kΩ 11 V 51 kΩ 1% J2-2
1% 1 MΩ VR3 RTN
1% 4
SMAJ
R32 150A
D103 100 kΩ 3 D2 C11
(4,5) BAV21 1 µF R11
50 V
MMBTAO6L
DL4002 5 1 kΩ
Q32 R10
C1 C2 R12
1.5 µF 1.5 µF 75 Ω
D104 34 kΩ
100 V 100 V R23 R21 1%
MMBTAO6L
10 kΩ
DPA-Switch 174 kΩ U2
VR32 U1 1%
Q20 PC357
D105 Q31 R33 27 V D L DPA423G N1TA
MMBTS
MMST3904 MMBTAO6L
2 kΩ R22
(3,6) 1% CONTROL 3906
C 10 kΩ
DL4002
R37 C13
220 kΩ 0.1 µF
D106 Q33 R35
S X F
R9
C5 51 Ω
LMV431A1M
100 kΩ
U31 0.1 µF U3
1% CAT431L
D107 Q34
(7,8) R34 R6 C6 R13
69.8 Ω VR33 8.66 kΩ 22 µF C12 20.0 kΩ
DL4002 15 V 0.33 µF
1% 1% 10 V 1%
D108 Q35 PI-4042-032706
100 V
Mandatory CAT-5 0.250 mΩ
Blocking Diodes
Figure 1. PoE Interface Circuit – Class 2.
*UNH-IOC test reports are available on the PI website www.powerint.com/poe
3-282
Rev. C 11/05
Operation • The bias current source (Q31) is used to allow the

classification current source to be turned-off for minimal
Resistor R31 provides the detection impedance. In order to allow power loss once input voltage exceeds 28 VDC. This limits
correct operation over the detection voltage range, Zener diode the dissipation of the classification circuit to approximately
VR31 inhibits the classification circuit at input voltages below 20 mW at high input line (57 VDC) plus detection resistor
11 V. Components Q32, Q31 and R32 form a 350 µA bias current
source programmed by resistor R33 working in conjunction
with the base-emitter voltage of Q31. Transistor Q33 forms 14
PI-4044-111005
the classification current source programmed by resistor R34 Class 1
working in conjunction with the 1.24 V voltage reference U31.
Transistor Q34 disables the classification current source when
Zener diode VR32 conducts (when the input voltage exceeds Class 1 Max
12
Current (mA)
approximately 28 V). Classification
Voltage Range
Key Design Points

10
• For Class 0, remove components VR31, R32, R33, R34,
R35, Q31, Q32, Q33, Q34 and U31.
• R34 values: Class 1, R34 = 133 Ω; Class 2, R34 = 68.9 Ω; Class 1 Min
Class 3, R34 = 45.3 Ω. 8

• It is possible to use either bipolar transistor or MOSFET 10 12 14 16 18 20 22
pass-switches (Q35). A bipolar transistor is less expensive,
Voltage (V)
but a MOSFET gives higher pass-switch efficiency. See
design idea (DI-70) for details. Figure 3. Classification Current (Class 1:
R34 = 133 Ω).
0.80
PI-4045-111005
PI-4043-080905
Class 2
Class 1 Class 3
Class 2 Class 3 Max
Class 3 30
0.60 Detect Min Classification
Voltage
Current (mA)
Detect Max
Current (mA)
23.75 kΩ Range
26
Class 3 Min
Detection
0.40 Voltage
Range
22
3
Class 2 Max
0.20
26.5 kΩ 18
Class 2 Min
0.00 14
0 2 4 6 8 10 12 10 12 14 16 18 20 22
Voltage (V) Voltage (V)
Figure 2. Detection Impedance V-I Curve. Figure 4. Classification Current (Classes 2 & 3:
R34 = 69.8 Ω and R34 = 45.3 Ω).
3-283
Rev. C 11/05
Design Idea DI-89
®
LinkSwitch
Low Cost 2 W CV Power Adapter

Adapter LNK362P 2W 85-265 VAC 6.2 V Flyback
Design Highlights dampens the ringing of the filter. Switching frequency jitter and
PIʼs E-Shield™ transformer construction technology enable this
• Low-cost, low parts-count CV solution: 20 components design to meet EN55022 Class-B conducted EMI with good
• Proprietary IC design and winding techniques enable a margin (see Figure 4). Y capacitor C4 (optional) can improve
Clampless™ drain-node the unit-to-unit repeatability of EMI scans.
• ± 5% over-temperature threshold – with hysteretic
recovery – keeps PCB temperatures below safety limits This supply also takes advantage of PIʼs Clampless transformer
• Auto-restart: output short circuit and open loop protection techniques, which uses T1ʼs primary winding capacitance to
• IC creepage > 3.2 mm: no arcing in humid environments clamp the voltage spike that its leakage inductance causes, each
• Easily meets all EPS energy efficiency standards time the MOSFET in U1 turns off. Therefore, this converter has
• Meets CISPR-22 Class B EMI with sufficient margin no primary clamp components connected to the drain-node.
Operation From no-load until maximum output power (2 W) is delivered,

This LinkSwitch-XT based flyback converter (Figure 1) provides the LNK362P (U1) regulates the output voltage by skipping
2 W of tightly regulated constant voltage (CV) output power, switching cycles, based on the current delivered into the
while meeting the active-mode efficiency and no-load power feedback (FB) pin. If the output is over loaded and no feedback
consumption requirements of all harmonized energy efficiency (< 49 µA) is received within a 40 ms period, U1 goes into auto-
(EPA, CEC) standards (see Figure 2 and Figure 3). restart mode. In auto-restart, MOSFET switching is enabled
for about 40 ms approximately every 800 ms if no feedback
Diodes D1– D4 rectify the AC input. The resulting DC is is received within the 40 ms window of enabled switching.
filtered by bulk storage capacitors C1 and C2. Components L1,
3 L2, C1 and C2 form a conducted EMI noise filter. Resistor R1
C4*
100 pF
250 VAC
C5
L1 T1 330 µF 6.2 V,
1 mH EE16 9 16 V 322 mA
4
5 J3-1
D5
1N4934
3 8
NC NC J3-2
RF1 D1 D2 R1 VR1
8.2 k 1N4005 1N4005 3.9 k BZX79-
J1 2.5 W 1/8 W B5V1
5.1 V, 2%
R3
390 Ω
85-265 C1 C2 1/8 W
400 V 400 V
R2
1k
J2 U2 1/8 W
D PC817A
LinkSwitch-XT FB
U1 BP
LNK362P
S
*Optional component
D3 D4 C3
1N4005 1N4005 L2 100 nF
1 mH 50 V
PI-4205-110805
Figure 1. LNK362 Based 6.2 V, 322 mA, 2 W, Low-Cost, Flyback CV Output Power Adapter.
3-284
Rev. A 11/05
PI-4236-110805
• The PI Xls spreadsheet calculates all of the parameters 66
required to specify and build transformer T1.
64
• The power transformer must have a two layer primary
Efficiency (%)
winding to ensure that its intra-winding capacitance is 62
sufficient for Clampless operation.
• The reflected output voltage (VOR) of this design was kept 60 85 VAC
< 90 V (74 V) for Clampless operation. 115 VAC
• Since this supply has a Clampless drain node, it must be 58 230 VAC
265 VAC
verified that the maximum drain voltage does not exceed EPA Std
56
650 V when the flyback voltage spike occurs.
• The primary current ripple-to-peak ratio (KP) factor should 54
be > 1 (ensures discontinuous conduction mode operation) 0 0.5 1 1.5 2 2.5
to minimize conducted EMI.
Output Power (W)
• The maximum operating flux density (BM) was kept
< 1500 Gauss to eliminate audible. Figure 3. Harmonized (EPA, CEC) Active-Mode Efficiency vs.
Output Power (25, 50, 75 & 100%).
0.12 PI-4235-110805 80
PI-4237-110805
70
0.1
60
Amplitude (dBµV)
Input Power (W)
0.08 50
40
0.06 30
20
0.04
-10
0.02 0
-10
0
0 50 100 150 200 250 300 -20
0.15 1 10 30
3
Input Voltage (VAC)
Frequency (MHz)
Figure 2. No-load Input Power Consumption vs. Input Voltage. Figure 4. Conducted EMI Scan to EN55022B Limits: Full-Load,
115 VAC, 60 Hz Input, with Artificial Hand.
3-285
Rev. A 11/05
DI-89
Design Idea DI-91
®
TinySwitch-III
12 W Universal Input CV Adapter

General Purpose TNY278P 12 W 85-265 VAC 12 V Flyback
Design Highlights The use of an E-shield™ in the transformer, a low-noise drain-

node clamp (R2, C4 and D5), a single Y capacitor (C5) and the
• No-load consumption <50 mW at 265 VAC (R8 fitted) deviceʼs switching frequency jitter function enable a low-cost
• Active mode efficiency >75% (CEC standard: ≥71%) pi (π) filter (C1, L1 and C2) to attenuate conducted EMI enough
• BP/M pin capacitor value selects MOSFET current limit to provide more than 10 dB of margin to EN550022 requirements
(ILIMIT–1, ILIMIT, or ILIMIT+1): for design flexibility (see Figure 4). The clamp circuit Zener (VR1) only conducts
• Output OVP function senses overvoltage on the output briefly during startup and at worst-case overload, just before
through the primary bias winding the auto-restart function is activated.
• Accurate (±5%), auto-recovering, hysteretic thermal
shutdown function maintains safe PCB temperatures Although TinySwitch-III family members do not need a bias
• Auto-restart function protects against output short circuits winding to operate, one was used in this design to take advantage
and open feedback loops of the ICʼs output OVP detection function. If an open loop fault
• > 3.2 mm package pin creepage: reliable operation in causes an overvoltage on the output, VR2 will conduct. When
high humidity and high pollution environments the current into the BP/M pin exceeds 5.5 mA, an internal latch
triggers and disables MOSFET switching (see Figure 3), until
Operation AC power is removed and reapplied (to reset the latch). Resistor
This universal input, 12 V, 1 A, flyback converter was designed R3 limits the current through VR2, while R3 and R7 attenuate
around a member of the TinySwitch-III IC family, the TNY278P. the portion of the leakage inductance spike that appears in the
Because of the many features integrated into the device family, bias winding.
the supply only requires 31 through-hole components (no SMT), C5
3
2.2 nF
which enables a simple, single-sided PCB layout to be used. 250 VAC
L2
D7 Ferrite Bead
VR1 BYV28-200
P6KE150A T1 3.5 × 7.6 mm +12 V, 1 A
NC 8
C10 C11 J3
D1 D2 R2 1000 µF 100 µF
1N4007 1N4007 100 Ω 1 6 25 V 25 V J4
F1
J1 3.15 A C4 RTN
C1 C2 R1
6.8 µF 22 µF 1 kΩ 10 nF
1 kV 3 R7
400 V 400 V
85-265 RV1 4 20 Ω
VAC 275 VAC
D5
1N4007GP 2 D6
R5* UF4003
J2 3.6 MΩ
D3 D4 5
1N4007 1N4007
L1 VR2
1 mH 1N5255B C6 VR3
28 V 1 µF BZX79-C11
60 V 11 V
R3
47 Ω
*R5 and R8 are optional 1/8 W R6
components 390 Ω
R8* 1/8 W
† 21 kΩ
C7 is configurable to adjust 1% U2
D PC817A
U1 current limit, see circuit EN/UV
description
BP/M
S
S R4
TinySwitch-III C7 † 2 kΩ
U1 100 nF 1/8 W
TNY278P 50 V
PI-4244-021406
Figure 1. TinySwitch-III 12 W, Universal Input, CV Adapter.
3-286
Rev. A 01/06
88
When R8 (optional) is installed, it supplies current to the BP/M
PI-4274-013106
86
pin, which reduces the no-load consumption of the supply. When 84
R5 (also optional) is installed, the current it feeds into the EN/UV 82
Efficiency (%)
pin of the IC enables the input under-voltage lockout function 80
(UVLO), and sets the start-up threshold at 65 VAC. 78 TNY279 (with ILIMIT-1)
TNY278 (with std ILIMIT)
76 TNY277 (with ILIMIT+1)
CEC/ENERGY STAR Minimum
The output voltage is determined by the series sum of the 74 TNY278 (with ILIMIT+1)
voltages across VR3, R6, and the LED in U2. The values of 72
70
R4 and R6 can be adjusted to fine tune the output voltage of the
68
supply, and a TL431 can be used in place of VR3, for tighter 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5
output voltage regulation. Output Current (A)
Figure 2. Operating Efficiency vs. ILIMIT+, ILIMIT- and Device Size.

Key Design Points
• In the TinySwitch-III family of devices, the MOSFET
PI-4288-012506
current limit can be selected from 3 levels by the value
of capacitance on the BP/M pin. This gives the designer a
15
number of options, which are shown in Figure 2. First, a
Voltage (V)
TNY279 could be used, with the current limit of a TNY278,
to obtain higher efficiency. Second, a TNY277 could be
used, with the current limit of a TNY278, to deliver the
same power at a lower efficiency. Lastly, a TNY278 could 0
be used, with the current limit of a TNY279, to extend the

power capability of the supply*. 0 250 500
• The UVLO function integrated into U1 only enables Time (ms)
MOSFET switching to occur once the current flowing Figure 3. BP/M Pin OVP Function Shuts Down Power Supply.
into the EN/UV pin exceeds 25 µA. Changing the UVLO
threshold voltage requires changing the value of R5 so that 80
PI-4289-012506
25 µA flows through it at the desired threshold voltage. 70
• If output OVP is not required and no-load power consumption 60

of 150 mW (max, at 265 VAC input) is acceptable, then R7,
Amplitude (dBµV)
50
D6, C6, R3 and VR2 can be eliminated and the bias winding 40
removed from T1, for an even lower parts count. 30
3
20
*Note: This supply was not thermally designed to continuously
-10
deliver the extended power range that could be obtained by
0
operating a TNY278 with its MOSFET current limit set at that
of a TNY279. -10
-20
0.15 1 10 30
Frequency (MHz)
Figure 4. Conducted EMI Scan (Line): 115 VAC, Full Load.
3-287
Rev. A 01/06
Design Idea DI-92
®
LinkSwitch-TN
0.5 W Non-isolated Constant Current LED Driver
Application Device Power Output Input Voltage Output Current Topology

LED Driver LNK302P 0.5 W 85-265 VAC 40 mA Buck-Boost
Design Highlights application, the device will switch and ramp up to the current
limit for each and every cycle.
• Extremely low component count – only 9 components
required
Since the peak current is limited and fixed for each cycle, the
• Universal AC input range – single design worldwide
output power is solely determined by the size of the inductor.
• Low cost, small size and very lightweight
It is recommended that this design operate in the discontinuous
• Replacement for passive capacitor or resistor droppers
conduction mode (DCM). Besides better EMI performance, this
• High efficiency (approximately 70% at 85 VAC)
also ensures that a low cost 75 ns reverse recovery diode such as
• Meets EN55022 B EMI limits with >8 dB margin (see
the UF4005 can be used. For designs that operate in the continuous
Figure 2)
conduction mode (CCM), a more expensive but faster diode (30
ns reverse recovery) like the BYV26C may be required.
Operation
Figure 1 shows a simple buck-boost converter, operating in The output will be replenished every switching cycle (66 kHz),
open loop with no output feedback, being used as a constant and thus the need for the output filter capacitor is eliminated.
current LED driver. The circuit relies on the internal current Persistence of vision of the human eye (typically 10 ms) is much
limiting function of the LNK302, which ensures constant current longer than the switching period, and it thus sees a consistent
is supplied to the load. Typical uses include night-lights, neon light output without flicker.
sign replacements, emergency exit signs or any application
utilizing LEDs for lighting. Select the value of L1 following the LinkSwitch-TN Design
Guide (www.powerint.com/appnotes.htm), or using the PI Xls
design spreadsheet (www.powerint.com/designsoftware.htm).
3 The AC input is rectified and filtered by D1, C1, C2, and RF2.
For safety, resistor RF1 should be a fusible flameproof type, Enter the output voltage as the voltage of the LED string, and the
whereas RF2 can be flameproof only. output current as the total combined LED current. Alternately,
one can calculate the inductance using
LinkSwitch-TN uses current limited ON/OFF control to regulate
the output current. This type of control inherently rejects
any input voltage variations over the entire operating range.
Current greater than 49 µA into the FEEDBACK pin disables
the MOSFET for that switching cycle. Since there is never
any current being fed back into the FEEDBACK pin in this
C3 LED 1-12
D1 RF2 D3 13 mA per string
1N4007 47 Ω FB BP 0.1 uF UF4005
50 V (average)
D S
RF1
8.2 Ω, 1 W LinkSwitch-TN
Fusible U1
LNK302P
C1 C2
85-265 2.2 uF 2.2 uF L1
VAC 400 V 400 V 1 mH
PI-4087-082605
Figure 1. A 0.5 W, 12.9 V, 40 mA Constant Current LED Driver, Using a Non-Isolated Buck-Boost Topology.
3-288
Rev. B 09/05
Key Design Points • The maximum number of LED strings determines the total
output current and is limited by the current limit of the
• The circuit shown in Figure 1 has a total output current LNK302 device and the inductance of L2.
tolerance of ±12% (including ∆T of 50 °C).
• To prevent noise coupling to the input, place the input filter 80
PI-4088-081205
components physically away from the source node of the 70
LinkSwitch-TN and L1 inductor. The DC input filter capacitors QP
C1 and C2 can be placed as a barrier between the AC input 60
and these two components. AV
50
• The circuit shown in Figure 1 uses a low cost resistive
40
pi (π) filter for differential mode filtering. For output power
dBµV
greater than 0.5 W, an inductive pi filter is recommended. 30
• For better EMI performance, operate the circuit strictly in 20
DCM (see Figure 3 – output current decays to zero in every
10
switching cycle).
• A second rectifier diode may be placed in the return leg of 0
the AC input (not used in Figure 1). This may give improved -10
EMI performance and better surge withstand capability.
-20
0.15 1.0 10.0 100.0
MHz
Figure 2. Conducted EMI Plot of the Schematic Shown in
Figure 1 – Background Scans Taken at 110 VAC:
Foreground Scans Taken at 230 VAC.
PI-4089-082605
Current (mA)
0 mA
0 mA
0 5 10 15 20 25 30 35 40 45 50
Time (µs)
Populated Circuit Board. Figure 3. Output Current (Top Trace) and Input Current
(Bottom Trace), 50 mA/div, 5 µs/div.
3-289
Rev. B 09/05
Design Idea DI-93
®
PeakSwitch
General Purpose 32 W Continuous (81 W Peak) Supply

Inkjet Printer PKS606Y 32 W / 81 W pk 90-265 VAC 30 V Flyback
Design Highlights PeakSwitch has three functions that interact with each other:
auto-restart, conditional latching shutdown and smart AC line
• Delivers up to 2.5 times the full load power for 50 ms sense. Components D5, C7, R5 and R6 enable the smart AC
• Uses a small EE25 core transformer line sense and the under-voltage lockout (UVLO) functions.
• Meets EPS active-mode efficiency specifications When U1 does not skip any switching cycles for >30 ms, the
• No-load input power <200 mW at 265 VAC auto-restart function activates. If AC line voltage is absent or
• High standby and sleep mode efficiency: > 66% and 75% insufficient for normal operation when auto-restart activates,
latching shutdown is disabled, and normal operation will
Operation resume after the AC line voltage is restored. If AC line voltage
is sufficient for normal operation when auto-restart activates,
This supply is configured as a flyback converter. The ON/OFF latching shutdown is enabled, and AC power must be removed
controller integrated within the PeakSwitch IC (U1) has an and reapplied to reset the latch. The low value of C7 enables
internal oscillator frequency of 277 kHz. Feedback from the latch reset to occur quickly, once AC is removed. F
output causes the controller to skip MOSFET switching cycles
to regulate the output voltage. The skipping of switching The smart AC line sense components also enable the UVLO
cycles adjusts the converter s effective switching frequency function. UVLO inhibits MOSFET switching until current
(FSW_EFF) to meet the demands of the load. When delivering into the EN/UV pin is >25 µA. Resistor R16 supplies the
32 W continuously, the FSW_EFF is near 90 kHz. When the load 1 µA threshold current that activates the UVLO and AC sense
demands peak power from the supply, the controller skips fewer features, keeping those functions activated during brownouts
switching cycles, raising the FSW_EFF. This enables the supply and line sags.
to deliver peak power pulses of up to 81 W (for up to 50 ms),
C10 R8
while keeping the output voltage in regulation.
3
1 nF 68 Ω C11
250 VAC 1/2 W 330 pF
C13 R9 C14 30 V @
D9 47 µF 0.33 Ω L2 220 nF 1.07 A Cont.
1N4148 16 V 2W 5.3 µH 50 V 2.7 A Peak
C17 C5 VR1 9,10 D8

4.7 nF 2.2 nF 1N4764A Q1
STPS3150 C12
1 kV 1 kV 100 V 2N3906
330 µF R10
1 50 V VR2
C4 R11 1.5 kΩ
D1-D4 1N5255B
1N4007 150 µF 3 kΩ
7,8 28 V
400 V
R3
10 kΩ RTN
R15 1/2 W 3
2.2 Ω
4
D10
R4 UF4003 VR3
C15
22 Ω C6 R12 1N5258B
2 100 nF
1/2 W 47 µF 1 kΩ 36 V
L1 50 V
5.3 mH 35 V R7
D6 4.7 kΩ
5 Q2
FR106
R2 R1 FS202DA
1.3 MΩ 1.3 MΩ D7
T1
D5 R5 R6 EE25 1N4148
1N4007 2.2 MΩ 2.4 MΩ
C3 R16
680 nF t
O
2.7 MΩ C16
X1 RT1 100 nF
PeakSwitch
10 Ω D
U1 EN/UV
PKS606Y R14
BP 100 Ω
C7
C1-C2 C8 U2 R13
F1 100 nF
3.15 A 400 V
250 VAC 50 V
J1
L J3
PE
PI-4170-060706
N
Figure 1. 32 W (Continuous), 81 W (Peak) Power Supply Using PKS606Y.
3-290
Rev. C 06/06
Ten components enable load overvoltage and over-current – If the load pulls peak current for longer than the RC time
protection: C13, C16, D10, Q1, Q2, R9, R10, R11, R14 and VR3. constant (≈ 60 ms) of C13 and R10, Q1 turns on, which turns
They work with the latching shutdown function as follows: Q2 on and shorts the secondary winding of T1. Again, after
30 ms of U1 receiving no feedback, the supply latches off.
– If the supply output voltage goes above 36 V, VR3 conducts
and turns on Q2, which shorts the secondary winding of Capacitor C17 attenuates differential-mode conducted EMI.
T1. After 30 ms of U1 receiving no feedback, the supply Resistor R15 dampens high frequency ringing.
latches off.
Key Design Points
90
• The value of C7 sets the reset time of the latched shutdown
PI-4311-021506
80
function, once the AC input is removed. Verify that the
70
latch resets, within the time allowed, at the highest input
voltage.
Efficiency (%)
60
50 • For thermal considerations, the PeakSwitch IC, the output

40 diode and their heatsinks, and the transformer core size
30
depend on the continuous-to-peak power ratio, and the
115 VAC Input
duration and frequency of the peak power pulses.
20
230 VAC Input • Choose the values for R10 and C13 so that normal peak
10 loads will not turn Q1 on. However, do not set the RC time
0 constant so long that the supply does not latch off within
0 5 10 15 20 25 30 35 the 60 seconds specified by IEC 60950-1, section 2.5, Table
Output Power (W) 2B (Limited Power Sources requirements).
Figure 2. Active-Mode Efficiency Performance.
80
PI-4335-031406
2.50
70
PI-4336-031506
2.25
Available Output Power (W)
60
2.00
1.75 50
1.50 40
= 1 W Input Power
dBµV
1.25 = 3 W Input Power 30

1.00
.75
20 3
10
.50
.25 0
.00 -10
80 100 120 140 160 180 200 220 240 260 280
-20
AC Input Voltage 0.15 1.0 10.0 -100.0
Figure 3. Available Output Power at 1 W and 3 W Input Power. MHz
Figure 4. Conducted EMI to EN55022 B Limit, at Full Load,
with 115 VAC, 60 Hz Input Voltage.
3-291
Rev. C 06/06
APPLICATION NOTE
Design Idea DI-116
®
TinySwitch-III
28 W Multiple Output Supply with <50 mW
No-Load Consumption
DVD / Set-top Box TNY280P 25 W (28 W pk) 90-265 VAC 5 V / 12 V / -12 V / -24 V Flyback
Design Highlights The internal MOSFET in U1 conducts current through the

primary winding of T1 during each enabled switching cycle.
• Simple, low cost, low parts count solution When the primary current reaches the MOSFET current limit, it
• Low input power at no-load: <50 mW at 265 VAC turns off and the energy in T1 is transferred to the secondary.
• Low standby power consumption: <90 mW input with
5 V, 5 mA load The primary clamp (D5, VR3, R1, R2 and C3) limits the
• High efficiency: >74% at 90 VAC maximum peak drain voltage below the 700 V breakdown
• >10 dBµV EMI margin to EN55022B conducted EMI voltage of the internal MOSFET.
limits, even with output connected to safety earth ground
• Simple output overvoltage latching shutdown circuit Output overvoltage protection (OVP) is provided by U2, R12,
protects load under fault conditions R13, VR1 and VR2. If the feedback loop were to open circuit
• On-time extension provides 28 ms hold-up time due to a failure of U3, VR1 or VR2 would turn on U2 causing
the current into the BP/M pins of U1 to exceed 6.5 mA, and U1
Operation to latch off. The values of VR1 and VR2 determine the output
The DVD or set top box supply shown in Figure 1 was designed voltage at which this occurs. Once triggered, cycling the AC
as a Flyback converter using a TNY280P device (U1). In this power resets the OVP latch.
circuit, the 10 µF value of C4 selects the increased current F
limit level of U1, which allows the supply to deliver up to To reduce no-load input power and increase light-load efficiency,
28 W of peak power during startup or load transients (opening resistor R3 feeds the supply current for U1 from the auxiliary
the DVD tray). bias winding on the transformer.
3 C18
1 nF
250 VAC
C6
330 pF R3
100 V 16 Ω
VR4
VR3 C3 C7 C8 BZX79- VR1
BZY97C200 1 nF L2 220 µF B8V2 1N5244B
D7 SB360 680 µF 3.3 µH
200 V 1 kV T1 8 16 V 16 V 8.2 V 14 V +12 V,
2
C9 1.15 A
R4 L3 C11
1 nF 10 Ω 220 µF
D1 D2 50 V 3.3 µH
1N4937 1N4937 3 6 10 V +5 V,
R2 NC 2.1 A
R1 C12 C10 C13 VR2
200 Ω D8 BZX79-B4V7
560 Ω 2.2 µF SB530 2200 µF 100 nF
1/2 W 50 V 10 V 50 V 4.7 V 2%
7 RTN
D9 R11
D5 R6 10 Ω
BAV20 10 Ω
F1 FR107 10 -12 V,
2A L1
10 mH 20 mA
D10 C14 R8 C15 R12
BAV20 2.2 µF 56 Ω 100 nF 100 Ω
9 50 V 50 V -24 V,
90-265 RV1 C1 C2 15 mA
VAC 275 VAC 47 µF 47 µF 4 R7
400V 400V
C5 10 Ω
D6 R13
BAV21 1 µF R9 1 kΩ
100 V U3-A U2-A
5 1 kΩ
TinySwitch-III
U1 EE25 R14 R15
TNY280P 15 kΩ 115 kΩ
C16 1% 1%
220 nF C18
D U2-B
EN/UV 50 V 100 nF
PC817D
C17 50 V
D3 D4 BP/M
1N4007GP 1N4007GP 1 µF
R3 50 V RTN
S
C4 U3-B 100 kΩ
10 µF PC817D U4 R10 R16
50 V TL431 3 kΩ 10 kΩ
2% 1%
PI-4416-090606
Figure 1. 25 W, 28 W pk Multiple Output Supply Using TNY280P.
3-292
Rev. A 09/06
Key Design Points • Select the value of VR1 and VR2 to limit the maximum
voltage during an open loop fault. Resistor R13 provides
• The primary clamp of D5, R1, VR3, R2 and C3 is an
a bias current so that the Zeners are operated closer to their
optimized RCD clamp. During full load, VR3 limits the
test current. This bias current also acts as a pre-load.
maximum voltage across C3. At light-load or no-load, as
• For improved cross-regulation, feedback for the power
the effective switching frequency is reduced, VR3 prevents
supply is provided from both the 5 V and 12 V output into
C3 from discharging completely. This prevents the clamp
the voltage reference U4 via R14 and R15.
network from appearing as a significant load. The use of a
fast instead of an ultra-fast diode for D5 improves efficiency
by recycling some of the leakage energy to the output.
EE25, N67 or equivalent, gap
80 Core Material
PI-4413-090606
EN55022B Limits for ALG of 105 nH/T2
70
5+5 pin vertical (Yih-Hwa YW-
60
QP Bobbin
360-02B)
AV
50 Bias: 27T, 29 AWG
40 Primary: 105T, 32 AWG
Shield: 2T, 100 mm × 9 mm ×
dBµV
30 QP 1 mil Cu foil
Winding Details
20 +5 V: 5T, 2 × 24 AWG T.I.W.
10 AV
+12 V: 6T, 25 AWG T.I.W.
-12 V: 11T, 32 AWG T.I.W.
0 -24 V: 11 T, 32 AWG T.I.W.
-10 1 mm tape margin, bias (4-
-20 5), tape, primary (3-2), shield
Winding Order
0.15 1.0 10.0 100.0 (2-NC), tape, +5 V (6-7), +12 V
(pin numbers)
MHz (8-6), tape, -12 V (7-10), -24 V
Figure 2. Worst-Case Conducted EMI Results (Output Earth (10-9), tape
Grounded). Primary: 1.15 mH - 0/+10%
Inductance
Leakage: 70 µH (max)
3
3-293
Rev. A 09/06
APPLICATION NOTE
Design Idea DI-117
®
TinySwitch-III
15 W, 12 V Adapter with <100 mW No-load Consumption

Adapters / General Purpose TNY279P 15 W 90-265 VAC 12 V Flyback
Design Highlights The internal MOSFET in U1 conducts current through the primary
winding of T1 during each enabled switching cycle. When the
• Simple, low cost, low parts count solution primary current reaches the MOSFET current limit, the controller
• Low input power at no-load: <100 mW at 265 VAC turns it off, and the energy in T1 is transferred to the output.
• High efficiency >81% at 90 VAC Schottky diode D7 and capacitor C8 rectify and filter the output.
• Meets CEC requirements for active mode efficiency Inductors L3 and capacitor C9 attenuate the switching ripple on
(79 % vs. 73.5 % requirement) the output. Capacitor C3 selects the standard current limit of
• >10 dBµV margin to EN55022B conducted EMI limits U1. For higher efficiency, the next larger (TNY280P) device
• Simple, primary-side output overvoltage latching shut- may be used. In this case, the value of C3 would be changed to
down protects load under fault conditions 1 µF, selecting the reduced current limit for the larger device,
• Low line frequency leakage current <10 µA but no other circuit changes would be required.
Operation The primary clamp (D5, R1, C5, R5 and R6) limits the maximum
The TNY279 (U1) in the 8-pin DIP package selected for the peak drain voltage below the 700 V breakdown voltage of U1's
flyback design in Figure 1 is ideal for adapter applications. internal MOSFET. Resistor R1 dampens the high-frequency
The arrangement of the four SOURCE pins on one side of ringing of the T1 leakage inductance.
the package allows a small metal heatsink to be inserted. This
allows the device to operate in a sealed adapter with an external The built-in frequency jitter and E-ShieldTM techniques allow
ambient of 40 °C. simple EMI filtering to comply with EN55022B. Resistor R2
and C4 form an RC snubber to reduce high-frequency EMI.
3 C6
68 pF
250 VAC
C11
1 nF R7
100 V 20 Ω
C5 L3
L4 1 nF R5 R6 Ferrite Bead
1 mH 1 kV 240 kΩ 240 kΩ T1 3.5 × 7.6 mm +12 V, 1.25 A
1 10
C8 C9
D7 680 µF 220 µF
D1 D2 SB580
1N4005GP 1N4005 3 9 25 V 25 V
F1 NC
3.15 A 5 RTN
C1 C2
10 µF 22 µF R1 D6
400 V 400 V 100 Ω 1N4148
90-265 4
VAC
D5 EF20 C7 R8
FR107 1 µF 56 Ω
50 V
D3 D4 VR3
1N4005GP 1N4005 BZX79-B6V8
L5 6.8 V
3.3 µH
R4 R9
U2-B 1 kΩ
47 Ω
TinySwitch-III R11
U1 39 kΩ
TNY279P R3 1%
10 kΩ
D
EN/UV
R2 C10 R10
BP/M
100 Ω S 220 nF 3 kΩ
S 50 V
C3 U2-A U3
C4 LM431
33 pF 100 nF PC817A R12
1 kV 50 V 10 kΩ
1%
PI-4417-051106
Figure 1. 15 W, 12 V Output Supply Using TNY279P.
3-294
Rev. A 09/06
Output overvoltage protection (OVP) is provided on the primary Key Design Points
side by sensing the voltage of the auxiliary transformer winding.
Should the main feedback loop open due to failure of U2, then U1 • Verify maximum drain voltage is <650 V at high line,
will latch off once the current into the BP/M pin (via VR3) exceeds maximum overload. Adjust values of R5, R6 and C5
6.5 mA. Diode D6 and capacitor C7 rectify and smooth the accordingly. However, avoid making the clamp too
output of the auxiliary winding. The value of VR3 is selected dissipative (low value of R5 and R6, and high value of C5)
to trigger the OVP latch when the main output, and hence the as this will increase no-load consumption.
auxiliary output voltage, rises above the normal regulation range. • To prevent an increase in no-load consumption or false
Once triggered, cycling the AC power resets the OVP latch. OVP triggering, VR3 should be selected to conduct
only when the output voltage is outside the normal regulation
To reduce no-load input power and thus increase light load range. Resistor R4 prevents excessive current from flowing
efficiency, resistor R3 feeds the supply current for U1 from the into the BP/M pin.
auxiliary winding on the transformer. • Fast recovery glass-passivated diodes were selected for
D1 and D3 to reduce low frequency conducted EMI. Fast
diodes such as FR107 are also suitable.
35
PI-4415-050806
30
25 EF20, N67 or equivalent, gap
Core Material
20
for ALG of 203 nH/T2
Voltage (V)
Bobbin 5+5 pin horizontal

15 Shield: 24T, 28 AWG
10 Winding Details
Bias: 5T, 4 × 28 AWG
5 12 V: 7T, 23 AWG T.I.W.
3 mm tape margin, shield
0
Winding Order (1-NC), tape, primary (3-1),
-5 (Pin Numbers) tape, bias (5-4), tape, 12 V
0 50 100 (10-9), tape
Time (ms) Primary: 790 µH ±7%
Inductance
3
Figure 2. Worst-Case Open Loop Output Overvoltage
(85 VAC, Full Load). Primary Resonant
650 kHz (min)
Frequency
T.I.W.: Triple Insulated Wire, NC: No Connection
3-295
Rev. A 09/06
APPLICATION NOTE
Design Idea DI-118
®
TinySwitch-III
4.5 W CV/CC Charger with <260 mW No-load Consumption

Charger TNY276P 4.56 W 90-265 VAC 5.7 V, 800 mA Flyback
Design Highlights When the primary current reaches the MOSFET current limit,
the controller turns it off, and the energy in T1 is transferred
• Simple, low cost, low parts count CV/CC solution to the output. Schottky diode D6 and capacitor C5 rectify and
• Low input power at no-load: <260 mW at 265 VAC filter the output. Inductor L3 and capacitor C7 attenuate the
• Efficiency >65% at 90 VAC switching ripple on the output.
• Meets CEC / ENERGY STAR requirements for active
mode efficiency (66.8 % vs. 62.6 % requirement) The primary clamp (D5, R2, C4 and R1) limits the maximum
• Compact design using small, low cost EE16 core size peak drain voltage to less than the 700 V BVDSS rating of the
• >15 dBµV margin to EN55022B conducted EMI limits internal MOSFET. Resistor R2 reduces high-frequency leakage
• No Y-capacitor: <10 µA line frequency leakage current inductance ringing and thereby EMI. The tightly controlled
tolerances of U1 allow this configuration to still meet low no-
Operation load input power levels.
The CV/CC charger circuit shown in Figure 1 was designed
as a Flyback converter, using TNY276P (U1). The device The pi filter formed by C1, L1, L2 and C2 attenuates conducted
has its four SOURCE pins on one side of its 8-pin package, EMI while C8 and R8 on the secondary side reduce high
which simplifies the layout of the PCB copper for heatsinking. frequency ringing. The integrated frequency jitter feature of
Additionally, the value of C3 selects the reduced current limit U1 along with E-ShieldTM techniques allow such simple EMI
of U1. Both factors allow U1 to deliver full power from within filtering to ensure compliance with EN55022B, even without a
a sealed enclosure, at an external ambient temperature of Y-capacitor across the primary to secondary isolation barrier.
40 °C. In less thermally challenging applications, a TNY275P
operating at its standard current limit (C3 = 0.1 µF) could be The output is regulated using optocoupler feedback. During
3 used to reduce cost, without any other changes. CV operation, reference IC U3 senses the output voltage
The internal MOSFET within U1 conducts current through the C8

1 nF R8
primary winding of T1 during each enabled switching cycle. 50 V 10 Ω
C5 R3 L3
L1 470 µF 1.2 Ω Ferrite Bead 5.7 V,
1 mH 10 V 2W 3.5 × 7.6 mm 800 mA
1 NC NC 10
D1 D2 C7
1N4005 1N4005 C4 R1 D6 100 µF
1 nF 200 kΩ 2 SB260 10 V
RF1 1 kV 7
8.2 Ω 3,4
2.5 W T1 RTN
C1 C2 EE16 R4
4.7 µF 4.7 µF 100 Ω
400 V 400 V R2
100 Ω
90-265
VAC
D5
1N4007GP
D3 D4 U2-B
R7
1N4005 1N4005 13.7 kΩ
L2 1%
Ferrite TinySwitch-III
Bead U1 C6
TNY276P 100 nF R5
D 50 V 1 kΩ
EN/UV
BP/M
S
S
C3 U2-A U3
1 µF PC817A TL431 R6
50 V 10 kΩ
1%
PI-4422-051006
Figure 1. 4.56 W, 5.7 V CV/CC Charger Using TNY276P.
3-296
Rev. A 09/06
via R6 and R7 and drives the optocoupler. However, the • Place tape between the primary winding layers to reduce
control shifts to CC mode of operation when the voltage intra-winding capacitance. This will help reduce the no-load
across R3 exceeds the forward drop of the photo-diode in U2. consumption.
TinySwitch-III allows this simple CC sensing scheme to be used,
while still meeting active mode efficiency requirements. 80
PI-4421-090806
EN55022B Limits
70
QP
• Verify that the maximum drain voltage is <650 V at high 50

AV
line and maximum overload condition. Adjust the values of
R1 and C4 as necessary. However, avoid making the clamp 40
QP
dBµV
circuit too large (i.e. low value of R1 and high value of C4), 30
as this will increase the no-load power consumption. AV
20
• Selecting a fast diode instead of an ultra-fast diode for
D5 will improve efficiency by recovering leakage energy. 10
If glass passivated (1N4007GP) is unavailable an FR107 may 0
be used.
-10
• For consistent EMI performance in production, manufacturing
variations in transformer T1 must be minimized from unit -20
to unit. This is especially important in designs that do not 0.15 1.0 10.0 100.0
use a Y-capacitor. MHz
Figure 2. Worst-Case Conducted EMI (Output RTN Connected
to Artificial Hand Input of LISN).
TRANSFORMER PARAMETERS 6.5
PI-4423-050906
EE16, NC-2H material or equiv- 6
Core Material 5.5
alent, gap for ALG of 156 nH/T2
Output Voltage (VDC)
5
Bobbin 5+5 pin horizontal 4.5 115 VDC
Shield: 28T, 2 × 33 AWG 4 230 VDC
Primary: 120T, 33 AWG 3.5 Low Limit
Winding Details 3 High Limit
Shield: 8T, 2 × 27 AWG
5.7 V: 10T, 25 AWG T.I.W. 2.5
Shield (3-NC), tape,

2
1.5 3
Winding Order primary (2-1), tape, 1
(pin numbers) shield (NC-3), tape, 0.5
5.7 V (10-7), tape 0
0 100 200 300 400 500 600 700 800 900
Primary: 2.25 mH ±12%
Inductance
Leakage: 45 µH (max) Output Current (mA)
Primary Resonant Figure 3. Typical Output Characteristics.
850 kHz (min)
Frequency
T.I.W.: Triple Insulated Wire
3-297
Rev. A 09/06
APPLICATION NOTE
Design Idea DI-119
®
LinkSwitch-LP
Cordless Phone Linear Adapter Replacement
with 10 kV Surge Withstand
Cordless Phone/Adapter LNK562P 1.6 W 85-265 VAC 7.7 V, 210 mA Flyback
Design Highlights The LNK562 device (U1) provides primary side sensed output
voltage and current regulation, eliminating the need for an
• Simple, low-cost, low parts count CV/CC solution optocoupler. Using the PI Transformer Designer software, shield
• Low no-load input power: <180 mW at 265 VAC windings were included in the transformer design. This allowed
• Dramatically improved regulation over line frequency the circuit to meet EN55022 B conducted EMI limits without
linear transformer the use of a Y-rated safety capacitor bridging the primary to
• Meets CEC / ENERGY STAR requirements for active secondary isolation barrier.
mode efficiency (63% vs. 53% requirement)
• Small, low-cost EE16 core size allows compact design The AC input is rectified and filtered by D1, D2 and C1, C6.
• >15 dBµV margin to EN55022B conducted EMI limits The input capacitance is split to form a π filter with L1 and L3,
• No Y-capacitor gives low (<10 µA) line frequency with R5 damping the self resonance. Varistor RV1 provides surge
leakage current protection for differential surges while RF1 provides filtering
• Meets 10 kV common mode and 2 kV differential mode and fusing. The internal MOSFET of U1 drives the transformer
surge (EN 1000-4-5 Class 4) primary, but the normal primary clamp network is not required
due to the low current limit of U1. Skipping switching cycles
Operation based on the voltage sensed from the bias winding provides output
Supplies for cordless phones or answering machines often regulation. Should the output of the supply be overloaded, then
require a 10 kV common mode surge withstand capability to U1 lowers the switching frequency to limit the output current
prevent damage to the telephone network during local lightning until ~2 V, when the unit enters auto-restart.
strikes. The design shown in Figure 1 meets this requirement
while still being simple and low cost.
3
RF1 C4
10 Ω D1 L1 D4 100 µF
2.5 W 1N4937 1 mH T1 1N4933 25 V 7.7 V, 210 mA
L 1
J1 J4 J3-1
NC R8
4.7 kΩ J3-2
R5 RTN
4.7 kΩ 2 J5
3
85-265 RV1 C6 C1 C3
VAC 275 VAC 3.3 µF 3.3 µF 10 µF
400 V 400 V 50 V 4
R7 D3 EE16
4.7 kΩ 1N4005
D2 L3
1N4005 1 mH
N
J2 R6
100 kΩ
R1
22.1 kΩ
D 1%
LinkSwitch-LP FB
U1 BP
LNK562 R2
S C2 3.01 kΩ
100 nF 1%
50 V
PI-4491-092806
Figure 1. LNK562 Linear Adapter Replacement Schematic.
3-298
Rev. A 09/06
Elimination of the optocoupler and Y1 capacitor allowed the

necessary printed circuit board (PCB) clearance and creepage
to be obtained to withstand a 10 kV surge. The use of triple
insulated wire for the secondary winding that terminates onto
the PCB as flying leads (J4 & J5) allows the necessary creepage
from primary to secondary. Figure 2 shows the PCB layout.
Key Design Points

• Verify maximum drain voltage is <650 V at high
line, maximum overload. For EMI repeatability, the
transformer must be manufactured consistently. This is
especially important in designs with no Y-capacitor.
• Using a fast diode for D1 improves EMI.
Figure 2. PCB Layout – Extended Clearance and Creepage
• Make sure the PCB layout provides 10 mm clearance Provided by Slot (A). Spark Gap Provided to Route High
and 15 mm creepage distance (use a slot in the PCB to Currents Back to Input and Around Electronics (B).
increase creepage distance).
• Provide a path for surge discharge currents to go around
12
sensitive electronic components (see spark gap (B) in
PI-4501-090606
Figure 2). 10
85 VAC
265 VAC
• To prevent arcing, keep the PCB surfaces clean. Remove
flux and any other contaminants. Output Voltage (V)
8
6
4
Core Material EE16, gap for ALG of 113 nH/T2
Bobbin 4+4 pin horizontal 2
Bias/Shield: 29T, 2 × 37 AWG
0
Winding Details 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
Secondary: 17T, 30 AWG TIW Output Current (A)
Bias/Shield (3-4), tape, primary Figure 3. Typical Output Characteristics. 3

Winding Order
(2-1), tape, shield (NC-1), tape,
(pin numbers)
7.7 V (FL-FL), tape
Inductance
Primary Resonant
250 kHz (min)
Frequency
TIW = Triple Insulated Wire, NC = No Connect, FL = Flying Lead
3-299
Rev. A 09/06
APPLICATION NOTE
Design Idea DI-123
®
TinySwitch-III
9.65 W, Dual Output Power Supply for Residential
Heating Control
Residential Heating Control TNY275P 9.65 W 185-265 VAC 5 V / 0.25 A, 24 V / 0.35 A Flyback
Design Highlights MOSFET is turned off. Then the energy stored in T1 transfers
to the secondary where it is rectified and filtered by D1 and C2
• Simple, low cost design only requires 38 parts and D4 and C5. The primary side RCD clamp (D8, C4 R1 and
• <150 mW no-load consumption at 230 VAC input R8) limits the peak DRAIN voltage spike caused by transformer
• Meets CEC / ENERGY STAR active-mode efficiency leakage inductance.
and no-load input power requirements
• Both outputs exhibit good cross regulation Power Integrations E-Shield™ transformer construction
• Meets CISPR-22 Class B/EN55022 B without input techniques, the RCD clamp, a snubber (R11 and C14), a simple
X or Y capacitors or an input common mode choke π filter (C7, C8, L1 and L5) and the frequency jitter function
of the TinySwitch-III family, provide good EMI margin, even
Operation with the output return connected to safety earth ground (see
The flyback converter shown in Figure 1 uses a TNY275 Figure 3).
(U1) to provide two output voltages: 5 V at 250 mA and
24 V at 350 mA. Typical applications are residential heating Key Design Points
controllers (furnace) or any application where 2 outputs are
required. The 9.65 W of output power is delivered by using • The turns ratio of the two secondary winding was
the increased current limit of U1, which is selected by the optimized for output voltage centering.
value of C11. • The use of a fast instead of an ultrafast diode for
D8 improves efficiency by recovering some leakage
The MOSFET integrated within U1 switches the primary of inductance energy.
transformer T1. Each time it turns on, the primary current
3 ramps until it reaches an internal current limit and the
R10
10 Ω C13
1/2 W 470 pF
L2 C4
1 nF L4
330 µH FB 24 V, 350 mA
1 kV 1 T1 10
R8 D1 UF4003 C2 C12
75 kΩ 220 µF L3 47 µF
D4 1N5819 35 V FB 35 V
6
3
D2 D3 R1 5 V, 250 mA
C5 C6
1N4937 1N4007 100 Ω 100 µF
330 µF
L 8, 9 10 V 16 V
D8
FR106 EF20 RTN
F1 C7 C8
1A 10 µF 10 µF TinySwitch-III
185-265 400 V 400 V R2
VAC U1
D TNY275P 47 Ω R3 R9
EN/UV 15 kΩ 261 kΩ
R11 BP/M
1% 1%
N 100 Ω
R4
S U2 1 kΩ
R12 PC817A C10 R5
D5 D7 30 Ω 100 nF 3.3 kΩ
1N4937 1N4007 C14 C15 C11
33 pF 0.1 µF 10 µF
1 kV 50 V 50 V U3
LM431
2% R6
L5 L3, L4 and L5 are 10 kΩ
FB 3.5 mm × 10 mm 1%
Ferrite beads.
PI-4495-090706
Figure 1. TinySwitch-III 9.65 W Residential Heating Controller Power Supply.
3-300
Rev. A 09/06
80
• Maximize the value of R8 and minimize the value of C4
PI-4496-090706
EN55022B Limits
for the lowest no-load consumption. However, verify 70
that the peak drain voltage is <650 V at high line, under 60
QP
maximum overload conditions. AV
50
• Select transformer wire gauge sizes so that each winding
QP
layer occupies the full bobbin width. This lowers leakage 40
dBµV
inductance and improves output cross regulation. 30
• Use option to add E-Shield windings in PI Transformer AV
20
Designer software to reduce conducted EMI noise
generation. 10
• To lower the no-load power consumption even further, 0

use an optional bias supply circuit to feed the rated data -10
sheet current (through a series resistor) to the
-20
BP/M pin of U1. 0.15 1.0 10.0 100.0
MHz
Load Regulation (%) Figure 3. Worst Case Conducted EMI at 230 VAC, Full Load
Output
Range Output Return Grounded.
(V) -2 -1.5 -1 -0.5 0 0.5 1 1.5 2
(mA)
5 50-250
24 88-350 TRANSFORMER PARAMETERS
EF20 TDK PC40, or equivalent
Table 1. Worst Case Output Cross Regulation at 185 VAC Core Material
Output Loads Varied as Shown and Maximum ALG of 323 nH/T2
Deviation Recorded. EF20, 10 pin (5+5), horizontal
Bobbin
Pin Shine P-2015 or equivalent
80
PI-4497-090506
Primary: 36T + 35T, 33 AWG

79 Shield: 4T, 5 × 29 AWG
Winding Details 5 V: 3T, 4 × 26 AWG T.I.W.
Efficiency (%)
78 24 V: 11T, 26 AWG T.I.W.

(4 × 26 AWG = quadfilar 26
AWG)
77
Apply 2 mm tape margin to both 3
sides of bobbin
76 Winding Order
Shield (1-NC), tape, Primary
(Pin Numbers)
(3-1), Shield (NC-1), 5 V (6-8),
75 24 V (10-6)
185 205 225 245 265
AC Input Voltage (V) Inductance
Leakage: 50 µH maximum
Figure 2. Full Load Efficiency vs Input Voltage.
Primary Reso-
800 kHz (minimum)
nant Frequency
TIW = Triple Insulated Wire, NC = No Connect
3-301
Rev. A 09/06
APPLICATION NOTE
Design Idea DI-124
®
LinkSwitch-TN
Ultrawide Input Range (57-580 VAC) Flyback Power Supply

Metering / Industrial LNK304 3W 57-580 VAC 12 V, 250 mA StackFET Flyback
Design Highlights A 600 V MOSFET, Q1, and U1 are arranged in the StackFET
configuration (cascode). The drain of U1 drives the source of
• StackFETTM flyback topology delivers full load over Q1 while the drain of Q1 drives the transformer primary. The
extremely wide input voltage range drain voltage of U1 is limited to 450 V by VR1-3. This extends
• E-ShieldTM transformer construction for reduced the maximum peak composite drain voltage of U1 and Q1 to
common-mode EMI (>10 dBµV margin) 1050 V. The resistor chain R6-R8 provides startup charge for
• 66 kHz switching frequency with jitter reduces the gate of Q1 and R9 dampens high-frequency ringing. Once
conducted EMI the converter is operating, the gate is largely driven by the
• Simple ON/OFF controller – no feedback compensation charge stored in the capacitance of VR1-3. Zener VR4 limits
required the gate to source voltage of Q1. Leakage inductance energy
• Auto-restart function for automatic and self-resetting is clamped by VR5 and D9 with R10 added to reduce ringing
open-loop, overload and short circuit protection and thereby, EMI.
• Built-in hysteretic thermal shutdown at 135 ºC
The operation of U1 is unaffected by the StackFET configuration.
Operation When the internal MOSFET turns on, Q1 is also turned on,
The AC input is rectified and filtered and the resultant DC applying the input voltage across the transformer primary.
applied to one end of the transformer primary winding. The Once the primary current reaches the internal current limit
450 V input capacitors are stacked with parallel balancing of U1, the MOSFET is turned off and the energy stored
resistors to meet the required voltage rating. Resistors R1 to is delivered to the output. Regulation is maintained using
R4 provide fusing in case of a catastrophic failure. Inductor ON/OFF control. Switching cycles are enabled/disabled based
L1, C1 and transformer E-Shield windings allow the design to on current into the FEEDBACK pin of U1. This is ideal as it
3 meet EN55022 B conducted limits with good margin. results in a lowering of the effective switching frequency with
C1
2.2 nF
250 VAC
D1 D2 D3 D4
1N4007 1N4007 1N4007 1N4007 R13 VR5 D10
475 kΩ R6 EEL16 UF4004 L2
680 kΩ P6KE150A 12 V, 250 mA
0.5 W NC 4
C5 C6 R14 0.5 W
15 µF 15 µF 475 kΩ Ferrite Bead
D9
PH1 R1 450 V 450 V 0.5 W R7 UF4007 5
680 kΩ C2 C3
10 Ω 1 W C9 0.5 W 470 µF 100 µF
PH2 R2 5.6 nF R10 7 16 V 16 V
1 kV 200 Ω 9
R8
10 Ω 1 W C8 680 kΩ
C7 15 µF R16 0.5 W
PH3 R3 450 V 10 1
15 µF 475 kΩ
450 V R15 0.5 W T1 RTN
10 Ω 1 W R9
475 kΩ
N R4 0.5 W 10 Ω Q1
IRFBC20
10 Ω 1 W
R5 R11
1k VR4 330 Ω
1N5245B
D5 D6 D7 D8 VR1 15 V U2B U2A
D PC817A PC817A
1N4007 1N4007 1N4007 1N4007 L1 P6KE150A FB
1 mH U1
LNK304P BP
R12
VR2 S 1 kΩ
P6KE150A
C4 VR6
VR3 100 nF BZX79-C11
P6KE150A 50 V 11 V
PI-4487-082906
Figure 1. Schematic Diagram of 3 W Bias Supply using LinkSwitch-TN in StackFET Configuration.
3-302
Rev. A 09/06
load, scaling switching losses and maximizing efficiency. The 80
PI-4493-081806
use of LinkSwitch-TN further improves efficiency due to its 75
66 kHz switching frequency.
70
Efficiency (%)
60
• The input stage (to the left of C9) can be omitted in
applications that have a high-voltage DC bus. Capacitor 55
C9 is still required to provide local decoupling. 50
• Long cores (EEL) are ideal for this application to provide
greater bobbin width to accommodate the increased 45
margins required to meet safety spacings at the high 40

operating voltage. 50 150 250 350 450 550
• Zener diodes VR1-3 can be replaced with a single AC Input Voltage (V)
P6KE540 device.
• The value of capacitors C5 to C8 can be reduced to Figure 3. Full Load Efficiency vs. Input Voltage.
10 µF if operation down to 57 VAC is not required
(100 VAC minimum).
• Use 0.5 W resistors for R13-16 and R6-8 to provide
adequate voltage rating. Core Material EEL16, gap for ALG of 70 nH/T2
• Efficiency falls at high line due to switching losses. 6+4 pin (Ying Chin YC-1604-1)
Reducing transformer capacitance by adding layers of Bobbin
with 3 mm + 3 mm tape margins
tape between the primary winding layers minimizes this.
Winding Details
80
PI-4492-090706
EN55022B Limits Secondary: 30T, 29 AWG TIW

70
Shield (5-NC), tape, primary
QP
60 Winding Order (7-5), tape between layers,
50
AV (pin numbers) shield (9-10), tape, 12 V / (4-1),
tape
40
dBµV
Inductance
30 QP Leakage: 160 µH (max)
3
20 Primary Resonant
500 kHz (min)
10 AV Frequency
0 Table 1. Transformer Design Parameters.

-10
-20
0.15 1.0 10.0 100.0
MHz
Figure 2. Conducted EMI (230 VAC, EN55022B Limits,
AV and QP Results).
3-303
Rev. A 09/06
APPLICATION NOTE
Design Idea DI-128

PeakSwitch
35 W (75 W Peak) Variable-speed
DC Motor Drive
DC Motor Drive PKS606Y 35 W (75 W Pk) 90-265 VAC 12 V Flyback
Design Highlights 10 VDC voltage source (connected to J4). The motor speed
controls vary the output voltage of the supply.
• Replaces a two-stage, linear power supply and chopper
circuit with a simple, single-stage design
The controller in U1 receives feedback from the output and
• Eliminates the chopper circuits normally used to achieve
enables or disables the switching of its integrated MOSFET.
variable-speed control of DC motors
Regulation is maintained by disabling or skipping MOSFET
• Motor speed is controllable by a small potentiometer or a
switching cycles. The output voltage is sensed across the series
3.6 V to 10 V variable DC voltage
string of R12, Zener diode VR2 and the LED in U2 (in parallel
• Low component count: only 47 parts
with R13). As the output voltage rises above the VR2 conduction
• Efficiency: ≥77% (at a load of 35 W)
threshold, the current that flows through the U2 LED turns on
• Meets EN55022 B conducted EMI limits
transistor Q3. As Q3 pulls current out of the EN/UV pin of
• ON/OFF control scheme is stable over the entire motor
U1 switching cycles are skipped and less energy is transferred
speed (output voltage) range
to the output. Once the output voltage falls, switching cycles
are enabled again.
Operation
The flyback converter shown in Figure 1 uses a member of the A bias winding (T1, pins 4 and 5) on the transformer is rectified
PeakSwitch family (U1, a PKS606Y) to drive a 35 W motor, and filtered by D7 and C6, and supplies operating current to
while delivering startup and load transition peaks of up to 75 W. U1, through R7. A smart AC sense circuit–comprised of D5,
The motorʼs speed is variable by two methods: 1) potentiometer C7, R5 and R6–enables the under-voltage lockout (UVLO)
R20 (connected to J3), or 2) an externally supplied 3.6 V to and latching shutdown functions of U1. The frequency jitter
3 C10
1 nF
250 VAC
R8
68 Ω
1/2 W
C11
330 pF
1 kV
9,10
R20
D8 J3-1 5 kΩ
MBR1060
C15
1 7,8 100 nF
R12 J3-2
50 V
C4 4.99 kΩ
D1-D4 VR1
180 µF 1%
1N4007 C17 C5 P6KE200A
400 V
4700 pF 470 pF 200 V 3 C20 +12 V
1 kV 1 kV 680 µF JP3
C12
25 V
R15 R3 680 µF
2.2 Ω 25 V J2-1
150 Ω D12
1/8 W 2 1N4148 MOTOR
1/2 W D6
FR106 5
J2-2
C6
47 µF 4
D5 R19 RTN
L1 35 V
1N4007 VR2 2 kΩ
5.3 mH
1A 1N5222B
2.5 V
R1 & R2 R7 R5
1.3 MΩ PeakSwitch 4.7 kΩ 2.2 MΩ
U1 J4-1
RT1 C7 PKS606Y R6
D7 +
t 10 Ω
O
100 nF D 1N4148 C19 R13

JP1 2.4 MΩ
C3 400 V EN/UV 1 nF 1 kΩ
680 nF U2B 250 VAC J4-2
BP
275 VAC PC817X4
S GND U2A C21 PI-4519-110606
PC817X4 1.0 µF
Q3 50 V
F1 C8 2N3904
C2,C1 3.15 A 220 nF
100 pF R18
50 V 20 Ω
275 VAC JP2 1/8 W
H PE L
CON3
Figure 1. Circuit Diagram of 35 W Continuous, 75 W Peak, Motor Drive Power Supply with Dual Speed Control Inputs.
3-304
Rev. A 11/06
function within U1, a shield winding in T1, and two small • If the motor is stopped externally for more than
Y-capacitors (C10 and C19) across T1 reduce the generation of 30 ms, U1ʼs latching shutdown function activates, and
conducted EMI so that a single common mode choke (L1), a MOSFET switching latches off until AC input power is
small X-capacitor (C3) and two small Y-capacitors (C1 and C2) removed and reapplied. If latching shutdown is not needed,
at the input allow the supply to meet EN55022B limits with more the function can be disabled and the parts count reduced by
than 12 dBµV of margin. A combination RCD-Zener clamp not installing D5, C7, R5 and R6.
(R3, C5, D6 and VR1) limits the peak drain-node voltage to
below the 700 V rating of the integrated MOSFET. 80
PI-4524-110206
70
If JP3 is removed, an external variable resistor (R20) adjusts QP
60
the voltage across R12 and therefore, the output voltage.
AV
The externally supplied motor speed regulating voltage 50
(3.6 to 10 VDC) changes the voltage at the node of R12 and VR2, 40 QP
which effectively adjusts the output voltage. Diode D12 blocks
dBµV
30
reverse current flow through R19 if the external adjustment
AV
voltage is less than about 3.6 VDC. 20
10
Key Design Points 0
• The externally supplied voltage adjusts the motor speed as -10

follows: ≤3.6 V sets the output voltage to about 12 V (the -20
highest motor speed) and ≥7 V sets the output voltage to 0.15 1.0 10.0 100.0
about 2 V (the lowest motor speed). MHz
• If the resistive speed control circuit is to be used, jumper Figure 3. Conducted EMI: 230 VAC in, IOUT = 4 A (48 W).
J3 must be removed from the PCB.
100
PI-4523-110606
Core Material PC40EE25-Z

Bobbin EE25 Vertical
80
1/2 Primary: 19T, 2 × 31 AWG
Bias: 5T, 2 × 29 AWG
Efficiency (%)
60 Winding Details Secondary: 4T, 4 × 23 AWG

Shield: 7T, 4 × 23 AWG 3
40 1/2 Primary: 19T, 2 × 31 AWG
1/2 Primary (1-3), Bias (4-5),
Winding Order
20
Secondary (7,8-9, 10), Shield
(pin numbers)
(1-NC), 1/2 Primary (3-2)
Inductance 145 µH
0
1 3 5 8 10 15 20 25 30 35 40 50 Leakage
5.4 µH
Inductance
Output Power (W)
Primary Resonant
Figure 2. Efficiency Across Extended Motor Load Range. 3.4 MHz (minimum)
Frequency
3-305
Rev. A 11/06
APPLICATION NOTE
Design Idea DI-129

PeakSwitch
33 W (60 W Peak) PVR Power Supply

PVR PKS606P 33 W (60 W Pk) 195-265 VAC 3.3 V, 5 V, 17.5 V, 22 V Flyback
Design Highlights As the 3.3 V or the 5 V output voltages rise above their set-
point thresholds, U2 pulls additional current through the LED
• Small, low-cost EF25 core size delivers 60 W peak
in U5. This in turn increases the base drive to Q1, increasing
the current pulled out of the EN/UV pin of U6. Switching
• High efficiency: ≥76% at 33 W
cycles are skipped once the EN/UV disable threshold current is
• No-load power consumption <140 mW
exceeded. When the current out of the EN/UV pin falls below
• Meets EN55022 B conducted EMI limits
the disable threshold, switching cycles are re-enabled.
Operation A bias winding (T1, pins 4 and 5) on the transformer is rectified
The flyback converter shown in Figure 1 uses a member of the and filtered by D15 and C21, and supplies operating current to
PeakSwitch family (U6, a PKS606P) to supply 33 W continuously U6, through R14. The frequency jitter function within U6 and
and peak power pulses of up to 60 W. a Y-type capacitor (C10) across T1 reduce the generation of
conducted EMI so that a single common mode choke (L5) and
The controller in U6 receives feedback from the secondary a small X-capacitor (C13) allow the supply meet EN55022B
through U5, and based on that feedback, enables or disables the limits with 6 dBµV or more of margin. A combination RCD-
switching of its integrated MOSFET to maintain regulation. A Zener clamp (R2, R15 C9, D10 and VR2) limits the peak
portion of both the 3.3 V and the 5 V outputs are fed into the drain-node voltage to below the 700 V rating of the MOSFET
TL431 (U2), which controls the current through the LED in U5. integrated within U6.
C10
3
2.2 nF
1 kV
VR2
1N4764A
100 V T1
1 6 +22 V
D8 C15 360 mA
C14
C9 STPS3150 150 µF 220 µF
2.2 nF 2 7 35 V 35 V
R15 +17.5 V
1 kV 670 mA
D5 D6 10 kΩ D9 C16 C8
L3
1N4007 1N4007 1/2 W STPS3150 2200 µF 3.3 µH 220 µF
8 16 V 10 V
R2 3 +5 V
C13 22 Ω 1.6 A
F1 D2 C17 L4 C6
100 nF 1/2 W D15
2A 1N4148
SB530 2200 µF 3.3 µH 220 µF
275 VAC 16 V 10 V
C20 5 10 +3.3 V
D10 1.74 A
33 µF FR106 D7
400 V C21
L5 47 µF SB520
19 mH 35 V 4 9
RTN
RV1 R14 EF25 R13 C18 VR1
275 VAC 4.7 kΩ 15 Ω 100 µF 1N4733A
1W 50 V 5.1 V
PeakSwitch -5 V
R11 28 mA
U6 D U5B D13 R12
PKS606P EN/UV PC817D 1N4148 R10 3.92 kΩ 56.2 kΩ
C22 150 Ω 1% 1%
BP 100 nF
Q1 2N3904 50 V
S C11
R17 100 nF
22 Ω 50 V
D4 D3 C12
1N4007 1N4007 220 nF R16 R9
50 V 1 kΩ 3.3 kΩ
D16
1N4148 U5A
PC817D
C2
10 µF U2 R8
50 V LM431A 10 kΩ
2% 1%
PI-4522-110906
Figure 1. Circuit Diagram of a 33 W Continuous, 60 W Peak, PVR Power Supply.
3-306
Rev. A 11/06
Resistor R16 provides the bias current for U2. Resistor R10 All output windings are AC stacked and exhibit good cross
sets the gain. Capacitor C22 improves transient responsiveness. regulation, due to the tight coupling within transformer T1.
Capacitor C11 and resistor R9 roll off the high frequency gain of The –5 V output uses Zener diode VR1 as a post regulator.
U2. Capacitor C2 performs a soft-finish function that prevents
the 3.3 V and the 5 V output voltages from overshooting their Key Design Points
regulation set points during the initial power up of the converter.
• All secondary winding should be wound in layers right
95 next to each other, in order to assure the best cross
PI-4527-110706
regulation.
85 • Use foil for 3.3 V and 5 V secondary windings for the
best cross regulation.
75
• The reflected output voltage (VOR) was set at 126 V to
Efficiency (%)
65 ensure good output voltages cross regulation. If tighter

cross regulation is needed, a lower value of VOR could
55 be used at the expense of reduced peak power delivery.
• The configuration of U5, Q1, R17 and D6 increases the
45
speed of U5 and reduces pulse grouping.
35
25 TRANSFORMER PARAMETERS
195 205 215 225 235 245 255 265
Core Material PC40EF25-Z or equivalent
AC Input Voltage Bobbin EF25 Horizontal
Figure 2. Efficiency vs. Input Line Voltage at Full Load, Room
Temperature, 50 Hz Line.
1/2 Primary: 32T, 31 AWG
Bias: 9T, 0.45 mm
Winding Details Secondary: Foil 2T, Foil 1T,
110
6T, 0.45 mm × 2 & 3T 0.25 mm
PI-4528-110906
1/2 Primary: 32T, 31 AWG

105
Primary (3-2), Bias (5-4),
Winding Order
Secondary (9-10, 10-8, 7-8,
Regulation (%)
100 (pin numbers)

6-7), Primary (2-1)
95 Primary
342 µH, ±10%
90 3.3 V
Inductance 3
5V Table 1. Transformer Design Parameters.
-5 V
85 22 V TIW = Triple Insulated Wire, NC = No Connect, FL = Flying Lead
17.5 V
80
190 200 210 220 230 240 250 260 270
AC Input Voltage (VAC)

Figure 3. Output Regulation vs. Input Line Voltage, Room
Temperature, Full Load.
3-307
Rev. A 11/06
APPLICATION NOTE
Design Idea DI-130
®
TinySwitch-III
Passive PFC LED Lighting Supply

LED Lighting TNY279P 18 W 185-265 VAC 10 V Flyback
Design Highlights by disabling or skipping MOSFET switching cycles. As the

load current reaches the current limit set-point threshold, U1
• Very high efficiency: ≥82%
drives U3 on. The photo-transistor in U3 pulls current out
of the EN/UV pin of U2, causing it to skip switching cycles.
• No common-mode choke required to meet EN55022B
Once the output current drops below the current limit set-point
conducted EMI requirements
threshold, U1 stops driving U3, which stops pulling current
• Valley Fill circuit allows supply to meet IEC61000-3-2
out of the EN/UV pin of U2, and switching cycles are enabled
THD limits
again. The TL431 (U4) provides a reference for U1 to compare
• ON/OFF control rejects the high line ripple voltage
against the voltage drop across R11.
caused by the Valley Fill (THD correction) circuit
The output diode (D9) is located in the lower leg of the
Operation transformer (T1) secondary winding to reduce EMI noise
The flyback converter shown in Figure 1 uses a member of
generation. An RCD clamp (R16, C4 and D13) protects the
the TinySwitch-III family (U2, a TNY279P) to provide up to
drain node of the MOSFET from the flyback voltage spike.
1.8 A of load current to six, high-intensity, Luxeon LEDs (the
LXHL series).
The Valley Fill circuit (D5, D6, D7, C15, C16 and R15) limits
the values of the third and fifth harmonics of the line frequency
The output voltage is slightly below the forward voltage drop
current, which enables this supply to meet the requirements for
of the LEDs. Therefore, when the LEDs are connected to the
Total Harmonic Distortion (THD) specified in IEC61000-3-2.
supply, it operates in constant current (CC) mode. If the LEDs
are disconnected from the supply, Zener diode VR1 provides
3 voltage feedback, which regulates the output voltage at about
The frequency jittering function in U2, a shield winding in T1
and a Y class capacitor (C8) across T1 reduce the generation
13.5 VDC. A 100 mΩ resistor (R11) senses the output current
of conducted EMI so that a simple pi filter (C13, L1, L2 and
and an Opamp (U1) drives the optocoupler (U3), which provides
C14) allows the supply to meet EN55022B limits.
feedback to U2. The TinySwitch-III family of devices regulate
C8
2.2 nF
250 VAC
C6 C7
680 µF 680 µF
35 V 35 V 10 V, 1.8 A
1 10
D1, D2 R16 R11

1N4007 100 kΩ 2 D9
SB580 100 mΩ
R14 C16 1/2 W C4 6 1W RTN
5.1 kΩ 6.8 µF 1 nF
400 V D6 1 kV R5
F1 1N4007 C9
100 nF 1 kΩ
3.15 A 3 1/8 W R17
50 V
C12 R12 5.1 kΩ
L1 220 pF 47 Ω 1/8 W
2200 µH 1 kV 1/2 W U1
C13 C14 D5 D13
185-265 47 nF 220 nF 8 2
VAC 1N4007 UF4005 1
275 VAC L2 275 VAC
R15
+
2200 µH LM358 3
10 Ω D11 4
1/2 W TinySwitch-III 1N4148 R11
U2 2 kΩ
D TNY279P 1/8 W
EN/UV R10 VR1
51 Ω 12 V
R13 D7 BP/M R6
5.1 kΩ 1N4007 C10 C17 68 kΩ
D3, D4 C15 S C16 1/8 W
6.8 µF 100 nF 100 µF U4
1N4007 1 µF 50 V 16 V
400 V 50 V U3 TL431
PC817A 2%
PI-4520-110606
Figure 1. Circuit Diagram of a Passive PFC Power Supply for Driving Lighting LEDs.
3-308
Rev. A 11/06
Key Design Points

• Take the value of input capacitance calculated by PI Expert or
the PI Xls spreadsheet, divide it by two, and round up to the
next standard value to select the values of C15 and C16.
• Using PI Expert or the PI Xls spreadsheet, design the supply for
the maximum output power at the maximum VF of the LEDs.
• The LM358 (U1) contains two operational amplifiers. Ensure
that the inputs to the second amplifier (pins 5 and 6) are
connected to secondary ground.
86
PI-4525-110606
84
82
Efficiency (%)
80 Figure 3. Input Voltage (100 V /div) and Current (100 mA/div),

100% Showing the Effect of the Valley Fill Circuit.
78 75%
50%
76 25%
74 TRANSFORMER PARAMETERS
Core Material PC40EF25-Z
72
Bobbin EF25 Horizontal bobbin
70
Primary: 92T, 0.3 mm heavy
185 195 205 215 225 235 245 255 265
nyleze magnet wire
Winding Details
Input Voltage (VAC) Secondary: 14T 2 × 0.4 mm
Figure 2. Efficiency vs. Input Voltage at Different Load Levels, Triple Insulated Wire (TIW)
Room Temperature, 50 Hz Line. Winding Order
Primary (2-4), Secondary (6-10)
(pin numbers)
Inductance 1.6 mH
3
3-309
Rev. A 11/06
APPLICATION NOTE
3-310
Rev. A 11/06
Data Sheets 2
Application Notes 3

DESIGN ACCELERATOR KITSREFERENCE DESIGN KITS
Quick Reference Guide Quick Reference Guide
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Battery Chargers
Cell phone adapter/charger � �
Cordless phone charger � �
Cordless tool charger � � � � � �
Digital camera charger � �
PDA adapter � �
Industrial Charger � �
Communication
24/48 V DC-DC converter �
Broadband modem �
Router �
Telecomm line card �
VoIP phone
PoE Powered Device (PD)
Computer
External media drives � � � �
Laptop adapter � �
LCD monitor / TV � � �
LCD projector � �
Printer � � �
Scanner � � � � � �
USB hub
Wireless access point/router
Consumer
Cable/satellite set-top box � �
DVD player/recorder � �
Television standby � �
Video game � �
Home Appliance
Major appliance � � � � �
Small appliance � � � � �
Home Comfort � � � � �
General Lighting
LED lighting
Industrial
Lighting � � �
Programmable logic controller � � �
Utility meter � �
REFERENCE DESIGN KITS
DESIGN ACCELERATOR KITS
Quick
QuickReference
Reference Guide
Guide
DC
ert DC-
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Co C-D Po
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Po W p
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DA
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Po
Su
Battery Chargers
Cell phone adapter/charger � � �
Cordless tool charger � �
Digital camera charger �
PDA adapter � � �
MP3 / MD player adapter � � �
Communication
24/48 V DC-DC converter � �
Broadband modem � �
Router � �
Telecomm line card � �
VoIP phone � � �
PoE Powered Device (PD) � � �
Computer
PC standby power supply �
External media drives � �
Laptop adapter
LCD monitor / TV �
LCD projector �
Printer �
Scanner � �
USB hub �
Wireless access point/router � �
Consumer
Cable/satellite set-top box � �
DVD player/recorder � �
Television standby �
Video game
Home Appliance
Major appliance
Small appliance
Home Comfort
General Lighting � � �
LED lighting �
Industrial
Lighting �
Programmable logic controller � � �
Uninterruptible power supply �
Utility meter � � � �
TABLE OF CONTENTS
PI Expert Suite .....................................................................................4-1
PI Expert ..............................................................................................4-2
PI XIs Design Spreadsheet ..................................................................4-3
PI Transformer Designer ......................................................................4-4
DAK Reference Designs ......................................................................4-5

PI EXPERT
PI Expert Suite
TM
Power Supply Design Software Suite
PI Expert Suite power supply design software installation also

includes the PI Viewer software application. PI Viewer provides
a convenient means to review design files created with previous
versions of PI Expert.
Order Today!
You can order PI Expert on CD-ROM or download the software

from our Web site right now. Hereʼs how:
• Go to the PI website at www.powerint.com and click the

PI Expert link under DESIGN SUPPORT, then
• Select Order PI Expert CD-ROM to get the software and
website snapshot shipped to you, or
• Select Download PI Expert to download the software only,
or if you prefer
• Contact your local authorized PI sales representative or
PI Expert Design Software Suite distributor
PI Expert Design Software Suite includes several tools that help System Requirements
you to simplify the design of off-line power supplies and DC-DC
converters based on products from Power Integrations: • Windows® 2000, ME, 98, XP
• CD-ROM Drive (CD-ROM version)
PI Expert design software is an interactive program that • 60 MB Free Hard Drive Space
takes a userʼs power supply specifications and automatically • 128 MB RAM System Memory
generates the electrical design of the transformer (and other
critical components) needed to generate a working switch
mode power supply. Optimization choices for cost or efficiency 4
are included to deliver designs that meet specific needs. The
program reduces design time from days to minutes. PI Expert
provides a straightforward, easy to follow methodology for
defining transformer requirements, bulk input capacitor, and
PI components.
PI Xls Designer provides design spreadsheet support for

recently introduced Power Integrations ICs not yet included in
the PI Expert design software program, as well as providing
a simplified spreadsheet approach for other PI products for
advanced users who prefer a spreadsheet interface.
PI Transformer Designer is a unique tool that takes data from

an existing PI Expert or PI Xls design file, and provides a
complete electrical and mechanical transformer specification,
including step-by-step winding instructions.
4-1
Rev. C 02/05
PI EXPERT
PI Expert
TM
Automated Design Tool
PI Expert The results produced by the software include selecting the

appropriate PI device, the electrical specifications for an
PI Expert power supply design software is an easy-to-use, time- optimized transformer as well as parameters to aid the designer
saving innovative design tool created by Power Integrations. in the selection of key components (input bridge, input capacitor,
clamp selection, under-voltage, overvoltage, output rectifiers
4 Three quick and easy steps to power supply design are what and output capacitors). The software creates designs based
make PI Expert indispensable among power supply engineers. around PIʼs TOPSwitch-FX, TOPSwitch-GX, TinySwitch-II,
Simply enter the power supply input and output specifications, and DPA-Switch product families.
then select the PI device family, package type and optimization
preferences. The software does all the rest. It truly slashes design
time, helping you get your product to the market faster.
4-2
Rev. C 02/05
PI EXPERT
PI Xls
Design Spreadsheet
A B D F G H I
LINKSwitch_082602_rev1c Copyright Power Integrations

1 Inc. 2002 INPUT INFO OUTPUT UNIT LINKSwitch 082602: LINKSWITCH Flyback Supply Design Spreadsheet
2 ENTER APPLICATION VARIABLES Description
6 VO 5.5 Volts Output Voltage
7 IO 0.5 Amps Continuous Output current
8 tC 3 msec Bridge Rectifier Conduction Time Estimate
9 CIN 9.4 uFarads Input Filter Capacitor
10
11 TARGETED / ESTIMATED LOSSES
12 P_NO_LOAD_GOAL 300 mW Target No Load losses for Power supply
13 PCORE 141.9261 mW Estimated Core Losses at peak Flux Density (BP)
14 RSEC 0.2 Ohms Estimated Resistance of transformer secondary winding.
Power losses at no load (includes feedback and switching losses). No Load losses
15 P_NO_LOAD_LOSS 245 mW target achieved
16
18 VMIN 100.8155 Volts Minimum DC Input Voltage
19 VMAX 374.7666 Volts Maximum DC Input Voltage
20
21 ENTER OUTPUT CABLE PARAMETERS
22 RCABLE 0.3 Ohms Resistance of total length of cable from power supply terminals to load and back.
23 VCABLE 0.15 Volts Drop along cable connecting power supply to load
24
25 ENTER LINKSWITCH & OUTPUT DIODE VARIABLES
26 LINKSwitch LNK501 Universal 115 Doubled/230
27 Power 3 5
28 I^2 f 2710 A^2 Hz I^2 f (typical) co-efficient for LinkSwitch
29 VOR 52 52 Volts Reflected Output Voltage (40<VOR<60 recommended)
30 VLEAK 6 Volts Error in Feedback voltage as a result of leakage inductance in primary circuit.
Output Winding Diode Forward Voltage Drop (0.5~0.7V for schottky and 0.7~1.0V for
31 VD 0.7 Volts PN diode)
60 Volts Ra
3 Amps
PI Xls is a stand-alone application as part of the PI Expert Suite, spreadsheets can be exported in Microsoft Excel format, ideal
providing access to Power Integrationsʼ design spreadsheets for for design documentation.
specific products and circuit topologies. It allows designers to
quickly generate key transformer and circuit parameters and PI Xls spreadsheets can be found within PI Expert by launching
evaluate design tradeoffs for circuits and products that may not the PI Xls design tool from the main “Tools” menu.
yet be fully supported by the PI Expert design software. The
Supported in
Device Family Topology Part Numbers
PI Xls PI Expert PI Transformer Designer 4
TOP242-250 ✓ ✓ ✓
Flyback
TOPSwitch- GX TOP245P, TOP246P ✓ ✓
Forward TOP248-250 ✓
TOPSwitch-FX* Flyback TOP232-234 ✓ ✓ ✓
TOPSwitch-II* Flyback TOP221-227 ✓ ✓
TOP41x* Flyback TOP412/414 ✓ ✓
TNY263, TNY265 ✓ ✓
TinySwitch-II Flyback
TNY264-268 ✓ ✓ ✓
TinySwitch* Flyback TNY253-255 ✓ ✓
Flyback ✓ ✓
DPA-Switch DPA423-426
Forward ✓ ✓ ✓
LinkSwitch Flyback LNK500-501 ✓ ✓
LinkSwitch-TN Buck & Buck-Boost LNK302-306 ✓
LinkSwitch-HF* Flyback LNK354 ✓ ✓
LinkSwitch-XT Flyback LNK362-364 ✓
LinkSwitch-LP Flyback LNK562-564 ✓
TinySwitch-III Flyback TNY274-280 ✓
PeakSwitch Flyback PKS603-606 ✓
Device Families and Topologies Supported by PI Xls, PI Expert and PI Transformer Designer. *Not recommended for new designs
4-3
C 02/05
Rev. D 04/06
PI EXPERT
PI Transformer Designer
Transformer Construction
PI Transformer Designer is a new timesaving and easy-to-use PI Xls 6 by processing data from pre-existing PI Expert and
tool from Power Integrations designed to bring the PI Expert PI Xls design files.
software suite to a new level of functionality.
By providing a clear and standardized way of presenting
PI Transformer Designer helps you to generate detailed transformer design information (including step-by-step winding
transformer specifications for your PI Expert and PI Xls instructions and detailed material listing), it greatly simplifies
designs. Supporting multi-filar windings, foil windings, one the task of making prototypes or requesting samples from a
negative output and AC stacked transformers, it also provides transformer vendor.
the option of including low cost shield windings, to lower
electromagnetic interference from the power supply and simplify PI Transformer Designer supports all families in the flyback
EMC compliance. It works as an extention to PI Expert 6 and topology and DPA-Switch in the forward topology.
4-4
Rev. C 02/05
REFERENCE DESIGNS
Reference Designs
Reference Designs provide all of the essential materials to get you

started on your next switch mode power supply design. The kits
include a fully assembled and tested prototype power supply board,
comprehensive engineering report, product samples, unpopulated
circuit board, data sheet and other related documentation. Reference
Designs are available through your local sales representative,
distributor or from the Power Integrations website.
For additional reference designs and design examples, visit

www.powerint.com/designsupport.htm.
2.75 W, 5.5 V AC-DC Power Supply (DAK-16A)
Board Specifications (EP-16)
VIN 85-265 VAC

VOUT 5.5 V @ 0.5 A
POUT 2.75 W
Samples
LNK500P, 501P, 520P & Unpopulated PCB
Documentation
Engineering Report, LinkSwitch Data Sheets &
AN-35 Application Note
10 W, Multi-Output AC-DC Power Supply (DAK-18)

VIN 85-265 VAC
VOUT 3.3 V @ 1.5 A, 5 V @ 0.9 A, 30 V @ 0.03A
POUT 10 W
Samples
TOP243P & Unpopulated PCB
Documentation
Engineering Report & TOPSwitch-GX Data Sheet
AN-29 & AN-32 Application Notes
4-5
Rev. E 04/06
REFERENCE DESIGNS
30 W, 5 V DC-DC Power Supply (DAK-21A)

VIN 36-72 VDC
VOUT 5V@6A
POUT 30 W
Samples
DPA423R/S, 424R/S, 425R/S, 426R/S & Unpopulated
PCB
Documentation
Engineering Report, DPA-Switch Data Sheet &
20 W Multi-Output AC-DC Power Supply (DAK-32)

VIN 85-265 VAC
VOUT 3.3 V @ 0.6 A, 5 V @ 1.2 A, 12 V @ 0.2 A,
-24 V @ 50 mA
POUT 20 W (cont.), 25 W (peak)
Samples
TOP245P & Unpopulated PCB
Documentation
Engineering Report, TOPSwitch-GX Data Sheet,
45 W, 12 V AC-DC LCD Monitor External Power Supply (DAK-33)

VIN 90-265 VAC
VOUT 12 V @ 3.75 A
4 POUT
Samples
45 W
TOP247Y & Unpopulated PCB

Documentation
30 W, 12 V AC-DC Power Supply (DAK-34)

VIN 85-265 VAC
VOUT 12 V @ 2.5 A
POUT 30 W
Samples
TOP245Y & Unpopulated PCB
Documentation
4-6
Rev. E 04/06
REFERENCE DESIGNS
1.44 W, 12 V Non-Isolated Appliance Power Supply (DAK-48A)

VIN 85-265 VAC
VOUT 12 V @ 120 mA
POUT 1.44 W
Samples
LNK302P/G, 304P/G, 305P/G, 306P/G & Unpopulated
PCB
Documentation
Engineering Report, LinkSwitch-TN Data Sheet &
2.75 W, 5.5 V Low Cost Charger / Adapter (DAK-54)

VIN 85-265 VAC
VOUT 5.5 V @ 500 mA
POUT 2.75 W
Samples
LNK520P/G & Unpopulated PCB
Documentation
Engineering Report, LinkSwitch (LNK520) Data Sheet
& AN-35 Application Note
6.6 W, 3.3 V DC-DC Supply for Distributed Power with PoE Front End (DAK-68A)

VIN 36-72 VDC
VOUT 3.3 V @ 2 A
POUT 6.6 W
Samples
DPA423G/S, 424G/S, 425G/S & Unpopulated PCB
Documentation 4
Engineering Report & DPA-Switch Data Sheet
6.6 W, 3.3 V DC-DC Standby Supply For Distributed Power (or DPA) (DAK-71A)

VIN 36-72 VDC
VOUT 3.3 V @ 2 A
POUT 6.6 W
Samples
DPA423G/S, 424G/S, 425G/S & Unpopulated PCB
Documentation
4-7
Rev. E 04/06
REFERENCE DESIGNS
1.6 W, 7.7 V Cordless Phone Linear Adapter Replacement (RDK-83)
Board Specifications (RD-83)

VIN 85-265 VAC
VOUT 7.7 V @ 210 mA
POUT 1.6 W
Samples
LNK562P/G, 563P/G, 564P/G & Unpopulated PCB
Documentation
Engineering Report, LinkSwitch-LP Data Sheet,
AN-39 Application Note & Design Idea DI-85
2 W, 6 V Low Cost Charger (DAK-85)

VIN 90-265 VAC
VOUT 6 V @ 330 mA
POUT 2W
Samples
Documentation
Engineering Report, LinkSwitch-LP Data Sheet &
6.6 W, 3.3 V PoE Powered Device (DAK-86)

4 VIN 33-57 VAC
VOUT 3.3 V @ 2 A
POUT 6.6 W
Samples
DPA423S, 424G/S, 425G/S & Unpopulated PCB
Documentation
4-8
Rev. E 04/06
REFERENCE DESIGNS
2 W, 6.2 V CV Adapter (DAK-89)

VIN 85-265 VAC
VOUT 6.2 V @ 332 mA
POUT 2W
Samples
Documentation
Engineering Report, LinkSwitch-XT Data Sheet &
12 W, 12 V Universal Input Supply (DAK-91)

VIN 85-265 VAC
VOUT 12 V @ 1 A
POUT 12 W
Samples
TNY274P/G 275P/G, 276P/G, 277P/G, 278P/G, 279P/G,
280P/G & Unpopulated PCB
Documentation
Engineering Report & TinySwitch-III Data Sheet
32 W / 81 W Peak, 30 V Universal Input Supply (DAK-93)

VIN
VOUT
90-265 VAC
30 V @ 1.07 A 4
POUT 32 W / 81 W pk
Samples
PKS604P/Y, 605P/Y, 606P/Y & Unpopulated PCB
Documentation
Engineering Report, PeakSwitch Data Sheet &
4-9
Rev. E 04/06
REFERENCE DESIGNS
4-10
Rev. E 04/06
Data Sheets 2
Application Notes 3

QUALITY & RELIABILITY
Quality and Reliability Overview
Quality and Reliability Overview Quality Management System

It is the goal of Power Integrations to be a reliable supplier of Power Integrations Quality Management System is ISO9001
energy efficient, high voltage integrated circuits that provide certified and it is registered with Bureau Veritas Quality
cost-effective power conversion and control functions. This International Inc. (BVQI). The quality system is woven
overview provides an insight into the quality systems that help throughout design, manufacturing, customer support, and
make this goal a reality. management functions. There are company-wide quality support
systems, including document control, internal audits, training,
Total Quality Commitment and continuous improvement programs. The overall quality
system and plan are documented in the quality manual. An
Power Integrations considers quality to be a critical factor in overview of the quality system is illustrated in Figure 1.
determining the success of the relationship with its customers
and suppliers alike. The company is committed to continuous Document Control
improvement of quality across all of its functional entities An essential part of quality system is the set of documented
and through all phases of the product life-cycle. At Power policies, specifications, procedures and drawings that are
Integrations, quality management begins during product controlled electronically within Power Integrations. This
development and continues through manufacturing and delivery insures that only current specifications are released to production
to the customer. Power Integrations, Inc. is committed to provide and that obsolete revisions are removed and archived in
products and services of high quality standards that meet or a systematic fashion. Whenever applicable, customerʼs
exceed customersʼ expectations. procurement specifications are reviewed by Quality Assurance
Quality Management System

Document Control
Training
Continual Improvement
5 Management Review
Process Control Applications Support
Product Definition Design Validation Internal Audit Customer Service
4 Design Controls
Design Reviews
Product Characterization
Product Qualification
Inspection and Testing
Supplier Management
Problem Resolution
Change Notification
Design Verification Application Validation EDAS Customer Feedback
Reliability Monitor Survey
Development Production Release Manufacturing Customer Support
PI-2722-010305
Figure 1. Quality System Map.
5-1
Rev. F 06/06
Continuous Improvement Process Flow
1. Measurement
Perform Gage R&R
Tools.
Process Monitors
2. Identify Critical Process Pareto of Failures
Characteristics. FMEA
Yield Study
Quality Planning
Precontrol, SPC,
Process Control Charts
Capable? Yes 3. Critical Process
in Control? XBar & R, P, C,
Cp, Cpk X Moving Range
No Brainstorming,
Cause & Effect
Yes Diagrams,
4. Identify Critical Process
No Parameters and their Yes Scatter Plots,
limits. Taguchi/Classical
DOE
Hold Gain and

Improve Continuously Precontrol, SPC,
5. Critical Process Control Charts
Parameters stable & XBar & R, P, C,
within limits? X Moving Range
No
Graphs, Tables,
5
6. Develop Action Plans - Tools in Step 4
Control Parameters
PI-2723-011105
Figure 2. Continual Improvement Process Flow.
and the applicable Engineering groups to identify any special Certification testing is repeated at six-month intervals to ensure
requirements. Special manufacturing flows, if required, are consistency in the performance of the operators per documented
documented and controlled within the Quality Assurance requirements.
group.
Continual Improvement
Training Continual improvement consists of a system of positive feedback
Employee skills are crucial to high quality performance. to correct any deficiencies. Customer inputs as well as the
Manufacturing requirements are communicated through observed trends are combined with closed-loop remedial actions
operator training and certification programs to ensure that to ensure continual improvement. The process is illustrated
proficiency is maintained at the highest possible skill levels. by Figure 2.
5-2
Rev. F 06/06
Management Review • Consideration of any resource requirements necessary to

The quality management system is periodically reviewed by the effectively address any identified deficiencies
executive staff for adequacy and relevance to the companyʼs
quality policy and quality objectives. Quality policy and The management review output consists of decisions and actions
objectives are communicated to all of the employees. Among related to the necessary improvements in the quality management
the management review inputs are the following. system. The minutes are documented and disseminated to
all responsible personnel, and followed up in the subsequent
• Status of progress towards quality objectives review meetings.
• Potential areas of improvement and recommended actions
• Status of process performance and product conformity Product Development
• Review of customer feedback obtained through surveys
• Review of the findings of internal and external audits, Product definition, design, qualification, and introduction follow
assessment of any recurring problems a thorough and rigorous discipline as illustrated in Figure 3
• Review of the status of corrective and preventive actions and described below. Quality planning is integrated with the
Product Development Cycle
Core functionality demonstrated

with some limits
New Product Fab and Assembly Concept data sheet
Business Analysis Early customer sampling
Very limited quantity
No Product Code β
Beta Sampling
Approved?
Silicon Validation
Device Characterization
Functional Silicon Full functionality demonstrated
Yes
Design Validation Automated test system developed
Early reliability verified
Objective Technical Preliminary data sheet
Specification Limited sample quantity
Limited prototype board quantity
Product Code D Approved? Key Customer Sampling
Product Code S
Design No
Schematics Yes
Layout Production Test Program Released
Simulation Reliability Verification Completed
5 Test Plan
No
Design Review Qualification Characterization completed
Final data sheet issued
Thousands in stock
Hundreds of Application Kits
Product Code A
Approved?
Approved? Marketing collateral
Application Tools
Application Guide Hundreds of
1,000 Application Kits thousands in stock
Yes Production Thousands in Stock Mass production
Product Code L capability
Product Code M
Tapeout and
Mask Release
Product Launch Mass Production
PI-3204-011105
Figure 3. Product Development Cycle.
5-3
Rev. F 06/06
engineering systems and design methodologies to blend in the progress of the product development and serve as a formal
various requirements and thus create a product suitable to meet review to ensure conformance of the design with its objective
customersʼ needs. technical specification as well as manufacturing and testability
requirements.
Product Definition
Key market requirements, competitive performance features, Design Verification
cost targets, and quality requirements are carefully considered Before the new product is released for wafer fabrication, the
and optimized to define a product. Product marketing and circuit design is subjected to simulation routines to verify device
applications engineering work together to create an objective performance for normal and extreme operating conditions.
technical specification which guides the designers to a set of Simulation routines are also applied to evaluate the productʼs
device parameters needed to create the optimum product. tolerance to manufacturing variations.
Before the actual design process begins, the objective technical Functional Silicon
specification is reviewed by the development team to make sure The functional silicon phase begins with the start of the first
that it is realistic, reliable, achievable and cost-effective. wafer lot. Important milestones within this phase are design
validation and product qualification, which are described below.
Design Start Any deviation observed during the evaluation is reviewed and
Once the product design is initiated, formal methods and controls corrected with necessary modification of the original design
are applied to make sure that the product will be manufacturable until all quality and performance requirements are met.
and perform reliably. Automated design tools apply design
rules, which guarantee that product performance is tolerant of Design Validation
normal process variations. Layout rules govern the physical Design validation begins immediately as the first wafer lot is
structure of the circuit to ensure reliability and manufacturability. fabricated. The design is validated by taking measurements of
Test engineers review the design for testability to make sure product parameters on the functional silicon to confirm that the
that all important product parameters can be measured in a product functions as expected and meets the design targets.
production-worthy manner.
Characterization of the first few wafer lots, across a broad
Design Review range of conditions, including temperature extremes beyond
During the development phase, the development team the expected operating conditions, are done to confirm that the
regularly holds design reviews. These reviews track the productʼs functional requirements have been met. Measured
Reliability Test Name Specification Conditions

High Temp. Reverse Bias MIL-STD 883-1005 150 °C, 80% of max rev. bias
Temperature-Humidity JESD 22 – A101 85 °C, 85% RH, 30 V rev. bias
Temperature Cycle MIL-STD 883-1010 -65 °C to +150 °C
SMD Moisture Sensitivity JESD22-A112A Level 1 or 4
Dynamic Operating Life JESD. 22 – A108 125 °C, 80% of specified BVDSS
ESD-HBM JESD22 114A 2,000 V 5
ESD-CDM JESD22 101 500 V
ESD-MM JESD22 115 200 V
Latch Up EIA/JESD78 CLASS 1, >100 mA, 125 °C
Lead Fatigue MIL-STD 883–2004 B2
Lead Bend MIL-STD 883–2004 B1
Bond Pull MIL-STD 883–2011 C
Die Shear MIL-STD 883–2019
Solder Heat MIL-STD 750–2031 260 °C, 15 sec
Solderability MIL-STD 883–2003
Acoustic Microscopy JESD22-A112-A
Mark Permanence MIL-STD 883–2015
Table 1. Reliability Tests for Product Qualification.
5-4
Rev. F 06/06
performance is compared to simulations, and any variance is Active Area critical dimensions
noted for investigation by engineering to understand the cause
and to refine the design rules and models. Field oxidation thickness
Gate oxidation thickness
System level characterization is done to confirm the suitability Polysilicon thickness
of the product for customer use. System fault response testing
is done to check the productʼs response to a set of system faults Polysilicon critical dimensions
selected to stress the IC to worst case conditions. LTO Deposition thickness
Metal thickness
The data gathered from these evaluations is distilled into the
Metal critical dimensions
final device specifications. The final limits are set to ensure
that process shifts will not impact product quality. Table 2. Wafer Fabrication Monitors.
Product Qualification
Concurrently with design validation, product qualification
Process Control Monitor Testing
begins. All products are required to complete a formal
qualification program. Product qualification consists of a Wafer Test Attributes Data
number of stress tests designed to accelerate potential failure Visual Inspection
mechanisms, ensuring that the product is reliable. Stress tests
for qualification are selected from those listed in Table 1 in a Table 3. Wafer Test Monitors.
case-specific manner.
Application Validation Saw kerf width

Product is evaluated on typical application platforms under the Die attach thickness and consistency
defined conditions of temperature, voltage, and other application
characteristics to ensure compliance to the limits published in Wire bond strength
the data sheet. Molding defects
Solderability
Manufacturing Mark permanency
Power Integrationsʼ manufacturing process is designed to Visual inspection
provide continuous control of product quality. The manufacturing Lead integrity
area has been designed for optimum production flow from
receiving through test operations, back-end processing, storage, Table 4. Assembly Monitors.
and shipping. A combination of discipline, in-line monitors,
sample testing, and real-time test data analysis assures a
consistent, predictable product output. Final Test Attributes at Room Temperature
Sample Electrical Test at 125 °C for Lot Acceptance
5 Process Control
Manufacturing quality is monitored and controlled at critical Sample Parameter Data Collection and Analysis
manufacturing process steps as shown in Figures 4-6. The in-line
Table 5. Final Test Monitors.
process monitors provide data to ensure that the manufacturing
steps are well controlled and capable of meeting quality targets.
At lot acceptance gates, the process records of each production lot improvements. The system provides the ability to store and
are reviewed to confirm proper processing and that all required analyze data from process, design, assembly, inspection and
tests were performed. Listing of in-line monitors at various test.
stages of production flow are given in Tables 2-5.
The integrated set of tools, known as EDAS, provide advanced
All changes in processing or materials are reviewed. Any changes statistical analysis techniques and graphical visualization of
that may impact product application, quality, or reliability are manufacturing data and process trends. Specialized tools
subject to re-qualification. support the extensive test characterizations that are performed
on new products, including guard band analyses and marginal
Engineering Data Analysis System (EDAS) parameter analyses. Engineering productivity improvements
Power Integrations uses sophisticated software tools and help streamline the characterization process and shorten the
databases to support process control and yield analysis and product development cycle.
5-5
Rev. F 06/06
Inspection and Testing 4. Monthly statistical process control (SPC) data in a format that
Manufacturing high-voltage integrated circuits requires allows Power Integrations to track continuous improvements
specialized testing beyond the capabilities of typical towards quality and manufacturing performance goals.
semiconductor test equipment. Power Integrations uses
automated testers especially designed for high voltage testing Power Integrations Manufacturing Partners have given
in a high-volume production environment. These testers enable unqualified support to the concept of the Manufacturing
100% testing of critical parameters. Gage reproducibility Partnership program as they join our goal to provide products
and repeatability (GR&R) studies, preventive maintenance, that meet or exceed customersʼ expectations.
and equipment calibration at regular intervals ensure the
accuracy and repeatability of the production testers. The test Product Traceability
floors were designed with safe high voltage testing in mind. Power Integrations maintains complete traceability of all
Special equipment allows 100% wafer testing of high voltage manufacturing steps. Each product is marked with a lot number,
components up to 1000 V. After 100% final electrical test which is the key to the processing history of that lot, including
at room temperature of finished products, QC unit samples process monitors, test results, and test parameter distributions.
are pulled randomly from each lot and tested at 125 °C to This lot number is also recorded in the customerʼs or distributorʼs
verify compliance per published specification and to make lot shipping records providing both forward and backward tracking
acceptance decisions. of material flow from wafer fabrication through delivery to the
customer.
Variable parameter data from sample testing of every lot are
collected directly from the testers and transferred to central
databases for future engineering review. Analysis is performed
with EDAS as described previously. Wafer Test Flow
Product specifications document specify how each device From Wafer
parameter is guaranteed, whether 100% test, or sample Fabrication
verification.
Supplier Quality Management

All suppliers of critical materials and manufacturing services are
Wafer
ISO9001 and ISO14001 registered. Each vendor is subject to Inspection
audits to identify ways to improve quality of materials provided
to Power Integrations.
Wafer fabrication vendors are required to provide data from

critical processes electronically with each lot. This information
is combined with Power Integrationsʼ manufacturing data in
EDAS to allow support engineers to monitor process trends Process
and correlate product performance to critical wafer process Wafer Sort Monitor
parameters.
5
For assembly subcontractors and wafer foundries, Power
Integrations has developed a Manufacturing Partnership Program
designed to achieve the highest quality materials with the shortest
cycle times, minimum inventory levels, and at the lowest total Optical
cost of ownership. Highlights of this program include: Inspection
and Lot
1. Quarterly quality and manufacturing performance ratings; Acceptance
2. A program to develop certified manufacturing partners that
allows product into Power Integrations manufacturing line
without the need for costly receiving inspection; To Assembly
3. Clearly defined requirements for both minor and major
change notification to Power Integrations so as to perform
any necessary qualification testing and to provide advance PI-1837-040201
notifications to customers per agreement;
Figure 4. Wafer Test Flow.
5-6
Rev. F 06/06
Package and Assembly Flow
Wafer Inspection
Solder Plate PM
Wafer Mount
PM
and Saw
Solderability Test
2nd Optical
Inspection / Lot
Acceptance Post Mold Lot
Acceptance
Die Attach PM
Marking PM
Wire Bond PM Mark Permanency

Test
100% Internal Visual

Inspection & Lot Trim and Form PM
Acceptance
5
Mold and Cure PM Final Inspection & Lot
Acceptance
Packing
Deflash PM
PM - Process Monitor
PI-2726-040201
Figure 5. Package and Assembly Flow.
5-7
Rev. F 06/06
products. The reliability monitoring program provides a regular

Final Test Flow monitor of manufacturing process as well as product reliability.
Samples from each product family are periodically subjected
to a variety of reliability stress tests and the data is reviewed
to determine any indications of process deviation. The results
of these monitors are used to continually improve reliability.
From Data is used to regularly update the reliability estimates for each
Assembly product family. Reliability reports are available to customers
upon request.
Customer Support
Customer support is an essential component of quality system.
With application design assistance to post-sales services, the
Receiving relationship with customer is maintained such that company
and its customers work as a team to serve the needs of the end
customer.
Applications Support
Applications Engineering provides comprehensive technical
100%
assistance. Application engineers help customers with many
Electrical Process development or design related tasks including device selection
Test Monitor and specification, circuit design, transformer design, PC design,
EMI filter design and regulatory compliance. The applications
engineering laboratory is fully equipped to evaluate customer
hardware.
Customer Service
Sample The Customer Service personnel are the customerʼs interface
QA Electrical with Power Integrations. Customer Service communicates the
Test customerʼs requirements to internal organizations. They also
work with the Manufacturing planners to schedule shipments.
If a problem surfaces, they will notify the customer and work
with the factory to resolve it.
Lot Customer Feedback Survey

Acceptance Company has a program for collecting feedback from selected
& Inspection customers regarding customer satisfaction on products, services,
quality, and delivery. The feedback data are reviewed by the
top management to identify opportunities for improvement. 5
Quality Support Services
Quality Assurance group is the focal point for resolution of
customer quality issues. Quality Assurance works closely
with Customer Service and other functional groups to provide
Finished pre and post-sales support to Power Integrationsʼ customers.
Goods Examples of quality support items include conducting customer
communications on quality matters, responding to customersʼ
PI-1839-040201
questionnaires, and administering a product change notification
Figure 6. Final Test Flow. (PCN) to those customers who have a major change notification
requirement.
Reliability Monitoring Program Reliability Engineering is responsible for supplying product

Maintaining a high quality manufacturing standard requires reliability information upon customer request.
periodic re-evaluation of both the production processes and
5-8
Rev. F 06/06
Failure Analysis analyzes and reports on all customer returns • High Resolution Optical microscopy
per RMA process flow illustrated in Figure 7. These reports • Emission Microscopy
document for the customer the analysis results and corrective • Scanning Acoustic Microscopy
actions. All incidences of product returns and discrepancies • Power Supply Module Characterization and Fault
are also reported to management and responsible groups within Diagnostic System
Power Integrations. • Chemical and Mechanical Deprocessing
• Probe station with Laser Cutter for fault isolation
Power Integrations maintains a failure analysis laboratory and • Scanning Electron Microscopy and Energy Dispersive
utilizes services of external laboratories that have many years X-ray Spectroscopy
of experience in semiconductor failure analysis. Some of the • Metallographic Cross Sectioning
analysis tools are listed below. • Auger Electron Spectroscopy
• X-Ray Photoelectron Spectroscopy
• High Voltage ATE equipment • Secondary Ion Mass Spectroscopy
• Various high-voltage device characterization and • Focused Ion Beam
measurement systems
5-9
Rev. F 06/06
No
Problem Review FA Report

Customer Report and Proposed Satisfied? Yes End
Corrective Action
Obtain RMA No. FA Request and

Area
from QA & Send RMA Information Review and Notify
Sales Mgr. or
Product to P.I. Forms Customer
Distributor
Rep. Headquarters
Preliminary Report
Correlation within 3 Days
Testing
Failure
Analysis
Failure Analysis
Root Cause Corrective Action Report
No
Analysis Required?
Yes
Corrective Action
Problem Evaluated Report
and Corrective No
Action Assigned
Quality
Assurance
Evaluates
Containment and
Acceptable? Yes
5
Permanent Action
Proposal
Yes
Implements
Permanent
Process Containment within
Corrective
Owner 7 Working Days.
Action
Proposes Long Term
Implemented
Corrective Action
PI-2727-040201
Figure 7. Failure Analysis and Corrective Action Process.
5-10
Rev. F 06/06
5-11
Rev. F 06/06
Data Sheets 2
Application Notes 3

TABLE OF CONTENTS
Plastic TO-220-7C ................................................................................6-1
Plastic TO-263-7C ................................................................................6-2
S-PAK MO-169-7C ...............................................................................6-3
TO-262-7C ...........................................................................................6-4
Plastic DIP-8 ........................................................................................6-5
Plastic DIP-8B ......................................................................................6-5
DIP-8C .................................................................................................6-6
SMD-8 ..................................................................................................6-7
SMD-8B ................................................................................................6-7
SMD-8C ...............................................................................................6-8
Tape & Reel Ordering Information ........................................................6-9
Pb-Free and RoHS Compliant Products ........................................... 6-11
Solder Temperature Profiles ...............................................................6-12
PC Board Cleaning ............................................................................6-13
Mounting Guidelines for TO-220 Package .........................................6-14

PACKAGE INFORMATION
Package Information
Package Design Specifications,
Tape & Reel and Assembly Information
Package Design Specifications
TO-220-7C
.165 (4.19)
.185 (4.70)
.390 (9.91) .045 (1.14)
.146 (3.71) .420 (10.67) .055 (1.40)
.156 (3.96)
.108 (2.74) REF
+ .234 (5.94)
.261 (6.63)
.461 (11.71) .570 (14.48)

.495 (12.57) REF.
7° TYP. .670 (17.02)
.860 (21.84) REF.
.880 (22.35)
.080 (2.03)
.120 (3.05)
.068 (1.73) MIN PIN 1 & 7 PIN 2 & 4
PIN 1 .024 (.61) .040 (1.02)

.010 (.25) M
.034 (.86) .060 (1.52)
.050 (1.27) BSC .012 (.30) .040 (1.02)
.024 (.61) .060 (1.52)
.150 (3.81) BSC
.190 (4.83)
.210 (5.33)
.050 (1.27)
.050 (1.27) Notes:
1. Controlling dimensions are inches. Millimeter
dimensions are shown in parentheses.
.050 (1.27) 2. Pin numbers start with Pin 1, and continue from left
to right when viewed from the front.
.050 (1.27) 3. Dimensions do not include mold flash or other
6
protrusions. Mold flash or protrusions shall not
.200 (5.08) .180 (4.58) exceed .006 (.15mm) on any side.
4. Minimum metal to metal spacing at the package
.100 (2.54)
body for omitted pin locations is .068 in. (1.73 mm).
PIN 1 PIN 7 5. Position of terminals to be measured at a location
.25 (6.35) below the package body.
.150 (3.81) .150 (3.81) 6. All terminals are solder plated.
Y07C MOUNTING HOLE PATTERN
PI-2644-122004
6-1
Rev. N 04/06
PACKAGE INFORMATION
TO-263-7C
.390 (9.91) .245 (6.22) .045 (1.14)
.420 (10.67) MIN .055 (1.40)
.055 (1.40)
.066 (1.68)
.225 (5.72)
.326 (8.28) MIN
.336 (8.53) .580 (14.73)
.620 (15.75)
.000 (0.00)
.010 (0.25)
.208 (5.28)
.090 (2.29)
Ref.
-A- .110 (2.79)
.010 (0.25)
0.68 (1.73)
LD #1 MIN .012 (0.30)
.024 (0.61)
.024 (0.61) .100 (2.54) .050 (1.27)
.034 (0.86) REF 0°- 8°
.315 (8.00)
.165 (4.19)
Solder Pad .185 (4.70)
Dimensions
.380 (9.65) .004 (0.10)
Notes:
1. Package Outline Exclusive of Mold Flash & Metal Burr.
.638 (16.21) 2. Package Outline Inclusive of Plating Thickness.
3. Foot Length Measured at Intercept Point Between
Datum A Lead Surface.
.128 (3.25) 4. Controlling Dimensions are in Inches. Millimeter
Dimensions are shown in Parentheses.
.050 (1.27) 5. Minimum metal to metal spacing at the package body
R07C
.038 (0.97) for the omitted pin locations is .068 in. (1.73 mm). PI-2664-122004
6-2
Rev. N 04/06
PACKAGE INFORMATION
S-PAK MO-169-7C
9.25 (0.364) 6.50 (0.256) C
A B
9.55 (0.376) REF 0.23 (0.009)
0.75 (0.029) 0.48 (0.019)
1.30 (0.051)
8.03 (0.316)
7.85 (0.309) 10.40 (0.410) REF
8.15 (0.321) 10.70 (0.421)
Detail A
1.27 (0.050)
PIN #1 BSC
1.78 (0.070)
2.54 (0.100) REF
BSC Detail A
6X 0.63-0.89 (0.025-0.035)
0.25 (0.010) M C A M B
1.75 (0.069) 0.23 (0.009)

0.48 (0.019) H
2.05 (0.081)
6X
C
0.10 (0.004) C
Notes: Seating
1. JEDEC reference: MO-169. Plane
2. Package outline exclusive of mold flash and metal burr. 0° - 8° 0.75 (0.029)
3. Package outline inclusive of plating thickness. 1.05 (0.041)
4. Minimum metal to metal spacing at the package body 0.25 (0.010)
1.53 (0.060)
for the omitted lead location is 1.78 mm (0.070 in). BSC GAUGE 0.00 (0.000)
REF
5. Datums A and B to be determined at datum plane H. PLANE 0.15 (0.006)
6. Controlling dimensions are in millimeters. Inch
dimensions are shown in parenthesis.
S07C PI-4024-071405
Solder Pad Information For S-PAK

Solder Pad
Dimensions
9.40 (0.370)
6
2.01 (0.079)
8.59 (0.338)
8.03 (0.316)
11.31 (0.445)
1.37 (0.054)
1.27 (0.050)
S07C 0.97 (0.038)
PI-4034-071405
6-3
Rev. N 04/06
PACKAGE INFORMATION
TO-262-7C
.045 (1.14)
.390 (9.91) .055 (1.40)
.420 (10.67) .165 (4.17)
.055 (1.40) .185 (4.70)
.066 (1.68)
.326 (8.28) .495 (12.56)

.336 (8.53) 7° TYP. REF.
.795 (20.18) .595 (15.10)
REF. REF.
.080 (2.03)
.120 (3.05)
.068 (1.73) MIN PIN 1 & 7 PIN 2 & 4
PIN 1 .024 (.61) .040 (1.02)

.010 (.25) M
.034 (.86) .060 (1.52)
.050 (1.27) BSC .012 (.30) .040 (1.06)
.024 (.61) .060 (1.52)
.150 (3.81) BSC
.190 (4.83)
.210 (5.33)
.050 (1.27)
.050 (1.27) Notes:
1. Controlling dimensions are inches. Millimeter
dimensions are shown in parentheses.
.050 (1.27) 2. Pin numbers start with Pin 1, and continue
.050 (1.27) from left to right when viewed from the front.
3. Dimensions do not include mold flash or
.180 (4.58) other protrusions. Mold flash or protrusions
.200 (5.08)
shall not exceed .006 (.15mm) on any side.
.100 (2.54) 4. Minimum metal to metal spacing at the pack-
PIN 1 PIN 7 age body for omitted pin locations is .068
inch (1.73 mm).
.150 (3.81) .150 (3.81) 5. Position of terminals to be measured at a
location .25 (6.35) below the package body.
MOUNTING HOLE PATTERN 6. All terminals are solder plated.
F07C
PI-2757-122004
6-4
Rev. N 04/06
PACKAGE INFORMATION
DIP-8
D S .004 (.10)
DIM inches mm
8 5
-E-
A 0.367-0.387 9.32-9.83
B 0.240-0.260 6.10-6.60
C 0.125-0.145 3.18-3.68
G 0.015-0.040 0.38-1.02
H 0.120-0.140 3.05-3.56 B
J1 0.057-0.068 1.45-1.73
J2 0.014-0.022 0.36-0.56
K 0.008-0.015 0.20-0.38
L 0.100 BSC 2.54 BSC
M 0.030 (MIN) 0.76 (MIN) 1 4
N 0.300-0.320 7.62-8.13 A -D-
P 0.300-0.390 7.62-9.91 M J1 N
Q 0.300 BSC 7.62 BSC
Notes:
1. Package dimensions conform to JEDEC C
specification MS-001-AB for standard dual in-line
(DIP) package .300 inch row spacing
(PLASTIC) 8 leads (issue B, 7/85). -F-
2. Controlling dimensions are inches.
3. Dimensions shown do not include mold flash H K
or other protrusions. Mold flash or G
protrusions shall not exceed .006 (.15) on any Q
J2
side. P08A
4. D, E and F are reference datums on the molded L P
body. PI-2076-101102
DIP-8B
⊕ D S .004 (.10) .137 (3.48) Notes:
-E- MINIMUM 1. Package dimensions conform to JEDEC specification
MS-001-AB (Issue B 7/85) for standard dual-in-line (DIP)
package with .300 inch row spacing.
2. Controlling dimensions are inches. Millimeter sizes are
shown in parentheses.
3. Dimensions shown do not include mold flash or other
.240 (6.10)
protrusions. Mold flash or protrusions shall not exceed
.260 (6.60)
.006 (.15) on any side.
4. Pin locations start with Pin 1, and continue counter-clock-
wise to Pin 8 when viewed from the top. The notch and/or
dimple are aids in locating Pin 1. Pin 6 is omitted.
Pin 1 5. Minimum metal to metal spacing at the package body for
6
the omitted lead location is .137 inch (3.48 mm).
.367 (9.32) 6. Lead width measured at package body.
-D- 7. Lead spacing measured with the leads constrained to be
.387 (9.83)
.057 (1.45) perpendicular to plane T.
.068 (1.73)
(NOTE 6)
.125 (3.18) .015 (.38)
.145 (3.68) MINIMUM
-T-
SEATING .008 (.20)
PLANE .120 (3.05) .015 (.38)
.140 (3.56)
.300 (7.62) BSC
.100 (2.54) BSC .048 (1.22) (NOTE 7)
.014 (.36)
.053 (1.35) .300 (7.62) P08B
.022 (.56) ⊕ T E D S .010 (.25) M .390 (9.91) PI-2551-121504
6-5
Rev. N 04/06
PACKAGE INFORMATION
DIP-8C
⊕D S .004 (.10) Notes:
-E- 1. Package dimensions conform to JEDEC specification
MS-001-AB (Issue B 7/85) for standard dual-in-line (DIP)
package with .300 inch row spacing.
2. Controlling dimensions are inches. Millimeter sizes are
shown in parentheses.
.240 (6.10) 3. Dimensions shown do not include mold flash or other
.260 (6.60) protrusions. Mold flash or protrusions shall not exceed
.006 (.15) on any side.
4. Pin locations start with Pin 1, and continue counter-clock-
wise to Pin 8 when viewed from the top. The notch and/or
dimple are aids in locating Pin 1. Pin 3 is omitted.
Pin 1
5. Minimum metal to metal spacing at the package body for
.367 (9.32) the omitted lead location is .137 inch (3.48 mm).
-D- 6. Lead width measured at package body.
.387 (9.83)
7. Lead spacing measured with the leads constrained to be
.057 (1.45) perpendicular to plane T.
.068 (1.73)
(NOTE 6)
.125 (3.18) .015 (.38)
.145 (3.68) MINIMUM
-T-
SEATING .008 (.20)
PLANE .120 (3.05) .015 (.38)
.140 (3.56)
.300 (7.62) BSC

.100 (2.54) BSC .048 (1.22) .137 (3.48) (NOTE 7)
.014 (.36)
.053 (1.35) MINIMUM .300 (7.62) P08C
.022 (.56) ⊕T E D S .010 (.25) M .390 (9.91) PI-3933-100504
6-6
Rev. N 04/06
PACKAGE INFORMATION
SMD-8
D S .004 (.10) DIM inches mm
8 5
-E- A 0.367-0.387 9.32-9.83
B 0.240-0.260 6.10-6.60
C 0.125-0.145 3.18-3.68
E S .010 (.25)
G 0.004-0.012 0.10-0.30
B P .420 H 0.036-0.044 0.91-1.12
J1 0.057-0.068 1.45-1.73
.046 .060 .060 .046 J2 0.048-0.053 1.22-1.35
J3 0.032-0.037 0.81-0.94
.080 J4 0.007-0.011 0.18-0.28
Pin 1
1 4 K 0.010-0.012 0.25-0.30
L L 0.100 BSC 2.54 BSC
.086
.186 M 0.030 (MIN) 0.76 (MIN)
A -D- .286 P 0.372-0.388 9.45-9.86
M J1 Solder Pad Dimensions α 0-8° 0-8°
Notes:
1. Package dimensions conform to JEDEC
specification MS-001-AB (issue B, 7/85)
C
K except for lead shape and size.
2. Controlling dimensions are inches.
-F- 3. Dimensions shown do not include mold
.004 (.10) flash or other protrusions. Mold flash or
J3 J4 protrusions shall not exceed .006 (.15) on
α G any side.
G08A J2 .010 (.25) M A S H 4. D, E and F are reference datums on the
molded body.
PI-2077-041003
SMD-8B
⊕ D S .004 (.10) .137 (3.48) Notes:
MINIMUM 1. Controlling dimensions are
inches. Millimeter sizes are
-E- shown in parentheses.
2. Dimensions shown do not
include mold flash or other
protrusions. Mold flash or
protrusions shall not exceed
.372 (9.45) .006 (.15) on any side.
.240 (6.10)
.388 (9.86) .420
.260 (6.60) 3. Pin locations start with Pin 1,
⊕ E S .010 (.25) and continue counter-clock-
.046 .060 .060 .046 wise to Pin 8 when viewed
from the top. Pin 6 is omitted.
6
4. Minimum metal to metal
.080 spacing at the package body
Pin 1 Pin 1
for the omitted lead location
.086 is .137 inch (3.48 mm).
.100 (2.54) (BSC)
.186 5. Lead width measured at
package body.
.286
.367 (9.32) 6. D and E are referenced
-D- Solder Pad Dimensions datums on the package
.387 (9.83)
body.
.057 (1.45)
.125 (3.18) .068 (1.73)
.145 (3.68) (NOTE 5)
.004 (.10)
.032 (.81) .048 (1.22)
.053 (1.35)
.009 (.23) .004 (.10) .036 (0.91) 0°- 8°
.037 (.94)
.012 (.30) .044 (1.12) G08B
PI-2546-121504
6-7
Rev. N 04/06
PACKAGE INFORMATION
SMD-8C
Notes:
⊕ D S .004 (.10) .046 .060 .060 .046 1. Controlling dimensions are
inches. Millimeter sizes are
-E- shown in parentheses.
.080 2. Dimensions shown do not
include mold flash or other
.086 protrusions. Mold flash or
.186 protrusions shall not exceed
.372 (9.45) .006 (.15) on any side.
.240 (6.10)
.388 (9.86) .286 .420 3. Pin locations start with Pin 1,
.260 (6.60)
⊕ E S .010 (.25) and continue counter-clock-
wise to Pin 8 when viewed
from the top. Pin 3 is omitted.
4. Minimum metal to metal
spacing at the package body
Pin 1 Pin 1 for the omitted lead location
.137 (3.48) is .137 inch (3.48 mm).
MINIMUM Solder Pad Dimensions 5. Lead width measured at
.100 (2.54) (BSC)
package body.
6. D and E are referenced
.367 (9.32) datums on the package
-D-
.387 (9.83) body.
.057 (1.45)
.125 (3.18) .068 (1.73)
.145 (3.68) (NOTE 5)
.004 (.10)
.032 (.81) .048 (1.22)
.053 (1.35)
.009 (.23) .004 (.10) .036 (0.91) 0°- 8°
.037 (.94)
.012 (.30) .044 (1.12) G08C
PI-4015-013106
6-8
Rev. N 04/06
PACKAGE INFORMATION
Tape & Reel Ordering Information TAPE REEL REEL

PACKAGE
WIDTH (W) PITCH (P) DIA QTY
Power Integrations makes selected surface-mount parts available
in tape and reel form for use with automatic pick-and-place SMD-8 16 mm 12 mm 330 mm 1000
equipment. Tape and reel specifications meet or exceed industry TO-263 24 mm 16 mm 330 mm 750
standard specification EIA-481.
MO-169-7C 24 mm 12 mm 330 mm 1000
Ordering Information Table 1. Primary Tape & Reel Dimensions and Reel Quantities.
Parts available in tape and reel form can be ordered by placing

a T&R ordering suffix after the base part number. The ordering Physical Specifications
suffix is TL.
Physical specifications of the tape, cover, and reel are governed
Base Part # T&R Suffix by EIA-481. Physical dimensions of the tapes are given in
TNY264G -TL Figure 2 and Table 2, and physical dimensions of the reels are
given in Figure 3 and Table 3.
Please contact the factory for other options. Minimum order
size is 1 reel per line item, and all orders will be in multiples Packaging for Shipment
of full reel quantities. The quantity per reel for each package
type is shown in Table 1. Power Integrations normal terms Power Integrations supplies the following information on the
and conditions apply. side of each reel for ease of product identification:
Electrical Specifications • Power Integrations part number (MPN), including

orientation suffix
Parts are subjected to the Power Integrations standard test flow, • Encapsulation date code (D/C)
after which the parts are loaded into the tape cavities and sealed • Assembly lot identification (LOT)
with a cover tape using standard anti-static handling procedures. • Quantity (QTY)
The tape and cover are constructed of conductive modified • Tape and reel packing date code (R/D)
polystyrene, providing a surface resistivity of ≤106 Ω/square.
The reel is made of polystyrene with a topical anti-static coating,
providing a surface resistivity of ≤1011 Ω/square.
User Direction of Feed
6
1
1
G Package R Package S-PAK

PI-4026-071505
Figure 1. Part Orientation.
6-9
Rev. N 04/06
PACKAGE INFORMATION
10 pitches
cumulative
P0 tolerance on tape
K ±0.2 mm
t D P2
Top
cover E
tape
A0
F
W
B1 B0
P
t1 Embossment D1
K0 Center lines
For machine reference only of cavity
including draft and radii User Direction of Feed
concentric around B0
Minimum bending radius

Tape and components shall pass
around "R" without damage
R
PI-807A-072794
Figure 2. Tape Dimension Index.
Tape
Package Type A0 B0 B1 D D1 E F K
Size
Plastic SMD-8 16 mm 10.1-10.3 10.0-10.2 12.1 (max) 1.5-1.6 1.5 (min) 1.65-1.85 7.40-7.60 6.5 (max)
Plastic TO-263 24 mm 10.9-11.1 16.2-16.4 16.9 (max) 1.5-1.6 1.5 (min) 1.65-1.85 11.40-11.60 5.9 (max)
6 MO-169-7C 24 mm 9.6-10.0 11.0-11.4 12.0 (max) 1.5-1.6 1.5 (min) 1.65-1.85 11.40-11.60 2.7 (max)
Tape
Package Type K0 P P0 P2 R t t1 W
Size
Plastic SMD-8 16 mm 3.60-3.80 11.9-12.1 3.9-4.1 1.90-2.10 40 (min) 0.400 (max) 0.10 (max) 23.7-24.3
Plastic TO-263 24 mm 5.40-5.60 15.9-16.1 3.9-4.1 1.90-2.10 50 (min) 0.350 (max) 0.07 (max) 23.7-24.3
MO-169-7C 24 mm 2.20-2.62 11.9-12.1 3.8-4.2 1.90-2.10 50 (min) 0.350 (max) 0.05 (typ) 23.7-24.3
Table 2. Tape Dimensions (in mm).
6-10
Rev. N 04/06
PACKAGE INFORMATION
Access hole
at slot location
40 (min)
A D C N
Tape slot
in core
for tape start
2.5 (min)
G
(measured at hub)
PI-808-120104
Figure 3. Reel Dimension Index.
Package Type Tape Size A B C D G N

Plastic SMD-8 16 mm 330 (max) 1.5 (min) 12.80-13.50 20.2 (min) 16 102 (ref)
Plastic TO-263 24 mm 330 (max) 1.5 (min) 12.80-13.50 20.2 (min) 24 102 (ref)
MO-169-7C 24 mm 330 (max) 1.5 (min) 12.80-13.50 20.2 (min) 24 102 (ref)
Table 3. Reel Dimensions (in mm).
Pb-Free and RoHS Hazardous Substances (RoHS), which mandates the removal of
lead and other hazardous substances cited in the directive.
Compliant Products
Power Integrations is committed to environmental, health and All Pb-free and RoHS compliant products have passed
safety excellence and is actively complying with regulatory qualification testing for moisture sensitivity, solderability, and
requirements regarding the removal of hazardous materials in whisker growth. Pb-free and RoHS compliant surface mount
manufacturing standards and processes. In response to concerns products also comply with the joint IPC/JEDEC industry standard
regarding the environmental impact of lead (Pb), a Pb-free solder on reflow solderability (J-STD-020C). More information on
soldering is included below.
6
finish is now available using 100% matte tin (Sn).
The S-PAK is only available with matte tin (Sn) solder finish RoHS compliant and Pb-free products are designated by an
and is RoHS compliant. N-suffix at the end of the part number (see the Part Ordering
Information section of the product family data sheets).
Pb-free packages offered by Power Integrations meet the
requirements of the European law on the Restriction of
6-11
Rev. N 04/06
PACKAGE INFORMATION
Solder Temperature Profiles
TYPICAL WAVE SOLDER PROFILE FOR Sn-Pb AND

Pb-FREE THROUGH-HOLE PACKAGES
15-25 s 10 s Max
Typical
260 °C Max (Lead-Free)
250 240-250 °C Max Range (Leaded)
Cool Down
2-4 °C/s
Temperature (°C)
200
150
Soak
100
Preheat at 2-3 °C/s

50
0
0 50 100 150 200 250
Time (s)
PI-3852-042706
TYPICAL IR REFLOW PROFILE FOR Sn-Pb AND

Pb-FREE SURFACE MOUNT PACKAGES
tp
Tp
Critical Zone
Ramp-Up TL to Tp
TL
Tsmax tL
Temperature (°C)
Tsmin
6 Ramp-Down
ts
Preheat
25
t 25 °C to Peak
Classification Reflow Profile (IPC/JEDEC J-STD-020C, Figure 5-1) Time (s)

Reproduced with permission by IPC and JEDEC, 2005 PI-3955-042706
Note 1: Pb-free packages are qualified for Sn-Pb assembly. Sn-Pb packages are not qualified for Pb-free assembly.
6-12
Rev. N 04/06
PACKAGE INFORMATION
Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly

Average Ramp-Up Rate 3 °C/second max. 3 °C/second max.
(Tsmax to Tp)
Preheat
± Temperature Min (Tsmin) 100 °C 150 °C
± Temperature Max (Tsmax) 150 °C 200 °C
± Time (tsmin to tsmax) 60-120 seconds 60-180 seconds
Time maintained above:
± Temperature (TL) 183 °C 217 °C
± Time (tL) 60-150 seconds 60-150 seconds
Peak/Classification Temperature (Tp) See Table 5 See Table 5
Time within 5 °C of actual Peak
10-30 seconds 20-40 seconds
Temperature (tp)
Ramp-Down Rate 6 °C/second max. 6 °C/second max.
Time 25 °C to Peak Temperature 6 minutes max. 8 minutes max.
Table 4. Classification Reflow Profiles (per IPC/JEDEC J-STD-020C, Table 5.2)
Note 1: All temperatures refer to topside of the package, measured on the package body surface.
Package Type MSL Sn-Pb Eutectic Assembly Pb-Free Assembly

G 4 225 +0/-5 °C 250 + 0 °C*
R 4 225 +0/-5 °C Not Available
S 4 Not Available 260 + 0 °C*
*Tolerance: Process compatibility is up to and including the stated classification temperature (this means Peak
reflow temperature + 0 °C. For example, 250 + 0 °C) at the rated MSL level.
Table 5. Peak/Classification Temperature (Tp) for PI Surface Mount Packages.
Note 1: Classification temperatures are in accordance with guidelines set forth in IPC/JEDEC J-STD-020C.
Soldering Guidelines: 4. Limit high temperature exposure only to single side or one
time and mostly to the leads area only.
1. Profiles shown are typical and will therefore vary with 5. Upon completion of soldering, gradual natural cooling
different soldering systems. should be observed for a minimum of three minutes.
2. Density and types of components on the board, size and Using forced cooling will increase temperature gradient
type of board, solder and flux being used, substrate material which increases mechanical stress leading to latent failure.
being used, equipment type/model and age are factors that
can influence the profile. 6
3. Since the melting temperature of solder is higher than the PC Board Cleaning
rated temperature of the device, care should be taken that Power Integrations does not recommend the use of "no-clean"
the device will get as little exposure as possible at the high flux.
temperature. Not doing so increases possibility of a device
failure.
6-13
Rev. N 04/06
PACKAGE INFORMATION
Mounting Guidelines for A smaller screw or larger heat sink hole can cause the tab to
be deformed, cracking the package. Care must also be taken
TO-220 Package to prevent contact between the plastic package and the screw
head or tool used to tighten it. Self-tapping screws may deform
Maximum Torque: the heat sink causing poor thermal contact.
The screw torque specification for the TO-220 packages used Rivets should not be used under any circumstances for TO-220
for Power Integrations products is 4 lbf • in or 0.45 N • m packages.
(4.6 kgf • cm) maximum.
The mounting surface must be flat and without burrs. Otherwise,
Mounting Guidelines: the TO-220 tab may be bent, causing damage to the IC chip.
The recommended fastener is a 6-32 screw using a rectangular Finally, the IC should be mounted to the heat sink before soldering
washer to prevent damage to the tab. If a rectangular washer the assembly to the PCB. Soldering the IC and heat sink to the
is not used, a round flat washer is required. The head of a PCB and then screwing them together will put unacceptable
machine screw is not flat enough to prevent damage. Without mechanical stress on the IC package.
a washer, damage to the plastic case and semiconductor chip
within may occur.
6-14
Rev. N 04/06
Notes
Notes
Notes
Notes
Notes
1 Product Selector Guide
2 Data Sheets
3 Application Notes
4 Reference Designs and Design Tools
5 Quality and Reliability
6 Package & Assembly Information

Worldwide Sales Support Locations
World Headquarters China (Shanghai) Korea

5245 Hellyer Avenue Rm 807-808A, RM 602, 6FL
San Jose, CA 95138, USA. Pacheer Commercial Centre, Korea City Air Terminal B/D, 159-6
Main: +1 408-414-9200 555 Nanjing Rd. West Samsung-Dong, Kangnam-Gu
Customer Service Shanghai, P.R.C. 200041 Seoul, 135-728, Korea
Phone: +1-408-414-9665 Phone: +86-21-6215-5548 Phone: +82-2-2016-6610
Fax: +1-408-414-9765 Fax: +86-21-6215-2468 Fax: +82-2-2016-6630
Email: usasales@powerint.com Email: chinasales@powerint.com Email: koreasales@powerint.com
Worldwide Applications China (Shenzhen) Singapore

Hotline: +1-408-414-9660 Room 2206-2207, Block A, 51 Newton Road,
Fax: +1-408-414-9760 Elec. Sci. Tech. Bldg. #15-08/10 Goldhill Plaza
2070 Shennan Zhong Rd. Singapore, 308900
On the Web Shenzhen, Guangdong, Phone: +65-6358-2160
www.powerint.com China 518031 Fax: +65-6358-2015
Phone: +86-755-8379-3243 Email: singaporesales@powerint.com
Fax: +86-755-8379-5828
Email: chinasales@powerint.com Taiwan
5F, No. 318, Nei Hu Rd., Sec. 1
Germany Nei Hu Dist.
Rueckertstrasse 3 Taipei 114, Taiwan R.O.C.
D-80336, Munich Phone: +886-2-2659-4570
Germany Fax: +886-2-2659-4550
Phone: +49-89-5527-3910 Email: taiwansales@powerint.com
Fax: +49-89-5527-3920
Email: eurosales@powerint.com United Kingdom
1st Floor, St. James’s House
India East Street, Farnham
#1, 14th Main Road Surrey, GU9 7TJ
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Phone: +91-80-4113-8020 Fax: +44 (0) 1252-727-689
Fax: +91-80-4113-8023 Email: eurosales@powerint.com
Email: indiasales@powerint.com
Italy
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Italy
Phone: +39-028-928-6000
Fax: +39-028-928-6009
Email: eurosales@powerint.com
Japan
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2-12-20 Kohoku-ku,
Yokohama-Shi Kanagawa
ken, Japan 222-0033
Phone: +81-45-471-1021
Fax: +81-45-471-3717
Email: japansales@powerint.com

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Innovation in power conversion

Data Book and Design Guide

Enabling cost-effective, and energy efficient

Product Selector Guide 1

Reference Designs and Design Tools 4

Quality and Reliability 5

Package & Assembly Information 6

LIFE SUPPORT POLICY

The PI logo, TOPSwitch, TinySwitch, LinkSwitch, DPA-Switch, PeakSwitch, EcoSmart, Clampless,

Printed in the U.S.A. ©Copyright 2007, Power Integrations, Inc.

PRODUCT FAMILY = ALPHA CHARACTERS

SERIES NUMBER = NUMERICAL CHARACTERS

F Plastic TO-262 package

Blank Standard (SnPb)

TAPE & REEL PACKAGING and OTHER OPTIONS

TL Tape & Reel packaging option

PRODUCT SELECTOR GUIDE .............................................................................................................................1-0

DATA SHEETS .......................................................................................................................................................2-0

DC-DC CONVERSION ICs

AC-DC CONVERSION ICs

LinkSwitch-TN Family .....................................................................................................................2-33

LinkSwitch-XT Family .....................................................................................................................2-47

LinkSwitch Family ...........................................................................................................................2-60

LinkSwitch-LP Family ...................................................................................................................2-110

PeakSwitch Family ........................................................................................................................2-123

TOPSwitch-GX Family ..................................................................................................................2-163

APPLICATION NOTES ..........................................................................................................................................3-0

DI-12 Lead Acid Battery Charger (TOP244P, 13.55 V @ 16 W, Universal) ..................3-212

PI Expert Suite .............................................................................................................................4-1

QUALITY AND RELIABILITY ................................................................................................................................5-0

Quality and Reliability Overview ..................................................................................................5-1

PACKAGE & ASSEMBLY INFORMATION............................................................................................................6-0

Product Selector Guide 1

Reference Designs and Design Tools 4

Quality and Reliability 5

Package & Assembly Information 6

AC-DC Product Selector Guide ............................................................1-1

DC-DC Product Selector Guide ......................................................... 1-11

AC-DC Product Selector Guide

85-265 VAC 0W 20 W 40 W 200 W

Output Characteristic Low Power Products

Tight CV, LNK500/501/520

Tight 274 TNY

Enclosed 0W 1W 1.5 W 2W 2.5 W 3W 3.7 W 5W 6W 6.5 W 8W 10 W 12 W 14 W

AC-DC Product Selector Guide

No-load Power Consumption

Simultaneous Line Sensing

EcoSmart® Low Standby/

and Current Limit

LinkSwitch-TN 230 VAC ± 15% 85-265 VAC

II. VERY LOW POWER AC-DC POWER CONVERSION (UP TO 9 W)

No-load Power Consumption

Simultaneous Line Sensing

EcoSmart Low Standby/

and Current Limit

1 LinkSwitch-LP 230 VAC ± 15% 85-265 VAC

III. LOW POWER AC-DC POWER CONVERSION (UP TO 36.5 W)

Simultaneous Line Sensing

and Current Limit

TinySwitch-III 230 VAC ± 15% 85-265 VAC

AC-DC Product Selector Guide

Latching Shutdown and Reset

Adaptive On-Time Extension