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LAPORAN TUGAS AKHIR

BAHASA DESKRIPSI PERANGKAT KERAS

Oleh :
Harits Al Furqon Akbar
165060300111012

Teknik Elektro
Fakultas Teknik
Universitas Brawijaya
2018
BAB I
PENDAHULUAN

1.1. Latar Belakang


Untuk memahami bagaimana kerja sebuah mikroprosesor, maka pengetahuan dan pemahaman bagian – bagian
yang menyusun mikroprosesor itu sendiri. Untuk memahami kerja dari bagian – bagian tersebut maka diperlukan
sarana yang dapat digunakan sebagai representasi dari mikroprosesor itu sendiri.
FPGA adalah salah satu sarana yang dapat digunakan untuk membuat representasi mikroprosesor tersebut.

1.2. Rumusan Masalah


1. Bagaimana cara membuat rangkaian – rangkaian logika pada FPGA ?
2. Bagaimana cara menyusun bagian – bagian mikroprosesor pada FPGA ?

1.3. Tujuan
1. Menerapkan rangkaian gerbang logika pada FPGA
2. Menggunakan rangkaian – rangkaian gerbang logika yang telah dibuat untuk membuat fungsi – fungsi pada
mikroprosesor
BAB II
HASIL DAN PEMBAHASAN

Secara garis besar akan dibahas hasil kerja dari tugas lab dari modul Xilinx dan pengaplikasian langsung pada
FPGA yang berupa decoder 7 segment dengan ROM dan komunikasi transmisi data melalui UART.
2.1. Lab 1.2.1 – MUX 2 – 1 Dengan Dataflow Modeling

Program Utama

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Mux21 is
Port (
x : in STD_LOGIC;
y : in STD_LOGIC;
s : in STD_LOGIC;
m : out STD_LOGIC
);
end Mux21;

architecture Behavioral of Mux21 is

begin
m <= (y and s) or (x and (not s));
end Behavioral;

2.2. Lab 1.2.2 – MUX 2 Bit 2-1 Dengan Dataflow Modeling

Program Utama

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Mux2bit is
Port ( x : in STD_LOGIC_VECTOR(1 downto 0);
y : in STD_LOGIC_VECTOR(1 downto 0);
m : out STD_LOGIC_VECTOR(1 downto 0);
s : in STD_LOGIC);
end Mux2bit;

architecture Behavioral of Mux2bit is

begin

m(0) <= (x(0) and s) or (y(0) and (not s));


m(1) <= (x(1) and s) or (y(1) and (not s));

end Behavioral;

Testbench

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Mux2bit_tb is
-- Port ( );
end Mux2bit_tb;

architecture Behavioral of Mux2bit_tb is


Component Mux2bit
port (
x : in STD_LOGIC_VECTOR(1 downto 0);
y : in STD_LOGIC_VECTOR(1 downto 0);
s : in STD_LOGIC;
m : out STD_LOGIC_VECTOR(1 downto 0)
);
End Component;

Signal m_int : STD_LOGIC_VECTOR(1 downto 0) := "00";


Signal s_int : STD_LOGIC := '0';
Signal x_int : STD_LOGIC_VECTOR(1 downto 0) := "00";
Signal y_int : STD_LOGIC_VECTOR(1 downto 0) := "00";

begin
uut: Mux2bit PORT MAP (
x => x_int,
y => y_int,
s => s_int,
m => m_int
);

process

begin
wait for 10 ns; x_int <= "01";s_int <= ‘1’;
wait for 10 ns; y_int <= "01";
wait for 10 ns; x_int <= "11"; y_int <= "00";
wait for 10 ns; x_int <= "10"; y_int <= "11";
wait for 10 ns; x_int <= "01";s_int <= ‘0’;
wait for 10 ns; x_int <= "01";
wait for 10 ns; x_int <= "01";
wait for 10 ns; x_int <= "01"; y_int <= "00";
wait for 10 ns; x_int <= "01"; y_int <= "11";
wait for 20 ns;

end process;
end Behavioral;

Pembahasan

Rangkaian yang di ekspresikan merupakan rangkaian multiplexer 2 ke 1 dengan masukan sebesar 2 bit
menggunakan Dataflow Modeling. Pada pelaksanaan simulasi, dilakukan beberapa perubahan masukan
dan selector dengan jeda 10 ns. Operasi fungsional dapat di lihat pada sebagian data analisis gelombang
yang di sertakan :
Catatan : untuk s_int bernilai 0, MUX akan memilih y_int untuk dilewatkan di jalur output (m_int)
sedangkan s_int bernilai 1, MUX akan memilih x_int untuk dilewatkan di jalur output.

2.3. Lab 1.3.1 – MUX 2 Bit 2 ke 1 Dengan Structural Modeling

Program Utama

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity and_gate is
Port ( a,b : in STD_LOGIC;
c : out STD_LOGIC);
end and_gate;

architecture and_op of and_gate is


begin
c <= a and b;
end and_op;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity not_gate is
Port ( a : in STD_LOGIC;
b : out STD_LOGIC
);
end not_gate;

architecture not_op of not_gate is


begin
b <= not a;
end not_op;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity or_gate is
Port ( a,b : in STD_LOGIC;
c : out STD_LOGIC);
end or_gate;

architecture or_op of or_gate is


begin
c <= a or b;
end or_op;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux2bit is
Port ( i0,i1,i2,i3,s : in STD_LOGIC;
m1,m2 : out STD_LOGIC);
end mux2bit;

architecture mux2bit_arch of mux2bit is


component and_gate
Port ( a,b : in STD_LOGIC;
c : out STD_LOGIC);
end component;

component or_gate
Port ( a,b : in STD_LOGIC;
c : out STD_LOGIC);
end component;

component not_gate
Port ( a : in STD_LOGIC;
b : out STD_LOGIC
);
end component;
signal out_and1, out_and2, out_and3, out_and4, not_out1, not_out2 : STD_LOGIC;

begin
and_one : and_gate port map(
a => i0,
b => s,
c => out_and1);
not_one : not_gate port map(
a => s,
b => not_out1
);
and_two : and_gate port map(
a => i1,
b => not_out1,
c => out_and2);
and_three : and_gate port map(
a => i2,
b => s,
c => out_and3);
not_two : not_gate port map(
a => s,
b => not_out2
);
and_four : and_gate port map(
a => i3,
b => not_out2,
c => out_and4);
or_opt1 : or_gate port map(
a => out_and1,
b => out_and2,
c => m1);
or_opt2 : or_gate port map(
a => out_and3,
b => out_and4,
c => m2);
end mux2bit_arch;

Testbench
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Struct_mux_tb is
-- Port ( );
end Struct_mux_tb;

architecture Behavioral of Struct_mux_tb is


Component mux2bit
Port ( i0,i1,i2,i3,s : in STD_LOGIC;
m1,m2 : out STD_LOGIC);
End Component;

Signal m_int : STD_LOGIC_VECTOR(1 downto 0) := "00";


Signal s_int : STD_LOGIC := '0';
Signal x_int : STD_LOGIC_VECTOR(1 downto 0) := "00";
Signal y_int : STD_LOGIC_VECTOR(1 downto 0) := "00";

begin
uut: mux2bit PORT MAP (
i0 => x_int(0),
i1 => y_int(0),
i2 => x_int(1),
i3 => y_int(1),
s => s_int,
m1 => m_int(0),
m2 => m_int(1)
);
process
begin
wait for 10 ns; x_int <= "01";s_int <= '0';
wait for 10 ns; y_int <= "01";
wait for 10 ns; x_int <= "11"; y_int <= "00";
wait for 10 ns; x_int <= "10"; y_int <= "11";
wait for 10 ns; x_int <= "01";s_int <= '1';
wait for 10 ns; x_int <= "01";
wait for 10 ns; x_int <= "01";
wait for 10 ns; x_int <= "01"; y_int <= "00";
wait for 10 ns; x_int <= "01"; y_int <= "11";
wait for 20 ns;
end process;
end Behavioral;

Pembahasan
Rangkaian yang dieskspresikan merupakan rangkaian MUX 2 Bit 2 ke 1 dengan Structural Modeling.
Komponen yang diinisialisasikan adalah gerbang AND, OR, dan NOT, kemudian dilakukan mapping pada
port sesuai rangkaian pada skema multiplexer tersebut. Testbench dibuat sama dengan Lab 1.2.2 dengan
beberapa penyesuaian mapping port, dan analisis gelombang yang didapat sama dengan analisis gelombang
pada lab 1.2.2 (rangkaian yang sama dengan modeling yang berbeda).
2.4. Lab 1.4.2 – MUX 2 Bit 2 ke 1 Dengan Behavioral Modeling

Program Utama
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux2bitwide is
-- Port ( );
Port (
x : in STD_LOGIC_VECTOR(1 downto 0);
y : in STD_LOGIC_VECTOR(1 downto 0);
s : in STD_LOGIC;
m : out STD_LOGIC_VECTOR(1 downto 0)
);
end mux2bitwide;
architecture Behavioral of mux2bitwide is
begin
process(x,y,s)
begin
case s is
when '1' => m(0) <= x(0);m(1) <= y(0);
when '0' => m(0) <= x(1);m(1) <= y(1);
end case;
end process;
end Behavioral;
Testbench
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Mux2bit_tb is
-- Port ( );
end Mux2bit_tb;

architecture Behavioral of Mux2bit_tb is


Component Mux2bit
port (
x : in STD_LOGIC_VECTOR(1 downto 0);
y : in STD_LOGIC_VECTOR(1 downto 0);
s : in STD_LOGIC;
m : out STD_LOGIC_VECTOR(1 downto 0)
);
End Component;

Signal m_int : STD_LOGIC_VECTOR(1 downto 0) := "00";


Signal s_int : STD_LOGIC := '0';
Signal x_int : STD_LOGIC_VECTOR(1 downto 0) := "00";
Signal y_int : STD_LOGIC_VECTOR(1 downto 0) := "00";

begin
uut: Mux2bit PORT MAP (
x => x_int,
y => y_int,
s => s_int,
m => m_int
);
process

begin
wait for 10 ns; x_int <= "01";s_int <= '0';
wait for 10 ns; y_int <= "01";
wait for 10 ns; x_int <= "11"; y_int <= "00";
wait for 10 ns; x_int <= "10"; y_int <= "11";
wait for 10 ns; x_int <= "01";s_int <= '1';
wait for 10 ns; x_int <= "01";
wait for 10 ns; x_int <= "01";
wait for 10 ns; x_int <= "01"; y_int <= "00";
wait for 10 ns; x_int <= "01"; y_int <= "11";
wait for 20 ns;

end process;
end Behavioral;

Pembahasan
Rangkaian yang diekspresikan adalah MUX 2 Bit 2 ke 1 dengan menggunakan Behavioral Modeling.
Testbench disamakan dengan dengan Lab 1.2.1. Terjadi perbedaan rangkaian skematik pada Behavioral
Modeling. Dimana ISE langsung mengenali rangkaian ini sebagai multiplexer 2 bit, sedangkan pada
Structural Modeling, skematik di reperesentasikan oleh gerbang – gerbang logika yang diinisialisasikan
sebagai komponennya.
2.5. Lab 2.1.1 – Menampilkan Bilangan Biner ke 7 Segment
Program Utama
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity numsys is
Port(
x : in STD_LOGIC_VECTOR(3 downto 0);
a : out STD_LOGIC;
b : out STD_LOGIC;
c : out STD_LOGIC;
d : out STD_LOGIC;
e : out STD_LOGIC;
f : out STD_LOGIC;
g : out STD_LOGIC
);
end numsys;

architecture Behavioral of numsys is


begin
process(x)
begin
case x is
when "0000" => a <= '0';b <= '0';c <= '0';d <= '0';e <= '0';f <= '0';g <= '1';
when "0001" => a <= '1';b <= '0';c <= '0';d <= '1';e <= '1';f <= '1';g <= '1';
when "0010" => a <= '0';b <= '0';c <= '1';d <= '0';e <= '0';f <= '1';g <= '0';
when "0011" => a <= '0';b <= '0';c <= '0';d <= '0';e <= '1';f <= '1';g <= '0';
when "0100" => a <= '1';b <= '0';c <= '0';d <= '1';e <= '1';f <= '0';g <= '0';
when "0101" => a <= '0';b <= '1';c <= '0';d <= '0';e <= '1';f <= '0';g <= '0';
when "0110" => a <= '0';b <= '1';c <= '0';d <= '0';e <= '0';f <= '0';g <= '0';
when "0111" => a <= '0';b <= '0';c <= '0';d <= '1';e <= '1';f <= '1';g <= '1';
when "1000" => a <= '0';b <= '0';c <= '0';d <= '0';e <= '0';f <= '0';g <= '0';
when "1001" => a <= '0';b <= '0';c <= '0';d <= '0';e <= '1';f <= '0';g <= '0';
when "1010" => a <= '0';b <= '0';c <= '0';d <= '1';e <= '0';f <= '0';g <= '0';
when "1011" => a <= '1';b <= '1';c <= '0';d <= '0';e <= '0';f <= '0';g <= '0';
when "1100" => a <= '1';b <= '1';c <= '1';d <= '0';e <= '0';f <= '1';g <= '0';
when "1101" => a <= '1';b <= '0';c <= '0';d <= '0';e <= '0';f <= '1';g <= '0';
when "1110" => a <= '0';b <= '1';c <= '1';d <= '0';e <= '0';f <= '0';g <= '0';
when "1111" => a <= '0';b <= '1';c <= '1';d <= '1';e <= '0';f <= '0';g <= '0';
end case;
end process;
end Behavioral;

Pembahasan
Pembahasan lebih lanjut ada pada bagian lain, dimana terdapat pengaplikasian langsung ke FPGA.
2.6. Lab 2.3.1
Program Utama
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity full_adder is
Port(
a,b : in STD_LOGIC;
cin : in STD_LOGIC;
cout,sum : out STD_LOGIC
);

end full_adder;

architecture Behavioral of full_adder is


begin

sum <= (a xor b) xor cin;


cout <= (a and b) or ((a xor b) and cin);
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity four_bit_fa is
Port(
a : in STD_LOGIC_VECTOR(3 downto 0);
b : in STD_LOGIC_VECTOR(3 downto 0);
cin : in STD_LOGIC;
sum : out STD_LOGIC_VECTOR(3 downto 0);
cout : out STD_LOGIC
);

end four_bit_fa;

architecture fa_behave of four_bit_fa is


signal c1,c2,c3 : STD_LOGIC:='0';
begin
FA1 : entity work.full_adder port map(
a => a(0),
b => b(0),
cin => cin,
cout => c1,
sum => sum(0)
);
FA2 : entity work.full_adder port map(
a => a(1),
b => b(1),
cin => c1,
cout => c2,
sum => sum(1)
);
FA3 : entity work.full_adder port map(
a => a(2),
b => b(2),
cin => c2,
cout => c3,
sum => sum(2)
);
FA4 : entity work.full_adder port map(
a => a(3),
b => b(3),
cin => c3,
cout => cout,
sum => sum(3)
);

end;

Testbench

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity FA_tb is
-- Port ( );
end FA_tb;

architecture Behavioral of FA_tb is


component four_bit_fa
Port(
a : in STD_LOGIC_VECTOR(3 downto 0);
b : in STD_LOGIC_VECTOR(3 downto 0);
cin : in STD_LOGIC;
sum : out STD_LOGIC_VECTOR(3 downto 0);
cout : out STD_LOGIC
);
end component;
signal a_int,b_int,sum_int : STD_LOGIC_VECTOR(3 downto 0);
signal cin_int : STD_LOGIC;
signal cout_int : STD_LOGIC;

begin
uut : four_bit_fa port map(
a => a_int,
b => b_int,
cin => cin_int,
cout => cout_int,
sum => sum_int
);

process
begin
cin_int <= '0';
wait for 10 ns;a_int <= "0000";b_int <= "1111";
wait for 10 ns;a_int <= "0011";b_int <= "0011";
wait for 10 ns;a_int <= "0101";b_int <= "0111";
wait for 10 ns;a_int <= "0001";b_int <= "1011";
wait for 10 ns;a_int <= "0111";b_int <= "1011";
end process;
end Behavioral;
Pembahasan
Lab 2.3.1 membahas tentang rangkaian Full adder 4 bit. Pemrograman menggunakan Structural Modeling
dengan menginisialisasikan rangkaian full adder 1 bit. Rangkaian full adder 1 bit diekspresikan dengan
dataflow modeling. Testbench melakukan tes dengan memberikan masukan cin awal adalah 0, dan
masukan bervariasi yaitu 0000 dan 1111, 0011 dan 0011, 0101 dan 0111, 0001 dan 1011, serta 0111 dan
1011. Pada analisis gelombang menunjukkan hasil yang sesuai dengan hasil penjumlahan masukan
tersebut.
2.7. Lab 3.3.1 – Desain Komparator + ROM
Program Utama

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity comp_2bit is
Port(
a : in std_logic_vector(1 downto 0);
b : in std_logic_vector(1 downto 0);
lt : out std_logic;
eq : out std_logic;
gt : out std_logic
);

end comp_2bit;

architecture Behavioral of comp_2bit is


begin
lt <= ((not a(1)) and (not a(0)) and b(0)) or ((not a(1)) and b(1)) or ((not a(0)) and b(1) and b(0));
eq <= ((not a(1)) and (not a(0)) and (not b(1)) and (not b(0))) or ((not a(1)) and a(0) and (not b(1)) and
b(0)) or (a(1) and (not a(0)) and b(1) and (not b(0))) or (a(0) and a(1) and b(0) and b(1));
gt <= (a(1) and (b(0) nor b(1))) or ((a(0) and a(1)) and (not b(1))) or (a(0) and (not b(0)));
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity ROM_3x2 is
Port(
addr : in std_logic_vector(2 downto 0);
o : out std_logic_vector(1 downto 0)
);

end ROM_3x2;

architecture ROM of ROM_3x2 is


type rom is array (0 to 3) of std_logic_vector(1 downto 0);
constant ROM_3x2 : rom := (
0 => "00",
1 => "01",
2 => "10",
3 => "11"
);

begin
process(addr)
begin
case addr is
when "000" => o <= ROM_3x2(0);
when "001" => o <= ROM_3x2(1);
when "010" => o <= ROM_3x2(2);
when "100" => o <= ROM_3x2(3);
when others => o <= ROM_3x2(0);
end case;
end process;
end ROM;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity ROM_COMP is
Port(
a,b : in std_logic_vector(1 downto 0);
otp : out std_logic_vector(1 downto 0)
);
end ROM_COMP;

architecture OP of ROM_COMP is
component comp_2bit is
Port(
a : in std_logic_vector(1 downto 0);
b : in std_logic_vector(1 downto 0);
lt : out std_logic;
eq : out std_logic;
gt : out std_logic
);
end component;

component ROM_3x2 is
Port(
addr : in std_logic_vector(2 downto 0);
o : out std_logic_vector(1 downto 0)
);
end component;
signal less,equal,greater : std_logic;
begin
COMPAR : comp_2bit port map(
a => a,
b => b,
lt => less,
eq => equal,
gt => greater
);
ROMCOMP : ROM_3x2 port map(
addr(0) => less,
addr(1) => equal,
addr(2) => greater,
o => otp
);
end OP;

Testbench

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ROM_COMP_tb is
-- Port ( );
end ROM_COMP_tb;

architecture Behavioral of ROM_COMP_tb is


component ROM_COMP
Port(
a,b : in std_logic_vector(1 downto 0);
otp : out std_logic_vector(1 downto 0)
);
end component;
signal a,b,otp : STD_LOGIC_VECTOR(1 downto 0);

begin
uut : ROM_COMP Port Map(
a => a,
b => b,
otp => otp
);

process
begin
wait for 10 ns;a <= "11";b <= "00";
wait for 10 ns;a <= "10";b <= "11";
wait for 10 ns;a <= "01";b <= "01";
end process;
end Behavioral;

Pembahasan
Desain komparator menggunakan Dataflow Modeling. Terdapat 3 keluaran komparator, lt (a lebih kecil
dari b), eq (a sama dengan b), gt (a lebih besar dari b). keluaran dari komparator akan dihubungkan ke port
alamat ROM 3x2 yang akan memiliki keluaran sesuai dengan alamat input ROM. lt (sebagai LSB) dan gt
(sebagai MSB) bit alamat. ROM akan meng-ouputkan nilai 00 untuk alamat yang tidak terdefinisi, nilai 01
untuk a kurang dari b, 10 untuk a sama dengan b, dan 11 untuk 1 lebih besar dari b. Testbench berisi
masukan yang bertujuan untuk mengecek 3 kemungkinan keluaran, lebih kecil, lebih besar, dan sama
dengan.
2.8 . Lab 3.3.1 – Desain Komparator + ROM
Program Utama
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity SR_latch is
Port(
r,s : in std_logic;
q,qbar : inout std_logic
);
end SR_latch;

architecture Behavioral of SR_latch is


begin
q <= qbar nor r;
qbar <= q nor s;

end Behavioral;

Testbench

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity SR_latch_tb is
end SR_latch_tb;

architecture Behavioral of SR_latch_tb is


component SR_latch
Port(
r,s : in std_logic;
q,qbar : inout std_logic
);
end component;
signal s_val,r_val,q_out,qbar_out : std_logic := '0';
begin
wew : SR_latch port map(
r => r_val,
s => s_val,
q => q_out,
qbar => qbar_out
);

process
begin
r_val <= '0';s_val <= '0';
wait for 10 ns;r_val <= '0';s_val <= '1';
wait for 10 ns;s_val <= '0';
wait for 10 ns;r_val <= '1';
wait for 10 ns;r_val <= '0';s_val <= '1';
wait for 10 ns;r_val <= '1';s_val <= '0';
wait for 10 ns;r_val <= '0';s_val <= '1';
wait for 10 ns;r_val <= '1';s_val <= '0';
-- wait for 10 ns;r_val <= '1';s_val <= '1';
wait for 20 ns;
end process;

end Behavioral;

Pembahasan
Desain dari rangkaian SR Latch dibuat dengan Dataflow Modeling. Testbench menguji kemungkinan –
kemungkinan yang diambil dari truth table SR Latch.

2.9 . Lab 5.2.1 – D Flip Flop


Program Utama

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity D_Flip_Flop is
Port(
D,clk : in std_logic;
Q : out std_logic
);
end D_Flip_Flop;

architecture Behavioral of D_Flip_Flop is


begin
process (clk)
begin
if rising_edge (clk) then
Q <= D;
end if;
end process;
end Behavioral;

Testbench

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity D_Flip_Flop_tb is
end D_Flip_Flop_tb;

architecture Behavioral of D_Flip_Flop_tb is


component d_flip_flop
Port(
D,clk : in std_logic;
Q : out std_logic
);
end component;
signal D_in,clk_in,Q_out : std_logic := '0';
begin
uvvuvwevve : d_flip_flop port map(
D => D_in,
clk => clk_in,
Q => Q_out
);

process
begin
wait for 10 ns;clk_in <= '1';d_in <= '0';
wait for 10 ns;clk_in <= '0';
wait for 10 ns;clk_in <= '1';d_in <= '1';
wait for 10 ns;clk_in <= '0';
wait for 10 ns;clk_in <= '1';
wait for 10 ns;clk_in <= '0';d_in <= '0';
wait for 10 ns;clk_in <= '1';
wait for 10 ns;clk_in <= '0';
wait for 10 ns;clk_in <= '1';d_in <= '1';
wait for 10 ns;clk_in <= '0';
wait for 10 ns;clk_in <= '1';
wait for 10 ns;clk_in <= '0';d_in <= '0';
wait for 10 ns;clk_in <= '1';
wait for 10 ns;clk_in <= '0';
wait for 10 ns;clk_in <= '1';d_in <= '0';
wait for 10 ns;clk_in <= '0';
end process;
end Behavioral;

Pembahasan
Desain D flip flop menggunakan Behavioral Modeling karena D flip flop hanya akan aktif ketika tepi naik
dari clk (clock). Testbench didesain untuk menyamakan gelombang di modul Lab Xilinx. Clock yang
digunakan memiliki periode 20 ns.
2.10 . Lab 6.1.1 – Synchronous Register 4 Bit
Program Utama
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity sync_reg_4bit is
Port(
D : in std_logic_vector(3 downto 0);
Q : out std_logic_vector(3 downto 0);
load,reset,clk : in std_logic
);
end sync_reg_4bit;

architecture Behavioral of sync_reg_4bit is


begin
Process(clk)
begin
if rising_edge(clk) then
if (reset = '1') then
Q <= "0000";
elsif (load = '1') then
Q <= D;
end if;
end if;
end Process;
end Behavioral;

Testbench
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity sync_reg_4bit_tb is
end sync_reg_4bit_tb;

architecture Behavioral of sync_reg_4bit_tb is


Component sync_reg_4bit
Port(
D : in std_logic_vector(3 downto 0);
Q : out std_logic_vector(3 downto 0);
load,reset,clk : in std_logic
);
end Component;

Signal Di,Qo : std_logic_vector(3 downto 0);


Signal reset1, load1, clk1 : std_logic := '0';
begin
tes_wew : sync_reg_4bit port map(
D => Di,
Q => Qo,
clk => clk1,
reset => reset1,
load => load1
);
Process
Begin
wait for 10 ns;clk1 <= '1';reset1 <= '0';Di <= "1111";load1 <= '0';
wait for 10 ns;clk1 <= '0';
wait for 10 ns;clk1 <= '1';load1 <= '1';
wait for 10 ns;clk1 <= '0';
wait for 10 ns;clk1 <= '1';Di <= "0011";load1 <= '0';
wait for 10 ns;clk1 <= '0';
wait for 10 ns;clk1 <= '1';load1 <= '1';
wait for 10 ns;clk1 <= '0';Di <= "0111";
wait for 10 ns;clk1 <= '1';
wait for 10 ns;clk1 <= '0';
wait for 10 ns;clk1 <= '1';
wait for 10 ns;clk1 <= '0';load1 <= '0';
wait for 10 ns;clk1 <= '1';
wait for 10 ns;clk1 <= '0';Di <= "1001";
wait for 10 ns;clk1 <= '1';load1 <= '1';
wait for 10 ns;clk1 <= '0';reset1 <= '1';
end Process;
end Behavioral;

Pembahasan
Synchronous register 4 bit ini didesain dengan Behavioral Modeling, karena dibutuhkan operasi yang
siinkron terhadap tepi naik clock. Register akan aktif hanya ketika masukan Load bernilai ‘1’ dan non-
aktif ketika masukan Load ‘0’, dan ketika reset bernilai ‘1’ register akan berisi keadaan default ( “0000”).
Testbench yang digunakan untuk melakukan simulasi memiliki clock dengan periode 20 ns dan melakukan
percobaan dengan beberapa kemungkinan.
2.11 . Lab 10.1.1 – Finite State Machine
Program Utama
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity FSM is
Port(
fsm_in, reset_fsm, clk_in : in STD_LOGIC;
fsm_out : out STD_LOGIC
);
end FSM;

architecture Behavioral of FSM is


type state is (reset, count);
type fsm is (S0,S1,S2);
signal fsm_state : fsm := S0;
signal status : state := count;
signal count_fsm : integer range 0 to 2 := 0;
begin
process (clk_in)
begin
if rising_edge(clk_in) then
fsm_out <= '0';
if reset_fsm = '1' then
status <= reset;
else status <= count;
end if;
case status is
when reset =>
count_fsm <= 0;
when count =>
case fsm_state is
when S0 =>
if fsm_in = '1' then
fsm_state <= S1;
count_fsm <= count_fsm +1;
else fsm_state <= S0;
end if;
when S1 =>
if fsm_in = '1' then
fsm_state <= S2;
count_fsm <= count_fsm + 1;
else fsm_state <= S0;
end if;
when S2 =>
if fsm_in = '1' then
fsm_state <= S1;
fsm_out <= '1';
else fsm_state <= S0;
end if;
end case;
end case;
end if;

end process;
end Behavioral;
Testbench
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity fsm_tb is
-- Port ( );
end fsm_tb;

architecture Behavioral of fsm_tb is


component FSM Port(
fsm_in, reset_fsm, clk_in : in STD_LOGIC;
fsm_out : out STD_LOGIC
);
end component;
signal in_sig, clk_sig, reset_sig, out_sig : STD_LOGIC := '0';

begin
tes : FSM port map(
fsm_in => in_sig,
reset_fsm => reset_sig,
clk_in => clk_sig,
fsm_out => out_Sig
);

process
begin
wait for 10 ns;clk_sig <= '1';
wait for 10 ns;clk_sig <= '0';
wait for 10 ns;clk_sig <= '1';
wait for 10 ns;clk_sig <= '0';in_sig <= '1';
wait for 10 ns;clk_sig <= '1';
wait for 10 ns;clk_sig <= '0';
wait for 10 ns;clk_sig <= '1';
wait for 10 ns;clk_sig <= '0';
wait for 10 ns;clk_sig <= '1';
wait for 10 ns;clk_sig <= '0';
wait for 10 ns;clk_sig <= '1';
wait for 10 ns;clk_sig <= '0';in_sig <= '0';
wait for 10 ns;clk_sig <= '1';
wait for 10 ns;clk_sig <= '0';
wait for 10 ns;clk_sig <= '1';
wait for 10 ns;clk_sig <= '0';in_sig <= '1';reset_sig <= '1';
wait for 10 ns;clk_sig <= '1';
wait for 10 ns;clk_sig <= '0';
wait for 10 ns;clk_sig <= '1';
wait for 10 ns;clk_sig <= '0';reset_sig <= '0';
wait for 10 ns;clk_sig <= '1';
wait for 10 ns;clk_sig <= '0';
wait for 10 ns;clk_sig <= '1';
wait for 10 ns;clk_sig <= '0';
wait for 10 ns;clk_sig <= '1';
wait for 10 ns;clk_sig <= '0';in_sig <= '0';
wait for 10 ns;clk_sig <= '1';
wait for 10 ns;clk_sig <= '0';
end process;
end Behavioral;
Pembahasan
Finite state machine ini digunakan untuk mendeteksi urutan bit. Ketika jumlah bit yang masuk dapat
dibagi dengan 3, maka output akan bernilai ‘1’. FSM menggunakan model moore. Kebenaran dari desain
FSM ini dapat dilihat pada analisis gelombang yang disertakan.
2.12 . Pengaplikasian Decoder 7 Segment dengan ROM pada FPGA (ISE DESIGN SUITE)
Program Utama
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity ROM_7SEG is
Port(
addr : in std_logic_vector(7 downto 0);
output : out std_logic_vector(3 downto 0)
);
end ROM_7SEG;

architecture ROM of ROM_7SEG is


type rom is array (0 to 10) of std_logic_vector(3 downto 0);
constant ROM_7SEG : rom := (
0 => "0000",
1 => "0001",
2 => "0010",
3 => "0011",
4 => "0100",
5 => "0101",
6 => "0110",
7 => "0111",
8 => "1000",
9 => "1001",
10 => "1111"
);
begin
process(addr)
begin
case addr is
when "00000000" => output <= ROM_7SEG(0);
when "00000001" => output <= ROM_7SEG(1);
when "00000010" => output <= ROM_7SEG(2);
when "00000100" => output <= ROM_7SEG(3);
when "00001000" => output <= ROM_7SEG(4);
when "00010000" => output <= ROM_7SEG(5);
when "00100000" => output <= ROM_7SEG(6);
when "01000000" => output <= ROM_7SEG(7);
when "10000000" => output <= ROM_7SEG(8);
when "11000000" => output <= ROM_7SEG(9);
when others => output <= ROM_7SEG(10);
end case;
end process;
end ROM;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Seven_seg is
port(
data_in : in std_logic_vector(3 downto 0);
sel : out std_logic_vector(3 downto 0);
seg_a : out std_logic;
seg_b : out std_logic;
seg_c : out std_logic;
seg_d : out std_logic;
seg_e : out std_logic;
seg_f : out std_logic;
seg_g : out std_logic
);

end Seven_seg;

architecture Behavioral of Seven_seg is


begin
process(data_in)
variable decoded : std_logic_vector(6 downto 0);
begin
case data_in is
when "0000" => decoded := "0000001";
when "0001" => decoded := "1001111";
when "0010" => decoded := "0010010";
when "0011" => decoded := "0000110";
when "0100" => decoded := "1001100";
when "0101" => decoded := "0100100";
when "0110" => decoded := "0100000";
when "0111" => decoded := "0001111";
when "1000" => decoded := "0000000";
when "1001" => decoded := "0000100";
when others => decoded := "1111110";
end case;
sel(0) <= '1';
sel(1) <= '1';
sel(2) <= '1';
sel(3) <= '0';
seg_a <= decoded(6);
seg_b <= decoded(5);
seg_c <= decoded(4);
seg_d <= decoded(3);
seg_e <= decoded(2);
seg_f <= decoded(1);
seg_g <= decoded(0);
end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity complete is
Port(
inputs : in std_logic_vector(7 downto 0);
outputs : out std_logic_vector(6 downto 0);
selects : out std_logic_vector(3 downto 0)
);

end complete;

architecture parts of complete is

component ROM_7SEG is
Port(
addr : in std_logic_vector(7 downto 0);
output : out std_logic_vector(3 downto 0)
);
end component;

component Seven_seg is
port(
data_in : in std_logic_vector(3 downto 0);
sel : out std_logic_vector(3 downto 0);
seg_a : out std_logic;
seg_b : out std_logic;
seg_c : out std_logic;
seg_d : out std_logic;
seg_e : out std_logic;
seg_f : out std_logic;
seg_g : out std_logic
);
end component;
Signal ROM_OUT : std_logic_vector(3 downto 0);
Begin
ROM : ROM_7SEG port map(
addr(0) => inputs(0),
addr(1) => inputs(1),
addr(2) => inputs(2),
addr(3) => inputs(3),
addr(4) => inputs(4),
addr(5) => inputs(5),
addr(6) => inputs(6),
addr(7) => inputs(7),
output(0) => ROM_OUT(0),
output(1) => ROM_OUT(1),
output(2) => ROM_OUT(2),
output(3) => ROM_OUT(3)
);

SEVSEG : Seven_seg port map(


data_in(0) => ROM_OUT(0),
data_in(1) => ROM_OUT(1),
data_in(2) => ROM_OUT(2),
data_in(3) => ROM_OUT(3),
sel(0) => selects(0),
sel(1) => selects(1),
sel(2) => selects(2),
sel(3) => selects(3),
seg_a => outputs(0),
seg_b => outputs(1),
seg_c => outputs(2),
seg_d => outputs(3),
seg_e => outputs(4),
seg_f => outputs(5),
seg_g => outputs(6)
);
end parts;

UCF
net "inputs(0)" loc = g18;
net "inputs(1)" loc = h18;
net "inputs(2)" loc = k18;
net "inputs(3)" loc = k17;
net "inputs(4)" loc = l14;
net "inputs(5)" loc = l13;
net "inputs(6)" loc = n17;
net "inputs(7)" loc = r17;

net "selects(0)" loc = f15;


net "selects(1)" loc = c18;
net "selects(2)" loc = h17;
net "selects(3)" loc = f17;

net "outputs(0)" loc = L18;


net "outputs(1)" loc = f18;
net "outputs(2)" loc = d17;
net "outputs(3)" loc = d16;
net "outputs(4)" loc = g14;
net "outputs(5)" loc = j17;
net "outputs(6)" loc = h14;

Pembahasan
ROM yang digunakan berukuran 11x4 yang difungsikan sebagai pengubah masukan diskrit ke kode 4 bit
yang nantinya akan masuk ke decoder seven segment dan ditampilkan di display seven segment.
2.13 . Pengaplikasian Komunikasi UART pada FPGA (ISE DESIGN SUITE)
Testbench
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY UART_tb IS
END UART_tb;

ARCHITECTURE behavior OF UART_tb IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT UART_TX
PORT(
in_CLK : IN std_logic;
BT_start : IN std_logic;
in_TX_Byte : IN std_logic_vector(7 downto 0);
out_TX_Active : OUT std_logic;
out_TX_Serial : OUT std_logic;
out_TX_Finished : OUT std_logic
);
END COMPONENT;

--Inputs
signal in_CLK : std_logic := '0';
signal BT_start : std_logic := '0';
signal in_TX_Byte : std_logic_vector(7 downto 0) := (others => '0');

--Outputs
signal out_TX_Active : std_logic;
signal out_TX_Serial : std_logic;
signal out_TX_Finished : std_logic;
-- Clock period definitions
constant in_CLK_period : time := 10 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)


uut: UART_TX PORT MAP (
in_CLK => in_CLK,
BT_start => BT_start,
in_TX_Byte => in_TX_Byte,
out_TX_Active => out_TX_Active,
out_TX_Serial => out_TX_Serial,
out_TX_Finished => out_TX_Finished
);

-- Clock process definitions


in_CLK_process :process
begin
in_CLK <= '0';
wait for in_CLK_period/2;
in_CLK <= '1';
wait for in_CLK_period/2;
end process;

-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;

wait for in_CLK_period*10;


-- insert stimulus here
in_TX_Byte <= "10101011";wait for 10 ns;
BT_Start <= '1';

wait;
end process;

END;

Program Utama
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
-- CLK_BAUD = CLK/BAUDRATE 50000000/115200 = 434

entity UART_TX is
generic (CLK_BAUD : integer := 434
);
port (
in_CLK : in std_logic;
BT_start : in std_logic;
in_TX_Byte : in std_logic_vector(7 downto 0);
out_TX_Active : out std_Logic; -- Untuk tanda LED
out_TX_Serial : out std_logic;
out_TX_Finished : out std_Logic -- Untuk tanda LED
);
end UART_TX;

architecture OP of UART_TX is

type TRIG_MAIN is (idle_SIG, TX_Start_Bit, TX_Data_Bits,


TX_Stop_Bit, Cleanup_SIG);
signal TRIG_UART : TRIG_MAIN := idle_SIG;
signal CLK_Count : integer range 0 to CLK_BAUD - 1 := 0;
signal INDEX_BIT : integer range 0 to 7 := 0;
signal BYTE_TX : std_logic_vector(7 downto 0) := (others => '0');
signal TX_Finished : std_logic := '0';

begin

Transmit : process(in_CLK)
begin
if rising_edge(in_CLK) then
case TRIG_UART is
when idle_SIG =>
out_TX_Active <= '0';
out_TX_Serial <= '1';
TX_FInished <= '0';
CLK_COUNT <= 0;
INDEX_BIT <= 0;

if BT_start = '1' then


BYTE_TX <= in_TX_Byte;
TRIG_UART <= TX_start_Bit;
else
TRIG_UART <= idle_SIG;
end if;

when TX_Start_Bit =>


out_TX_Active <= '1';
out_TX_Serial <= '0';
if CLK_Count < CLK_BAUD - 1 then
CLK_Count <= CLK_Count + 1;
TRIG_UART <= TX_Start_Bit;
else
CLK_Count <= 0;
TRIG_UART <= TX_Data_Bits;
end if;

when TX_Data_Bits =>


out_TX_Serial <= BYTE_TX(INDEX_BIT);
if CLK_Count < CLK_BAUD - 1 then
TRIG_UART <= TX_Data_Bits;
CLK_Count <= CLK_Count + 1;
else
CLK_Count <= 0;
if INDEX_BIT < 7 then
INDEX_BIT <= INDEX_BIT + 1;
else
INDEX_BIT <= 0;
TRIG_UART <= TX_Stop_Bit;
end if;
end if;

when TX_Stop_Bit =>


out_TX_Serial <= '1';
if CLK_Count < CLK_BAUD - 1 then
CLK_Count <= CLK_Count + 1;
TRIG_UART <= TX_Stop_Bit;
else
CLK_Count <= 0;
TRIG_UART <= Cleanup_SIG;
TX_Finished <= '1';
end if;

when Cleanup_SIG =>


out_TX_Active <= '1';
TX_Finished <= '1';
TRIG_UART <= idle_SIG;

when others =>


TRIG_UART <= idle_SIG;

end case;
end if;
end process;
out_TX_Finished <= TX_Finished;
end OP;

Pembahasan
Komunikasi UART menggunakan BAUDRATE 115200. Rancangan ini menggunakan sebuah counter
yang akan mencacah hingga (CLK/BAUDRATE)-1, dalam hal ini dengan CLK adalah 50 Mhz dan
BAUDRATE 115200 menghasilkan nilai pencacah 434, yang berarti setiap data akan mendapatkan lebar
434 clock. Didefinisikan 6 keadaan, yaitu idle ketika keadaan tidak ada transmisi data, start bit untuk
memberikan sinyal start pada serial, data bits untuk transmisi data per bit, stop bit untuk memberikan
sinyal bahwa seluruh data sudah terkirim pada jalur serial, cleanup unutk memberikan jeda dan sebagai
pengaman agar transmisi benar – benar tidak ada yang berjalan, serta others untuk hal yang tidak
terdefinisi dan membuat serial tetap idle. Pengiriman data hanya akan terjadi ketika ada pemicuan pada
tombol yang ditentukan. Pengiriman data dilalkukan dari LSB ke MSB. Testbench pada ISE di generate
otomatis, berbeda dengan Vivado yang harus di inisialisasikan manual. Belum di tes menggunakan FPGA
karena tidak adanya konverter RS232 ke USB.
BAB IV
KESIMPULAN DAN SARAN

4.1. Kesimpulan
Dari beberapa percobaan yang telah dilakukan, segalanya memberikan gambaran
yang cukup jelas tentang bagaimana berbagai fungsi dapat berjalan pada suatu
mikroprosesor.

4.2. Saran
Dari beberapa percobaan yang telah dilakukan, akan lebih baik jika melakukan tes
lebih intensif dan melengkapi beberapa bagian yang belum dilakukan.