NOTE: When ordering, use the entire part number. Add the suffix 9A to
obtain the TO-263AB variant in the tape and reel, i.e., RF1S630SM9A. S
Packaging
JEDEC TO-220AB JEDEC TO-263AB
SOURCE
DRAIN
GATE
DRAIN
(FLANGE)
DRAIN (FLANGE) GATE
SOURCE
4-202 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
IRF630, RF1S630SM
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TJ = 25oC to 125oC.
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IRF630, RF1S630SM
S
Source to Drain Diode Voltage (Note 2) VSD TJ = 25oC, ISD = 9A, VGS = 0V (Figure 13) - - 2 V
Reverse Recovery Time trr TJ = 150oC, ISD = 9A, dISD/dt = 100A/µs - 450 - ns
Reverse Recovery Charge QRR TJ = 150oC, ISD = 9A, dISD/dt = 100A/µs - 3 - µC
NOTES:
2. Pulse Test: Pulse width ≤ 300µs, Duty Cycle ≤ 2%.
3. Repetitive rating: Pulse width limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3).
4. VDD = 20V, starting TJ = 25oC, L = 3.37mH, RG = 50Ω, peak IAS = 9A.
1.2 10
POWER DISSIPATION MULTIPLIER
1.0
8
ID, DRAIN CURRENT (A)
0.8
6
0.6
4
0.4
2
0.2
0 0
0 50 100 150 25 50 75 100 125 150
TC, CASE TEMPERATURE (oC) TC, CASE TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
TEMPERATURE CASE TEMPERATURE
1.0
ZθJC, NORMALIZED TRANSIENT
THERMAL IMPEDANCE
0.5
0.2
0.1 PDM
0.1 0.05
0.02
0.01 t1
SINGLE PULSE t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC RθJC + TC
0.01
10-5 10-4 10-3 10-2 10-1 1 10
t1, RECTANGULAR PULSE DURATION (s)
4-204
IRF630, RF1S630SM
100
20
VGS = 10V PULSE DURATION = 80µs
VGS = 8V DUTY CYCLE = 0.5% MAX
16
ID, DRAIN CURRENT (A)
OPERATION IN THIS 8
1 AREA MAY BE 10ms
LIMITED BY rDS(ON) 100ms VGS = 5V
DC 4
TJ = MAX RATED
VGS = 4V
TC = 25oC
0.1 0
1 10 100 1000 0 20 40 60 80 100
VDS, DRAIN TO SOURCE VOLTAGE (V)
VDS, DRAIN TO SOURCE VOLTAGE (V)
10 10
PULSE DURATION = 80µs PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX VGS = 10V DUTY CYCLE = 0.5% MAX
VDS > ID(ON) x rDS(ON)MAX
8 VGS = 9V ID, DRAIN CURRENT (A) 8
ID, DRAIN CURRENT (A)
VGS = 8V
VGS = 7V
6 VGS = 6V 6
125oC
VGS = 5V
4 4 25oC
-55oC
2 2
VGS = 4V
0 0
0 1 2 3 4 5 0 1 2 3 4 5 6 7
VDS, DRAIN TO SOURCE VOLTAGE (V) VGS, GATE TO SOURCE VOLTAGE (V)
0.8 2.2
2µs PULSE TEST PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
NORMALIZED DRAIN TO SOURCE
1.8
0.6
ON RESISTANCE
ON RESISTANCE
1.4
0.4
1
VGS = 20V
0.2
0.6
0 0.2
0 10 20 30 40 -40 0 40 80 120
ID, DRAIN CURRENT (A) TJ , JUNCTION TEMPERATURE (oC)
4-205
IRF630, RF1S630SM
1.25 2000
VGS = 0V, f = 1MHz
ID = 250µA
NORMALIZED DRAIN TO SOURCE
C, CAPACITANCE (pF)
1.05 1200
0.95 800
CISS
0.85 400
COSS
CRSS
0.75 0
-40 0 40 80 120 160 1 10 20 30 40 50
TJ , JUNCTION TEMPERATURE (oC) VDS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
VOLTAGE vs JUNCTION TEMPERATURE
6 55oC
25oC 150oC
10
4 25oC
125oC
0
1
0 2 4 6 8 10 0 1 2 3 4
ID , DRAIN CURRENT (A) VSD, SOURCE TO DRAIN VOLTAGE (V)
FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE
20
ID = 9A
VGS, GATE TO SOURCE VOLTAGE (V)
VDS = 40V
15 V20
DS = 100V
10 VDS = 160V
IRF630, IRF632
0
0 8 16 24 32 40
Qg, GATE CHARGE (nC)
4-206
IRF630, RF1S630SM
VDS
BVDSS
L tP
VDS
tP
0V IAS
0
0.01Ω
tAV
FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS
tON tOFF
td(ON) td(OFF)
tr tf
RL VDS
90% 90%
+
VDD 10% 10%
RG
- 0
DUT 90%
FIGURE 17. SWITCHING TIME TEST CIRCUIT FIGURE 18. RESISTIVE SWITCHING WAVEFORMS
VDS
CURRENT (ISOLATED
REGULATOR SUPPLY)
VDD
D
VDS
G DUT
0
Ig(REF) S
0
VDS IG(REF)
IG CURRENT ID CURRENT
SAMPLING SAMPLING
RESISTOR RESISTOR 0
FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORMS
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IRF630, RF1S630SM
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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