REPORT

Phase Frequency Detector

(In Cadence Virtuoso)

BY-
Suhal S Shetty
Raghavendra M Balekundri
Akshay R

Under the guidance of:

Mr.Pavan, Mr.Santosh, Mr.Sunil
(KarMic Internship /Training)

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 Abstract

Phase Frequency Detector (PFD) plays a crucial role and an essential part in Phase Locked
Loop (PLL). PFD has an advantageous function over the Phase Detector (PD) and Frequency
Detector (FD) by detecting phase and frequency detection at a time. PFD compares the
phase difference between the input reference signal and the output signal from voltage
controlled oscillator (VCO). Generation of Up and Down clock signals depend upon phase
and frequency deviation. The key factor is to observe the dead zone problem in various PFD
structures.

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 CONTENTS

1. Introduction …………………….…. 4
2. MOSFET …………………….…. 6
3. Terminologies …………………….…. 7
4. Creating symbol …………………….…. 8
5. Creating Schematic …………………….…. 9
6. Creating layout …………………….…. 10
7. DRC run …………………….…. 12
8. LVS run …………………….…. 12
9. Simulation steps …………………….…. 13

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I. INTRODUCTION

Phase Locked Loop (PLL) is a closed loop negative feedback control system that generates a
signal that has a fixed relation to the phase of a "reference" signal [1]. A PLL circuit responds
to the input signals considering both phase and frequency. It automatically raises or lowers
the frequency of a voltage controlled oscillator until it is matched to the reference in both
frequency and phase. Capability of a PLL is used to track the phase changes that falls within
the bandwidth. It consists of a PFD, a charge pump (CP), a loop filter (LF), and a VCO, whose
output is fed back to the PFD which is illustrated in Fig-1.PFD compares the reference input
and clock output and generate the phase difference signal as Up and Down signals. The
Charge pump converts those signals from PFD into current. Loop filter is used for filtering
out the pulses generated by the charge pump to limit frequency jumps. It is also used to
allow necessary DC signals into the VCO and also store the charges from the CP. VCO
synthesizes the different output frequencies by changing its input frequency. The output of
loop filter is taken as controlled voltage for VCO. As the phase difference critically affects
the overall characteristics of the PLL such as lock-in time and jitter performance, the PFD
should be designed to work accurately for any phase difference. Due to lots of reasons such
as circuit mismatch and delay mismatch, the PFD has a difficulty in detecting such a small
difference. The PFD doesn’t detect the phase error when it is within dead zone region, then
PLL locks

The present work focuses on the redesign of a PFD system using the 180 nm
process technology (GPDK180 library) in CADENCE Virtuoso Analog Design Environment. The
layout structure of the PFD is drawn in CADENCE VirtuosoXL Layout editor.

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It compares the phase and frequency difference between the reference clock and the
feedback clock. Depending upon the phase and frequency deviation, it generates two
output signals “UP” and “DOWN”. Figure 2.3 shows a traditional PFD circuit. If there is a
phase difference between the two signals, it will generate “UP” or “DOWN” synchronized
signals. When the reference clock rising edge leads the feedback input clock rising edge
“UP” signal goes high while keeping “DOWN” signal low. On the other hand, if the feedback
input clock rising edge leads the reference clock rising edge “DOWN” signal goes high and
“UP” signal goes low. Fast phase and frequency acquisition PFDs [6-7] are generally

preferred over traditional PFD.

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MOSFET (BUILDING BLOCK): The MOSFET (Metal Oxide Semiconductor Field Effect
Transistor) transistor is a semiconductor device which is widely used for switching and
amplifying electronic signals in the electronic devices. The MOSFET is a core of integrated
circuit and it can be designed and fabricated in a single chip because of these very small
sizes. The MOSFET is a four terminal device with source(S), gate (G), drain (D) and body (B)
terminals. The body of the MOSFET is frequently connected to the source terminal so
making it a three terminal device like field effect transistor. The MOSFET is very far the most
common transistor and can be used in both analog and digital circuits. The MOSFET works
by electronically varying the width of a channel along which charge carriers flow (electrons
or holes). The charge carriers enter the channel at source and exit via the drain. The width
of the channel is controlled by the voltage on an electrode is called gate which is located
between source and drain. It is insulated from the channel near an extremely thin layer of
metal oxide. The MOS capacity present in the device is the main part

Working Principle of MOSFET:

The aim of the MOSFET is to be able to control the voltage and current flow between the
source and drain. It works almost as a switch. The working of MOSFET depends upon the
MOS capacitor. The MOS capacitor is the main part of MOSFET. The semiconductor surface
at the below oxide layer which is located between source and drain terminal. It can be
inverted from p-type to n-type by applying a positive or negative gate voltages respectively.
When we apply the positive gate voltage the holes present under the oxide layer with a
repulsive force and holes are pushed downward with the substrate. The depletion region
populated by the bound negative charges which are associated with the acceptor atoms.
The electrons reach channel is formed. The positive voltage also attracts electrons from the
n+ source and drain regions into the channel. Now, if a voltage is applied between the drain
and source, the current flows freely between the source and drain and the gate voltage
controls the electrons in the channel. Instead of positive voltage if we apply negative
voltage, a hole channel will be formed under the oxide layer.

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Terminologies:

Accumulation:

Accumulation occurs when one applies a voltage less than the flatband voltage. The
negative charge on the gate attracts holes from the substrate to the oxide-semiconductor
interface. Only a small amount of band bending is needed to build up the accumulation
charge so that almost all of the potential variation is within the oxide

Depletion:

As a more positive voltage than the flatband voltage is applied, a negative charge builds up
in the semiconductor. Initially this charge is due to the depletion of the semiconductor
starting from the oxide-semiconductor interface. The depletion layer width further
increases with increasing gate voltage.

Inversion:

As the potential across the semiconductor increases beyond twice the bulk potential,
another type of negative charge emerges at the oxide-semiconductor interface: this charge
is due to minority carriers, which form a so-called inversion layer. As one further increases
the gate voltage, the depletion layer width barely increases further since the charge in the
inversion layer increases exponentially with the surface potential.

CREATING A NOT GATE SYMBOL:

Create->cell view->from cell view

Not gate schematic

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Not gate layout

DESIGN AND SIMULATION:

Creating Schematic:

1)Open Virtuoso

2)Click on Tools->Library Manager->Choose your directory

3)File->New->Library->Attach to an existing library->GPDK 180

4)File->New->Cell View and give cell name

5)To add Instance, in Schematic click on Create->Instance->Browse->Pmos /Nmos->Symbol

(or I)

6)To add pin, in Schematic, click on Create pin (or P)

7)Check and save, then check for any errors by pressing ' G'

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Creating Layout:

1)Launch->Layout XL

2)Create new->Give a name

3)In order to insert all elements click on, Connectivity->Generate->All from Source

4) In order to insert selected elements click on, Connectivity->Generate->Selected from

Source->Click on selected from source

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Layout1: designed by Suhal Shetty

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Layout2: designed by Raghavendra

Layout3: designed by Akshay

All the above different modules of PFD are simulated using Cadence in GPDK 180
technology.

CHECKING DRC (DESIGN RULE CHECK) ERRORS:

Layout must be drawn according to strict design rules. After you have finished your layout,
an automatic program will check each and every polygon in your design against these design
rules and report violations. This process is called Design Rule Checking (DRC) and MUST be
done for every layout to ensure it will function properly when fabricated.

Click on assura->technology and select GPDK180

Then click on assura->run DRC-> select technology GPDK180 and run

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We will get the above prompt if we have no DRC errors

CHECKING LVS (LAYOUT VERSUS SCHEMATIC) ERRORS: Compare the netlist extracted from
the layout with the schematic to ensure the layout you have drawn is an identical match to the
cell schematic.
Click on assura->run LVS-> select technology GPDK180 and run

If layout matches with schematic, then we will get the above prompt
Simulation steps:

In the schematic replace all the pins with required voltage sources

1)Click on Launch->ADE L

2)Analyse->Choose->trans->delaytime:100ns->moderate->ok

3)Output->Setup->From design select the nets

4)Setup->Model libraries->GPDK 180nm

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5)Simulation->Netlist & Run

This is the required output in which the PFD compares reference clock and VCO clock and
measures the phase difference between them

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