INTEGRATION, the VLSI journal 47 (2014) 62–70

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INTEGRATION, the VLSI journal

journal homepage: www.elsevier.com/locate/vlsi

Full-Swing Gate Diffusion Input logic—Case-study of low-power

CLA adder design
Arkadiy Morgenshtein, Viacheslav Yuzhaninov, Alexey Kovshilovsky, Alexander Fish n
Faculty of Engineering, Bar-Ilan University, Ramat-Gan 52900, Israel

art ic l e i nf o a b s t r a c t

Article history: Full Swing Gate Diffusion Input (FS-GDI) methodology is presented. The proposed methodology is
Received 15 July 2012 applied to a 40 nm Carry Look Ahead Adder (CLA). The CLA is implemented mainly using GDI full-swing
Received in revised form F1 and F2 gates, which are the counterparts of standard CMOS NAND and NOR gates. A 16-bit GDI CLA
8 February 2013
was designed in a 40 nm low power TSMC process. The CLA, implemented according to the proposed
Accepted 24 April 2013
Available online 7 May 2013
methodology, presents full functionality and robustness under global and local process variations at
wide range of supply voltages. Simulation results show 2
area reduction, 5
improvement in dynamic
Keywords: energy dissipation and 4
decrease in leakage, with a slight (24%) degradation in performance, when
Alternative logic family compared to the CMOS CLA. Advanced design metrics of GDI cells, such as minimum energy point (MEP)
Carry Look Ahead (CLA) adder
operation and minimum leakage vector (MLV), are discussed.
Full-Swing GDI
& 2013 Elsevier B.V. All rights reserved.
Gate Difusion Input (GDI)
Low power

1. Introduction
Power consumption and area reduction of logic and memory
have become primary focuses of attention in VLSI digital design
[1–6]. Power is the limiting factor in both high performance
systems and portable applications. Die area directly affects the
device size and cost. Since the introduction of the standard CMOS
Logic in early 80s, many design solutions have been proposed
to improve power dissipation, area and performance of digital
VLSI chips.
Gate Diffusion Input (GDI) design methodology was introduced
as a promising alternative to Static CMOS Logic [7]. Originally
proposed for fabrication in Silicon on Insulator (SOI) and twin-well
CMOS processes, GDI methodology allowed implementation of a
wide range of complex logic functions using only two transistors
[7]. It was shown, that area and dynamic power of GDI combina-
torial and sequential logic were significantly reduced, as compared
to standard CMOS implementations. Similarly to existing alter-
natives to CMOS, such as Pass Transistor Logic (PTL), the GDI gates
presented reduced voltage swing at their outputs due to threshold
drops. These drops usually cause degradation in performance and
increased short circuit power [8]. However, since the GDI circuits
were implemented with much less transistors, a significant power
overall power reduction was observed, while maintaining minimal
performance penalty.
n
Corresponding author. Tel.: +972 54 8044144; fax: +972 3 7384051.
E-mail addresses: alexander.fish@gmail.com, alexander.fish@biu.ac.il (A. Fish).
Recently, it was shown that any GDI circuit can be implemented
in a standard CMOS process [8]. The efficiency of the GDI method
for both combinatorial and sequential logic was shown by many
groups [8–15]. Various combinatorial circuits, such as adders,
multipliers, comparators, and counters, were implemented in
processes from 0.8 mm down to 65 nm. GDI Flip-Flops were also
presented, showing improvements in both area and power, com-
pared to existing Flip Flop styles.
In this paper we present an efficient methodology for digital
circuits implementation. The proposed methodology was applied
to a 16-bit adder in low power standard 40 nm TSMC process. CLA
adder architecture, which was originally proposed as an alterna-
tive for the speed enhancement of a simple ripple adder, was
chosen as a benchmark circuit in this work. The proposed CLA
implementation utilizes improved full-swing GDI F1 and F2 gates,
which are the counterparts of standard CMOS NAND and NOR
gates. The CLA design is compared with our previously shown GDI
methodology [8], which utilizes swing-restoring buffers with
selective application of high-Vth transistors, as well as with
standard CMOS implementation. Simulation results show CLA
functionality and robustness under global and local process varia-
tions. The CLA presents 2
area reduction and 4–5
power
reduction, compared to the conventional CMOS implementation.
The contributions of this paper are as follows: (1) The GDI full
swing methodology for a standard nanoscaled CMOS technology is
presented; (2) Leakage reduction in GDI is discussed through
minimum leakage vector (MLV) analysis; (3) GDI robustness is
evaluated through statistical Monte Carlo simulations; and (4) Low
voltage operation of the GDI cells, including minimum energy
operation (MEP) is shown.

0167-9260/$ - see front matter & 2013 Elsevier B.V. All rights reserved.
http://dx.doi.org/10.1016/j.vlsi.2013.04.002
 A. Morgenshtein et al. / INTEGRATION, the VLSI journal 47 (2014) 62–70
The paper is organized as follows: Section 2 overviews the
GDI methodology and presents its benefits and limitations. The
proposed CLA implementation is discussed in Section 3. Section 4
presents simulation results of the proposed GDI CLA in 40 nm
standard CMOS process, comparing them to the CMOS CLA.
Section 5 concludes the paper.
2. Overview of GDI
The basic GDI cell is shown in Fig. 1. At the first glance, the GDI
cell, which consists of only two transistors, resembles the conven-
tional CMOS inverter. However, contradictory to the inverter, it
contains three inputs: G (common gate input of both the nMOS
and the pMOS), P (input to the source/drain of the pMOS), and N
(input to the source/drain of the nMOS).
It was shown that multiple Boolean functions can be imple-
mented by a simple GDI cell, as demonstrated in Table 1. This is
achieved by a change of the input configuration of the GDI cell.
While implementation of most of these functions is relatively
complex (6–12 transistors) in Static CMOS, it is very efficient (only
2 transistors) with the GDI cells. The Multiplexer (MUX) is the
most complex function that can be implemented with a basic GDI
cell, while being the most efficient function as compared to CMOS
implementation.
GDI gates may suffer from threshold voltage drops which
reduce current drive and therefore affect the performance of the
gate. These drops also increase direct-path static power dissipation
in the cascaded inverters, used for swing restoration. It was shown
that these effects can be significantly reduced by using swing-
restoration buffers with a multiple VTH approach [7], herein
named MVT. This approach suggests using low threshold transis-
tors in all paths where a voltage drop is expected. This way,
the voltage drop at the output will be minimal. In addition, all
regenerative inverters are implemented using high threshold
Fig. 1. Basic GDI cell.
Table 1
Boolean function synthesis through input configuration of a simple GDI cell
N P G Out
‘0’ B A AB
B ‘1’ A AþB
‘1’ B A AþB
‘0’
B A AB
C B A AB þ AC
‘0’ ‘1’ A NOT
A F 1 ðb; aÞ;
63
transistors. This combination allows minimization of the direct-
path static power in the inverters.
Most of today's static digital designs are based on CMOS NAND
and NOR gates. The reasons for this are known and well explored.
Both NAND and NOR gates are implemented using only four
transistors and each one of these functions is a universal set. The
GDI method, which is very efficient for implementation of various
gates, such as MUX, AND, OR (see Table 2), has similar number of
transistors in NAND/NOR gates implementation as standard CMOS
methodology. However, the GDI technology provides alternative
basic functions, F1 and F2. Consisting only of two transistors (one
GDI cell), each one of these functions represents a universal set.
Moreover, it was shown in [7] that F1 and F2 functions can be used
to synthesize other functions more efficiently than the NAND
and NOR gates. Fig. 2 shows a comparison of number of various
functions that can be implemented using the same number of F1
and NAND gates. The strength of the F1 and F2 gates will be also
demonstrated by implementation of CLA using mainly these GDI
gates (see Section 3).
3. GDI CLA adder design
3.1. Full-swing GDI cells
In this paper we propose full-swing (FS) GDI cells. The
proposed technique utilizes a single swing restoration (SR) tran-
sistor to improve the output swing of F1 and F2 GDI gates. Fig. 3
shows the structure of full swing F1 and F2 cells. As can be seen,
the SR transistor is activated only in cases when the Vth drop may
occur at the output. Since in F1 and F2 gates, the output VTH drop
can occur only at one of the logical levels (VTH instead of 0 V in F1,
and VDD–VTH instead of VDD in F2), only a single SR transistor is
required to ensure the full swing operation.
In cases where the gate input signal of GDI cell has an inverted
representation in the circuit, it can be used to control the swing
restoring transistor. This transistor will have a diffusion input similar
to the diffusion input of GDI, but will be of an opposite type (nMOS
for F1, and pMOS for F2). In this manner, the diffusion input signal
will pass through a pair of transistors of both types (in the transistor
of original GDI cell, and the complementary SR transistor). The
FS GDI cells are efficient alternative for swing restoration buffers,
in designs where inverted signals can be obtained as part of logic
function implementation. The CLA adder presented in the next sub-
section is a good example of such design. An example of a logic chain
in CLA, containing full-swing GDI cells, is shown in Fig. 4.
3.2. CLA implementation
Two GDI versions of a 16-bit CLA adder were implemented in
this work: one using swing restoration buffers with multiple Vth
(MVT GDI), and the second one with FS GDI gates.
A similar conventional CLA architecture, shown in Fig. 5, was
used to implement all the CLA versions. The circuit-level imple-
mentation of MVT and FS GDI adders was different, in order to
address the specific properties of each technique. The implemen-
tation was based mostly on F1 and F2 cells. The detailed GDI
implementation of various CLA blocks is given in (1)–(4) and
Function
is depicted in Table 2, assuming the logical functions F1 ða; bÞ ¼ ab
F1 and F2 ða; bÞ ¼ a þ b.
F2 The pg unit outputs were implemented as follows:
OR
p ¼ a⊕b; GDI XOR gate
AND (
MUX F 2 ða; bÞ; MVT GDI ð1Þ
g ¼ ab ¼
FS GDI
64 A. Morgenshtein et al. / INTEGRATION, the VLSI journal 47 (2014) 62–70

Table 2
The transistor-level design of CLA blocks.

Unit MVT GDI Full-Swing (FS) GDI

pg

PG

LCG

CLA
 A. Morgenshtein et al. / INTEGRATION, the VLSI journal 47 (2014) 62–70 65

Table 2 (continued )

Unit MVT GDI Full-Swing (FS) GDI

Last CLA

Inverter with HVT nMOS transistor, Inverter with HVT pMOS transistor, Inverter with both, HVT transistors.

Note: F1* and F2* stand for GDI F1 and F2 full swing gates.

CMOS NAND cell vs. GDI F1 cell

45
41
40

35
Number of Functions

30

25 GDI

21
20
16
CMOS
15

10
8 Fig. 3. Scheme of the FS GDI gates.
8
5 4
2
The local and global carry generator blocks are implemented
0
0 1 2 3 4 according to:
Number of Cells C loc ¼ g 0 þ p0 C in
(
Fig. 2. Number of various functions that can be implemented using the same F 1 ðg 0 ; F 2 ðC in ; p0 ÞÞ; MVT GDI
number of F1 and NAND cells (after [7]). ¼ ð3Þ
F 2 ðF 1 ðp0 ; C in Þ; g 0 Þ; FS GDI

C out ¼ G1 þ P 1 G0 þ P 1 P 0 C in ¼ F 2 ðP 1 G0 þ G1 ; P 1 P 0 C in Þ
where a similar GDI XOR gate was used in both versions, as will be
explained below. ¼ F 2 ðF 2 ðP 1 G0 ; G1 Þ; F 1 ðP 1 P 0 ; C in ÞÞ
The PG unit implementation is the following:
¼ F 2 ðF 2 ðF 1 ðP 1 ; G0 Þ; G1 Þ; F 1 ðF 1 ðP 1 ; P 0 Þ; C in ÞÞ ð4Þ
P ¼ p1 p0 ¼ F 1 ðp1 ; p0 Þ
( The signals P 1 ; G1 and P 0 ; G0 in (4) represent the outputs from
F 1 ðg 1 ; F 2 ðg 0 ; p1 ÞÞ; MVT GDI top hierarchy level CLA blocks.
G ¼ g 1 þ g 0 p1 ¼ ð2Þ It should be noted that in the MVT implementation, the
F 2 ðF 1 ðp1 ; g 0 Þ;g 1 Þ; FS GDI
application of high-Vth (HVT) transistors in swing restoration
where output P has similar implementation in both the versions. buffers is selective and depends on the Vth drop that may occur
66 A. Morgenshtein et al. / INTEGRATION, the VLSI journal 47 (2014) 62–70

in the path between two buffers. In case that the Vth drop at buffer
input may occur only at high (low) voltage, then an asymmetric
buffer will be used with high-Vth nMOS (pMOS) transistor. All
other transistors in the buffers will remain low-Vth (LVT) to
maintain the performance. In all the GDI cells, the transistor that
may cause a Vth drop, will be LVT in order to minimize the Vth
drop. Other GDI transistors will be standard-Vth (SVT).
The FS GDI implementation is based on the F1 and F2 cells, as
described in Fig. 3. The implementation did not require addition of
inverters for driving the SR transistors. All the inverted signals that
were used in SR transistors appeared inherently in the functional
implementation. In MUX cell implementation, a couple of com-
plementary SR transistors was used at the output, making the cell
similar to a PTL MUX.
In both the versions the XOR implementation was optimized.
The basic implementation of a GDI XOR gate, as was proposed
in [1], consists of 4 transistors comprising a GDI cell used as a
MUX, and an inverter. However, in complex circuits, the diffusion
input to GDI XOR may already have an inverted representation
F*
elsewhere in the circuit. Thus, instead of implementing an inverter
again as part of GDI XOR, we can use both signals as diffusion
inputs to GDI MUX while maintaining the same functionality.
This allows a significant decrease in number of transistors in
circuits with high number of XOR/XNOR gates. An example of the
optimization in GDI CLA adder can be seen in implementation of
the p function in Table 2. This optimization allowed reducing the
number of transistors in GDI design.
Both versions of GDI implementation were compared with
standard CMOS design of CLA adder. In order to maintain optimal
design, the XOR circuits in CMOS were implemented using the
PTL technique. Table 3 summarizes the transistor count and area
estimation of both GDI designs vs. CMOS counterpart. Note, all
CMOS gates were implemented using minimum sized transistors
with a standard ratio between pull up and pull down networks, i.e.
β¼2. GDI F1, F2 and XOR gates were sized similarly to a CMOS
inverter (β¼ 2). Supplementary SR transistors were: minimum
sized NMOS and double sized PMOS. The area estimation is
normalized with respect to WminLmin.
It can be clearly seen that both GDI implementations have
significant advantage in terms of transistors count and area,
as compared to CMOS. While FS GDI implementation provides
full swing and improved performance (as will be shown in the
following sections), it implies about 40% area increase as com-
pared to MVT GDI. Still, it occupies only half of area as compared to
CMOS design.

F* 3.3. Leakage elimination in GDI

As was shown in [7], the unique structure of the GDI cell

provides significant reduction of both the sub-threshold and the
Fig. 4. Example logic chain in CLA, containing full-swing GDI cells. gate leakage components, as compared to a static CMOS gate.

Fig. 5. The general CLA architecture.

Table 3
Transistor count and area estimation comparison between GDI and Static CMOS designs.

Design Unit

pg PG LCG CLA Last CLA Total

CMOS 18 18 12 30 34 934
(41) (35) (24) (59) (77) (2039)

MVT GDI 8 8 8 16 24 438

(12) (12) (12) (24) (36) (657)

FS GDI 11 11 10 21 31 627
(16) (16) (15) (31) (46) (925)

Transistors count (Area [W min L min]).

 A. Morgenshtein et al. / INTEGRATION, the VLSI journal 47 (2014) 62–70 67

values of 100 mV up to nominal values of 1.1 V. The designs were

simulated using SPICE based Virtuoso simulator. Both GDI designs
were compared to the CMOS counterpart in terms of performance,
power consumption, area estimation and sensitivity to process
variations.

4.1. Nominal voltage operation

The comparative results of performance, static power, energy

per operation and energy-delay product (EDP) in CMOS and GDI
Fig. 6. LCG unit with minimum leakage vector.
implementations are presented in Table 4.
Delay—As can be seen, the CMOS design has the shortest delay
among all implementations. The FS GDI implementation shows a
30% delay increase as compared to CMOS. The MVT GDI is about
three times slower than CMOS due to voltage drops. The perfor-
mance improvement in FS GDI is achieved due to better driving
capabilities of the modified F1 and F2 gates.
Static power consumption—According to the results presented
in Table 4, the static power of both GDI designs is significantly
lower than in CMOS design. One of the reasons for leakage
reduction in GDI is the reduced transistor count. In addition, as
shown in previous section, GDI benefits from an inherent sub-
threshold leakage reduction in half of the input vectors, leading to
a zero potential between the diffusion inputs of GDI cell [7]. The FS
GDI implementation presents reduction in static power consump-
tion. as compared to MVT GDI. This is achieved by maintaining full
swing at output nodes of all GDI cells, and therefore eliminating
the direct-path currents.
Dynamic Energy and EDP—Table 4 shows a 5–6
reduction of
dynamic energy consumption per operation in both GDI circuits
as compared to CMOS. The main reason for this is the reduced
switching capacitance in GDI. Note that although CMOS presents
an advantage over GDI by means of delay, it can be clearly seen
that the EDP metric of both GDI designs is better.
Fig. 7. PG unit with minimum leakage vector.

Since the sub-threshold leakage is still dominant, it is addressed Table 4

Comparison of performance, static and dynamic power in GDI and CMOS CLA
here in more details. implementations.
A general GDI cell eliminates the sub-threshold leakage in half
of all possible states. This is contrary to static CMOS gates, where tpd [psec] PStat [nW] EDyn [f] EDP [J sec 10−24]
the pull-up and the pull-down networks are always connected to
CMOS 134 78.7 123 16.5
the supply voltage and ground, respectively.
MVT GDI 422 35.9 23.5 8.2
Here we demonstrate this advantage by analyzing the minimum FS GDI 167 18.4 19.4 3.9
leakage vector (MLV) of a basic two-bit CLA module, consisting of
PG and LCG blocks. The following input vector provides the minimal
leakage in the two-bit FS-GDI CLA
!
vin ¼ ðg 0 ; g 1 ; p0 ; p1 ; C in Þ ¼ ð1; 1; 0; 1; 0Þ
As can be seen in Fig. 6, when the input vector is applied to LCG
block, four transistors are turned off (M1, M3, M4 and the inverter
nMOS). However, as the inputs Cin and go are connected to
diffusions of turned-off transistors, the potential at both diffusion
nodes of the transistors is similar. This leads to elimination of sub-
threshold leakage in transistors M1, M3 and M4.
Similar effect is observed when the input vector vin is applied
to the PG block, as shown in Fig. 7. As can be seen, due to the
diffusion input connections, three out of five turned-off transistors
have zero potential between the diffusion nodes. In this case
transistors M2, M8 and M9 exhibit zero sub-threshold leakage.

4. Comparative simulation results

The proposed 16-bit CLA circuits were designed in 40 nm TSMC

process with supply voltage varying from deep sub-threshold Fig. 8. Delay distribution of CMOS design derived by Monte Carlo simulation.
68 A. Morgenshtein et al. / INTEGRATION, the VLSI journal 47 (2014) 62–70
Fig. 9. Delay distribution of MVT GDI design derived by Monte Carlo simulation.
Fig. 10. Delay distribution of FS GDI design derived by Monte Carlo simulation.
Fig. 11. MEPs simulation.
Sensitivity of Process Variations—In order to evaluate the sensi-
tivity of the designs to local and global process variations, Monte
Carlo simulations have been carried out. Figs. 8–10 present the
delay distribution of CMOS, MVT GDI and FS GDI, respectively.
As expected, FS GDI presents much better immunity to process
variations than MVT GDI, while showing μ/s ratio that is very close
to CMOS (only 12% degradation). The MVT GDI adder is much
more sensitive (4
degradation as compared to CMOS), because
of driving current dependence on process-sensitive Vth, which is
amplified due to voltage drops at internal nodes.
4.2. Low voltage operation
Driven by demand for ultra-low power dissipation, low voltage
operation of digital circuits has recently gained extensive research
efforts [16–23]. It was shown that minimum energy operation
point (MEP) is usually achieved in the sub-threshold region. Here
we examine the operation of GDI and CMOS adders at low supply
voltages.
While discussing the MEP term, it should be reminded that the
total energy consumption is comprised of two different compo-
nents— Etotal ¼ Edyn þ Eleak . The dynamic energy component is
proportional to an effective load capacitance and supply voltage—
Edyn ∝C ef f V DD 2 , while the leakage component is dominated by
integration of a sub-threshold current along the operation time—
Eleak ∝V DD 2 expð−V DD =nV t Þ, assuming full swing operation [24]. It can
be easily noticed that these two components have an opposite
effect as a function of VDD, so their relation determines the MEP.
Fig. 10 presents the dependency of total energy consumption
on varying supply voltages. MEPs of GDI and CMOS adders are
shown. Note that the simulation was carried out at a typical corner
(TT), thus the actual MEPs may be higher due to increased leakage
currents under process variations.
An interesting observation from Fig. 11 is that the same order of
MEP energy dissipation is obtained for all designs, while the MEPs
were achieved at different voltages. The FS GDI has 35% lower MEP
energy, as compared to CMOS.
Both GDI designs have reduced effective load capacitances, thus
the consumed energy at high VDD values is lower than in CMOS.
The sub-threshold leakage in MVT GDI adder starts dominating
 A. Morgenshtein et al. / INTEGRATION, the VLSI journal 47 (2014) 62–70
Fig. 12. Propagation delay of CLA Adders at low supply voltages.
Table 5
Transistor count and area estimation comparison between GDI and Static CMOS
designs.
MEP VDD [V] MEP energy [fJ] MEP delay [μ sec]
CMOS 0.18 4.7 5.51
MVT GDI 0.32 5.2 5.92
FS GDI 0.22 3.1 4.17
at higher VDD values because of the VTH drops. Thus, the MVT GDI
achieves the MEP at higher voltage. FS GDI design has slightly
higher effective capacitances. Therefore, its energy consumption at
large voltages is increased. Since no VTH drops occur in FS GDI, its
leakage component becomes dominant at lower supply voltage and
therefore the MEP is shifted towards lower VDD. The CMOS adder
MEP appears at lower VDD because of the dominating dynamic
energy caused by higher switching capacitances.
Fig. 12 presents the propagation delay of all adders as function
of supply voltage sweep. The delays at MEP are also shown. As can
be seen, the MVT GDI adder exhibits a delay of about one order
higher than in CMOS and FS GDI. However, at MEP, the delay
of MVT GDI is comparable with the MEP delays of the other
techniques.
Table 5 summarizes the characteristics of all the designs at
MEP. As can be seen, FS GDI presents the best energy and delay
at MEP. Moreover, the MEP is achieved at higher VDD than CMOS,
which when accounting the similar process variation sensitivity
make FS GDI beneficial for minimal energy operation.
5. Conclusions
Full Swing Gate Diffusion Input (FS GDI) methodology was
proposed and evaluated on a 16-bit Carry Look Ahead Adder (CLA).
It was shown that the proposed FS-GDI circuits are beneficial in
terms of performance and static power consumption, as compared
to the conventional multiple Vth GDI (MVT-GDI). Three CLA
versions, based on FS-GDI, MVT-GDI and standard CMOS were
69
designed and compared in 40 nm low power TSMC process.
Simulation results showed a clear advantage of the proposed GDI
CLAs by means of area, dynamic and static energy. The FS-GDI
achieved 2
area reduction, 5
improvement in dynamic energy
dissipation and 4
decrease in leakage, with a slight (24%)
degradation in performance, when compared to the CMOS CLA.
Advanced design metrics of GDI cells, such as minimum energy
point (MEP) operation and minimum leakage vector (MLV) were
discussed. It was shown that MVT-GDI achieved better character-
istics at MEP, as compared to other techniques.
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Arkadiy Morgenshtein received the B.Sc. degree in
electrical engineering in 1999, M.Sc. in biomedical
engineering in 2003, MBA in 2006 and Ph.D in elec-
trical engineering in 2008 from Technion, Israel Insti-
tute of Technology. In 2012 he joined the IBM Haifa
Research Lab. Prior to that he worked with Core CAD
Technologies group at Intel Corporation, where he was
researching and developing tools for power optimiza-
tion and estimation at various levels of VLSI design. He
has been a Teaching and Research Assistant at Electrical
Engineering Department, Technion since 1999, where
he is currently an Adjunct Lecturer.
Dr. Morgenshtein's research interests include low-
power design techniques for digital circuits, optimization of on-chip interconnect,
CMOS sensors and EDA tools for power estimation and optimization. He has
authored over 40 scientific papers and patent applications. Dr. Morgenshtein co-
authored a paper that won the IEEE VLSI Transactions (TVLSI) Best Paper award
for 2012. He was honored by Technion President's award and Intel-Technion award
for excellence in study in 1998 and 2007. He supervised projects winning the award
of Oz Moses Foundation by Intel in 2002 and best VLSI project in 2003 and 2005.
Dr. Morgenshtein has served as associate editor for the Journal of Low Power
Electronics and Applications (JLPEA), as session chairman at ICECS'04 Conference
and as referee in multiple journals and conferences.
Viacheslav Yuzhaninov received the B.Sc. degree
in Electrical Engineering from Ben-Gurion University,
Be’er Sheva, Israel, in 2012. He has been a Research
Assistant at the Low Power Circuits and Systems Lab,
VLSI Systems Center, Ben-Gurion University, since 2011.
He is currently working on his M.Sc degree in
Electrical Enginering at Bar-Ilan University. His research
interests are energy effcient logic families and low
voltage high performance digital design.
Alexey Kovshilovsky received the B.Sc. degree in
Electrical Engineering from Ben-Gurion University,
Be’er Sheva, Israel, in 2012. He has been a Research
Assistant at the Low Power Circuits and Systems Lab,
VLSI Systems Center, Ben-Gurion University, since 2011.
Currently he is working as an Embedded Software
Engineer at Powermat Technologies in Neve-Ilan, Israel.
Alexander Fish received the B.Sc. degree in Electrical
Engineering from the Technion, Israel Institute of
Technology, Haifa, Israel, in 1999. He completed his
M.Sc. in 2002 and his Ph.D. (summa cum laude) in
2006, respectively, at Ben-Gurion University in Israel.
He was a postdoctoral fellow in the ATIPS laboratory at
the University of Calgary (Canada) from 2006–2008. In
2008 he joined the Ben-Gurion University in Israel, as a
faculty member in the Electrical and Computer Engi-
neering Department. There he founded the Low Power
Circuits and Systems (LPC&S) laboratory, specializing in
low power circuits and systems. In July 2011 he was
appointed as a head of the VLSI Systems Center at BGU.
In October 2012 Prof. Fish joined the Bar-Ilan University, Faculty of Engineering as
an Associate Professor and the head of the microelectronics track. Prof. Fish also
leads new Energy Efficient Electronics and Applications Labs.
Prof. Fish's research interests include development of energy efficient “smart”
CMOS image sensors, ultra low power SRAM, DRAM and Flash memory arrays and
energy efficient design techniques for low voltage digital and analog VLSI chips. He
has authored over 70 scientific papers in journals and conferences, including IEEE
Journal of Solid State Circuits, IEEE Transactions on Electron Devices, IEEE Transac-
tions on Circuits and Systems and many others. He also submitted 16 patent
applications. Prof. Fish has published two book chapters. He was a co-author
of papers that won the Best Paper Finalist awards at IEEE ISCAS and ICECS
conferences.
Prof. Fish serves as an Editor in Chief for the MDPI Journal of Low Power
Electronics and Applications (JLPEA) and as an Associate Editor for the IEEE Sensors
Journal. He also served as a chair of different tracks of various IEEE conferences. He
was a co-organizer of many special sessions at IEEE conferences, including IEEE
ISCAS, IEEE Sensors and IEEEI conferences. Prof. Fish is a member of Sensory, VLSI
Systems and Applications and Bio-medical Systems Technical Committees of IEEE
Circuits and Systems Society.