As we did for BJT design, the first step is to define a Q-point. For
convenience, the Thevenin equivalent voltage and resistance and the Q-
point relationships developed in Section J4 are repeated here (remember
that the assumption |λvDS|<<1 in the derivation of these equations):
R1 R2
RG = R1 || R2 =
R1 + R2
V DD R1
VGG =
R1 + R2
2 2
⎛ VGSQ
2 ⎞ ⎛ V ⎞
I DQ = K (VGSQ − VT ) (1 + λV DSQ ) ≅ K (VGSQ
2
− VT ) = KVT ⎜⎜1 −
2
⎟ = I DSS ⎜1 − GSQ
⎟ ⎜
⎟
⎟ ( MOSFET )
⎝ VT ⎠ ⎝ VT ⎠
2 2
⎛ VGSQ ⎞ ⎛ V ⎞
I DQ = I DSS ⎜⎜1 − ⎟ (1 + λV DSQ ) ≅ I DSS ⎜1 − GSQ
⎟ ⎜
⎟
⎟ ( JFET )
⎝ VP ⎠ ⎝ VP ⎠
VGG = VGSQ + I DQ R S
V DD = I DQ R D + V DSQ + I DQ R S = V DSQ + I DQ ( R D + R S )
2 I DSS ⎛ V ⎞
gm = − ⎜1 − GSQ ⎟ Note : VT = V P for JFETs
⎜ ⎟
VT ⎝ VT ⎠
Writing the dc KVL around the drain source loop in the figure above
(assuming IS•ID) and solving for the unknown resistors RS and RD yield one
equation in two unknowns:
V DD − V DS
RS + RD = = K1 , (Equation 6.59)
ID
where the constant K1 is introduced to simplify future notation. Note that we
need another equation to solve for the resistances (two unknowns requires
two independent equations). For our second equation, we can use either the
voltage gain or current gain expression derived in the previous section:
− g m ( R D || R L ) − ( R D || R L ) − RG RD
AV = = Ai =
(1 + g m R S ) RS + 1 / g m RS + 1 / g m RD + RL
− ( R D || R L )
AV = . (Equation 6.60)
(K1 − RD ) + 1 / g m
There are two possible solutions to the quadratic equation, one negative and
one positive. Since RD must be greater than zero, only the positive solution
is used. However, it’s not quite that simple and we must get through
checkpoint #1…
With RS and RD known, the remaining unknowns are R1 and R2. Directly
analogous to our work with BJT amplifiers, the first thing we do is write the
general dc KVL for the gate source loop to solve for VGG:
Once a value for VGG is obtained, we hit checkpoint #2…if VGG has the
same polarity as VDD, use either the equation for input resistance or
current gain (reproduced below) to solve for RG.
− RG RD
Rin = RG = R1 || R2 Ai =
RS + 1 / g m RD + RL
Using the expressions for the Thevenin equivalent voltage and resistance,
we can now solve for R1 and R2:
RG RG V DD
R1 = R2 = . (Equation 6.63)
1 − VGG / V DD VGG
Oh well, can’t do it right? Come now, you’ve been at this long enough to
know that there’s a trick involved!
R S dc = R S1 + R S 2 ; R S ac = R S 1 .
Going back to our dc KVL equation for the gate-source loop and setting VGG
equal to zero, we can define RSdc:
− VGS
R Sdc = .
ID
Once we have defined RSdc, we must back up and revise other values in the
design. The dc KVL equation for the drain-source loop (Equation 6.59) now
becomes:
V DD − V DS
R S dc + R D = = K1 ,
ID
− ( R D || R L )
AV = . (Equation 6.66)
R Sac + 1 / g m
Note that, in this case, RSac is the only unknown. Solving for RSac, we get
− (RD || RL ) 1
RSac = RS1 = − . (Equation 6.67)
AV gm
If we’re taking this route, we’ve got yet one more checkpoint to encounter!
¾ less than RSdc, we can solve for RS2 ( R S 2 = R Sdc − R Sac ) and the design is
complete; or
¾ greater than RSdc. If this happens, the amplifier cannot be designed with
the gain specified and the Q-point selected. If the gain specification is
reasonable, a new Q-point should be chosen and the design process
repeated. However, if the gain specified is too high, the amplifier cannot
be designed with a single stage and/or with the transistor chosen –
which, after all this work, is a total bummer!
1
Rout = R S || Rin = RG = R1 || R2
gm
R S || R L RG R S
AV = Ai =
( R S || R L ) + 1 / g m ( R S + R L )[( R S || R L ) + 1 / g m ]
The first step in any design process is to choose the operating point (Q-
point). This may be achieved by using the device characteristic curves, or
the normalized curve presented in Figure 6.20. Specifically, your author
states that a good rule of thumb for setting a starting point for the quiescent
values is the condition
Once the Q-point is selected, quiescent values for VDS, VGS, ID and gm are
defined. Rearranging the dc KVL equation for the drain-source loop and
solving for dc value of the source resistance, RSdc:
V DD − V DS
R Sdc = . (Equation 6.71, Modified)
ID
If the voltage gain is given (this is not in your text), the ac resistance of the
source circuit may be expressed as:
RL
R Sac = .
⎛ 1 ⎞
g m R L ⎜⎜ − 1⎟⎟ − 1
⎝ AV ⎠
This expression will yield a positive value for RSac for any voltage gain less
than 0.5 (recall |AV| < 1 for the CD configuration). However, since the
voltage gain is usually not defined for these amplifiers, the specification of
interest will be the current gain as discussed in your text.
Rearranging the current gain equation and solving for RSac yields:
RL
R Sac = . (Equation 6.72)
⎛R ⎞
g m ⎜⎜ in − R L ⎟⎟ − 1
⎝ Ai ⎠
where the substitution RG = Rin has been made. How we proceed now
depends on whether or not Rin is specified.
¾ If Rin is specified, calculate RSac from Equation 6.72. In this case, RSac
will be different from RSdc. Now…
o if RSac < RSdc, the source resistance RS is composed of RS1 and RS2 in
series and RS2 must be bypassed with a capacitor. For this case,
RSdc=RS1+RS2 and RSac=RS1.
o if RSac > RSdc, a smaller VDSQ must be chosen and the design process
started over. Shifting the Q-point in this manner causes a larger
voltage drop across the total source resistance, thereby making RSdc
(=RS1+RS2) larger. If VDS cannot be reduced enough to make RSdc >
RSac, the amplifier cannot be designed with the given Ai, Rin and
transistor type. One (or more) of these specifications must be
changed, or a second amplifier stage introduced to achieve the
required gain.
¾ If Rin is not specified, let RSac=RSdc and solve Equation 6.72 for Rin
(=RG). If the input resistance is not high enough, it may be necessary to
change the Q-point location and begin the design process over.
Once we get all that straightened out, to solve for R1 and R2 it is necessary
to solve for the Thevenin equivalent voltage VGG by writing the dc KVL
equation around the gate-source loop:
Using the expressions for the Thevenin equivalent voltage and resistance,
we can now solve for R1 and R2 in the usual manner:
RG RG V DD
R1 = R2 = . (Equation 6.74)
1 − VGG / V DD VGG
The SF Bootstrap Amplifier
¾ The need for a bypass capacitor across part of the source resistance is
removed.
¾ The bootstrap configuration may attain a much larger input resistance
than the normal CD (SF) configuration. This allows the designer to take
advantage of the high impedance characteristic of a FET device without
using a large gate resistance.
The first thing we’re going to do is make the assumption that Rin is
sufficiently large that iin is very much smaller than i1 (iin << i1). This
assumption will allow us to say that the voltage drop across RG may be
considered negligible when compared to vout. This will allow us to define the
output voltage in terms of RS||RL, where RS=RS1+RS2.
Using the above assumption, we may define the output voltage as
g m v gs R L
i1 = . (Equation 6.79)
RS + RL
To account for the contribution of iin on the input side, the current through
RS2 is the sum of iin and i1. Also, note that there are two possible paths in the
gate-source loop for dc KVL equations (shown in purple and green in the
figure above):
I’m going to take a slightly different approach for the next few equations,
but we’ll get the same place…
Combining terms and equating the two expressions for vin, we get:
v gs + i1 ( R S 1 + R S 2 ) + iin R S 2 = i in ( RG + R S 2 ) + i1 R S 2 ,
Solving for iin and substituting the expression of Equation 6.79 for i1:
v gs + i1 R S 1 v gs ⎛ g R R ⎞
iin = = ⎜⎜1 + m L S 1 ⎟⎟ . (2)
RG RG ⎝ RS + RL ⎠
Prove to yourself that the above relationship is exactly the same as Equation
6.82 derived in your text. Next, substitute Equations 6.79 and (2) into (1)
for (after lots of algebra):
⎡ R ⎛ g R R ⎞⎤
v in = v gs ⎢1 + g m ( R S || R L ) + S 2 ⎜⎜1 + m L S 1 ⎟⎟⎥ . (3)
⎢⎣ RG ⎝ R L + R S ⎠⎥⎦
Finally, for the input resistance Rin, divide (3) by (2), shake violently, and we
come up with:
⎛ ⎞
⎜ ⎟
v in ⎜ 1 + g m ( R S || R L ) ⎟
Rin = = RG ⎜ + RS 2 ,
iin g m R L RS1 ⎟
⎜⎜ 1 + ⎟
⎝ R S + R L ⎟⎠
which gets you the same place as Equation 6.83, but (to my mind anyway)
doesn’t look quite so horrific.
( Rin − R S 2 )( R S + R L + g m R L R S1 )
RG = =
RS + RL + g m RS RL
. (Equation 6.84)
[
( Rin − R S 2 ) ( R S + R L ) / g m + R L R S 1 ]
(RS + RL ) / g m + RS RL
Note that the denominator in Equation 6.84 is larger than the numerator (RS
> RS1), so RG < (Rin - RS2). Equivalently, Rin > (RG + RS2), so the input
impedance may be made larger without simply relying on RG.
The current gain for the SF bootstrap is found by using Equation 6.75 to
express iout=vout/RL and calculating Ai=iout/iin:
RG R S
Ai = . (Equation 6.86)
R L R S1 + ( R L + R S ) / g m
Finally, the voltage gain may be found by calculating vout/vin or by using the
gain impedance formula (the easier way):
Ai R L RG R S R L
Av = ,
Rin Rin [ R L R S 1 + ( R L + R S ) / g m ]
where Rin is given by the expression above or by Equation 6.83 in your text.