VLSI Testing &Testability

(ECT
ECT624/ECT306)
(M Tech VLSI Design)

Course File
(2019
(2019-20 Odd Semester)

Department
artment of Electronics and CCommunication Engineering
Malaviya National
ional Institute of Technology, JJaipur
aipur
Jaipur
aipur-India, 302017
 VLSI Testing &Testability
COURSE FILE

Program : Master of Technology

Specialisation : ECE/ VLSI Design

Course Code : ECT624/ECT306

Approved By

HoD
Electronics and CommunicationEngineering

2
 CONTENTS

1. SYLLABUS
2. REFERENCES
3. COURSE OUTCOMES
4. COURSE OUTCOME EVALUATION

3
 1. SYLLABUS (Module wise)

Specialisation: VLSI Design Code: ECT624/ECT306

Subject: VLSI Testing &Testability Credits: L-T-P: 3-0-0
Total Theory Periods: 36 Total Tutorial Periods: 00
Marks: 100, 30 in Mid-Term, 50 in End-Term, 20 marks assignment

Syllabus
UNIT 1. Introduction to Digital Testing: Intrloduction, Test process and Test economics,- Functional
vs. Structural Testing Defects, Errors, Faults and Fault Modeling ( Stuck at Faults, Bridging Faults,
transitor fault, delay fault), Fault Equivalence, Fault Dominance, Fault Collapsing and Checkpoint
Theorem
UNIT 2. Fault Simulation and Testability Measures: Circuit Modelling and Algorithms for Fault
Simulation, Serial Fault Simulation, Parallel Fault Simulation, Deductive Fault Simulation,
Concurrent Fault Simulation, Combinational SCOAP Measures and Sequential SCOAP Measures,
Critical Path Tracing
UNIT 3. Combinational Circuit Test Pattern Generation: Introduction to Automatic Test Pattern
Generation (ATPG) and ATPG Algebras, Standard ATPG Algorithms, D-Calculus and D-Algorithm,
Basics of PODEM Random, Deterministic and Weighted Random Test Pattern Generation; Aliasing and
its effect on Fault Coverage. PLA Testing, Cross Point Fault Model and Test Generation. Memory Testing-
Permanent, Intermittent and Pattern Sensitive Faults
UNIT 4. Sequential Circuit Testing and Scan Chains: ATPG for Single-Clock Synchronous Circuits,
Use of Nine-Valued Logic and Time-Frame Expansion Methods, Complexity of Sequential ATPG,
Scan Chain based Sequential Circuit Testing, Scan Cell Design, Design variations of Scan Chains,
Sequential Testing based on Scan Chains, Overheads of Scan Design, Partial-Scan Design
Controllability and Observability Scan Design, BILBO , Boundary Scan for Board Level Testing ; BIST and
Totally self checking circuits
UNIT 5. Self Repairing circuits and BIST: Introduction to BIST architecture BIST Test Pattern
Generation, Response Compaction and Response Analysis, Memory BIST, March Test, BIST with
MISR, Neighbourhood Pattern Sensitive Fault Test, Transparent Memory BIST, Totally self checking
circuits, Concept of Redundancy, Spatial Redundancy, Time Redundancy, Error Correction Codes. Recent
trends in VLSI Testing and Testability

Prerequisites:

 ECT202 Switching theory or equivalent

Course plan

Module Contents for delivery No Marks Mode of

no. . delivery
of
lec
tur
es
1. Intrloduction, Test process and Test economics,- Functional 7 MT=12 Choke and
vs. Structural Testing Defects, Errors, Faults and Fault Talk, PPT
Modeling (Stuck at Faults, Bridging Faults, transitor fault, delay ET=4

4
 fault), Fault Equivalence, Fault Dominance, Fault Collapsing
and Checkpoint Theorem

2. Circuit Modelling and Algorithms for Fault Simulation, 6 MT=12 Choke and
Serial Fault Simulation, Parallel Fault Simulation, Deductive Talk, PPT
Fault Simulation, Concurrent Fault Simulation, ET=4
Combinational SCOAP Measures and Sequential SCOAP
Measures, Critical Path Tracing

3. Introduction to Automatic Test Pattern Generation (ATPG) 7 MT=6 Choke and

and ATPG Algebras, Standard ATPG Algorithms, D- Talk, PPT
Calculus and D-Algorithm, Basics of PODEM Random, ET=10
Deterministic and Weighted Random Test Pattern Generation;
Aliasing and its effect on Fault Coverage. PLA Testing, Cross
Point Fault Model and Test Generation. Memory Testing-
Permanent, Intermittent and Pattern Sensitive Faults
4. ATPG for Single-Clock Synchronous Circuits, Use of Nine- 7 MT=0 Choke and
Valued Logic and Time-Frame Expansion Methods, Talk, PPT
Complexity of Sequential ATPG, Scan Chain based ET=16
Sequential Circuit Testing, Scan Cell Design, Design
variations of Scan Chains, Sequential Testing based on Scan
Chains, Overheads of Scan Design, Partial-Scan Design
Controllability and Observability Scan Design, BILBO ,
Boundary Scan for Board Level Testing ; BIST and Totally self
checking circuits
5. Introduction to BIST architecture BIST Test Pattern 7 MT=0 Choke and
Generation, Response Compaction and Response Analysis, Talk, PPT
Memory BIST, March Test, BIST with MISR, ET=16
Neighbourhood Pattern Sensitive Fault Test, Transparent
Memory BIST, Totally self checking circuits, Concept of
Redundancy, Spatial Redundancy, Time Redundancy, Error
Correction Codes. Recent trends in VLSI Testing and Testability

2. REFERENCES
Text Books:
1. Abramovici, M., Breuer, M. A. and Friedman, A. D. Digital systems testing and testable design. IEEE
press (Indian edition available through Jayco Publishing house), 2001.
2. Bushnell and Agarwal, V. D. VLSI Testing. Kluwer.
3. Agarwal, V. D. and Seth, S. C. Test generation for VLSI chips. IEEE computer society press.
4. Hurst, S. L. VLSI testing: Digital and mixed analog/digital techniques. INSPEC/IEE, 1999.

Other References:
1. https://nptel.ac.in/courses/106103116/handout/mod7.pdf
2. http://ece-research.unm.edu/jimp/vlsi_test/slides/html/overview1.htm
3. http://www.cs.uoi.gr/~tsiatouhas/CCD/Section_8_1-2p.pdf

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 4. Latest journal papers for recent trends in VLSI Testing and Testability

3. COURSE OUTCOMES

(And their mapping with Modules/Units, POs)

CO1 To able to grasp core concept of digital system PO1, PO9

testing and testability. (Knowledge)
CO2 To understand fault detection using different PO1,PO2, PO3,PO5
fault simulation techniques. (Skill)
CO3 To develop ability to design algorithms for PO1, PO2, PO3,
automatic test generation for combinational PO4,PO5, PO8,
circuits, sequential circuits, PLAs and memory. PO10, PO12
(Skill)
CO4 To apply probabilistic approaches for random PO1, PO2, PO3,
test generation. (Skill) PO4, PO6, PO8,
PO11, PO12,
CO5 To design BIST for a CUT in Verilog and PO1, PO2, PO4,
implement ATPG algorithms in PO5, PO6, PO8, PO9,
C/C++/MATLAB. (Skill) PO13
.

Mapping of COs with Modules/Units

CO-> CO1 CO2 CO3 CO4 CO5

1 √ √
2 √
Module/Unit

3 √ √
4 √
5 √ √

Mapping of COs with POs

Pos
6
 1 2 3 4 5 6 7 8 9 10 11 12 13
CO1 √ √
CO2 √ √ √ √
COs

CO3 √ √ √ √ √ √ √ √
CO4 √ √ √ √ √ √ √ √
CO5 √ √ √ √ √ √ √ √
4. COURSE OUTCOME EVALUATION
(To be modified later.)

4.1 (2018-19)

Mid Term Test

Module 1: 12 Marks
Module 2: 10 Marks
Module 3: 08 Marks

End Term Examination:

Unit 1: 4 marks-Q1
Unit 2: 6 Marks-Q2
Unit 3: 8 Marks-Q3
Unit 4: 16 Marks-Q4
Unit 5: 16 Marks-Q5

4.2 (2019-20)

S Stude CO CO2 CO3 CO4 CO5 CO6 CO7

N nt ID 1
Q1 Q Q Q Q Q Q Q Q Q Q Q5 Q1
2 3 2 3 3 4 5 2 3 4
1
2
3
4
5
6

7
 7
8
9
10
Total Avg(Q2+Q4)= Avg(Q5)= Avg(Q6
16/20 10/20 )=
10/20
This is the 80% 80% 30%
percentage
achieveme
nt of COs