DATA SHEET

TRUEVIEW™ 5725
Multimedia processor for HD PTV and LCD TV

Tel: 86-756-3628728 Email: sales@tvia.com

Version 3.2
April 2013

DS-5725-3.2
TRUEVIEWTM 5725

NOTE:
Tvia products are not designed for use in life support appliances, devices, or
systems where malfunction of a Tvia product can reasonably be expected to result in
personal injury. Distributors and/or customers using or selling such products for use
in life support equipment do so at their own risk and agree to fully indemnify Tvia of
such product liability or any damages, resulting from such use or sale.

REVISION HISTORY
Revision Description Corresponding Page(s)
1.0 2011 version
2.1 Add some details
3.1 Add some details
3.2 Add some details

http://www.tvia.com
Tel: 86-756-3628728 Email: sales@tvia.com ii DS-5725-3.2
TRUEVIEWTM 5725

Table of Contents
INTRODUCTION ............................................................................................................................................................................... 1
FEATURES ........................................................................................................................................................................................ 2
PINOUT DIAGRAM .......................................................................................................................................................................... 3
PIN DIAGRAM FOR QFP160 ............................................................................................................................................................ 3
PIN DESCRIPTION........................................................................................................................................................................... 4
FUNCTIONAL DESCRIPTION ..................................................................................................................................................... 10
ADC ............................................................................................................................................................................................... 10
INPUT FORMATTER......................................................................................................................................................................... 10
DE-INTERLACER ............................................................................................................................................................................. 10
FILM MODE..................................................................................................................................................................................... 10
3D TIME – SPACE CONVERTER ..................................................................................................................................................... 10
VIDEO PROCESSING ...................................................................................................................................................................... 10
ANALOG AND DIGITAL OUTPUT ...................................................................................................................................................... 11
MEMORY CONTROLLER ................................................................................................................................................................. 11
PLL AND OSCILLATOR .................................................................................................................................................................... 11
HOST BUS INTERFACE ................................................................................................................................................................... 11
OSD ............................................................................................................................................................................................... 12
CLOCK RECOVERY CIRCUITS ........................................................................................................................................................ 12
APPLICATION NOTES .................................................................................................................................................................. 13
ADC PIN CONNECTION.................................................................................................................................................................. 13
CRYSTAL PIN.................................................................................................................................................................................. 14
VIDEO PORT USAGE .................................................................................................................................................................... 16
BOARD MEMORY CONNECTION: ............................................................................................................................................. 24
ELECTRICAL CHARACTERISTICS ........................................................................................................................................... 29
ABSOLUTE MAXIMUM RATINGS...................................................................................................................................................... 29
DC CHARACTERISTICS .................................................................................................................................................................. 30
AC CHARACTERISTICS .................................................................................................................................................................. 32
MEMORY INTERFACE AC CHARACTERISTICS................................................................................................................................ 34
DAC CHARACTERISTICS................................................................................................................................................................ 38
ADC CHARACTERISTICS................................................................................................................................................................ 39
PACKAGE DIMENSIONS .................................................................................................................................................................. 40
CONTACT INFORMATION ........................................................................................................................................................... 41

http://www.tvia.com
Tel: 86-756-3628728 Email: sales@tvia.com iii DS-5725-3.2
TRUEVIEWTM 5725

Table of Figures
Figure 1: Block Diagram .................................................................................................................................................... 1
Figure 2: OSD Icons ........................................................................................................................................................ 12
Figure 3: Example ADC Signal Connection .................................................................................................................... 13
Figure 4: Crystal Connection Diagram ............................................................................................................................ 14
Figure 5: External Clock Drive Configuration .................................................................................................................. 14
Figure 6: Internal Driver Configuration ............................................................................................................................ 15
Figure 7: Digital 24-bit YUV/RGB Input with Analog Output Mode ................................................................................. 17
Figure 8: Digital 16-bit YUV 4:2:2 Input with Analog Output Mode ................................................................................. 18
Figure 9: Digital 8-bit 601/656 4:2:2 YUV Input with Analog Output Mode ..................................................................... 19
Figure 10: Analog YUV/RGB Input with Analog Output Mode ........................................................................................ 20
Figure 11: Digital 8-bit 601/656 4:2:2 YUV Input with 16bit Digital Output ..................................................................... 21
Figure 12: Analog RGB/YUV Input with 16bit Digital Output Mode................................................................................. 22
Figure 13: Analog RGB/YUV Input with 24bit Digital Output Mode................................................................................. 23
Figure 14: THREE 1MX16X2BANK MEMORY (1) .......................................................................................................... 24
Figure 15: THREE 1MX16X2BANK MEMORY (2) .......................................................................................................... 25
Figure 16: ONE 1MX16X4BANK MEMORY .................................................................................................................... 26
Figure 17: ONE 512KX32X4BANK MEMORY ................................................................................................................ 27
Figure 18: TWO 1MX16X4BANK MEMORY ................................................................................................................... 28
Figure 19: Video Input Port AC Timing ............................................................................................................................ 32
Figure 20: Video Output Port AC timing .......................................................................................................................... 33
Figure 21: Memory Interface AC Input timing .................................................................................................................. 34
Figure 22: Memory Interface AC output timing ................................................................................................................ 35
Figure 23: Definition of timing for F/S-mode devices on the I²C-bus .............................................................................. 36
Figure 24: Package Dimensions for QFP160 Package ................................................................................................... 40

Table of Tables
Table 1: Digital Video Input Pins ....................................................................................................................................... 4
Table 2: Digital Video Output Pins .................................................................................................................................... 4
Table 3: Analog Video input Pins ...................................................................................................................................... 5
Table 4: Analog Video Output Interface Pins .................................................................................................................... 6
Table 5: Clock Generation Pins ......................................................................................................................................... 6
Table 6: System Interface Pins.......................................................................................................................................... 6
Table 7: SDRAM Interface Pins......................................................................................................................................... 7
Table 8: Digital Power and Ground Pins ........................................................................................................................... 8
Table 9: Numerical Pin List ................................................................................................................................................ 9
Table 10: I²C Slave Addresses ........................................................................................................................................ 12
Table 11: Over sampling ratio ......................................................................................................................................... 12
Table 12: Absolute Maximum Ratings ............................................................................................................................. 29
Table 13: DC Characteristics........................................................................................................................................... 30
Table 14: Video Input Port AC Timing ............................................................................................................................. 32
Table 15: Video Output Port AC timing ........................................................................................................................... 33
Table 16: Memory Interface AC Input timing ................................................................................................................... 34
Table 17: Memory Interface AC output timing ................................................................................................................. 35
Table 18: Characteristics of the SDA and SCL bus lines for F/S-mode I²C-bus devices................................................ 37
Table 19: DAC Characteristics ........................................................................................................................................ 38
Table 20: ADC Characteristics ........................................................................................................................................ 39

http://www.tvia.com
Tel: 86-756-3628728 Email: sales@tvia.com iv DS-5725-3.2
TRUEVIEWTM 5725

INTRODUCTION
The TrueView5725 is a low pin count, low-cost
advanced and highly integrated Digital and Analog
Video Display Processor providing the key features
needed to design HD-READY, Progressive scan or
LCD Televisions
TrueView5725 accepts interlaced or progressive video
input and graphic input such as NTSC/PAL,
1080i/720p, and SXGA, etc. in both analog and digital
channels. It provides a high quality display output. It is
capable of advanced de-interlacing, video
enhancement, advanced 3D noise reduction, Y/C
cross talk suppression and frame rate conversion. It
also provides superior video output quality.
It integrates a complete triple 8-bit pipeline ADC with a
clock-recovery and sync separation circuit to generate
the sampling clock from HSYNC. In applications where
the analog outputs are used the 24-bit digital pins can
be inputs if the pins are not used for digital output.
With the high quality video DACs, the video stream is
displayed through its de-interlaced RGB/YPbPr
outputs.
The I²C host interface enables OEMs to select from
many different CPU’s in order to meet their system
and technical requirements.
OEMs can easily design a very low cost solution, while
minimizing their software development time by
leveraging on TrueView5725’s level of integration and
software support.
TrueView5725 provides 3D motion adaptive de-
interlacing with diagonal edge detection. It performs
high quality line doubling and high-accuracy non-linear
motion estimation. It performs pixel based motion
detection using two-field buffers. The Video De-
interlacing Processor automatically detects noise level
and can respond to different noise thresholds. It can
also automatically detect input modes such as still
images, 3:2 / 2:2 films and provide adaptive
processing.

Figure 1: Block Diagram

External
Reset Reset External Memory Controller
Logic

OSD
8/16/24-bit
digital input *
16/24 bit
Analog 3 m
m 3D timing Video
digital out *
Analog 2 u ADC Input De-
u space Enhancment HSOUT
Analog 1 x Formatter interlace /Output
x conversion
Formatter VSOUT
HS HBOUT
VBOUT
Clock-Recovery VS
Circuit

HSYNC2 Mux
VSYNC2 SYNC
processor
HSYNC1 Serial Host Interface
VSYNC1 R/V
Quad B/U
DAC G/Y
XTIN Crystal
PLL SVM
XTOUT OSC

* digital input/outputs pins are shared. They can be inputs our

outputs but not simultaneously SCL SDA SA INT
http://www.tvia.com
Tel: 86-756-3628728 Email: sales@tvia.com 1 DS-5725-3.2
TRUEVIEWTM 5725

FEATURES
 Analog Input Formatter
 Max three channel analog inputs  Memory Controller
 RGB/YCbCr/YPbPr input  2-8Mbyte memory support
 Analog input range: 0.5V – 1.0V (p-p)  16/32bit data access
 Programmable gain/offset controls
 Video enhancement
 DC or AC coupling inputs
 Internal sync separator to support SOG/SOY  Black Level Expansion (BLE)
 SXGA (1280x1024@75Hz) at 135MHz  White Level Expansion (WLE)
 HDTV up to 1080p  Color Transition Improvement (DCTI)
 Macrovision input detection  Dynamic Range expansion
 Brightness, Saturation, Contrast, HUE
 Triple 8-bit ADC  Dynamic 2D Peaking
 Maximum analog sampling rate up to 162MSPS  2D coring
 3D noise reduction
 Clock-recovery Circuit  Scan Velocity Modulation (SVM)
 Programmable phase adjustment cells  2D Nonlinear scaling
 HSYNC frequency range is from 15KHz to 110KHz  Primary Color Enhancement
 Skin Tone Enhancement
 Digital Input Formatter  Blue Stretch
 24bit RGB/YUV input
 8/16bit YUV input  OSD
 8bit 656/601 input  Simple OSD generator to support component
 NTSC/PAL input video inputs
 480p, 576p input
 VGA/SVGA/XVGA input  Host Interface and I/O
 720p, 1080i, 1080p HD input  Two-wire I²C interface
 Support DVI interface  GPIO

 Output formatter  Quadruple 10bit DAC

 480p, 576p, 720p, 1080i, 1080p
 Package and Technology
 Up to SXGA graphic output formats
 100/120 interlace double scan  160-pin QFP 28*28mm
 75Hz interlace single scan  0.18 micron, 3.3V / 1.8V technology
 50-75Hz scan rate conversion
 15~80KHz horizontal frequency Note: All packages are lead-free and RoHS compliant.
 16bit YPbPr digital output with syncs
 24bit YPbPr/RGB digital output with syncs

 De-interlace
 HD 1080i support
 SD NTSC/PAL
 Direct Edge Correction De-interlace
 Motion Detection
 Edge Detection
 Mode Detection
 Noise Detection
 3:2/2:2 pull-down detection
http://www.tvia.com
Tel: 86-756-3628728 Email: sales@tvia.com 2 DS-5725-3.2
TRUEVIEWTM 5725

PINOUT DIAGRAM

PIN DIAGRAM FOR QFP160

XTOUT
DQM1#
DAVD

ASVM

PVDD

PVDD
DAVS

MD16
PVDD

MD17

PAVD
MD24
MD23

MD22

MD21
MD27

MD30

MD31
MD19
MD29
MD18
MD25

MD26

MD20
MD28
DVSS

PAVS
AGPb

PVSS

PVSS
PVSS

XTIN
AGPr

MA2
AGY

IREF

MA3

MA4
VDD
VSS
158
157
156
155
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
160
159

154

HSOUT 1 120 MA1

VSOUT 2 119 MA5
PVDD 3 PIN 1 118 MA0
CLKOUT 4 IDENTIFIER 117 MA6
PVSS 5 116 MA10
HBOUT 6 115 MA7
VBOUT 7 114 MA8
VB0 8 113 PVSS
VB1 9 112 PVDD
VB2 10 111 MA9
VB3 11 110 FBCLK
PVDD 12 109 MCS1#
PVSS 13 108 MCS0#
VB4 14 107 MBA
VB5 15 106 RAS#
VDD 16 105 PVSS
VSS 17 104 MCLK
VB6
VB7
VG0
VG1
18
19
20
TrueView 5725 103
102
101
PVDD
VDD
VSS
21 100 CAS#
VG2
VG3
PVDD
22
23
24
(QFP160) 99
98
WE#
DQM0#
97 MD8
PVSS 25 96 MD7
VG4 26 95 MD10
VG5 27 94 MD9
VG6 28 93 PVSS
VG7 29 92 PVDD
VR0 30 91 MD6
VR1 31 90 MD5
VR2 32 89 MD11
VR3 33 88 MD4
PVDD 34 87 MD12
PVSS 35 86 MD3
VR4 36 85 MD13
VR5 37 84 MD2
VR6 38 83 PVSS
VR7 39 82 PVDD
PCLKIN 40 81 MD14
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
HSIN1
VSIN1

AVD_PLL

GPIO
SCLDA

HSIN2
VSIN2

FILT
SCLCK

MD1
AVS_PLL
SCLSA

AVS_B

AVS_B

AVS_B

HALF
MD0
AVS_REF

MD15
REFBP

RSTN
B0

B1

B2
G1
AVD_REF

G2
AVD_R

AVD_B
R0

R1

AVD_G

AVS_G
AVS_G
AVS_R

AVS_R

SOG1
SOG0
G0
R2

http://www.tvia.com
Tel: 86-756-3628728 Email: sales@tvia.com 3 DS-5725-3.2
TRUEVIEWTM 5725

PIN DESCRIPTION

Table 1: Digital Video Input Pins

Pin Name QFP160 Pin # Type Pin Description

PCLKIN 40 IPD Digital input video clock
Digital input video H-sync
HSIN1 44 I Shared with Analog input video H-sync1
Digital input video V-sync
VSIN1 45 I
Shared with Analog input video V-sync1
Video Green Input data.
 G data for 24bit RGB mode.
 Y data for 4:4:4 mode
VG [7:0] 29~26, 23~20 IOPD
 YUV data for 8bit 4:2:2 YUV mode.
 Y/G data for 24bit input
Shared with digital video output data
Video Blue Input data.
 B data for 24bit RGB mode.
 U data for 4:4:4 YUV mode.
VB [7:0] 19~18, 15~14, 11~8 IOPD  UV data for 16bit 4:2:2 YUV mode.
 U/B data for 24bit input.
 Y data for 16bit input.
Shared with digital video output data
Video Red Input data.
 R data for 24bit RGB mode.
 V data for 4:4:4 mode.
VR [7:0] 39~36, 33~30 IOPD  Y data for 16bit 4:2:2 mode.
 V/R data for 24bit input
 U/V data for 16bit input
Shared with digital video output data
Display enable input from DVI/HDMI decoder
CLKOUT 4 IO
Shared with video clock output & GPIO bit 7
Input H-sync for digital input mode
HSOUT 1 IO
Shared with H-sync output
Input V-sync for digital input mode
VSOUT 2 IO
Shared with V-sync output
Half tone input
HALF 77 IOPD
Shared with GPIO bit 1

Table 2: Digital Video Output Pins

Pin Name QFP160 Pin # Type Pin Description

Digital video display output clock
CLKOUT 4 IO Shared with display enable input & GPIO bit 7
Digital video display output H-sync
HSOUT 1 IO
Shared with H-sync input for digital input mode
Digital video display output V-sync
VSOUT 2 IO
Shared with V-sync output for digital input mode

http://www.tvia.com
Tel: 86-756-3628728 Email: sales@tvia.com 4 DS-5725-3.2
TRUEVIEWTM 5725

Display enable output in LCD application

VBOUT 7 IO
Shared with GPIO bit 6 and V-blank output
 Y/G data for 24bit digital output.
VG [7:0] 29~26, 23~20 IOPD
Shared with digital video input data
 UV data for 16bit digital output.
VB [7:0] 19~18, 15~14, 11~8 IOPD  R/V data for 24bit digital output.
Shared with digital video input data
 Y data for 16bit digital output.
VR [7:0] 39~36, 33~30 IOPD  B/U data for 24bit digital output.
Shared with digital video input data

Table 3: Analog Video input Pins

Pin Name QFP160 Pin # Type Pin Description

Analog video input H-sync1
HSIN1 44 I Shared with digital video input H-sync
Analog video input V-sync1
VSIN1 45 I Shared with digital video input V-sync
HSIN2 46 I Analog video input H-sync2
VSIN2 47 I Analog video input V-sync2
SOG0 61 AI Green input 0 for Sync-On-Green sync tip clamping
SOG1 64 AI Green input 1 for Sync-On-Green sync tip clamping
R0 55 AI Analog input for Red input channel 0
G0 62 AI Analog input for Green input channel 0
B0 69 AI Analog input for Blue input channel 0
R1 57 AI Analog input for Red input channel 1
G1 65 AI Analog input for Green input channel 1
B1 71 AI Analog input for Blue input channel 1
R2 59 AI Analog input for Red input channel 2
G2 67 AI Analog input for Green input channel 2
B2 73 AI Analog input for Blue input channel 2
REFBP 52 AI Internal reference bypass
AVD_R 54 AP Analog power (3.3V)
AVS_R 56, 58 AG Analog ground
AVD_G 60 AP Analog power (3.3V)
AVS_G 63, 66 AG Analog ground
AVD_B 68 AP Analog power (3.3V)
AVS_B 70, 72, 74 AG Analog ground
AVD_REF 51 AP Analog power (3.3V)
AVS_REF 53 AG Analog ground
AVD_PLL 48 AP Analog power (3.3V) for PLLAD
FILT 49 AI Connection for External Filters components for PLLAD
AVS_PLL 50 AG Analog ground for PLLAD

http://www.tvia.com
Tel: 86-756-3628728 Email: sales@tvia.com 5 DS-5725-3.2
TRUEVIEWTM 5725

Table 4: Analog Video Output Interface Pins

Pin Name QFP160 Pin # Type Pin Description

Analog video display output H-sync
HSOUT 1 IO
Shared with H-sync input for digital input mode
Analog video display output V-sync
VSOUT 2 IO
Shared with V-sync output for digital input mode
Analog video display output H-Blank
HBOUT 6 IO
Shared with GPIO bit 5
Analog video display output V-Blank
VBOUT 7 IO Shared with GPIO bit 6 and DE output for digital
video output
AGPb 158 AO Analog Blue/Pb output
AGY 159 AO Analog Green/Y output
AGPr 160 AO Analog Red/Pr output
ASVM 154 AO Analog SVM output
IREF 155 AI Full-scale adjust resistor
DVSS 153 AG Big current GND
DAVS 156 AG Analog ground for DAC
DAVD 157 AP Analog power for DAC

Table 5: Clock Generation Pins

Pin Name QFP160 Pin # Type Pin Description

XTOUT 125 O External crystal output.
XTIN 124 I External crystal input.
PAVD 121 AP Analog power (3.3V) for PLL648
PAVS 122 AG Analog ground for PLL648

Table 6: System Interface Pins

Pin Name QFP160 Pin # Type Pin Description

Serial bus slave address selection,
SCLSA 43 IOPU
Shared with GPIO bit 2
SCLCK 41 I Serial bus clock
SCLDA 42 IO Serial bus data
RSTN 75 I External asynchronous reset, low active
GPIO bit 0
GPIO 76 IOPD Shared with Interrupt Output, low active

http://www.tvia.com
Tel: 86-756-3628728 Email: sales@tvia.com 6 DS-5725-3.2
TRUEVIEWTM 5725

Table 7: SDRAM Interface Pins

Pin Name QFP160 Pin # Type Pin Description

MD31 132 IOPD
MD30 134 IOPD
MD29 138 IOPD
MD28 140 IOPD
MD27 144 IOPD
MD26 146 IOPD
MD25 150 IOPD
MD24 152 IOPD
MD23 151 IOPD
MD22 149 IOPD
MD21 145 IOPD
MD20 141 IOPD
MD19 139 IOPD
MD18 137 IOPD
MD17 133 IOPD
MD16 131 IOPD
Memory Data Bus [31:0]
MD15 79 IOPD
MD14 81 IOPD
MD13 85 IOPD
MD12 87 IOPD
MD11 89 IOPD
MD10 95 IOPD
MD9 94 IOPD
MD8 97 IOPD
MD7 96 IOPD
MD6 91 IOPD
MD5 90 IOPD
MD4 88 IOPD
MD3 86 IOPD
MD2 84 IOPD
MD1 80 IOPD
MD0 78 IOPD
DQM0# 98 O Memory data qualify signal 0
DQM1# 130 O Memory data qualify signal 1
MCLK 104 O SDRAM clock
WE# 99 O Write enable control for SDRAM
RAS# 106 O Row address strobe
CAS# 100 O Column address strobe
Feed back clock for SDRAM
FBCLK 110 IOPD Chip Selection 2 for 6MByte external memory
MBA 107 IOPD SDRAM bank select Shared with GPIO bit 3
http://www.tvia.com
Tel: 86-756-3628728 Email: sales@tvia.com 7 DS-5725-3.2
TRUEVIEWTM 5725

Pin Name QFP160 Pin # Type Pin Description

Memory chip Selection 1,
MCS1# 109 IOPD
And shared with GPIO bit 4.
MCS0# 108 IOPD Memory chip Selection 0
MA10 116 IOPD
MA9 111 IOPD
MA8 114 IOPD
MA7 115 IOPD
MA6 117 IOPD
MA5 119 IOPD Memory address bus [10:0]
MA4 127 IOPD
MA3 129 IOPD
MA2 128 IOPD
MA1 120 IOPD
MA0 118 IOPD

Table 8: Digital Power and Ground Pins

Pin Name QFP160 Pin # Type Pin Description

VSS 17,101,143 DG Core Power GND
VDD 16,102,142 DP 1.8V Core Power
3, 12, 24, 34, 82, 92, 3.3V I/O Power
PVDD DP
103, 112, 123, 135, 147,
5, 13, 25, 35, 83, 93,
PVSS DG I/O GND
105, 113, 126, 136, 148

Pin types include the following:

 I Digital Input
 IPD Digital Input with pull-down
 O Digital Output
 OPD Digital Output with pull-down
 IO Digital Bi-directional (input/output)
 IOPU Digital Bi-directional (input/output) with pull-up
 IOPD Digital Bi-directional (input/output) with pull-down
 AI Analog Input
 AO Analog Output
 DP Digital Power
 DG Digital Ground
 AP Analog Power
 AG Analog Ground

http://www.tvia.com
Tel: 86-756-3628728 Email: sales@tvia.com 8 DS-5725-3.2
TRUEVIEWTM 5725

Table 9: Numerical Pin List

Pin Name QFP160 Pin # Pin Name QFP160 Pin # Pin Name QFP160 Pin # Pin Name QFP160 Pin #
HSOUT 1 SCLCK 41 MD14 81 PAVD 121
VSOUT 2 SCLDA 42 PAVS 122
PVDD 82
PVDD SCLSA 43
3 PVDD 123
PVDD HSIN1 44 PVSS 83
CLKOUT 4 VSIN1 45 MD2 84 XTIN 124
PVSS HSIN2 46 MD13 85 XTOUT 125
5
PVSS VSIN2 47 MD3 86 PVSS
126
HBOUT 6 AVD_PLL MD12 87 PVSS
48
VBOUT 7 AVD_PLL MD4 88 MA4 127
VB0 8 FILT 49 MD11 89 MA2 128
VB1 9 AVS_PLL 50 MD5 90 MA3 129
VB2 10 AVD_REF 51 MD6 91 DQM1 130
VB3 11 REFBP 52 PVDD 92 MD16 131
PVDD 12 AVS_REF 53 PVSS 93 MD31 132
PVSS 13 AVD_R MD9 94 MD17 133
54
VB4 14 AVD_R MD10 95 MD30 134
VB5 15 R0 55 MD7 96 PVDD 135
VDD AVS_R 56 MD8 97 PVSS 136
16
VDD R1 57 DQM0 98 MD18 137
VSS 17 AVS_R 58 WE# 99 MD29 138
VB6 18 R2 59 CAS# 100 MD19 139
VB7 19 AVD_G VSS 101 MD28 140
60
VG0 20 AVD_G VDD MD20 141
102
VG1 21 SOG0 61 VDD VDD
142
VG2 22 G0 62 PVDD VDD
103
VG3 23 AVS_G 63 PVDD VSS
143
PVDD 24 SOG1 64 MCLK 104 VSS
PVSS 25 G1 65 PVSS MD27 144
105
VG4 26 AVS_G 66 PVSS MD21 145
VG5 27 G2 67 RAS# 106 MD26 146
VG6 28 AVD_B MBA 107 PVDD 147
68
VG7 29 AVD_B MCS0# 108 PVSS 148
VR0 30 B0 69 MCS1# 109 MD22 149
VR1 31 AVS_B 70 FBCLK 110 MD25 150
VR2 32 B1 71 MA9 111 MD23 151
VR3 33 AVS_B 72 PVDD 112 MD24 152
PVDD B2 73 PVSS 113 DVSS 153
34
PVDD AVS_B 74 MA8 114 ASVM 154
PVSS 35 RSTN 75 MA7 115 IREF 155
VR4 36 GPIO 76 MA10 116 DAVS 156
VR5 37 HALF 77 MA6 117 DAVD 157
VR6 38 MD0 78 MA0 118 AGPb 158
VR7 39 MD15 79 MA5 119 AGY 159
PCLKIN 40 MD1 80 MA1 120 AGPr 160

http://www.tvia.com
Tel: 86-756-3628728 Email: sales@tvia.com 9 DS-5725-3.2
TRUEVIEWTM 5725
FUNCTIONAL DESCRIPTION
The TrueView 5725 TV Display Processor consists of a
number of functional blocks which are described below.
ADC
The ADC can accommodate input signals with inputs
ranging from 0.5V to 1.0V full scale. The full-scale
range is set in three 8-bit registers (Red Gain, Green
Gain, and Blue Gain).
The ADC offset control shifts the input source a DC
level, there are three 7-bit registers (Red Offset, Green
Offset, Blue Offset) available to independently control
each channel, The offset controls provide a  63 LSB
adjustment range. If the input range is 1.0V, the
adjustable range is 0.25V. Every step is 4mV (0.25 /
63 = 0.004V). If the input range is 0.5V, the adjustable
range is 0.125V. Every step is 2mV (0.125 / 63 =
0.002V).
The ADC has three input data channels, two SOG
input channels and two separate H/V-sync input
channels. It also generates an over-sampling clock
from H-sync with a frequency range from lower than
10MHz up to 162Mhz.
INPUT FORMATTER
The Input Formatter accepts video data in several
formats.
- 24-bit YCbCr or RGB
- 4:4:4 or 4:2:2
- 8 bit ITU-R BT.656
- 8 or 16 or 24 bit ITU-R BT.601
- NTSC or PAL
- 24 bit VGA (800*525@60Hz), SVGA, XGA and
SXGA
- 1080i, 720p, 1080p, HD
The True View 5725 can automatically detect all
supported monitor and TV modes including NTSC,
PAL, VGA, SVGA, XGA, SXGA and HD modes and
their supported refresh rate.
DE-INTERLACER
The TrueView5725 Motion Adaptive De-interlacer
automatically determines the type of
http://www.tvia.com
Tel: 86-756-3628728 Email: sales@tvia.com
incoming video content such as film, static interlaced or
moving interlaced video. Different algorithms are
applied for each content type. The de-interlacer
produces a progressive scan video output. Noise
which otherwise would be seen as motion can be
removed during motion processing. It also uses an
edge detection algorithm that enables the smoothing of
jagged edges that could occur in the de-interlacing
process. Several different detection angles can be
programmed.
FILM MODE
The De-interlace Processor can detect video that has
originated from film and detects 3:2 or 2:2 pull down. If
film originated video is detected the two fields from the
original frame are combined into one progressive
frame.
Thirty frames per second interlaced video can be
output as 60 or 72Hz progressive frames.
Twenty-five frames per second interlaced video can be
output as 50 or 75Hz progressive frames, or 100Hz-
interlaced fields.
The de-interlacer continuously monitors the incoming
video to detect any changes to the pull-down sequence.
If a change is detected the deinterlacer quickly adapts
its de-interlacing algorithm to compensate.
3D TIME – SPACE CONVERTER
The 3D Time – Space converter is used to alter the
size of the picture depending on the output resolution.
It contains an Up-Down scaler and Rate converter.
VIDEO PROCESSING
The Video Enhancer is a high-quality programmable
processor that brings out details and color in the video.
Output Formatter
The Output formatter formats the output to give the
required levels for RGB or YPbPr. It contains a 2X
interpolator to increase sharpness that results from a
smaller aperture.
10 DS-5725-3.2
TRUEVIEWTM 5725
Transient Improvement
Digital Chroma Transient improvement (DCTI)
improves video by replacing slower edges of the video
with edges that have steeper rise and fall times. DCTI
turns sloped or sinusoidal waveforms into rectangular
or square waveforms with the same duty cycles and
peak-to-peak amplitude. It improves the color
transitions of vertical objects and reduces color
smearing introduced by a video decoder.
Black & white Level Expansion
The black and white-level expander enhances the
contrast of the picture. The luminance signal is
modified with an adjustable, non-linear function. Dark
areas of the picture are made blacker, while bright
areas of the picture are made whiter.
2D Peaking
Especially if the input signals are decoded composite
signals and a notch filter has been used for
luminance/color separation, it is necessary to improve
the luminance/color frequency characteristics. The
TrueView5725 2D peaking process uses edge
enhancement to improve the Y and C sharpness in the
vertical and horizontal directions. For Y, there is 2D
peaking and for UV, there is only vertical peaking.
Skin tone correction
Skin tone correction is used to alter skin color to make
it look more natural.
Non-linear saturation
Non-linear saturation is used to enhance the saturation
of some colors without affecting other colors. Both the
Y and UV parameters of the range of colors to be
enhanced are programmable.
Brightness and Contrast
Brightness and contrast can be programmed by
adjusting the offset and gain of the video signal.
Contrast is adjusted by multiplying the luminance by a
constant. Brightness is adjusted by adding or
subtracting a constant, from the luminance value.
Saturation
Saturation can be changed by changing the UV gain of
the color signal
Hue
The Hue of the color can be changed by rotating the
http://www.tvia.com
Tel: 86-756-3628728 Email: sales@tvia.com
UV vectors in either direction.
Background Noise Reduction
Background noise reduction is a process that uses a
digital filtering algorithm on the digital image data to
reduce the amount of random noise such as RF noise
or comb filter artifacts in composite video sources etc.
It is 3D motion adaptive and pixel based
Scan Velocity Modulation
The Scan Velocity Modulation (SVM) output is used to
modulate the horizontal CRT scan timing. It has the
effect of sharpening the transitions from dark to light
and light to dark which results in a clearer sharper
picture.
ANALOG AND DIGITAL OUTPUT
The Analog Display Port generates the analog RGB or
YPbPr with triple Digital-to-Analog Converters (DACs).
The DAC’s have 10-bit quality. The analog RGB or
YPbPr output is generated in synchronization with H
and V timing signals. The 16-bit YCbCr digital output is
ITU-R BT.601 compatible with a 1 X clock. The output
comes from the 3D time-space converter block and is
in 4:2:2 format.
MEMORY CONTROLLER
The internal Memory Controller supports the
addressing and control of up to 8MB of external
SDRAM. The external SDRAM memory buffer is used
to store video fields and motion data. The Memory
Controller also supports frame rate up-conversion with
different input and output refresh rates.
PLL AND OSCILLATOR
The TrueView 5725 integrates a PLL to generate the
MCLK to the Memory interface and the VCLK to the
display. Only an external crystal is required to be
connected between the XTIN and XTOUT pins. On
power-up, the PLL is initialized to provide a 108 MHz
MCLK and a 27 MHz VCLK when a 27MHz reference
is used. Alternatively, the MCLK and VCLK can be
driven directly by external clocks.
HOST BUS INTERFACE
Access to the TrueView 5725 registers is provided by
an I²C 2-wire serial bus interface. The Interface
11 DS-5725-3.2
TRUEVIEWTM 5725

supports standard and fast modes, up to 400kbits/S. relationship of the KS and CKOS register
Only slave mode is supported in the TrueView 5725 TV values.
Display Processor.
The slave address is hardware selectable.
Table 11: Over sampling ratio
Table 10: I²C Slave Addresses
KS CKOS OSR
TrueView 5725 I²C slave addresses 00 00 1
Read Write 00 2
2F 2E 01
AF AE 01 1

00 4
OSD 10 01 2

The TrueView 5725 OSD engine is a simple eight icon, 10 1

hardware graphic engine. It consists of eight 13x13
hard-wired OSD ROM locations containing the most
common TV OSD symbols. Brightness, contrast, hue,
sound, up/down adjustment, left/right adjustment,
horizontal size adjustment, and vertical size adjustment.
Figure 2: OSD Icons

One of eight foreground and background colors can be

selected and they can be zoomed in the horizontal or
vertical direction up to eight times horizontally and four
times vertically.

CLOCK RECOVERY CIRCUITS

The clock recovery circuit generates the ADC
sampling clock and its over-sampling clock up
to 162Mhz.The hsync signal can also be
recovered from the PLL even when the input
clock reference is a composite sync signal.
This is achieved by sending a COAST high
signal to the PLL to disable the PLL from
tracking the input reference and to maintain
the PLL output clock frequency if the input
reference is not a regular period hsync signal.
FS, KS and ICP registers are used to optimize
the PLL performance for each specific video
format. The CKOS register is used to control
the over-sampling ratio. The following table
gives the possible over-sampling cases. The
over sampling ratio is determined by the

http://www.tvia.com
Tel: 86-756-3628728 Email: sales@tvia.com 12 DS-5725-3.2
TRUEVIEWTM 5725

APPLICATION NOTES

ADC PIN CONNECTION

The analog RGB signals are connected to the TrueView5725 as shown below:

Figure 3: Example ADC Signal Connection

http://www.tvia.com
Tel: 86-756-3628728 Email: sales@tvia.com 13 DS-5725-3.2
TRUEVIEWTM 5725

CRYSTAL PIN
1. EXTERNAL

XTIN and XTOUT are the input and output, respectively, of an inverting amplifier, which can be configured for use as
an on-chip oscillator, as shown below. A 27 MHz crystal is preferred. In addition to an external crystal, the oscillator
requires two external capacitors and an external feedback resistor.

XTIN

15pF

27MHz
1M TV5725

XTOUT

15pF

Figure 4: Crystal Connection Diagram

To drive the device from an external clock source, XTIN should be driven, while XTOUT floats, as shown below.

EXTERNAL
OSCILLATOR SIGNAL
XTIN

TV5725

N/C
XTOUT

Figure 5: External Clock Drive Configuration

http://www.tvia.com
Tel: 86-756-3628728 Email: sales@tvia.com 14 DS-5725-3.2
TRUEVIEWTM 5725

2. INTERNAL

C[2:0] are register bits, for changing the clock driver drive capability. The default value is 0 as shown below.
SMT_EN_O is the register bit to select between a TTL or Schmitt trigger input buffer.

C[2:0]
TTL
1
IN

SMT 0
TV5725

SMT_EN_O

XTIN XTOUT

Figure 6: Internal Driver Configuration

http://www.tvia.com
Tel: 86-756-3628728 Email: sales@tvia.com 15 DS-5725-3.2
TRUEVIEWTM 5725

VIDEO PORT USAGE

The TrueView 5725 has both analog and digital video input ports.

For analog input port:

 Three ADC input channels 0, 1, 2
 Two separate sync h/v or composite sync for ADC channels 0, 1, 2
 Two SOG inputs for ADC input channels 0, 1
For analog output port:
 One set of RGBS, H/V-sync, H/V-blank outputs
 It can output sync-on-Y YPbPr or sync-on-green RGB signal
For digital input port:
 One digital 24-bit input port
 8-bit 601/656 YUV, 16-bit YUV, 24-bit YUV/RGB input
 De-in (display enable input) signal
For digital output port:
 Shared with 24-bit digital input port
 16-bit YUV, 24-bit YUV/RGB.
 De-out (display enable output) signal
 H/V-sync and pixel clock
 H/V Blank <-------------Note: H/V blank could be used for letter-box mode and pillar-box mode

The following pages show the port usage and corresponding register programming:

http://www.tvia.com
Tel: 86-756-3628728 Email: sales@tvia.com 16 DS-5725-3.2
 http://www.tvia.com
System Solution 1: Digital 24-bit YUV/RGB Input with Analog Output Mode

AGPb:
TRUEVIEWTM 5725

VB[7:0]: Pin158 5725 Key Register Setting

Pin[19,18,15,14,11,10,9,8]
AGY: Register Name Address Value
Pin159

Tel: 86-756-3628728 Email: sales@tvia.com

VG[7:0]: pad_bout_en Reg_S0_48[0] 1'b0
Pin[29,28,27,26,23,22,21,20] 1'b
AGPr: pad_bin_enz Reg_S0_48[1]
VR[7:0]: Pin160 0
pad_rout_en Reg_S0_48[2] 1'b
Pin[39,38,37,36,33,32,31,30] ASVM: 0
Pin154 pad_rin_enz Reg_S0_48[3] 1'b
PCLKIN: 0
1'b
Pin40 TrueView 5725 HSOUT: pad_gout_en Reg_S0_48[4]
0
1'b
HSIN1: Pin1 pad_gin_enz Reg_S0_48[5]
Pin44
0
1'b
VSOUT: pad_ckout_enz Reg_S0_49[1]

17
Pin2 1
1'b
VSIN1: pad_sync_out_enz Reg_S0_49[2]
Pin45 HBOUT: 0
1'b
Pin6 pad_blk_out_enz Reg_S0_49[3]
CLKOUT: 0
1'b
Pin4 VBOUT: vds_do_16b_en Reg_S3_50[7]
Pin7 0
1'b
out_blank_sel_0 Reg_S0_50[0]
0
if_sel_adc_sync 1'b
Reg_S1_28[2]
0
if_sel_656 Reg_S1_00[3] 1'b
0
Input Pin Description Output Pin Description if_sel16bit Reg_S1_00[4] X
VB[7:0] Digital Blue/U data input AGPb Analog Blue/Pb output Reg_S1_01[7] 1'b
if_sel24bit
VG[7:0] Digital Green/Y data input AGY Analog Green/Y output 1
Figure 7: Digital 24-bit YUV/RGB Input with Analog Output Mode

VR[7:0] Digital Red/V data input AGPr Analog Red/Pr output Note: "X" means either "0" or "1" is OK.
PCLKIN Pixel clock input ASVM Analog SVM output
HSIN1 Video H-sync input HSOUT Video H-sync output
VSIN1 Video V-sync input VSOUT Video V-sync output
CLKOUT DE input from DVI/HDMI HBOUT Video H-blank output
VBOUT Video V-blank output

DS-5725-3.2
 System Solution 2: Digital 16-bit YUV 4:2:2 Input with Analog Output Mode

http://www.tvia.com
AGPb: 5725 Key Register Setting
Pin158
Register Name Address Value
TRUEVIEWTM 5725

VB[7:0]: AGY:
Pin[19,18,15,14,11,10,9,8] pad_bout_en Reg_S0_48[0] 1'b0
Pin159
1'b
pad_bin_enz Reg_S0_48[1]
VR[7:0]: AGPr: 0
1'b

Tel: 86-756-3628728 Email: sales@tvia.com

Pin[39,38,37,36,33,32,31,30] Pin160 pad_rout_en Reg_S0_48[2]
0
1'b
PCLKIN: ASVM: pad_rin_enz Reg_S0_48[3]
Pin40 Pin154 0
pad_gout_en Reg_S0_48[4] X
HSIN1: TrueView 5725 HSOUT: pad_gin_enz Reg_S0_48[5] X
Pin44 Pin1 1'b
VSIN1:
pad_ckout_enz Reg_S0_49[1]
VSOUT: 1
1'b
Pin45 Pin2
pad_sync_out_enz Reg_S0_49[2]
0
1'b
CLKOUT: HBOUT: pad_blk_out_enz Reg_S0_49[3]
Pin4 0

18
Pin6 vds_do_16b_en 1'b
Reg_S3_50[7]
VBOUT: 0
1'b
Pin7 out_blank_sel_0 Reg_S0_50[0]
0
if_sel_adc_sync 1'b
Reg_S1_28[2]
0
if_sel_656 Reg_S1_00[3] 1'b
0
if_sel16bit Reg_S1_00[4] 1'b1
Input Pin Description Output Pin Description
Reg_S1_01[7] 1'b
VB[7:0] Digital UV data input AGPb Analog Blue/Pb output if_sel24bit
0
VR[7:0] Digital Y data input AGY Analog Green/Y output
Note: "X" means either "0" or "1" is OK.
PCLKIN Pixel clock input AGPr Analog Red/Pr output
HSIN1 Video H-sync input ASVM Analog SVM output
Figure 8: Digital 16-bit YUV 4:2:2 Input with Analog Output Mode

VSIN1 Video V-sync input HSOUT Video H-sync output

CLKOUT DE input from DVI/HDMI VSOUT Video V-sync output
HBOUT Video H-blank output
VBOUT Video V-blank output

DS-5725-3.2
 http://www.tvia.com
System Solution 3: Digital 8-bit 601/656 4:2:2 YUV Input with Analog Output Mode
TRUEVIEWTM 5725

AGPb:
Pin158 5725 Key Register Setting
AGY: Register Name Address Value

Tel: 86-756-3628728 Email: sales@tvia.com

Pin159 pad_bout_en Reg_S0_48[0] X
VG[7:0]:
Pin[29,28,27,26,23,22,21,20] AGPr: pad_bin_enz Reg_S0_48[1] X
Pin160
PCLKIN: pad_rout_en Reg_S0_48[2] X
Pin40 ASVM:
Pin154 pad_rin_enz Reg_S0_48[3] X
HSIN1: 1'b
Pin44 TrueView 5725 HSOUT:
pad_gout_en Reg_S0_48[4]
0
1'b
VSIN1: Pin1 pad_gin_enz Reg_S0_48[5]
0
Pin45 VSOUT: pad_ckout_enz Reg_S0_49[1] X

19
Pin2 pad_sync_out_enz Reg_S0_49[2] 1'b
HBOUT: 0
1'b
Pin6 pad_blk_out_enz Reg_S0_49[3]
0
1'b
VBOUT: vds_do_16b_en Reg_S3_50[7]
0
1'b
Pin7
out_blank_sel_0 Reg_S0_50[0]
0
if_sel_adc_sync 1'b
Reg_S1_28[2]
0
if_sel_656 Reg_S1_00[3] Note*
Input Pin Description Output Pin Description if_sel16bit Reg_S1_00[4] 1'b0
VG[7:0] Digital YUV data input AGPb Analog Blue/Pb output Reg_S1_01[7] 1'b
if_sel24bit
Pixel clock input Analog Green/Y output 0
PCLKIN AGY
Note: "X" means either "0" or "1" is OK.
HSIN1 Video H-sync input AGPr Analog Red/Pr output
Note* : if 656 input , set it to 1;
VSIN1
Figure 9: Digital 8-bit 601/656 4:2:2 YUV Input with Analog Output Mode

Video V-sync input ASVM Analog SVM output if 601 input , set it to 0.
HSOUT Video H-sync output
VSOUT Video V-sync output
HBOUT Video H-blank output
VBOUT Video V-blank output

DS-5725-3.2
 System Solution 4: Analog YUV/RGB Input with Analog Output Mode

http://www.tvia.com
AGPb: 5725 Key Register Setting
Pin158
R0/R1/R2: Register Name Address Value
TRUEVIEWTM 5725

Pin55/Pin57/Pin59 AGY:
pad_bout_en Reg_S0_48[0] X
Pin159
G0/G1/G2:
pad_bin_enz Reg_S0_48[1] X
Pin62/Pin65/Pin67 AGPr:
pad_rout_en

Tel: 86-756-3628728 Email: sales@tvia.com

Pin160 Reg_S0_48[2] X
B0/B1/B2:
Pin69/Pin71/Pin73 ASVM: pad_rin_enz Reg_S0_48[3] X
Pin154
pad_gout_en Reg_S0_48[4] X
SOG0/SOG1: TrueView 5725 HSOUT: pad_gin_enz Reg_S0_48[5] X
Pin62/Pin64 Pin1
pad_ckout_enz Reg_S0_49[1] X
HSIN1/HSIN2: VSOUT: 1'b
Pin44/Pin46 Pin2
pad_sync_out_enz Reg_S0_49[2]
0
1'b
VSIN1/VSIN2: HBOUT: pad_blk_out_enz Reg_S0_49[3]
Pin6 0
1'b
Pin45/Pin47

20
vds_do_16b_en Reg_S3_50[7]
VBOUT: 0
1'b
Pin7 out_blank_sel_0 Reg_S0_50[0]
0
if_sel_adc_sync 1'b
Reg_S1_28[2]
1
if_sel_656 Reg_S1_00[3] 1'b
0
if_sel16bit Reg_S1_00[4] X
Input Pin Description Output Pin Description
Reg_S1_01[7] 1'b
R0/R1/R2 Analog R/V input of CHN0/1/2 AGPb Analog Blue/Pb output if_sel24bit
1
G0/G1/G2 Analog G/Y input of CHN0/1/2 AGY Analog Green/Y output Note: "X" means either "0" or "1" is OK.
B0/B1/B2 Analog B/U input of CHN0/1/2 AGPr Analog Red/Pr output
SOG0/SOG1 Analog SOG/Y input of CHN0/1 ASVM Analog SVM output
Figure 10: Analog YUV/RGB Input with Analog Output Mode

HSIN1/HSIN2 Video H-sync input 1/2* HSOUT Video H-sync output

VSIN1/VSIN2 Video V-sync input 1/2* VSOUT Video V-sync output
HBOUT Video H-blank output
VBOUT Video V-blank output
Note*: HSIN1/VSIN1 and HSIN2/VSIN2 could be programmed for analog channel 0/1/2

DS-5725-3.2
 http://www.tvia.com
System Solution 5: Digital 8-bit 601/656 4:2:2 YUV Input with 16bit Digital Output Mode
5725 Key Register Setting
Register Name Address Value
TRUEVIEWTM 5725

VB[7:0]:
Pin[19,18,15,14,11,10,9,8] pad_bout_en Reg_S0_48[0] 1'b1
1'b
VG[7:0]: pad_bin_enz Reg_S0_48[1]

Tel: 86-756-3628728 Email: sales@tvia.com

VR[7:0]: 1
1'b
Pin[29,28,27,26,23,22,21,20] pad_rout_en Reg_S0_48[2]
Pin[39,38,37,36,33,32,31,30]
1
1'b
PCLKIN: pad_rin_enz Reg_S0_48[3]
Pin40 1
1'b
HSOUT: pad_gout_en Reg_S0_48[4]
HSIN1: Pin1 0
1'b
Pin44 TrueView 5725 pad_gin_enz Reg_S0_48[5]
VSOUT:
0
1'b
VSIN1: pad_ckout_enz Reg_S0_49[1]
Pin2 0
1'b
Pin45 pad_sync_out_enz Reg_S0_49[2]
CLKOUT: 0
Pin4 1'b
pad_blk_out_enz Reg_S0_49[3]

21
0
1'b
VBOUT: vds_do_16b_en Reg_S3_50[7]
Pin7 1
1'b
out_blank_sel_0 Reg_S0_50[0]
1
if_sel_adc_sync 1'b
Reg_S1_28[2]
0
if_sel_656 Reg_S1_00[3] 1'b
1
if_sel16bit Reg_S1_00[4] 1'b0
Reg_S1_01[7] 1'b
if_sel24bit
0

Note: "X" means either "0" or "1" is OK.

Input Pin Description Output Pin Description
VG[7:0] Digital YUV data input VB[7:0] Digtial UV data output
Figure 11: Digital 8-bit 601/656 4:2:2 YUV Input with 16bit Digital Output

PCLKIN Pixel clock input VR[7:0] Digital Y data output

HSIN1 Video H-sync input HSOUT Video H-sync output
VSIN1 Video V-sync input VSOUT Video V-sync output
CLKOUT Video display clock output
VBOUT Display enable output for LCD

DS-5725-3.2
 http://www.tvia.com
System Solution 6: Analog RGB/YUV Input with 16bit Digital Output Mode

5725 Key Register Setting

Register Name Address Value
TRUEVIEWTM 5725

R0/R1/R2: VB[7:0]:
Pin55/Pin57/Pin59 Pin[19,18,15,14,11,10,9,8] Reg_S0_48[0]
pad_bout_en 1'b1
G0/G1/G2: 1'b
pad_bin_enz Reg_S0_48[1]

Tel: 86-756-3628728 Email: sales@tvia.com

Pin62/Pin65/Pin67 VR[7:0]: 1
1'b
Pin[39,38,37,36,33,32,31,30]
pad_rout_en Reg_S0_48[2]
B0/B1/B2: 1
1'b
pad_rin_enz Reg_S0_48[3]
Pin69/Pin71/Pin73 1
HSOUT: pad_gout_en Reg_S0_48[4] X
SOG0/SOG1: Pin1
TrueView 5725 pad_gin_enz Reg_S0_48[5] X
Pin62/Pin64 1'b
VSOUT: pad_ckout_enz Reg_S0_49[1]
HSIN1/HSIN2: Pin2 0
1'b
Pin44/Pin46 CLKOUT:
pad_sync_out_enz Reg_S0_49[2]
0
1'b
Pin4

22
VSIN1/VSIN2: pad_blk_out_enz Reg_S0_49[3]
0
1'b
Pin45/Pin47 VBOUT: vds_do_16b_en Reg_S3_50[7]
Pin7 1
1'b
out_blank_sel_0 Reg_S0_50[0]
1
if_sel_adc_sync 1'b
Reg_S1_28[2]
1
if_sel_656 Reg_S1_00[3] X
if_sel16bit Reg_S1_00[4] X
Reg_S1_01[7] 1'b
if_sel24bit
1
Input Pin Description Output Pin Description Note: "X" means either "0" or "1" is OK.
Figure 12: Analog RGB/YUV Input with 16bit Digital Output Mode

R0/R1/R2 Analog R/V input of CHN0/1/2 VB[7:0] Digtial UV data output

G0/G1/G2 Analog G/Y input of CHN0/1/2 VR[7:0] Digital Y data output
B0/B1/B2 Analog B/U input of CHN0/1/2 HSOUT Video H-sync output
SOG0/SOG1 Analog SOG/Y input of CHN1/2 VSOUT Video V-sync output
HSIN1/HSIN2 Video H-sync input 1/2* CLKOUT Video display clock output
VSIN1/VSIN2 Video V-sync input 1/2* VBOUT Display enable output for LCD
Note*: HSIN1/VSIN1 and HSIN2/VSIN2 could be programmed for analog channel 0/1/2

DS-5725-3.2
 System Solution 7: Analog RGB/YUV Input with 24bit Digital Output Mode

http://www.tvia.com
5725 Key Register Setting
Register Name Address Value
R0/R1/R2: VB[7:0]: pad_bout_en Reg_S0_48[0] 1'b1
Pin55/Pin57/Pin59 Pin[19,18,15,14,11,10,9,8] 1'b
TRUEVIEWTM 5725

pad_bin_enz Reg_S0_48[1]
G0/G1/G2: 1
1'b
VR[7:0]: pad_rout_en Reg_S0_48[2]
Pin62/Pin65/Pin67 Pin[39,38,37,36,33,32,31,30] 1
1'b
pad_rin_enz Reg_S0_48[3]
B0/B1/B2:

Tel: 86-756-3628728 Email: sales@tvia.com

VG[7:0]: 1
1'b
Pin69/Pin71/Pin73 pad_gout_en Reg_S0_48[4]
Pin[29,28,27,26,23,22,21,20] 1
1'b
pad_gin_enz Reg_S0_48[5]
SOG0/SOG1: HSOUT: 1
1'b
Pin62/Pin64
TrueView 5725 Pin1
pad_ckout_enz Reg_S0_49[1]
0
1'b
HSIN1/HSIN2: pad_sync_out_enz Reg_S0_49[2]
VSOUT: 0
1'b
Pin44/Pin46 Pin2 pad_blk_out_enz Reg_S0_49[3]
0
1'b
VSIN1/VSIN2: CLKOUT: vds_do_16b_en Reg_S3_50[7]
Pin45/Pin47 Pin4 0
1'b
out_blank_sel_0 Reg_S0_50[0]

23
VBOUT: 1
Pin7 if_sel_adc_sync 1'b
Reg_S1_28[2]
1
if_sel_656 Reg_S1_00[3] 1'b
0
if_sel16bit Reg_S1_00[4] X
Reg_S1_01[7] 1'b
if_sel24bit 1
Input Pin Description Output Pin Description
R0/R1/R2 Analog R/V input of CHN0/1/2 VB[7:0] Digtial R/V data output
Note: "X" means either "0" or "1" is OK.
G0/G1/G2 Analog G/Y input of CHN0/1/2 VG[7:0] Digtial G/Y data output
B0/B1/B2 Analog B/U input of CHN0/1/2 VR[7:0] Digital B/U data output
SOG0/SOG1 Analog SOG/Y input of CHN1/2 HSOUT Video H-sync output
Figure 13: Analog RGB/YUV Input with 24bit Digital Output Mode

HSIN1/HSIN2 Video H-sync input 1/2* VSOUT Video V-sync output

VSIN1/VSIN2 Video V-sync input 1/2* CLKOUT Video display clock output
VBOUT Display enable output for LCD
Note*: HSIN1/VSIN1 and HSIN2/VSIN2 could be programmed for analog channel 0/1/2

DS-5725-3.2
 http://www.tvia.com
1M x 16 SDRAM 1M x 16 SDRAM
MD15 49 19 BA MD15 49 19 BA
DQ15 BA DQ15 BA
MD14 48 20 MA10 MD14 48 20 MA10
DQ14 A10 DQ14 A10
MD13 46 32 MA9 MD13 46 32 MA9
TRUEVIEWTM 5725

DQ13 A9 DQ13 A9
MD12 45 31 MA8 MD12 45 31 MA8
DQ12 A8 DQ12 A8
MD11 43 30 MA7 MD11 43 30 MA7
DQ11 A7 DQ11 A7
MD10 42 29 MA6 MD10 42 29 MA6
DQ10 A6 DQ10 A6
MD9 40 28 MA5 MD9 40 28 MA5

Tel: 86-756-3628728 Email: sales@tvia.com

DQ9 A5 DQ9 A5
MD8 39 27 MA4 MD8 39 27 MA4
DQ8 A4 DQ8 A4
MD7 12 24 MA3 MD7 12 24 MA3
DQ7 A3 DQ7 A3
MD6 11 23 MA2 MD6 11 23 MA2
DQ6 A2 DQ6 A2
MD5 9 22 MA1 MD5 9 22 MA1
DQ5 A1 DQ5 A1
MD4 8 21 MA0 MD4 8 21 MA0
DQ4 A0 DQ4 A0
MD3 6 MD3 6
DQ3 DQ3
MD2 5 MD2 5
DQ2 DQ2
MD1 3 MD1 3
DQ1 18 CS0# DQ1 18 CS1#
MD0 2 CS MD0 2 CS
DQ0 15 WE# DQ0 15 WE#
WE WE
16 CAS# 16 CAS#

24
CAS CAS
17 RAS# 17 RAS#
RAS RAS
34 PVDD 34 PVDD
CKE CKE
36 DQM1# 36 DQM1#
UDQM UDQM
35 SDCLK 35 SDCLK
CLK CLK
PVDD 14 DQM0# PVDD 14 DQM0#
LDQM LDQM
1 1
VDD1 VDD1
7 4 7 4
VDD2 GND VDD2 GND
13 10 13 10
VDD3 GND VDD3 GND
25 26 25 26
VDD4 GND VDD4 GND
38 41 38 41
VDD5 GND VDD5 GND
Figure 14: THREE 1MX16X2BANK MEMORY (1)

44 47 44 47
BOARD MEMORY CONNECTION:

VDD6 GND VDD6 GND

50 50
GND GND

SDRAM_1MX16X2BANK CHIP0 SDRAM_1MX16X2BANK CHIP1

DS-5725-3.2
 http://www.tvia.com
1M x 16 SDRAM
MD15 49 19 BA
DQ15 BA
MD14 48 20 MA10
TRUEVIEWTM 5725

DQ14 A10
MD13 46 32 MA9
DQ13 A9
MD12 45 31 MA8
DQ12 A8
MD11 43 30 MA7
DQ11 A7
MD10 42 29 MA6

Tel: 86-756-3628728 Email: sales@tvia.com

DQ10 A6
MD9 40 28 MA5
DQ9 A5
MD8 39 27 MA4
DQ8 A4
MD7 12 24 MA3
DQ7 A3
MD6 11 23 MA2
DQ6 A2
MD5 9 22 MA1
DQ5 A1
MD4 8 21 MA0
DQ4 A0
MD3 6
DQ3
MD2 5
DQ2
MD1 3
DQ1 18 FBCLK
MD0 2 CS
DQ0 15 WE#
WE
16 CAS#

25
CAS
17 RAS#
RAS
34 PVDD
CKE
36 DQM1#
UDQM
35 SDCLK
CLK
PVDD 14 DQM0#
LDQM
1
VDD1
7 4
VDD2 GND
13 10
VDD3 GND
25 26
VDD4 GND
38 41
VDD5 GND
44 47
Figure 15: THREE 1MX16X2BANK MEMORY (2)

VDD6 GND
50
GND

SDRAM_1MX16X2BANK CHIP2

DS-5725-3.2
TRUEVIEWTM 5725

Figure 16: ONE 1MX16X4BANK MEMORY

1M x 16 SDRAM 20 CS0#
MD15 53 BA0
DQ15 BA1
21 CS1#
MD14 51
DQ14 35 BA
MD13 50 A11
DQ13 A10
22 MA10
MD12 48
DQ12 34 MA9
MD11 47 A9
DQ11 A8
33 MA8
MD10 45
DQ10 32 MA7
MD9 44 A7
DQ9 A6
31 MA6
MD8 42
DQ8 30 MA5
MD7 13 A5
DQ7 A4
29 MA4
MD6 11
DQ6 26 MA3
MD5 10 A3
DQ5 A2
25 MA2
MD4 8
DQ4 24 MA1
MD3 7 A1
DQ3 A0
23 MA0
MD2 5
DQ2
MD1 4
DQ1 19 GND
MD0 2
DQ0
CS
16 WE#
WE
CAS
17 CAS#
RAS
18 RAS#
CKE
37 PVDD
UDQM
39 DQM1#
CLK
38 SDCLK
PVDD LDQM
15 DQM0#
1
VDD1
3 6
VDD2 GND
9 12
VDD3 GND
14 28
VDD4 GND
27 41
VDD5 GND
49 46
VDD6 GND
43 VDD7 52
GND
54
GND

SDRAM_1MX16X4BANK CHIP

http://www.tvia.com
Tel: 86-756-3628728 Email: sales@tvia.com 26 DS-5725-3.2
TRUEVIEWTM 5725

Figure 17: ONE 512KX32X4BANK MEMORY

2M x 32 SDRAM 22 CS0#
MD15 85 BA0
DQ15 BA1
23 CS1#
MD14 83
DQ14 24 MA10
MD13 82 A10
DQ13 A9 66 MA9
MD12 80
DQ12 65 MA8
MD11 79 A8
DQ11 A7 64 MA7
MD10 77
DQ10 63 MA6
MD9 76 A6
DQ9 A5 62 MA5
MD8 74
DQ8 61 MA4
MD7 13 A4
DQ7 A3 60 MA3
MD6 11
DQ6 27 MA2
MD5 10 A2
DQ5 A1 26 MA1
MD4 8
DQ4 25 MA0
MD3 7 A0
DQ3
MD2 5
DQ2
MD1 4 CS
20 GND
DQ1
MD0 2
DQ0
MD16 31
DQ16 WE 17 WE#
MD17 33
DQ17 CAS 18 CAS#
MD18 34
DQ18 RAS 19 RAS#
MD19 36
DQ19 CKE 67 PVDD
MD20 37
DQ20 DQM1 71 DQM0#
MD21 39
DQ21 CLK 68 SDCLK
MD22 40
DQ22 DQM0 16 DQM0#
MD23 42
DQ23 28 DQM1#
MD24 45 DQM2
DQ24 DQM3 59 DQM1#
MD25 47
DQ25
MD26 48
DQ26
MD27 50
DQ27
MD28 51
DQ28
MD29 53
DQ29 GND
6,12,32,38,44,46
MD30 54
DQ30 GND 52,58,72,78,84,86
MD31 56
DQ31
PVDD
Vss
NC 14,21,30,57,69,70,73

1,3,9,15,29 VDD
35,41,49,55,75,81 VDD

http://www.tvia.com
Tel: 86-756-3628728 Email: sales@tvia.com 27 DS-5725-3.2
 http://www.tvia.com
1M x 16 SDRAM 1M x 16 SDRAM 20 CS0#
20 CS0# MD31 53 BA0
MD15 53 BA0 DQ15 21 CS1#
TRUEVIEWTM 5725

DQ15 21 CS1# MD30 51 BA1

MD14 51 BA1 DQ14 A11 35 BA
DQ14 A11 35 BA MD29 50
MD13 50 22 DQ13 22 MA10
DQ13 A10
MA10 MD28 48 A10
MD12 48 34 DQ12 34 MA9
DQ12 A9
MA9 MD27 47 A9
MD11 47 33 DQ11 33 MA8
DQ11 MA8 MD26 45 A8

Tel: 86-756-3628728 Email: sales@tvia.com

MD10 45 A8 DQ10 32 MA7
DQ10 32 MA7 MD25 44 A7
MD9 44 A7 DQ9 31 MA6
DQ9 31 MA6 MD24 42 A6
MD8 42 A6 DQ8 30 MA5
DQ8 30 MA5 MD23 13 A5
MD7 13 A5 DQ7 29 MA4
DQ7 29 MA4 MD22 11 A4
MD6 11 A4 DQ6 26 MA3
DQ6 26 MA3 MD21 10 A3
MD5 10 A3 DQ5 25 MA2
DQ5 25 MA2 MD20 8 A2
MD4 8 A2 DQ4 24 MA1
DQ4 24 MA1 MD19 7 A1
MD3 7 A1 DQ3 23 MA0
DQ3 23 MA0 MD18 5 A0
MD2 5 A0 DQ2
DQ2 MD16 4
MD1 4 DQ1 19 GND
DQ1 19 GND MD17 2 CS
MD0 2 CS DQ0 16 WE#
DQ0 16 WE# WE
WE 17 CAS#
17 CAS# CAS

28
CAS 18 RAS#
18 RAS# RAS
RAS 37 PVDD
37 PVDD CKE
CKE 39 DQM1#
39 DQM0# UDQM
UDQM 38 SDCLK
38 SDCLK CLK
CLK PVDD 15 DQM1#
PVDD 15 DQM0# LDQM
LDQM
1 1
VDD1 VDD1
3 6 3 6
VDD2 GND VDD2 GND
9 12 9 12
VDD3 GND VDD3 GND
14 28 14 28
VDD4 GND VDD4 GND
27 41 27 41
VDD5 GND VDD5 GND
49 46
Figure 18: TWO 1MX16X4BANK MEMORY

49 46 VDD6 GND
VDD6 GND 43 VDD7 52
43 VDD7 52 GND
GND 54
54 GND
GND

SDRAM_1MX16X4BANK CHIP SDRAM_1MX16X4BANK CHIP

DS-5725-3.2
TRUEVIEWTM 5725

ELECTRICAL CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS

Table 12: Absolute Maximum Ratings

Parameter Symbol Min Max Units Conditions

3.3V Power Supply Voltage 1

VDD - 0.3 4.0 V
(Reference to Ground)

1.8V Power Supply Voltage

VCC - 0.3 2.2 V
(Reference to Ground)
Voltage on any input VI - 0.3 VDD+0.3 V

Storage Temperature TS - 40 125 ℃

Operating temperature To 0 70 ℃

Warning: Stressing the device beyond the “Absolute maximum Ratings” may cause permanent damage.

Notes

1.
TV5725’s 3.3V power supply : PVDD, DAVD, PAVD, AVD_PLL, AVD_REF, AVD_R, AVD_G, AVD_B.

http://www.tvia.com
Tel: 86-756-3628728 Email: sales@tvia.com 29 DS-5725-3.2
TRUEVIEWTM 5725

DC CHARACTERISTICS
Table 13: DC Characteristics

Parameter Symbol Min Typ Max Units Comments

1.8V Power Supply Voltage

VCC 1.71 1.89 V 1.8V Operation
(1.8V±5%)

PVDD, DAVD,
3.3V Power Supply Voltage PAVD, AVD_PLL,
AVD_REF, 3.135 3.465 V 3.3V Operation
(3.3V±5%) AVD_R, AVD_G,
AVD_B

1.8V Supply Current1.a

IVCC 320 mA
(VCC)

3.3V Supply Current1.a

IVDD33 100 mA
(PVDD, PAVD, AVD_PLL)

3.3V Supply Current1.b

(AVD_REF, AVD_R, AVD_G, IAVD 240 mA
AVD_B)

3.3V Supply Current1.c

IDAVD 85 mA
(DAVD)

Input Low Voltage VIL 0 0.8 V

Input High Voltage VIH 2.0 Vcc + 0.3 V

Schmitt Input Low Voltage2 VILS 0 1.0 V

Schmitt Input High Voltage2 VIHS 2.4 Vcc + 0.3 V

Output Low Voltage VOL 0.4 V IOL = 8mA

Output High Voltage VOH 2.4 V IOH = -8mA

Input Capacitance CIN 7 pF

Output Capacitance COUT 7 pF

http://www.tvia.com
Tel: 86-756-3628728 Email: sales@tvia.com 30 DS-5725-3.2
TRUEVIEWTM 5725

Notes

1. Current measured condition:

a. @ HD 1080i, 74.25MHz input, SOG, 162MHz 32bit memory, 108MHz Display clock, VCC is 1.8V.
b. @ UXGA 60Hz, power supply is 3.3V.
c. For VESA Video Levels, the Riref in the board is 160ohms. The output load is double terminated with 75ohms and
0
10pf per channel. Full-scale for all four channels is 0.7V, power supply is 3.3V. Measurement temperature is 25 C.
This is a preliminary measurement and is subject to change by Tvia, Inc.

2. Schmitt trigger PADs (Total: 41 Pads):

HSOUT, VSOUT
CLKOUT
HBOUT, VBOUT
VB[0:7]
VG[0:7]
VR[0:7]
PCLKIN
SCLSA
HSIN1, VSIN1, HSIN2, VSIN2
RSTN
GPIO
HALF
MBA
MCS1#
FBCLK

http://www.tvia.com
Tel: 86-756-3628728 Email: sales@tvia.com 31 DS-5725-3.2
TRUEVIEWTM 5725

AC CHARACTERISTICS
Figure 19: Video Input Port AC Timing

Tc

CLKIN
Thd
Tsud

VR[7:0],VG[7:0],VB[7:0]
Thc
Tsuc
HSIN1,VSIN1, CLKOUT
(CLKOUT is shared as DE input)

Table 14: Video Input Port AC Timing

Parameter Symbol Min Typ Max Units Conditions

VR[7:0], VG[7:0], VB[7:0] Setup Time
Tsud 2 ns
to CLKIN
VR[7:0], VG[7:0], VB[7:0] Hold Time
Thd 5 ns
to CLKIN
HSIN1, VSIN1, CLKOUT Setup Time
Tsuc 2 ns
to CLKIN
HSIN1, VSIN1, CLKOUT Hold Time
Thc 6 ns
to CLKIN

CLKIN Frequency 1/Tmc 80 MHz

http://www.tvia.com
Tel: 86-756-3628728 Email: sales@tvia.com 32 DS-5725-3.2
TRUEVIEWTM 5725

Figure 20: Video Output Port AC timing

Tc

CLKOUT
(REG S0_4F[1] =0)

CLKOUT
(REG S0_4F[1] =1)

Tdd

VR[7:0],VG[7:0],VB[7:0]

Tdc

HSOUT,VSOUT, HBOUT, VBOUT

Table 15: Video Output Port AC timing

Parameter Symbol Min Typ Max Units Conditions

VR[7:0], VG[7:0], VB[7:0] Delay
Tdd -1 1.5 ns 20pF load
Timing from CLKOUT
HSOUT, VSOUT, HBOUT, VBOUT
Thd -1 2.5 ns 20pF load
Delay Timing from CLKOUT

CLKOUT Frequency 1/Tmc 108 MHz 20pF load

http://www.tvia.com
Tel: 86-756-3628728 Email: sales@tvia.com 33 DS-5725-3.2
TRUEVIEWTM 5725

MEMORY INTERFACE AC CHARACTERISTICS

Figure 21: Memory Interface AC Input timing

Tmc

FBCLK
Thd
Tsud

MD[31:0]

Table 16: Memory Interface AC Input timing

Parameter Symbol Min Typ Max Units Conditions

MD[31:0] Setup Time to FBCLK Tsud 2.0 ns

MD[31:0] Hold Time to FBCLK Thd 1.5 ns

FBCLK Frequency 1/Tmc 162 MHz

http://www.tvia.com
Tel: 86-756-3628728 Email: sales@tvia.com 34 DS-5725-3.2
TRUEVIEWTM 5725

Figure 22: Memory Interface AC output timing

Tmc

MCLK
Tdmd

MD[31:0]
Tdma

CS1#, CS0#, MBA, MA[10:0]

Tdmc

RAS#, CAS#, WE#, DQM0#, DQM1#

Table 17: Memory Interface AC output timing

Parameter Symbol Min Typ Max Units Conditions

MD[31:0] Delay Time from MCLK Tdmd 3.7 5.4 ns 20pF load

CS1#, CS0#, MBA, MA[10:0] Delay

Tdma 3.7 5.4 ns 20pF load
Time from MCLK
RAS#, CAS#, WE#, DQM0#, DQM1#
Tdmc 3.7 5.4 ns 20pF load
Delay Time from MCLK

MCLK Frequency 1/Tmc 162 MHz 20pF load

http://www.tvia.com
Tel: 86-756-3628728 Email: sales@tvia.com 35 DS-5725-3.2
TRUEVIEWTM 5725

Figure 23: Definition of timing for F/S-mode devices on the I²C-bus

* Figure 7 Referenced document:

Philips Semiconductors, “The I²C-BUS Specification, version2.1 ---January 2000”
Page33: Fig.31: Definition of timing for F/S-mode devices on the I²C-bus.

http://www.tvia.com
Tel: 86-756-3628728 Email: sales@tvia.com 36 DS-5725-3.2
TRUEVIEWTM 5725

Table 18: Characteristics of the SDA and SCL bus lines for F/S-mode I²C-bus devices

Notes:

1. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the
SCL signal) to bridge the undefined region of the falling edge of SCL.
2. The maximum tHD;DAT has only to be met if the device does not stretch the LOW period ( tLOW ) of the SCL
signal.
3. A Fast-mode I²C-bus device can be used in a Standard-mode I²C-bus system, but the requirement tSU;DAT
250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period
of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next
data bit to the SDA line tr max+ tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I²C-bus
specification) before the SCL line is released.
4. Cb = total capacitance of one bus line in pF.

* Table 17 Referenced document:

Philips Semiconductors, “The I²C-BUS Specification, version2.1 ---January 2011”
Page32: Table 5: Characteristics of the SDA and SCL bus lines for F/S-mode I²C-bus devices¹

http://www.tvia.com
Tel: 86-756-3628728 Email: sales@tvia.com 37 DS-5725-3.2
TRUEVIEWTM 5725

DAC CHARACTERISTICS
Table 19: DAC Characteristics

Parameter Min Typical Max Unit Notes

Resolutions 10 Bits
Number of channels 4
Clock Rate 162 MHz
INL -1.0 +1.0 LSB
DNL -1.0 +1.0 LSB
Full Scale Voltage 665 700 770 mV 1, 2
LSB Current 18.2 uA 1
Monotonicity Guaranteed
RGB Video Output Rise Time
2.6 4.7 ns 3
(10-90% of full-scale)
RGB Video Output Fall Time
2.5 4.0 ns 3
(10-90% of full-scale)

NOTES:

1. For VESA Video Levels, the Riref in the board is 160ohms. The output load is double terminated with 75ohms and 10pf
per channel. Full-scale for all four channels is 0.7V.
2. For good linearity, the full-scale voltage should be less than 1V when the output load is 75ohms and 10pf per channel.
3. As measured with 37.5ohm and 10pf load.

http://www.tvia.com
Tel: 86-756-3628728 Email: sales@tvia.com 38 DS-5725-3.2
TRUEVIEWTM 5725

ADC CHARACTERISTICS
Table 20: ADC Characteristics

Parameter Min Typical Max Unit Notes

Resolutions 8 Bits
Number of channels 3
Sampling Frequency (Fs) 10 162 MHz
Full Scale Adjust Range at RGB Inputs 0.5 1 V 1
Reference Voltage 1.24 V 2
INL +/- 1.2 LSB
DNL +/- 0.8 LSB
No Missing Codes Guaranteed

NOTES:
1. Operation with 8-bit gain controller and 7-bit offset controller.
2. Internal reference voltage output.

http://www.tvia.com
Tel: 86-756-3628728 Email: sales@tvia.com 39 DS-5725-3.2
TRUEVIEWTM 5725

Figure 24: Package Dimensions for QFP160 Package

PACKAGE DIMENSIONS
In Millimeters

Min Typ Max

A1 0.25
A2 3.2 3.32 3.6
L1 1.6REF
b 0.22 0.3 0.38
c 0.09 0.15 0.2
e 0.65 BSC
D1 28
E1 28

Tvia, Inc.
http://www.tvia.com
Tel: 86-756-3628728 E-mail: sales@tvia.com 40 DS-5725-3.1
TRUEVIEWTM 5725

CONTACT INFORMATION

Tvia, Inc., USA Tvia, Inc., Zhuhai China

4800 Great America Parkway, Rm 414, 4F, Bldg D1, NO.1, Software
Suite 405, Road,Tangjia,
Santa Clara, CA 95054 Zhuahai city, Guangdong,
U.S.A. P.R. China
519082

Tel: 408-400-3702
Tel: 86-756-362 8728
Fax: 408-982-8591
Fax: 86-756-362 7758
Email: sales@tvia.com
Email: sales@tvia.com

Copyright Tvia, Inc., 2011 rights reserved. Tvia, Inc. reserves the right to make changes to Tvia products. The content within this document is
subject to change. Customers should contact Tvia, Inc. to verify that they have the most recent documentation.
Tvia and TrueView products are trademarks or registered trademarks of Tvia, Inc. All other trademarks are the properties of the respective owners.

Tvia, Inc.
http://www.tvia.com
Tel: 86-756-3628728 E-mail: sales@tvia.com 41 DS-5725-3.1