Operational Amplifiers and Linear

Library o f Congress Cataloging-in-Publication Data
C o u g h lin , R o b e rt F.
O p e ra tio n a l a m p lifie rs and lin e a r in te g ra te d c irc u its / R o b e rt F. C o u g h lin ,
F re d e ric k F. D risc o ll. — 6th ed.
p. cm .
In c lu d e s b ib lio g ra p h ic a l re fe re n c e s and index.
ISB N 0 -1 3 -0 1 4 9 9 1 -8
1. O p e ra tio n a l am p lifie rs. 2. L in e a r in te g ra te d c irc u its.
I. D risc o ll, F re d e ric k F., II. T itle.
T K 7 8 7 1.5 8 .0 6 C 6 8 2001
6 2 1 .3 8 1 5 — dc21 0 0 -0 4 0 6 3 3
C IP
Vice President and Publisher: Dave Garza

Editor in Chief: Stephen Helba
Acquisitions Editor: Scott J. Sambucci
Production Editor: Rex Davidson
Design C oordinator: Karrie Converse-Jones
C over Designer: Thomas Mack
Cover art: M arjory Dressier
Production M anager: Pat Tonneman
M arketing M anager: Ben Leonard
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Contents
PREFACE XXV
INTRODUCTION TO OP AMPS
Learning Objectives 1
1-0 Introduction 2
1-1 Is There Still a Need for Analog Circuitry? 2

7-7.7 Analog and Digital Systems, 2
7-7.2 Op Amp Development, 3
1-1.3 Op Amps Become Specialized, 3
1-2 741 General-Purpose Op Amp 4

1-2.1 Circuit- Symbol and Terminals, 4
1-2.2 Simplified Internal Circuitry o f a General-Purpose Op
Amp, 5
VI Contents
1-2.3 Input Stage—Differential Amplifier, 6

1-2.4 Intermediate Stage—Level Shifter, 6
1-2.5 Output Stage—Push-Pull, 6
1-3 Packaging and Pinouts 7

1-3.1 Packaging, 7
1-3.2 Combining Symbol and Pinout, 8
1-4 How to Identify or Order an Op Amp 9

1-4.1 The Identification Code, 9
1-4.2 Order Number Example, 10
1-5 Second Sources 10

1-6 Breadboarding Op Amp Circuits 11
1-6.1 The Power Supply, 11
1-6.2 Breadboarding Suggestions, 11
Problems 12
FIRST EXPERIENCES WITH AN OP AMP 13
2-0 Introduction 14
2-1 Op Amp Terminals 14
2-1.1 Power Supply Terminals, 15
2-1.2 Output Terminal, 16
2-1.3 Input Terminals, 16
2-1.4 Input Bias Currents and Offset Voltage, 17
2-2 Open-Loop Voltage Gain 18

2-2.1 Definition, 18
2-2.2 Differential Input Voltage, Ed, 18
2-2.3 Conclusions, 19
2-3 Zero-Crossing Detectors 20

2-3.1 Noninverting Zero-Crossing Detector, 20
2-3.2 Inverting Zero-Crossing Detector, 21
2-4 Positive- and Negative-Voltage-Level Detectors 21

2-4.1 Positive-Level Detectors, 21
2-4.2 Negative-Level Detectors, 21
2-5 Typical Applications of Voltage-Level Detectors 21

2-5.1 Adjustable Reference Voltage, 21
Contents
2-5.2 Sound-Activated Switch, 22

2-5.3 Light Column Voltmeter, 24
2-5.4 Smoke Detector, 26
2-6 Voltage Reference ICs 27

2-6.1 Introduction, 27
2-6.2 Ref-02, 27
2-6.3 Ref-02/Voltage Level Detector Applications, 27
2-7 Signal Processing with Voltage-Level Detectors 29

2-7.2 Sine-to-Square Wave Converter, 29
2-7.3 Sawtooth-to-Pulse Wave Converter, 29
2-7.4 Quad Voltage Comparator, LM339, 30
2-8 Computer Interfacing with Voltage-Level Detectors 32

2-8.2 Pulse-Width Modulator, Noninverting, 33
2-8.3 Inverting and Noninverting Pulse-Width Modulators, 35
2-9 A Pulse-Width Modulator Interface to a Microcontroller

2-10 Op Amp Comparator Circuit Simulation 38
2-10.2 Creating, Initializing, and Simulating a Circuit, 38
Problems 41
INVERTING AND NONINVERTING AMPLIFIERS
3-0 Introduction 45
3-1 The Inverting Amplifier 45
3-1.2 Positive Voltage Applied to the Inverting Input, 45
3-1.3 Load and Output Currents, 47
3-1.4 Negative Voltage Applied to the Inverting Input, 48
3-1.5 Voltage Applied to the Inverting Input, 49
3-1.6 Design Procedure, 51
3-1.7 Analysis Procedure, 51
3-2 Inverting Adder and Audio Mixer 52

3-2.1 Inverting Adder, 52
3-2.2 Audio Mixer, 53
3-2.3 DC Offsetting an AC Signal, 53
3-3 Multichannel Amplifier 55
3-3.1 The Need fo r a Multichannel Amplifier, 55
3-3.2 Circuit Analysis, 55
3-4 Inverting Averaging Amplifier 56

3-5 Noninverting Amplifier 57
3-5.1 Circuit Analysis, 57
3-6 Voltage Follower 61

3-6.2 Using the Voltage Follower, 62
3-7 The "Ideal" Voltage Source 64

3-7.1 Definition and Awareness, 64
3-7.2 The Unrecognized Ideal Voltage Source, 64
3-7.3 The Practical Ideal Voltage Source, 65
3-7.4 Precise Voltage Sources, 66
3-8 Noninverting Adder 66

3-9 Single-Supply Operation 67
3-10 Difference Amplifiers 69
3-10.1 The Subtractor, 70
3-10.2 Inverting-Noninverting Amplifier, 71
3-11 Designing a Signal Conditioning Circuit

3-12 PSpice Simulation 76
3-12.1 Inverting Amplifier—DC Input, 76
3-12.2 Inverting Amplifier—AC Input, 77
3-12.3 Inverting Adder, 78
3-12.4 Noninverting Adder, 79
Problems 80
COMPARATORS AND CONTROLS
4-0 Introduction 85
4-1 Effect of Noise on Comparator Circuits
Contents
OP AMPS WITH DIODES

7-0 Introduction to Precision Rectifiers 188
7-1 Linear Half-Wave Rectifiers 189
7-1.2 Inverting Linear Half-Wave Rectifier, Positive Output, 190
7-1.3 Inverting Linear Half-Wave Rectifier, Negative Output, 192
7-1.4 Signal Polarity Separator, 193
7-2 Precision Rectifiers: The Absolute-Value Circuit 194

7-2.2 Types o f Precision Full-Wave Rectifiers, 195
7-3 Peak Detectors 198

7-3.1 Positive Peak Follower and Hold, 198
7-3.2 Negative Peak Follower and Hold, 200
7-4 AC-to-DC Converter 200

7-4.1 AC-to-DC Conversion or MAV Circuit, 200
7-4.2 Precision Rectifier with Grounded Summing Inputs, 202
7-4.3 AC-to-DC Converter, 203
7-5 Dead-Zone Circuits 203

7-5.2 Dead-Zone Circuit with Negative Output, 203
7-5.3 Dead-Zone Circuit with Positive Output, 205
7-5.4 Bipolar-Output Dead-Zone Circuit, 208
7-6 Precision Clipper 208

7-7 Triangular-to-Sine Wave Converter 208
7-8 PSpice Simulation of Op Amps with Diodes 209
7-8.1 Linear Half-Wave Rectifier, 209
7-8.2 Precision Full-Wave Rectifier, 211
7-8.3 Mean-Absolute-Value Amplifier, 213
Problems 215
DIFFERENTIAL, INSTRUMENTATION, AND BRIDGE AMPLIFIERS

Introduction 217
Basic Differential Amplifier 217

8-1.2 Common-Mode Voltage, 219
8-1.3 Common-Mode Rejection, 220
Differential versus Single-Input Amplifiers 221

8-2.1 Measurement with a Single-Input Amplifier, 221
8-2.2 Measurement with a Differential Amplifier, 222
Improving the Basic Differential Amplifier 223

8-3.1 Increasing Input Resistance, 223
8-3.2 Adjustable Gain, 223
Instrumentation Amplifier 226

8-4.1 Circuit Operation, 226
8-4.2 Referencing Output Voltage, 228
Sensing and Measuring with the Instrumentation

Amplifier 229
8-5.1 Sense Terminal 229
8-5.2 Differential Voltage Measurements, 230
8-5.3 Differential Voltage-to-Current Converter, 231
The Instrumentation Amplifier as a Signal Conditioning

Circuit 233
8-6.1 Introduction to the Strain Gage, 233
8-6.2 Strain-Gage Material, 233
8-6.3 Using Strain-Gage Data, 234
8-6.4 Strain-Gage Mounting, 235
8-6.5 Strain-Gage Resistance Changes, 235
Measurement of Small Resistance Changes 235

8-7.1 Need fo r a Resistance Bridge, 235
8-7.2 Basic Resistance Bridge, 236
8-7.3 Thermal Effect on Bridge Balance, 237
Balancing a Strain-Gage Bridge 238

8-8.1 The Obvious Technique, 238
8-8.2 The Better Technique, 238
Increasing Strain-Gage Bridge Output 239

Practical Strain-Gage Application 241
Measurement of Pressure, Force, and Weight 243
Contents .
8-12 Basic Bridge Amplifier 243

8-12.2 Basic Bridge Circuit Operations. 244
8-12.3 Temperature Measurement with a Bridge Circuit, 245
8-12.4 Bndge Amplifiers and Computers, 248
8-13 Adding Versatility to the Bridge Amplifier 248

8-13.1 Grounded Transducers, 248
8-13.2 High-Current Transducers, 248
Problems 249
DC PERFORMANCE: BIAS, OFFSETS, AND DRIFT

9-0 Introduction 253
9-1 Input Bias Currents 254
9-2 Input Offset Current 255
9-3 Effect of Bias Currents on OutputVoltage 256
9-3.1 Simplification, 256
9-3.2 Effect o f ( —) Input Bias Current, 256
9-3.3 Effect o f (+) Input Bias Current, 258
9-4 Effect of Offset Current on Output Voltage 259

9-4.1 Current-Compensating the Voltage Follower, 259
9-4.2 Current-Compensating Other Amplifiers, 260
9-4.3 Summary on Bias-Current Compensation, 260
9-5 Input Offset Voltage 261

9-5.1 Definition and Model, 261
9-5.2 Effect o f Input Offset Voltage on Output Voltage, 262
9-5.3 Measurement of Input Offset Voltage, 262
9-6 Input Offset Voltage for the Adder Circuit 264

9-6.1 Comparison o f Signal Gain and Offset Voltage Gain. 264
9-6.2 How Not to Eliminate the Effects o f Offset Voltage, 265
9-7 Nulling-Out Effect of Offset Voltage and Bias

Currents 265
9-7.1 Design or Analysis Sequence, 265
9-7.2 Null Circuits fo r Offset Voltage, 266
9-7.3 Nulling Procedure fo r Output Voltage, 267
9-8 Drift 267

9-9 Measurement of Offset Voltage and Bias Currents
9-10 Common-Mode Rejection Ratio 270
9-11 Power Supply Rejection Ratio 271
Problems 272
AC PERFORMANCE: BANDWIDTH, SLEW RATE, NOISE

10-1 Frequency Response of the Op Amp 275
10-1.1 Internal Frequency Compensation, 275
10-1.2 Frequency-Response Curve, 276
10-1.3 Unity-Gain Bandwidth, 277
10-1.4 Rise Time, 278
10-2 Amplifier Gain and Frequency Response 279

10-2.1 Effect o f Open-Loop Gain on Closed-Loop Gain o f an
Amplifier, DC Operation, 279
JO-2.2 Small-Signal Bandwidth, Low- and High-Frequency
Limits, 28J
10-2.3 Measuring Frequency Response, 282
10-2.4 Bandwidth o f Inverting and Noninverting
Amplifiers, 282
JO-2.5 Finding Bandwidth by a Graphical Method, 283
10-3 Slew Rate and Output Voltage 284

10-3.1 Definition o f Slew Rate, 284
10-3.2 Cause o f Slew-Rate Limiting, 285
JO-3.3 Slew-Rate Limiting o f Sine Waves, 285
10-3.4 Slew Rate Made Easy, 288
10-4 Noise in the Output Voltage 289

JO-4.2 Noise in Op Amp Circuits, 289
J 0-4.3 Noise Gain, 290
JO-4.4 Noise in the Inverting Adder, 290
10-4.5 Summary, 290
10-5 Loop Gain 291
Problems 292
Contents
ACTIVE FILTERS
11-1 Basic Low-Pass Filter 296
11-1.2 Designing the Filter, 297
11-1.3 Filter Response, 299
11-2 Introduction to the Butterworth Filter 299

11-3 -40-dB/Decade Low-Pass Butterworth Filter
11-3.1 Simplified Design Procedure, 300
11-4 -60-dB/Decade Low-Pass Butterworth Filter

11-4.1 Simplified Design Procedure, 302
11-5 High-Pass Butterworth Filters 305

11-5.2 20-dB/Decade Filter, 306
11-5.3 40-dB/Dec,ade Filter, 308
11-5.4 60-dB/Decade Filter, 309
11-5.5 Comparison o f Magnitudes and Phase Angles, 311
11-6 Introduction to Bandpass Filters 312

11-6.1 Frequency Response, 312
11-6.2 Bandwidth, 313
11-6.3 Quality Factor, 314
11-6.4 Narrowband and Wideband Filters, 314
11-7 Basic Wideband Filter 315

11-7.1 Cascading, 315
11-7.2 Wideband Filter Circuit, 315
11-7.3 Frequency Response, 315
11-8 Narrowband Bandpass Filters 316

11-8.1 Narrowband Filter Circuit, 317
11-8.2 Performance, 317
11-8.3 Stereo-Equalizer Octave Filter, 318
11-9 Notch Filters 319

11-9.2 Notch Filter Theory, 320
11-10 120-Hz Notch Filter 320
11-10.1 Need fo r a Notch Filter 320
11-10.2 Statement o f the Problem, 321
11-10.3 Procedure to Make a Notch Filter, 321
11-10.4 Bandpass Filler Components, 321
11-10.5 Final Assembly, 322
11-11 Simulation of Active Filter Circuits Using PSpice 322

11-1 L I Low-Pass Filter 323
11-11.2 High-Pass Filter, 325
11-11.3 Bandpass Filter 326
Problems 328
MODULATING, DEMODULATING, AND FREQUENCY CHANGING

WITH THE MULTIPLIER
12-1 Multiplying DC Voltages 331
12-1.1 Multiplier Scale Factor, 331
12-1.2 Multiplier Quadrants, 332
12-2 Squaring a Number or DC Voltage 334

12-3 Frequency Doubling 334
12-3.1 Principle of the Frequency Doubler, 334
12-3.2 Squaring a Sinusoidal Voltage, 335
12-4 Phase-Angle Detection 337
12-4.1 Basic Theory, 337
12-4.2 Phase-Angle Meter, 339
12-4.3 Phase Angles Greater than ±90°, 340
12-5 Analog Divider 340

12-6 Finding Square Roots 342
12-7 Introduction to Amplitude Modulation 342
12-7.1 Need fo r Amplitude Modulation, 342
12-7.2 Defining Amplitude Modulation, 343
12-7.3 The Multiplier Used as a Modulator, 343
12-7.4 Mathematics o f a Balanced Modulator, 343
12-7.5 Sum and Difference Frequencies, 345
12-7.6 Side Frequencies and Sidebands, 347
Contents
12-8 Standard Amplitude Modulation 348

12-8.1 Amplitude Modulator Circuit, 348
12-82 Frequency Spectrum o f a Standard AM Modulator, 351
12-8.3 Comparison o f Standard AM Modulators and
Balanced Modulators, 352
12-9 Demodulating an AM Voltage 352

12-10 Demodulating a Balanced Modulator Voltage 3!
12-11 Single-Sideband Modulation and
Demodulation 356
12-12 Frequency Shifting 356
12-13 Universal Amplitude Modulation Receiver 358
12-13.1 Tuning and Mixing, 358
12-13.2 Intermediate-Frequency Amplifier, 360
12-13.3 Detection Process, 360
12-13.4 Universal AM Receiver, 360
Problem s 361
INTEGRATED-CIRCUIT TIMERS

13-1 Operating Modes of the 555 Timer 364
13-2 Terminals of the 555 365
13-2.1 Packaging and Power Supply Terminals, 365
13-2.2 Output Terminal, 366
13-2.3 Reset Terminal, 366
13-2.4 Discharge Terminal, 366
13-2.5 Control Voltage Terminal, 366
13-2.6 Trigger and Threshold Terminals, 366
13-2.7 Power-on Tune Delays, 368
13-3 Free-Running or Astable Operation 371

13-3.2 Frequency o f Oscillation, 371
13-3.3 Duty Cycle, 373
13-3.4 Extending the Duty Cycle, 374
13-4 Applications of the 555 as an Astable
Multivibrator 375
13-4.1 Tone-Burst Oscillator, 375
13-4.2 Voltage-Controlled Frequency Shifter, 377
13-5 One-Shot or Monostable Operation 378

13-5.2 Input Pulse Circuit, 380
13-6 Applications of the 555 as a One-Shot

Multivibrator 381
13-6.1 Water-Level Fill Control, 381
13-6.2 Touch Switch, 381
13-6.3 Frequency Divider, 382
13-6.4 Missing Pulse Detector, 383
13-7 Introduction to Counter Tinners 384

13-8 The XR 2240 Programmable Timer/Counter 3
13-8.1 Circuit Description, 385
13-8.2 Counter Operation, 386
13-8.3 Programming the Outputs, 388
13-9 Timer/Counter Applications 389

13-9.1 Timing Applications, 389
13-9.2 Free-Running Oscillator, Synchronized Outputs, 390
13-9.3 Binary Pattern Signal Generator, 391
13-9.4 Frequency Synthesizer, 392
13-10 Switch Programmable Timer 394

13-10.1 Timing Intervals, 394
13-11 PSpice Simulation of 555 Timer 394

13-1 L I Astable or Free-Running Multivibrator, 394
13-11.2 Tone-Burst-Control Circuit, 397
Problems 399
DIGITAL-TO-ANALOG CONVERTERS
14-1 DAC Characteristics 401
Contents ix
4-2 Positive Feedback 87

4-2.2 Upper-Threshold Voltage, 58
4-2.3 Lower-Threshold Voltage, 88
4-3 Zero-Crossing Detector with Hysteresis 90

4-3.1 Defining Hysteresis, 90
4-3.2 Zero-Crossing Detector with Hysteresis as a Memory
Element, 91
4-4 Voltage-Level Detectors with Hysteresis 91

4-4.2 Noninverting Voltage-Level Detector with Hysteresis, 92
4-4.3 Inverting Voltage-Level Detector with Hysteresis, 94
4-5 Voltage-Level Detector with Independent Adjustment

of Hysteresis and Center Voltage 96
4-5.2 Battery-Charger Control Circuit, 9<S
4-6 On-Off Control Principles 99

4-6.1 Comparators in Process Control, 99
4-6.2 77w Thermostat as a Comparator, 100
4-6.3 Selection/Design Guideline, 700
4-7 An Independently Adjustable Setpoint Controller 100

4-7.7 Principle o f Operation, 100
4-7.2 Output-Input Characteristics o f an Independently
Adjustable Setpoint Controller, 100
4-7.3 Choice o f Setpoint Voltages, 101
4-7.4 Circuit fo r Independently Adjustable Setpoint Voltage, 102
4-7.5 Precautions, 104
4-8 1C Precision Comparator, 111/311 104

4-8.2 Output Terminal Operation, 104
4-8.3 Strobe Terminal Operation, 104
4-9 Biomedical Application 106

4-10 Window Detector 108
4-11 Propagation Delay 108
4-11.1 Definition, 108
4-11.2 Measurement o f Propagation Delay, 110
4-12 Using PSpice to Model and Simulate Comparator

Circuits 111
4-12.1 Simulation of the Zero-Crossing Detector with
Hysteresis, 111
4-12.2 Window Detector, 113
Problems 115
SELECTED APPLICATIONS OF OP AMPS

5-1 High-Resistance DC Voltmeter 119

5-1.1 Basic Voltage-Measuring Circuit, 119
5-1.2 Voltmeter Scale Changing, 120
5-2 Universal High-Resistance Voltmeter 121

5-3 Voltage-to-Current Converters: Floating Loads 123
5-3.1 Voltage Control o f Load Current, 123
5-3.2 Zener Diode Tester, 123
5-3.3 Diode Tester, 123
5-4 Light-Emitting-Diode Tester 125

5-5 Furnishing a Constant Current to a Grounded Load
5-5.1 Differential Voltage-to-Current Converter, 126
5-5.2 Constant-High-Current Source, Grounded Load, 127
5-5.3 Interfacing a Microcontroller Output to a 4- to-20-mA
Transmitter, 128
5-5.4 Digitally Controlled 4- to 20-mA Current Source, 129
5-6 Short-Circuit Current Measurement and Current-to-

Voltage Conversion 130
5-6.2 Using the Op Amp to Measure Short-Circuit Current, 130
Contents
5-7 Measuring Current from Photodetectors

5-7.7 Photoconductive Cell, 132
5-7.2 Photodiode, 133
5-8 Current Amplifier 133

5-9 Solar Cell Energy Measurements 134
5-9.1 Introduction to the Problems, 134
5-9.2 Converting Solar Cell Short-Circuit Current t
Voltage, 135
5-9.3 Current-Divider Circuit (Current-to-Current
Converter), 136
5-10 Phase Shifter 137

5-10.2 Phase-Shifter Circuit, 138
5-11 Temperature-to-Voltage Converters 139

5-11.1 AD590 Temperature Transducer, 139
5-11.2 Celsius Thermometer 140
5-11.3 Fahrenheit Thermometer, 140
5-12 Integrators and Differentiators 140

5-12.1 Integrators, 141
5-12.2 Servoamplifier, 142
5-12.3 Differentiators, 144
5-13 PSpice Simulation 146

Problems 148
SIGNAL GENERATORS
6-1 Free-Running Multivibrator 152
6-1.1 Multivibrator Action, 152
6-2 One-Shot Multivibrator 156

6-2.2 Stable State, 156
6-2.3 Transition to the Timing State, 157
6-2.4 Timing State, 157
6-2.5 Duration o f Output Pulse, 159
6-2.6 Recovery Time, 159
Triangle-Wave Generators 160

6-3.1 Theory o f Operation, 760
(5-J.2 Frequency o f Operation, 162
6-3.3 Unipolar Triangle-Wave Generator, 163
Sawtooth-Wave Generator 165

6-4.2 Sawtooth Waveshape Analysis, 165
6-4.4 Voltage-to-Frequency Converter, 167
6-4.5 Frequency Modulation and Frequency Shift Keying, 167
6-4.6 Disadvantages, 168
Balanced Modulator/Demodulator, the AD630 170

6-5.2 Input and Output Terminals, 170
6-5.3 Input-Output Waveforms, 170
Precision Triangle/Square-Wave Generator 170

Sine-Wave Generation Survey 172

Universal Trigonometric Function Generator,
the AD639 173
6-8.2 Sine Function Operation, 173
Precision Sine-Wave Generator 175

6-9.3 High Frequency Waveform Generator, 178
PSpice Simulation of Signal Generator Circuit

6-10.1 Free-Running Multivibrator, 179
6-10.2 One-Shot Multivibrator, 181
6-10.3 Bipolar Triangle-Wave Generator, 182
6-10.4 Unipolar Triangle-Wave Generator, 183
Problems 185
Contents
14-1.1 Resolution, 40]

14-1.2 Offset Error, 405
14-1.3 Gain Error, 406
14-1.4 Monotonic, 408
14-1.5 Relative Accuracy, 408
14-2 Digital-to-Analog Conversion Process 408

14-2.1 Block Diagram, 408
14-2.2 R-2R Ladder Network, 409
14-2.3 Ladder Currents, 410
14-2.4 Ladder Equation, 411
14-3 Voltage Output DACs 412

14-4 Multiplying DAC 414
14-5 8-Bit Digital-to-Analog Converter;the DAC-08
14-5.1 Power Supply Terminals, 414
14-5.2 Reference (Multiplying) Terminal, 414
14-5.3 Digital Input Terminals, 416
14-5.4 Analog Output Currents, 416
14-5.5 Unipolar Output Voltage, 417
14-5.6 Bipolar Analog Output Voltage, 418
14-6 Microprocessor Compatibility 420

14-6.1 Interfacing Principles, 420
14-6.2 Memory Buffer Registers, 420
14-6.3 The Selection Process, 420
14-7 AD558 Microprocessor-Compatible DAC 421

14-7.2 Power Supply, 423
14-7.3 Digital Inputs, 423
14-7.4 Logic Circuitry, 423
14-7.5 Analog Output, 423
14-7.6 Dynamic Test Circuit, 425
14-8 Serial DACs 425

14-8.1 Interfacing a Serial DAC to a Microprocessor, 426
14-8.2 Assembly Language Programming. 427
Problems 428
ANALOG-TOtDIGITAL co n verters

Introduction 431
ADC Characteristics 431

15-L I Resolution, 431
15-1.2 Quantization Error, 433
15-1.3 Offset Error, 433
15-1.4 Gain Error, 434
15-1.5 Linearity Error, 435
Integrating ADC 435

15-2.1 Types o f ADCs, 435
15-2.2 Principles o f Operation, 436
15-2.3 Signal Integrate Phase, Th 436
15-2.4 Reference Integrate Phase, T2, 436
15-2.5 The Conversion, 438
15-2.6 Auto-Zero, 439
15-2.7 Summary, 439
Successive Approximation ADC 440

15-3.2 Successive Approximation Analogy, 442
15-3.3 Conversion Time, 442
ADCs for Microprocessors 442
AD670 Microprocessor-Compatible ADC

15-5.1 Analog Input Voltage Terminals, 445
15-5.2 Digital Output Terminals, 445
15-5.3 Input Option Terminal, 445
15-5.4 Output Option Terminal, 445
15-5.5 Microprocessor Control Terminals, 445
Testing the AD670 447
Flash Converters 447

15-7.1 Principles o f Operation, 447
15-7.2 Conversion Time, 447
Frequency Response of ADCs 450

15-8.1 Aperture Error, 450
15-8.2 Sample-and-Uold Amplifier, 450
Problems 451
Contents
POWER SUPPLIES
16-1 Introduction to the Unregulated Power Supply 454
16-L l Power Transformer, 454
16-L2 Rectifier Diodes, 456
16-1.3 Positive versus Negative Supplies, 456
I6-J.4 Filter Capacitor, 457
16-1.5 Load, 457
16-2 DC Voltage Regulation 457

16-2.1 Load Voltage Variations, 457
16-2.2 DC Voltage Regulation Curve, 458
16-2.3 DC Model o f a Power Supply; 459
16-2.4 Percent Regulation, 461
16-3 AC Ripple Voltage 461

16-3.1 Predicting AC Ripple Voltage, 461
16-3.2 Ripple Voltage Frequency and Percent Ripple, 463
16-3.3 Controlling Ripple Voltage, 464
16-4 Design Procedure for a Full-Wave Bridge Unregulated

Supply 464
16-4.1 Design Specification, General, 464
16-5 Bipolar and Two-Value Unregulated Power

Supplies 468
16-5.1 Bipolar or Positive and Negative Power Supplies, 468
16-5.2 Two-Value Power Supplies, 469
16-6 Need for Voltage Regulation 469

16-7 The History of Linear Voltage Regulators 469
16-7.1 The First Generation, 469
16-7.2 Th£ Second Generation, 470
16-7.3 The Third Generation, 470
16-8 Linear IC Voltage Regulators 470

16-8.1 Classification, 470
16-8.2 Common Characteristics, 470
16-8.3 Self-Protection Circuits, 472
16-8.4 External Protection, 472
16-8.5 Ripple Reduction, 472
X X IV Contents
16-9 Power Supply for Logic Circuits 472

16-9.1 The Regulator Circuit, 472
16-9.2 The Unregulated Supply, 473
16-10 ±15-V Power Supplies for Linear Application 473

16-10.1 High-Current ±15-V Regulator, 473
16-10.2 Low-Current ± 15-V Regulator, 474
16-10.3 Unregulated Supply fo r the ± I5 -V Regulators, 475
16-11 Adjustable Three-Terminal Positive Voltage Regulator

(the LM317HV) and Negative Voltage Regulator
(the LM337HV) 475
16-12 Load Voltage Adjustment 475

16-12.1 Adjusting the Positive Regulated Output Voltage, 475
16-12.2 Characteristics o f the LM3I7HVK, 477
16-12.3 Adjustable Negative-Voltage Regulator, 477
16-12.4 External Protection, 477
16-13 Adjustable Laboratory-Type Voltage Regulator 478

16-14 Other Linear Regulators 479
Problems 479
APPENDIX 1 |j,A741 FREQUENCY-COMPENSATED OPERATIONAL

AMPLIFIER 481
APPENDIX 2 LM301 OPERATIONAL AMPLIFIER 491
APPENDIX 3 LM311 VOLTAGE COMPARATOR 498
APPENDIX 4 LM117 3-TERMINAL ADJUSTABLE REGULATOR 505
ANSWERS TO SELECTED ODD-NUMBERED PROBLEMS 511
BIBLIOGRAPHY 518
INDEX 521
Preface
T he a u th o rs’ intention in all previous ed itio n s o f O p era tio n a l A m p lifiers a n d L in ea r

Integrated Circuits has been to show that operational am plifiers and other linear integrated
circuits are easy to use and fun to w ork with. This sixth edition has kept that basic phi
losophy. For the fundam ental circuits, we have continued to use devices that are readily
available, easy to use, and forgiving if a w iring error is made. N ew er devices are intro
duced w here the application requires it. We have preserved our original objective o f sim
plifying the process of learning about applications involving signal conditioning, signal
generation, filters, instrum entation, tim ing, and control circuits. T his edition continues to
reflect the evolution o f analog circuits into applications requiring transducer signals that
m ust be conditioned for a m icrocontroller’s analog-to-digital in p u t. 1 We have kept circuit
sim ulation using OrCAD® PSpice®. A laboratory m anual is now available to accom pany
1 A detailed procedure on how to design circuits that interface between the physical world and m icrocon
trollers is presented in Data Acquisition and Process Control with the M68HCH Microcontroller, 2nd Edition.
by F. Driscoll, R. Coughlin, and R. Villanucci, published by Prentice Hall (2000).
XXV
XXVi Preface
this sixth edition.2 It includes both detailed hardw are and sim ulation exercises. Som e ex
ercises are step-by-step; others are design projects. The exercises follow the text material.
C hapters 1 through 6 provide the reader with a logical progression from op am p
fundam entals to a variety of practical applications w ithout having to w orry about op am p
lim itations. C hapter 7 show s how op am ps com bined w ith diodes can be used to design
ideal rectifier circuits as w ell as clam ping and clipping circuits. PSpice m odels and sim
ulations are included in these chapters.
C hapter 8 shows applications that require m easuring a physical variable such as
tem perature, force, pressure, or w eight and then having the signal conditioned by an in
stru m e n ta tio n am p lifier b efore b ein g in p u t into a m ic ro c o n tro lle r’s A /D converter.
Instrum entation am plifiers are required w hen a designer has to m easure a differential sig
nal, especially in the presence o f a larger noise signal.
As previously m entioned, in order not to obscure the inherent sim plicity and o ver
w helm ing advantages o f using op am ps, their lim itations have been left for C hapters 9
and 10. Dc lim itations are studied in C hapter 9 and ac lim itations are covered in C hapter
10. A n expanded discussion on com m on-m ode rejection ratio has been included in this
edition. M any lim itations have been m ade negligible by the latest generations of op am ps,
as pointed out in these chapters.
A ctive filters, low -pass, h ig h -p ass, b an d -p a ss, and b an d -reje ct, are covered in
C hapter 11. B utterw orth-type filters w ere selected because they are easy to design and
produce a m axim ally flat response in the pass band. C hapter 1 I show s the reader how to
design a variety of filters easily and quickly.
C hapter 12 introduces a linear integrated circuit known as the m ultiplier. T he d e
vice m akes analysis and design o f AM com m unication circuits sim pler than using discrete
com ponents. M odulators, dem odulators, frequency shifters, a universal A M radio receiver,
and analog divider circuits all use a m ultiplier IC as the sy stem ’s basic building block.
T his chapter has been retained because instructors have w ritten to say that the principles
of single-side band suppressed carrier and standard am plitude-m odulation transm ission
and detection are clearly explained and quite useful for their courses.
T he inexpensive 555 IC tim er is covered in C hapter 13. T his chapter show s the ba
sic operation of the device as well as many practical applications. The chapter also in
cludes a tim er/counter unit.
In previous editions, analog-to-digital and digital-to-analog converters have been
covered in a single chapter. T his edition separates these topics into tw o chapters so that
m ore device specifications can be included as well as practical applications. C hapter 14
deals only w ith analog-to-digital converters, w hile the new C hapter 15 covers digital-to-
analog converters. A serial A D C connected to a M otorola m icroprocessor is show n (with
assem bly language code) in C hapter 14.
C hapter 16 shows how to design a regulated linear pow er supply. T his chapter be
gins w ith the fundam entals of unregulated supplies and proceeds to regulated supplies. It
show s how IC regulators are used for building low -cost 5 V and ± 15 V bench supplies.
2
Laboratory M anual to Accom pany Operational Amplifiers and Linear Integrated Circuits, 6th Edition, by
R. Coughlin, F. Driscoll, and R. Villanucci published by Prentice Hall (2001).
Preface X X V ii
T his edition has m ore than enough m aterial for a single-sem ester course. A fter the
first three chapters, instructors often take chapters out o f sequence depending on the class
interest, need to com plem ent another course (such as a design course), or availability o f
lab equipm ent or class time. Therefore, C hapters 4 through 16 have been w ritten as stand
alone chapters for this very reason. The circuits have been tested in the laboratory by the
authors and the m aterial is presented in a form useful to students or as a reference to p rac
ticing engineers and technologists. Each chapter includes learning objectives and p ro b
lem s, and m ost chapters have PSpice sim ulations. T he reader should refer to the accom
panying laboratory m anual for lab exercises and additional sim ulation exercises.
ACKNOW LEDGM ENTS _______________________________________________________________________
We acknow ledge with gratitude the advice of Professor R obert V illanucci, w ho is also a
co-author o f the laboratory m anual, and two highly respected engineers, Dan Sheingold
of A nalog Devices and Bob Pease o f N ational Sem iconductor. A special thanks goes to
Libby D riscoll for assisting in the preparation of the m anuscript. We thank the follow ing
review ers o f the m anuscript: W arren H ioki, C om m unity C ollege of Southern N evada;
G regory M . R asm u ssen , St. Paul T echnical S chool; M ichael W. R ud isill, N o rth ern
M ichigan University; Rod Schein, Edm onds C om m unity College, ATTC; and A ndrew C.
W oodson.
Finally, we thank our students for their insistence on relevant instruction that is im
m ediately useful and our readers for their enthusiastic reception of previous editions and
their perceptive suggestions for this edition.
CHAPTER 1
Introduction to Op Amps
LEARNING OBJECTIVES ________________________________________________
U pon com pleting this introductory chapter on op am ps, you will be able to:
• U nderstand w hy anaJog circuitry using op am ps is still req u ired in co m p u ter-b ased

system s.
• Draw the circuit sym bol for a general-purpose op am p such as the 741 and show the
pin num bers for each term inal.
• N am e and identify at least three types o f package styles that house a general-purpose
op am p.
• Identify the m anufacturer, op am p, and package style from the PIN.
• C orrectly place an order for an op am p.
• Identify the pins o f an op am p from the top or bottom view.
• Identify the pow er supply com m on on a circu it schem atic, and state why you m ust
do so.
• B readboard an op am p circuit.
1
Chapter 1
1-0 INTRODUCTION
O ne o f the m ost versatile and w idely used electronic devices in linear applications is the
operational am plifier, m ost often referred to as the op amp. Op am ps are popular because
they are low in cost, easy to use, and fun to w ork with. They allow you to build useful
circuits w ithout needing to know about their com plex internal circuitry. O p am ps are usu
ally very forgiving of w iring errors because of their self-protecting internal circuitry.
T he w ord operational in operational am plifiers originally stood for m athem atical
operations. Early op am ps w ere used in circuits that could add, subtract, m ultiply, and
even solve differential equations. T hese operations have given way to digital com puters
because o f their speed, accuracy, and versatility. However, digital com puters w ere not the
dem ise of the op amp.
1-1 IS THERE STILL A NEED FOR ANALOG CIRCUITRY? ______________________________
1-1.1 Analog and Digital System s
You often hear an expression sim ilar to ‘‘It is a digital w orld.” This usually is follow ed by
a statem ent such as “Is there a reason for studying analog circuitry, including op am ps
and other linear integrated circuits, when so many applications use a co m p u ter?” It is true
that m ore and m ore functions are being done and problem s are being solved by m icro
com puters, m icrocontrollers, or digital signal processing chips and system s today than
ever before. This trend o f going digital will continue at an even faster pace because so ft
w are packages are better and easier to use, com puters are faster and m ore accurate, and
data can be stored and transferred over networks. However, as m ore digital system s are
created for data acquisition and process control, m ore interface circuits using op am ps and
other linear integrated circuits are also required. T hese integrated system s now require d e
signers to understand the principles of both the analog and the digital w orld in order to
obtain the best perform ance o f a system at a reasonable cost.
In the past, op am ps w ere studied as separate entities and entire analog system s
w ere developed using only analog circuitry. In som e specialized real-tim e applications,
this is still true but m ost system s that find their way to the m arketplace are a co m b in a
tion o f analog and digital. A typical data acquisition system block diagram is show n in
c Sensor
Converts
Signal
conditioning
circuit
J
A/D
CPU
and
memory
Output
port
Output
interface
Provides isolation
Load
(ac or dc)
Typical loads
a physical
between a are motors,
param eter to Input interface M icrocontroller
m icrocontroller heaters, pumps,
an electrical using op amps
and high-voltage air conditioning
quantity and other TCs
loads. SCRs triacs, units, etc.
and power transistors
are typical output
interface devices.
FIGURE 1-1 Typical data acquisition block diagram.

Fig. 1-1. It uses a sensor to convert a physical param eter (such as tem perature, pressure,
or flow) into an electrical param eter (such as voltage, current, or resistance). U nfortunately,
sensors rarely produce an output w hose electrical param eter or value is suitable for direct
input into the com puter through an analog-to-digital (A/D) converter. T hus an input in
terface circuit using op am ps or other linear ICs is needed to condition the signal for the
com puter’s A/D. Sim ilarly, at the com puter’s output another analog circuit is needed to
interface and isolate the com p u ter’s low voltage from a high-voltage ac or dc load. This
text is designed to show applications of op am ps and other linear integrated circuits in
O p am ps are designed using a w ide variety o f fabrication techniques. O riginally they co n

tained only bipolar transistors, but now there are a host o f devices that use field-effect
transistors w ithin the op amp. Junction field-effect transistors at the input draw very sm all
currents and allow the input voltages to be varied betw een the pow er supply lim its. M O S
transistors in the output circuitry allow the output term inal to go w ithin m illivolts o f the
O p am ps designed w ith bipolar inputs and com plem entary M O S outputs, appropri
ately nam ed B iM O S, are faster and have a higher frequency response than the general-
purpose op am ps. M anufacturers have also designed dual (2) and quad (4) op am p p ack
ages. H ence, the package that once housed a single op am p can now contain tw o or four
op am ps. In the quad package, all four op am ps share the sam e pow er supply and ground
Inevitably, general-purpose op am ps w ere redesigned to optim ize or add certain features.

Special function ICs that contain m ore than a single op am p w ere then developed to per-
You need only to look at linear data books to appreciate their variety. O nly a few
4 Chapter 1
G eneral-purpose op am ps will be around for a long tim e. H ow ever, m ore com plex in te
grated circuits on a single chip are being developed. T hese devices com bine analog with
digital circuitry. In fact, w ith im proved very large scale integrated (V L SI) technology, en
tire system s are being fabricated on a single large chip.
A single-chip com puter is today's reality. A single-chip TV set w ill happen eventu
ally. B efore learning how to use op am ps, it is w ise to learn w hat they look like and how
to buy them . As previously stated, the op am p 's greatest use w ill be as a part in a system
that interfaces the real w orld o f analog voltage w ith the digital w orld o f the com puter, as
w ill be show n throughout this text. If you w ant to understand the system , you m ust un
derstand the w orkings o f one o f its m ost im portant com ponents.
1-2 741 GEN ERAL-PURPOSE OP AM P
1-2.1 Circuit Sym bol and Terminals
T he 741 op am p has been “around” for a num ber o f years. However, it still is a great d e
vice to begin with because it is inexpensive, rugged, and easy to obtain. T he op-am p sy m
bol in Fig. 1-2 is a triangle that points in the direction o f signal flow. T his com ponent has
U7(IC14) = reference designator
Pin or terminal
Positive supply
number
terminal
Inverting input 2
terminal a
-o Output terminal
N oninverting input
terminal Part identification num ber (PIN)
Negative supply
terminal
FIGURE 1-2 Circuit symbol for the general-purpose op amp. Pin num
bering is for an 8-pin mini-DIP package.
a part identification num ber (PIN ) placed w ithin the triangular sym bol. T he PIN refers to
a p articular op am p w ith specific characteristics. T he 741C op am p illustrated here is a
general-purpose op am p that is used throughout the book for illustrative purposes.
The op amp may also be coded on a circuit schem atic with a reference designator such
as U7, IC14, and so on. Its PIN is then placed beside the reference designator in the parts
list of the circuit schematic. All op amps have at least five terminals: (1) The positive pow er
supply term inal Vc c or 4- V at pin 7, (2) the negative power supply term inal VEE or —V at pin
4, (3) output pin 6 , (4) the inverting ( —) input terminal at pin 2, and (5) the noninverting ( + )
input term inal at pin 3. Som e general-purpose op am ps have additional specialized terminals.
(The pins above refer to the 8-pin m ini-D IP case discussed in the following section.)
Positive
power supply
FIG U RE l-3(b)
1-2.3 Input Stage—Differentia! Amplifier
T he input stage o f the op am p in Fig. l-3 (a ) is called a differential am plifier. It has very
high input im pedance as well as a large voltage gain. W hen input signals V(+) and V(_)
are applied, the difference voltage, Ech is am plified by this stage and appears as the o u t
put voltage Vj. (Exam ples of how Ed is calculated are given in C hapter 2.)
1-2.4 Intermediate Stage—Level Shifter

Signal voltage K, at the output of the differential am plifier is directly coupled to the in
put o f the interm ediate level shifter stage. T his stage perform s tw o functions. First, it
shifts the dc voltage level at the output of the differential am plifier to a value required to
bias the output stage. Second, this stage allow s input signal V| to pass nearly unaltered
and becom e the input signal V2 for the output stage.
1-2.5 Output Stage—Push-Pull

T he signal voltage V2 at the output of the interm ediate stage is coupled directly into the
output stage. The most com m on output stage is a p np-npn push-pull transistor con fig u ra
tion. U sing a push-pull circuit as the final stage allow s the op am p to have a very low o u t
put resistance. As show n in Figs. I-3(a) and (b), load resistor RL is connected betw een
the output term inal and com m on to develop output voltage V0.
T his sim plified m odel of the op am p in Fig. I-3(a) presents the basic inform ation
on its internal architecture. T he actual circuitry is m ore com plicated, but the functions are
similar.
Introduction to Op Am ps 7
1-3 PACKAGING AND PINOUTS ____________________________________________________________
1-3.1 Packaging
The op am p is fabricated on a tiny silicon chip and packaged in a suitable case. Fine-gage
w ires connect the chip to external leads extending from a m etal, plastic, or ceram ic pack
age. C om m on op am p packages are show n in Figs. I-4(a) to (d).
The metal can package show n in Fig. I-4(a) is available w ith 3, 5, 8, 10, and 12
leads. T he silicon chip is bonded to the bottom metaJ sealing plane to expedite the d issi
pation of heat. In Fig. l-4 (a) the tab identifies pin 8 , and the pins are num bered co u n ter
clockw ise w hen you view the m etal can from the top.
T he popular 14-pin and 8-pin dual-in-line packages (DIPs) are show n in Figs. l-4 (b )
and (c). Either plastic or ceram ic cases are available. As view ed from the top, a notch or
dot identifies pin 1 and term inals are num bered counterclockw ise.
C om plex integrated circuits involving m any op am ps and other ICs can now be fab
ricated on a single large chip or by interconnecting many chips and placing them in a sin
gle package. For ease o f m anufacture and assem bly, pads replace the leads. T he resulting
FIG U RE 1-4 The three most popular op amp packages are the metal can in
(a) and the 14- and 8-pin dual-in-line packages in (b) and (c), respectively. For
systems requiring high density, surface-mounted technology (SMT) packages
are used as shown in (d).
Introduction to Op Am ps 9
the num bering schem es are identical for an 8-pin can and an 8-pin DIP. A notch or dot
identifies pin 1 on the D IPs, and a tab identifies pin 8 on the TO -5 (or the sim ilar TO -99)
package. From a top view, the pin count proceeds counterclockw ise.
The final tasks in this chapter are to learn how to buy a specific type o f op am p and
to present advice on basic breadboarding techniques.
7-4 HOW TO IDENTIFY OR ORDER AN OP AM P ________________________________________
7-4.7 The Identification Code
Each type of op am p has a le tte r-n u m b e r identification code. T his code answ ers four
questions:
1. W hat type of op am p is it? (Exam ple: 741.)

2. W ho m ade it? (Exam ple: A nalog D evices.)
3. How good is it? (Exam ple: the guaranteed tem perature range for operation.)
4. W hat kind o f package houses the op am p chip? (Exam ple: plastic DIP.)
N ot all m anufacturers use precisely the sam e code, but most use an identification code
that consists of four parts w ritten in the follow ing order: ( 1) letter prefix, (2) circuit d es
ignator, (3) letter suffix, and (4) m ilitary specification code.
Letter prefix. T he letter prefix code usually consists o f tw o or three letters that
identify the m anufacturer. T he follow ing exam ples list som e o f the codes used by a m an
ufacturer. You may w ish to visit their Web site to obtain data sheets and application notes
about a particular product. T heir m ain Web site address is given.
Letter prefix M anufacturer M anufacturer’s Web Site
AD/OP Analog Devices www.analog.com

INA/OPA Bu i t - Brown www.burr-brown.com
CD Cirrus Logic www.cinrus.com
LF/LT/LTC Linear Technology www.linear-tech.com
MAX Maxim www.m axim -ic.com
MC M otorola www.m otorola.com
LF/LM /LM C/LM V N ational Sem iconductor w ww.national.com
T U T L C /T H /T M Texas Instruments www.ti.com
Circuit designation. T he circu it d esig n ato r co n sists o f three to seven n u m

bers and le tte rs. T hey id e n tify the typ e o f op am p and its te m p e ra tu re ran g e . F or
exam ple:
324C
Part n u m b e r-------^ ^ ------- “C ” identifies com m ercial
tem perature range
10 Chapter 1
T he three tem perature-range codes are as follow s:
1. C: com m ercial, 0 to 70°C

2 . I: industrial, —25 to 85°C
3. M: m ilitary, - 5 5 to J25°C
Letter suffix. A one- or tw o -le tte r suffix id e n tifie s the p ac k ag e sty le th a t

houses the op am p chip. You need the package style to g et the co rrec t pin co n n ectio n s
from the data sheet (see A ppendix 1). T h ree o f the m ost co m m o n p ac k ag e suffix co d es
Package code Description
D Plastic dual-in-line for surface m ounting on a pc board

J Ceram ic dual-in-line
N, P Plastic dual-in-line for insertion into sockets. (Leads extend through the top surface
of a pc board and are soldered to the bottom surface.)
Military specification code. T he m ilitary specification code is used only w hen

the part is for high-reliabiIity applications.
1-4.2 Order Number Example
A 74J general-purpose op am p w ould be com pletely identified in the follow ing way
Prefix D esignator Suffix
i
LM
i
7 4 IC
i
N (8-pin)
i
National
i
General-purpose
i
Plastic package
op amp, com m ercial
tem perature range
1-5 SECOND SO U R C ES ______________________________________________________________________
Som e op am ps are so w idely used that they are m ade by m ore than one m anufacturer.
This is called second sourcing. The com pany (Fairchild) w ho designed and m ade the o rig
inal 741 contracted for licenses w ith other m anufacturers to m ake 741s in exchange for a
license to m ake op am ps or other devices.
As time went on, the original 741 design was modified and improved by all m anufac
turers. The present 741 has evolved over several generations. Thus, if you order a 741 8-pin
D IP from a supplier, it may have been built by Texas Instruments (TL741), Analog Devices
(AD741), National Sem iconductor (LM 741), or others. Therefore, always check the m anu
facturer’s data sheets that correspond to the device you have. You will then have inform ation
on its exact perform ance and a key to the identification codes on the device.
Introduction to Op Amps 11
1-6 BREADBOARDING OP AMP CIRCUITS ______________________________________
1-6.1 The Power Supply
Power supplies for general-purpose op am ps are bipolar As shown in Fig. l - 6(a), the typical
com mercially available power supply outputs ± 15 V. The com m on point between the + 1 5 V
supply and —15 V is called the pow er supply com m on. It is shown with a com m on symbol
for two reasons. First, all voltage measurem ents are made with respect to this point. Second,
the power supply com m on is usually wired to the third wire of the line cord that extends
ground (usually from a water pipe in the basement) to the chassis containing the supply.
T he schem atic draw ing of a portable supply is show n in Fig. I -6 (b). T his is offered
to reinforce the idea that a bipolar supply contains tw o separate pow er supplies connected
in series aiding.
1-6.2 Breadboarding Suggestions
It should be possible to breadboard and test the perform ance o f all circuits presented in
this text. A few circuits require printed circuit board construction. B efore w e proceed to
learn how to use an op am p, it is prudent to give som e tim e-tested advice on b rea d
boarding a circuit:
1. Do all w iring with pow er off.

2. Keep w iring and com ponent leads as short as possible.
3. W ire the + V and — V supply leads fir s t to the op amp. It is surprising how often
this vital step is om itted.
4. Try to w ire all ground leads to one tie point, the pow er supply com m on. T his type
o f connection is called star grounding. Do not use a ground bus, because you may
create a ground loop, thereby generating unw anted noise voltages.
5. R echeck the w iring before applying pow er to the op amp.
+ 9- + 9- +V
9-V b a tte ry -------

Power
supply
com mon Com mon
-1 5 V 9-V b a tte ry -------
- 6- - 1/ - o- -► -V
(a) Schem atic of a (b) Power supply
com mercial bipolar for portable
power supply. operation.
FIG U RE 1-6 Power supplies for general-purpose op amps must be bipolar.

12 Chapter 1
6 . C onnect signal voltages to the circuit only after the op am p is pow ered.
7. Take all m easurem ents with respect to com mon. For example, if a resistor is connected
between two term inals of an IC, do not connect either a m eter or an oscilloscope across
the resistor; instead, m easure the voltage on one side o f the resistor w ith respect
to com m on, then the voltage on the other side, and calculate the voltage across the
resistor.
8. Avoid using am m eters, if possible. M easure the voltage as in step 7 and calculate
current.
9. D isconnect the input signal before the dc pow er is rem oved. O therw ise, the IC may
be destroyed.
10. T hese ICs will stand m uch abuse. B ut never:
a. Reverse the polarity of the pow er supplies,
b. Drive the op am p ’s input pins above or below the potentials at the + V and —V
term inal, or
c. Leave an input signal connected w ith no pow er on the IC.
11 - If unwanted oscillations appear at the output and the circuit connections seem correct:
a. C onnect a 0.1 -julF capacitor betw een the op a m p ’s + V pin and ground and an
other 0 . 1-fxF capacitor betw een the op a m p ’s —V pin and ground.
b. Shorten your leads, and
c. C heck the test instrum ent, signal generator, load, and pow er supply ground leads.
They should com e together at one point.
I 2. T he sam e principles apply to all other linear ICs.
We now proceed to our first experience w ith an op amp.
P ROBL E MS _____________________________________________________________________
1-1. In the term operational amplifier, what does the word operational stand for?
1-2. Is the LM324 op amp a single op amp housed in one package, a dual op amp in one pack
age, or a quad op amp in one package?
1-3. With respect to an op amp, what does the abbreviation PIN stand for?
1-4. Does the letter prefix of a PIN identify the manufacturer or the package style?
1-5. Does the letter suffix of a PIN identify the manufacturer or the package style?
1-6. Which manufacturer makes the AD741CN?
1-7. Does the tab on a metal can package identify pin 1 or pin 8?
1-8. Which pin is identified by the dot on an 8-pin mini-DIP?
1-9. (a) How do you identify power supply common on a circuit schematic?
(b) Why do you need to do so?
1-10. When breadboarding an op amp circuit, should you use a ground bus or star grounding?
1-11. Search a manufacturer’s Web site and download a 741 data sheet.
(a) What is the manufacturer’s identification code?
(b) What package styles are available?
(c) List three applications that the 741 op amp can be used in.
CHAPTER 2
First Experiences
with an Op Amp
LEARNING O BJECTIVES ________________________________________________
Upon com pleting this chapter on first experiences w ith an op am p, you will be able to:
• Briefly describe the task perform ed by the pow er supply and input and output term inals
o f an op amp.
• Show how the single-ended output voltage o f an op am p depends on its open-loop gain
and differential input voltage.
■ C alculate the differentia] input voltage Ed, and the resulting output voltage VQ.
• D raw the circuit schem atic for an inverting or noninverting zero-crossing detector.
• Draw the output voltage w aveshape o f a zero-crossing detector if you are given the in
put voltage waveshape.
• Draw the o u tp u t-in p u t voltage characteristics of a zero-crossing detector.
• Sketch the schem atic o f a noninverting or inverting voltage-level detector.
13
14 Chapter 2
D escribe at least tw o practical applications o f voltage-level detectors.

A nalyze the action of a pulse-w idth m odulator and tell how it can interface an analog
signal w’ith a m icrocom puter.
U se voltage reference ICs to design precise voltage-level detectors.
U se SPIC E to analyze a basic com parator circuit.
2-0 INTRODUCTION
T he nam e operational am plifier was originally given to early high-gain vacuum -tube am
plifiers designed to perform m athem atical operations o f addition, subtraction, m ultiplica
tion, division, differentiation, and integration. They could also be interconnected to solve
differential equations.
T he m odern successor of those am plifiers is the linear integrated-circuit op amp. It
inherits the nam e, w orks at low er voltages, and is available in a variety o f specialized
form s. T oday's op am p is so low in cost that m illions are now used annually. T heir low
cost, versatility, and dependability have expanded their use far beyond applications envi
sioned by early designers. Som e present-day uses for op am ps are in the fields o f signal
conditioning, process control, com m unications, com puters, pow er and signal sources, d is
plays, and testing or m easuring system s. T he op am p is still basically a very good high-
gain dc am plifier.
O n e ’s first experience w ith a linear IC op am p should concentrate on its m ost im
portant and fundam ental properties. A ccordingly, our objectives in this chapter will be to
identify each term inal of the op am p and to learn its purpose, som e o f its electrical lim i
tations, and how to apply it usefully.
2-1 OP AM P TERMINALS
R em em ber from Fig. 1-2 that the circuit sym bol for an op am p is an arrow head that sy m
bolizes high gain and points from input to output in the direction o f signal flow. O p am ps
have five basic term inals: two for supply power, two for input signals, and one for o u t
put. Internally they are com plex, as was show n by the schem atic diagram in Fig. l-3(a).
It is not necessary to know much about the internal operation of the op am p in order
to use it. We will refer to certain internal circuitry, w hen appropriate. T he people who
Ideal
op amp
:o n
FIG U RE 2-1 The ideal op amp has

infinite gain and input resistances plus
zero output resistance.
First Experiences with an Op Amp 15
design and build op am ps have done such an outstanding jo b that external com ponents
connected to the op am p determ ine w hat the overall system will do.
The ideal op amp of Fig. 2-1 has infinite gain and infinite frequency response. The in
put terminals draw no signal or bias currents and exhibit infinite input resistance. O utput im
pedance is zero ohms, and the powrer supply voltages are without limit. We now exam ine the
function of each op amp terminal to learn som ething about the lim itations of a real op amp.
2-1.1 Power Supply Terminals

O p am p term inals labeled + V and — V identify those op am p term inals that m ust be co n
nected to the pow er supply (see Fig. 2-2 and A ppendices I and 2). N ote that the pow er
supply has three term inals: positive, negative, and pow er supply com m on. T he pow er sup
ply com m on term inal may or may not be w ired to earth ground via the third w ire o f line
cord. A ll voltage m easurem ents are m ade with respect to p o w er supply com m on.
Bipolar power supply
(+) terminal
( - ) terminal
(a) Actual wiring from power supply to op amp.
+V
Power supply comm on symbol
(b) Typical schem atic representations of supplying power to an op amp.
FIGURE 2-2 Wiring power and load to an op amp.

16 Chapter 2
T he pow er supply in Fig. 2-2 is called a bipolar or split supply and has typical val
ues o f ± 1 5 V. Som e op am ps are now designed to operate from a single-polarity supply
such as + 5 or + 1 5 V and ground. N ote that the com m on is not w ired to the op am p in
Fig. 2-2. C urrents returning to the supply from the op am p m ust return through external
circuit elem ents such as the load resistor RL. T he m axim um supply voltage that can be
applied betw een + V and — V is typically 36 V or ± 1 8 V.
2-1.2 Output Terminal

In Fig. 2-2 the op am p ’s output term inal is connected to one side o f the load resistor R L.
The other side of R L is wired to ground. O utput voltage V0 is m easured with respect to
ground. Since there is only one output term inal in an op am p, it is called a single-ended
output. There is a lim it to the current that can be draw n from the output term inal o f an op
am p, usually on the order o f 5 to 10 mA. There are also lim its on the output term inal’s
voltage levels; these lim its are set by the supply voltages and by the op am p ’s output tran
sistors (see also A ppendix 1, “O utput Voltage Swing as a Function o f Supply Voltage”).
T hese output transistors need about 1 to 2 V from collector to em itter to ensure that they
are acting as am plifiers and not as sw itches. Thus the output term inal can rise ap proxi
mately to w ithin 1 V o f + V and drop to w ithin 2 V o f —V. The upper lim it o f VQ is called
the positive saturation voltage, + Vsah and the low er lim it is called the negative saturation
voltage, —Vsal. For exam ple, with a supply voltage o f ± 1 5 V, + Vsa( = + 1 4 V and —Vsat
= —13 V. Therefore, VQ is restricted to a sym m etrical peak-to-peak sw ing o f ± 13 V. Both
cu rren t and voltage lim its place a m inim u m value on the load resistan ce R t o f 2 k fl.
However, op am ps are now available especially for applications that operate from low sup
ply voltages ( + 3 .3 V) and have M O S rather than bipolar output transistors. The output o f
these op am ps can be brought to w ithin m illivolts o f either + l / or —V
M ost op am ps, like the 741, have internal circuitry that autom atically lim its current
draw n from the output term inal. Even w ith a short circuit for R L, output current is lim
ited to about 25 mA, as noted in A ppendix 1. T his feature prevents destruction o f the op
am p in the event o f a short circuit.
2-1.3 Input Terminals
In Fig. 2-3 there are tw o input term inals, labeled — and + . They are called differential in
pu t term inals because output voltage Va depends on the difference in voltage betw een
them , Ech and the gain o f the am plifier, A OL. As show n in Fig. 2-3(a), the output term inal
is positive with respect to ground w hen the ( + ) input is positive w ith respect to, or above,
the ( —) input. W hen Ed is reversed in Fig. 2-3(b) to m ake the ( + ) input negative w ith re
spect to, or below, the ( —) input, V0 becom es negative w ith respect to ground.
We conclude from Fig. 2-3 that the polarity o f the output term inal is the sam e as
the polarity of ( + ) input term inal w ith respect to the ( —) input term inal. M oreover, the
polarity of the output term inal is opposite or inverted from the polarity o f the ( —) input
term inal. For these reasons, the ( —) input is designated the inverting input and the ( + )
input the noninverting input (see A ppendix 1).
It is im portant to em phasize that the polarity o f VQ depends only on the difference in
voltage between inverting and noninverting inputs. This difference voltage can be found by
First Experiences with an Op Amp 17
V0 = A OLEd = +V,
(a) V0 goes positive when the (+) input is more

positive than (above) the ( -) input, Ed - (+).
FIG U RE 2-3 Polarity of single

-inp u t
Vo = A 0L E d = -V , ended output voltage Va depends on
the polarity of differential input volt
age Ej. If the ( + ) input is above the
( —) input, Ed is positive and V0 is
above ground at +Vrsal. If the (+ ) in
(b) VQ goes negative when the (+) input is less put is below the ( —) input, Ed is nega
positive than (below) the ( - ) input, Ed - (-). tive and V0 is below ground at - Vsat.
Ed = voltage at the ( + ) input — voltage at the ( —) input ( 2 - 1)
Both input voltages are m easured with respect to ground . T he sign o f E d tells us (I) the
polarity o f the ( + ) input w ith respect to the ( - ) input and (2 ) the polarity o f the output
term inal w ith respect to ground. This equation holds if the inverting input is grounded, if
the noninverting input is grounded, and even if both inputs are above or below ground p o
tential. Thus, if the polarity o f Ed m atches the op a m p ’s sym bol, the output voltage goes
to + V sal. W hen the polarity of Ed is opposite the op a m p ’s sym bol, the output voltage
goes to - Vsat.
Review. We have chosen the w ords in Fig. 2-3 very carefully. T hey sim plify
analysis o f open-loop operation (no conn ectio n from o u tp u t to eith er input). A n o th er
m em ory aid is this: If the ( + ) input is above the ( —) input, the output is above ground
and at + Vsal. If the ( + ) input is below the ( —) input, the output is below ground at —Vsal.
2-1.4 Input Bias Currents and Offset Voltage
T he input term inals o f real op am ps draw tiny bias currents and signal currents to acti
vate the internal transistors. T he input term inals also have a sm all im balance called input
18 Chapter 2
offset voltage, Vio. It is m odeled as a voltage source Vio in series w ith the ( + ) input. In
C hapter 9, the effects of Vio are explained in detail.
We must learn m uch m ore about op am p circuit operation, particularly involving
negative feedback, before we can m easure bias currents and offset voltage. For this rea
son, in these introductory chapters we will assum e that both are negligible.
2-2 OPEN-LOOP VOLTAGE GAIN
2-2.1 Definition
R efer to Fig. 2-3. O utput voltage V0 is determ ined by Ed and the open-loop voltage g a in ,
A o u A o l is called open-loop voltage gain because possible feedback connections from
output term inal to input term inals are left open. A ccordingly, VQ is expressed by the rela
tionship
output voltage = differential input voltage X open-loop gain

(2- 2)
V0 = E d * A o l
2-2.2 Differential Input Voltage, E d
T he value of A OL is extrem ely large, often 200,000 or more. R ecall from Section 2-1.2
that V0 can never exceed the positive or negative saturation voltages + Vsat and - Vsal. For
a ± 15-V supply, the saturation voltages are approxim ately ± 1 3 V. T hus, for the op am p
to act as an am plifier, Ed m ust be lim ited to a m axim um voltage o f ± 6 5 jxV. T his co n
clusion is reached by rearranging Eq. (2-2).
+ V^sa« 13 V
-’d m ax = 65 |ulV
Aol 200,000
-V sat -1 3 V
m ax = -6 5 jjiV
- 'd
Aql 200,000
In the laboratory or shop it is difficult to m easure 65 (ulV, because induced noise,
60-H z hum , and leakage currents on the typical test setup can easily generate a m illivolt
(1000 jjiV). Furtherm ore, it is difficult and inconvenient to m easure very high gains. The
op am p also has tiny internal unbalances that act as a small voltage that m ay exceed Ed.
As m entioned in Section 2-1.4, this sm all voltage is called an offset voltage and is dis
cussed in C hapter 9.
2-2.3 Conclusions
T here are three conclusions to be draw n from these brief com m ents. First, V0 in the cir
cuit o f Fig. 2-3 either will be at one of the lim its + Vsa, or —Vsat or will be oscillating b e
tw een these limits. D o n ’t be disturbed, because this behavior is w hat a high-gain am pli
fier usually does. Second, to m aintain VQ betw een these lim its we m ust go to a feedback
First Experiences with an Op Am p 19
type of circuit that forces V0 to depend on stable, precision elem ents such as resistors and
capacitors. Feedback circuits are introduced in C hapter 3.
W ithout learning any m ore about the op am p, it is possible to understand basic co m
parator applications. In a com parator application, the op am p perform s not as an am p li
fier but as a device that tells w hen an unknow n voltage is below, above, or ju s t equal to
a know n reference voltage. B efore introducing the op am p as a com parator in the next
section, E xam ple 2 - 1 is given to illustrate ideas presented thus far.
Example 2-1
In Fig. 2-3, + V = 15 V, - V = - 1 5 V, + Vsal - + 13 V, - V sat = - 1 3 V, and gain A OL =
200,000. A ssum ing ideal conditions, find the m agnitude and polarity o f for each o f the
follow ing input voltages. These input voltages are given w ith respect to ground.
Voltage at Voltage at
( - ) input ( + ) input
(a) -10 fxV - 1 5 jxV

(b) - 1 0 iulV + 15 |ulV
(c) - 1 0 |ulV - 5 |ulV
(d) + 1.000001 v + 1.000000 V
(e) + 5 mV 0 V
(0 0 V + 5 mV
Solution T he polarity o f Va is the sam e as the polarity of the ( + ) input w ith respect to
the ( - ) input. T he ( + ) input is m ore negative than the ( - ) input in (a), (d), and (e). This
is show n by Eq. (2-1), and therefore VQ will go negative. From Eq. (2-2), the m agnitude of
Vo ^ A o l tim es the difference, Ed, between voltages at the ( + ) and ( —) inputs, but if A OL
X Ed exceeds + V or —V} then Va m ust stop at + Vsal or —Vsat- C alculations are sum m arized
as follows:
Polarity of
( + ) input with Theoretical
respect to Vo
[using Eq. (2-1)] ( - ) input [from Eq. (2-2)] Actual V„
-5 |ulV - - 5 |ulV X 200,000 = - 1 . 0 V -1 3 V

(a)
(b) 25 jjlV + 25 illV X 200,000 = 5.0 V + 13 V
(c) 5 jxV + 5 |xV X 200,000 - 1.0 V + 13 V
(d) -J |jlV - - 1 (jlV X 200,000 - - 0 .2 V -1 3 V
(e) -5 mV - - 5 mV X 200,000 = - 1 0 0 0 V -1 3 V
(f) 5 mV + 5 mV X 200,000 - 1000 V + 13 V
20 Chapter 2
2-3 ZERO-CROSSIN G DETECTORS ________________________________________________________
2-3.1 Noninverting Zero-Crossing Detector

The op amp in Fig. 2-4(a) operates as a comparator. Its ( + ) input com pares voltage with
a reference voltage of 0 V (Vref = 0 V). When E, is above Vref, V0 equals + Vsat. This is be
cause the voltage at the ( + ) input is more positive than the voltage at the ( —) input. Therefore,
the sign of Ed in Eq. (2-1) is positive. Consequently, Vc>is positive, from Eq. (2-2).
(a) Noninverting: W hen E x is above Vref, Vt) = + 1 ^ .
(b) Inverting: W hen E, is above Vrcf> V0 = - V 5al.
FIG U RE 2-4 Zero-crossing detectors, noninverting in (a) and inverting in (b). If the sig
nal Ej is applied to the ( + ) input, the circuit action is noninverting. If the signal £, is ap
plied to the ( - ) input, the circuit action is inverting.
T he polarity o f V0 “tells’’ if E , is above or below Vref. T he transition o f V0 tells when

Ej crossed the reference and in w hat direction. For exam ple, w hen Va m akes a positive-
going transition from —Vsat to + K sal, it indicates that £*, ju st crossed 0 in the positive d i
rection. T he circuit o f Fig. 2-4(a) is a noninverting zero-crossing detector.
2-3.2 Inverting Zero-Crossing Detector
T he op am p ’s ( - ) input in Fig. 2-4(b) com pares E f w ith a reference voltage o f 0 V (Vref

= 0 V). T his circuit is an inverting zero-crossing detector. T he w aveshapes o f VQ versus
tim e and Va versus E f in Fig. 2-4(b) can be explained by the follow ing sum m ary:
1. If E, is m ore positive than Vref, then V0 equals - Vsat.

2. W here Et crosses the reference going positive, Va m akes a negative-going transition
from + Vsat to - Vsat.
Summary. If the signal or voltage to be m onitored is connected to the ( + ) in

put, a noninverting com parator results. If the signal or voltage to be m onitored is co n
nected to the ( —) input, an inverting com parator results.
W hen V0 = + Vsa(, the signal is above (m ore positive than) Vref in a noninverting
com parator and below (m ore negative than) Vref in an inverting com parator.
2-4 POSITIVE- AND NEGATIVE-VOLTAGE-LEVEL DETECTO RS _______________________
2-4.1 Positive-Level Detectors

In Fig. 2-5 a positive reference voltage Vref is applied to one o f the op a m p ’s inputs. T his
m eans that the op am p is set up as a com parator to detect a positive voltage. If the volt
age to be sensed, E h is applied to the op a m p ’s ( + ) input, the result is a noninverting p o s
itive-level detector. Its operation is show n by the w aveshapes in Fig. 2-5(a). W hen E x is
above Vref, V0 equals + Vsat. W hen £, is below Vref, V0 equals —Vsat.
If Ej is applied to the inverting input as in Fig. 2-5(b), the circuit is an inverting p o s
itive-level detector. Its operation can be sum m arized by the statem ent: W hen E-, is above
Kef, V0 equals —Vsat. This circuit action can be seen m ore clearly by observing the plot
o f Ej and Vref versus tim e in Fig. 2-5(b).
2-4.2 Negative-Level Detectors

Figure 2-6(a) is a noninverting negative-level detector This circuit detects when input signal
Ej crosses the negative voltage - Vref. W hen Et is above - Vref, VQ equals + Vsat. W hen E , is
below —Vref, V0 = —Vsaj. The circuit of Fig. 2-6(b) is an inverting negative-level detector
W hen E ( is above - Vref, V0 equals - Vsat> and when Ej is below - Vref, V0 equals + Vsat.
2-5 TYPICAL APPLICATIONS OF VOLTAGE-LEVEL D ETECTO RS ______________________
2-5.1 Adjustable Reference Voltage
ICs are available to set p recise voltage references. T hese referen ce chips w ill be in tro
duced in the next section. In this section a resistive divider netw ork is used to set Vref.
F igure 2-7 show s how to m ake an adjustable reference voltage. Two iO -kH resistors and
22 Chapter 2
(a) Noninverting: W hen E , is above
+v +K, +vQ
(b) Inverting: When £,- is above
FIG U RE 2-5 Positive-voltage-level detector, noninverting in (a) and inverting in (b). If

the signal E, is applied to the ( + ) input, the circuit action is noninverting. If the signal E-t
is applied to the ( —) input, the circuit action is inverting.
a 10-kfi potentiom eter are connected in series to m ake a 1-mA voltage divider. Each
kilohm o f resistance corresponds to a voltage drop o f 1 V. Vref can be set to any value
betw een - 5 and + 5 V. R em ove the — V connection to the bottom 10-kf2 resistor and
substitute a ground. You now have a 0.5-m A divider, and Vref can be adjusted from 5 to
10 V.
2-5.2 Sound-Activated Switch

Figure 2-8 first shows how to make an adjustable reference voltage o f 0 to 100 mV. Pick
a 10-kH pot, 5-kH resistor, and + I5 - V supply to generate a convenient large adjustable
voltage of 0 to 10 V. N ext connect a 100:1 (approxim ately) voltage divider that divides
the 0-to-10-V adjustm ent dow n to the desired 0-to-100-m V adjustable reference voltage.
{Note: Pick the large 100-kH divider resistor to be 10 tim es the potentiom eter resistance;
this avoids loading dow n the 0-to -10-V adjustm ent.)
24 Chapter 2
Sonalert + 15 V
alarm or
+ 15 V lamp
+V
0 tn m n m V
A
No. 1893
SCR
-6
5 kn
C106B
0 to +10 V
o - io k n
}
Reset
} Ej I
-V
switch
v
M icrophone
FIG U RE 2-8 A sound-activated switch is made by connecting the output of

a noninverting voltage-level detector to an alarm circuit.
1. O pen the reset sw itch to turn off both SCR and alarm.
2. In a quiet environm ent, adjust the sensitivity control until Va ju st sw ings to ~ V SM.
3. C lose the reset sw itch. The alarm should rem ain off.
A ny noise signal w ill now generate an ac voltage and be picked up by the m icro
phone as an input. T he first positive sw ing o f E t above Vrel drives Va to + Vsat. T he diode
now conducts a current pulse of about 1 mA into the gate, G, o f the silicon-controlled
rectifier (SCR). Norm ally, the S C R ’s anode, A , and cathode, K, term inals act like an open
sw itch. How ever, the gate current pulse m akes the SCR turn on, and now the anode and
cathode term inals act like a closed sw itch. The audible or visual alarm is now activated.
Furtherm ore, the alarm stays on because once an SCR has been turned on, it stays on u n
til its an o d e -cath o d e circuit is opened.
T he circuit of Fig. 2-8 can be m odified to photograph high-speed events such as a
bullet penetrating a glass bulb. Som e cam eras have m echanical sw itch contacts that close
to activate a stroboscopic flash. To build this sound-activated flash circuit, rem ove the
alarm and connect anode and cathode term inals to the strobe input in place o f the cam
era sw itch. Turn off the room lights. O pen the cam era shutter and fire the rifle at the glass
bulb. T he rifle ’s sound activates the sw itch. T he strobe does the w ork o f apparently sto p
ping the bullet in midair. C lose the shutter. T he position o f the bullet in relation to the
bulb in the picture can be adjusted experim entally by m oving the m icrophone closer to or
farther aw ay from the rifle.
2-5.3 Light-Column Voltmeter
A light-colum n voltm eter displays a colum n o f light w hose height is proportional to volt
age. M anufacturers o f audio and m edical eq u ip m en t m ay replace analog m eter panels
with light-colum n voltm eters because they are easier to read at a distance.
First Exp eriences with an Op Am p 25
A light-colum n voltm eter is constructed in the circuit o f Fig. 2-9. R cal is adjusted
so that 1 m A flow s through the equal resistor divider netw ork to R ]0. Ten separate ref
erence voltages are established in 1-V steps from 1 V to 10 V.
W hen Ei = 0 V or is less than 1 V, the outputs o f all op am ps are at - Vsat. T he sil
icon diodes protect the light-em itting diodes against excessive reverse bias voltage. W hen
+ 15 V = +V
A
FIGURE 2-9 Light-column voltmeter. Reference voltages to each op amp are

in steps of 1 V. As Et is increased from 1 V to 10 V, LED1 through LED 10 light
in sequence. R { to R [0 are 1% resistors. The op amps are 741 8-pin mini-DIPS.
26 Chapter 2
Ej is increased to a value betw een I and 2 V, only the output o f op am p 1 goes positive
to light L E D I. Note that the op am p ’s output current is autom atically lim ited by the op
am p to its short-circuit value approxim ately 20 to 25 mA. T he 220-H output resistors d i
vert heat away from the op amp.
As Ei is increased, the L ED s light in num erical order. This circuit can also be built
using tw o-an d -o n e-h alf L M 324 quad op am ps; som e m anufacturers have designed IC
packages for this particular application, such as N ational S em ico n d u cto r’s LM 3914.
2-5.4 Sm oke Detector
A nother practical application of a voltage-level detector is a sm oke or dust particle d e

tector, as show n in Fig. 2-10. The lam p and photoconductive cell are m ounted in an en
closed cham ber that adm its sm oke or dust but not external light. T he p hotoconductor is a
light-sensitive resistor. In the absence o f sm oke or dust, very little light strikes the pho
toconductor and its resistance stays at som e high value, typically several hundred kilo-
hms. T he 10-kH sensitivity control is adjusted until the alarm turns off.
Smoke particles
• Photoconductor
FIGURE 2-10 With no smoke or dust present the 10-kH sensitivity control
is adjusted until the alarm stops. Light reflected off any smoke or dust particles
causes the alarm to sound.
Any particles entering the cham ber cause light to reflect off the particles and strike
the photoconductor. This, in turn, causes the photoconductor’s resistance to decrease and
the voltage across R i to increase. As Ei increases above Vref, V0 sw itches from —Vsat to
+ y sat, causing the alarm to sound. The alarm circuit o f Fig. 2-10 does not include an SCR.
T herefore, w hen the particles leave the cham ber, the photoconductor’s resistance increases
and the alarm turns off. If you w ant the alarm to stay on, use the SCR alarm circuit show n
in Fig. 2-8. The lam p and photoresistor m ust be m ounted in a flat black, lightproof box
that adm its smoke. A m bient (room ) light prevents proper operation. T he resistive netw ork
at the input of the op am p form s a W heatstone bridge. This circuit can be used to m onitor
the level of dust particles in a clean room environm ent.
2-6 VOLTAGE R EFER EN C E ICs _____________________________________________________________
2-6.1 Introduction
V oltage reference ICs are used to provide a precise voltage for circuit and system de
signers, especially w hen setting the reference voltage for com parator circuits as well as
A/D or D/A converters. Any fluctuation on the reference pin(s) o f converter devices pro
duces an inaccuracy in the conversion. Fluctuations on the reference input to a com para
tor can result in data being lost or erroneous data being sent to a com puter system . In
Figs. 2-7 and 2-8, we needed a reference voltage, Vref, and used a resistor divider netw ork
connected between the supply voltages or the positive supply and ground. A lthough this
circuit may be adequate for som e quick-testing or low -cost designs, a better solution is to
use a precision voltage reference chip. M any o f these chips are inexpensive (less than a
dollar), set a constant output voltage independent o f tem perature, and can be operated
from a w ide range of input pow er supply voltages. Variations in pow er supply voltages
do not affect their output reference voltage. Som e o f these chips use the bandgap diode
principle to produce a constant voltage o f 1.2 V. This tem perature-independent voltage is
followed by an am plifier and buffer (am plifiers and buffers are topics covered in C hapter
3) to provide standard output voltages such as 2.5 V, 5 V, or 10 V. O ther reference chips
use a Z ener diode as the reference follow ed by a buffer and am plifier to provide output
voltages such as + 5 V and - 1 0 V, as well as ± 5 V and ± 1 0 V tracking outputs. Som e
of the m ost com m only used IC voltage reference chips are the REF-01 (4- 10 V), REF-02
(5 V), and REF-03 (2.5 V). W e’ll use the REF-02 IC as an introduction to precision volt
age reference devices.
2-6.2 REF-02
The R EF-02 IC outputs a stable + 5 .0 V, w hich can be adjusted by ± 6 % ( ± 3 0 0 mV) u s
ing one external potentiom eter as show n in Fig. 2 - 11(a). The 1 0 -k fl potentiom eter al
lows the actual output voltage to be adjusted from 4.7 to 5.3 V. T hus for an 8-bit A/D
converter the reference voltage can be set to 5.12 V, creating a resolution o f 20 m V /bit.
(R esolution of A/D converters is discussed in detail in C hapter 14.) T he R EF-02 can o p
erate from an input supply voltage o f from 7 to 40 V, m aking it an ideal voltage refer
ence device for a w ide range o f applications. Two com m on package styles are show n in
Figs. 2 - 1 1(b) and (c).
2-6.3 REF-02/Voltage Level Detector Applications
Figure 2 -1 1(d) shows how the REF-02 can be connected to an op am p com parator to set
the reference voltage at 5.0 V. In this circuit, the adjustm ent potentiom eter is not used and
the REF-02 is used in its basic configuration. In this application, Vref for the com parator
If your application requires a stable but variable reference voltage o f 0 to 5.0 V you
still may use the R E F-02 w ith a potentiom eter connected betw een the R E F -0 2 ’s output
term inal and com m on, as show n in Fig. 2 -1 1(e). {Note: T he 5-kH potentiom eter in this
figure allow s us to vary for the com parator.) T his po ten tio m eter is not being used to
adjust the output voltage o f the R EF-02 but rather the input reference to the com parator
so that Vref can be varied from 0 to 5.0 V. You still may use the circuit o f Fig. 2 -1 1(a) if
you need to set the R E F -0 2 ’s m axim um output voltage to 5.0 V ± 3 0 0 mV. T he tem p er
ature pin (pin 3) is used if the R E F-02 is being used as a tem perature sensor. For an ex
am ple, refer to A nalog D evices’ Web Site, specifically the R E F -0 2 ’s data sheet, to see this
device as a sensor in a tem perature controller application.
2-7 SIGNAL PROCESSIN G WITH VOLTAGE LEV EL DETECTO RS _____________________
2-7.1 Introduction
Arm ed with only the know ledge gained thus far, we will m ake a sine-to-square w ave co n
verter, an analog-to-digital converter, and a pulse-w idth m odulator out o f the versatile op
amp. T hese open-loop com parator (or voltage-level detector) applications are offered to
show how easy it is to use op am ps.
2-7.2 Sine-to-Square Wave Converter
The zero-crossing detector o f Fig. 2-4 will convert the output o f a sine-w ave from a func
tion generator into a variable-frequency square wave. If E t is a sine wave, triangular wave,
or a wave o f any other shape that is sym m etrical around zero, the zero-crossing d etecto r’s
output will be square. T he frequency of £ , should be below 100 Hz, for reasons that are
explained in C hapter 10.
2-7.3 Sawtooth-to-Pulse Wave Converter
Zener Diode Method: The voltage level detector circuits o f Section 2-4 can be
used to convert a saw tooth wave to a pulse w ave provided that the output o f the op am p
is modified to create only a positive pulse. T his m odification is show n in Fig. 2.12(a) and
consists o f a silicon diode, a resistor, and a zener diode in series. W hen the output volt
age o f the op am p is at + V sa!, the resistor lim its the current to appro x im ately 5 mA,
enough current to cause zener breakdow n. For this condition the output voltage o f the cir
cuit, V09 equals the zener voltage. Vz 5 4.7 V in Fig. 2.12(a). W hen the op a m p ’s output
voltage is at —Vsal, diode D1 is reversed biased and the op a m p ’s output current is zero,
hence V0 = 0 V. This circuit is a quick way o f converting a saw tooth-to-pulse wave that
is T T L com patible. T he input and output w aveform s are show n in Figs. 2.12(b) and (c),
respectively. For this application, however, a better m ethod is to use an integrated circuit
called a com parator because we can get V0 to sw ing betw een 0 and 5 V w ithout the ex
ternal diodes.
o 14
lOo
o 13
Il o FIG U RE 2-13 Connection diagram
for the LM339 quad comparator. Four
voltage comparators are contained in
- V or gnd one 14-pin dual-in-line package.
Power supply terminals. Pins 3 and 12 are positive and negative supply volt
age term inals, respectively, for all four com parators. M axim um supply voltage betw een
pins 3 and 12 is ± 1 8 V. In m ost applications, the negative supply term inal, pin 12, is
grounded. T hen pin 3 can be any voltage from 2 to 36 V dc. T he L M 339 is used p rim ar
ily for single-supply operation.
Output terminals. T he output term inal o f each op am p is an o p en-collector npn

transistor. Each transistor collector is connected to the respective output term inals 2, 1,
14, and 13. All em itters are connected together and then to pin 12. If pin 12 is grounded,
the output term inal acts like a sw itch. A closed sw itch extends the ground from pin 12 to
the output term inal [see Fig. 2-14(b)].
If you w ant the output to go high w hen the sw itch is open, you m ust install a pull-
up resistor and an external voltage source. As show n in Fig. 2 - 14(a), this feature allow s
easy interfacing betw een a ± 1 5 -V analog system and a 5-V digital system . T he output
term inal should not sink more than 16 mA.
Input terminals. T he input term inals are differential. Use Eq. (2-1) to determ ine
the sign for Ed. If Ed is p ositive, the output sw itch is o pen, as in Fig. 2 - 14(a). If Ed is neg
ative, the output sw itch is closed, as in Fig. 2 - 14(b). U nlike many other op am ps, the in
put term inals can be brought dow n to ground potential w hen pin 12 is grounded.
146 Chapter 5
Design Exam ple 5-18

(a) D esign the circuit in Fig. 5 -17(b) to differentiate signals in the range from 500 Hz to
1000 Hz. C hoose C, = 0.1 fi¥. (b) If the input signal is e in = 0.4 sin 2 tt (1000 )t volts, w hat
is the expression of the output voltage?
Solution (a) R earranging Eq. (5-16)
1
*,■ = = 1.59 kft
277(1 X 103 Hz)(0.1 X 10-6 F)
Let T2 = 207’| and solve for f y fro m Eq. (5-17).
20
= 31.8 kH
Rf 277(1 X 103 H z)(0.1 X 10~ 6 F)
U se Eq. (5-16) to solve for Cf .
1
= 0.005 /jlF
C/ 277(1 X 103 H z )(3 1 .8 k fi)
(b) F rom Fig. 5 - 17(a), the output voltage is
d etn
= -R /C r
dt
T hen,
vc = -(3 1 .8 kn)(0.1 /i.F)— [0.4 sin 2tt(1000)«]

dt
= - ( 3 1 .8 kflX O .l / aF )(0.4)(27 t)( 1000)cos[27t( 1000)t]
= ~ 8 cos[27r(1000)t] V
Note: W ith large values o f Rf , the output o f the op am p may go into saturation because it
is m ultiplied by the input sig n al’s peak value, frequency, and the constant 2 tt.
5-13 PSPICE SIMULATION
Ln this section, we w ill use PSpice and sim ulate the perform ance o f the differential volt
age-to-current converter w ith a grounded load as show n in Fig. 5-5. U se an IPROBE to
m easure IL. Place the follow ing parts on the right-hand side o f the w ork area:
Selected Applications of Op Am ps 147
Draw => Get New Part
Part Num ber Library
= >uA 741 1 eval»slb

= > VDC 4 source.slb
= > R 5 analog.slb
= > GLOBAL 4 p o r ts lb
= > AGND 5 p o rt.slb
= > IP R O B E 1 special.sib
A rrange the parts as show n in the schem atic o f Fig. 5-5 but include the IPROBE to m ea
sure IL. Set the four resistors labeled R as /?, = R 2 = R 3 = #4 = 10 k f l, E x = 5 V, E 2 =
3 V, and R L = 1 k fl. N ow select Analysis = > Setup = > DC Sweep. O pen DC Sweep
and select
Swept Van Type = > Voltage Source
Sweep TVpe = > Linear
Now set
Name = > V I, Start Value = > 5V, End Value = > 5V, Increment = > IV
Select
Nested Sweep = > Swept Var. Type = > Voltage Source

= > Sweep Type = > Linear
N ow set
Name = > V2, Start Value = > 3V, End Value = > 3V, Increment = > IV
In this sim ulation you do not w ant to run Probe. Rem ove Probe execution by
Analysis = > Probe Setup = >
Click
Do Not Auto-Run Probe
Save the file w ith an .SCH extension and click Analysis = > Simulate. T he com pleted
circuit w ith current value l L is show n in Fig. 5-18.
148 Chapter 5
15 V - 7
Vo
15 V
VO
FIGURE 5-18 PSpice model of Fig. 5-5.
PROBLEMS
5-1. Refer to Example 5-1 and Fig. 5-1. Assume that 1FS = 1 mA and meter winding resistance
Rm = 1 k f l If Ei = ~ 1.0 V and /?, = Ik ft, find (a) (b) V0.
5-2. A 1-mA movement, with R„, = 1 kfl, is to be substituted in thecircuit inFig. 5-2. Redesign
the R; resistors for full-scale meter deflection when (a) Ej = ± 6 V dc; (b) Et =
6 V rms; (c) E, = 6 V p-p; (d) E, = 6 V peak.
5-3. In Fig. P5-3 complete the schematic wiring between op amp,diodes, and milliammeter.The
current through the meter must be steered from right to left.
5-4. Calculate a value for Ridc in Fig. P5-3 so that the meter readsfull scale whenEt—5Vand
the range switch is on the 5-V position.
5-5. Consider that the range switch is in the 5-V position in Fig. P5-3.Calculatevalues for the
following resistors to give a full-scale meter deflection of 5 V: (a)Rirms for Et= 5 Vrms; (b)
Rj p-p for Ej = 5 V p-p; (c) R, peak for E, = 5 V peak.
5-6. With the circuit conditions shown in Problem 5-4, (a) which diodes are conducting? (b) Find
Va. Assume that diode drops are 0.6 V.
5-7. For the constant-current source shown in Fig. P5-7, (a) draw the current direction, the emit
ter arrow, and state if the transistor is npn or pnp\ (b) find /; (c) find VL.
5-8. If V0 = 11 V and Et = 5 V in Fig. 5-3, find Vz.
5-9. / 1 must equal 20 mA in Fig. 5-4 when £ f- = - 10 V. Find Rh
5-10. Define a floating load.
5-11. In Fig. 5-5, E2 = 0 V, R = 10 kH, and RL = 5 k i l Find lL> VL, and V0 for (a) Et = - 2 V;
(b) £, = + 2 V.
150 Chapter 5
5-12. In Fig. 5-5, E ] = 0 V, R = 10 kft, and R L = 1 kCl. Find l u VLt and V0 for (a) E2 = - 2 V;
(b) E2 = +2 V.
5-13. In Fig. 5-5, E, = E2 = - 5 V, and R = RL = 5 k f l Find IL, VL, and V*.
5-14. Replace Vz in Fig. 5-6 with a 900-H resistor. Find lL.
5-15. Sketch an op amp circuit that will draw short-circuit current from a signal source and con
vert the short-circuit current to a voltage.
5-16. A CL5M9M photocell has a resistance of about 10 k il under an illumination of 2 fc. If Et -
—10 V in Fig. 5-9, calculate Rf for an output Va of 0.2 V when the photoconductive cell is
illuminated by 2 fc.
5-17. Change multiplier resistor mR in Fig. 5-10 to 49 kfi. Find lL.
5-18. A solar cell that has a maximum short-circuit current of 0.1 A = ISc is installed in the cir
cuit in Fig. 5-12. (a) Select RF to give Va = 10 V when Isc = 0.1 A. (b) A 50-[xA meter
movement is to indicate full scale when Isc = 0.1 A. Find /?scaie if RM = 5 kfl.
5-19. Resistor Rj is changed to 10 kfl in Example 5-14. Find the phase angle 6.
5-20. Design a phase shifter to give a —90° shift at 1 Hz. Choose C, from 0.001, 0.01, 0 .1, or 1.0
/ j F . R, must lie between 2 and 100 kfl.
5-21. Design a -9 0 ° phase shift at 1590 Hz. Then for your design, calculate (a) 6 at 15 Hz; (b) 6 at
15 kHz.
5-22. Calculate the net current through Rf in Fig. 5 -14(a) if the AD590 temperature is 100°C. Then
find V..
5-23. Calculate the net current through Rf in Fig. 5 -14(b) when the temperature is 100°F. Find V0.
5-24. Calculate the value of fl/in Fig. 5 -14(a) to design a signal conditioning circuit that interfaces
with a microcontroller’s A/D converter. The voltage range of the converter is 0 to 5 V.
5-25. Use a simulation program and design an integrating circuit. The input sugnal is
ein = t sin 20007rt V
5-26. Use a simulation program and design a differentiating circuit. The input signal is (a) sine
wave of 500 Hz and a peak value of 0.2 V; (b) square wave of 500 Hz and a peak value of
0.2 V; (c) cosine wave of 500 Hz and a peak value of 0.2 V.
CHAPTER 6
Signal Generators
LEARNING OBJECTIVES _________________________________________________
U pon com pletion o f this chapter on signal generators, you w ill be able to:
• E xplain the operation o f a m ultivibrator circuit, sketch its output voltage w aveshapes,
and calculate its frequency of oscillation.
• M ake a one-shot m ultivibrator and explain the purpose o f this circuit.
• Show how tw o op am ps, three resistors, and one capacitor can be connected to form an
inexpensive triangle/square-w ave generator.
• Predict the frequency o f oscillation and am plitude o f the voltages in a bipolar or unipo
lar triangle-w ave generator and identify its disadvantages.
• Build a saw tooth wave generator and tell how it can be used as a voltage-to-frequency
converter, frequency m odulator, or frequency shift key circuit.
• C on n ect an A D 630 balanced m o d u la to r/d em o d u lato r to o p erate as a sw itch ed gain
am plifier.
151
152 Chapter 6
C onnect the A D 630 to an op am p circuit to m ake a precision triangle-w ave generator

w hose output voltage am plitude can be adjusted independently o f the oscillating fre
quency, and vice versa.
B uild, test, m easure, and explain the operation o f an A D 639 universal trigonom etric
function generator w hen it is w ired to generate sine functions.
C onnect the A D 639 to the triangle-w ave generator to m ake a superb p recisio n sine-w ave
generator. Its oscillating frequency can be adjusted over a w ide frequency range by a
single resistor, w ithout changing am plitude.
Know about the operation o f a single IC function generator.
6-0 INTRODUCTION
Up to now our m ain concern has been to use the op am p in circuits that process signals.
In this chapter w e concentrate on op am p circuits that generate signals. Four o f the m ost
com m on and useful signals are described by their shape w hen viewed on an oscilloscope.
T hey are the square wave, triangular wave, saw tooth wave, and sine wave. A ccordingly,
the signal generator is classified by the shape o f the wave it generates. Som e circuits are
so w idely used that they have been assigned a special name. For exam ple, the first circuit
presented in Section 6-1 is a m ultivibrator that generates prim arily square waves and ex
ponential waves. Som e ICs that generate these w aveform s from a single IC are available.
How ever, you may need a w aveform quickly and not have on hand one o f these function
generator ICs.
6-1 FREE-RUNNING MULTIVIBRATOR
6-1.1 Multivibrator Action
A fre e-ru n n in g or astable m ultivibrator is a square-w ave generator. T he circuit o f Fig.

6 - 1 is a m u ltiv ib rato r circu it and looks so m eth in g like a co m p arato r w ith h y steresis
(C hapter 4), except that the input voltage is replaced by a capacitor. R esistors R i and R 2
form a voltage divider to feed back a fraction o f the output to the ( + ) input. W hen V0 is
at + Vsat, as show n in Fig. 6 -l(a ), the feedback voltage is called the upper-threshold volt
age VUT. VUT is given in Eq. ( 4 -1) and repeated here for convenience:
V,rr = ( + y sa|)
R esistor Rf provides a feedback path to the ( —) input. W hen V0 is at + Vsat, current

I + flows through Rf to charge capacitor C tow ard VUT. A s long as the capacitor voltage
Vc is less than VUTt the output voltage rem ains at + Vsal.
W hen Vc charges to a value slightly greater than VUT, the ( —) input goes positive with
respect to the ( + ) input. This sw itches the output from + Vsat to —Vsal. The ( + ) input is now
held negative with respect to ground because the feedback voltage is negative and given by
154 Chapter 6
lished except that C now has an initial charge equal to VLT. T he cap acito r w ill discharge
from VLT to 0 V and then recharge to VUT> and the process is repeating. F ree-running m ul
tivibrator action is sum m arized as follow s:
1. W hen V0 — — Vsal, C discharges from VUT to VLT and sw itches V0 to + Vsat.

2. W hen V0 = + V sat, C charges from VLT to VUT and sw itches V0 to —Vsat.
T he tim e needed for C to charge and discharge determ ines the frequency o f the m ultivi
brator.
6-1.2 Frequency of Oscillation
T he capacitor and output-voltage w aveform s for the free-running m ultivibrator are show n
in Fig. 6-2. R esistor R 2 is chosen to equal 0 .86/?i to sim plify calculation o f cap acito r
charge time. Tim e intervals /] and t2 show how Vc and VD change w ith tim e for Figs.
6 - 1(a) and (b), respectively. Tim e intervals t x and t2 are equal to the product o f /fy-and C.
T he period o f oscillation, T, is the tim e needed for one com plete cycle. S ince T is
the sum o f t, and t2,
T = 2Rf C for R2 = O M R (6-3a)
v»
(volts)
A
V
vo
= ^+vv sai
10 T=2RC=y
Tim e
10 /, - RjC
15
FIGURE 6-2 Voltage waveshapes for the multivibrator of Fig. 6-1.

Signal G enerators 155
T he frequency of o s c illa tio n /is the reciprocal o f period T and is expressed by
(6-3b)
w here T is in s e c o n d s ,/in hertz, / ^ i n ohm s, and C in farads.
Example 6-1
In Fig. 6-1, if R { = 100 k fl, R 2 = 86 k fl, + V sat = + 1 5 V, and - V sat = - 1 5 V, find (a)
VuT>' (b) V l t -
Solution (a) By Eq. (6-1),
(b) By Eq. (6-2),

86 k fl
Example 6-2
Find the period o f the m ultivibrator in E xam ple 6-1 if Rf = 100 k f i and C = 0.1 fxF.
Solution U sing Eq. (6-3a), T - (2)(100 k H )(0 .1 pF ) = 0.020 s = 20 ms.
Example 6-3
Find the frequency o f oscillation for the m ultivibrator o f E xam ple 6-2.
Solution From Eq. (6-3b),
Example 6-4
Show w hy 7 = 2 Rf C w hen R 2 = 0.86R, as stated in Eq. (6-3a).
Solution T he tim e required for a capacitor C to charge through a resistor Rf from som e
starting capacitor voltage toward som e aim ing voltage to a stop voltage is expressed g en
erally as
aim — start
aim — stop
156 Chapter 6
Applying the equation to Fig. 6-2 yields
+ V/sat ~ VLT
11 = Rf C In
+ Vsat - V u r
If the m agnitudes of + V sat and — VsiLX are equal, the term in parentheses sim plifies to
In
Since In 2.718 = 1, the In term can be reduced to I if
R| 2R 2
----- —------= 2.718 or R 2 = 0.86/?,
Now /, = R jC and t2 = R fC if R 2 = 0.86/? |. Therefore, T = t x + t2 = 2Rf C.
6-2 ONE-SHOT MULTIVIBRATOR ___________________________________________________________
6-2.1 Introduction
A o n e-sh o t m u ltivib ra to r generates a single o u tp u t pulse in response to an input sig

nal. T he length o f the o u tp u t pulse depends only on external co m p o n en ts (resistors and
cap acito rs) co n nected to the op am p. As show n in Fig. 6-3, the o n e-sh o t generates a
sin g le o u tpu t pulse on the neg ative-going edge o f £,. The d uration o f the input pulse
can be longer or sh o rter than the ex pected output pulse. T he duratio n o f the o u tp u t
p ulse is represen ted by r in Fig. 6-3. S ince r can be changed only by ch an g ing re sis
tors or capacitors, the o n e-sh o t can be con sid ered a p u lse stretch er T his is b ecause the
w idth o f the pulse can be lon ger than the input pulse. M oreover, the o n e-sh o t in tro
duces an idea o f an ad ju stab le delay, that is, the delay betw een the tim e w hen E, goes
negative and the tim e for VQ to go positive again. O peration o f the o n e-sh o t w ill be
stu d ied in three parts: (1) the stable state, (2) tran sition to the tim ing state, and (3) the
tim ing state.
6-2.2 Stable State
In Fig. 6-4(a), VQ is at + Vsat. Voltage divider /?, and R2 feeds back VUT to the ( + ) input.
V u r is given by Eq. (6-1). The diode D x clam ps the ( —) input at approxim ately + 0 .5 V.
T he ( + ) input is positive with respect to the ( —) input, and the high open-loop gain tim es
the differential input voltage (Ed = 2.1 - 0.5 = 1.6 V) holds V0 at + K sat.
Chapter 6
O,
Dt
FIGURE 6-4 Monostable or one-shot multivibrator.

Next we select and C. B egin by m aking a trial choice for C = 0.05 /xF. T hen ca l
culate a value for /?, to see if R t is greater than 10 k fl. F rom Eq. (6-6),
2.8
= 14 k a
4/C 4(1000 H z)(0.05 jjlF)
In practice it w ould be prudent for to be a 12 -k fl resistor in series w ith a 0 to 5 -k fl pot.

T he 5 - k fl pot m ay then be adjusted for an oscillation frequency o f precisely 1.00 kHz.
6-3.3 Unipolar Triangle-Wave Generator
T he bipolar triangle-w ave generator circuit o f Fig. 6-6 can be changed to produce a u nipo
lar triangle w ave output. S im ply add a diode in series w ith p R as show n in Fig. 6-7.
C ircuit operation is studied by reference to the w aveshapes in Fig. 6-7(b).
W hen VB is at + Vsal, the diode stops current flow through p R and sets V lt at 0 V.
W hen VB is at —ysat, the diode allow s current flow through p R and sets VUT at a value o f
~ ysat + 0-6 V (6-7 a)

V ur = —
P
Frequency of oscillation is then given approxim ately by
(6-7b)
2 R,C
Example 6-7
Find the approxim ate peak voltage and frequency for the unipolar triangle-w ave g enerator
in Fig. 6-7.
Solution C alculate
_ p R _ 28 k f l _
P ~ R ~ 10 k f l _
Find the peak value of VA from Eq. (6-7a):
-1/ t + 0 .6 V - 1 3 .8 V + 0.6 V
VUT ~ - 4.7 V
2.8
From Eq. (6-7b),
2.8
f = = 1000 Hz
2R £ 2(28 kH )(0.05 jjlF )
N ote the change in R , value from Fig. 6-6(a) to Fig. 6-7(a).

Chapter 6
FIGURE 6-7 Diode D in (a) converts the bipolar triangle-wave generator into
a unipolar triangle-wave generator. Waveshapes are shown in (b). (a) Basic
unipolar triangle-wave generator; oscillating frequency is 1000 Hz. (b) Output-
voltage waveshapes.
6-4 SAWTOOTH-WAVE GENERATOR _____________________________________________________
6-4.1 Circuit Operation
A low -parts-count saw tooth-w ave generator circuit is show n in Fig. 6-8(a). Op am p A is
a ram p generator. Since E t is negative, Voramp can only ram p up. T he rate o f rise of the
ram p voltage is constant at
(6- 8)
t R tC
The ram p voltage is m onitored by the ( + ) input o f com parator 301B. If Voramp is
below Vref, the com parator’s output is negative. D iodes protect the transistors against ex
cessive reverse bias.
W hen Voramp rises to ju st exceed Vref, the output Vocomp goes to positive saturation.
This forward biases “dum p’' transistor Q D into saturation. T he saturated transistor acts as
a short circuit across the integrating capacitor C. C discharges quickly through QD to es
sentially 0 V. W hen Vocomp goes positive, it turns on Q x to short-circuit the lO-kO p o
tentiom eter. This drops Vref to alm ost zero volts.
As C discharges toward 0 V, it drives Vorarnp rapidly toward 0 V. Voramp drops be
low Vref, causing lôcomp to go negative and turn off Q D. C begins charging linearly, and
generation o f a new saw tooth wave begins.
6-4.2 Sawtooth Waveshape Analysis
The ram p voltage rises at a rate of 1 V per m illisecond in Fig. 6-8(b). M eanw hile, Vocomp
is shown to be negative. W hen the ram p crosses Vref, VOCOmp snaps positive to drive the
ram p voltage quickly toward 0 V. As Voramp snaps to 0 V, the co m p arator’s output is re
set to negative saturation. R am p operation is sum m arized in Fig. 6-8(c).
6-4.3 Design Procedure
T he tim e for one saw tooth-w ave period can be derived m ost efficiently by analogy with
a fam iliar experience.
distance (of rise)

tim e (of rise) = (6-9a)
speed (of rise)
(6-9b)
Since frequency is the reciprocal o f the period
(6-9c)
Design Example 6-8
D esig n a sa w to o th -w av e g e n e ra to r to have a 10-V p ea k o u tp u t and a fre q u en c y o f

100 Hz. L et Ei = 1 V.
Design Procedure
1. D esign a voltage divider to give a reference voltage Vref = + 1 0 V for op am p B in
Fig. 6-8(a).
2. L e t’s select a ram p rate rise o f 1 V /m s. P ick any R tC com b in atio n to give 1.0 ms.
T herefore, let’s select /?,* = 10 k f I and C = 0.1 fiF. ■
3. T he resulting circuit is show n in Fig. 6-8(a).
4. Ei may be m ade from a voltage divider and voltage follow er to m ake an ideal voltage
source (see Section 3.7).
5. A lternatively, you could pick a trial value for R tC and solve for £ , in Eq. (6-9b)
6. C heck the design values in Eq. 6-9c.
6-4.4 Voltage-to-Frequency Converter
T here are tw o w ays to change or m odulate the o scillating frequency o f Fig. 6-8. We see
from Eq. (6-9c) that the frequency is directly pro p o rtio n al to E L and inversely p ro p o r
tional to Vref. T he advantages and disadvantages o f each m ethod are exam ined w ith an
exam ple.
T his type o f frequency m odulation by Vref has tw o disadvantages w ith respect to
control o f frequency by E t. First, the relationship betw een input voltage Vrcf and output
frequency is not linear. Second, the saw too th ’s peak output voltage is not constant, since
it varies directly w ith Vref.
6-4.5 Frequency Modulation and Frequency Shift Keying
E xam ples 6-9 and 6-10 indicate one way o f achieving fre q u en c y m odulation (FM ). T hus,
if the am plitude o f Ei varies, the frequency o f the saw tooth oscillator w ill be changed or
m odulated. If E { is keyed betw een tw o voltage levels, the saw tooth oscillator changes fre
quencies. T his type o f application is called fre q u en c y shift keying (FSK ) and is used for
data transm ission. T hese tw o preset frequencies correspond to “0 ” and “ 1” states (co m
m only called space and m ark) in binary.
168 Chapter 6
Example 6-9
If Ei is doubled to - 2 V in Fig. 6-8, find the new frequency o f oscillation.
S o lu tio n In Eq. (6 —9c) use | E,
1
(10 X 103 n x o . l X 10“ 6 F) 10 V
---------1 = ^ = M00Hz\
1.0 X 10-3 s 10 V I V
For E, = - 2 V ,/ = (2 V )(100 H z/V) = 200 Hz. T hus as £ , changes from 0 V to - 1 0 V, fre

quency changes from 0 Hz to 1 kHz. The peak am plitude o f the saw tooth w ave rem ains
equal to Vref (10 V) for all frequencies.
Example 6-10
K eep E h and C at their value show n in Fig. 6-8(a). R educe Vref by o n e-h alf to 5 V. Is
the frequency doubled or halved?
Solution From Exam ple 6-8 and Eq. (6-9c),
1V _ (1000 H z)/V
f (ms) Vref Kef
For Vrei = 10 V , / = 100 Hz. For Vref = 5 V the frequency is doubled to 200 Hz. As Vref is
reduced from 10 V to 0 V, the frequency is increased from 100 H z to a very high value.
6-4.6 Disadvantages
T he triangle-w ave generators o f Section 6-3 are inexpensive and reliable. However, they
have tw o disadvantages. T he rates o f rise and fall o f the triangle w ave are unequal. A lso,
the peak values o f both triangle-w ave and square-w ave outputs are unequal, because the
m agnitudes o f + V sat and - V sat are unequal.
In the next section w e substitute an A D 630 for the com parator. T his will give the
equivalent o f precisely equal square-w ave ± voltages that w ill a lso be equal to the ±
peak values o f triangle-w ave voltage. O nce we have m ade a precision triangle-w ave g en
erator, we w ill use it to drive a new state-of-the-art trigonom etric function g enerator to
make a precision sine-w ave generator.
170 Chapter 6
6-5 BALANCED MODULATOR/DEMODULATOR, THE AD630 _________________________
6-5.1 Introduction
T he A D 630 is an advanced integrated circuit. It has 20 pins, w hich allow s this versatile
sw itched voltage gain IC to act as a m odulator, dem odulator, phase detector, and m ulti
plexer, as well as perform other signal conditioning tasks. We connect the A D 630, as in
Fig. 6-9(a), as a controlled sw itched gain ( + 1 or —1) am plifier. T his p articu lar applica
tion w ill be exam ined by discussing the role perform ed by the d om inant term inals.
6-5.2 Input and Output Terminals
T he input signal Vref is connected to m odulation pins 16 and 17 in Fig. 6-9, and thus to the
inputs of two am plifiers, A and B. The gain o f A is program m ed for —1 and B for + 1 by
shorting term inals (1) 13 to 14, (2) 15 to 19 to 20, (3) 16 to 17, and (4) grounding pin 1.
T he carrier input term inal, pin 9 (in this application), determ ines w hich am plifier,
A or B , is connected to the o u tp u t term in al. If pin 9 is a b o ve the v o ltag e at pin 10
(ground), am plifier B is selected. Voltage at output pin 13 then equals Vref tim es (4-1).
If pin 9 voltage is below ground (negative), am plifier A is selected and output pin 13
equals l/ref times ( —1). (Note that in com m unication circuits, Vref is called the analog data
or signal voltage, Vc is called a chopper or carrier voltage, and VQ is the m odulated output.
T hat is, the am plitude o f the low -frequency signal voltage is impressed upon the higher-
frequency carrier wave— hence the names selected for the A D 630’s input and output terminals.)
6-5.3 Input-Output Waveforms
Vrcf is a dc voltage of 5.0 V in Fig. 6-9(b). Vc is a 100-Hz square w ave w ith peak am
plitudes that m ust exceed ± 1 mV. O utput voltage V0 is show n in Fig. 6-9(c) to sw itch
synchronously with Vc from + l/ref to —\/ref> and vice versa. We are going to replace the
unpredictable ± Vsat o f the 301 com parator in Fig. 6-6 with precisely + or —Vref. M oreover,
Vref can be adjusted easily to any required value. As show n in the next sectio n , Vref
w ill set the positive and negative peak values o f both triangle-w ave and square-w ave
generators.
6-6 PRECISION TRIANGLE/SQUARE-WAVE GENERATOR _____________________________
O nly six parts plus a voltage source, Vref, m ake up the versatile precision triangle- and square-
wave generator in Fig. 6 -10(a). Circuit operation is explained by referencing the waveshapes
in Fig. 6 - 10(b). We begin at time zero. Square-wave output Vos begins at —Vref or —5 V. This
forces the triangle wave Vot to go positive from a starting point of — = —5 V. D uring this
time, pin 9 is below ground to select an AD630 gain o f —1 and holds Vos at —5 V.
172 Chapter 6
T he easiest way to find the frequency o f oscillation is to begin w ith the rate o f rise o f the
triangle wave, Vol/ t y in volts per second. T he rate o f rise o f the triangle wave, from 0 to
0.5 ms in Fig. 6-10(b), is found from
v„
t R,C (6- ,0 )
T he tim e t for a half-cycle is 772, and during this tim e, Vol changes by 2Vref. S ubstituting
these for t and Vot into Eq. (6-10), w e obtain
2 V re f = Vn f
(6-11)
772 R tC
and solve for both period T and frequency o f o sc illa tio n /:
T = 4 RfC and (6-12)
N ote that Vref cancels out in Eqs. (6-11) and (6-12). This is a very im portant ad
vantage. T he peak output voltages of both square- and triangle-w ave signals are set by
+ Vref. As Vref is adjusted, the frequency o f oscillation does not change.
Example 6-11
M ake a triangle/square-w ave generator that has peak voltages o f ± 5 V and oscillates at a
frequency o f 1.0 kHz.
Solution C hoose Vref = 5.0 V. For low im pedance, Vref should be the output o f an op am p.
A rbitrarily choose C = 0.01 /xF. F rom Eq. (6-12),
1 1
*/ =
4 /C 4(1000)(0.01 jjlF)
For a fine adjustm ent of the output frequency, m ake /?; from a 2 2 -k fl resistor in series w ith
a 5- or 10-kH variable resistor.
6-7 SINE-W AVE GENERATION SU R V EY
C om m ercial function generators produce triangular, square, and sinusoidal signals w hose
frequency and am plitude can be changed by the user. To obtain a sine-w ave output, the
triangle w ave is passed through a shaping netw ork m ade o f carefully selected resistors
Signal Generators 173
and diodes (see Fig. 7-19). T he sine waves thus produced are reasonably good. H owever,
there is inevitably som e distortion, particularly at the peaks o f the sine wave. A nother so
lution is to use an IC function generator chip such as M A X IM ’s M A X 038, w hich is ca
pable of producing sine, square, and triangle w aveform s fro m 1 H z to 20 M Hz.
W hen an application requires a single-frequency sine wave, conventional oscillators
use phase-shifting techniques that usually em ploy (1) tw o R C tuning netw orks, and (2)
com plex am plitude lim iting circuitry. To m inim ize distortion, the lim it circuit m ust usu
ally be custom -adjusted for each oscillator. T he frequency o f this oscillator is difficult to
vary because tw o R C netw orks m ust be varied and their values m ust track w ithin ± 1%.
W aveform s m ay also be generated by using the A D 630 w ith a universal trig o n o
metric function generator, the A D 639. The A D 630 has already been used to generate a
precision triangle wave w hose frequency and am plitudes are precise and easy to adjust.
We w ill co n n ect the triangle-w ave outp u t Vol o f Fig. 6-10(a) to an A D 639 universal
trigonom etric function generator. The resulting circuit w ill have the best qualities o f a p re
cision sine-w ave generator whose fre q u en c y will be easily a djustable.
6-8 UNIVERSAL TRIGONOMETRIC FUNCTION GENERATOR,

THEAD639 _________________________________________________________________________________
6-8.1 Introduction
T he A D 639 is a state -o f-th e-art trig o n o m etric fu n ctio n generator. It w ill perfo rm all
trigonom etric functions in real tim e, including sin, cos, tan, cosec, sec, and cotan. W hen
a calculator perform s a trig function, the operator punches in a num ber corresponding to
the num ber of angular degrees and punches SIN. T he calculator pauses, then displays a
num ber indicating the sine o f the angle. T hat is, a num ber for angle 0 is entered and the
calculator produces a num ber for sin 0.
T he A D 639 accepts an input voltage that represents the angle. It is called the angle
voltage, Vang. For the A D 639, the angle voltage is found from
(6-13)
F our input term inals are available. However, we shall look at only the single active
input that generates sin functions. T he output voltage will equal sin 0 or 10 sin 0, d e
pending how the internal gain control is pin program m ed.
6-8.2 Sine Function Operation
T he A D 639 is w ired to output VQ = 1 sin 0 in Fig. 6-11. T here are four input term inals:
1, 2, 7, and 8. W ired as show n, the chip perform s a sine function. Pins 3, 4, and 10 co n
trol gain. N orm ally, 3 and 4 are grounded so that pin 10 can activate the internal gain co n
trol. A gain o f 1 results w hen pin 10 is w ired to — Vs or pin 9. W ire pin 10 to + Vs or pin
174 Chapter 6
-v, +V*
-15 V + 15 V
9 10 16
Angle
voltage Vn = 1 sin 0
AJ3639A
5 7
12 8
T
(a)
(a) °a
,(V)
FIG U RE 6-11 The AD639 is pin-programmed in (a) to act as a sine function genera
tor. Each ± 20 mV of input angle voltage corresponds to an input angle of 0 = ±1°.
Output Va equals 1 X sin 0. (a) The AD639A is pin-programmed to output the sine of the
angle voltage; (b) output voltage V0 equals the sine of 8 if 9 is represented by an angle
voltage of 20 mV per angular degree.
16 and obtain a gain of + 1 0 . Then VQ — 10 sin 0. Pin 6 is a precision 1.80-V reference

voltage that corresponds to an angle voltage of 90° (see Eq. (6-13)). We analyze sine func
tion operation by an exam ple.
Example 6-12
C a lc u late the req u ired in p u t angle voltage and resu ltan t o u tp u t v o ltag e fo r an g les o f
(a) ± 4 5 °; (b) ± 9 0 °; (c) ± 2 2 5 °; (d) ± 4 0 5 °.
Solution From Eq. (6-13) and Fig. 6-11,
(a) — 2 0 ( ±45° ) = ± 0 .9 0 V, = 1 sin (± 4 5 ° ) = ± 0 .7 0 7 V.
(b) Vang = (± 9 0 ° ) = ± 1 .8 0 V, V0 = 1 sin (± 9 0 ° ) = ± 1 .0 V.
(c) Vane = ( ± 2 2 5 ° ) = ± 4 .5 0 V, V„ = 1 sin (± 2 2 5 ° ) = ± 0 .7 0 7 V.
(d) Vang = 20 (± 4 0 5 ° ) = ± 8 .1 0 V, = 1 sin (± 4 0 5 ° ) = ± 0 .7 0 7 V.
E xam ple 6-12 clearly illustrates that the A D 639, rem arkable as it is, cannot output
the sine of, for exam ple, 36,000°. This w ould require an angle voltage o f 720 V T he nor
mal ± 1 5 -V supply lim its the guaranteed usable input angle to ± 5 0 0 ° , or ± 1 0 .0 0 0 V. We
extend the results o f E xam ple 6-12 to sum m arize briefly the perform ance o f the sine fu n c
tion generator in Table 6-1 and Fig. 6 -1 1(b).
In Fig. 6 -1 1(b), VQ is plotted against both Vang and 0. A study o f this figure shows
that if Vang could be varied linearly by a triangle wave, VD w ould vary sinusoidally. Further,
if the frequency o f the triangle wave could be varied easily, the sine-w ave frequency could
easily be tuned, adjusted, or varied. We pursue this observation in the next section.
6-9 PRECISION SINE-WAVE GENERATOR ________________________________________________
C onnect the precision triangle-w ave oscillator in Fig. 6-10 to the sine function generator
in Fig. 6-11 to construct the precision sine-w ave generator in Fig. 6-12. As a bonus, we
also have precision triangle-w ave and square-w ave outputs. The 1.80-V reference voltage
o f the A D 639 is connected to m odulation inputs 16 and 17 o f the A D 630 m odulator (Fig.
6-9). C ircuit operation is now exam ined by reference to Fig. 6-12.
176 Chapter 6
TABLE 6-1 AD639 Sine Functions3
Input Output (V)
0 Angle V0 - 1 sin 6 = 10 sin 6

(angular voltage, (wire pin (wire pin
degrees) V.„fi (V) 10 to 9) 10 to 16)
0 0.00 0.000 0.000

±45 ± 0 .9 0 ± 0.707 ± 7.07
±90 ± 1 .8 0 ± 1.000 ± 10.07
±135 ± 2 .7 0 ± 0.707 ± 7.07
±180 ± 3 .6 0 0.000 0.000
±225 ± 4 .5 0 ± 0.707 ± 7 .0 7
±270 ± 5 .4 0 ± 1.000 ± 1 0 .0 0
±315 ± 6 .3 0 ± 0.707 ± 7 .0 7
±360 ± 7 .2 0 0.000 0.00
±405 ± 8 .1 0 ± 0.707 ± 7 .0 7
±450 ± 9 .0 0 ± 1.000 ± 1 0 .0 0
±495 ± 9 .9 0 ± 0.707 ± 7.07
±500 ± 1 0 .0 0 ± 0.643 ± 6 .4 3
a C onnect terminal 10 to 9 to pin program V0 = sin 0; or connect pin 10 to 16 to pin program Va = 10

sin 0. Input angle voltage Vang = (20 m V /l°C ) 0.
Triangle-wave rise time, 0 to T/2 in Fig. 6-12(b)
1. A D 63 0
a. Pin 13 is at —Vref = —1.8 V, causing
b. Pin 9 to select gain = - 1 to hold 13 at - 1 . 8 V and
c. O p am p output voltage to ram p up.
2. Op am p
a. Pin 6 ram ps from —Vref = —1.8 V tow ard + V ref = 1.8 V to
b. H old pin 9 of the A D 630 negative and
c. D rive input 1 o f the A D 639 w ith an angle voltage linearly from - 1 . 8 to 1.8 V.
3. A D 639
a. Pin l ’s input angle voltage corresponds to an input angle that varies linearly
from - 9 0 ° to + 9 0 °.
b. Pin 13 outputs VQ — 10 sin 6 from —10 to + 1 0 V.
W hen op am p pin 6 reaches + 1 .8 V, pin 9 o f the A D 630 goes positive to select a

gain o f + 1 . Its output, in 13, snaps to + 1 .8 V. T his begins the fa ll time.
Triangle-wave fall time, T/2 to T in Fig. 6-12(b)
l . A D 630: C auses the triangle w ave to ram p down from + 1 .8 V to - 1 .8 V. A t - 1 . 8 V,

gain is sw itched to —1 and a new cycle begins.
(a) Precision sine-wave generator circuit.

( a ) £/\ pus '
FIG U RE 6-12 Frequency of the precision sine-square-triangle-wave generator in (a)

can be easily changed by adjusting Output waveshapes are shown in (b). Their am
plitudes are independent of frequency.
178 Chapter 6
2. Op am p: A pplies an angle voltage to input pin 1 o f the A D 639 that varies linearly
from + 1 .8 to ~ 1 .8 V.
3. A D 639: Its input angle voltage corresponds to an input angle o f 0 = + 9 0 ° to - 9 0 ° .
Pin 13 outputs a sine w ave that varies from + 1 0 to —10 V.
T he frequency of o s c illa tio n ,/ is determ ined by R if C, and the op am p in Fig. 6 - 12(a) from
( 6 - | 4 )
Peak am plitudes of the triangle wave and square w ave are precisely equal to ± 1 .8 V. T he
sine w ave has peak am plitude o f ± 1 0 V and is synchronized to the triangle wave (for the
± 1-V peak, change the A D 639 pin 10 connection to —Vs).
E x a m p le 6-13
Let C = 0.025 |jlF in Fig. 6 - 12(a) (two 0.05-fjiF capacitors in series). How does frequency
change as Ri is changed from 10 k f l to 100 k fl?
S o lu tio n F rom Eq. (6-14),
/*_ l __ * 1 | | /»_ l t _ *Q Q |^| ^

J ~ 4(10 kfl)(0 .0 2 5 |xF) ” Z 1 ~ 4(100 k fl)(0 .0 2 5 julF) ~~ Z
E xam ple 6-13 show s the overw helm ing superiority o f this m ulti w ave generator.
Frequency is tuned easily an d with precision. A lthough we have used the A D 639 to gen
erate a sine wave, this chip is a universal trigonom etric function g enerator and could be
rew ired to produce other trigonom etric w aveform s.
6-9.3 High-Frequency Waveform Generator
M a x im ’s M A C 038 is a 20-pin, high-frequency, precision function g enerator w hose fre

quency can be controlled over a w ide range from 0.1 Hz to 20 M H z. It can produce sine,
trian g le, or sq uare w aves at o utputs that are selected by an ap p ro p riate co d e at tw o
(transistor-transistor logic) T T L -com patible select inputs. It can also produce saw tooth or
pulse outputs as well as a synchronizing output.
A pplications for this versatile chip include function or FSK generation, V C O s (volt
age controlled oscillator), frequency m odulators, and synthesizers, as well as pulse-w idth
m odulation.
6-10 PSPiCE SIMULATION O F SIGNAL GENERATOR CIRCUITS ______________________
In this section, we will use PSpice to m odel and sim ulate the perform ance o f four signal
generator circuits studied in this chapter: the free-running m ultivibrator, the one-shot m ul
tivibrator, the bipolar triangle-w ave generator, and the unipolar triangle-w ave generator.
6-10.1 Free-Running Multivibrator
R efer to Fig. 6-1 and create the PSpice model o f the circuit. Set the resistor and capacitor
values as given in E xam ples 6-1 and 6-2. Use the 741 op am p if you are using the evalu
ation softw are package o f PSpice. O btain a plot o f Vc and VQ versus tim e. For the circuit
to begin oscillating in a sim ulation it is necessary to provide a sudden im pulse at the be
ginning of the sim ulation. This stim ulus can be generated by using tw o pulse sources in
stead o f two dc sources to pow er the op amp. T he pulse w idth will be set to a m uch longer
tim e interval than the period o f oscillation and will have a fast rise tim e to sim ulate sud
denly applying pow er to the circuit. To begin, place the follow ing parts in the w ork area.
Draw = > Get New Part
= > uA741 1 eval.slb

= > VPULSE 2 source.sib
= > R 3 analog.slb
= > C J analog.sJb
= > G LO BAL 4 port.sib
= > AGND 4 port.sib
{Note: We are using VPULSE instead o f VDC for the op am p supplies.) A rrange the parts
and w ire the circuit as show n in Fig. 6-1. C hange the attributes o f the parts as given in
E xam ples 6-1 and 6-2. Set up each o f the VPULSE attributes by double-clicking on the
sym bol. In the pop-up box, set the values for VI (m inim um input voltage), V2 (m axim um
input voltage), TD (tim e delay), TR (rise tim e), TF (fall tim e), PW (pulse w idth), and
PER (period):
VI = > OV = > Save Attr
V2 = > 15 V = > Save Attr = > Change Display = > Both name and value
TD = > 0 = > Save Attr
TR = > Ins = > Save Attr
TF = > Ins = > Save Attr
PW = > 50s = > Save Attr
PER = > 51s = > Save Attr
E ach pulse attribute pop-up box is set up the sam e because the —V supply has been ro
tated 180 degrees, as we have done w ith the dc supplies connected to pin 4 o f other op
am ps. D ouble-click on the lead from the capacitor and label it Vc. D ouble-click on the
lead from the output term inal of the op am p and label it Vo (see Fig. 6-13).
182 Chapter 6
In order to obtain a plot o f E , and V0 versus tim e, w e m ust initialize the transient menu.
Analysis = > Setup = > Select Transient

Click Transient = > Print Step: = > lOOus
= > Final Time: = > 10ms
Save the circuit as a file w ith the .SCH extension. Run the sim ulation
Analysis = > Simulate
In the P robe w'indow, select
Trace = > Add = > V[Ei]

= > V[Vo]
Label the plots and obtain a printout as show n in Fig. 6-16.
15 v r
10 v ^ V0
Input
5V _ pulse,
0 V
/
-5 V
-10 V
Period -►
-1 5 V 1 1---------------1
- 1 ------------1 FIGURE 6-16 Waveforms for the
Os 2 ms 4 ms 6 ms 8.ms 10 ms one-shot multivibrator modeled in
Tim e PSpice in Fig. 6-15.
6-10.3 Bipolar Triangle-Wave Generator
C reate the P Spice m odel o f the bipolar triangle-w ave generator show n in Fig. 6-6. Use
tw o 741 op am ps. O btain a plot o f VA and V0 versus tim e. Place the follow ing parts in the
w ork area.
Draw => Qet New Part

= > VPULSE 2 source.sib
= > R 4 analog.sib
= > C 1 analog.slb
= > G LOBAL 6 port, sib
= > AGND 5 port.slb
A rrange the parts, change the attributes, and w ire the circuit as show n in Fig. 6-6. T he
VPULSE attributes are set the sam e as they are in Section 6-10.1 (see Fig. 6-17).
FIG U RE 6-17 Bipolar triangle-wave generator modeled in PSpice.
In order to obtain a plot of VA and VQ versus tim e, set the transient m enu.
Analysis = > Setup = > Select Transient

C lick Transient = > Print Step: = > 0.01ms
Save the circuit as a file with the .SCH extension. Run the sim ulation

In the Probe w indow, select
Trace = > Add = > V[VA]

= > V[Vo]
6-10.4 Unipolar Triangle-Wave Generator
M odify the P S pice m odel o f Fig. 6-17 to create the un ip o lar trian g le-w av e g en erato r
show n in Fig. 6-7. From the P Spice parts list, obtain a 1N4002 diode and place it in se
ries w ith pR (see Fig. 6-19). Save the circuit w ith the .SCH extension.
15 V
10 V
5V
0V
-5 V
-10 V
-1 5 V
Os 0.5 ms 1.0 ms 1.5 ms 2.0 ms 2.5 ms 3.0 ms
Tim e
FIGURE 6-20 Waveforms VA and V(, for the unipolar triangle-wave genera
tor of Fig. 6-19.
PROBLEMS __________________________________________________________________________
6-1. Make two drawings of a multivibrator circuit with R\ = 100 kH, R2 = 86 kfl, Rf = 10 kfl,
and C = 0.01 /xF. Show the direction of current through C and calculate both VUT and VLT
for (a) = +Ksa( = 15 V; (b) V, = - V sa( = - 1 5 V.
6-2. Calculate the frequency of oscillation for the multivibrator circuit in Problem 6-1.
6-3. In Problem 6-1, if C is changed to 0.1 ^F, do you expect the output frequency to oscillate at
500 Hz? (See Example 6-3.) What could you do to Rf to increase frequency to 1000 Hz?
6-4. The monostable multivibrator of Figs. 6-4 and 6-5 generates a negative output pulse in re
sponse to a negative-going input signal. How would you change these circuits to get a posi
tive output pulse for a positive-going input edge?
6-5. Explain what is meant by monostable recovery time.
6-6. Sketch a one-shot multivibrator circuit whose output will deliver a negative pulse lasting
1 ms with a recovery time of about 0.1 ms.
6 -7 . Assume for simplicity that saturation voltages in the triangle-wave oscillator of Fig. 6-6 are
± 15 V, Rj = R = 10 kH, C = 0.1 fiF, and pR = 50 kfl. Find the peak triangle-wave voltages
and oscillating frequency.
6-8. Refer to the triangular-wave oscillator circuit of Fig. 6-6. What happens to peak output volt
ages and oscillating frequency if you (a) double pR only; (b) double R, only; (c) double ca
pacitor C only?
6-9. Change pR to 14 kfl and C to 0.1 jjlF in the unipolar triangle-wave generator of Fig. 6-7.
Find the resulting peak output voltage and frequency of oscillation. (See Example 6-7.)
186 Chapter 6
6-10. In the sawtooth-wave generator of Fig. 6-8(a), let Vref = 1 V, R, = 10 kfl, and C = 0.1 jjlF.
(a) Find an expression for frequency / i n terms of Ev
(b) C alculate/for Et = I V and E, = 2 V.
6-11. These questions refer to the AD630 balanced modulator circuit in Fig. 6-9.
(a) Name the application for which the A.D630 is wired.
(b) When pin 9 is at a positive voltage, which amplifier is selected, and what is the value of
\/»o?•
(c) Suppose that Vrcl. is a ± l-V-peak sine wave and pin 9 is at 1 V; what happens at V0 when
pin 9 is changed to - 1 V?
6-12. Figure 6-10 shows a precision triangle/square-wave oscillator.Threecomponentscontrol
peak output voltages and oscillating frequency, R h C, and Vref.
(a) Which does what?
(b) Can the oscillating frequency be adjusted independent of peak outputs, and vice versa?
(c) What must be done to change the frequency from 100 to 500 Hz and the peak voltages
from ±5 V to ±1 V?
6-13. V0 ~ 0.866 V in the sine function generator circuit of Fig. 6-11.
(a) What angle does this represent?
(b) What is the value of the input angle voltage?
6-14. Calculate V0 in Fig. 6-11 when the input angle is 30° and pin 10 is wired to (a) pin 9;
(b) pin 16.
6-15. Design a sine-wave oscillator whose frequency can be varied from 0.5 Hz to 50 Hz with just
a single variable resistor.
CHAPTER 7
Op Amps with Diodes
LEARNING OBJECTIVES ____________________________________________________
U pon com pleting this chapter on op am ps w ith diodes, you w ill be able to:
- D raw the circuit for a precision (or linear) half-w ave rectifier.
• Show current flow and circuit voltages in a precision half-w ave rectifier for either p o s
itive or negative inputs.
• D o the sam e for precision full-w ave rectifiers.
• Sketch tw o types o f precision full-w ave rectifier circuits.
• E xplain the operation o f a peak detector circuit.
• A dd one cap acito r to a p rec isio n half-w ave rectifier to m ake an ac-to -d c co n v erter
(m ean-average-value) circuit.
• Explain the operation o f dead-zone circuits.
• D raw the circuit for and explain the operation o f precision clipper circuits.
187
diode can be designed using an op am p and tw o ordinary diodes. T he result is a pow er
ful circuit capable o f rectifying input signals o f only a few m illivolts.
T he low cost o f this equivalent ideal diode circuit allow s it to be used routinely for
many applications. They can be grouped loosely into the follow ing classifications: linear
half-w ave rectifiers and precision full-w ave rectifiers.
1. L inear half-w ave rectifiers. T he linear half-w ave rectifier circuit delivers an output
that depends on the m agnitude and p o la rity o f the input voltage. It w ill be show n
that the linear half-w ave rectifier circuit can be m odified to perform a variety o f sig
nal-processing applications. T he linear half-w ave rectifier is also called a precision
half-w ave rectifier and acts as an ideal diode.
2. P recision fu ll-w a v e rectifiers. T he precision full-w ave rectifier circuit delivers an
output proportional to the m agnitude but not the polarity o f the input. For exam ple,
the output can be positive at 2 V for inputs o f either + 2 V or - 2 V. Since the ab
solute value o f + 2 V and —2 V is equal to + 2 V, the precision full-w ave rectifier is
also called an absolute-value circuit.
A pplications for both linear half-w ave and precision full-w ave rectifiers includes:
1. D etection o f am plitude-m odulated signals

2. D ead-zone circuits
3. Precision bound circuits or clippers
4. C urrent sw itches
5. W aveshapers
6. Peak-value indicators
7. Sam ple-and-hold circuits
8. A bsolute-value circuits
9. A veraging circuits
10. Signal polarity detectors
1 1. A c-to-dc converters
T he functions listed are often necessary to condition signals before they are applied to an
input of a m icrocontroller.
7-1 LINEAR HALF-WAVE RECTIFIERS ______________________________________________________
7-1.1 Introduction
L inear half-w ave rectifier circuits transm it only one-half cycle o f a signal and elim inate
the other by bounding the output to 0 V. The input half-cycle that is transm itted can be
either inverted or noninverted. It can also experience gain or attenuation, or rem ain un
changed in m agnitude, depending on the choice o f resistors and placem ent o f diodes in
the op am p circuit.
In Fig. 7-2(b), negative input E t forces the op am p output VOA to go positive. This
causes D 2 to conduct. T he circ u it then acts like an inverter, since Rf = /?, and VD =
- ( - £ , ) = + £ ,. Since the ( - ) input is at ground potential, diode D , is reverse biased.
Input current is set by £,//?, and gain by - R f /Ri. R em em ber that this gain equation ap
plies only for negative inputs, and V0 can only be positive or zero.
C ircuit operation is sum m arized by the w aveshapes in Fig. 7-3. V0 can only go p o s
itive in a linear response to negative inputs. The m ost im portant property o f this linear
half-w ave rectifier w ill now be exam ined. An ordinary silicon diode or even a hot-carrier
diode requires a few tenths o f volts to becom e forw ard biased. A ny signal voltage below
this threshold voltage cannot be rectified. However, by connecting the diode in the feed
back loop o f an op am p, the threshold voltage o f the diode is essentially elim inated. For
exam ple, in Fig. 7-2(b) let £, be a low voltage o f - 0 .1 V. E i and /?, convert this low v o lt
age to a current that is conducted through D 2. VOA goes to w hatever voltage is required
to supply the necessary diode drop plus the voltage drop across Rf . T hus m illivolts o f in
put voltage can be rectified, since the d io d e’s forw ard bias is supplied autom atically by
the negative feedback action o f the op amp.
and V0A
FIGURE 7-3 Input, output, and

transfer characteristics of a positive-
output, ideal, inverting half-wave
rectifier.
194 Chapter 7
£ , and V
FIGURE 7-6 Input and output voltages for the polarity separator of Fig. 7-5
7-2 PRECISION RECTIFIERS: THE A BSO LU TE-VALU E CIRCUIT _______________________
7-2.1 Introduction
The precision full-w ave rectifier transm its one polarity o f the input signal and inverts the
other. T hus both half-cycles o f an alternating voltage are transm itted but are converted to
a single polarity o f the circu it’s output. T he precision full-w ave rectifier can rectify input
voltages with m illivolt am plitudes.
T his type o f circuit is useful to prepare signals for m ultiplication, averaging, or d e
m odulation. T he characteristics o f an ideal precision rectifier are show n in Fig. 7-7.
T he precision rectifier is also called an absolute-value circuit. The absolute value of
a num ber (or voltage) is equal to its m agnitude regardless o f sign. For exam ple, the absolute
values of | +2 | and |—2 | are +2. T he sym bol 11 m eans “absolute value of.” Figure 1-1 shows
that the output equals the absolute value of the input. In a precision rectifier circuit the o ut
put is either negative or positive, depending on how the diodes are installed.
198 Chapter 7
T he w aveshapes in Fig. 7-8(c) show that V0 is alw ays o f positive polarity and equal
to the absolute value of the input voltage. To obtain negative outputs fo r either polarity
o f E h sim ply reverse the diodes.
High-impedance precision full-wave rectifier. T he second type o f p reci

sion rectifier is show n in Fig. 7-9. T he input signal is connected to the noninverting op
am p inputs to obtain high input im pedance. Figure 7-9(a) show s w hat happens for p o si
tive inputs. Ej and set the current through diode D P. T he ( —) inputs o f both op am ps
are at a potential equal to E L so that no current flow s through R 2>R 3, and R 4. T herefore,
V0 = Ei for all positive input voltages.
W hen Ei goes negative in Fig. 7-9(b), E, and R j set the current through both R ] and R 2
to turn on diode D /V. Since R { = R 2 = R> the anode o f D N goes to 2E f or 2 ( - £ , ) = —4 V.
The ( - ) input of op amp B is at ~ E r The voltage drop across R 3 is 2 E{ —E { or ( - 4 V) —
( —2) = - 2 V. This voltage drop and R 3 establishes a current / 3 through both /?3 and R4 equal
to the input current /. Consequently, V0 is positive when E t is negative. Thus VQ is always
positive despite the polarity of E h so VG = lE t |.
T he w aveshapes for this circuit are the sam e as in Fig. 7-8(c). N ote that the m axi
m um value o f Ei is lim ited by the negative saturation voltage o f the op am ps.
7-3 PEAK D ETECTO RS _______________________________________________________________________
In addition to rectifying a signal precisely, diodes and op am ps can be interconnected to

build a peak detector circuit. This circuit follow s the voltage peaks o f a signal and stores
the hig h est value (alm ost indefinitely) on a capacitor. If a higher peak signal value com es
along, this new value is stored. The highest peak voltage is stored until the capacitor is
discharged by a m echanical or electronic sw itch. This peak detector circuit is also called
a fo llo w -a n d -h o ld circuit or pea k follow er. We shall also see that reversing tw o diodes
changes this circuit from a peak to a valley follower.
7-3.1 Positive Peak Follower and Hold
T he peak follow er-and-hold circuit is shown in Fig. 7-10. It consists o f tw o op am ps, two
diodes, a resistor, a hold capacitor, and a reset switch. Op am p A is a precision half-wave
rectifier that charges C only when input voltage E t exceeds capacitor voltage Vc . Op am p
B is a voltage follow er w hose output signal is equal to Vc . The follow er's high input im
pedance does not allow the capacitor to discharge appreciably.
To analyze circuit operation, let us begin with Fig. 7 - 10(a). W hen E t exceeds Vc,
diode D P is forw ard biased to charge hold capacitor C. As long as Et is greater than Vc ,
C charges tow ard £ :. Consequently, Vc follow s £, as long as E t exceeds Vc . W hen E {
drops below Vc , diode D N turns on as show n in Fig. 7 - 10(b). D iode D P turns off and d is
connects C from the output o f op am p A. D iode D P m ust be a low -leakage-type diode or
the capacitor voltage will discharge (droop). To m inim ize droop, op am p B should require
Op Am ps with Diodes 203
7-4.3 AC-to-DC Converter
A large-value low -leakage capacitor (10-/xF tantalum ) is added to the absolute-value cir
cuit of Fig. 7-13. The resultant circuit is the MAV am plifier or ac-to-dc converter show n
in Fig. 7-14. C apacitor C does the averaging o f the rectified output o f op am p B. It takes
about 50 to 500 cycles of input voltage before the capacitor voltage settles dow n to its fi
nal reading. If the w aveshapes of Fig. 7-12 are applied to the ac-to-dc converter, its o u t
put will be the MAV o f each input signal.
FIGURE 7-14 Add one capacitor to the absolute-value amplifier of Fig. 7-13
to get this ac-to-dc converter or mean-absolute-value amplifier.
7-5 DEAD ZONE CIRCUITS
7-5.1 Introduction
C om parator circuits tell i f a signal is below or above a particular reference voltage. In

contrast w ith the com parator, a dead-zone circuit tells by how m uch a signal is below or
above a reference voltage.
7-5.2 Dead-Zone Circuit with Negative Output
A nalysis of a dead-zone circuit begins w ith the circuit o f Fig. 7-15. A convenient regulated
supply voltage + V and resistor m R establish a reference voltage Uref. Vre( is found from
the equation Vrc{ — + V /m . As will be shown, the negative o f Vref, —Vref, will establish the
dead zone. In Fig. 7-15(a), current I is determ ined by + V and resistor m R at / = + V /m R
D iode D n will conduct for all positive values o f E h clam ping VOA and V qb t0 0 V.
T herefore, all positive inputs are elim inated from affecting the output. In order to get any
Op A m ps with Diodes 205
output at VOA, Ei m ust go negative, as show n in Fig. 7 - 15(b). D iode D P will conduct when
the loop current E t/R through £, exceeds the loop current V/mR through resistor mR.
T he value o f Ei necessary to turn on D P in Fig. 7-15(b) is equal to - Vref. T his co n
clusion is found by equating the currents
= +v
R mR
and solving for E (:
+V
E i = ---------- = - V ref (7 -la )
m
w here
+ \/
^ re f= ------ ( 7 - lb)
m
T hus all values o f E t above - Vref will lie in a dead zone w here they will not be tran s
m itted [see Fig. 7-1 5(c)]. O utputs VOA and VOB will be zero.
W hen Ei is below Vref, £, and VTCf are added and their sum is inverted at output VOA.
VOA is reinverted by op am p B. T hus VOB only has an output w hen E, goes below Vref.
VOB tells you by how many volts £, lies below Vref.
Circuit operation is sum m arized by the w aveshapes o f Fig. 7 - 15(c) and illustrated
by an exam ple.
E x a m p le 7-1
In the circuit o f Fig. 7-15, 4- V = + 15 V, m R = 30 k fi, and R = 10 k f), so that m = 3. Find

(a) Vref; (b) VOA w hen E, = - 1 0 V; (c) w hen E, = - 1 0 V.
S o lu tio n (a) From Eq. (7 -lb ), Vref = + 1 5 V/3 = 5 V. (b) VOA and VOB will equal zero for
all values o f E { above —Vref = - 5 V, from Eq. (7 -la ). T h erefo re, VOA = - E j - Vr&f =
- ( - 1 0 V) - 5 V = + 5 V. (c) Op am p B inverts the output o f VOA so that VOB = - 5 V.
T hus, VOB indicates how m uch E { goes below —Vref. All input signals above — Vref fall in a
dead zone and are elim inated from the output.
7-5.3 Dead-Zone Circuit with Positive Output
If the diodes in Fig. 7-15 are reversed, the result is a positive-output dead-zone circuit as
show n in Fig. 7-16. R eference voltage Vref is found from Eq. (7 -lb ): Vrer = —15 V/3 =
—5 V. W henever Ej goes above —Vref = - ( - 5 V) = + 5 V, the output VOB tells by how
m uch Ei exceeds —Vref. T he dead zone exists for all values o f below — Vrcf.
2R
+ +V0
(b) W aveshapes for precision clipper.
FIGURE 7-18 A precision clipper is made from a bipolar dead-zone circuit plus an
added resistor Rc.
208 Chapter 7
7-5.4 Bipolar-Output Dead-Zone Circuit
T he positive and negative output dead-zone circuits can be com bined as show n in Fig.
7-17 and discussed in Fig. 7-18. The VOA outputs from Figs. 7-15 and 7-16 are connected
to an inverting adder. The adder output VOB tells how much Ej goes above one positive ref
erence voltage and also how m uch E( goes below a different negative reference voltage.
7-6 PRECISION CLIPPER _____________________________________________________________________
A clipper or am plitude lim iter circuit clips off all signals above a positive reference volt
age and all signals below a negative reference voltage. The reference voltages can be
m ade sym m etrical or nonsym m etrical around zero. C onstruction o f a precision clipper cir
cuit is accom plished by adding a single resistor, R c, to a bipolar output dead-zone circuit
as show n in Fig. 7-18. The outputs o f op am ps A and B are each connected to the input
o f the inverting adder. Input signal £, is connected to a third input o f the inverting adder,
via resistor R c . If R c is rem oved, the circuit would act as a dead-zone circuit. However,
w hen R c is present, input voltage Et is subtracted from the dead-zone circu it’s output and
the result is an inverting precision clipper.
C ircuit operation is sum m arized by the w aveshapes in Fig. 7 - 18(b). O utputs VQa
and VOB are inverted and added to ~ E r The plot of V0 versus tim e show s by solid lines
how the clipped output appears. The dashed lines show how the circuit acts as a dead-
zone circuit if R c is removed.
7-7 TRIANGULAR TO-SINE-WAVE CONVERTER _________________________________________
V ariable-frequency sine-w ave oscillators are m uch harder to build than variable-frequency
triangular-w ave generators. The circuit of Fig. 7-19 converts the output o f a triangular-
wave generator into a sine wave that can be adjusted for less than 5% distortion. The
triangle-to-sine-w ave converter is an am plifier w hose gain varies inversely with am plitude
o f the output voltage.
R { and R3 set the slope of V0 at low am plitudes near the zero crossings. As V0 in
creases, the voltage across R 3 increases to begin forw ard biasing D, and Z)3 for positive
outputs, or D 2 and D 4 for negative outputs. W hen these diodes conduct, they shunt feed
back resistance /?3, lowering the gain. This tends to shape the triangular output above about
0.4 V into a sine wave. In order to get rounded tops for the sine-wave output, R 2 and diodes
D5 and D 6 are adjusted to make am plifier gain approach zero at the peaks o f V0.
T he circu it is adjusted by co m paring a 1-kHz sine wave and the o u tp ut o f the
triangle/sine-w ave converter on a dual-trace CRO. /?,, R 2, R 3, and the peak am plitude of
Ej are adjusted in sequence for best sinusoidal shape. The adjustm ents interact, so they
should be repeated as necessary. {Note: A lthough the circuit of Fig. 7-19 will shape a tri
angular wave to a sine wave, the parts count is high, but you may need to generate such
a w aveform with readily available parts. A better solution is to purchase an IC chip that
generates triangle, square, and sine waves in a single package.)
210 Chapter 7
A rrange the parts as show n and change the attributes o f the parts as given in Fig. 7-2. Set
up the sine-w ave attributes by double-clicking the sym bol. In the pop-up w indow change
VOFF, VAMPL, and FREQ
VOFF = > 0 = > Save Attr
VAMPL = > 2V = > Save Attr —> Change Display —> Both name and value
FREQ = > 1kHz = > Save Attr = > Change Display = > Both name and value
C lose the pop-up box. D ouble-click on the lead from the sine wave to R x and label it E h
D ouble-click on the lead from the cathode term inal of diode D 2 and label it V0 (see Fig.
7-20).
_y2
15V
VO
-V
Vam pl = 2V
freq = lk
“ l5V
Vo
FIGURE 7-20 PSpice model of Fig. 7-
In order to obtain a plot o f E, and VG versus tim e, w e m ust initialize the T ransient menu.
Analysis = > Setup = > S elect Transient

C lick Transient = > Print Step: = > 1/us

In the P robe window, select
Trace = > Add = > V[Ei]

= > V[Vo]
L abel the plots and obtain a printout as show n in Fig. 7-21.
Op Am ps with Diodes 215
FIG U RE 7-25 Plot of Vr, versus time for the mean-absolute-value amplifier
in Fig. 7-24.
PROBLEMS _____________________________________________________________________
7-1. What is the absolute value of +3 V and - 3 V?
7-2. If the peak value of E{ — 0.5 V in Fig. 7-1, sketch the waveshapes of VQ vs. t and Va vs. £,
for both a silicon and an ideal diode.
7-3. If E{ is a sine wave with a peak value of 1 V in Figs. 7-2 and 7-3, sketch the waveshapes of
V0 vs. l and VQ vs. Er
7-4. If diodes D\ and D2 are reversed in Fig. 7-2, sketch V0 vs. £, and Va vs. t.
7-5. Sketch the circuit for a signal polarity separator.
7-6. Let both diodes be reversed in Fig. 7-8. What is the value of Vn if £,• = +1 V or E, - - 1 V?
7-7. What is the name of a circuit that follows the voltage peaks of a signal and stores the highest
value?
7-8. How do you reset the hold capacitor’s voltage to zero in a peak follower-and-hold circuit?
7-9. How do you convert the absolute-value amplifier of Fig. 7-13 to an ac-to-dc converter?
7-10. If resistor mR is changed to 50 kH in Example 7-1, find (a) Vref; (b) VOA when E, = 10 V;
(c) when Et = 10 V.
7 - 11. If resistor Rc is removed in Fig. 7-18, sketch Va vs. Et.
CHAPTER 8
Differential,
Instrumentation, and
Bridge Amplifiers
LEARNING O B JEC TIVES _________________________________________________
W hen you com plete this chapter on differential, instrum entation, and bridge am plifiers,
you w ill be able to:
• D raw the circuit for a basic differential am plifier, state its o u tp u t-in p u t equation, and ex
plain why it is superior to a single-input am plifier.
•D e fin e com m on-m ode and differential input voltage.
•D raw the circuit for a differential input to differential output voltage am plifier and add
a differential am plifier to m ake a three-op-am p instrum entation am plifier (IA).
• C alculate the output voltage o f a three-op-am p instrum entation am plifier if you are given
the input voltages and resistance values.
• U se com m ercially available instrum entation am plifiers.
• Explain how the sense and reference term inals o f an IA allow you to (1) elim inate the
effects o f connecting-w ire resistance on load voltage, (2) obtain load current boost, or
(3) m ake a differential voltage-to-current converter (ac current source).
Differential, Instrumentation, and Bridge Amplifiers 217
• E xplain how a strain gage converts tension or com pression forces into a change in re
sistance.
• C onnect strain gages into a passive bridge resistance netw ork to convert gage resistance
change into an output voltage.
•A m p lify the strain gage b rid g e’s differential output w ith an instrum entation am plifier.
• M easure pressure, force, or weight.
• Draw the circuit for a bridge am plifier and show how it converts a change in transducer
resistance to an output voltage.
• U se the bridge am plifier to m ake a tem perature-to-voltage converter.
8-0 INTRODUCTION __________________________________________________________________________
The m ost useful am plifier for m easurem ent, instrum entation, or control is the in stru m en
tation amplifier. It is designed w ith several op am ps and precision resistors, w hich m ake
the circuit extrem ely stable and useful w here accuracy is im portant. T here are now many
integrated circuits available in single packages. A lthough these packages are m ore ex
pensive than a single op am p, w hen perform ance and precision are required, the in stru
m entation am plifier is well w orth the price, because its perform ance cannot be m atched
by the average op amp.
A first cousin and basic block w ithin the instrum entation am plifier is the differen
tial amplifier, also referred to as a subtractor circu it T his chapter begins with the differ
ential am plifier, show ing the applications in w hich it is superior to the ordinary inverting
or noninverting am plifier. T he differential am plifier, w ith som e additions, leads into the
instrum entation am plifier, w hich is discussed in the second part o f this chapter. T he final
sections consider bridge am plifiers, w hich involve both instrum entation and basic differ
ential am plifiers.
8-1 BASIC DIFFERENTIAL AMPLIFIER ______________________________________________________
8-1.1 Introduction
T he differential am plifier can m easure as well as am plify sm all signals that are buried in
m uch larger signals. How the differential am plifier accom plishes this task w ill be studied
in Section 8-2, but first, let us build and analyze the circuit perform ance o f the basic d if
ferential am plifier.
Four precision (1% ) resistors and an op am p m ake up a differential am plifier, as
show n in Fig. 8-1. T here are two input term inals, labeled ( - ) input and ( + ) input, co r
responding to the closest op am p term inal. If E v is replaced by a short circuit, E 2 sees an
inverting am plifier w ith a gain o f —m. T herefore, the output voltage due to E 2 is —m E 2.
N ow Jet E 2 be short-circuited; £ , divides betw'een R and m R to apply a voltage o f E xm!
(1 + m) at the op a m p ’s ( + ) input. This divided voltage sees a noninverting am plifier with
a gain of {m + 1). T he output voltage due to E\ is the divided voltage, E vm!{ 1 + m), tim es
the noninverting am plifier gain, (1 + m), w hich yields m E x. T herefore, E { is am plified at
Differential, Instrum entation, and Bridge A m plifiers 219
8-1.2 Common-Mode Voltage
The output o f the differential am plifier should be 0 w hen E x — E 2. T he sim plest w ay to

apply equal voltages is to w ire the inputs together and connect them to the voltage source
(see Fig. 8-2a). For such a connection, the input voltage is called the com m on-m ode in
p u t voltage, E Cm > Now VQ w ill be 0 if the resistor ratios are equal (m R to R for the in
verting am plifier gain equals m R to R o f the voltage-divider netw ork). Practically, the re
sistor ratios are equalized by installing a p o ten tio m eter in series w ith one resistor, as
show n in Fig. 8-2a. T he potentiom eter is trim m ed until V0 is reduced to a negligible value.
This causes the com m on-m ode voltage gain, Vn/E CMi to approach 0. It is this ch aracter
istic o f a differential am plifier that allow s a sm all signal voltage to be picked out o f a
mR = 100 k£2
------------V W -------------
+v
(a)
+ 10V
*4
(b)
FIG U RE 8-2 (a) The common-mode voltage gain should be zero, (b) Basic
differential amplifier connected to a Wheatstone bridge.
220 Chapter 8
larger noise voltage. It may be possible to arrange the circuit so that the larger undesired
signal is the com m on-m ode input voltage and the sm all signal is the differential input
voltage. T hen the differential am plifier’s output voltage will contain only an am plified
version o f the differential input voltage.
O perational am plifier circuits, as w ell as op am ps, have com m on m ode error, and
the com m on m ode voltage is different for the circuit and the op am p. In this section, we
will introduce com m on m ode voltage and com m on m ode rejection for a basic differential
am plifier circuit, w hich is the fundam ental building block for the instrum entation am pli
fier. In C hapter 10, com m on m ode rejection is revisited, but for the op am p only.
R efer to the basic differential am plifier circuit in Fig. 8-2(b). T he difference v o lt
age, £ , - E2, may be defined as input difference signal voltage, Eds, and the average o f
the tw o inputs, ( E l + E 2)/2 , is defined as the com m on m ode voltage, E cm. In this circuit,
the differential am plifier is being used to m easure the voltage difference betw een the two
output nodes o f a W heatstone bridge.
E x a m p le 8-2
For the circuit o f Fig. 8-2(b), the bridge is slightly unbalanced and the input voltages with
respect to ground are £ , = 5 V 4- 2 mV and E2 = 5 V — 2 mV. D eterm ine (a) the input
signal voltage and (b) the com m on m ode voltage.
S o lu tio n (a) T he difference input signal voltage is
£ ds = E x - E 2 = (5 V + 2 m V) - (5 V - 2 mV) = 4 mV
(b) T he com m on m ode voltage is
_ E l + E2 (5 V + 2 mV) + (5V - 2 mV) _

Cm 2 2
Ideally, the circuit design is to reject the com m on m ode voltage and am plify the input
signal voltage.
8-1.3 Common M ode Rejection
Introduction
C ircuits or op am ps are com pared to one another by their com m on-m ode rejection (CM R )
or com m on m ode rejection ratio (CM R R). C M R is a m easure o f the change in output
voltage w hen both inputs are changed by an equal am ount. CMR_R is a ratio expression,
w hile com m on-m ode rejection is a logarithm o f that ratio. For exam ple, if C M R R is
10,000, the C M R is calculated by
C M R = 20 log jo CM R R ( 8- 2 )
For this exam ple,

CM R - 20 lo g ,o (10,000) = 80 dB
CMR of a Differential Amplifier Circuit

R eferring to the circuit in Fig. 8-2(b) and using the superposition principle discussed in
Section 8-1, the general equation for output voltage is
R? 7?3 + R4
Vn = E> (8-3)
Ri + R 2
For this circuit to w ork properly all resistors have to be carefully ratio-m atched to
m aintain excellent com m on-m ode rejection. For exam ple, if all the resistors are equal,
then the output voltage is the difference o f the input signals, V0 = E\ ~ E 2>and if the in
put voltages are equal, then VQ is 0. T his results in an infinite com m on-m ode rejection.
How ever, let's consider the situation w here one resistor is m ism atched and the circu it val
ues are E y — E 2 — E and R x = R 3 — R4 = R. T he m ism atched resisto r is R 2 w here R 2 =
R + 0A % R . A pplying Eq. (8.3) yields
1.0017?\ / 2R
Vn = X E = 0.0005 X E
2.001 R ) \ R
A lthough this expression shows the input voltage is reduced by 2000 (1/0.0005),
the com m on-m ode rejection o f the circuit has been degraded to
CM R = 20 log jo (2000) = 66 dB
In this application, we have discussed only the com m on-m ode rejection o f the cir
cuit and considered the op am p to be ideal. A disadvantage w ith the basic differential am
plifier circuit in Fig. 8.2(b) is that a slight m ism atch o f the resistors causes a degradation
of the CM R. In this exam ple, the m ism atch was R2, but a m ore com m on m ism atch is the
input resistors R\ or R 3 because o f loading effect(s). A solution to this problem will be
covered in Section 8-3.
8-2 DIFFERENTIAL V ER SU S SINGLE-INPUT AM PLIFIERS
8-2.1 Measurem ent with a Single-Input Amplifier
A sim plified w iring diagram o f an inverting am plifier is show n in Fig. 8-3. T he pow er
com m on term inal is show n connected to earth ground. Earth ground com es from a co n
nection to a w ater pipe on the street side o f the w ater meter. G round is extended via co n
duit or a bare Rom ex w ire to the third (green) w ire o f the instrum ent line cord and finally
to the chassis o f the am plifier. T his equipm ent or chassis ground is m ade to ensure the
Am plifier
ground ground
FIGURE 8-3 Noise voltages act as if they are in series with the input signal
Consequently, both are amplified equally. This arrangement is unworkable
if En is equal or greater than £,.
safety o f hum an operators. It also helps to drain off static charges or any capacitive co u
pled noise currents to earth.
T he signal source is also show n in Fig. 8-3 to be connected to earth ground. Even
if it w ere not grounded, there would be a leakage resistance or capacitance coupling to
earth, to com plete a ground loop.
Inevitably, noise currents and noise voltages abound from a variety o f sources that
are often not easily identifiable. T he net effect o f all this noise is m odeled by noise volt
age source En in Fig. 8-3. U sing the pow er supply com m on as the reference, it is evident
that E n is in series with signal voltage E h so that both are am plified by a factor o f - 1 0 0
due to the inverting am plifier. En may be m uch larger than For exam ple, the skin sig
nal voltage due to heart beats is less than 1 mV, w hereas the bod y ’s noise voltage m ay be
tenths o f volts or m ore; it w ould be im possible to m ake an EK G m easu rem en t w ith a sin
gle-input am plifier. W hat is needed is an am plifier that can distinguish betw een Et and E n
and am plify only E h Such a circuit is the differential am plifier.
8-2.2 Measurem ent with a Differential Amplifier
A differential am plifier is used to measure only the signal voltage (see Fig. 8-4). The signal
voltage Ej is connected across the ( + ) and ( —) inputs of the differential amplifier. Therefore,
Ei is am plified by a gain o f —100. Noise voltage En becom es the com m on-m ode voltage in
put voltage to the differential am plifier as shown in Fig. 8-2. (Note: Apply superposition.)
Therefore, the noise voltage is not am plified and has been effectively elim inated from hav
ing any significant effect on the output Vot as long as the resistors are matched as shown.
Differential, Instrum entation, and Bridge A m p lifiers 223
A m plifier
Third line
' cord wire
En noise voltage becom es the

Earth com m on-m ode voltage of the
g ro u n d diff. amp and is not am plified
FIGURE 8-4 The differential amplifier is connected so that noise voltage be
comes the common-mode voltage and is not amplified. Only the signal voltage
Ej is amplified because it has been connected as the differential input voltage.
8-3 IMPROVING THE BASIC DIFFERENTIAL AMPLIFIER
8-3.1 Increasing Input Resistance
T here are tw o disadvantages to the basic differential am plifier studied thus far: It has low
input resistance, and changing gain is difficult because the resistor ratios m ust be closely
m atched. T he first disadvantage is elim inated by buffering or isolating the inputs with volt
age followers. This is accom plished w ith two op am ps connected as voltage follow ers in
Fig. 8-5(a). The output o f op am p A, with respect to ground is E u and the output o f op
am p A 2 w ith respect to ground is E2. The differential output voltage V0 is developed across
the load resistor R L. V0 equals the difference between E\ and E 2 (V0 = E x — E 2). N ote that
the output o f the basic differential am plifier of Fig. 8-1 is a single-ended output; that is,
one side o f R L is connected to ground, and V0 is m easured from the output pin o f the op
am p to ground. The buffered differentia] am plifier o f Fig. 8-5(a) is a differential output;
that is, neither side of R L is connected to ground, and V0 is m easured only across R L.
8-3.2 Adjustable Gain
T he second disadvantage o f the basic differential am plifier is the lack o f adjustable gain.
T his problem is elim inated by adding three m ore resistors to the buffered am plifier. T he
resulting buffered, differential-input to differential-output am plifier w ith adjustable gain
is show n in Fig. 8-5(b). T he high input resistance is preserved by the voltage follow ers.
(a) B u ffered d iffer en tia l-in p u t to d iffe r e n tia l-o u tp u l a m p lifier.
+V
FIG U RE 8-5 Improving the basic differentia] amplifier.

226 Chapter 8
8-4 INSTRUMENTATION AMPLIFIER _______________________________________________________
T he instrum entation am plifier (IA ) is one o f the m ost useful, precise, and versatile am
plifiers available today. Youwill find at least one in every data acquisition unit. The b a
sic IA is m ade from three op am ps and seven resistors, as show n in Fig. 8-6. To sim plify
circuit analysis, note that the instrum entation am plifier is actually m ade by connecting a
buffered am plifier [Fig. 8-5(b)] to a basic differential am plifier (Fig. 8-1). O p am p A 3 and
its four equal resistors, R, form a differential am plifier w ith a gain o f 1. O nly the A 3 re
sistors have to be m atched. T he prim ed resistor, R \ can be m ade variable to balance out
any com m on-m ode voltage, as show n in Fig. 8-2. O nly one resistor, aR, is used to set the
gain according to Eq. (8-6), repeated here for convenience:
V 2
^ — = 1+ - (8-6)
E ]- E2 a
w here a = aR /R .
£ ] is applied to the ( + ) input and E2 to the ( —) input. V0 is proportional to the dif
ference betw een input voltages. C haracteristics o f the instrum entation am plifier are su m
m arized as follow s:
FIGURE 8-6 Basic instrumentation amplifier model.

1. T he voltage gain, from differential input ( E x — E2) to single-ended output, is set by

one resistor.
2. T he input resistance o f both inputs is very high and does not change as the gain is
varied.
3. VD does not depend on the voltage com m on to both E x and E 2 (com m on-m ode volt
age), only on their difference.
E x a m p le 8-3
In Fig. 8-6, R = 25 k f l and aR = 50 ( 1 C alculate the voltage gain.
S o lu tio n From Eq. (8-6),
aR 50 1
= a
R 25,000 500
1+ - = 1+ = 1 + (2 X 500) = 1001
£, ~ E 7 a 1/500
E x a m p le 8-4
If aR is rem oved in Fig. 8-6 so that aR = w hat is the voltage gain?
S o lu tio n a = «>, so
1/ 2
= 1+ — = 1
e {- e2
E x a m p le 8-5
In Fig. 8-6, the follow ing voltages are applied to the inputs. E ach voltage polarity is given
w ith respect to ground. A ssum ing the gain o f 1001 from E xam ple 8-3, find V0 fo r (a)
E } = 5.001 V and E 2 = 5.002 V; (b) £ , = 5.001 V and E 2 = 5.000 V; (c) E x = - 1 .0 0 1 V,
E 2 = - 1 .0 0 2 V.
S o lu tio n (a)
V0 = 1001(£, - E 2) = 1001(5.001 - 5.002) V
- lO O l(-O .O O l) V = —1.001 V
(b) V0 = 1001(5.001 - 5.000) V = 1001(0.001) V = 1.001 V

(c) VQ = 1001[—1.001 - ( -1 .0 0 2 ) ] V = 1001(0.001) V = 1.001 V
An offset voltage or reference voltage Kref is inserted in series w ith reference ter
m inal R. Vref is divided by 2 and applied to the A3 op am p ’s ( + ) input. T hen the nonin
verting am plifier gives a gain o f 2 so that V0 equals Vref. N ow V0 can be set to any d e
sired offset value by adjusting Vref. In practice Vref is the output o f a voltage-follow er
circuit as show n in Fig. 8-7(b).
8-5 SEN SIN G AND M EASURIN G WITH THE

INSTRUMENTATION AMPLIFIER ______________________________________________
8-5.1 Sen se Terminal
T he versatility and perform ance o f the instrum entation am plifier in Fig. 8-6 can be im
proved by breaking the negative feedback loop around op am p A3 and bringing out three
term inals. As show n in Fig. 8-8, these term inals are output term inal 0, sense term inal Sf
and reference term inal R. If long w ires or a current-boost transistor are required betw een
the instrum entation am plifier and load, there will be voltage drops across the connecting
w ires. To elim inate these voltage drops, the sense term inal and reference term inal are
w ired directly to the load. Now, w ire resistance is added equally to resistors in series w ith
the sense and reference term inals to m inim ize any m ism atch. Even m ore im portant, by
sensing voltage at the load term inals and not at the am p lifier’s output term inal, feedback
acts to hold load voltage constant. If only the basic differential am plifier is used, the out-
+v
A
R Sense
R
AAA---- o
2
Connecting wire
resistance
FIGURE 8-8 Extending the sense and reference terminals to the load termi
nals makes Va depend on the amplifier gain and the input voltages, not on the
load current or load resistance.
49,400 \
G ain = 1 + (8-7)
Rc I
For gain values of 1, 10, 100, and 1000, a table listing the R G values is given in Fig. 8-9(b).
The usual w ay to m easure VCE o f a w orking com m on-em itter am plifier circuit is to
(1) m easure collector voltage (w ith respect to ground), (2) m easure em itter voltage (w ith
respect to ground), and (3) calculate the difference. The IA allow s you to m ake the m ea
surem ent in one step, as show n in Fig. 8-9(b). Since £ , = Vcolleclor and E 2 = Vemi(ter,
= ( ! ) ( £ , - E2) = (l)(V collect0r - êmitter) = (8-8)
Example 8-6
G iven V0 = 5 V in Fig. 8-9(b), find VC£.
Solution From Eq. (8-8),
5 V = (£ , - E 2) =
Example 8-7
E xtend E xam ple 8-6 as follows. C onnect + In to the em itter and - In to ground, assum e
V0 m easures 1.2 V, and calculate (a) em itter current Z£ ; (b) the voltage across R L or VRL.
Solution (a) Since V0 — 1.2 V, E { — E 2 = 1.2 V, and therefore VRE — 1.2 V. U se O h m ’s

law to find IE.
/£ = ^ = i ^ = 1.2 mA
Re i kn
(b)
V,c o l l e c t o r = V « + V „ = 5 V + 1 .2 V = 6 .2 V
Vrl = Vrr - V,c o l l e c t o r = 15 V - 6.2 V = 8.8 V
C C v
Part (a) o f this exam ple show s how to m easure current in a w orking circuit by m easuring
the voltage drop across a know n resistor.
8-5.3 Differential Voltage-to-Current Converter
T he A D 620 instrum entation am plifier does not have a sense term inal. T herefore, if your
application requires this term inal, choose another IA such as the A D 524 or A D 624. Figure
8-10 show s how to m ake an excellent current source that can sink or source dc current
into a grounded load. It can also be an ac current source.
232 Chapter 8
+ 15 V -1 5 V
FIGURE 8-10 A differential voltage-to-current converter is made from an IA,

op amp, and resistor.
To understand how this circuit operates, one m ust understand that the IA’s output
voltage at pin 9 depends on load current, / L, load resistor, R Ly and current set resistor, R s.
In equation form
Vg = I^R S + I lJRl (8-9a)
T he output voltage o f an IA can also be expressed generally by
V9 = K ef + g a ln (£ | - E 2) (8-9b)
T he A D 547 voltage follow er forces the reference voltage to equal load voltage or VrCf =
I l R l . Since the IA’s gain is set for 10 in Fig. 8-10, we can rew rite Eq. (8-9b) as
V9 = l LR L + 10(£, - E 2) (8-9c)
E quate Eqs. (8-9a) and (8-9c) to solve for 1L, w hich yields
E quation (8-9d) indicates that load resistor, R L , does not control load current; this
is true as long as neither am plifier is forced to saturation. 1L is controlled by R , and the
difference betw een £ , and E 2.
Example 8-8
In the circuit o f Fig. 8-10, Rs = 1 kH , E\ = 100 mV, E 2 = 0 V, and R L = 5 kCl. Find (a)
(b) VR - (c) Vref; (d) V9.
Solution (a) F rom Eq. (8-9d),
4 = 10
IlRs = (1 m A )(l
(b) VRr = k ft) = 1 V
(c)vj= IlRl (1 m A )(5
= k ft) = 5 V
(d) From Eq. (8-9a) or (8-9c),
V9 = I l R s + I l R l = 1 V + 5 V = 6 V
or
Vg = Vref 4- g a in (£ 1 - E2) = 5 V + 10(0.1 V) = 6 V
8-6 THE INSTRUMENTATION AMPLIFIER A S A SIGNAL

CONDITIONING CIRCUIT _____________________________
In C hapter 3, we m entioned that som e sensor circuits are designed with a differential o u t
put. However, the input voltage to a m icrocontroller is w ith respect to ground and hence
is single ended. T herefore we need a signal conditioning circuit (SC C) that has a differ
ential input and a single-ended output— the instrum entation am plifier. We begin by intro
ducing a sensor circuit with a differential output.
8-6.1 Introduction to the Strain Gage
A strain gage is a conducting w ire w hose resistance changes by a sm all am ount w hen it
is lengthened or shortened. T he change in length is sm all, a few m illionths o f an inch.
T he strain gage is bonded to a structure so that the percent change in length o f the strain
gage and structure are identical.
A foil-type gage is show n in Fig. 8 -1 1(a). T he active length o f the gage lies along
the transverse axis. T he strain gage m ust be m ounted so that its transverse axis lies in the
sam e direction as the structure m otion that is to be m easured [see Figs. 8 -1 1(b) and (c)].
L engthening the bar by tension lengthens the strain gage conductor and increases its re
sistance. C om pression reduces the g ag e’s resistan ce b ecause the norm al length o f the
strain gage is reduced.
8-6.2 Strain-Gage Material
S train gages are m ade from m etal alloy such as co n stan tan , N ich ro m e V, D ynaloy,
Stabiloy, or platinum alloy. For high-tem perature w ork they are m ade o f wire. For m od
erate tem perature, strain gages are m ade by form ing the m etal alloy into very thin sheets
by a photoetching process. The resultant product is called a foil-type strain gage and a
typical exam ple is show n in Fig. 8 -1 1(a).
No. 30 insulated Lateral axis
instrument wire ^
I _______ A c tiv e __
length
(a) Metal foil-type strain gage.
Hi AD 1kor
(b) Tension lengthens bar and gage

to increase gage resistance by AR.
(c) Com pression shortens bar and gage

to reduce gage resistance by AR.
FIG U RE 8-11 Using a strain gage to measure the change in length of a

structure.
8-6.3 Using Strain-Gage Data
In the next section, we show that our instrum entation m easures only the g ag e’s change in
resistance AR. The m anufacturer specifies the unstrained g ag e’s resistance R. O nce AR has
been m easured, the ratio AR /R can be calculated. The m anufacturer also furnishes a spec
ified gage fa c to r (GF) for each gage. T he gage factor is the ratio o f the percent change in
resistance of a gage to its percent change in length. T hese percent changes m ay also be ex
pressed as decim als. If the ratio AR /R is divided by gage factor G, the result is the ratio o f
the change in length o f the gage AL to its original length L O f course the structure w here
the gage is m ounted has the sam e AL /L An exam ple will show how gage factor is used.
E x a m p le 8-9
A 1 2 0 strain gage w ith a gage factor o f 2 is affixed to a m etal bar. T he bar is stretched
and causes a A R o f 0.001 Cl. Find A L/L.
234
Solution
AL A R/R o.ooi a/120 a

L GF 2
— 4.1 m icroinches per inch
T he ratio AL/L has a nam e. It is cal led unit strain. It is the unit strain data (we have
developed from a m easurem ent o f AR) that m echanical engineers need. They can use this
unit strain data together w ith know n characteristics o f the structural m aterial (m odulus o f
elasticity) to find the stress on the beam. Stress is the am ount o f fo rc e acting on a unit
area. T he unit for stress is pounds per square inch (psi). If the bar in E xam ple 8-9 w ere
m ade of m ild steel, its stress w ould be about 125 psi. Strain is the deform ation o f a ma~
B efore m ounting a strain gage the surface o f the m ounting beam m ust be cleaned, sanded,
and rinsed w ith alcohol, Freon, or m ethyl ethyl ketone (M EK ). The gage is then fastened
perm anently to the cleaned surface by E astm an 910, epoxy, polym ide adhesive, or ce
ram ic cem ent. T he m anufacturer’s procedures should be follow ed carefully.
8-6.5 Strain-Gage Resistance Changes
It is the change o f resistance in a strain gage AR that m ust be m easured and this change
is small. AJ? has values of a few m illiohm s. T he technique em ployed to m easure small re-
8-7 M EA SU R EM EN T O F SM A LL RESISTA N CE CHANGES _____________________________
To m easure resistance, w e m ust first find a technique to convert the resistance change to
a current or voltage for display on an am m eter or voltm eter. If we m ust m easure a sm all
change of resistance, we will obtain a very sm all voltage change. For exam ple, if we
passed 5 m A of current through a 1 2 0 -0 strain gage, the voltage across the gage w ould
be 0.600 V. If the resistance changed by 1 m ft, the voltage change w ould be 5 fiV . To
display the 5-/llV change, w e w ould need to am plify it by a factor of, for exam ple, 1000
to 5 mV. H ow ever, we w ould also am plify the 0.6 V by 1000 to obtain 600 V plus 5 mV.
It is difficult to detect a 5-m V difference in a 600-V signal. T herefore, we need a circuit
that allow s us to am plify only the difference in voltage across the strain gage caused by
a change in resistance. T he solution is found in the W heatstone bridge circuit.
238 Chapter 8
8-8 BALANCING A STRAIN-GAGE BRIDGE
8-8.1 The Obvious Technique
S uppose that you had a w orking gage and tem perature-com pensation gage in Fig. 8-14
that are equal to w ithin 1 m ft. To com plete the bridge, you install two 1%, 1 2 0 -ft resis
tors. O ne is high by 1% at 121.200 f t and one is low by 1% at 118.800 ft. T hey m ust be
equalized to balance the bridge. To do so, a 5 -ft, 20-turn balancing pot is installed, as
show n in Fig. 8-14. Theoretically, the pot should be set as show n to equalize resistances
in the top branches of the bridge at 122.500 ft.
F urther assum e that an instrum entation am plifier w ith a gain o f 1000 is connected
to the bridge of Fig. 8-14. F rom E xam ple 8-10, the o u t p u t o f the instrum entation am pli
fier (IA ) w ill be about 22 mV per m illiohm o f unbalance. This m eans th at the 5 -fl pot
m ust be adjusted to w ithin 1 m ft o f the values show n, so that E x — E2 and consequently
VQ o f the IA will equal 0 V ± 22 mV.
U nfortunately, it is very difficult in practice to adjust for balance. T his is because each
turn o f the pot is worth 5 ft/2 0 turns = 250 m ft. W hen you adjust the pot it is normal to
expect a backlash o f o f a turn. Therefore, your best efforts result in an unbalance at the
pot o f about ± 5 m ft. You observe this unbalance at the IA’s output, w here V0 changes by
± 0.1 V on either side of zero as you fine-tune the 20-tum pot. It turns out there is a better
technique that uses an ordinary linear potentiom eter ( | turn) and a single resistor.
£=10 V
Set for Set for
3.700 Cl ^ y 1.300 a
R2 - *3 =
118.800 Cl 121.200 Cl
£j to differential amp (+) in
120.000 Cl J 20.000 Cl
tem perature w orking gage
com pensation
gage
FIGURE 8-14 Balance pot RB is adjusted in an attempt to make £, - E2 — 0 V.
8-8.2 The Better Technique
To analyze operation of the balance netw ork in Fig. 8-15, assum e that the R 2 and R 3
bridge resistors are reasonably equal, to w ithin ± I %. The strain g ag e’s resistance should
have equal resistances w ithin several m illiohm s if the w orking gage is not under strain.
E= 10 V
Balance
I
network
f= 1.0$
RB] = 10 kQ. pot

-<— w \
^ 2= 1
to 1000
f= 06
working gage
R + AR
v
FIGURE 8-15 Improved balance network. <RBi and RB, allow easy adjustment
of V0 to 0 V.
R esistor R B i is an ordinary 3/4-turn linear pot. Its resistance should be about 1/10
or less than resistor R Bl so that the voltage f E depends only on E and the decim al frac
t i o n / Values o f / v a r y from 0 to 1.0 as the pot is adjusted from one lim it to the other. R B]
should be 10 or m ore tim es the gage resistance.
Resistor R Bl is chosen to be greater than 10 or more times R B]. U nder these conditions
RB2 does not load down the voltage-divider action of RB]. Also, the size o f R B2 determ ines
the m axim um balancing current that can be injected into, or extracted from, the E2 node. The
pot setting /d e te rm in e s how much of that m axim um current is injected or extracted.
B alancing action is sum m arized by observing that i f / > 0.5, a sm all current is in
jected into the E 2 node and flows through the tem perature gage to ground, this m akes E 2
m ore positive. If / < 0.5 current is extracted from the E 2 node, this increases current
through R 2 to m ake E 2 less positive.
In a real bridge setup, begin with R Bl = 100 k fl and R B] = 10 k fl. M onitor VQ o f
the IA and check the balancing action. If the variation in VQ is larger than you w ant, in
crease R Bl to 1000 k f l and recheck the balance action. T he final value o f RB7 is selected
by experim ent and depends on the m agnitude o f unbalance betw een R2 and R 3.
8-9 INCREASING STRAIN-GAGE BRIDGE OUTPUT _____________________________________
A single w orking gage and a tem perature-com pensation gage w ere show n to give a d if
ferential bridge output in Fig. 8-12 o f
( 8 - 11)
This bridge circuit and placem ent o f the gages is show n again in Fig. 8 - 16(a).
T he bridge output voltage E x — E2 can be doubled by doubling the num ber o f w ork
ing gages, as in Fig. 8-16(b). G ages 1-2 and 5 -6 are the w orking gages and w ill increase
resistance (tension) if force is applied as shown. By arranging the w orking gages in oppo
site arm s of the bridge and the tem perature gages in the other arm s, the bridge output is
AR AR
£, - E? = E - E ( 8 - 12 )
2 R + AR 2R
If the structural m em ber experiences bending as show n in Fig. 8 - 16(c), even greater
bridge sensitivity can be obtained. T he upper side o f the bar will lengthen (tension) to in
crease the resistance of the w orking strain gages by + A R. The low er side o f the bar will
shorten (com pression) to decrease the w orking strain gages by —A/?.
T he te n sio n gages 1 -2 and 5 - 6 are co n n ected in o p p o site arm s o f the bridge.
C om pression gages 3 - 4 and 7 -8 are connected in the rem aining opposite arm s o f the
bridge. T he gages also tem perature-com pensate one another. T he output o f the four-strain-
gage arrangem ent in Fig. 8 -16(c) is quadrupled over the single-gage bridge to
AR
E| ~Ey = E (8-13)
R
O f course, each bridge arrangem ent in Fig. 8-16 should be connected to a balance
netw ork (w hich, for clarity, was not show n) (see Fig. 8-15 and Section 8-8). N ote that the
output o f the four-gage bridge is linear.
8-10 A PRACTICAL STRAIN-GAGE APPLICATION
As show n in Fig. 8-17, an A D 620 (A nalog D evices) instrum entation am plifier (IA ) is co n
nected to a bridge arrangem ent of four strain gages. T he gages are 1 2 0 -0 , SR4, foil-type
strain gages. T hey are m ounted on a steel bar in accordance w ith Fig. 8 -16(c). A lso the
balance netw ork o f Fig. 8-15 is connected to the strain-gage bridge. R&2 w as selected, af
ter experim ent, as 100 k fl. Strain gages w ere m ounted in strict accordance w ith the m an
u facturer’s instructions (BLH Electronics, Inc.). From the table in Fig. 8-9(b) R c is se
lected for a gain o f 1000.
E x a m p le 8-11
T he SCC o f Fig. 8-17 is used to m easure the strain resulting from deflection o f a steel
bar. V0 is m easured to be 100 mV. C alculate (a) AR \ (b) AR /R \ (c) AL/L. The gain is
1000. The gage factor is 2.0.
S o lu tio n (a) Find E x — E 2 from
100 mV
Et -Eo = = 0.1 mV
1000
8-11 M EA SU R EM EN T OF P R ESSU R E, FORCE, AND WEIGHT ________________________
E xam ple 8 - l l illustrated how pressure could be m easured by a strain-gage system . T he

m echanical engineers can be given AL!L by electrical personnel, w ho can m easure AR /R
and look up the gage factor. F rom the value o f AL/L, the m echanical engineers and tech
nicians can calculate pressure on a structure. Since pressure is force per unit area, they
can calculate force by m easuring the stru ctu re’s area.
Furtherm ore, the w eight of an object exerts a force on any supporting structure. By
installing a strain gage on the supporting structure, you can w eigh very heavy objects such
as a gravel-filled truck or a 747 aircraft.
8-12 BASIC BRIDGE AMPLIFIER ____________________________________________________________
8-12.1 Introduction
Som e transducers can be connected into a low er-parts-count signal conditioning circuit
called a bridge am plifier. A n op am p, four resistors, and a tran sd u cer form the basic
bridge am plifier in Fig. 8-1 8(b). The transducer in this case is any device that converts
an environm ental change to a resistance change. For exam ple, a therm istor is a tran s
ducer w hose resistance decreases as tem perature increases. A p h o to co n d u ctive cell is a
transducer w hose resistance decreases as light intensity increases. For circuit analysis,
the transducer is represented by a resistor R plus a change in resistance AR. R is the re
sistance value at the desired reference, and AR is the am ount of change in R. For ex am
ple, a UUA 41J1 therm istor has a resistance of 10,000 f l at a reference o f 25°C . A tem
perature change o f +1 ° to 26°C results in a therm istor resistance o f 9573 f l. AR is found
to be negative from
^ tra n sd u c e r ^ re fe re n c e
9573 n = 10,000 n + AR
AR = -4 2 1 n
Since we have defined 25°C to be the reference tem perature, w e define the reference re
sistance to be R vef — 10,000-ft. O ur definitions force AR to have a negative sign if the
transducer’s resistance is less than R ref.
To operate the bridge, we need a stable bridge voltage E y w hich may be either ac
' or dc. E should have an internal resistance that is sm all with respect to R. T he sim plest
way to generate E is to use a voltage divider across the stable supply voltages as show n
in Fig. 8-18(a). Then connect a sim ple voltage follow er to the divider. For the resistor val
ues shown, E can be adjusted between + 1 0 and —10 V.
V. - ~ E = - / AR (8-14)
w here / = E /(R ref + R), A/? = fitrans - Krcf.
Zeroing procedure
1. Place the transducer in the reference environm ent: for exam ple, 25°C.
2. A djust R ref until V0 = 0 V.
N orm ally, it is too costly to control an environm ent fo r test or calibration o f a single cir
cuit. Therefore, (1) replace the transducer, R trans, w ith a resistor equal to R ref; (2) now, AR
equals zero; (3) from Eq. (8-14), V0 should also be equal to zero.
S uppose that V0 is close to, but not equal to, zero. You w ant to adjust VQto pre
cisely zero volts.
1. C heck that the R \ resistors are equal to w ithin 1%.

2. Check that the replacem ent transducer jRref equals the value o f /?ref[from ( + ) input
to ground in Fig. 8 -18(b)] w ithin 1%.
3. U se an op am p with a low dc offset such as the O P -177.
8-12.3 Temperature Measurem ent with a Bridge Circuit
In this section we show how to design a low -parts-count tem perature-m easuring system
to illustrate a design procedure.
Design Example 8-12
D esign a tem perature-to-voltage converter that w ill m easure tem peratures betw een 25°
and 50°C.
Design Procedure
1. Select any therm istor on a trial basis. T he therm istor converts a tem perature change to
a resistance change. Select the F enw al U U A 41J1 and list its corresponding tem p era
ture versus resistance as in Table 8-1. (N ote the nonlinearity betw een tem perature and
resistance.)
2. Select the reference tem perature. A t the reference tem perature, V0 m ust equal zero.
S elect either the low lim it of 25°C or the high lim it o f 50°C. We shall select the low
lim it o f 25°C for this exam ple. We have ju s t defined R ref. R Tet- is equal to the tran s
d u ce r’s resistance at the reference tem perature. Specifically, 7 ref = 25°C ; therefore,
ftref = 10,000 H . Now calculate AR for each tem perature from
Mrans iVrer
At 50°C,
3603 f t = 10,000 f t + ar
AR = - 6 3 9 7 ft
N ote the negative sign for AR.
TABLE 8-1 Resistance versus Temperature of a UUA41J1 Thermistor
Temp. (°C) * ,r
25 10,000 1983
30 8,057 Ohmic change for 5°C change
35 6,530
nonlinear
5,327
/
40
45 4,370
767
50 3,603 Ohm ic change for 5°C change
3. P redict the voltage-tem perature characteristics. We shall select the bridge circuit o f
Fig. 8-18 because it converts a resistance change AR into an output voltage [see Eq.
(8-14)].
a. S elect resistors R\ to equal 10 k ft, 1%.
b. M ake a trial choice for E = 1.0 V.
If you are w ondering w hy we should m ake these particular choices, the answ er is
that (1) 10-k ft resistor sizes are readily available, and (2) a 1-V selection w ill give us
an idea o f the size of V0. If later you w ant to double or triple Voy sim ply double or
triple E.
c. C alculate / from Eq. (8-14).
1V
I = = 0.050 mA
io kft + 10 kn
d. C alculate VQ for each value of R and tabulate the results (see Table 8-2). From Eq.
(8-14),
= - / AR
For 50°C,
VQ = - ( 0 .0 5 0 mA)( —6397 ft) = 310 mV
4. D ocum ent p erfo rm a n ce. VQ is plotted against tem perature in Fig. 8-19, w here the d e
sign circuit is also draw n.
248 Chapter 8
Summary review and comments. E xam ple 8-12 show s how a bridge circuit
converts the resistance change of a transducer into a voltage change. The circuit output
voltage is linear w ith respect to AR [see Eq. (8-14)]. However, AR is not linear with re
spect to tem perature (see Table 8-1 and Fig. 8-19). Therefore, Va is not linear with respect
to tem perature. The bridge sim ply transm its the nonlinearity o f the therm istor.
T he sensitivity of the tem perature-to-voltage converter can be increased easily by
increasing E. T he m axim um value of E is set by the m axim um therm istor current to avoid
self-heating, typically 1 mA. T herefore, E has a m axim um value of
E = /(/?ref + R }) = (1 m A )(iO + 10) k f l = 20 V
If we w ant to increase the 319-m V output span (E = 1 V) to a 5 .0-V span for the input
to a m icrocontroller, sim ply increase E by 15.67 to 15.67 V [(5.0 V /0.319 V = 15.67)].
8-12.4 Bridge Amplifiers and Computers
T h u s far, the b rid g e am p lifier show n co n v erts te m p eratu re ch a n g es to a v oltage. In

C hapter 2 you studied the principles of how a voltage change could be converted into a
change o f high tim e by a pulse-w idth m odulator. T hose principles can be used again to
com m unicate betw een the analog world o f continuous tem perature variation and the d ig
ital w orld of the com puter. T he bridge am plifier provides m easurem ent; the PW M pro
vides an interface. A nother m ethod is to have the output voltage o f Fig. 8-19 applied to
the A /D converter o f a m icrocontroller. N ote that the nonlinearity o f the therm istor can
be com pensated for by a softw are program know n as piecew ise linearization. (See D ata
A c q u isitio n a n d P rocess C ontrol w ith the H C 11 M icro c o n tro ller 2nd E dition by
F. D riscoll, R. C oughlin, and R. V illanucci, published by Prentice Hall.)
8-13 ADDING VERSATILITY TO THE BRIDGE AMPLIFIER ______________________________
8-13.1 Grounded Transducers
In som e applications it is necessary to have one term inal o f the transducer connected to
ground. T he standard technique is show n in Fig. 8-20(a). N ote that current I depends on
transducer resistance (in Figs. 8 - 18 and 8-19, the current w as constant). N ote also that V0
is not linear with AR because AR appears in the denom inator o f the equation for V0 ver
sus AR. Finally, in contrast w ith D esign E xam ple 8-10, if £ , is positive and 7 ref is at the
low end o f the scale, V0 goes negative for negative values o f AR. T hat is, if /?lrans is a ther
m istor, V0 goes m ore negative as tem perature increases.
8-13.2 High-Current Transducers
If the current required by the transducer is higher than the current capability o f the op
am p (5 m A ), use the circuit o f Fig. 8-20(b). T ran sd u cer cu rren t is fu rn ish ed from E.
Resistors m R are chosen to hold their currents to about 1 to 4 mA. T ransducer current and
output voltage may be found from the equation in Fig. 8-20(b). If the transducer current
250 Chapter 8
8-4. For the differential amplifier circuit of Fig. 8-2(b), all the resistors are equal to 10 kfl except
R2, which is mismatched by 5 H (R2 = 10 kCl + 5 Cl). What is the common mode rejection
of the circuit?
8-5. Design the differential amplifier circuit of Fig. 8-2(b) for a gain of 4. The input resistors R ,
and R3 are equal to 25 kfl.
8 - 6 . A circuit has a common-mode rejection ratio of 100,000. What is the common-mode rejec
tion?
8-7. A circuit has a CMR of 75 dB. What is the common-mode rejection ratio?
8 - 8 . In Fig. 8-3, E, — 2 mV and En = 50 mV. What is the output voltage due to (a) (b)£„?
8-9. In Fig. 8-4, Ej = 2 mV and En - 50 mV. What is the output voltage due to (a) £,■; (b)Enl
8 - 10. What is the main advantage of a differential amplifier over an inverting amplifier with re
spect to an input noise signal voltage?
8 - 11. Find VQ in Fig. 8-5(b) if £, = - 5 V and E2 = - 3 V.
8 - 12, In Fig. 8-5(b), R = 10 kH and aR = 2 kH. If Ex = 1.5 V and E2 = 0.5 V, find V0.
8-13. In Fig. 8-6 the overall gain is 21 and VQ = 3 V. Determine (a) E x — E2, (b) a.
8-14. In Fig. 8-6, R = 25 kCly aR = 100 Cty E {= 1.01 V, and £ 2 = 1.02 V. Find V0.
8-15. If Ker - 5.0 V in Fig. 8-7, find (a) V0\ (b) the voltage at the ( + ) input with respect to ground.
8-16. Refer to the circuit of Fig. P8-16. Complete the table below for each input condition.
£, (V) E2 (V) Ey (V) V at ( + ) input
(a) -2 -2 0
(b) -2 -2 2
(c) 2 -2 -2
(d) 2 0 2
10 k O
-A /W -
10 kQ
-AAAr-
10 k a
-AAyV-
S y
io k a ; -
10 kO •
FIGURE P8-16
8-17. Refer to the voltage-to-current converter of Fig. 8-10. Assume that the AD524 is wired for a
gain of 1 [no wires on pins 13 and 3]. The load current is now IL = (£| — E2)!RS. Let Rs =
1 kCl, E2 = 0 V or ground, and E\ = 1 V. (a) Will the direction of IL be up or down in Fig.
8-10? (b) Find IL. (c) Find the voltage across RL \ f RL = 100 fl. (d) Find the output voltage
of the IA (V9) if RL = 3 kCL.
8-18. Repeat Problem 8-17 except change E2 = ground and E , = 1 V. (Note that Section 8-5.3 tells
you how to make an ac voltage-controlled current source for a grounded load.)
8-19. Change E\ to —1 V in Problem 8-17. (a) Would V0 be positive or negative withrespect to
ground? (b) Would V0 decrease or increase in magnitude as temperature increased?
8-20. In Fig. 8-16, the value for/? = 120.00 H, AR = 1.2 raO, and E = 10.0 V. Find (£, - E2) for
the strain-gage arrangement of (a) Fig. 8-16(a); (b) Fig. 8- 16(b); (c) Fig. 8-16(c).
8-21. Assume that an IA with a gain of 1000 is wired to the bridges of Problem 8-20. Find V0 for
each of the three bridge arrangements.
8-22. Consider a gage factor of 2 in Problems 8-20 and 8-21 and calculate AL/L for each bridge
arrangement.
8-23. Refer to Section 8-12.3. To gain experience with this type of bridge circuit, repeat Design
Example 8-13 (except change only your reference temperature to 50°C. R\ remains at 10 kfi
and E — 1 V). Present your solution in the same format as shown in Table 8-2 and Fig. 8-19.
Redraw the new design schematic like that of Fig. 8-19. [Remember that Rmf will now be
3603 ft so that / = 1 V /(l0,000 + 3603) f t = 73.51 //A.]
8-24. You want a circuit that has an increasing magnitude of output voltage as temperature of a
thermistor increases. You put the thermistor in the feedback loop [see Fig. 8-18(b)]. Would
you choose Rret- at the low or the high end of the temperature scale? (Hint: Compare VQ vs.
VT of Design Example 8-13 with the solution of Problem 8-23.) This problem forces you to
face briefly the issue of “human engineering.” People want to see an increasing voltage as
temperature increases.
CHAPTER 9
DC Performance: Bias,
Offsets, and Drift
LEARNING OBJECTIVES ___________________________________________________
U pon com pletion of this chapter on dc perform ance, you will be able to:
e N am e the op amp characteristics that add dc error com ponents to the output voltage.
■ Show how an op am p requires a small bias current at both ( —) and ( + ) inputs to acti
vate its internal transistors.
° Give the definition for input offset voltage and show how it is m odeled in an op am p
circuit.
3 W rite the equation for input offset current in term s o f the bias currents.
• C alculate the effect o f input offset voltage on the output voltage o f eith er an inverting
or noninverting am plifier.
• C alculate the effects of bias currents on the output voltage o f an inverting or n o n in
verting am plifier.
• C alculate the value o f and install a com pensating resistor to m inim ize the errors in o u t
put voltage caused by bias currents.
252
DC Performance: Bias, Offsets, and Drift 253
• C onnect a nulling circuit to null out any errors due to bias currents and input offset
voltage.
• M easure offset voltage and bias currents.
• U nderstand the dc characteristics of present-day op am ps versus earlier versions.
• U nderstand the difference betw een C M R R o f an op am p and an op am p circuit.
• C alculate pow er supply rejection ratio.
9 0 INTRODUCTION ___________________________________________________________________________
The op am p is w idely used in am plifier circuits to am plify dc or ac signals or co m b in a

tions of them . In dc am plifier applications, certain electrical characteristics of the op am p
can cause large errors in the output voltage. T he ideal output voltage should be equal to
the product o f the dc input signal and the am p lifier’s closed-loop voltage gain. However,
the output voltage may have an added error com ponent. T his error is due to differences
betw een an ideal op am p and a real op amp. If the ideal value o f output voltage is large
w ith respect to the error com ponent, then w e can usually ignore the op am p ch aracteris
tic that causes it, but if the error com ponent is com parable to or even larger than the ideal
value, we m ust try to m inim ize the error. O p am p characteristics that add error co m p o
nents to the dc output voltage are
1. Input bias currents

2. Input offset current
3. Input offset voltage
4. D rift
W hen the op am p is used in an ac am p lifier, co u p lin g ca p ac ito rs e lim in a te dc

output-voltage error. T herefore, characteristics 1 to 4 are often u n im portant in ac ap p li
cations. However, there are new problem s for ac am plifiers:
5. Frequency response
6. Slew rate
Frequency response refers to how voltage gain varies as frequency changes. T he m ost
convenient way to display such data is by a plot o f voltage gain versus frequency. O p am p
m anufacturers give such a plot for open-loop gain versus frequency. A glance at the plot
quickly show s how m uch gain is obtainable at a particular frequency.
If the op am p has sufficient gain at a p articu la r frequency, th ere is still a p o ssi
bility o f an erro r being in troduced in V0. T his is b ecau se there is a fu n d am en tal lim it
im posed by the op am p (and certain circ u it cap acito rs) on h ow fa s t the o u tp u t voltage
can change. If the input signal “te lls” the op am p o u tp u t to ch an g e faster than it can,
d isto rtio n is intro d u ced in the o u tp u t voltage. T h e op am p ch aracteristic resp o n sib le
for this type o f erro r is its internal capacitan ce. T his type o f erro r is called siew -ra te
lim iting.
254 Chapter 9
Op am p characteristics and the circuit applications that each type o f error m ay af
fect are sum m arized in Table 9-1. The first four characteristics can lim it dc perform ance;
the last tw o can lim it ac perform ance.
O p am p characteristics that cause errors prim arily in dc perform ance are studied in
this chapter. T hose that cause errors in ac perform ance are studied in C hapter 10. We be
gin w ith input bias currents and w ays in w hich they cause errors in the dc output voltage
o f an op am p circuit.
T A B L E 9-1 OP AM P A pplications and C haracteristics That Affect Operation
Op amp application
Dc am plifier Ac amplifier
Op amp characteristic
that may affect Small Large Small Large
perform ance output output output output
1. Input bias current Yes Maybe No No

2. Offset current Yes Maybe No No
3. Input offset voltage Yes M aybe No No
4. D rift Yes No No No
5. Frequency response No No Yes Yes
6. Slew rate No Yes No Yes
In addition to these characteristics the user m ay need to consider com m on-m ode
and pow er supply rejection ratios. T hese values may be specified under static test but vary
dynam ically.
9-1 INPUT BIAS CURREN TS
T ransistors w ithin the op am p m ust be biased correctly before any signal voltage is ap
plied. B iasing correctly m eans that the transistor has the right value o f base and collector
current as w ell as collector-to-em itter voltage. Until now, we have considered that the in
put term inals of the op am p conduct no signal or bias current. T his is the ideal condition.
Practically, however, the input term inals do conduct a sm all value o f dc current to bias
the op am p s’ transistors (see A ppendix 1). A sim plified diagram o f the op am p is show n
in Fig. 9 - 1(a). To discuss the effect o f input bias currents, it is convenient to m odel them
as current sources in series w ith each input term inal, as show n in Fig. 9 - 1(b).
T he ( - ) input's bias current, /# _ , will usually not be c;;acUy equal to the ( + ) in
p u t’s bias current, l B+. M anufacturers specify an average b.put bias current IB> w hich is
found by adding the m agnitudes of / fl+ and IB- and dividing this sum by 2. In equation
form ,
Ib (9-1)
w here | IB+ | is the m agnitude o f IB+ and | /# _ | is the m agnitude o f IB- . T he range of
IB is from 1 /j l A or m ore for general-purpose op am ps to 1 pA or less for op am ps that
256 Chapter 9
Example 9-1
C onsider a 741 op am p that has IB+ = 0.4 /xA and IB- — 0.3 Find (a) the average
bias current JB\ (b) the offset current l os.
S o lu tio n (a) By Eq. (9-1),
r (0.4 + 0.3) MA aoc a

IB = ---------- o-----------= °*35
(b) By Eq. (9-2),
I os = (0.4 — 0.3) fi A = 0.1 /xA
A general-purpose op am p such as the O P -177 has typical values o f IB = 2.4 nA

and Ios = 0.5 nA. N ew er versions o f the 741 op am p have typical values low er than those
given in E xam ple 9-1.
9-3 E FFEC T O F BIAS CURREN TS ON OUTPUT VOLTAGE
9-3.1 Simplification
In this section it is assum ed that bias currents are the only op am p characteristic that will
cause an undesired com ponent in the output voltage. T he effects o f other op am p ch arac
teristics on VQ will be dealt w ith individually.
9-3.2 Effect of <-) Input Bias Current
O utput voltage should ideally equal 0 V in each circuit o f Fig. 9-2, because input voltage
E, is 0 V. T he fact that a voltage com po n en t w ill be m easured is due strictly to IB —
(A ssum e for sim plicity that Vio, input offset voltage, is zero. Vio is discussed in Section
9-5.) In Fig. 9-2(a), the bias current is furnished from the output term inal. Since negative
feedback forces the differential input voltage to 0 V, VQ m ust rise to supply the voltage
drop across Rf . Thus, the output voltage error due to / fl_ is found from V0 = Rf IB_. IB+
flow s through 0 f 2, so it causes no voltage error. Signal source E , m ust contain a dc path
to ground.
The circuit o f Fig. 9-2(b) has the sam e output-voltage error expression, V0 = Rf IB- .
No current flow s through R h because there is 0 V on each side o f T hus all o f IB_ flows
through Rf. [Recall that an ideal am plifier w ith negative feedback has 0 voltage betw een
the ( + ) and ( - ) inputs.]
260 Chapter 9
age drop across Rf of Rf IB— If R / = R g and h + = h - , their voltage drops will cancel
each other and V0 w ill equal 0 V w hen = 0 V. U nfortunately, l B+ is seldom equal to
/fl_. V0 w ill then be equal to R c tim es the difference betw een IB+ and IB - (IB+ — / s _ =
Ios). T herefore, by m aking Rf = R G, w e have reduced the error in VQ from R GI B+ in Fig.
9-3 to —R(jIos in Fig. 9-4(a). R ecall that Ios is typically 25% o f IB. If the value o f l os is
too large, an op am p w ith a sm aller value o f l os is needed.
9-4.2 Current Compensating Other Amplifiers
To m inim ize errors in V0 due to bias currents for either inverting or noninverting am pli
fiers, resistor R as show n in Fig. 9-4(b) m ust be added to the circuit. W ith no input sig
nal applied, V0 depends on Rf tim es Ios [w here Ios is given by Eq. (9-2)]. R esistor R is
called the current-com pensating resistor and is equal to the parallel com bination o f R t and
R f, or
R = R i \\Rf = (9-3)
Ri + Rf
Ri and R should include any signal generator resistance. By inserting resistor /?, the error
voltage in V0 will be reduced m ore than 25% , from Rf IB~ in Fig. 9-2(b) to - R f Ios in Fig.
9-4(b). In the event that l B_ = IB+ , then Ios = 0 and Va = 0.
9-4.3 Sum m ary of Bias-Current Compensation
A lw ays a d d a bias-current com pensating resistor R in series with the ( + ) input term inal
(except for FET input op am ps). T he value o f R should equal the parallel com bination o f
all resistance branches connected to the ( —) term inal. Any internal resistance in the sig
nal source should also be included in the calculations.
In circuits w here m ore than a single resistor is connected to the ( + ) input, bias-
current com pensation is accom plished by observing the following principle. The dc resis
tance seen from the ( + ) input to ground should equal the dc resistance seen fro m the ( —) in
p u t to ground. In applying this principle, signal sources are replaced by their internal dc re
sistance and the op amp output term inal is considered to be at ground potential.
E x a m p le 9-4
(a) In Fig. 9-4(b), Rf = 100 k f t and /?, = 10 k fl. Find R. (b) If Rf = 100 k l i and
Ri = 100 k ft, find R.

(100 k f tX lO k O )
100 k f l + 10 k f l = 9.1 k f l
262 Chapter 9
Vio is show n in series w ith the ( + ) input term inal o f the op am p. It m akes no difference
w hether Vio is m odeled in series w ith the ( —) input or the ( + ) input. B ut it is easier to
determ ine the polarity o f Vio if it is placed in series w ith the ( + ) input. For exam ple, if
the output term inal is positive (w ith respect to ground) in Fig. 9-5(b), Vio should be draw n
w ith its ( + ) battery term inal connected to the ideal op am p ’s ( + ) input.
9-5.2 Effect of Input Offset Voltage on Output Voltage
Fig. 9-6(a) shows that Vio and the large value o f the open-loop gain o f the op am p act to
drive V0 to negative saturation. C ontrast the polarity o f Vio in Figs. 9-5(b) and 9-6(a). If
you buy several op am ps and plug them into the test circuit o f Fig. 9-6(a), som e w ill drive
V0 to + V sal and the rem ainder w ill drive V() to —Vsat. T herefore, the m agnitude and p o
larity o f Vio varies from op am p to op am p. To learn how Vio affects am plifiers w ith neg
ative feedback, we study how to m easure Vio.
9-5.3 M easurem ent of Input Offset Voltage
F or sim plicity, the effects o f bias cu rren ts are n eglected in the fo llo w in g d iscu ssio n .
F igure 9-6(b) shows how to m easure Vio. It also show s how to predict the m agnitude o f
eiTor that Vio w ill cause in the output voltage. Since E L = 0 V, V0 should equal 0 V, but
Vio acts exactly as w ould a signal in series w ith the noninverting input. T herefore, Vio is
am plified exactly as any signal applied to the ( + ) input o f a noninverting am plifier (see
Section 3 -5 ). The error in V0 due to Vio is given by
(9-4)
T he output error voltage in Fig. 9-6(b) is given by Eq. (9-4) w hether the circuit is used
as an inverting or as a noninverting amplifier. That is, Et could be inserted in series with /?,
(inverting amplifier) for a gain of —(Rf/Ri) or in series with the ( + ) input (noninverting am
plifier) for a gain of 1 4- {Rf/Rt). A bias-current com pensating resistor (a resistor in series
with the ( + ) input) has no effect on this type o f error in the output voltage due to Vio.
Conclusion. To m easure Vi0, set up the circuit o f Fig. 9-6(b). T he cap acito r is
installed across Rf to m inim ize noise in V0. M easure V0, Rfj and R h C alculate Vio from
N ote that Rt is m ade sm all to m inim ize the effect o f input bias current.
E x a m p le 9-5
Vio is specified to be 1 m V for a 741-type op am p. Predict the value o f VG that w ould be

m easured in Fig. 9-6(b).
DC Perform ance: Bias, O ffsets, and Drift 265
For exam ple, in Fig. 9-7(a) signals £ , and E 2 are each larger than Vio but £ , is m u l
tiplied by - R j / R i = - 1 and develops a com ponent o f - 5 m V in V0. E2 is likew ise m u l
tiplied by - 1 and adds a —5-m V com ponent to Va. T hus the correct value o f V0 should
be —10 mV. Since E 3 is 0 its contribution to Va is 0 (see Section 3-2).
If we tem porarily let E x and E2 = 0 V in Fig. 9-7(a), the ( —) input sees three equal
resistors form ing parallel paths to ground. The single equivalent series resistance, R h is
show n in Fig. 9-7(b). For three equal 10-kH resistors in parallel, the equivalent resistance
Rj is found by 10 kO /3 = 3.33 k fi. Vio is am plified ju st as in Fig. 9-6(b) to give an output
error of + 1 0 mV. Therefore, the total output voltage in Fig. 9-7(a) is 0 instead o f - 1 0 mV.
Conclusions. In an adder circuit, the input offset voltage has a gain o f 1 p lu s

the n um ber o f inputs. T he m ore inputs, the greater the error com ponent in the output volt
age. Since the gain for the inputs is —1, the o ffset voltage gain alw ays exceeds the signal
voltage gain.
9-6.2 How Not to Eliminate the Effects of Offset Voltage
One m ight be tem pted to add an adder input such as E 3 in Fig. 9-7(a) to balance out the
effect of Vio. For exam ple, if E 3 is m ade equal to 10 mV, then £ 3, /?3, and Rf will add a
- 1 0 m V com ponent to VQ and balance out the + 1 0 mV due to Vio. There are two disad
vantages to this approach. First, such a small value o f E 3 w ould have to be obtained from
a resistor-divider netw ork betw een the pow er supply term inals o f + V and —V. The second
disadvantage is that any resistance added betw een the ( —) input and ground raises the noise
gain. This situation is treated in Sections 10-4.3 and 10-4.4. In Section 9-7 we show how
to m inim ize the output voltage errors caused by both bias currents and input offset voltage.
9-7 NULLING-OUT EFFEC T O F O FFSET VOLTAGE AND BIAS

CURREN TS ________________________________________________________________________________
9-7.7 Design or Analysis Sequence
To m inim ize dc error voltages in the output voltage, follow this sequence:
1. Select a b ias-current com pensating resistor in accordance w ith the principles set
forth in Section 9-4.3.
2 . Get a circuit for m inim izing effects o f the input offset voltage from the op am p m an
ufacturer’s data sheet. T his principle is treated in m ore detail in Section 9-7.2 and in
A ppendix 1.
3. Go through the output-voltage nulling procedure given in Section 9-7.3.
D ata sheets published by op am p m anufacturers usually show an offset nulling circuit. In

m ost o f your applications this circuit is not necessary because you can purchase an op
am p with an input offset voltage sm all enough to cause negligible effects. However, let
us study the operation o f these nulling circuits.
(a) O P -177 o ffset nulling circuit. (b) 741 offse t voltage adjustment (m inidip).
+V +V
(c) 301 or 748 offset voltage (d) 537 offset voltage adjustment,
adjustment (TO-99 case).
FIG U RE 9-8 Typical circuits to minimize errors in output voltage due to in
put offset voltage and offset current (see also Appendix 1).
9-7.2 Null Circuits for Offset Voltage
It is possible to im agine a fairly com plex resistor-divider netw ork that w ould inject a
sm all variable voltage into the ( + ) or ( - ) input term inal. T his w ould com pensate for the
effects o f both input offset voltage and offset current. However, the extra com ponents are
m ore costly and bulky than necessary. It is far better to go to the op am p m anufacturer
for guidance. The data sheet for your op am p will have a voltage offset n u ll circuit rec
om m ended by the m anufacturer. T he op am p will have null term inals brought out for co n
nection to the null circuit. E xperts have designed the null circuit to m inim ize offset errors
at the low est cost to the user (see A ppendix 1).
S om e typical output-voltage null circuits are show n in Fig. 9-8. In Fig. 9-8(a), one
variable resistor is connected betw een the + V supply and a trim term inal. For an expen-
DC Perform ance: Bias, Offsets, and Drift 267
sive op am p, the m anufacturer m ay furnish a m etal-film resistor selected especially for

that op am p. In Fig. 9-8(b), a 10-kfl pot is connected betw een term inals called offset null.
M ore com p licated null circuits are show n in Figs. 9-8 (c) and (d). N ote that only the
offset-voltage com pensating resistors are show n by the m anufacturer. T hey assum e that a
current-com pensating resistor will be installed in series w ith the ( + ) input.
9-7.3 Nulling Procedure for Output Voltage (If Necessary)
1. B uild the circuit. Include (a) the current-com pensating resistor (see Section 9-4.3)
and (b) the voltage offset null circuit (see Section 9-7.2).
2. R educe all generator signals to 0. If their output cannot be set to 0, replace them
w ith resistors equal to their internal resistance. T his step is unnecessary if their in
ternal resistance is negligible w ith respect to (m ore than about 1% o f ) any series re
sistor Ri connected to the generator.
3. C onnect the load to the output term inal.
4. Turn on the pow er and w ait a few m inutes for things to settle down.
5. Connect a dc voltm eter or an oscilloscope (dc coupled) across the load to m easure V0.
(The voltage sensitivity should be capable o f reading down to less than a few millivolts.)
6. Vary the offset voltage adjustm ent resistor until VG reads 0 V. N ote that output volt
age errors due to both input offset voltage and input offset current are now m inim ized.
7. Install the signal sources and do not touch the offset-voltage adjustm ent resistor again.
9-8 DRIFT _______________________________________________________________________________________
It has been show n in this chapter that dc error com ponents in V0 can be m inim ized by in
stalling a current-com pensating resistor in series w ith the ( + ) input and by trim m ing the
offset-voltage adjustm ent resistor. It m ust also be em phasized that the zeroing procedure
holds only at one tem perature and at one tim e.
The offset current and offset voltage change with tim e because o f aging o f com po
nents. The offsets w ill also be changed by tem perature changes in the op am p. In addition,
if the supply voltage changes, bias currents, and consequently the offset current, change. By
use o f a w ell-regulated pow er supply, the output changes that depend on supply voltage can
be elim inated. However, the offset changes w ith tem perature can only be m inim ized by ( I )
holding the tem perature surrounding the circuit constant, or (2) selecting op am ps w ith off
set current and offset voltage ratings that change very little w ith tem perature changes.
T he changes in offset current and offset voltage due to tem perature are described
by the term drift. D rift is specified for offset current in nA /°C (nanoam peres per degree
Celsius). For offset voltage, drift is specified in /xV/°C (m icrovolts per degree Celsius).
D rift rates m ay differ at different tem peratures and m ay even reverse; that is, at low tem
p eratu res Vio m ay d rift by + 2 0 fxV I°C (in crease), and at high te m p eratu re s Vio m ay
change by —10 /xV/°C (decrease). For this reason, m anufacturers m ay specify eith er an
average or m axim um drift betw een tw o tem perature lim its. Even b etter is to have a plot
o f drift vs. tem perature. An exam ple is show n to calculate the effects o f drift.
268
270 Chapter 9
2. To m easure l B set up the circuit o f Fig. 9 - 10(b). M easure Va. U sing the value o f
Vio found in step 1, calculate IB from
V —V
/it- = — Rf — ( 9 ' 7)
3. To m easure IB+, m easure Va in Fig. 9-10(c) and calculate IB < from
E x a m p le 9-7
T he circu its o f Fig. 9-10 are used w ith the resistan ce values show n for a 741 op am p.
R esults are Va = + 0 .4 2 1 V fo r Fig. 9-10(a), V0 = 0.097 V for Fig. 9- 10(b), and Va =
--0.082 V for Fig. 9 - 10(c). Find (a) Vio\ (b) /* _ ; (c) IB+.
S o lu tio n (a) F rom Eq. (9-6),
0.421 V
V-lO = j QJ = 4 1 JmV
111V
(b) F rom Eq. (9-7),
( 9 7 - 4 . 1 ) mV
h = ------ -------------- = 93 nA
I M fi
(c) From Eq. (9-8),
r ( - 8 2 - 4 .1 ) m V _ A
'»* = --------- T m S ------ = 86 nA
N ote that Ios is found to be IB+ - IR_ = - 7 nA.
9 ’ 10 C O M M O N -M O D E R E J E C T IO N R A T IO
C hapter 8 introduced com m on-m ode rejection ratio (C M R R ) as it applied to an op am p

subtractor circuit (also referred to as the basic differential am plifier circuit). For that cir
cuit, the op am p w as considered to be ideal and w e saw the effects o f a m ism atch o f a
single resistor. A m ism atch o f only 0.1% in one o f four resistors caused the C M R R o f the
circuit to be degraded to 66 dB. However, the com m on-m ode rejection ratio o f the o p er
ational am plifier is different than that o f the op am p circuit. For exam ple, the C M R R o f
an operational am plifier is usually greater than 100 dB and for the O P -177 a typical value
is 130 dB. In this section, w e shall consider only an operational am p lifier’s co m m o n
m ode rejection ratio specification and not the circ u it’s C M R R .
First rem em ber that an ideal op am p is a pure differential am plifier and is insensi
tive to the absolute voltages on the inputs w ith respect to ground. T he feedback co n n ec
tion for inverting and noninverting am plifiers m aintains the differential voltage, E(h near
0 V. In som e applications, such as com parators or in am plifier circuits w here the input
voltages exceed the level required to saturate the output, the differential voltage may ex
ceed a m axim um value. In order not to cause perm anent dam age to the device, this d if
ferential voltage m ust be w ithin the range bounded by the supply voltages.
For differential am plifiers, the voltage at both inputs can be g reater than or less than
ground potential but m ust be w ithin the supply voltage lim its. C om m on-m ode voltage,
E cm, is defined as the sam e voltage being applied to both inputs sim ultaneously. An ideal
operational am plifier responds only to the difference betw een the inputs {F.' — E ) and
produces zero output for a com m on-m ode v o ltag e— both inputs at the sam e potential.
However, due to slight differences betw een the input transistors that m ake up the input
differential pair o f an operational am plifier, the com m on-m ode voltage is not subtracted
entirely. H ence a com m on-m ode output voltage exists.
The com m on-m ode rejection ratio (C M R R ) is defined as the ratio o f the change in
com m on-m ode voltage to the resulting change in input offset voltage. It is often conve
nient to specify this param eter logarithm ically in dB:
CM R = 20 lo g l() (C M R R ) (9-9)
For exam ple, consider a com m on-m ode voltage o f 10 V results in a 10 fxV change
in input offset voltage. For this application, the C M R R is 10 V/IO fxV = 10^: l o r 120 dB.
T his expression m eans that a 10 V com m on-m ode voltage passes through the device as if
it w ere a 10 |jlV differential input signal.
C M R R is specified at dc but it is frequency dependent. T herefore, som e m anufac
turers will supply curves o f C M R R vs. frequency and you w ill see that it is a nonlinear
curve.
Note: C om m on-m ode rejection is som etim es defined as the ratio o f the open loop
gain to the com m on-m ode gain, w here com m on-m ode gain is the ratio o f the output volt
age to the com m on-m ode voltage. In equation form .
C M R = 20 l o g , o 4 ^ (9-10)
w here A OL is the op am p ’s open loop gain and A cm is the com m on-m ode gain and equals
the ratio o f the output voltage due to the input com m on-m ode voltage.
91 1 POWER SUPPLY REJECTION RATIO ---------------------------------------------------
Pow er supplies connected to the op am p should have low noise and be well regulated b e
cause all o f the op a m p ’s internal circuitry is sensitive to changes in supply voltages. The
m axim um offset versus supply value is a m easure o f this sensitivity. T he reciprocal o f the
sensitivity is the pow er supply rejection ratio (PSRR). T his param eter is conveniently ex
pressed logarithm ically as
PSR = 20 lo g 10 (PSR R ) ( 9 -I D
272 Chapter 9
Consider that an op amp has an offset change of 10 jxV per volt. This results in a
PSRR o f 100,000 (1 V/10 |xV) and a power supply rejection o f 100 dB. As a compari
son, the typical value of power supply rejection for the OP-177 op amp is 125 dB, and
for the 741 the sensitivity is only 30 jxV/V or a PSR of 90.5 dB.
PROBLEMS ______________________________________________________________________
9-1. Which op amp characteristics normally have the most effect on (a) dc amplifier performance;
(b) ac amplifier performance?
9-2. If IB+ = 0.2 jxA and IB- = 0.1 /jA , find (a) the average bias current 1B\ (b) the offset cur
rent Ios.
9-3. In Example 9-2, V0 = 0.2 V. Find /*_.
9-4. In Example 9-3, V0 = - 0 .2 V. Find IB+.
9-5. /*_ is 0.2 /LtA in Fig. 9-2(c). Find Va.
9-6. In Fig. 9-4(a), Rf = RG = 100 kCi. IB+ = 0.3 fiA and IB_ = 0.2 ijlA. Find Va.
9-7. In Fig. 9-4(b), Rf = R( = 25 kH and R = 12.5 kO. If Ios = 0.1 /iA, find Va.
9-8. In Fig. 9-4(b), = 25 k ft and /? = 12.5 kft. If Ios = -0 .1 /iA, find V0.
9-9. In Fig. 9-6(b), = 200 mV. Find Vio.
9-10. Resistors R u R2, # 3, and /?/all equal 20 k fi in Fig. 9-7(a). = E2 = £3 = = 2 mV. Find
(a) the actual value of V0\ (b) V0 assuming that Vio = 0.
9-11. What value of current-compensating resistor should be added in Problem 9-10?
9-12. What is the general procedure to null the dc output voltage of an op amp to 0 V?
9-13. In Fig. 9-9, Vio changes by ±0.5 mV when the temperature changes by 50°C. What is the
change in V0 due to the change in Viol
9-14. Ios changes by ± 2 nA in Fig. 9-9 for a temperature change of 50°C. What is the resulting
change in V01
9-15. V0 = 101 mV in the circuit in Fig. 9-10(a), VQ = 201 mV in Fig. 9-10(b), and V0 = - 9 9 mV
in Fig. 9-10(c). Find (a) (b) IB (c) IB+.
9-16. Refer to Fig. P9-16. Vio = 3 mV, IB- = 0.4 /xA, and IB+ = 0.1 fiA. (a) What is the best value
for resistor R1 Calculate the individual error in the output voltage, Va, due to (b) Vio only;
(c) IB+ only; (d) lB- only; (e) Ios only. The ideal value of V0 should be 1.00 V because of Et.
(f) What is the actual value of VQwhen both input offset voltage and current are present along
with Et?
50 k n
AA/V
+V
E: - - 0 .2 0 V
FIG U RE P9-16
9-17. An op amp’s typical common-mode rejection is 110 dB for the change in common-mode volt
age of 12 V. What is the change of input offset voltage?
9-18. Refer to Maxim Integrated Products’ Web site and compare their MAX4281 op amp CMRR
and PSRR with the OP-177 device.
CHAPTER 10
AC Performance:
Bandwidth, Slew Rate,
and Noise
LEARNING OBJECTIVES ____________________________________________________
Upon completion of this chapter on ac performance of an op amp, you will be able to:
• Recognize an op amp’s frequency response graph in the manufacturer’s data sheet,

determine (1) the dc open-loop gain A Ql> (2) the small-signal unity-gain bandwidth B
from it, and (3) read the magnitude of A Ql at any frequency.
• Calculate the unity-gain bandwidth if rise time is given, and vice versa.
• Predict the open-loop gain o f an op amp at any frequency if you know the unity-gain
bandwidth.
• Measure the rise time.
• Show how closed-loop gain, ACL, o f either an inverting or noninverting amplifier de
pends on open-loop gain, A OL.
• Measure the frequency response o f an inverting or noninverting amplifier.
274
AC Performance: Bandwidth, Slew Rate, and Noise 275
• Predict the bandwidth or upper cutoff frequency for an inverting amplifier if you know
the external resistor values and the op amp’s small-signal unity.
• Calculate the maximum sinusoidal frequency that can be obtained from an op amp at a
given peak output voltage if you know its slew rate.
• Calculate the maximum peak output voltage at any given sine frequency if the op amp’s
slew rate is known.
• Calculate noise gain.
• Understand the difference between open loop, closed loop, and loop gain.
10-0 INTRODUCTION _________________________________________________________________
When the op amp is used in a circuit that amplifies only ac signals, we must consider
whether ac output voltages will be small signals (below about 1 V peak) or large signals
(above 1 V peak). If only small ac output signals are present, the important op amp char
acteristics that limit performance are noise and frequency response. If large ac output sig
nals are expected, then an op amp characteristic called slew-rate limiting determines
whether distortion will be introduced by the op amp, and may further limit frequency re
sponse.
Bias currents and offset voltages affect dc performance and usually do not have to
be considered with respect to ac performance. This is especially true if a coupling ca
pacitor is in the circuit to pass ac signals and block dc currents and voltages. We begin
with an introduction to the frequency response of an op amp.
10-1 FREQUENCY RESPONSE OF THE OP AMP ____________________________________
10-1.1 Internal Frequency Compensation
General-purpose op amps and specialized op amps are internally compensated; that is,
the manufacturer has installed within such op amps a small capacitor, usually 30 pF. This
internal frequency compensation capacitor prevents the op amp from oscillating at high
frequencies. Oscillations are prevented by decreasing the op amp’s gain as frequency in
creases. Otherwise, there would be sufficient gain and phase shift at some high frequency
where enough output signal could be fed back to the input and cause oscillations (see
Appendix 1).
From basic circuit theory it is known that the reactance o f a capacitor goes down
as frequency goes up: Xc = 1/(2 77/C). For example, if the frequency is increased by 10,
the capacitor reactance decreases by 10. Thus, it is no accident that the voltage gain o f
an op amp goes down by 10 as the frequency of the input signal is increased by 10. A
change in frequency of 10 is called a decade. Manufacturers show how the open-loop gain
o f the op amp is related to the frequency of the differential input signal by a curve called
open-loop voltage gain versus frequency. The curve may also be called small-signal
response.
276 Chapter 10
10-1.2 Frequency-Response Curve
A typical curve is shown in Fig. 10-1 for internally compensated op amps such as the 741.
At low frequencies (below 0.1 Hz), the open-loop voltage gain is very high. A typical
value is 200,000 (106 dB), and it is this value that is specified on data sheets where a
curve is not given. See “Large-Signal Voltage Gain” equals 200,000 in Appendix 1. In
comparison, the open-loop gain for the OP-177 is greater than 140 dB or 10,000,000.
Point A in Fig. 10-1 locates the break frequency at which the open-loop voltage
gain o f the op amp is 0.707 times its value at very low frequencies. Therefore, the volt
age gain at point A (where the frequency of Ed is 5 Hz) is about 140,000, or 0.707 X
200,000.
Points C and D show how gain drops by a factor of 10 as frequency rises by a fac
tor o f 10. Changing frequency or gain by a factor of 10 is expressed more efficiently by
the term per decade (“decade” signifies 10). The right-hand vertical axis of Fig. 10-1 is
a plot o f voltage gain in decibels (dB). The voltage gain decreases by 20 dB for an in
crease in frequency of 1 decade. This explains why the frequency-response curve from A
Frequency (Hz)
FIGURE 10-1 Open-loop voltage gain of a 741 op amp versus frequency.

to £ is described as rolling off at 20 dB/decade. An alternative description is 6 dB/octave

roll-off (“octave” signifies a frequency change of 2). Therefore, each time the frequency
doubles, the voltage gain decreases by 6 dB.
10-1.3 Unrty-Gain Bandwidth
When an amplifier is made from an op amp and a few resistors, the frequency response
o f the amplifier depends on the frequency response o f the op amp. The key op amp char
acteristic is defined as that frequency where the op amp’s gain equals unity. We will use
the symbol B for this op amp characteristic, which is called small-signal unity-gain band
width. Later in this chapter we will need a value for B o f the op amp to predict the high-
frequency response o f an amplifier constructed with this op amp.
Three ways to obtain B from a manufacturer’s data sheet are presented in this sec
tion. First, if you have the manufacturer’s plot o f A ql versus frequency, look for that fre
quency where Aql = 1 (see point B in Fig. 10-1, B = 1 MHz). Second, some data sheets
may not give a specification called unity-gain bandwidth or a curve like Fig. 10-1. Instead,
they give a specification called transient response rise time (unity gain). For a 741 op amp
it is typically 0.25 jms and 0.8 |xs at maximum. The bandwidth B is calculated from the
rise-time specification by
rise time
where B is in hertz and rise time is in seconds. Rise time is defined in Section 10-1.4.
(See the “Electrical Characteristics” tables in Appendix 1, ‘Transient Response (Unity
Gain)” = 0.3 jjus typical.)
Example 10-1
A 741 op amp has a rise time o f 0.35 /is. Find the small-signal or unity-gain bandwidth.
0 35
B= = 1 MHz
0.35 p,s
Example 10-2
What is the open-loop voltage gain for the op amp of Example 10-1 at 1 MHz?
Solution From the definition o f B, the voltage gain is 1.
Example 10-3
What is the open-loop voltage gain at 100 kHz for the op amp in Examples 10-1 and 10-2?
278 Chapter 10
Solution By inspection o f Fig. 10-1, if the frequency goes down by 10, the gain goes up
by 10. Therefore, since the frequency goes down by a decade (from 1 MHz to 100 kHz),
the gain must go up by a decade from 1 at 1 MHz to 10 at 100 kHz.
Example 10-3 leads to the conclusion that if you divide the frequency o f the signal,
/ into the unity-gain bandwidth, B, the result is the op amp’s gain at the signal frequency.
Expressed mathematically,
, . - bandwidth at unity gain

open-loop gam at / = ----- — :--- — ------1 - (10-2)
input signal frequency, /
Exam ple 10-4
What is the open-loop gain o f an op amp that has a unity-gain bandwidth o f 1.5 MHz for
a signal o f 1 kHz?
Solution From Eq. (10-2), the open-loop gain at 1 kHz is
1 kHz
Equation (10-2) gives a third way to find B. If you know the op amp’s open-loop
gain at one frequency (in the roll-off region), simply multiply the two values to obtain B.
Let’s consider Example 10-4 again. If A Ql = 1000 at a frequency of 1500 Hz, then B =
1500 X 1000 = 1.5 MHz.
The data shown in Fig. 10-1 are useful for learning but probably do not apply to
your op amp. For example, while 200,000 is a specified typical open-loop gain for the
741, the manufacturer guarantees only a minimum gain o f 20,000 for general-purpose
op amps. Still, 20,000 may be enough to do the job. Section 10-2 deals with this ques
tion.
10-1.4 Rise Time
Assume that the input voltage E t of a unity-gain amplifier is changed very rapidly by a
square wave or pulse signal. Ideally, E t should be changed from 0 V + 20 mV in 0 time;
practically, a few nanoseconds are required to make this change (see Appendix 1,
‘Transient Response” in the “Typical Performance Curves”). At unity gain, the output
should change from 0 to + 2 0 mV in the same few nanoseconds. However, it takes time
for the signal to propagate through all the transistors in the op amp. It also takes time for
the output voltage to rise to its final value. Rise time is defined as the time required for
the output voltage to rise from 10% o f its final value to 90% o f its final value. From
Section 10-1.3, the rise time o f a 741 is 0.35 /ts. Therefore, it would take 0.35 /is for the
output voltage to change from 2 mV to 18 mV.
10-2 AMPLIFIER GAIN AND FREQUENCY RESPONSE
10-2.1 Effect of Open-Loop Gain on Closed-Loop Gain

of an Amplifier, DC Operation
It is necessary to leam how open-loop gain AOL affects the actual closed-loop gain o f an
amplifier with dc signal voltages (zero frequency). First, we must define ideal closed-loop
gain o f an amplifier as that gain which should be determined only by external resistors.
However, the actual dc closed loop o f an amplifier is determined by both the external re
sistors and open-loop gain o f an op amp.
The actual dc closed-loop gain o f a noninverting amplifier is
_ (Rf+Rd/R,
actual ACl /Rf + R i\ (10-3a)
i+ ± h n
where
Rf + Rt
= ideal ACL for noninverting amplifiers (10-3b)
If A0 l is very large, the denominator o f Eq. (10-3a) approaches unity. Then the amplifier
gain will not depend on the open-loop gain of the op amp but rather only on the external
resistors and can be calculated from Eq. (10-3b).
The actual dc gain o f an inverting amplifier depends on Aql according to
A /tfllA l A ^
- Rf /R,
____________________ —________
(10-3c)
where
-R f
—— = ideal ACL for inverting amplifiers (10-3d)
R i
Equation (10-3d) is valid if Aql is large with respect to (Rf + Ri)/Rt.
Exam ple 10-5
Find the actual gain for a dc noninverting amplifier if ideal ACl — 100 and AOL is (a)
10,000; (b) 1000; (c) 100; (d) 10; (e) 1. Repeat for a dc inverting amplifier with an ideal
gain o f —100.
Solution (a) For the noninverting amplifier: (Rf + Ri)/Ri = 100 = ideal gain. From
Eq. (10-3a),
280 Chapter 10
100
actual A cl = = 99.0099
1 + — -— 1100
10,0 0 0 ,/
For the inverting amplifier, Rf/Ri = Iideal gain| = 1 0 0 . Therefore, (Rf + Ri)/Ri = 1 0 1 .
From Eq. (10-3c),
actual ACL =
-100
= -9 9 .0 0 0 0
1 +
io,ooo )101
If these steps are repeated for parts (b) through (e), the results may be tabulated as
follows:
Aql
1 10 100 103 104 105
Actual Acl% noninverting 0.99 9.09 50 90.9 99.0 99.9

Actual ACl>inverting -0 .9 8 -9.01 -4 9 .7 -9 0 .8 -9 9 .0 -9 9 .9
The results o f Example 10-5 are shown by plot ACl versus A ql in Fig. 10-2.
There are two important lessons to be learned from Example 10-5 and Fig. 10-2. First
FIGURE 10-2 The actual closed-loop gain of an inverting or noninverting

amplifier depends on both the ideal gain that is set by resistor ratios, and the
open-loop gain of the op amp at dc (see Example 10-5).
the actual gains o f both noninverting and inverting amplifiers are o f approximately the
same magnitudes for the same value o f open-loop gain. Second, we would like the ac
tual closed-loop gain to be equal to the ideal closed-loop gain. An examination o f Eqs.
(10-3a) and (10-3c) shows that this w ill be true i/t h e open-loop gain o f the op amp
Aol is large with respect to the ideal closed-loop gain o f the op amp. Practically, we
would like AGl to be 100 or more tim es the ideal ACL, so that the
external precision resistors and not the op amp’s AOL determine the actual gain, to
within 1%.
We already learned in Section 10-1.2 that AOL depends on frequency. Since AOL o f
the op amp also determines ACL o f an amplifier, then ACL o f the amplifier will also de
pend on frequency. But before we look at the amplifier’s frequency response we must de
fine it and also define bandwidth.
10-2.2 Small-Signal Bandwidth, Low- and High-Frequency

Limits
The useful frequency range o f any amplifier (closed- or open-loop) is defined by a

high-frequency limit f H and a low-frequency lim it//.. At f L and f H, the voltage gain is
down to 0.707 times its maximum value in the middle o f the useful frequency range.
In terms o f decibels, the voltage gain is down 3 dB at both//, and f H. These statements
are summarized on the general frequency response curve in Fig. 10-3 and in Appen
dix 1.
fi Ih
FIG URE 10-3 Small-signal bandwidth.
282 Chapter 10
Small-signal bandwidth is the difference between f H and f L. Often f L is very small

with respect to ///, o r /L is 0 for a dc amplifier. Therefore, the small-signal bandwidth ap
proximately equals the high-frequency limit fH. From point A o f Fig. 10-1, we see that
the small-signal bandwidth o f an op amp is 5 Hz.
10-2.3 Measuring Frequency Response
You can learn a lot about frequency response by learning how to measure frequency re
sponse at a test bench.
Laboratory procedure. The frequency-response curve o f Fig. 10-3 would have

been obtained in the following manner:
1. Adjust the input voltage Eto f an op amp to some convenient value, let’s say
30 mV rms.
2. Set the sinusoidal frequency o f Etto some convenient midband value, let’s say
1000 Hz.
3. Measure the midband output voltage; assume that it equals 3.0 V.
4. Calculate the midband voltage gain ACL = 3 V/0.030 V = 100.
5. Calculate the expected value o f VQat fL and fH>VQ= (0.707) (V0 midband). Thus VQ=
(0.707) 3 V = 2.1 V rms where ACL = 70.7.
6. Hold Ei constant in magnitude at 30 mV. Reduce the oscillator frequency until
V0 = 2.1 V. Read the oscillator dial frequency to obtain the lower cutoff fre
quency f L.
7. Hold Ei constant in amplitude at 30 mV. Increase the oscillator frequency (beyond 1
kHz) until VQagain drops to 2.1 V. Read f H from the oscillator dial.
8. Calculate bandwidth B from B = f H —f L.
Note: For dc amplifiers, / = 0; therefore, B = f H.
The low and high cutoff frequencies are also called the comer frequencies, the
3-dB frequencies, the 0.707 frequencies, or simply the cutoff frequencies.
10-2.4 Bandwidth of Inverting and Noninverting Amplifiers
In this section let’s stipulate that all amplifiers are direct coupled. Next, observe that both
inverting and noninverting amplifiers are made from exactly the same structure. They
have an op amp, a feedback resistor Rf , and an input resistor Rs. An amplifier only as
sumes an identity when you choose which input will experience the input signal. If you
connect Exvia Rt to the ( —) input and ground the (+ ) input, you define the amplifier to
be inverting. If E{is wired to ( + ) input and ground to Rh the same structure becomes a
noninverting amplifier.
In view o f the observation above, it is perhaps not surprising that the upper cutoff
frequency f Hfor both inverting and noninverting amplifiers is given by
h = ~ (10-4)
(Rf+Rd/R,
where B = op amp small-signal bandwidth
Rf = feedback resistance
Rt = input resistor
Exam ple 10-6
Given that Rf = /?, = lO k fi for an inverting amplifier and also for a noninverting amplifier,
find the gain and bandwidth o f (a) the inverting amplifier; (b) the noninverting amplifier, (c)
What are the gain and bandwidth o f a voltage follower? The op amp is a 741 with a small-
signal gain-bandwidth product o f B = 1 MHz.
Solution (a) From Eq. (3-2b) or (10-3d), A Cl ~ ~R /!R i = —1. From Eq. (10-4),
f H= ---------—— 6 — --------- = 500 kHz

JM (io k n + io k fiy io kn
(b) From Eq. (3-1 lb ) or (10-3b), ACl —(Rf + RdfRi = 2. fa is the same as in part (a). The
noninverting amplifier has a higher gain-bandwidth product than the inverting amplifier.
(c) The voltage follower has a gain o f 1 [see Eq. (3-9b)]. In Eq. (3-1 lb), Rf = 0 and Rt is
an open circuit approaching an infinite resistance for a voltage follower. Therefore, (Rf +
Ri)/Rt = 1. Hence the upper cutoff frequency fH is calculated from Eq. (10-4) as
, 1 X 106 Hz 106 Hz
fH= ^ = — :----- = 1 MHz
JH (Rf + Ri)/Ri 1
10-2.5 Finding Bandwidth by a Graphical Method
There is a graphical technique for obtaining the frequency response o f a noninverting am
plifier. An example is shown in Fig. 10-4. Let the amplifier gain equal 1000 at low and
middle frequencies. From Eq. (1 0 -4 ),/# = 999 Hz =* 1 kHz. At f H, the amplifier gain is ap
proximately 700 (0.707 X 1000 — 700). For all frequencies above f H, the frequency re
sponse o f the amplifier and op amp coincide. For another example, use Fig. 10-4 and draw
a horizontal line starting at A Cl = 100. The ending point where it intercepts the curve o f
A0l versus /s h o w s the amplifier’s bandwidth. For this c a se ,/# — 10 kHz. The conclusion
is that the gain-bandwidth product o f a noninverting amplifier is equal to B o f the op amp.
There is a direct trade-off. If you want more closed-loop gain, you must sacrifice band
width.
284 Chapter 10
Rj= 999 kO
t
f H = bandwidth of amplifier
Frequency (Hz)
FIGURE 10-4 Op amp small-signal bandwidth and amplified closed-loop
bandwidth.
10-3 SLEW RATE AND OUTPUT VOLTAGE __________________________________________
10-3.1 Definition of Slew Rate
The slew rate o f an op amp tells how fast its output voltage can change. For a general-
purpose op amp such as the 741, the maximum slew rate is 0.5 V //is. This means that the
output voltage can change a maximum o f { V in 1 /is. Slew rate depends on many fac
tors: the amplifier gain, compensating capacitors, and even whether the output voltage is
going positive or negative. The worst case, or slowest slew rate, occurs at unity gain.
Therefore, slew rate is usually specified at unity gain (see Appendix 1).
10-3.2 Cause of Slew-Rate Limiting
Within general-purpose op amps at least one capacitor is required to prevent oscillation

(see Section 10-1.1). Connected to this capacitor is a portion o f the op amp’s internal cir
cuitry that can furnish a maximum current that is limited by op amp design. The ratio o f
this maximum current I to the compensating capacitor C is the slew rate. For example, a
741 can furnish a maximum o f 15 /xA to its internal 30-pF compensating capacitor (see
Appendix 1). Therefore,
slew rate = outPut voltagc change . 1 = I L n L = 0 ,5 X (10. 5)

time C 30 pF /ts u ;
From Eq. (10-5), a faster slew rate requires the op amp to have either a higher
maximum current or a smaller compensating capacitor. Op amps with slew rates greater
than 100 V//xs are referred to as high-speed operational amplifiers. For special appli
cations such as video systems, op amps with slew rates greater than 1000 V//xs are
available.
Exam ple 10-7
An instantaneous input change o f 10 V is applied to a unity-gain inverting amplifier. If the

op amp is a 741, how long will it take for the output voltage to change by 10 V?
Solution By Eq. (10-5),
slew rate = output voltage change

time
0.5 V 10 V lO V X ^ s
-------- = —------ . time = — T-z-rr^ = 2 0 as
l*s time 0.5 V
10-3.3 Slew-Rate Limiting of Sine Waves
In the voltage follower o f Fig. 10-5, Et is a sine wave with peak amplitude Ep. The
maximum rate o f change o f depends on both its frequency / and the peak ampli
tude. It is given by 2TtfEp. If this rate o f change is larger than the op amp’s slew rate,
the output V0 w ill be distorted. That is, output V0 tries to follow Et but cannot do so
because o f slew-rate limiting. The result is distortion, as shown by the triangular shape
o f V„ in Fig. 10-5. The maximum frequency / max at which we can obtain an undistorted
output voltage with a peak value o f Vop is determined by the slew rate in accordance
286 Chapter 10
FIGURE 10-5 Example of slew-rate limiting of output voltage VQ.
with
slew rate
/m ax (10-6a)
6.28 X Vtop
where / max is the maximum frequency in Hz, Vop is the maximum undistorted output volt
age in volts, and the slew rate is in volts per microsecond.
The maximum peak sinusoidal output voltage Vop max that can be obtained at a
given frequency / i s found from
slew rate
r op max (10-6b)
6.28 X /
Example 10-8
The slew rate for a 741 is 0.5 V//xs. At what maximum frequency can you get an undis
torted sine-wave output voltage o f (a) 10-V peak; (b) 1-V peak?
Solution (a) From Eq. (10-6a),
f = 1 V M I _ o k„ 7
/max 6.28 X 10 V MS
(b) From Eq. (10-6a),
/m a x = 80 kHz
In the next example, we leam that the slew rate and bandwidth must both be con
sidered before we can predict the highest frequency at which we can obtain an undistorted
output voltage.
Example 10-9
In Example 10-6, the small-signal bandwidth was 500 kHz for both an inverting amplifier
with a gain o f —1 and a noninverting amplifier with a gain o f 2. Find (a) the maximum peak
and undistorted sine wave output voltage at f H = 500 kHz; (b) the maximum frequency at
which you can obtain a peak output voltage o f 10 V.
Solution Since the op amp is a 741, its maximum slew rate is 0.5 V / jis. (a) From Eq.
(10-6b),
- 6.28(5° ^ ) H z ' 160 mV

(b) From Eq. (10-6a),
= 0.5 V//xs ^
/m“ (6.28)(10 V)
/m ax is defined as full-power output frequency dXfull-power output. The meaning o f

these new terms will become clear after a brief introduction.
A prudent amplifier design would restrict V0 to limits of ± 10 V. Then you have a safety
margin o f ±20% if the amplifier is overdriven at ± 12 V (almost into ±Vssa). Manufacturers
of op amps specify the ± 1 0 V output voltage level as full-power output Note that a full-
power output frequency specification is often supplied by the manufacturer (see Appendix 1,
“Output Voltage Swing as a Function of Frequency” in the “Typical Performance Curves”).
Examples 10-8 and 10-9 showed that the op amp’s slew rate limits the upper frequency of
laige-amplitude output voltages. As the peak output voltage required from the op amp is re
duced, the upper-frequency limitation imposed by the slew rate increases.
Recall that the upper-frequency limitation imposed by small-signal response
increases as the closed-loop gain decreases. For each amplifier application, the upper-
frequency limit imposed by slew-rate limiting (Section 10-3.3) and small-signal bandwidth
288 Chapter 10
(Section 10-2.3) must be calculated. The smaller value determines the actual upper-
frequency limit. In general, the slew rate is a large-signal frequency limitation and small-
signal frequency response is a small-signal frequency limitation.
10-3.4 Slew Rate Made Easy
Figure 10-6 simplifies the problem of finding / max at any peak output voltage for slew
rates between 0.5 and 5 V/fjus. For example, to do part (b) of Example 10-8, locate where
the horizontal line Vop = 10 V intersects the slew-rate line 0.5 V / j l l s . Below the intersec
tion, read / max = 8 kHz.
Maximum sine frequency (kHz)
FIGURE 10-6 Slew rate made easy. Any point on a slew-rate line shows the
maximum sinusoidal frequency allowed for the corresponding peak output
voltage.
10-4 NOISE IN THE OUTPUT VOLTAGE _____________________________________________
10-4.1 Introduction
Undesired electrical signals present in the output voltage are classified as noise. Drift (see
Chapter 9) and offsets can be considered as very-low-frequency noise. If you view the
output voltage o f an op amp amplifier with a sensitive oscilloscope setting (1 mV/cm),
you will see a random display o f noise voltages called hash. The frequencies o f these
noise voltages range from 0.01 Hz to megahertz.
Noise is generated in any material that is above absolute zero (-2 7 3 °C ). Noise is
also generated by all electrical devices and their controls. For example, in an automobile
the spark plugs, voltage regulator, fan motor, air conditioner, and generator all generate
noise. Even when headlights are switched on (or off), there is a sudden change in current
that generates noise. This type o f noise is external to the op amp. Effects o f external noise
can be minimized by proper construction techniques and circuit selection (see Sections
10-4.3 to 10-4.5).
10-4.2 Noise in Op Amp Circuits
Even if there was no external noise, there would still be noise in the output voltage caused
by the op amp. This internal op amp noise is modeled most simply by a noise voltage
source En. As shown in Fig. 10-7, En is placed in series with the ( + ) input. On data sheets,
noise voltage is specified in microvolts or nanovolts (rms) for different values o f source
resistance over a particular frequency range. For example, the 741 op amp has 2 /xV of to
tal noise over a frequency o f 10 Hz to 10 kHz. This noise voltage is valid for source
C/ = 3pF
---- W v ----
Rf = 100 kft
k+V
FIGURE 10-7 Op amp noise is

modeled by a noise voltage in series
with the (+ ) input.
290 Chapter 10
resistors (Ri) between 100 f l and 20 kfl. The noise voltage goes up directly with /?, once
Ri exceeds 20 kft. Thus Rt should be kept below 20 k fl to minimize noise in the output
(see Appendix 1). Data sheets may also specify an input current value over the same fre
quency range.
10-4.3 Noise Gain
Noise voltage is amplified just as offset voltage is. That is, noise voltage gain is the same
as the gain o f a noninverting amplifier:
noise gain = 1 + — (10-7)

Ri
What can you do about minimizing output voltage errors due to noise? First, avoid, if pos
sible, large values o f and Rf. Install a small capacitor (3-pF) across Rf to shunt it at
high noise frequencies. Then the higher noise frequencies will not be amplified as much.
Next, do not shunt Rt with a capacitor; otherwise, the RtC combination will have a smaller
impedance at higher noise frequencies than Rt alone, and gain will increase with fre
quency and aggravate the situation. Finally, try to keep Rt at about 10 k fl or below.
N oise currents, like bias currents, are also present at each op amp input terminal. If
a bias-current compensation resistor is installed (see Chapter 9), the effect of noise cur
rents on output voltage will be reduced. As with offset current, the effects o f noise cur
rents also depend on the feedback resistor. So if possible, reduce the size o f Rf to mini
mize the effects of noise currents.
10-4.4 Noise in the Inverting Adder
In the inverting adder (see Section 3-2), each signal input voltage has a gain o f 1. However,
the noise gain will be 1 plus the number of inputs; for example, a four-input adder would
have a noise gain o f 5. Thus noise voltage has five times as much gain as each input signal.
Therefore, low-amplitude signals should be preamplified before connecting them to an adder.
10-4.5 Summary
To reduce the effects o f op amp noise:

1. Never connect a capacitor across the input resistor or from ( - ) input to ground.
There will always be a few picofarads of stray capacitance from ( - ) input to ground
due to wiring, so
2. Always connect a small capacitor (3 pF) across the feedback resistor. This reduces
the noise gain at high frequencies.
3. If possible, avoid large resistor values.
10-5 LOOP GAIN ____________________________________________________________
Loop gain (A(3) is defined as the ratio o f open-loop gain to closed-loop gain.
( 10- 8)
See Fig. 10-8. Loop gain determines circuit performance. For 1% gain accuracy, the loop
gain must be 100 times the closed-loop gain. This is the same conclusion stated in Section
10-2. Hence the greater the loop gain at a particular frequency, the closer the closed-loop
gain depends only on external circuit values.
0 is that fraction o f the output fed back to the input
1 Rj + R f
(10-9)
P R,
Figure 10-9 shows that the noise gain may peak in the vicinity o f the frequency at
which A|$ = 1 even if the signal gain (the normal closed-loop gain) rolls off at a much
lower frequency. This is because the loop gain may have more than 90° phase shift and
the amplifier is lightly damped at this frequency.
Gain
A
Open loop gain A0L
,Closed loop bandwidth
■w
FIGURE 10*8 Loop gain.

292 Chapter 10
PROBLEMS __________________________________________________________________________
10-1. What is the typical open-loop gain of a 741 op amp at very low frequencies?
10-2. The dc open-loop gain of an op amp is 100,000. Find the open-loop gain at its break fre
quency. V
10-3. The transient response rise time (unity gain) of an op amp is 0.07 /as. Find the small-signal
bandwidth.
10-4. An op amp has a small signal unity-gain bandwidth of 2 MHz. Find its open-loop gain at
200 kHz.
10-5. What is the difference between the open-loop and closed-loop gain of an op amp?
10-6. What is the open-loop gain for the op amp of Problem 10-4 at 2 MHz?
10-7. What is rise time?
10-8. An op amp has a dc open-loop gain of 100,000. It is used in an inverting amplifier circuit
with Rf = 100 kH, Ri = 10 kft. Find the actual dc closed-loop gain.
10-9. The op amp of Problem 10-8 is used in a noninverting amplifier with the same Rf and Rh
Find the amplifier’s actual dc closed-loop gain.
10-10. What is the small-signal bandwidth of the op amp whose frequency response is given in Fig.
10- 1?
10-11. The unity-gain bandwidth of an op amp is 10 MHz. It is used to make a noninverting am
plifier with an ideal closed-loop gain of 100. Find the amplifier’s (a) small-signal band
width; (b) Ac l at///.
10-12. How fast can the output of an op amp change by 10 V if its slew rate is 1 V//as?
10-13. Find the maximum frequency for a sine-wave output voltage of 10-V peak with an op amp
whose slew rate is 1 V//is.
10-14. Find the noise gain for an inverting amplifier with a gain of /?///?, = -1 0 .
10-15. What is the noise gain for a five-input inverting adder?
10-16. The op amp in Example 10-9 is changed to one with a slew rate of 1 V//xs. Find its maxi
mum full-power output frequency. Assume that V0 max = 10-V peak.
10-17. Use the Internet and compare the slew rate of an OP-177 op amp with a MAX4281.
CHAPTER 11
Active Filters
-----------------------------------------------------------------------------------------------------------------------------
LEARNING O B J E C T I V E S
Upon completion o f this chapter on active filters, you will be able to:
• Name the four general classifications o f filters and sketch a frequency-response cur^fe
that shows the band o f frequencies that they pass and stop. *
• Design or analyze circuits for three types o f low-pass filters: —20 dB/decade, —40 dB/
decade, or - 6 0 dB/decade roll-off.
• Design or analyze circuits for three types of high-pass filters: + 2 0 dB, + 4 0 dB, and
+ 6 0 dB per decade o f roll-off.
• Cascade a low-pass filter with a high-pass filter to make a wide bandpass filter.
• Calculate the lower and upper cutoff frequencies of either a bandpass or a notch filter
if you are given (1) bandwidth and resonant frequency, (2) bandwidth and quality fac
tor, or (3) resonant frequency and quality factor.
294
Active Filters 295
• Calculate the quality factor, bandwidth, and resonant frequency of a bandpass or notch
filter for a given lower and upper cutoff frequency.
• Design a bandpass filter that uses only one op amp.
• Make a notch filter by (1) designing a bandpass filter circuit with the same bandwidth
and a resonant frequency equal to the notch frequency, and (2) properly connecting the
bandpass circuit to an inverting adder.
• Explain the operation o f a stereo equalizer circuit.
• Use PSpice to simulate the performance o f filter circuits.
11-0 INTRODUCTION __________________________________________________________________
A filter is a circuit that is designed to pass a specified band o f frequencies while attenu
ating all signals outside this band. Filter networks may be either active or passive. Passive
filter networks contain only resistors, inductors, and capacitors. Active filters, which are
the only type covered in this text, employ transistors or op amps plus resistors, inductors,
and capacitors. Inductors are not often used in active filters, because they are bulky and
costly and may have large internal resistive components.
There are four types o f filters: low-pass, high-pass, bandpass, and band-elimination
(also referred to as band-reject or notch) filters. Figure 11-1 illustrates frequency-
Wo\ Wo\
A A
\
X
\
\
Passband t\ Stop band Stopband Passband

* r x ------------
Frequency fc Frequency
(a) Low-pass filter. (b) High-pass filter.
|V„I W0\
A
\ /
\ Stop /
\ /
‘ Passband ' band t Passband
I I
i L i --------------------------►
/,
fr A Frequency
(c) Bandpass filter. (d) Band-elimination filter.
FIGURE 11-1 Frequency response for four categories of filters.
296 Chapter 11
response plots for the four types of filters. A low-pass filter is a circuit that has a constant
output voltage from dc up to a cutofffrequency /<*. As the frequency increases above f c,
the output voltage is attenuated (decreases). Figure 11-1(a) is a plot of the magnitude of
the output voltage o f a low-pass filter versus frequency. The solid line is a plot for the
ideal low-pass filter, while the dashed lines indicate the curves for practical low-pass fil
ters. The range o f frequencies that are transmitted is known as the passband. The range
o f frequencies that are attenuated is known as the stop band. The cutoff frequency, f C9 is
also called the 0.707 frequency, the -3 -d B frequency, the comer frequency, or the break
frequency.
High-pass filters attenuate the output voltage for all frequencies below the cutoff
frequency / c. Above f c> the magnitude o f the output voltage is constant. Figure 11-1(b) is
the plot for ideal and practical high-pass filters. The solid line is the ideal curve, the
dashed curves show how practical high-pass filters deviate from the ideal.
Bandpass filters pass only a band of frequencies while attenuating all frequencies
outside the band. Band-elimination filters perform in an exactly opposite way; that is,
band-elimination filters reject a specified band o f frequencies while passing all frequen
cies outside the band. Typical frequency-response plots for bandpass and band-elimina-
tion filters are shown in Figs. l l - l ( c ) and (d). Once again, the solid line represents the
ideal plot, while dashed lines show the practical curves.
Filters are an integral part of electronic networks and are used in applications from
audio circuits to digital signal processing systems.
11-1 BASIC LOW-PASS FILTER _______________________________________________________
11-1.1 Introduction
The circuit of Fig. 1 l-2(a) is a commonly used low-pass active filter. The filtering is done
by the RC network, and the op amp is used as a unity-gain amplifier. The resistor Rf is
equal to R and is included for dc offset. [At dc, the capacitive reactance is infinite and the
dc resistance path to ground for both input terminals should be equal (see Section 9-4).]
The differential voltage between pins 2 and 3 is essentially 0 V. Therefore, the volt
age across capacitor C equals output voltage VQ, because this circuit is a voltage follower.
Et divides between R and C. The capacitor voltage equals VQand is
V° = R +\/ja>C X E‘ (1 M a )
where <o is the frequency of £ , in radians per second (o> = 2 irf) and j is equal to V ^ T .
Rewriting Eq. (11-la) to obtain the closed-loop voltage gain A CL, we have
To show that the circuit of Fig. 1 l-2(a) is a low-pass filter, consider how A CL in Eq. (1 1-lb)
varies as frequency is varied. At very low frequencies, that is, as a>approaches 0 ,1 ACL | =
1, and at very high frequencies, as cdapproaches infinity, | A Cl I = 0. (The absolute value
sign, | • | , indicates magnitude.)
Active Filters 297
(b) Frequency-response plot for the circuit of part (a).

FIGURE 11-2 Low-pass filter and frequency-response plot for a filter with a
—20-dB/decade roll-off.
Figure 1 l-2(b) is a plot of | ACl I versus a>and shows that for frequencies greater than
the cutoff frequency \ a Cl I decreases at a rate o f 20 dB/decade*. This is the same as say
ing that the voltage gain is divided by 10 when the frequency o f <o is increased by 10.
11-1.2 Designing the Filter
The cutoff frequency <ac is defined as that frequency o f E, where \a Cl \ is reduced to

0.707 times its low-frequency value. This important point will be discussed further in
Section 11-1.3. The cutoff frequency is evaluated from
298 Chapter 11
where a>c is the cutoff frequency in radians per second, fc is the cutoff frequency in hertz,
R is in ohms, and C is in farads. Equation (1 l-2a) may be rearranged to solve for R:
= 2 ^ C ( 1 ' - 2b)
Exam ple 11-1
Let R = 10 k fl and C = 0.001 /iF in Fig. 1 l-2(a); what is the cutoff frequency?
Solution By Eq. (11-2a),
= (10 x l^XO.OOl X 10- 6 ) = 100113(1/8

or
6.28 6.28
Exam ple 11-2
For the low-pass filter in Fig. 11-2(a), calculate R for a cutoff frequency o f 2 kHz and
C = 0.005 nF.
Solution From Eq. (ll-2 b ),
R = a>c C = (6.28)(2 X 103)(5 X 10- 9 ) = 15'9 kft

Exam ple 11-3
Calculate R in Fig. 1 l-2(a) for a cutoff frequency of 30 krad/s and C = 0.01 fjF.
Solution From Eq. (1 l-2b),
R ~ wc C ~ (30 X 103)(1 X 10- 8 ) - 3,3 ^

Design Procedure The design o f a low-pass filter similar to Fig. 11-2(a) is accom
plished in three steps:
1. Choose the cutoff frequency— either <dc or

2. Choose the capacitance C, usually between 0.001 and 0.1 /xF.
3. Calculate R from Eq. (ll-2 b ).
Active Filters 299
11-1.3 Filter Response
The value o f ACL at toc is found by letting cdRC = 1 in Eq. (11-lb):
Therefore, the magnitude o f ACl at <oc is
lAcz.1 = = 0.707 = - 3 dB
and the phase angle is - 4 5 ° .

The solid curve in Fig. 11-2(b) shows how the magnitude o f the actual frequency
response deviates from the straight dashed-line approximation in the vicinity o f <oc. At
0.1 <oc, \a cl | =* 1 (0 dB), and at 10<uc, \a Cl I “ 0-1 ( —20 dB). Table 11-1gives both
the magnitude and the phase angle for different values of to between 0.1 <ac and10o>c.
Many applications require steeper roll-offs after the cutoff frequency. One common
filter configuration that gives steeper roll-offs is the Butterworth filter.
TABLE 11-1 MAGNITUDE AND

PHASE ANGLE FOR THE LOW-PASS
FILTER OF FIG. 11-2(a)
0> \&cl \ Phase angle (deg)
0A<oc 1.0 —6
0.25<oc 0.97 -1 4
0.5<yc 0.89 -2 7
0.707 -4 5
2(t>c 0.445 -6 3
4a>c 0.25 -7 6
\0a>c 0.1 -8 4
11-2 INTRODUCTION TO THE BUTTERWORTH FILTER _____________________________
In many low-pass filter applications, it is necessary for the closed-loop gain to be as close
to 1 as possible within the passband. The Butterworth filter is best suited for this type o f
application. The Butterworth filter is also called a maximally flat or flat-flat filter, and all
filters in this chapter will be o f the Butterworth type. Figure 11-3 shows the ideal (solid
line) and the practical (dashed lines) frequency response for three types o f Butterworth
filters. As the roll-offs become steeper, they approach the ideal filter more closely.
Two active filters similar to Fig. 11-2(a) could be coupled together to give a roll
off o f - 4 0 dB/decade. This would not be the most economical design, because it would
require two op amps. In Section 11-3.1, it is shown how one op amp can be used to build
a Butterworth filter with a single op amp to give a -40-d B /d ecad e roll-off. Then in
Section 11-4, a —40-dB/decade filter is cascaded with a —20-dB/decade filter to produce
a -60-dB /decade filter.
300 Chapter 11
Butterworth filters are not designed to keep a constant phase angle at the cutoff fre
quency. A basic low-pass filter of —20 dB/decade has a phase angle of —45° at (oc. A
-40-dB /decade Butterworth filter has a phase angle of -90° at <oc, and a “ 60-dB/decade
filter has a phase angle of —135° at a)c. Therefore, for each increase of —20 dB/decade,
the phase angle will increase by —45° at a>c. We now proceed to a Butterworth filter that
has a roll-off steeper than —20 dB/decade.
FIGURE 11-3 Frequency-response plots for three types of low-pass

Butterworth filters.
11-3 - 40-DB/DECADE LOW-PASS BUTTERWORTH FILTER _______________________
11-3.1 Simplified Design Procedure
The circuit o f Fig. 1 l-4(a) is one o f the most commonly used low-pass filters. It produces
a roll-off o f —40 dB/decade; that is, after the cutoff frequency, the magnitude o f ACl de
creases by 40 dB as <o increases to 10<oc. The solid line in Fig. ll-4 (b ) shows the actual
frequency-response plot, which is explained in more detail in Section 11-3.2. The op amp
is connected for dc unity gain. Resistor Rf is included for dc offset, as explained in Section
9-4. Since the op amp circuit is basically a voltage follower (unity-gain amplifier), the
voltage across Cy equals output voltage, V0.
The design o f the low-pass filter o f Fig. 1 l-4(a) is greatly simplified by making re
sistors R{ = R2 = R. Then there are only five steps in the design procedure.
Design procedure
1. Choose the cutoff frequency, <oc or f c.
2. Pick C\\ choose a convenient value between 100 pF and 0.1 fiF.
3. Make C2 — 2C i.
4. Calculate
O _ 0.707
A — — (11-3)
(Oc Cl
5. Choose Rf = 2R.
c2
(b) Frequency-response plot for the low-pass filter of part (a).
FIGURE 11-4 Circuit and frequency plot for a low-pass filter of

- 4 0 dB/decade.
Example 11-4
Determine Ri and R2 in Fig. ll-4 (a ) for a cutoff frequency of 1 kHz. Let Cx = 0.01 /iF.
Solution Pick C2 = = 2(0.01 /xF) = 0.02 /iF. Select R\ = R2 = R from Eq. (11.3):
p = ___________ 0.707___________ = 1 1 258 f l

(6.28)(1 X 103)(0.01 X 10"6) ’
and
Rf = 2(11,258 ft) = 22,516 ft
301
302 Chapter 11
The solid curve in Fig. 11-4(b) shows that the filter o f Fig. 11-4(a) not only has a steeper
roll-off after <oc than does Fig. 11-2(a), but also remains at 0 dB almost up to about
0.25 <oc. The phase angles for the circuit of Fig. 1 l-4(a) range from 0° at a> = 0 rad/s (dc
condition) to -1 8 0 ° as co approaches °o (infinity). Table 11-2 compares magnitude and
phase angle for the low-pass filters o f Figs. 11 -2(a) and ll-4 (a ) from 0.1 to 10<uc.
The next low-pass filter cascades the filter of Fig. 1 l-2(a) with the filter o f Fig. 11-
4(a) to form a roll-off o f —60 dB/decade. As will be shown, the resistors are the only val
ues that have to be calculated.
TABLE 11-2 MAGNITUDE AND PHASE ANGLE FOR FIGS. 11-2<a) AND 11-4(a)
IAcl | Phase angle (deg)
“ 20 dB/decade; “ 40 dB/decade;
0> Fig. 11-2(a) Fig. ll-4(a) Fig. 11-2(a) Fig. ll-4(a)
0.1<oc 1.0 1.0 -6 -8

0.25 (dc 0.97 0.998 -1 4 -21
0.5a>c 0.89 0.97 -2 7 -4 3
<*>c 0.707 0.707 -4 5 -9 0
2o)c 0.445 0.24 -6 3 -137
4a)c 0.25 0.053 -7 6 -143
I0o)c 0.1 0.01 -8 4 -172
11-4 - 60-DB/DECADE LOW-PASS BUTTERWORTH FILTER _______________________
11-4.1 Simplified Design Procedure
The low-pass filter o f Fig. 1 l-5(a) is built using one low-pass filter o f —40 dB/decade
cascaded with another o f —20 dB/decade to give an overall roll-off o f - 6 0 dB/decade.
The overall closed-loop gain A Cl is the gain o f the first filter times the gain o f the sec
ond filter, or
For a Butterworth filter, the magnitude o f A CL must be 0.707 at <oc. To guarantee that the
frequency response is flat in the passband, use the following design steps.
Design procedure
1. Choose the cutoff frequency, <oc or fc.
2. Pick C3; choose a convenient value between 0.001 and 0.1 /xF.
3. Make
—^ 3 and C2 — 2 C3 (11-5)
Active Filters 303
B#
4)
9
I
0.001
0.1 CDc C0c 10 G>c
(b) Plot of frequency response for the circuit of part (a).
FIGURE 11-5 Low-pass filter designed for a roll-off of —60 dB/decade and
corresponding frequency-response plot.
4. Calculate
R= ( 11-6)
0)c C3
5. Make Ri — R2 R3 — A.
6. Rfx = 2R and Rfl = R. For best results the value o f R should be between 10 and 100 kft.
If the value o f R is outside this range, you should go back and pick a new value of C3.
304 Chapter 11
Exam ple 11-5
For the — 60-dB/decade low-pass filter o f Fig. ll-5 (a ), determine the values o f Cj, C2,
and R for a cutoff frequency o f 1 kHz. Let C3 = 0.01 juF.
Ci = iC 3 = 1(0.01 /xF) = 0.005 /jF

and
C2 = 2C3 = 2(0.01 /xF) = 0.02 /xF

From Eq. (11-6),
R ~ (6.28)(1 X 103)(0.01 X 10-6 ) ~ 15,915 ^
Example 11-5 shows that the value o f R in Fig. ll-5 (a ) is different from those o f
Fig. 11-4(a), although the cutoff frequency is the same. This is necessary so that | A cl I
remains at 0 dB in the passband until the cutoff frequency is nearly reached; then \a Cl I =
0.707 at (oc.
The solid line in Fig. 1 l-5(b) is the actual plot o f the frequency response for Fig. 1 l-5(a).
The dashed curve in the vicinity shows the straight-line approximation. Table 11-3 com
pares the magnitudes o f ACl for the three low-pass filters presented in this chapter. Note
that the | ACL | for Fig. 1 l-5(a) remains quite close to 1 (0 dB) until the cutoff frequency,
<oc; then the steep roll-off occurs.
TABLE 11-3 \ A c l \ FOR THE LOW-PASS FILTERS OF FIGS. 11-2(a),

11-4(a), AND 11-5(a)
-2 0 dB/decade; -4 0 dB/decade; -6 0 dB/decade;

o> Fig. ll-2(a) Fig. ll-4(a) Fig. ll-5(a)
0.1 a>c 1.0 1.0 1.0

0.25 toc 0.97 0.998 0.999
0.5<ac 0.89 0.97 0.992
<»c 0.707 0.707 0.707
2o)c 0.445 0.24 0.124
4ioc 0.25 0.053 0.022
I0a>c 0.1 0.01 0.001
Active Filters 305
The phase angles for the low-pass filter of Fig. 1 l-5(a) range from 0° at <o = 0 (dB
condition) to —270° as <o approaches Table 11-4 compares the phase angles for the
three low-pass filters.
All digital signal processing systems use a low-pass filter at the front end to atten
uate frequencies above the Nyquist frequency, which is one-half the sampling rate.
TABLE 11-4 PHASE ANGLES FOR THE LOW-PASS FILTERS OF

FIGS. 11-2(a), 11-4(a), AND 11-5<a)
-2 0 dB/decade; -4 0 dB/decade; -6 0 dB/decade;

(1) Fig. 11-2(a) Fig. 11-4(a) Fig. 11-5(a)
0A<tic -6 ° -8 ° -12°
0.25<oc -4 ° -21° -29°
0.5 <oc -27° -43° -60°
*>c -45° -90° -135°
2a>c -63° -137° -210°
4 ojc -76° -143° -226°
I0<oc -84° -172° -256°
11-5 HIGH-PASS BUTTERWORTH FILTERS _________________________________________
11-5.1 Introduction
A high-pass filter is a circuit that attenuates all signals below a specified cutoff frequency
<t)c and passes all signals whose frequency is above the cutoff frequency. Thus a high-pass
filter performs the opposite function o f the low-pass filter.
Figure 11-6 is a plot o f the magnitude of the closed-loop gain versus <o for three
types o f Butterworth filters. The phase angle for a circuit o f 20 dB/decade is + 45° at <wc.
FIGURE 11-6 Comparison of frequency response for three high-pass

Butterworth filters.
306 Chapter 11
Phase angles at <oc increase by + 4 5 ° for each increase of 20 dB/decade. The phase an
gles for these three types o f high-pass filters are compared in Section 11-5.5.
In this book the design o f high-pass filters will be similar to that o f the low-pass fil
ters. In fact, the only difference will be the position o f the filtering capacitors and resistors.
11-5.2 20-dB/Decade Filter
Compare the high-pass filter o f Fig. ll-7 (a ) with the low-pass filter o f Fig. ll-2 (a ) and
note that C and R are interchanged. The feedback resistor Rf is included to minimize dc
offset. Since the op amp is connected as a unity-gain follower in Fig. 1 l-7(a), the output
voltage V0 equals the voltage across R and is expressed by
V- = W ( L rO XE- <>'-7>
Rf = R
(b) Frequency response for (a).
FIGURE 11-7 Basic high-pass filter, 20 dB/decade.

wnen <o approaches 0 rad/s in Eq. (11-7), V0 approaches 0 V. At high frequencies,
as a>approaches infinity, V0 equals Et. Since the circuit is not an ideal filter, the frequency
response is not ideal, as shown by Fig. 1 l-7(b). The solid line is the actual response; the
dashed lines show the straight-line approximation. The magnitude o f the closed-loop g a in
equals 0.707 when (oRC — 1. Therefore, the cutoff frequency a>c is given by
or
R <oc C 2 irfc C (11' 8b)
I k IS3S0D /Of solving for R and not CinEq. (ll-8b) is that it is easier to adjust R
than it is C. The steps needed in designing Fig. 11-7(a) are as M ow s:
Design procedure for 20-dB/decade high-pass

1. Choose the cutoff frequency, toc or f c.
2. Choose a convenient value o f C, usually between 0.001 and 0.1 jjF.
3. Calculate R from Eq. (ll-8 b ).
4. Choose Rf = R.
Exam ple 11-6
Calculate R in Fig. ll-7 (a ) if C = 0.002 /jF and f c = 10 kHz.
Solution From Eq. (1 l-8b),
= _____________ 1 .__________ = g
(6.28)(10 X 103)(0.002 X 10"6)
Exam ple 11-7
In Fig ll-7 (a ) if R = 22 kft and C = 0.01 /xF, calculate (a) cdc; (b) f c.
Solution (a) From Eq. (1 l-8a),
1
<*>c = = 4.54 krad/s
(22 X 103)(0.01 X 10“ 6)
(b)
f = “?£-= 4 54 * IQ3 = 724 Hz

Jc lir 6.28
The circuit o f Fig. 11-8(a) is to be designed as a high-pass Butterworth filter with a roll
o ff o f 40 dB/decade below the cutoff frequency, o>c. To satisfy the Butterworth criteria,
the frequency response must be 0.707 at o>c and be 0 dB in the pass band. These condi
tions will be met if the following design procedure is followed:

1. Choose a cutoff frequency, u)c or / c.
2. Let Ci = C2 = C and choose a convenient value.
(b) Frequency response for circuit of part (a).

FIGURE 11-8 Circuit and frequency response for a 40-dB/decade high-pass
Butterworth filter.
Active Filters 309
3. Calculate R\ from
1.414
= -L±7T (H -9 )
a>c C
4. Select
R2 = \Ri (11-10)
5. To minimize dc offset, let Rf = R\.
Exam ple 11-8
In Fig. 1 l-8(a), let C\ = C2 = 0.01 fiF. Calculate (a) R\ and (b) R2 for a cutoff frequency
o f 1 kHz.
Solution (a) From Eq. (11-9),

n _ 1.414 „„ ^
“ (6.28)(1 X 103)(0.01 X 10“6) “ 22-5
(b) R2 = ^(22.5 k fl) ■ 11.3 kfl.
Exam ple 11-9
Calculate (a) Ri and (b) R2 in Fig. 11 -8(a) for a cutoff frequency o f 80 krad/s. Ci = C2 =
125 pF.
Solution (a) From (11-9),
/?l ~ (80 X 103)(125 X 10“ 12) ~ 140
(b)
r 2 = i( i4 0 kft) = 70 m .
As with the low-pass filter o f Fig. 11-5, a high-pass filter o f + 6 0 dB/decade can be con
structed by cascading a +40-dB/decade filter with a +20-dB/decade filter. This circuit
(like the other high- and low-pass filters) is designed as a Butterworth filter to have the
frequency response in Fig. ll-9 (b ). The design steps for Fig. 11 -9(a) are as follows:
1. Choose the cutoff frequency, wc or fc.
2. Let Ci = C2 = C3 = C and choose a convenient value between 100 pF and 0.1 /iF.
40 dB/decade 20 dB/decade
1^1 lirl
E,
(b) Frequency-response for the circuit of part (a).

FIGURE 11-9 Circuit and frequency response for a 60-dB/decade Butterworth
high-pass filter.
3. Calculate R3 from
<*>n C
4. Select
Rx = 2 R 3 ( 11- 12)
310
312 Chapter 11
TABLE 11-5 COMPARISON OF \A c l \ FOR FIGS. 117(a), 118(a),

AND 11 -9(a)
20 dB/decade; 40 dB/decade; 60 dB/decade;

O) Fig. 1l-7(a) Fig. 11-8(a) Fig. 11-9(a)
0A(dc 0.1 0.01 0.001

0.25 o)c 0.25 0.053 0.022
0.5o)c 0.445 0.24 0.124
(Or 0.707 0.707 0.707
2a>c 0.89 0.97 0.992
4 (t)c 0.97 0.998 0.999
10o)c 1.0 1.0 1.0
TABLE 11-6 COMPARISON OF PHASE AN GLES FOR FIGS. 11-7(a),

11-8(a), AND 11 -9(a)
20 dB/decade; 40 dB/decade; 60 dB/decade;

a) Fig. 11-7(a) Fig. 1l-8(a) Fig. 11-9(a)
0.1 U)c 84° 172° 256°

0.25 76° 143° 226°
0.5wc 63° 137° 210°
Cl) 45° 90° 135°
2o,t. IT 43° 60°
4(oc 14° 21° 29°
10coc 6° 8° 12°
11-6 INTRODUCTION TO BANDPASS FILTERS ___________________________________________
11-6.1 Frequency Response
A bandpass filter is a frequency selector. It allow s one to select or pass only one p artic
ular band o f frequencies from all other frequencies that may be present in a circuit. Its
norm alized frequency response is show n in Fig. 11-10. T his type o f filter has a m axim um
gain at a resonant frequency f r. In this chapter all bandpass filters will have a gain o f 1.
or 0 dB at/,.. T here is one frequency b elow /,, w here the gain falls to 0.707. It is the low er
c u to ff frequency, f h At the higher cutofffrequency, f h the gain also equals 0.707, as in Fig.
11 - 1 0 .
Active Filters 313
Resonant frequency f r
1.0
— Bandwidth
A « = /* - //
0.707
-------- ^---------------- ► Frequency

f, fr
FIGURE 11-10 A bandpass filter has a maximum gain at resonant frequency

f r . The band of frequencies transmitted lies between / and//,.
11-6.2 Bandwidth
The range of frequencies betw een / and f h is called bandw idth Bf or
B = fh ~ ft (I I -14)
T he bandw idth is not exactly centered on the resonant frequency. (It is for this reason that
we use the historical nam e “ resonant frequency” rather than “center frequency” to de
s c rib e /..)
If you know the values for / and / /7, the resonant frequency can be found from
fr = 'S J J h (11-15)
If you know the resonant frequency, f r >and bandw idth, B, cutoff frequencies can be found
from
(I I-16a)
L = f i + B (I I -16b)
Example 11-12
A bandpass voice filter has low er and upper cutoff frequencies o f 300 and 3000 Hz. Find
(a) the bandw idth; (b) the resonant frequency.
314 Chapter 11
B = f h ~ f i = (3000 - 300) = 2700 Hz
(b) From Eq. (11-15),
f r = y /J J h = V (3 0 0 )(3 0 0 0 ) = 948.7 H z
Note: f r is alw ays below the center frequency o f (3000 + 300)/2 = 1650 Hz.
Example 11-13
A bandpass filter has a resonant frequency o f 950 Hz and a bandw idth o f 2700 Hz. Find its
low er and upper cutoff frequencies.
Solution F rom Eq. (11 -16a),
= 1650 - 1350 = 300 Hz
From Eq. ( 1 1- I 6b) t f h = 300 + 2700 = 3000 Hz.
11-6.3 Quality Factor
T he quality fa c to r Q is defined as the ratio o f resonant frequency to bandw idth, or
( 11- 1 7 )
Q is a m easure o f the bandpass filter's selectivity. A high Q indicates that a filter selects
a sm aller band of frequencies (m ore selective).
11-6.4 Narrowband and Wideband Filters
A w ideband filter has a bandw idth that is tw o or m ore tim es the resonant frequency. T hat
is, Q < 0.5 for w ideband filters. In general, w ideband filters are m ade by cascading a low-
pass filter circuit with a high-pass filter circuit. T his topic is covered in the next section,
A narrow band filter (Q > 0.5) can usually be m ade w ith a single stage. T his type o f fil
ter is presented in Section 11-8.
Example 11-14
Find the quality factor o f a voice filter that has a bandw idth o f 2700 H z and a resonant fre
quency o f 950 H z (see E xam ples 11-12 and 11-13).
Active Filters 315
£> = — = = 0.35
“ B 2700
This filter is classified as w ideband because Q < 0.5.
11-7 BASIC WIDEBAND FILTER
11-7.1 Cascading
W hen the output of one circuit is connected in series w ith the input o f a second circuit,
the process is called cascading gain stages. In Fig. 11-11, the first stage is a 3000-H z low-
pass filter (Section 11-3). Its output is connected to the input o f a 300-H z high-pass fil
ter (Section 11-5.3). The cascaded pair o f active filters now form a bandpass filter from
input Et to output Va. N ote that it m akes no difference if the high-pass is connected to the
low -pass, or vice versa. Note: Each op am p circuit in Fig. 11-11 has unity gain.
11-7.2 Wideband Filter Circuit
In general, a w ideband filter (Q < 0.5) is m ade by cascading a low- and a high-pass fil
ter (see Fig. 11-11). C utoff frequencies o f the low- and high-pass sections m ust n o t over
lap, and each m ust have the sam e passband gain. F urtherm ore, the low -pass filter's cu t
off frequency m ust be 10 or m ore tim es the high-pass filter’s cutoff frequency.
For cascaded low- and high-pass filters, the resulting w ideband filter will have the
follow ing characteristics:
1. T he low er cutoff frequency,//, will be determ ined only by the high-pass filter.
2. The high cutoff frequency,/*, will be set only by the low -pass filter.
3. G ain will be m axim um at resonant fre q u e n c y ,/,, and equal to the passband gain o f
either filter.
T hese principles are illustrated next.
11-7.3 Frequency Response
In Fig. 11-11 the frequency response o f a basic —40-dB /decade 3000-H z low -pass filter
is plotted as a dashed line. T he frequency response o f a 300-H z high-pass filter is plotted
as a solid line. T he 40-dB /decade roll-off o f the high-pass filter is seen to d e te r m in e /.
T he -4 0 -d B /d e c a d e roll-off of the low -pass s e ts /,. B oth roll-off curves m ake up the fre
quency response o f the bandpass filter, V0 versus / O bserve that the resonant, low, and
high c u to ff fre q u en c ies plus b an d w id th agree ex actly w ith the v alues ca lc u lated in
320 Chapter 11
11-9.2 Notch Filter Theory
As show n in Fig. 11-14, a notch filter is m ade by subtracting the output o f a bandpass fil
ter from the original signal. For frequencies in the notch filter’s passband, the output o f
the bandpass filter section approaches zero. T herefore, input £, is transm itted via adder
input resistor /?, to drive V0 to a value equal to —E h Thus VQ = in both low er and
upper passbands of the notch filte r
Suppose that the frequency of E-, is adjusted to resonant frequency f r o f the narrow
bandpass filter com ponent. (Note: f r o f the bandpass sets the notch frequency.) £, will exit
from the bandpass as — £, and then is inverted by R x and R to drive V0 to + E t. However,
E t is transm itted via R 2 to drive V0 to —E {. T hus VQ responds to both inputs o f the adder
and becom es Va = - E t = 0 V at f n
In practice, VG approaches zero only a t / r . T he depth o f the notch depends on how
closely the resistors and capacitors are m atched in the bandpass filter and ju d icio u s fine
adjustm ent o f resistor /?, at the inverting ad d er’s onput. T his procedure is explained in
Section 11-10.3.
R
AAAt
Fig. 11-12
Narrow
bandpass
filter
V
FIGURE 11-14 A notch filter is made by a circuit that subtracts the output
of a bandpass filter from the original signal.
11-10 120-HZ NOTCH FILTER ________________________________________________________________
11-10.1 Need for a Notch Filter
In applications w here low -level signals m ust be am plified, there may be present one or
m ore o f an assortm ent o f unw anted noise signals. E xam ples are 50-, 60-, or 400-H z fre
quencies from pow er lines, 120-Hz ripple from full-w ave rectifiers, or even higher fre
quencies from regulated sw itching-type pow er supplies or clock oscillators. If both sig
nals and a signal-frequency noise com ponent are passed through a notch filter, only the
desired signals will exit from the filter. T he noise frequency is “notched out.” As an ex
am ple, let us m ake a notch filter to elim inate 120-Hz hum.
Active Filters 321
11-10.2 Statement of the Problem
T h e p ro b lem is to m ake a n o tch filte r w ith a n o tch (re so n a n t) fre q u e n c y o f f r =

120 Hz. L et us select a stopband o f B = 12 Hz. T he gain o f the notch filter in the pass-
band w ill be unity (0 dB ) so that the desired sig n als w ill be tran sm itted w ith o u t at
tenuations. We use Eq. (1 1-17) to d eterm in e a value for Q th at is req u ired by the notch
filter:
This high value of Q m eans that (1) the notch and com ponent bandpass filter w ill have
narrow bands with very sharp frequency -resp o n se curves, and (2) the bandw idth is es
sentially centered on the resonant frequency. A ccordingly, this filter will transm it all fre
quencies from 0 to (120 - 6) = 114 Hz and all frequencies above (120 + 6) = 126 Hz.
The notch filter will stop all frequencies betw een 114 and 126 Hz.
11-10.3 Procedure to Make a Notch Filter
A notch filter is m ade in two steps:
1. M ake a bandpass filter that has the sam e resonant frequency, bandw idth, and conse
quently Q as the notch filter.
2. C o n n e ct the in v e rtin g ad d e r o f Fig. 11-15 by se le c tin g eq u al re sis to rs for R .
U sually, R — 10 k fl. (A practical fine-tuning p ro ced u re is p resented in the next
section.)
11-10.4 Bandpass Filter Components
T he first step in m aking a 120-Hz notch filter is best illustrated by an exam ple (see Fig.
11-15).
D esign E x a m p le 11-17
D esign a bandpass filter w ith a resonant frequency o f f r = 120 Hz and a bandw idth o f
12 H z so that 2 = 1 0 . T hus gain of the bandpass section will be 1 at f r and approach zero
at the output o f the notch labeled V0.
Solution C hoose C = 0.33 /xF. From Eq. (11-18a),
0.1591
= 40.2 k f l
(12)(0.33 X 10“ 6)
Active Filters 323
11-11.1 Low-Pass Filter
R efer to Fig. ll- 4 ( a ) and create the PSpice m odel o f the circuit using a 741 op am p if
you are using the evaluation softw are package. The input voltage source will be VAC and
w ill be set for a 1-V m agnitude. We w ant a plot o f V0 versus frequency. To begin, place
the follow ing parts in the w ork area.
Qraw => get New Part
Part Number Library

= > VAC 1 source.sib
= > VDC 2 source^lb
= > R 4 analog.slb
= > C 2 analog.slb
= > GLOBAL 4 port.slb
= > AGND 5 porLslb
Note: We are using VAC as the input source instead o f VSIN as we have in previ
ous chapters. The VAC sym bol requires only that m agnitude and phase be set. T he fre
quency range will be set in the A nalysis Setup m enu. A rrange the parts as show n in Fig.
11-4(a). C hange the attributes o f the parts to those values given in Exam ple 11-4. Set up
the VAC sine w ave attributes by d o u b le-click in g the sym bol; in the p o p-up w indow
change phase and m agnitude.
ACPHASE = > 0 = > Save Attr

ACMAG = > IV = > Save Attr —> Change Display = > Both name and value
D ouble-click on the lead from the output term inal of the op am p and label it Vo
(see Fig. 11-16). To obtain a plot of V0 versus frequency, we m ust initialize the AC Sw eep
m enu.
Analysis = > Setup = > Enable AC Sweep

Open AC Sweep = > Decade
=> Pts/Decade = > 1 0
=> Start Freq = > 10Hz
=> End Freq = > 10kHz
In the Probe window, we need to select both P lot and Trace options from the m enu bar.
Plot = > Y Axis Settings = > Scale = > Log

Trace = > Add = > V[Vo]

A ctive Filters 325
11-11.2 High-Pass Filter
T he procedure for m odeling and sim ulating a high-pass filter is sim ilar to that for the low-
pass filter previously described. R efer to Fig. ll- 8 ( a ) and create the PSpice m odel o f the
circuit using a 741 op amp. T he input voltage source w ill be VAC and will be set for a
1-V m agnitude. O btain a plot o f V0 versus frequency. To begin, place the follow ing parts
in the w ork area.
Part Number Library
=> uA741 1 evalslb

=> VAC I source.slb
=> VDC 2 source.slb
=> R 4 analog.slb
=> C 2 analog.s!b
=> GLOBAL 4 portslb
=> AGND 5 port.slb
As previously m entioned w e are using VAC as the input source instead o f VSIN so that
we may vary frequency through a range, because the VAC sym bol requires only m agni
tude and phase to be set. T he frequency range is set in the A nalysis Setup m enu. A rrange
the parts as show n in Fig. 1 l-8(a). Change the attributes o f the parts to those values given
in Exam ple 11-8. Set up the VAC sine wave attributes by double-clicking the sym bol; in
the pop-up w indow change phase and m agnitude.
ACPHASE = > 0 = > Save Attr

ACMAG = > IV = > Save Attr —> Change Display —> Both name and value
D ouble-click on the lead from the output term inal o f the op am p and label it Vo
(see Fig. 11-18). To obtain a plot o f V0 versus frequency, we m ust initialize the AC Sw eep
menu.
Analysis = > Setup = > Enable AC Sweep

Open AC Sweep = > Decade
=> Pts/Decade = > 1 0
=> Start Freq = > 100Hz
=> End Freq = > 100kHz

In the Probe window, we need to select both Plot and T race options from the m enu bar.
Plot = > Y Axis Settings = > Scale = > Log

Label the plots and obtain a printout as shown in Fig. 11-19.

328 Chapter 11
PROBLEMS _____________________________________________________________________
11-1. List the four types of filters.
11-2. What type of filter has a constant output voltage from dc up to the cutoff frequency?
11-3. What is a filter called that passes a band of frequencies while attenuating all frequencies
outside the band?
11-4. In Fig. 11-2(a), if R = 100 kO and C = 0.02 /zF, what is the cutoff frequency?
11-5. The low-pass filter of Fig. 11 -2(a) is to be designed for a cutoff frequency of 4.5 kHz. If
C = 0.005 /aF, calculate R.
11-6. Calculate the cutoff frequency for each value of C in Fig. PI 1-6.
Rf = 10 kQ
AAAr
FIG U RE PI 1-6
11-7. What are the two characteristics of a Butterworth filter?

11-8. Design a -40-dB /decade low-pass filter at a cutoff frequency of 10 krad/s. Let C | =
0.02 fxF.
11-9. In Fig. 11-4(a), if = R2 = 10 kll, C} = 0.01 /jlF, and C2 = 0.002 /jlF, calculate the cut
off frequency f c.
11-10. Calculate (a) /?3, (b) Ru and (c) R2 in Fig. 1 l-5(a) for a cutoff frequency of 10 krad/s. Let
C3 = 0.005 mF.
11-11. If R y = R2 = R3 = 20 kfl, C, = 0.002 fjuF, C2 = 0.008 ^ and C3 = 0.004 ^ in Fig. 11-
5(a), determine the cutoff frequency (oc.
11-12. In Fig. 11-5(a), C{ = 0.01 /xF, C2 = 0.04 fjuF, and C3 = 0.02 y,F. Calculate R for a cutoff
frequency of 1 kHz.
11-13. Calculate R in Fig. 1 l-7(a) if C = 0.04 fjuF a n d /c = 500 Hz.
Active Filters 329
11-14. In Fig. 1 l-7(a) calculate (a) a)c and (b) f c if R = 10 k ft and C = 0.01 /xF
11-15. Design a 40-dB/decade high-pass filter for o)c = 5 krad/s. G = C2 = 0.02 jjlF.
11-16. Calculate (a) R ] and (b) /?2 in Fig. 11 -8(a) for a cutoff frequency of 40 krad/s. CA = C2 =
250 pF.
11-17. For Fig. I I-9(a), let C{ = C2 = C3 = 0.05 /xF. Determine (a) /?3, (b) /?,, and (c) R2 for a
cutoff frequency of 500 Hz.
11-18. The circuit of Fig. 11-9(a) is designed with thevalues CA = C2 = C3 = 400 pF, =
100 kH, /?2 = 25 kH, and /?3 = 50 kfi. Calculate the cutoff frequency/,.
11-19. Find the (a) bandwidth, (b) resonant frequency, and (c) quality factor of a bandpass filter
with lower and upper cutoff frequencies of 55 and 65 Hz.
11-20. A bandpass filter has a resonant frequency of 1000 Hz and a bandwidth of 2500Hz.Find
the lower and upper cutoff frequencies.
11-21. Use the capacitor and resistor values of the high-pass filter in Fig. 11-11 to prove f c =
3000 Hz.
11-22. Use the capacitor and resistor values of the high-pass filter in Fig. 11-11 to prove that
f c = 300 Hz.
11-23. Find Q for the bandpass filter of Fig. 11-11.
11-24. Design a narrow bandpass filter using one op amp.The resonantfrequency is 128Hz and
Q = 1.5. Select C = 0.1 /jlF in Fig. 10-12.
11-25. (a) How would you convert the bandpass filter of Problem 11-24 into a notchfilter with the
same resonant frequency and Q1 (b) Calculate / and f h for the notch filter.
CHAPTER 12
Modulating, Demodulating,
and Frequency Changing
with the Multiplier
LEARNING O B J E C T I V E S _____________________________________________________
U pon com pletion o f this chapter on m ultiplier ICs, you will be able to:
• W rite the output-input equation of a m ultiplier IC and state the value o f its scale factor.
• M ultiply tw o dc voltages or divide one dc voltage by another.
• Square the value of a dc voltage or take its square root.
• D ouble the frequency o f any sine wave.
• M easure the phase angle betw een tw o sine w aves o f equal frequency.
• Show that am plitude m odulation is actually a m ultiplication process.
• M ultiply a carrier sine w ave by a m odulating sine wave and express the output voltage
either by a product term or by a term containing sum and difference frequencies.
• C alculate the am plitude and frequency o f each output frequency term.
• M ake either a balanced am plitude m odulator or a standard am plitude m odulator.
• Show how a m ultiplier can be used to shift frequencies.
Modulating, Demodulating, and Frequency Changing with the Multiplier 331
12-0 INTRODUCTION _________________________________________________________________
A nalog m ultipliers are arrangem ents o f op am ps and other circuit elem ents available as
an integrated circuit. M ultipliers are easy to use; som e o f their applications are (1) m ea
surem ent o f power, (2) frequency doubling and shifting, (3) detecting phase-angle differ
ence betw een two signals o f equal frequency, (4) m ultiplying tw o signals, (5) dividing
one signal by another, (6) taking the square root o f a signal, (7) squaring a signal, and (8)
designing nonlinear signal conditioning circuits. A nother use for m ultipliers is to dem on
strate the principles o f am plitude m odulation and dem odulation. T he schem atic o f an
A D 633 m ultiplier is show n in Fig. 12-l(a). The device is a four-quadrant analog m ulti
plier. It has high input im pedance, w hich makes signal source loading negligible. Pow er
supply voltages can range from ± 8 V to ± 1 8 V. No external com ponents or user calibra
tion are required. T he output voltage is a scaled version o f the x and y inputs. T he scale
fa c to r is explained in Section 12-1.
8-Pin plastic DIP (N) package

W
FIG U RE 12-1 Introduction to the

AD633JN multiplier.
12-1 MULTIPLYING DC VOLTAGES __________________________________________________
12-1.1 Multiplier Scale Factor
T he 8-pin m ini-D IP housing and internal schem atic o f the A D 633 m ultiplier is show n in
Fig. 12-1(a). In general term s, the output voltage V0 is expressed by,
V0 = — ~ ~ + ; (12-1)
w here V0 is the output voltage m easured at term inal W w ith respect to ground. T he fac
tor of is called a scale fa c to r and is typical o f m ultipliers, because m ultipliers are d e
signed for the sam e type o f pow er supplies used for op am ps, nam ely ± 1 5 V. For best re
sults, the voltages applied to either x or y inputs should not exceed + 1 0 V or —10 V w ith
respect to ground. T his ± 1 0 -V lim it also holds for the output, so the scale factor is u su
ally the reciprocal o f the voltage lim it, or 1/10 V. If both input voltages are at their posi
tive lim its o f + 1 0 V, the output w ill be at its positive lim it o f 10 V.
332 Chapter 12
12-1.2 Multiplier Quadrants
M ultipliers are classified by quadrants; for exam ple, there are one-quadrant, tw o-quadrant,
and four-quadrant m ultipliers. T he classification is explained in tw o w ays in Fig. 12-2. In
Fig. 12-2(a), the input voltages can have four possible polarity com binations. C onsider
*2 ~ )>2 = z = 0 , then both x v and y x are positive and operation is in quadrant 1, since x,
is the horizontal and y x the vertical axis. If x x is positive and y ] is negative, quadrant 4 o p
eration results, and so forth.
Example 12-1
Find V0 for the follow ing com bination o f inputs if x 2 = y2 = z — 0: (a) x x = 10 V, y x =

10 V; ( b )x , - - 1 0 V ,y, = 10 V; (c) jca = 10 V, y x - - 1 0 V; (d) jc, = - 1 0 V, y x = - 1 0 V.
Solution From Eq. (1 2 -lb ),
(a) VB = ( 1° X 10) = 10 V, quadrant 1
(b) V0 = ( - 1|q ^ 1Q) = - 1 0 V, quadrant 2
(c) V0 = ^ = - 1 0 V, quadrant 4
(d) V0 = —-— ^ = 10 V, quadrant 3
In Fig. 12-2(b), V0 is plotted on the vertical axis and x, on the horizontal axis. If
w e apply 10 V to the y input and vary jc from - 1 0 V to + 1 0 V, we plot the line ab, la
beled y = 10 V. If y x is changed to - 1 0 V, the line cdy labeled 3^1 = —10 V, results. T hese
lines can be seen on an oscilloscope by connecting V0 o f the m ultiplier to the y x input o f
the oscilloscope and X\ of the m ultiplier to the + x x input o f the oscilloscope. F or accu
racy, V0 should be 0 V w hen either m ultiplier input is 0 V. M ultiplier errors are prim ar
ily due to input and output offsets, scale factor error, and/or nonlinearity o f the core m ul
tiplying unit. T hese errors are only fractions o f a percen t error, and if they need to be
elim inated refer to the m anufacturer’s data sheet.
12-4 PHASE-ANGLE DETECTION ___________________________________________________________
12-4.1 Basic Theory
If two sine w aves o f the sam e frequency are applied to the m ultiplier inputs in Fig. 12-
5(a), the output voltage V0 has a dc voltage com ponent and an ac com ponent w hose fre
quency is tw ice that o f the input frequency. This conclusion was developed in Section 12
3.2. T he dc voltage is actually proportional to the difference in phase angle 0 betw een EX]
and Eyx. For exam ple, in Fig. 12-5, 0 = 0°, because there was no phase difference be
tw een EXi and Eyr Figure 12-5(b) shows two sine waves o f identical frequency but a phase
difference o f 90°; therefore, 0 = 90°.
If one input sine w ave differs in phase angle from the other, it is possible to calcu
late or m easure the phase-angle difference from the dc voltage com ponent in VD. This dc
com ponent VQ dc is given by*
( 12-4a)
w here Exp and Eyp are peak am plitudes o f EX] and Eyr For exam ple, if Exp = 10 V, Eyp =
5 V, and they are in p h a se, then Va dc would indicate 2.5 V on a dc voltm eter. This volt
m eter point w ould be m arked as a phase angle o f 0° (cos 0° = 1). If 0 = 45° (cos 45°
= 0.707), the dc m eter w ould read 0.707 X 2.5 V — 1.75 V. O ur dc voltm eter can be cal
ibrated as a phase-angle m eter 0° at 2.5 V, 45° at 1.75 V, and 90° at 0 V.
E quation (12-4a) m ay also be expressed by*
( 12-4b)
•xp L *yp
If we could arrange for the product Exp Eyp to equal 20, we could use a 0 -to -l-V dc
voltm eter to read cos 0 directly from the m eter face and calibrate the m eter face in d e
grees from a cosine table. T hat is, Eq. (12-4b) reduces to
V0 dc = cos 0 for Exp = Eyp = 4.47 V (] 2-4c)
T his point is explored further in Section 12-4.2.
^Trigonometric identity:
sin A sin B = {[cos (A - B) - cos (A + £)]
For equal frequencies, different phase angle:
A = l u f i + 6 for E„ B = 27rft for Ey
Therefore,
[sin (27r/r + 0)][sin 2irft] = {[cos 0 — cos (477/if + 0)J
= y(dc - double frequency term)

+ 15 V
x2 = y2 = z = 0
(a) Phase-angle m easurem ent.
(b) Input voltage for 0 = 90°.
VQ— -s in 2rc2000/
FIGURE 12-5 Multiplier used to measure the phase-angle difference between

two equal frequencies.
340 Chapter 12
0 (deg) cos 0 V„dc(V)
±30 0.866 0.866

±45 0.707 0707
±60 0.500 0.500
± 0 1.000 1.000
±90 0.000 0.000
(The last tw o rows of this table com e from E xam ples 12-5 and 12-6.)
T he 0 -to -l-V voltm eter scale can now be calibrated in degrees, 0 V for a 90° phase
angle and 1.0 V for 0° phase angle. A t 0.866 V, 0 = 30°, and so forth. T he phase-angle
m eter does not indicate w hether 0 is a leading or lagging phase angle but only the phase
difference betw een EXx and Eyr
12-4.3 Phase Angles Greater Than ±90°
T he cosine o f phase angles greater than + 9 0 ° or - 9 0 ° is a negative value. T herefore, V0

will be negative. This extends the capability o f the phase angle m eter in E xam ple 12-7.
Example 12-8
C alculate VQ dc for phase angles o f (a) 0 = ± 9 0 ° ; (b) 0 = ± 1 2 0 °; (c) 0 = ± 135°; (d) 6

± 1 5 0 °; (e) 0 = ± 1 8 0 °.
Solution U sing Eq. (12-4a) and tabulating results, we have
0
O
OO
o
+1
±90° ± 120° ± 135° ±150°
vodc 0V - 0 .5 V - 0 .7 0 V - 0 .8 6 6 V -1 V
F rom the results o f E xam ples 12-7 and 12-8, a ± 1-V voltm eter can be calibrated to
read from 0 to ± 1 8 0 °.
72-5 ANALOG DIVIDER ______________________________________________________________________
A n analog divider gives the ratio o f two signals or provides gain control. It is constructed
as show n in Fig. 12-6 by inserting a m ultiplier in the feedback loop o f an op am p. Since
the op a m p ’s ( - ) input draw s negligible current, the sam e value o f current I flow s through
resistors R. Therefore, the output voltage o f the m ultiplier Vm is equal in m agnitude but
opposite in polarity (with respect to ground) to E in or
£ in = - V m ( 12-5a)
B ut Vm is also equal to one-tenth (scale factor) o f the product o f input Ex and output of
the op am p V0. Substituting for Vm yields
V E
3 " = -“ U 2-5b)
S olving for Voy we obtain
E quation (12-5c) show s that the d iv id e r's o u tp u t VQ is p ro p o rtio n al to the ratio

o f inputs £ in and Ex. Ex should never be allow ed to go to 0 V or to a negative voltage,
b ecause the op am p w ill saturate. E m can be positive, negative, or 0 V. N ote th at the
d ivider can be view ed as a voltage gain 10!EX acting on £ in. So if Ex is ch an g ed , the
gain w ill change. T his voltage control o f the gain is useful in au to m atic g ain -co n tro l
circuits.
342 Chapter 12
12-6 FINDING SQ U A RE ROOTS ____________________________________________________________
A divider can be m ade to find square roots by connecting both inputs o f the m ultiplier to
the output o f the op am p (see Fig. 12-7). E quation (l2 -5 a ) also pertains to Fig. 12-7. But
now Vm is one-tenth (scale factor) o f V0 X V0 or
V2
~E-m = V m = - £ ( 12-6a)
Solving for V0 (elim inate V - T ) yields
Vc = V l O l E j (12-6b)
Equation (12-6b) states that V0 equals the square root o f 10 tim es the m agnitude o f £ in.
E in m ust be a negative voltage, or else the op am p saturates. T he range o f E m is betw een
— 1 and —10 V. Voltages sm aller than —1 V w ill cause inaccuracies. T he diode prevents
( - ) saturation for positive E m. If E [n has positive values, reverse the diode.
Square root finder
FIGURE 12-7 Square rooting with an op amp and a multiplier (x2 = y i

z = 0).
12-7 INTRODUCTION TO AMPLITUDE MODULATION __________________________________
12-7.1 Need for Amplitude Modulation
L ow -frequency audio or data signals cannot be transm itted from antennas o f reasonable
size. A udio signals can be transm itted by changing or m odulating som e characteristic o f
a higher-frequency carrier wave. If the am plitude o f the carrier w ave is changed in pro-
Input =
tem perature 115 to output
0 to 50 °C 323 (iA Current-to- 0 to 5 V
■N
■> W
W’ — Transducer w voltage
W W C
converter
(a) Block diagram of a temperature-

to-voltage converter.
0 10 20 30 40 50
Tem perature (°C)
(b) In put-output characteristic of a
tem perature-to-voltage converter.
FIG U RE 2-15 An example of how room or a process temperature is mea

sured electronically.
A ssum e that you have available a circu it that gives 0 to 5 V out fo r a ro o m -tem -
p erature change o f 0° to 50°C (see Fig. 2-15). T he o u tput, Vtemp, can now be used as
a m easu rem en t o f tem perature, or it can be used to co n tro l tem p eratu re. S u p p o se that
you w ant to send this te m p eratu re in fo rm atio n to a co m p u ter so th at the co m p u te r
could m onitor, control, or chan g e room tem p eratu re. A voltag e-lev el d etec to r can a c
com plish this task. To u nderstand how this can be done, w e p resen t a p u lse -w id th m o d
ula to r using the L M 339 com parator.
2-8.2 Pulse-Width Modulator; Noninverting

T he L M 339 co m p arato r in Fig. 2 - 16(a) co m p ares tw o input v o ltag es, Ec and Vtemp.
[Figure 2-16(b) is sim ilar to Fig. 2 - 12(a).] A saw tooth wave, Ec, w ith constant frequency
is connected to the ( - ) input, it is called a carrier w ave. Vlemp is a tem perature-controlled
voltage. Its rate o f change must be m uch less than that o f E c. In this design, Vtemp is the
signal from the tem perature transducer. It can be treated as a variable reference voltage
when Fig. 2 - 16(a) is com pared to Fig. 2 - 12(a) or Fig. 2-5(b).
In this circuit the input signal is defined as Viemp. The output is defined as the high
tim e, T h o f Va. In Fig. 2 - 16(b), the output stays high for 2 ms w hen Vtemp = 1 V.If Vtemp
increases to 4 V, high tim e TH increases to 8 ms as in Fig. 2 - 16(c).
(a) N o n i n v e r t i n g p u l s e - w i d t h - m o d u l a t o r circuit.
( t » ^ m P = ' V , r „ = 2 m s. (c ) ^lemp = 4 V , = 8 ms.
r H= r -
(d) Input voltage Viemv vs. output high time Th -
FIGURE 2-16 V,emp is defined as the input signal in (a). As V'(emp increases from 0 to 5 V, the
high time of output voltage V0 increases from 0 to 10 ms. The circuit is called a noninverting pulse-
width modulator
O peration of the circuit is sum m arized by the in p u t-o u tp u t characteristics in Fig. 2-

16(d). T he w idth of output pulse TH is changed (m odulated) by Vtemp. T he constant p e
riod o f the output wave is set by Ec. Thus Ec carries the inform ation co n ta in ed in Vtemp.
V0 is then said to be a pulse-w idth-m odulated wave. The in p u t-o u tp u t equation is
output T h = (Vêrop) - J — (2-3)
w here T = period of saw tooth carrier wave

E cm = m axim um peak voltage o f a saw tooth carrier
Exam ple 2-2 shows that the pulse-w idth m odulator can also be called a duty-cycle
controller.
Example 2-2
A 10-V, 50-H z saw tooth wave is pulse-w idth m odulated by a 4-V signal. Find the o u tp u t’s
(a) high tim e; (b) duty cycle.
S o lu tio n Period T is found from the reciprocal o f the frequency:
T = ~ = = 20 ms
f 50 Hz
(a) From Eq. (2-3),

20 ms
T„ = (4 V) = o ms
10 V
(b) D uty cycle is defined as the ratio o f high tim e to the period and is expressed in
percent:
duty cycle = X 100 (2-4)
8 ms
X 100
20 ms
Thus the output stays high for 40% o f each signal.
2-8.3 Inverting and Noninverting Pulse- Width Modulators
F igure 2-17 show s the difference betw een noninverting and inverting pulse-w idth m odu
lators. If signal Vlemp is applied to the ( + ) input, the circuit is defined as noninverting [see
Figs. 2 - 17(a), (b), and (c)]. T he slope of TH versus Vlemp rises to the right and is p o sitive
or noninverting.
(a) N o n i n v e r t i n g P W M . (d) Inve rting P W M .
(A )°3
(A) °A
(b) Input and output wave forms for Vref = I V. (e) Input and output wave forms for Vref = I V.
lemp V v t
(c ) Output T h vs. \/[emp 7 = 1 0 ms. (f) Output T h vs. Vle[np T = 10 ms.
FIGURE 2-17 Output high time increases as input Vlemp increases in a noninverting pulse-width modulator
[see (a), (b), and (c)]. Output high time decreases as Vicmp increases in an inverting pulse-width modulator
Vtemp is applied to the ( - ) input in Fig. 2 - 17(d). As Vtemp increases, TH decreases,

The slope of TH versus Vternp is show n in Fig. 2 -1 7(f) and is negative. T he inverting p er
form ance equation is
(2-5)
Example 2-3
C alculate the output high tim e if Vternp = 4 V in Fig. 2 - 17(d).

4 V
2-9 A PULSE-WIDTH MODULATOR INTERFACE

TO A MICROCONTROLLER __________________
Either circuit of Fig. 2-17 can be used to transm it tem perature inform ation as a pulse-w idth
m odulated signal to a com puter. The advantage o f such an analog interface circuit is to
elim inate a voltage drop over distances o f several hundred feet. Thus the pulse-w idth m od
ulator can interface an analog signal with an input port o f a m icrocontroller (see Fig. 2
18). T he tem perature is first converted to a voltage by the sensor. A noninverting pulse-
w idth m odulator then converts this analog voltage to an output that is digital in nature; that
is, its output is either high or low and the high tim e is directly proportional to tem perature.
^T em p erature 20° C ^ ( ^ 2 V = Vltmp ^ TH = 40 ms ^
Noninverting Internal
w Tem perature-to-
W pulse- counter of a
voltage converter
width m odulator m icrocontroller
FIGURE 2-18 Block diagram of a computerized temperature measurement.
T he com puter program m er can perform the analog-to-digital conversion o f the high
tim e to a digital code. T his may be done by using a 1-ms tim ing loop and counting the
num ber o f tim es that the loop is executed. A nother and m ore efficient m ethod is to use
the internal counter designed into m ost m icrocontrollers. T he O-to-5-V transition o f V0 is
38 Chapter 2
used to start the m icrocontroller’s counter and the 5-to-O-V transition stops the co u n ter
T he count, w hich is autom atically stored in one o f the m icro co n tro ller’s internal registers,
is directly proportional to the tem perature.
2-10 OP AM P COMPARATOR CIRCUIT SIMULATION
2-10.1 Introduction
PSpice is a softw are package for analog and digital design analysis. S tudents w ho are
studying op am ps usually have aLready used PSpice in previous courses, so all the PSpice
fundam entals are not introduced; however, enough introduction steps are included th ro u g h
out this text to allow first-tim e users to create and analyze their circuits.
2-10.2 Creating, Initializing, and Simulating a Circuit
L et us create and analyze the noninverting positive-level detector circuit show n in Fig.
2-5(a). We will use a sine wave for the input signal because it is easy to obtain from the
basic parts list. (Note: T he parts list does not contain a triangular w aveform although one
can be created, w hich we w ill do in a later chapter.) To create and sim ulate Fig. 2-5(a),
open a new w orksheet either by clicking on File = > New, or if the PSpice w indow is not
open, double-click on the Schem atics icon in the window, [f necessary, enlarge the w ork
area to fill the entire screen.
The basic parts list browser may be obtained by clicking Draw from the Menu bar and
then clicking Get New Part from the drop-down menu. These steps will be represented by
A shortcut for obtaining the parts list is to click the icon on the toolbar. (Note: T he
icon sym bol is different for different versions o f PSpice.) E ith er m ethod produces a p o p
up m enu that contains the Parts Browser’s basic list. Click Advanced > > and the b a
sic m enu expands to include a w indow to show you the part before you place it in the
w ork area. O ther libraries o f parts can be obtained by clicking on the Libraries button.
The general guidelines for creating and sim ulating a circuit in P Spice are:
1. O pen a new work area.

2. O btain each part from the parts list and place it in the w ork area. T hen close the
parts list.
3. A rrange the parts the way they appear in the circuit schem atic.
4. Interconnect the parts.
5. C hange any attribute value(s) for a part if necessary.
6. Initialize setup param eters— Analysis = > Setup.
7. Initialize probe setup if you w ant a plot— Analysis = > Probe Setup
8. Save the schem atic as a file with the .SCH extension.
9. E nsure there are no w iring errors— Analysis = > Create Netlist.
10. E xecute the program to observe the results— Analysis = > Simulate.
Let us create the noninverting positive-level detector circuit o f Fig. 2-5(a) by call
ing up the follow ing parts and placing them in the w ork area. It is easier if you get all the
parts at once and place them in the right section o f the w ork area, close the parts list, and
then arrange the parts as they appear in the circuit schem atic. For this application, w e will
use three dc supplies for + V, - V, and Vref.
Part Num ber Version 6.2 Library
=> UA741 pins 1 and 5 are shown but not used eval. sib
=> VDC place three for + V, - Vr and Vre( source.slb
=> VSIN sine wave source.slb
=> GLOBAL place six portslb
=> AGND analog ground, place five port.slb
=> R resistor for RL analog.slb
Close the parts list and arrange the parts as in Fig. 2-5(a). (Note: T he op am p PSpice
m odel com es from the parts list w ith the inverting term inal at the bottom and the nonin
verting term inal at the top o f the diagram . For now w e will leave it w ith this orientation.
T he term inals can be sw itched if the op am p is rotated tw ice and then flipped. In this new
orientation, however, + V is at the bottom and - V is at the top.) To interconnect the parts,
click D ra w = > W ire or click the thin Pencil icon in the toolbar. F igure 2-19 show s how
the parts can be interconnected.
ref
+V
v2 — V4
6V - 15V - 15V
+V
VO Vo Vo
. 5
VampJ = 10 V
Freq = 100 Hz Rl =
uA741 10 k
V
FIG U RE 2-19 PSpice model of a noninverting comparator circuit.
The parts in this circuit that require setting new values (attributes) are the three dc
supply voltages; the six globals; the sine w ave’s am plitude, frequency, and offset; and the
value o f R l . C hanging a p art’s attributes is done by first double-clicking on the part or
value to be changed and then entering the new value. D ouble-clicking highlights the part
or value in red and then opens an attribute box that allow s you to en ter the new value.
40 Chapter 2
O ne at a tim e, double-click on 0 V and set the voltages at the supplies as:
+ V = 15 V
—V = 15 V (N ote the orientation o f this supply.)
V ref = 6 V
O ne at a tim e, set the six G L O B A L labels as:
+ V — at pin 7 of the op am p and that connected to + 1 5 V

—V— at pin 4 of the op am p and that connected to —15 V
V ref — at pin 2 o f the op am p and the source used for Vref.
Sim ilarly the label o f the resistor and its value can be changed to R L and 10 k fl, re
spectively. To change the attributes of the input sine-w ave signal, double-click the sym
bol and a VS1N attribute box appears. O ne at a time, change each attribute by dou b le
clicking the attribute and setting the new value in the window. For this circuit, am plitude,
frequency, and offset values have to be changed as show n:
AM PL = to 10 V = > Save Attr = > Change Display = > Both name and value
FREQ - to 100 Hz = > Save Attr = > Change Display = > Both name and value
VOFF = to O V = > Save Attr (not necessary to change display for this application)
In this application, we w ant a plot o f E n Vref, and VQ versus tim e sim ilar to w hat is
show n in Fig. 2-5(a). In order to do this, we first m ust add the location o f Et and VDto
the op a m p ’s inverting and output term inals, respectively. T he location o f Vref is already
show n on the circuit diagram . This step is done by double-clicking the “w ire” connection
at the point o f interest and entering the label in the w indow o f the pop-up box. Figure 2
19 show s the com pleted schem atic ready for analysis. To obtain these plots, open Analysis
= > Probe Setup and click A u to m a tic ally Run P robe A fter S im u la tio n . N ow open
Analysis = > Setup and click the box next to Transient. An x appears indicating it has
been selected. Now click on Transient and set Print Step to 0.05 ms and Final T im e to
20 ms. This will allow P robe to display tw o com plete cycles o f a 100-H z sine wave.
Save the file by File = > Save or by clicking the Disk icon in the toolbar. You may
use any file nam e but be sure to use extension .SCH. A check o f the w iring corrections
is done by creating a netlist— Analysis = > Create Netlist. A w arning appears if there
are any w iring errors. C lick O K and a list o f the error location(s) is obtained. If there are
no errors, then the circuit is ready to run the sim ulation program . T his step is done by
Analysis = > Simulate or using the hot key FI 1. T he Probe window (a b lack screen) ap
pears. To plot the graphs, use Trace = > Add and click V[Ei], V[Vref], and V[Vo] and
then OK. T he three w aveform s should now be plotted as show n in Fig. 2-20. To add la
bels to the graphs, use Tools = > Label = > Text and a text box appears. Type in the la
bel you w ish to place on the graph and then click OK. Use the m ouse to place the label
w here you w ant it and repeat the procedure for any new labels. To add arrow s, use Tools
= > Label = > Arrow. Use the m ouse to place the tail o f the arrow at the starting point
and draw out the arrow. C lick the left m ouse button to stop and the com pleted arrow is
draw n.
42 Chapter 2
2-7. Ej is applied to the ( - ) input and ground to the ( + ) input of a 741 in Fig. P2-7. Sketch ac
curately (a) Va vs. / and (b) V0 vs. E-r
FIGURE P2-7
2-8. Swap the input connections to E, and ground in Fig. P2-7. Sketch (a) Vn vs. t and (b) V0 vs.
E,
2-9. Refer to Problems 2-7 and 2-8. Which circuit is the noninverting zero-crossing detector, and
which is the inverting zero-crossing detector?
2-10. To which input would you connect a reference voltage to make an inverting level detector?
2-11. You need a 741 noninverting voltage-level detector, (a) Will the output be at +V sa, or ~ V sM
when the signal voltage is above the reference voltage? (b) To which input do you connect
the signal?
2-12. Design a reference voltage that can be varied from 0 to - 5 V. Assume that the negative sup
ply voltage is - 1 5 V.
2-13. Design a 0 to +50 mV adjustable reference voltage. Derive it from the + 15-V supply.
2-14. The frequency of carrier wave Ec is constant at 50 Hz in Fig. P2-14. If Vlemp = 5 V, (a) cal
culate high time TH\ (b) plot V0 vs. time.
FIGURE P2-14
2-15. Assume that Vtemp is varied from 0 V to + 10 V in Problem 2-14. Plot TH vs. Vlemp
2-16. In Fig. P2-16, £ in is a triangle wave. The amplitude is - 5 V to + 5 V and the frequency is
100 Hz. Sketch accurately the graphs of (a) Va vs. £ in; (b) V0 vs. /.
+ 15 V
A +5 V
FIGURE P2-16
2-17. Draw the schematic of a circuit whose output voltage will go positive to + Vsa„ when the in
put signal crosses +5 V in the positive direction.
2-18. Is the solution of Problem 2 -1 7 classified as an inverting or noninverting comparator?
2-19. Draw a circuit whose output goes to + Vsat when the input signal is below - 4 V. The output
should be at —Vsa, when the input is above - 4 V.
2-20. Does the solution circuit for Problem 2-19 represent an (a) inverting or noninverting, (b) pos
itive- or negative-voltage-level detector?
CHAPTER 3
Inverting and Noninverting

Amplifiers
U pon com pleting this chapter on inverting and noninverting am plifiers, you will be able
to:
• D raw the circuit for an inverting am plifier and calculate all voltages and currents for a
given input signal.
• Draw the circuit for a noninverting am plifier and calculate all voltages and currents.
• Plot the output voltage w aveshape and o u tp u t-in p u t characteristics o f eith er an invert
ing or a noninverting am plifier for any input voltage w aveshape.
• D esign an am plifier to m eet a gain and input resistance specification.
• Build an inverting or noninverting adder and audio mixer.
• U se a voltage follow er to m ake an ideal voltage source.
• C reate a negative output voltage from a positive reference voltage.
• Add a dc offset voltage to an ac signal voltage.
Inverting and Noninverting A m plifiers 45
• M easure the average value of several signals.

• D esign with single-supply op am ps.
• Build a subtractor.
• D esign a signal conditioning circuit for a tem perature sensor.
• A nalyze inverting and noninverting am plifier circuits using PSpice.
3-0 INTRODUCTION _________________________________________________________________________
This chapter uses the op am p in one of its m ost im portant applications— m aking an am
plifier. An am plifier is a circuit that receives a signal at its input and delivers an undis
torted larger version o f the signal at its output. All circuits in this chapter have one fea
ture in com m on: An external feedback resistor is connected betw een the output term inal
and ( —) input term inal. T his type of circuit is called a negative fe ed b a c k circuit.
T here are many advantages obtained with negative feedback, all based on the fact
that circuit perform ance no longer depends on the open-loop gain o f the op am p, A OL. By
adding the feedback resistor, we form a loop from output to ( —) input. T he resulting cir
cuit now has a closed-loop gain or am plifier gain, A CL, w hich is independent o f A OL (pro
vided that A 0 l is m uch larger than ACL).
As will be shown, the closed-loop gain, A CL, depends only on external resistors. For
best results 1% resistors should be used, and A CL will be know n within 1%. N ote that
adding external resistors does not change the open-loop gain A OL. A OL still varies from
op am p to op am p, so adding negative feedback will allow us to ignore changes in A o L
as long as A OL is large. We begin with the inverting am plifier to show that A CL depends
sim ply on the ratio o f two resistors.
3-1 THE INVERTING AMPLIFIER ____________________________________________________________
3-1.1 Introduction
T he circuit of Fig. 3 - 1 is one of the most w idely used op am p circuits. It is an am plifier

w hose closed-loop gain from Et to V0 is set by Rf and /?,. It can am plify ac or dc signals.
To understand how this circuit operates, we make two realistic sim plifying assum ptions
that w ere introduced in C hapter 2.
1. T he voltage E d betw een the ( + ) and ( —) inputs is essen tially 0 if VQ is not in

saturation.
2. The current drawn by either the ( + ) or the ( - ) input term inal is negligible.
3-1.2 Positive Voltage Applied to the Inverting Input
In Fig. 3-1, positive voltage E, is applied through input resistor R t to the op am p ’s ( —) in
put. N egative feedback is provided by feedback resistor Rf . T he voltage betw een the ( + )
and ( - ) inputs is essentially equal to 0 V. T herefore, the ( - ) input term inal is also at
46 Chapter 3
Voltage across
R f equals V(>.
—
Rf = 100 kft
Voltage across +V
Rj equals Et
— W v -----------
R; = 10 kQ -0V
FIG U RE 3-1 A positive input voltage is applied to the ( —) input of an in

verting amplifier, ft, converts this voltage to a current, /; /^converts / back into
an amplified version of Er
0 V, so ground potential is at the ( —) input. For this reason, the ( - ) input is said to be at
virtual ground.
S ince one side of /?, is at E, and the other is at 0 V, the voltage drop across /?, is E h
T he current I through /?, is found from O h m 's law:
(3 -la )
Rj includes the resistance of the signal generator. This point is discussed further in Section
3-5.2.
All of the input current I flow s through Rf> since a negligible am ount is draw n by
the ( —) input term inal. N ote that the current through Rf is set by /?, and not by Rft V0,
or the op amp.
T he voltage drop across R f is sim ply I (Rf), or
(3 -lb )
As shown in Fig. 3-1, one side of R f and one side o f load R L are connected. The voltage from
this connection to ground is V0. The other sides o f R f and o f R L are at ground potential.
Therefore, V0 equals VRj (the voltage across RJ). To obtain the polarity o f VQ, note that the
left side of R f is at ground potential. The current direction established by Ef forces the right
side of R f to go negative. Therefore, VQ is negative when Et is positive. Equating V0 with VRj
and adding a minus sign to signify that VG goes negative when Ex goes positive, we have
(3-2a)
0 '/?,■
Now, introducing the definition that the closed-loop gain o f the am plifier is A cL, we
rew rite Eq. (3-2a) as
A C L — (3-2b)
R,
T he m inus sign in Eq. (3-2b) show s that the polarity o f the output Va is inverted
w ith respect to E h For this reason, the circuit o f Fig. 3-1 is called an inverting amplifier.
3-1.3 Load and Output Currents
The load current 1L that flow s through R L is determ ined only by R L and V0 and is fu r
nished from the op am p ’s output term inal. T hus 1L = V J R L. The current / through Rf m ust
also be furnished by the output term inal. T herefore, the op am p output current l0 is
(3-3)
E x a m p le 3-1
For Fig. 3-1, let Rf = 100 k fl, R, = 10 k fl, and £, = 1 V. C alculate (a) /; (b) V*; (c) A b
s o lu tio n (a) From Eq. (3 -la),
F 1V
I = — = “4 ^ 7 7 = 0.1 mA
/?, io k n
(b) From Eq. (3-2a),
Rr
v’ = - % x e >- (iv»- - |ov
(c) U sing Eq. (3-2b), we obtain
R>r _ 100 k f l
= -10
Ri 10 k f l
This answ er m ay be checked by taking the ratio o f Vv to
AcL = ^ = ^ y - = - l0
C E, 1V
E x a m p le 3-2
U sing the values given in Exam ple 3-1 and R L = 25 k fl, determ ine (a) IL\ (b) the total cu r
rent into the output pin of the op amp.
E x a m p le 3-3
For Fig. 3-2, let R j = 250 k R t = 10 kCl, and = - 0 . 5 V. C alculate (a) /; (b) the volt
age across R /y (c) V0.
S o lu tio n (a) From Eq. (3 -la ),
Ej_ = 0.5 V
1= = 50 /jlA = 0.05 mA
R, 10 k a
(b) From Eq. (3 -lb ),
VR f = I X R f
= (50 /iA )(2 5 0 k ft)
= 12.5 V
(c) From Eq. (3-2a),
Rr 250 kH
( - 0 . 5 V) = + 1 2 .5 V
io k n
Thus the m agnitude of the output voltage does equal the voltage across Rf, and A C L = —25.
E x a m p le 3-4
U sing the values in Exam ple 3-3, determ ine (a) R L for a load current o f 2 mA; (b) I0\ (c)
the circu it’s input resistance.
S o lu tio n (a) U sing O h m ’s law and VD from E xam ple 3-3,
Vn 12.5 V
IL 2 mA
(b) From Eq. (3-3) and E xam ple 3-3,
IQ = 1 + IL = 0.05 mA + 2 mA = 2.05 mA
(c) The circu it’s input resistance, or the resistance seen by , is /?, = 10 kH.
A PSpice model and sim ulation results are given in Section 3-13.
3-1.5 Voltage Applied to the Inverting Input
Figure 3-3(a) shows an ac signal voltage E t applied via R , to the inverting input. For the
positive half-cycle, the voltage polarities and the direction o f currents axe the sam e as in
Fig. 3-1. For the negative half-cycle voltage, the polarities and direction o f currents are the
sam e as in Fig. 3-2. T he output waveform is the negative (or 180° out o f phase) o f the
Inverting and Noninverting Amplifiers 51
E x a m p le 3-6
If the input voltage in Exam ple 3-5 is - 5 V, determ ine the output voltage.
S o lu tio n U sing Eq. (3-2a) or rearranging Eq. (3-2b), we obtain
V, = — X E, = A cl E, = ( —2 )(—5 V) = 10 V
See tim e 0 in Figs. 3-3(b) and (c). T he frequency o f the output and input signals is the
same.
A P Spice m odel and sim ulation are given in Section 3-13. The sim ulation uses a 5-V-
peak sine w ave w ith a frequency set at 500 H z as the input signal.
Follow ing is an exam ple o f the design procedure for an inverting am plifier.
D esign an am plifier w ith a gain of —25. The input resistance R {n should equal or exceed
10 m .
D esign P ro c e d u re
1. C hoose the circuit type illustrated in Figs. 3-1 to 3-3.

2. Pick Ri = 10 k f l (safe, prudent choice).
3. C alculate R f from Rf ~ (gain)(/?>). (For this calculation, use the m agnitude o f gain.)
3-1.7 Analysis Procedure
You are interview ing for a jo b in the electronics field. T he technical interview er asks you
to analyze the circuit. A ssum e that you recognize the circuit as that o f an inverting am
plifier. Then,
1. Look at R h State that the input resistance o f the circuit equals the resistance o f R
2. D ivide the value of R f by the value o f R h State that the m agnitude o f gain equals
R f/R h A lso, the output voltage will be negative w hen the input voltage is positive.
Solution From Eq. (3-4), VQ = - ( 2 V + 3 V + 1 V) = —6 V. T he PSpice model for this

circuit is shown in Fig. 3-24.
Example 3-9
If the polarity of E 3 is reversed in Fig. 3-4 but the values are the sam e as in E xam ple 3-8,
find V0.
Solution From Eq. (3-4), V , = - ( 2 V + 3 V - 1 V) = - 4 V.
If only two input signals, E x and E 2, are needed, sim ply replace E 3 w ith a short cir
cuit to ground. If four signals m ust be added, sim ply add another equal resistor R betw een
the fourth signal and the sum m ing point S . E quation (3-4) can be changed to include any
num ber o f input voltages.
3-2.2 Audio Mixer
In the adder of Fig. 3-4, all the input currents flow through feedback resistor Rf . T his
m eans that /, does not affect / 2 or / 3. M ore generally, the input currents do not affect one
another because each “sees” ground potential at the sum m ing node. T herefore, the input
currents— and consequently the input voltages £ ], E 2, and E 3— do not interact.
T his feature is especially desirable in an audio mixer. For exam ple, let E u E2, and
E 3 be replaced by m icrophones. The ac voltages from each m icrophone w ill be added or
m ixed at every instant. Then if one m icrophone is carrying guitar m usic, it will not com e
out of a second m icrophone facing the singer. If a lOO-kfl volum e control is installed be
tw een each m icrophone and associated input resistor, their relative volum es can be ad
justed and added. A w eak singer can then be heard above a very loud guitar.
3-2.3 DC Offsetting an AC Signal

Som e applications require that you add a dc offset voltage or current to an ac signal.
Suppose that you m ust transm it an audio signal via an infrared em itting diode (IR ED ) or
light-em itting diode. It is first necessary to bias the LRED on w ith a dc current. T hen the
audio signal can be superim posed as an ac current that rides on or m odulates the dc cu r
rent. T he result is a light or infrared beam w hose intensity changes directly w ith the au
dio signal. We illustrate this principle by an exam ple.
Example 3-10
D esign a circuit that allow s you to add a dc voltage to a triangle wave.
Solution S elect a tw o-channel adder circuit as in Fig. 3-5(a). A variable dc offset voltage
Edc, is connected to one channel. The ac signal, £ ac, is connected to the other.
56 Chapter 3
Rf Rr Rr
E 1\„n + E2
D-7T + E 3 -Z-D (3-7a)
A1 A2 A3
E quation (3-7a) shows that the gain of each channel can be changed independently o f the
others by sim ply changing its input resistor.
Rf_
CL-S (3-7b)
/?>’ R?
or
V0 — E ]A Cl } + E 2A CL2 + E?A c L)
Follow ing is an exam ple of the design procedure for a m ultichannel am plifier.
D esign a three-channel inverting am plifier. T he gains for each channel will be
Channel number Voltage gain

1 -10
2 -5
3 -2
1. S elect a 10-kfi resistor for the input resistance o f the channel with the highest gain.
C hoose /?! = 10 k f l since A CLi is the largest.
2. C alculate feedback resistor Rf from Eq. (3-7b):
A = _K l R,
C L , . 10 = R f = 100 k n
10 k f l ’
3. C alculate the rem aining input resistors from Eq. (3-7b) to get R 2 — 20 k H and R 3 =
50 kfl.
3-4 INVERTING AVERAGING AMPLIFIER
Suppose that you had to m easure the average tem perature at three locations in a dw elling.
First m ake three tem perature-to-voltage converters (shown in Section 5-14). T hen connect
their outputs to an averaging amplifier. An averaging am plifier gives an output voltage
proportional to the average o f ail the input voltages. If there are three input voltages, the
averager should add the input voltages and divide the sum by 3. The averager is the sam e
circuit arrangem ent as the inverting adder in Fig. 3-4 or the inverting adder w ith gain in
Fig. 3-6. T he difference is that the input resistors are m ade equal to som e convenient value
R and the feedback resistor is made equal to R divided by the num ber of inputs. Let n equal
the num ber of inputs. Then for a three-input averager, n = 3 and Rf = R!3. Proof is found
by substituting into Eq. (3-7a), for Rf = R!3 and R x = R 2 — R^ = R to show that
(3-8)
E x a m p le 3-12
In Fig. 3-4, = R2 = R 3 = R = 100 kH and Rf = 100 kH /3 ~ 33 k f l If E x = + 5 V,

E 2 = + 5 V, and E 3 = - IV , find V0.
S o lu tio n Since R f = R B y the am plifier is an averager, and from Eq. (3-8) with n — 3, we
have
5 V + 5 V + ( - 1 V)
3
Up to now we have dealt w ith am plifiers w hose input signals were applied via R{
to the op am p ’s inverting input. We turn our attention next to am plifiers in w hich E-, is ap
plied directly to the op am p ’s noninverting input.
3-5 NONINVERTING AMPLIFIER ___________________________________________________________
3-5.1 Circuit Analysis
Figure 3-7 is a noninverting am plifier; that is, the output voltage, VD, is the sam e polar
ity as the input voltage, T he input resistance o f the inverting am plifier (Section 3-1)
is R h but the input resistance o f the noninverting am plifier is extrem ely large, typically
exceeding 100 M fl. Since there is practically 0 voltage between the ( + ) and ( - ) pins of
the op am p, both pins are at the sam e potential E r Therefore, Et appears across R\>
causes current I to flow as given by
(3-9a)
T he direction o f / depends on the polarity of E r C om pare Figs. 3-7(a) and (b). The input
current to the op am p ’s ( —) term inal is negligible. T herefore, I flows through f y a n d the
voltage drop across Rf is represented by VR and expressed as
Rf
Va = Ei + - ^ - E,
R\
or
Vo ~ [ 1 + E,- (3-IOa)
Ri
R earranging Eq. (3 -10a) to express voltage gain, we get
V Rf R f + R]
A cl = - ^ = I+ ~ J ~ = / p (3-IOb)
Ej R\ Ri
E quation ( 3 - 10b) shows that the voltage gain o f anoninverting am plifier is alw ays greater
than 1.
The load current 1L is given by V0/R l and therefore depends only on V0 and R L. I0
is the op am p ’s output current and is given by Eq. (3-3).
Example 3-13
(a) Find the voltage gain for the noninverting am plifier o f Fig. 3-8. If E , is a 100-Hz trian
gle w ave w ith a 2-V peak, plot (b) V0 vs. t\ (c) VD vs. E h
S o lu tio n (a) From Eq. ( 3 - 10b),
R f+ R t ( 4 0 + 1 0 ) k fl
CL~ R] ~ 10 kH “
(b) See Fig. 3-8(b). T hese are the w aveshapes that w ould be seen on a dc-coupled, d u al
trace oscilloscope.
(c) See Fig. 3-8(c). S et an oscillo sco p e for an x - y display, vertical 5 V /div, h o rizo n tal
1 V/div. N ote that the slope rises to the right and is positive. R ise over run gives you the
gain m agnitude of + 5 .
Follow ing is an exam ple o f the design procedure for a noninverting am plifier.
Design Example 3-14

D esign an am plifier with a gain of + 10.
Chapter 3
R/+ R \
■E, = 5E:
(a) Noninverting am plifier

circuit with gain of +5.
K>(V)
(A) !3
(A) '3 PU« °A
(c) Input-output characteristic

o f a noninverting amplifier.
(b) W aveshape of
VQ and £ , vs. /.
FIGURE 3-8 Noninverting amplifier circuit analysis for Example 3-13.

Design Procedure
1. Since the gain is positive, select a noninverting am plifier. T hat is, we apply E, to the
op a m p ’s ( + ) input.
2. Choose R { = 10 kft.
3. C alculate Rf from Eq. (3-10b).
10 = 1 + 777777’ Rf = 9(10 k fl) = 90 left

10 k i l
3 6 VOLTAGE FOLLOW ER ___________________________________________________________________
3-6.1 Introduction
The circuit o f Fig. 3-9 is called a voltage follow er, but it is also referred to as a source
follower, unity-gain amplifier, buffer amplifier, or isolation amplifier. It is a special case
o f the noninverting amplifier. The input voltage, £, , is applied directly to the ( + ) input.
Since the voltage betw een ( + ) and ( —) pins of the op am p can be considered 0,
( 3 - II a)
Note that the output voltage equals the input voltage in both m agnitude and sign. T herefore,
as the nam e o f the circuit im plies, the output voltage fo llo w s the input or source voltage.
The voltage gain is 1 (or unity), as shown by
(3-1 lb)
FIG U RE 3-9 Voltage follower.

64 Chapter 3
Now let us consider the sam e signal source connected to an inverting am p lifier
w hose gain is - 1 [see Fig. 3 - 1 1(b)]. As stated in Section 3-1.3, the input resistan ce to
an inverting am plifier is R,. T his causes the g en erato r voltage £ gen to divide betw een
R ini and /?,. U sing the voltage division law to find the g en erato r term inal voltage E {
yields
R, io k n
E ,= X Earn = x (1.0 V) = 0.1 V
R\nl + Ri 10 k n + 90 k.Q
T hus it is this 0.1 V that becom es the input voltage to the inverting am plifier. If the in
verting am plifier has a gain of only —1, the output voltage V0 is —0.1 V.
In conclusion, if a high-im pedance source is connected to an inverting am plifier, the
voltage gain from V0 to Egen is not set by /fy-and R , as given in Eq. (3-2b). T he actual gain
m ust include R inl, as
R71 io kn
o .i
Ri + R \, ioo k n
If you m ust am plify and invert a signal from a high-im pedance source and w ish to
draw no signal current, first buffer the source w ith a voltage follower. Then feed the fo l
low er’s output into an inverter. If you need buffering and do not w ant to invert the input
signal, use the noninverting amplifier.
3-7 THE "IDEAL" VOLTAGE SO U RC E
3-7.1 Definition and Awareness
T he ideal voltage source is first encountered in textbooks concerned w ith fundam entals.
By definition, the voltage does not vary regardless o f how m uch current is draw n from it.
You m ay not be aw are of the fact that you create a perfect voltage source w hen you m e a
sure the frequency response o f an am plifier or filter. We explain how this apparently per
fect perform ance com es about in the next section.
3-7.2 The Unrecognized Ideal Voltage Source
The lab or field procedure typically goes like this: Set the input signal am plitude at 0.2 V
rm s and frequency at the low est lim it. M easure output V0. Hold E in at 0.2 V rm s for each
m easurem ent. Plot VQ or V0/E [u versus frequency. As you dial higher frequencies, E m b e
gins to decrease (because of input capacitance loading). You autom atically increase the
function g en erato r’s volum e control to hold E lu at 0.2 V. You have ju st, by definition, cre
ated an “ideal” voltage source. £ in never varied throughout the test sequence no m atter
how m uch current was draw n from it. This is an exam ple o f the unrecognized ideal volt
age source.
66 Chapter 3
To preserve the value of any reference voltage, sim ply buffer it with a voltage fol
lower. T he 7.5-V reference voltage is connected to a voltage follow er in Fig. 3-12(c). The
output of the follow er equals K e f - You can extract up to 5 mA from the fo llo w er's output
w ith no change in Vref.
T he buffer m akes an excellent clandestine bug. You can m onitor w hat is going on
at any circuit point. Since a follow er has a high input im pedance, it draw s negligible cu r
rent from the circuit. T herefore, it is nearly im possible to detect.
3-7.4 Precise Voltage Sources
Section 2-6 introduced precision voltage reference ICs such as the R E F -02 (a precision
+ 5-V reference chip). You can use these voltage reference chips w ith an inverting am
plifier to create precise negative voltages as well as positive and negative voltages. The
circuit o f F igure 3 - 13(a) show s how a negative voltage o f —5 V can be created using the
R E F -02 and an inverting am plifier. T his circu it has a low er parts count and m ore p reci
sion than the circuit o f Figure 3-12(c). T he parts co u n t is obvious, and the precision is
obtained by the R E F -02 in place o f /?, and Rf . C onsider R t and Rjr to be 1% resistors.
T hen there is a possibility that one resistor could be + 1 % w hile the other is —1%. T his
w ill produce an o utput voltage w ith a 2% error, w hich may not be acceptable for your
design.
A n o th er ap p licatio n using the R E F -02 w ith an inverting am p lifier is show n in
F igure 3 - 13(b). T his circuit creates a ± 5 -V source from a single R E F-02 chip and an in
verting am plifier.
3-8 NONINVERTING ADDER ________________________________________________________________
A three-input noninverting adder is constructed with a passive averager and noninverting

am plifier as shown in Fig. 3 - 14(a). The passive averager circuit consists o f three equal re
sistors R a and the three voltages to be added. The output o f the passive averager is £ in,
w here £ in is the average o f E lt E2, and £ 3, or E in — (E , 4- E 2 + E3)/3. C onnect a voltage
follow er to E in if you need a noninverting averager (in contrast with Sec. 3-4).
O utput V0 results from am plifying £ in by a gain equal to the num ber o f inputs rt. In
Fig. 3 - 14(a), n — 3. D esign the am plifier by choosing a convenient value for resistor R.
T hen find Rf from
Rf = R ( n - 1) (3-12)
As shown in Fig. 3-14(a), the value for /^ s h o u ld be Rf = 10 kH (3 — 1) = 20 kH . If

E 2, and E 3 are not ideal voltage sources, such as a battery or output of an op am p, buffer
them w ith follow ers as in Fig. 3 - 14(b).
+ 15 V
1
2
V -1 5 V SJ
(b)
FIGURE 3-13 (a) A - 5 V precision output voltage; (b) a ±5 V output voltage.
3-9 SIN GLE-SUPPLY OPERATION __________________________________________________________
Som e am plifier designs require battery-pow ered operation and output voltage sw ings to
w ithin m illivolts o f the supply voltages. Thus, you w ant an op am p described by m anu
facturers as a device capable o f single-supply and rail-to-rail operation. Two such devices
are the A D 820 and the O P-90 from A nalog D evices. T h ese op am ps can operate from
either a single or dual supply. For exam ple, the A D 820 can operate from a dual supply
. sources, simply buffer each one with
a voltage follower.
FIG U RE 3-14 All resistors of an n-input noninverting adder are equal except
the feedback resistor; choose R = 10 kfl and RA = 10 kfl. Then /êq u als R
times the number of inputs minus one: Rf = R(n — I).
(± 1 .5 V to ± 1 8 V) or from a single supply ( + 3 V to + 3 6 V). T he input signal applied

to these devices can be brought to ground, and the output can sw ing to w ithin 10 mV of
either supply voltage. They are available in an 8-pin m ini-D IP package w ith the sam e
pinouts as the 741 or O P-177 op am ps. Single-supply op am ps are often used in battery-
pow ered applications, portable instrum ents, m edical instrum entation, and data acquisition
units. O ften they are used to am plify positive signals com ing from sensors such as strain
Rf = 90 k Q
---------W V --------
+5 V
A
FIG U R E 3-15 The AD820 can operate for single-supply applications as

shown in (a) and (b).
gages or therm ocouples. Figure 3 -15(a) show s the A D 820 w ired as a noninverting am
plifier w ith a gain o f 10. If you are operating the A D 820 from a single supply and w ant
to am plify an ac signal, then the input ac signal has to have a dc offset or be com bined
w ith a dc voltage as show n in F igure 3 -15(b). (Note: T his circuit is sim ilar to the invert
ing adder studied in F igure 3-5(a) but now operated from a single supply.)
3-10 DIFFERENCE AM PLIFIERS _____________________________________________________________
T he differential am plifier and its more pow erful relative, the instrum entation am plifier,
will be studied in C hapter 8. However, as other applications of inverting and noninvert
ing am plifiers, we offer two exam ples o f the difference am plifier in this section and the
design o f a signal conditioning circuit for a tem perature sensor in the next.
70 Chapter 3
3-10.1 The Subtractor
A circuit that takes the difference betw een tw o signals is called a su b tra cto r [see Fig. 3-
16(a)]. It is m ade by connecting an inverting am plifier to a tw o-input inverting averager.
To analyze this circuit, note that E, is transm itted through op am p A w ith a gain o f — 1
and appears as V0] = —E x. VDi is then inverted (tim es - 1 ) by the top channel o f the in
verting am plifier B. Thus E { is inverted once by op am p A and again by op am p B to ap
pear at VQ as E ,.
E 2 is inverted by the bottom channel o f op am p B and drives V0 to —E 2. T hus V0
responds to the difference betw een E { and E2, or
V0 = E l - E 2 (3-13a)
Inverting am plifier T w o-input inverting adder
10 kO
J5 V
(a) An inverting am plifier and a two-input inverting
adder make a subtractor. VQ= E { - £ 2-
Rr= JOkft
------- Â/V---------
15 V
(b) Both am plifier inputs are used to make an am plifier
that calculates the difference between 2E, and E 2.
FIG U RE 3-16 Two examples of difference amplifiers are the subtractor in (a) and us
ing the op amp as both an inverting and a noninverting amplifier in (b).
As show n in Fig. 3-16(a), for £ , = 2 V and E2 = 3 V, V0 = 2 - 3 = - 1 V. If the value

o f R f is m ade larger than R h the subtractor w ill have gain
Va = ^ (£, - E2) ( 3 - 13b)

K,
3-10.2 Inverting-Noninverting Amplifier
In Fig. 3-16(b), signal E\ is applied to the am p lifier’s noninverting input and signal E2 is
applied to the inverting input. We w ill use superposition to analyze this circuit. First re
m ove E2 and replace it by a ground. E { sees a noninverting am plifier w ith a gain o f (Rf
+ Ri)IRit or 2. T hus E x alone drives V0 to 2E {. N ext reconnect E2 and replace E } by a
ground. E2 sees an inverting am plifier with a gain o f - 1 . E2 drives V0 to —E2. W hen both
E x and E2 are connected, V0 is given by
V„ = 2E[ - E2 (3-14)
As show n in Fig. 3 - 16(b), VQ = 1 V w hen - 2 V and E2 = 3 V.

W e will now show how to design the subtractor circuit o f Fig. 3 - 16(a) to be the an a
log interface circuitry connected betw een a tem perature sensor and the analog—digital
converter o f a m icrocontroller. T his analog interface circuit is also know n as a signal co n
ditioning circuit.
3-77 DESIGNING A SIGNAL CONDITIONING CIRCUIT*
A nother way of viewing the circuit in Fig. 3-5(a) (redraw n in Figure 3-17 for convenience)
is that it allows us to design a signal conditioning circuit (SCC) for a m icrocontroller ap
plication that satisfies the equation of a straight line, y = mx + b. This equation occurs quite
often w hen designing SCCs. Com paring the equation o f y = mx + b to the circuit o f Fig.
3-17, the y term is the output voltage, V0; the x term is the input signal voltage, E the m
term is the gain o f the circuit, R f/R {\ and the b term is Rf /R2 tim es Edc. Therefore, if your
application uses a sensor that generates an output signal m easured with respect to ground,
w hich m ust be am plified and offset, then an SCC sim ilar to Fig. 3-17 may be used. (Note:
T he outputs o f som e sensors generate a differential output, and these devices require an SCC
capable o f m easuring a differential voltage. Such circuits are studied in C hapter 8.) The de
sign of any SCC unit requires obtaining the equation o f the circuit. This equation is obtained
from w hat y o u ’ve got (the output conditions o f the sensor) to what you w ant (the input con
ditions o f the m icrocontroller’s A /D converter). Let us study this topic.
Statement of the problem. D esign a signal conditioning circuit to interface

betw een a tem perature sensor and the A /D converter o f a m icrocontroller. T he tem pera
* For more exam ples of the linear circuil design procedure refer to D ata Acquisition and Process Control
with the M 6 8 H C I1 Microcontroller, 2nd Ed. by F. Driscoll, R. Coughin, and R. Villanucci, Prentice Hall (2000).
72 Chapter 3
AA/V
R
+ 15 V
A
FIGURE 3-17 The inverting summer can be designed to satisfy the equation
of a straight line, y = mx + b
ture range to be m easured is 0° to 50°C, and the range o f the A /D converter is from 0 to
5 V. You w ant the output o f the SCC to be linear; that is, w hen the sensor is m easuring
0°C , the output o f the SCC is 0 V; w hen the sensor is m easuring 10°C, the S C C ’s output
is to be 1 V; and so forth up to 50°C, at w hich tem perature the SC C outputs 5 V.
Solution. A lthough our goal is to design the SCC, w hich is an op amp circuit, our
starting point is the sensor and w riting an equation for it, because the output o f the sensor
is the input to the SCC. Therefore, once the sensor is picked, this is w hat y o u ’ve got. W hat
you want is the output o f the SCC to fit the range o f the m icrocontroller’s A/D converter.
Therefore, the SCC design is being squeezed between w hat y o u ’ve got and w hat you want.
L et’s first learn about one type of tem perature sensor and how to w rite the equation for it.
Introduction to a temperature sensor. For this application, we shall choose

the LM 335, which is a solid-state temperature sensor that belongs to a family o f devices that
has a sensitivity of 10 mV/°K. It is used in applications that require m easuring tem peratures
from —10° to 100°C and is m odeled as a two-terminal zener. The package style and model
are shown in Figures 3-18(a) and (b), respectively. This device is capable o f operating over
a current range of from 400 fiA to 5 mA. The data sheet for the LM 335 gives the device’s
sensitivity as 10 mV/°K. However, our application is to measure degrees Celsius. The rela
tionship between degrees Kelvin and degrees Celsius is: A 1-degree rise in Kelvin equals a
1-degree rise in Celsius, and the freezing point o f water is 0°C, which equals 273°K.
Writing an equation that describes the sensor. A plot o f the output volt
age of the JLM335 versus tem perature is given in Figure 3-18(c). The slope o f the line is
the d ev ice’s sensitivity— 10 m V /°K . T herefore, in term s o f °K the output voltage is
Vj = (10 mV/°K) (7 inOK) (3-15)
w here T is the tem perature in °K. At 273°K (0°C), the sen so r’s output voltage is
VV = (10 m V /°K ) (273°K ) - 2.73 V
as show n in Figure 3 - 18(c).

TO-92 TO-46
Plastic package Metal can package
Current-limiting
extemaj resistor, R
Model
of the
LM335
Voltage (VT)
(c)
FIGURE 3-18 The LM335 (a) package styles, (b) model, and (c) voltage ver
sus temperature characteristic.
N ow the sensor’s output voltage can be w ritten in term s o f degrees C elsius as
Vr - (10 m V /°C ) (7 inoC) + 2.73 V (3-16)
w here T is the tem perature in degrees Celsius. For our application, at 0°C VT = 2.73 V
and at 50°C VT = 3.23 V. This is the input voltage range for the SCC. T he output range
o f the SC C is the input range o f the A /D converter, w hich is 0 V to 5 V. F igure 3-19 show s
a block diagram o f this data acquisition system for m easuring tem perature.
Writing an equation that describes the SCC. F rom the inform ation we
know about the sensor and the A /D converter, we can plot the output/input characteristics
o f the SCC. F igure 3-19 includes such a plot. T he output values o f the SCC are plotted
on the y-axis. R em em ber, these values are the voltage range o f the A /D converter— 0 V
to 5 V. T he input values to the SCC are plotted on the je-axis. T hese values are the volt
age range o f the sensor— 2.73 V to 3.23 V for this application.
74 Chapter 3
o°c 2.73 V Signal 0 V

■Ar/
50°C
LM335
3.23 V
conditioning
circuit 5V
M icrocontroller
VV(V)
(3.23 - 2.73) = 0.5 V

-2 7 .3
FIGURE 3-19 Block diagram of a temperature measuring system and the de
sired output-input characteristics of the SCC.
T he slope o f the line is
(5 ~ 0) V
10 (3-17)
(3.23 - 2.73) V A vy
T his value of 10 is the gain that VT m ust be m ultiplied by. T he dc offset is found from
ch o o sin g a point on the line and su b stitu tin g into the eq u atio n o f a stra ig h t lin e—
y = m x + b. C hoosing the coordinate pair (2.73, 0), we obtain
0 = (10) (2.73) + b
S olving for b yields
b = - 2 7 .3 V
T hus, the equation of the S C C ’s output voltage is
V0 = (10) (V T ) - 27.3 V (3-18)
Note: A lthough the dc offset is - 2 7 .3 V, the output voltage, Vot never goes to this value be
cause the range of VT is from 2.73 V to 3.23 V. This range o f VT limits V0 from 0 to 5 V.
Designing the signal conditioning circuit. N ow that we know the equation

for the SC C and it is in the form o f y = m x + b, we w ant a circuit in w hich the gain o f
10 and the offset o f —27.3 V can be set independently. A noninverting sum m er is not the
3-12.2 Inverting Amplifier—A C Input
R efer to Fig. 3-3 and create the PSpice model o f the circuit. Set the input voltage to a
sine w ave with a peak value o f 5 V and a frequency o f 500 Hz. O btain a plot o f £, and
V0 versus tim e. To begin, place the follow ing parts in the w ork area.

= > VSIN 1 source.slb
= > R 3 analog.sib
= > GLOBAL 4 port.slb
= > AGND 5 p ortslb
N ote that we are using a sine wave as the input signal instead o f a triangular wave as
show n in Fig. 3-3. A rrange the parts as shown in Fig. 3-3. C hange the attributes o f the
parts as given in Fig. 3-3. Set up the sine-w ave attributes by double-clicking on the sym
bol. In the pop-up w indow change VOFF, VAMPL, and FREQ.
VOFF = > 0 = > Save Attr

VAMPL = > 5V — > Save Attr — > Change Display — > Both name and value
FREQ = > 500Hz = > Save Attr = > Change Display = > Both name and value
D ouble-click on the lead from the sine w ave generator to Ri and label it Ei. D ouble-click
on the lead from the output term inal o f the op am p and label it Vo. See Fig. 3-22.
*/
- A /W -
20 kQ.
FIGURE 3-22 PSpice model for Fig. 3-3
In order to obtain a plot o f E, and V0 versus tim e, we m ust initialize the T ransient m enu
Draw => G e t New Part
= > uA741 1 evai.slb

= > R 5 analog.slb
= > G LOBAL 4 port.slb
= > AGND 7 port.slb
= > IPROBE 4 special.sib
= > V IEW PO INT 2 special.slb
A rrange and w ire the parts as show in Fig. 3-4. Place the IP R O B E s to m easure /,, / 2, / 3,
and If, and place the V IE W P O IN T S to m easure the voltage at the sum m ing point, S , and
V0. C hange the parts attributes to correspond to Fig. 3-4. Save the circuit in a file and run
the sim ulation A n aly sis = > S im u la te . T he results are show n in Fig. 3-24.
2.000E-03
Jo
FIGURE 3-24 PSpice model of Fig. 3-4— the inverting adder.
3-12A Noninverting Amplifier
C reate a P S pice m odel o f the noninverting am p lifier show n in Fig. 3-7(a) w ith Rf =
20 k fl, /?, = 10 k f l, and £,■ = 2 V. U se IP R O B E to m easure l 0, If , ILy and / ( - ) . Use
V IE W P O I N T to m easure VL and the v o ltag e at the ( - ) input. If you are using the
80 Chapter 3
evaluation softw are package, build the circuit with a 741 op am p instead o f the O P - 177
as show n in Fig. 3-7(a). Place the follow ing parts in the w ork area.
Part N um ber Library
=> uA741 1 eval.slb

=> VDC 3 source.slb
=> R 3 analog.slb
=> GLOBAL 4 port.slb
=> AGND 5 portslb
=> IPROBE 4 special.sib
=> VIEWPOINT 2 speciahslb
A rrange the parts and include the IP R O B E s and V IE W P O IN T S . Save the file and run
the sim ulation A nalysis = > S im u la te. The results are show n in Fig. 3-25.
FIGURE 3-25 PSpice model for the noninverting amplifier of Fig. 3-7(a).
PRO BLEM S ___________________________________________________________________________

3-1. What type of feedback is applied to an op amp when an external component is connected
between the output terminal and the inverting input?
3-2. If the open-loop gain is very large, does the closed-loop gain depend on the external com
ponents or the op amp?
3-3. What two assumptions have been used to analyze the circuits in this chapter?
portion to the audio signal, the process is called am plitude m odulation (A M ). C hanging
the frequency or the phase angle of the carrier wave results in freq u en cy m odulation (FM )
and p hase-angle m odulation (PM ), respectively.
O f course, the original audio signal m u st eventually be recovered by a pro cess
called dem odulation or detection. T he rem ainder o f this section concentrates on using the
m ultiplier for am plitude m odulation. (“M o d u late” is from the ancient G reek language
m eaning to “change.” Curiously, it is the Latin prefix “d e” that converts the m eaning to
“change back.” )
12-7.2 Defining Amplitude Modulation
T he introduction to am plitude m odulation begins w ith the am plifier in Fig. 12-8(a). T he

input voltage E c is am plified by a constant gain A. A m plifier output VQ is the product
gain o f A and E c. N ow suppose that the am p lifier’s gain is varied. T his co n cep t is rep
resented by an arrow through A in Fig. 12-8(b). A ssum e that A is varied from 0 to a m ax
im um and back to 0 as show n in Fig. 12-8(b) by the plot o f A versus t. T his m eans that
the am plifier m ultiplies the input voltage E c by a different value (gain) over a period o f
tim e. VD is now the am plitude o f input E c varied or m ultiplied by an am plitude o f A. This
process is an exam ple o f am plitude m odulation, and the output voltage VQ is called the
am plitude m odulated signal. T herefore, to obtain an am plitude-m odulated signal (V0),
the am plitude o f a high-frequency carrier signal (Ec) is varied by an intelligence or data
signal A .
12-7.3 The Multiplier Used as a Modulator
F rom S ection 12-7.2 and Fig. 12-8(b), V0 equals E c m ultiplied by A. T h erefo re, am p li
tude m odulation is a m ultiplication p ro c ess. As show n in Fig. 12-8(c), E c is applied to
a m u ltip lie r’s x input. E m [having the sam e shape as A in Fig. 12-8(b)] is applied to the
m u ltip lier’s y input. E c is m ultiplied by a voltage th at varies from 0 th rough a m ax i
m um and back to 0. So VQ has the sam e envelope as Em. T he m u ltip lier can be co n sid
ered a voltage-controlled gain device as w ell as an am plitude m odulator. T he w aveshape
show n is th a t o f a b a la n c e d m odulator. T h e reaso n fo r th is nam e w ill be given in
S ection 12-8.3.
N ote carefully in Fig. 12-8(c) that VQ is not a sine wave; that is, the peak values o f
successive half-cycles are different. This principle is used in Section 12-12 to show how
a frequen cy-sh ifter (heterodyne) circuit w orks, but first, w e exam ine am plitude m odula
tion in greater detail.
72-7.4 Mathematics of a Balanced Modulator
A high-frequency sinusoidal carrier wave Ec is applied to one input o f a m ultiplier. A

low er-frequency audio or data signal is applied to the second input o f a m odulator and
w ill be called the m odulating w ave, Em. For test and analysis, both E c and Em w ill be sine
w aves described as follows.
Modulating, Dem odulating, and Frequency Changing with the M ultiplier 345
M odulating wave, Em:
= Emp sin l u f j ( l2-7b)
w here E mp is the peak value of the m odulating wave and f m is the m odulating frequency.
Now let the carrier voltage Ec be applied to the x input o f a m ultiplier as Ex, and
let the m odulating voltage E m be applied to the y input o f a m ultiplier as Ey. The m ulti
p lier’s output voltage VD is expressed as a product term from Eq. (12-16) as
= Emp\ Q cp (sin 27* > ,)(sin 2jrf[l) ( 12' 8)
Equation (12-8) is called the product term , because it represents the product of two sine
waves w ith different frequencies. However, it is not in the form used by ham radio o per
ators or com m unications personnel. They prefer the form obtained by applying to Eq. (12
8) the trigonom etric identity
(sin y4)(sin B) = i[co s (A - B) - cos (A + 5)] ( 12-9)
Substituting Eq. (12-9) into Eq. (12-8), w here A - E c and B - Ern, we have
va = COS 2 M / C - fjt ~ cos 2 -nifc + f m)t (12-10)
Equation (12-10) is analyzed in Section 12-7.5.
12-7.5 Sum and Difference Frequencies
R ecall from Section 12-7.3 that E cis a sine w ave and E,„ is a sine w ave, but no part
o f V0 is a sine wave. V0in Fig. 12-8(c) is expressed m athem atically by either Eq. (12-8)
or (12-10). B ut Eq. (12-10) show s that VD is m ade up o f tw o cosine w aves w ith fre
q uencies d ifferent from either E m or E c. T hey are the sum fre q u e n c y f c -I- f m and the
d iffe re n c e fr e q u e n c y f c —f m. T he sum and d iffe re n c e fre q u e n c ie s are ev a lu a ted in
E xam ple 12-9.
Example 12-9
In Fig. 12-9, carrier signal Ec has a peak voltage o f Ecp = 5 V and a frequency o f f c =
10,000 Hz. The m odulating signal Em has a peak voltage o f Em = 5 V and a frequency of
f m = 1000 Hz. C alculate the peak voltage and frequency o f (a) the sum frequency; (b) the
difference frequency.
S o lu tio n From Eq. (12-10), the peak value o f both sum and difference voltages is
Emp ECp _ 5 V X 5 V — | 25 V
20 _ 20 ~ *
T he sum frequency is f c + f m = 10,000 Hz + 1000 Hz = 11,000 Hz; the difference fre

quency is f c — f m = 10,000 Hz - 1000 Hz = 9000 Hz. T hus V0 is m ade up o f the differ-
ence o f two cosine waves:
V0 = 1.25 cos 2tt9 0 0 0 / - 1.25 cos 2tt1 1,0001
This result can be verified by connecting a wave or spectrum analyzer to the m ulti
p lier’s output; a 1.25-V deflection occurs at 11,000 Hz and at 9000 Hz. T he original input
signals o f 1 kH z and 10 kH z do not exist at the output.
An oscilloscope can be used to show input and output voltages o f the m ultiplier o f
E xam ple 12-9. The product term for VQ is found from Eq. (12-8):
V0 = 2.5 V (sin 2 7 rl0 ,0 0 0 0 (sin 2 tt1 0 0 0 0
2.5 X Ec X Em
VQ is show n w ith Em in the top draw ing and with E c in the bottom draw ing o f Fig. 12-9.
O bserve that Em and E c have peak voltages o f 5 V. The peak value o f VD is 2.5 V. N ote
that the upper and low er envelopes o f V0 are not the sam e shape as Em. T herefore, w e
cannot rectify and filter Va to recover Em. T his characteristic distinguishes the balance
moduJator.
12-7.6 Side Frequencies and Sidebands
A nother way o f displaying the output o f a m odulator is by a graph show ing the peak am
plitude as a vertical line for each frequency. T he resulting fre q u en c y spectrum is show n
in Fig. 12-10(a). The sum and difference frequencies in V0 are called upper and low er
side frequencies because they are above and below the carrier frequency on the graph.
W hen m ore than one m odulating signal is applied to the m odulator ( y input) in Fig. 12
9, each generates a sum and difference frequency in the output. Thus, there will be tw o
side frequencies for each y input frequency, placed sym m etrically on either side o f the
carrier. If the expected range of m odulating frequencies is known, the resulting range o f
side frequencies can be predicted. For exam ple, if the m odulating frequencies range b e
tw een 1 and 4 kHz, the low er side frequencies fall in a band betw een (10 — 4) kH z =
6 kH z and ( 1 0 — 1) kH z = 9 kHz. The band betw een 6 and 9 kH z is called the low er
sid e b a n d . F or this sam e exam ple, the u p p er sid e b a n d ran g es from ( 1 0 + 1 ) k Hz =
11 kH z to (10 + 4) kH z = 14 kHz. Both upper and low er sidebands are show n in Fig
1 2-10(b).
M odulating, Dem odulating, and Frequency Changing with the M ultiplier 349
standard am plitude m odulator (A M ) adds the carrier term to the output. The A M car ra
dio uses standard AM . O ne way of adding the carrier term to generate a standard AM out
put is show n in Fig. 12-11(a). The m odulating signal is fed into one input o f an adder. A
dc voltage equal to the peak value o f the carrier voltage E cp is fed into the other input.
The output of the adder is then fed into the y input o f a m ultiplier, as show n in Fig. 12-
11(b). T he carrier signal is fed into the x input. T he m ultiplier m ultiplies Ex by Ey, and
its output voltage is the standard AM voltage given by either o f the follow ing equations:
' E2
sin 27jfct (carrier term )
10
+ ( 12- 1
E E
—^ — — (sin 277/c/)(sin 2 ttf mt) (product term )
10
or
E 2cp ■
sin 2.'nfct (carrier term )
10
+
V0 = ^ £<?/? Emp cos 277( f c — f m) t (low er side frequency) ( 12 - 12 )

20
E mp
cos 2 ir{fc + f m) l (upper side frequency)
20
The output voltage V0 is shown in Fig. 1 2 -1 1(b). T he voltage levels are w orked out in the
follow ing exam ple.
Example 12-10
In Fig. 12-11, Ecp = E mp = 5 V. T he carrier frequency f c = 10 kH z, and the m odulating

frequency is f m = 1 kHz. Evaluate the peak am plitudes o f the output carrier and product
term s.
S olution From Eq. (12-11), the carrier term peak voltage is
(5 V)(5 V)
= 2.5 V
10
M odulating, Dem odulating, and Frequency Changing with the M ultiplier 351
The product term peak voltage is
(5V X5 V) = 2_5 v
10
T he side frequencies peak voltages are
( 5 V X 5 V ) = i 25 v
20
T he w aveshape o f V0 is show n in Fig. 1 2 -1 1(b). O bserve that the upper and low er
envelopes o f V0 are the sam e shape as Em. This is characteristic o f a standard am plitude
m odulator (A M ), not of the balanced modulator. It allow s easy recovery o f audio signal E m
by a half-w ave rectifier and suitable filter capacitor.
12-8.2 Frequency Spectrum of a Standard A M Modulator
T he signal frequencies present in V0 for the standard AM output o f Fig. 12-11 are found
from Eq. (12-11). U sing the voltage values in E xam ple 12-10, we have
C arrier term = 2.5 V peak at 10,000 Hz
Low er side frequency = 1.25 V peak at 9000 H z
U pper side frequency = 1.25 V peak at 11,000 H z
T hese frequencies are plotted in Fig. 12-12 and should be com pared w ith the balanced
m odulator of Fig. 12-10.
Dc term
/( k H z )
0 5 10
5V Carrier
Output
0
F IG U R E 12-12 Frequency spectrum for a standard AM modulator,
f c = 10 kH z,/m = 1 kHz.
352 Chapter 12
12-8.3 Comparison of Standard A M Modulators

and Balanced Modulators
If the sw itch in Fig. 1 2 -1 1(a) is position ed to A M , V0 w ill co n tain three fre q u en c ies—
fc> f c + fnv a n d / c — f m— carrier, plus sum and d ifference frequencies. O b serv e that the
envelopes o f VQ have the sam e shape as the in tellig en ce signal E m. T h is observ atio n can
be used to recover Em from the AM signal, as stated in E xam ple 12-JO. N ote that if
there is no signal frequency, the station still transm its carrier f c. R adio receivers use this
fact to activate sig n a l-stre n g th m eters, tu n in g lights, and a u to m atic v o lu m e co n tro l
(AVC).
If the sw itch in Fig. 12-11(a) is positioned to “B alanced,” V0 will contain only the
product term with only tw o frequencies, f c + / m and f c — f m. T he envelope o f V0 does not
follow Em. Since VQ does not contain f ct this type o f m odulation is called balanced m o d
ulation in the sense that the carrier has been balanced out. It is also called suppressed ca r
rier m odulation, since the carrier is suppressed in the output. If no m odulating frequency
is present, the radio station does not transm it. This is a good system for clandestine o p
eration. For a com parison o f balanced and standard AM m odulation, both outputs are
show n together in Fig. 12-13.
M odulating
5 V at 1 kHz
Carrier
5 V a t 10 kHz
m%mwm
MM 4- M t H- I I M M MM MM MM MM MM I in
Balanced V.. 0
AM V„ 0
— ;A / \ /
FIGURE 12-13 Comparison of balanced modulation and standard AM from

Fig. 12-11.
12-9 DEMODULATING AN A M VOLTAGE
D em odulation, or detection, is the process o f recovering a m odulating signal Em from the

m odulated output voltage V0. To accom plish this, the AM m odulated w ave is applied to
the y input o f a m ultiplier as show n in Fig. 12-14. Each y input frequency is m ultiplied
by the x input carrier frequency and generates a sum and difference frequency as show n
Modulator (AM)
of Fig. 12-11 10 k a
A A /V
354
FIG U RE 12-15 Voltage waveforms in an amplitude modulator and demodulator

( f c = 10 kHz, f m = 1 kHz).
Balanced modulator
of Fig. 12-9 or 12-11(a) 10
------------ v w
FIGURE 12-16 Demonstration of balanced modulator and demodulator with wave

shapes.
356 Chapter 12
12-10 DEMODULATING A BALANCED MODULATOR VOLTAGE ______________________
M odulating signal E m is recovered from a balanced m odulator by means o f the same tech
nique em ployed in Fig. 12-14 and Section 12-9. The only difference is the absent carrier fre
quency of 10 kHz at the dem odulator’s y input. This missing 10 kH z also elim inates both the
dc and 20-kHz term in V^. The circuit arrangem ent in Fig. 12-16 was built to dem onstrate
the dem odulating technique and show the resulting waveshapes. The dem odulated Em is not
a pure sine wave because only a sim ple filter was used. I f f c is increased to 100 kHz, Em will
be closer to being a pure sine wave. The carrier’s frequency fed into the dem odulator should
be exactly equal to the carrier frequency driving the modulator.
12-11 SINGLE-SIDEBAND MODULATION AND DEMODULATION ____________________
In the balanced m odulator o f Figs. 12-9 and 12-10, we could add a high-pass filter (see
C hapter 11) to the m o dulator’s output. If the filter rem oves all the low er side frequencies,
the output is single sideband (SSB). If the filter only attenuates the low er side freq u en
cies (to leave a vestige of the low er sideband), we have a vestigial sideband m odulator.
A ssum e that only one m odulating frequency f m is applied to our single-sideband
m odulator together with carrier f c. Its output is a single, upper side frequency f c + f m. To
dem odulate this signal and recover f m, all we have to do is connect the SSB signal f c +
f m to one m ultiplier input a n d / c to the other input. A ccording to the principles set forth
in Section 12-7.4, the dem odulator’s output w ould have a sum frequency o f ( f c + / m) +
f c and a difference frequency o f ( f c + f m) — f c = f n- A low -pass filter w ould recover the
m odulating signal f m and easily elim inate the high-frequency signal, w hose frequency is
2 f c + fm-
12-12 FREQ U EN CY SHIFTING _______________________________________________________________
In radio com m unication circuits, it is often necessary to shift a carrier frequency f c with
its accom panying side frequencies dow n to a low er interm ediate frequency f lF. T his shift
o f each frequency is accom plished w ith the m ultiplier connections o f Fig. 1 2 -17(a). T he
m odulated carrier signals are applied to the y input. A local oscillator is adjusted to a fre
quency f Q equal to the sum o f the carrier and desired interm ediate frequency and applied
to the x input. The frequencies present in the output o f the m ultiplier are calculated in the
follow ing exam ple.
Example 12-11
In Fig. 12-17(a) am plitudes and frequencies o f an AM m odulated wave are present at each
input as follow s:
y input:
Peak am plitude (V) Frequency (kHz)
( f c + f „ ) = 1005
4 fc
= 1000
(/C- / J = 995
w here f c is the broadcasting station’s carrier frequency and ( f c + / m) and ( f c - f m) are the
upper and low er side frequencies due to a 5-kH z m odulating frequency, and 1000-kH z car
rier frequency.
jt input: T he local oscillator is set for a 5-V-peak sine wave at 1445 kHz, because the
desired interm ediate frequency is 455 kHz.
Find the peak value and frequency of each signal com ponent in the output o f the
m ultiplier.
S olution From Eq. (12-12), the peak am plitude o f each y input frequency is m ultiplied by
the peak am plitude of the local oscillator frequency. This product is m ultiplied by ^ ( ^ for
the scale factor X { from the trigonom etric identity) to obtain the peak am plitude o f the re
sulting sum and difference frequencies at the m ultiplier’s output. T he results are tabulated
in Fig. 12-17.
All frequencies present in the m ultiplier’s output are plotted on the frequency spectrum
o f Fig. 12- 17(c). A low -pass filter or band-pass filter is used to pass only the three low er in
term ediate frequencies o f 450, 455, and 460 kHz. The upper interm ediate frequencies o f
2450, 2455, and 2460 kH z may be used if desired, but they are usually filtered out.
We conclude from E xam ple 12-11 that each frequency present at the y input is shifted
down and up to new interm ediate frequencies. The low er set o f interm ediate frequencies
can be extracted by a filter. Thus, the inform ation contained in the carrier f c has been pre
served and shifted to another subcarrier or interm ediate frequency. T he process o f fre
quency shifting is also called heterodyne. The heterodyne principle will be used in Section
12-13 to construct a universal AM receiver that will dem odulate standard A M , and bal
ance m odulator and single-sideband signals.
M odulated
S ee(b)
Local oscillator
(a) Circuit for a frequency shifter.
FIGURE 12-17 The multiplier as a frequency shifter

358 Chapter 12
Multiplier output
Frequency at Frequency
Peak (V) (kHz)
y input (kHz)
1005 1455+ 1005 = 2460

T - 0-25 1455-1005 = 450
1000 1455+ 1000 = 2455

1i r " ° 1455- 1000= 455
995 ^ = 0.25 1455 + 995 = 2450

1455 -9 9 5 = 460
(b) Frequencies present in multiplier output.
o
>
tN I <N
l _L_ 1 1 1 1 1 > /(kHz)
-fr
flF fo
y input
(c) The y input frequencies are shifted to the intermediate frequency.
FIG U RE 12-17 {com.)
12-13 UNIVERSAL AMPLITUDE MODULATION RECEIVER
12-13.1 Tuning and Mixing
T he ordinary autom obile or household AM radio can receive only standard A M signals
that occupy the AM broadcast band, about 500 to 1500 kH z. This type o f radio receiver
cannot extract the audio or data signals from single-sideband (CB) or suppressed carrier
transm ission.
F igure 12-18 shows a receiver that will receive any type o f AM transm ission, ca r
rier plus sidebands, sidebands w ithout carrier, or a single sideband (either up p er o r lower).
To understand its operation, assum e that a station is transm itting a 5-kH z audio signal that
m odulates a 1005-kHz carrier wave. The station transm its a standard AM frequency sp ec
trum of the 1005-kHz carrier and both low er and upper side frequencies o f 1000 kH z and
1010 kH z [see Fig. 12- 18(a)].
Station 1005-k H z transmitter
1000 kHz LSF

Audio
Dc + 5 kHz 1005 kHz CAR
1010 kHz USF
AM band (a) Standard AM station broadcasting a 5-kHz signal on a carrier of 1005 kHz.
500 to
1600 kHz
Tuner, tuned 2460 kHz LSF Aud

to 1005-kHz IF mixer IF amp detec
carrier multiplier 2465 kHz IF, 455 kHz multip
LSF 2470 kHz USF
1000 kHz 460 kHz LSF
K
1005 kHz
1010 kHz
x 460 kHz LSF
455 kHz IF A 455 kHz IF
450 kHz USF
-----
>
v Bandwidth
10 kHz
USF T
1005 +455 kHz =
450 kHz USF Bandwidth
10 kHz IF = 45'
A 915 kHz LSF
1460 kHz 910 kHz IF,
Low-pass
Filter 905 kHz USF
5 kHz LSF
Audio 1 V at 5 kHz LSF
5 kHz
{ 0 Hz
1 V at 5 kHz USF 0-5 kHz
0 CxR
5 kHz USF
(b) Universal AM receiver frequency distribution.
FIGURE 12-18 The superheterodyne receiver in (b) can demodulate or detect audio
signals from the standard AM transmission in (a) and also single-sideband or suppressed
359
carrier AM.
360 Chapter 12
In Fig. 12-18(b) the receiver’s tuner is tuned to select this one sta tio n ’s 10-kHz band
o f frequencies out of the entire broadcast band o f frequencies that are present on the re
ceiver’s antenna. A local oscillator in the radio is designed to produce a signal that tracks
the tuner and is alw ays 455 kH z higher than the tuner frequency. T he oscillato r and tuner
output frequencies are m ultiplied by the IF mixer. T he IF m ixer acts as a frequency shifter
to shift the incom ing radio-frequency carrier down to an interm ediate-frequency (IF) car
rier o f 455 kHz.
12-13.2 Intermediate-Frequency Amplifier
T he o utput o f the IF m ixer contains both sum frequencies (2465-kH z IF2 carrier) and d if
ference frequencies (455-kH z IF carrier). O nly the difference frequencies are am plified
by the tuned high-gain IF amplifier. T his first frequency shift (heterodyning) is perform ed
so that m ost o f the signal am plification is done by a single narrow band tuned-IF am pli
fier that usually has three stages o f gain. A n y station carrier that is selected by the tuner
is shifted by the local oscillator and m ixer m ultiplier dow n to the IF frequency for am
plification. T his frequency dow nshift schem e is used because it is m uch easier to build a
reliable narrow band IF am plifier (10-kH z bandw idth centered on a 4 5 5-kH z carrier) than
it is to build an am plifier that can provide equal am plification of, a n d select 10-kHz band-
w idths over, the entire AM broadcast band.
12-13.3 Detection Process
The output o f the IF am plifier is m ultiplied by the IF frequency in the audio d etecto r m u l
tiplier. T he term detection m eans that we are going to detect or dem odulate the audio sig
nal from the 455-kH z IF carrier. T he audio detector shifts the incom ing IF carrier and side
frequ en cies up and dow n as sum and d ifference frequencies. O nly the d ifference fre
quencies are transm itted through the low -pass filter in Fig. 12-18(b). T he astute reader
w ill note that the low -pass filte r output frequencies are not labeled ( + ) 5 kH z for the up
per side frequency and ( —) 5 kH z for the low er side frequency. If you w ork the m ath e
m atics out using sine waves for audio, carrier, local oscillator, and IF signals, it turns out
that both audio 5-kH z signals are in phase (as negative cosine w aves). T he output o f the
low -pass filter is applied to an audio am plifier and finally to a speaker.
12-13.4 Universal A M Receiver
W hy w ill this receiver do w hat m ost other receivers cannot do? T he previous sections
dealt w ith a standard AM transm ission carrier plus both upper and low er side frequencies.
Suppose that you elim inated the 1005-kH z carrier at the transm itter in Fig. 12-18(a). N ote
how the carrier is identified by enclosure in a rectangle as it progresses through the re
ceiver in Fig. 1 2 -18(b). If no carrier enters the receiver, but only the side frequencies, both
audio signals (U SF and LSF) w ill still enter the audio am plifier. T hus this receiver can
recover audio inform ation from either standard AM or balanced A M m odulation. An AM
car radio w ill not recover the audio signal from balanced AM transm issions.
N ext suppose that you elim inated (by filters) the carrier and upper side frequency
from the transm itter in Fig. 12-18(a); only the low er side frequency o f 1000 kH z would
be broadcast. T he entire low er sideband would occupy 1000 to 1005 kHz. This is sin g le
sideband transm ission. A t the receiver, the tuner w ould select 1000 kH z (to 1005 kHz).
The IF am plifier would output 460 kH z (to 455 kHz). Finally, the low -pass filter would
output 5 kH z (to 0 kH z); thus this receiver can also receive single-sideband transm ission.
The versatility o f this type o f receiver is inherent in the design. It requires no sw itches to
activate circuit changes for different types o f AM m odulation.
PROBLEMS _________________________________________________________________________
12-1. Find V0 in Fig. 12-1 for the following combination of inputs: (a) x = 5 V, y = 5 V; (b)
x = - 5 V, y = 5 V; (c) x - 5 V, y = - 5 V; (d) x = - 5 V, y = - 5 V.
12-2. State the operating point quadrant for each combination in Problem 12-1 [see Fig. 12-2(a)].
12-3. What is the name of the procedure used to make VQ = 0 when both x and y inputs are at 0 V?
12-4. Find V0 in Fig. 12-3 if E, = - 3 V.
12-5. The peak value of £, in Fig. 12-4 is 8 V, and its frequency is 400 Hz. Evaluate the output’s
(a) dc terms; (b) ac term.
12-6, In Fig. 12-5, Exp = 10 V, Eyp = 10 V, and 0 = 30°. Find V0.
12-7. Repeat Problem 12-6 for 0 = - 30°.
12-8. Ex = 10 V and £ in = - 1 V in Fig. 12-6. Find V0.
12-9. In the balanced modulator of Fig. 12-9, Ex is a 15-kHz sine wave at 8-V peak and Ey is a
3-kHz sine wave at 5-V peak. Find the peak voltage of each frequency in the output.
12-10. In Fig. 12-9, the carrier frequency is 15 kHz. The modulating frequencies range between 1
and 2 kHz. Find the upper and lower side bands.
12-11. The switch is on AM in Fig. 12-11. The modulating frequency is 10 kHz at 5-V peak. The
carrier is 100 kHz at 8-V peak. Identify the peak value and each frequency contained in the
output.
12-12. If the switch is thrown to “Balanced’’ in Problem 12-11, what changes result in the output?
12-13. The x input of Fig. 12-14 is three sine waves of 5 V at 20 kHz, 2.0 V at 21 kHz, and 2.0 V at
19 kHz. The y input is 5 V at 20 kHz. What are the output signal frequency components?
12-14* You need to shift a 550-kHz signal to a 455-kHz intermediate frequency. What frequency
should be generated by the local oscillator?
CHAPTER 13
Integrated-Circuit Timers
U pon com pletion of this chapter on integrated-circuit tim ers, you w ill be able to:
■ N am e three operating states of a 555 tim er and tell how they are con tro lled by the trig
ger and threshold term inals.
• D raw circuits that produce a tim e delay or an initializing pulse upon application o f power.
• C onnect the 555 to m ake an oscillator for any desired frequency.
• U se 555 oscillators to make a tone-burst oscillator or voltage-controlled frequency shifter.
• Explain the operation o f a 555 w hen it is w ired to perform as a one-shot or m onostable
multivibrator.
• U se the 555 one-shot as a touch sw itch, frequency divider, or m issing pulse detector.
• D escribe the operation o f an X R 2240 program m able tim er/counter.
• C onnect the X R 2240 as a long-interval tim er, free-running oscillator, binary p attern
generator, or frequency synthesizer.
362
A long with the 555 tim er, there are also available counter tim ers such as E x ar’s
X R 2240. T he 2240 contains a 555 tim er plus a program m able binary counter in a single
16-pin package. A single 555 has a m axim um tim ing range o f approxim ately 15 m inutes.
C ounter tim ers have a m axim um tim ing range o f days. The tim ing range o f both can be
extended to m onths or even years by cascading. O ur study o f tim ers will begin with the
555 and its applications and then proceed to the counter tim ers.
13-1 OPERATING M O DES OF THE 555 TIMER ___________________________________________
T he 555 IC tim er has two m odes of operation, either as an astable (free-running) m ulti
vibrator or as a m onostable (one-shot) m u ltiv ib rato r F ree-running operation o f the 555 is
show n in Fig. 13-2(a). T he output voltage sw itches from a high to a low state and back
again. T he tim e the output is either high or low is determ ined by a resisto r-cap acito r n et
w ork connected externally to the 555 tim er (see Section 13-2). T he value o f the high o u t
put voltage is slightly less than Vc c . The value o f the output voltage in the low state is
approxim ately O.l V.
W hen the tim er is operated as a one-shot m ultivibrator, the output voltage is low
until a negative-going trigger pulse is applied to the tim er; then the output sw itches high.
T he tim e the output is high is determ ined by a resistor and cap acito r connected to the IC
timer. At the end o f the tim ing interval, the output returns to the low state. M onostable
operation is exam ined further in Sections 13-5 and 13-6. To understand how a 555 tim er
operates, a brief description o f each term inal is given in Section 13-2.
366 Chapter 13
13-2.2 Output Terminal
A s show n in Figs. l3-3(b) and (c), the output term inal, pin 3, can either source or sink
current. A flo a tin g supply load is on w hen the output is low, and o ff w hen the output is
high. A grounded load is on w hen the output is h ig h and o ff w hen the output is low. In
norm al operation either a supply load or a grounded load is connected to pin 3. M ost ap
plications do not require both types of loads at the sam e tim e.
T he m axim um sink or source current is technically 200 mA, but m ore realistically
is 40 mA. T he high output voltage [Fig. 13-3(c)] is about 0.5 V below Vc c , a°d the low
output voltage [Fig. 13-3(b)] is about 0.1 V above ground, fo r load currents below 25 mA.
13-2.3 Reset Terminal
T he reset term inal, pin 4, allow s the 555 to be disabled and override com m and signals on
the trigger input. W hen not used, the reset term inal should be w ired to + V CC. If the re
set term inal is grounded or its potential reduced below 0.4 V, both the output term inal,
pin 3, and the discharge term inal, pin 7, are at approxim ately ground potential. In other
w ords, the output is held low. If the output was high, a ground on the reset term inal im
m ediately forces the output low.
13-2.4 Discharge Terminal
The discharge term inal, pin 7, is usually used to discharge an external tim ing capacitor
during the tim e the output is low. W hen the output is high, pin 7 acts as an open circuit
and allow s the capacitor to charge at a rate determ ined by an external resistor or resistors
and capacitor. Figure 13-4 show s a m odel o f the discharge term inal fo r w hen C is d is
charging and for w hen C is charging.
13-2.5 Control Voltage Terminal
A 0.01 - j j l F filter capacitor is usually connected from the control voltage term inal, pin 5,
to ground. The capacitor bypasses noise and/or ripple voltages from the pow er supply to
m inim ize their effect on threshold voltage. The control voltage term inal m ay also be used
to change both the threshold and trigger voltage levels. For exam ple, co nnecting a 1 0-kfl
resistor betw een pins 5 and 8 changes threshold voltage to 0.5 VCc and the trigger volt
age to 0.25 Vc c . An external voltage applied to pin 5 will change both threshold and trig
ger voltages and can also be used to m odulate the output w aveform.
13-2.6 Trigger and Threshold Terminals
T he 555 has tw o possible operating states and one m em ory state. They are determ ined by
both the trigger input, pin 2, and the threshold input, pin 6. T he trigger input is com pared
by com parator 1 in Fig. 13-1, w ith a low er threshold voltage VLT that is equal to Vc c /3.
T he threshold input is com pared by com parator 2 w ith a higher threshold voltage VUT that
368 Chapter 13
TABLE 13-1 OPERATING STATES OF A 555 TIMER: VUT= 2l/cc/3,

VLT= Vcc/ 3; HIGH - Vcc. LOW OR GROUND - 0 V
State of term inals

Operating Trigger Threshold
state pin 2 pin 6 Output 3 Discharge 7
A Below VLT Below Vv r High Open '

B Below VLT Above VUT High Open
C Above VLT Below VUT Remembers last state
D Above VLT Above V ut Low Ground
A visual aid in understanding how these operating states occur is presented in Fig.
13-5. An input voltage Et is applied to both trigger and threshold input term inals. W hen
Ei is below VLT during time intervals A - B and E-F, state A operation results, so that out
put VDy is high. W hen £, lies above VLT but below VUT> w ithin tim e B -C , the 555 enters
state C and rem em bers its last A state. W hen Et exceeds VUTy state D operation sends the
output low. W hen E t drops betw een Vu r and VLT during tim e D -E , the 555 rem em bers
the last D state and its output stays low. Finally, w hen £, drops below VLT during tim e
E-F, the A state sends the output high.
By plotting output V03 against E t in Fig. 13-5, w e see a hysteresis characteristic.
Recall from C hapter 4 that a hysteresis loop m eans that the circuit has memory. This also
m eans that if the inputs are in one of the m em ory states, you cannot tell w hat state the
output is now in, unless you know the previous state. Two pow er-on applications will now
be given to show how to analyze circuit operation from Table 13-1.
13-2.7 Power-on Time Delays
There are tw o types o f tim ing events that may be required during a pow er-on application.
You may wish to apply pow er to one part of a system and w ait for a short interval before
starting som e other part of a system . For exam ple, you may need to reset all counters to
zero before starting a personal com puter at the beginning o f a business day. A circuit that
solves this problem is show n in Fig. 13-6(a). W hen the pow er sw itch is throw n to on at
t = 0, the initial capacitor voltage is zero. T herefore, both pins 2 and 6 are above their re
spective thresholds and the output stays low in operating state D. As capacitor C charges,
the threshold drops below VUT w hile the trigger is still above VLT> forcing the 555 into
m em ory state C. Finally, both trigger and threshold drop ju st below VLTf w here the 555
enters state A and forces the output high at tim e T.
T he net result is that an output from pin 3 o f the 555 is delayed for a tim e interval
7 after the sw itch closure at / = 0. The tim e delay is found from 7 = 1 . 1 RAC.
By interchanging RA and C, a tim e delay with a high output can be generated. In the
circuit of Fig. 13-6(b), pow er is applied to a system when the sw itch is closed. The 5 5 5 ’s
output goes high for a period o f time 7 and then goes low. 7 is found from Eq. (13-9). This
type of startup pulse is typically used to reset counters and initialize com puter sequences
after a power failure. It also can allow tim e before arm ing an alarm system so that an op
erator can exit after the system has been turned on.
Integrated-Circuit Tim ers
+15 V
state state
FIGURE 13-5 Three of the four operating states of a 555 timer are shown by a test cir
cuit to measure E, and V0y versus time and V0x versus Eh
Integrated-Circuit Tim ers 371
13-3 FREE-RUNNING OR ASTABLE OPERATION
The 555 is connected as a free-running m ultivibrator in Fig. 13-7(a). R efer to the w ave
shapes in Fig. 13-7(b) to follow the circu it’s operation. At tim e A both pins 2 and 6 go
just below VLT = { Vc c and output pin 3 goes high (state A). Pin 7 also becom es an open,
so capacitor C charges through RA + R B. D uring output high tim e A - B , the 555 is in
m em ory state C, rem em bering the previous A state. W hen Vc goes ju st above VUT =
f Vc c at tim e B} the 555 enters state D and sends the output low. Pin 7 also goes low and
capacitor C discharges through resistor RB. D uring output low tim e B -C , the 555 is in
m em ory state C, rem em bering the previous state D. W hen Vc drops ju st below VLT, the
sequence repeats.
The output stays high during the tim e interval that C charges from y Vc c to j Vc c as
show n in Fig. 13-7(b). T his tim e interval is given by
*high — 0.695(7^ + R b )C (13-1)
T he output is low during the tim e interval that C discharges from f Vc c to { VCc an ^ is
given by
/,ow = 0.695 R bC (13-2)
T hus the total period o f oscillation T is
T = thlgh + f,ow = 0.695(R a + 2 R b)C (13-3)
T he free-running frequency o f oscillation / is
1 1 44
f = ~ = ------------------- (13-4)
J T (Ra -h 2R b)C K J
Figure 13-7(c) is a plot of Eq. (13-4) for different values o f (RA + 2R B)and quickly shows
w hat com binations o f resistance and capacitance are needed to design an astable m ultivi
brator.
E x a m p le 13-1
C alculate (a) /high, (b) /]OW, and (c) the free-running frequency for the tim er circuit o f Fig.
13-7(a).
*high = 0.695(6.8 k f l + 3.3 kfl)(0 .1 / jlF ) = 0.7 ms

13-4.2 Voltage-Controlled Frequency Shifter
A low -cost, low -freq u en cy v o lta g e-co n tro lled freq u en cy sh ifte r is p resen ted in Fig.
13-10(a). Since the 555 tim er is pow ered by Vc c = 5 V, VUT = 5 V (f) and VLT = 5 V({).
C apacitor voltage Vc will charge to VUT at w hich tim e the 555 will ground pin 7 to rapidly
discharge C to VLT. Then the discharge path for C is disconnected. T he voltage w aveshape
described for C is show n in Fig. 13 -10(c).
C apacitor C is charged by a constant current I. I is set by the voltage across R E and
the value of R E. T he voltage across R E is determ ined by the difference betw een the 15-V
supply and the voltage at pin 2 (10 V — E) o f voltage follow er 7415. T hus VRE = 15 -
(10 — E) = 5 V + E. Pin 2 follow s pin 3 o f op am p B, or VoA. The inverting adder, 741A,
has an output voltage of VoA = 10 - E.
T he charge lost by C for each cycle equals C(AVc ) w here AVC = 5 V(f) - 5 V(^) =
5 V/3. C harge stored by C equals charge current I tim es period T (the charge tim e). For
equilibrium
charge stored = charge lost ( 13-8a)
IT = C A V 3-8b)
13-8c)
Since period T = 1//olU, we can rew rite Eq. (13-8c) as
/out = center frequency f c + shift frequency A / (13-8d)
w here
f c — —- — w hen E = 0 V ( I 3-8e)
Re C
and
± f = 0 . 2 f cE ( 13-80
This reasoning will be clarified by an exam ple.
E x a m p le 13-3
For the frequency shifter of Fig. J3-10 calculate (a) the charge current / for E = 0 V; (b)
the center frequency f c w hen E — 0 V; (c) the frequency shift for E = ± 1 V and / out. (d)
Point out the positive and negative lim its for Eh
S o lu tio n (a)
378 Chapter 13
(b) From Eq. (13-8e), when E = 0,
fe Re C (3 k f l)( l X 10-6 F)
T herefore, / out = 1 kH z w hen E — 0.
(c) From Eq. (13-8f),
A / = 0.2f cE = 0.2(1000)1 = 200 Hz
/out = / c + A / = 1000 + 200 H z = 1200 Hz [see Fig. 13-10(b), point A]. For E = - 1 V,
then, A / = - 2 0 0 Hz and f oul - 800 Hz [see Fig. 13-10(b), point £ ].
(d) Pin 2 of 741B cannot go closer to the 15-V supply voltage than about 1 V. This re
stricts the low er lim it o f E to about - 4 V and / out to 200 Hz. o f the transistor
needs about 2 V headroom above VUT = 3.3 V, so the upper lim it o f E is about + 4 V,
w here
In sum m ary, the 555 oscillates at a center frequency f c determ ined by Eq. (13-8e).
E increases or decreases this center frequency by an am ount o f 0.2 f c per volt for positive
and negative values of E , respectively.
13-5 ONE-SHOT OR MONOSTABLE OPERATION _______________________________________
13-5.1 Introduction
N ot all applications require a continuous repetitive wave such as that obtained from a free-
running m ultivibrator. M any applications need to operate only for a specified length o f
tim e. T hese circuits require a one-shot or m onostable m ultivibrator. F igure 1 3 -11(a) is a
circuit diagram using the 555 for m onostable operation. W hen a negative-going pulse is
applied to pin 2, the output goes high and term inal 7 rem oves a short circuit from capac
itor C. T he voltage across C rises from 0 volts at a rate determ ined by RA and C. W hen
capacitor voltage reaches \ Vc & com parator 1 in Fig. 13-1 causes the output to sw itch
from high to low. The input and output voltage w aveform s are show n in Fig. 1 3 -1 1(a).
T he output is high for a tim e given by
(13-9)
Figure 13-11(b) is a plot of Eq. (13-9) and quickly show s the w ide range o f output pulses
that are obtainable and the required values o f R A and C. Figure 1 3 -11(a) gives the idea o f
a one-shot. In practice we m ust add m ore parts to m ake a w orkable circuit (see Section
13-5.2).
(b) By Eq. (13-2),

/low = 0.695(3.3 kfl)(0.1 fxF) = 0.23 ms
(c) By Eq. (13-4),
1.44
/ = 1.07 kH z
[6.8 k f t + (2)(3.3 kft)][0.1 jjlF]
T he answ er to part (c) agrees w ith results obtainable from Fig. 13-7(c).
13-3.3 Duty Cycle
The ratio of tim e w hen the output is low, /)ow, to the total period T is called the duty c y
cle D. In equation form,*
Q _ ^low _ ( l 3-5)
r ra + 2rb
The next section presents an inexpensive way o f extending the duty cycle.
E x am p le 13-2
C alculate the duty cycle for the values given in Fig. 13-7(a).
S o lu tio n By Eq. (13-5),

3.3 kH
D = = 0.25
6.8 k f t + 2(3.3 k fl)
T his checks with Fig. 13-6(b), w hich shows that the tim er’s output is low for approxi
m ately 25% o f the total period T Equation (13-5) shows that it is im possible to obtain a
duty cycle o f 7, or 50% . As presented, the circuit o f Fig. 13-7(a) is not capable o f produc
ing a square wave. T he only way D in Eq. (13-5) can equal 7 is for RA to equal 0. Then
there w ould be a short circuit betw een Vc c and pin 7. However, R A m ust be large enough
so that w hen the discharge transistor is “on,” current through it is lim ited to 0.2 A. Thus
the m inim um value o f RA in ohm s is given by
Vr c
m inim um RA — --------- (13-6)
* 0.2 A
In practice, keep RA equal to or greater than 1 kCt
*The original literature published by Signetics (the maker of the 555) defined duty cycle as shown. We
go along with the originator in this chapter. In most other texts and papers, duty cycle is expressed, in percent,
as the ratio of high time to period.
*high = 0.695Ra C (13-7a)
t]ow = 0.695R BC ( 13-7b)
T = 0.695(R a + Rb)C (13-7c)
E quations (13-7a) and (13-7b) show that if RA = /?#, then the duty cycle is 50% , as shown
in Figs. 13-8(b) and (c).
13-4 APPLICATIONS OF THE 555 A S AN ASTABLE MULTIVIBRATOR
13-4.1 Tone-Burst Oscillator
With the sw itch in Fig. 13-9 set to the “continuous” position, the B 555 tim er functions
as a free-ru n n in g m ultivibrator. T he frequency can be varied from ab o u t 1.3 kH z to
14 kH z by the 10-kH potentiom eter. If the potentiom eter is replaced by a therm istor or
photoconductive cell, the oscillating frequency will be proportional to tem perature or light
intensity, respectively.
The A 555 tim er oscillates at a slower frequency. T h e 1-MH potentiom eter sets the
lowest frequency at about 1.5 Hz. Lower frequencies are possible by replacing the l-ûF ca
pacitor with a larger value. W hen the connecting switch is thrown to the “burst” position,
output pin 3 of the A tim er alternately places a ground or high voltage on reset pin 4 o f the
B 555 timer. W hen pin 4 of the B tim er is grounded, it cannot oscillate, and when ungrounded
the tim er oscillates. This causes the B tim er to oscillate in bursts. The output o f the tone-burst
generator is V0 and is taken from pin 3 of tim er B . V0 can drive either an audio am plifier or
a stepdown transform er directly to a speaker. The 556 IC tim er contains two 555 timers in a
single 14-pin dual-in-line package. Thus the tone-burst generator can be made with one 556.
This circuit is modeled and its perform ance is sim ulated in Section 13-11.
cc
A
l kD. io kn
7 4 8 8 7
Continuous
555 . 555
l MO : 6 a 3 4 B 6
burst 2
2 l 1 3
1 |iF
V
F IG U R E 13-9 Tone-burst oscillator.
!ntegrated-Circuit Tim ers 381
mally low. Cz is charged to (Vc c - Ez) until the negative-going trigger pulse occurs. The time
constant of R , and C, should be small with respect to the output timing interval rhigh. Diode
D prevents the 555 tim er from triggering on positive-going edges o f £,. W aveforms for the
input pulse, Eh the pulse at pin 2, V2, and the output pulse, VOJ are all shown in Fig. 13-12.
E x a m p le 13-5
(a) If Ra = 10 and C = 0.2 jjlF in Fig. 13-12, find rhigh. (b) W hat is the tim e constant
o f Rj and C, in Fig. 13-12?
'high = 1-1(10 X 103)(0.2 X 10“ 6) = 2.2 ms
(b) T im e constant = tf/C, = (10 X 103)(0.001 X 10~6) = 0.01 ms.

Just as with astable operation, reset term inal pin 4 is norm ally tied to supply voltage
Vc c . If pin 4 is grounded at any tim e, the tim ing cycle is stopped. W hen the reset term inal
is grounded, both output pin 3 and discharge term inal 7 go to ground potential. T hus the
output goes low and any charge accum ulated by the tim ing capacitor C is rem oved. As long
as the reset term inal is grounded, these conditions rem ain.
13-6 APPLICATIONS OF THE 555 A S A ONE-SHOT MULTIVIBRATOR ________________
13-6.1 Water-Level Fill Control
In Fig. 13-13(a), the start sw itch is closed and the output o f the 555 is low. W hen the start
sw itch is opened, the output goes high to actuate the pump. T he output is high for a tim e
interval given by Eq. (13-9). U pon com pletion o f the tim ing interval, the output o f the
555 returns to its low state, turning the pum p off. T he height o f the w ater level is set by
the tim ing interval, w hich is set by R a and C. In the event o f a potential overflow, the
overfill sw itch m ust place a ground on reset pin 4, w hich causes the tim er’s output to go
low and stops the pum p.
13-6.2 Touch Switch
The 555 is w ired as a one-shot m ultivibrator in Fig. 13-13(b) to perform as a touch switch.
A 22-M O resistor to pin 2 holds the 555 in its idle state. If you scuff your feet to build
up a static charge, the 555 will produce a single-shot output pulse w hen you touch the
finger plate. If the electrical noise level is high (due, for exam ple, to fluorescent lights)
the 555 may oscillate w hen you touch the finger plate. R eliable and consistent triggering
Integrated-Circuit Timers 383
terval given by Eq. (13-9) is rhigh = 1 . 1 ms. T herefore, the one shot w ill be triggered by
the first negative-going pulse o f E h but the output w ill still be high w hen the second neg
ative-going pulse occurs. T he one-shot will, however, be re-triggered on the third nega
tive-going pulse. In this exam ple, the one-shot triggers on every other pulse o f E h so there
is only one output for every two input pulses; thus E, is divided by 2.
Example 13-6
(a) C alculate the tim ing interval in Fig. 13-12 if R A = 10 k f l and C = 0.1 fuF.
(b) W hat value o f RA should be installed to divide a 1-kHz input signal by 3?
S o lu tio n (a) By Eq. (13-9), /high = 1.1(10 X 103)(0.1 X 1 (T 6) = 1.1 ms. (b) /high should
exceed tw o periods o f E h or 2 ms, and be less than three periods (3 ms). C hoose /high = 2.2
ms; then 2.2 ms = 1 . 1 ^ X 0.1 X 10-6 F; R A = 20 k fl.
13-6.4 Missing Pulse Detector
Transistor Q is added to the 555 one-shot in Fig. 13-14(a) to m ake a m issing pulse detec
tor. W hen Ei is at ground potential (0 V), the em itter diode of transistor Q clam ps capaci
tor voltage Vc to a few tenths of a volt above ground. The 555 is forced into its idle state
V FIGURE 13-14 Missing pulse

(a) Circuit. detector.
384 Chapter 13
Missing pulse
4 V-
/
5 V-
5 V-
(b) Voltage waveforms.
FIG U RE 13-14 (,cont.)
w ith a high output voltage V0 at pin 3. W hen £, goes high, the transistor cuts off and ca
pacitor C begins to charge. This action is show n by the waveshapes in Fig. 13-14(b). If E {
again goes low before the 555 com pletes its tim ing cycle, the voltage across C is reset to
about 0 V. If, however, E t does not go low before the 555 com pletes its tim ing cycle, the
555 enters its norm al state and output VQ goes low. This is exactly w hat happens if the
R a C tim ing interval is slightly longer than the period o f E t and E t suddenly m isses a pulse.
T his type o f circuit can detect a m issing heartbeat. If E t pulses are generated from a ro tat
ing w heel, this circuit tells w hen the wheel speed drops below a predeterm ined value. T hus
the m issing pulse detector circuit also perform s speed control and m easurem ent.
13-7 INTRODUCTION TO COUNTER TIM ERS
W hen a tim er circuit is connected as an oscillator and is used to drive a counter, the re
sultant circuit is a counter timer. Typically, the counter has m any separate output term i
nals. O ne output term inal gives one pulse for each period T o f the oscillator. A second
output term inal gives one output pulse for every two periods (27) o f the oscillator. A third
output term inal gives one output pulse fo r every four oscillator periods (47), and so on,
depending on the design of the counter. Thus each output term inal is rated in term s of the
basic oscillator period 7
S om e counters are designed so that their outputs can be connected together. T he re
sultant output pulse is the sum o f the individual output pulses. For exam ple, if the first,
second, and third output term inals are w ired together, the result is one output pulse for
every 17 + 2 7 -f 4 7 = 7 7 oscillator periods. A counter w ith this capability is said to be
program m able, because the user can program the counter to give one output pulse for any
com bination o f tim er outputs. O ne such program m able tim er/counter is E x ar's X R 2240.
This integrated-circuit device is representative o f the tim er/counter family, and som e o f
its features will be studied next. A nother tim er/counter is E x ar’s X R 2242 or its pin re
placem ent from Harris Sem iconductor, the ICM 7242. This device is a long-range fixed
timer. The tim ing can be set from m icroseconds to days and is cascadable. The device is
housed in an 8-pin m ini-D IR
13-8 THE X R 2240 PROGRAM MABLE TIMER/COUNTER
13-8.1 Circuit Description
As shown in Fig. 13-15, the X R 2240 consists o f one modified 555 timer, one 8-bit binary
counter, and a control circuit. They are all contained in a single 16-pin dual-in-line package.
A positive-going pulse applied to trigger input 11 starts the 555 tim e base oscilla
tor. A positive-going pulse on reset pin 10 stops the 555 tim e base oscillator. T he thresh
old voltage for both trigger and reset term inals is about + 1 .4 V.
The tim e base period T for one cycle o f the 555 oscillator is set by an external R C
netw ork connected to the tim ing pin 13. T is calculated from
T = RC (13-10)
w here R is in ohm s, C in farads, and T in seconds. R can range from 1 kCi to 10 M Cl and
C from 0.05 to 1000 / j F . Thus the period o f the 555 can range from m icroseconds to hours.
o 14 (Time base output)
Reset
T= R x C
FIGURE 13-15 Block diagram of the XR 2240 programmable timer/counter.

ground w hile the other side is w ired to a 2 0 -k fl pull-up resistor. A regulated positive volt
age is available at pin 15. Each negative-going edge from the 555 steps the 8-bit counter
up by one count.
N orm ally, the 2240 is in its reset position. T hat is, all 8 output pins (pins 1 to 8)
act like open circuits, as shown by the output sw itch m odels in Fig. 13-16. P ull-up resis
tors (10 k f I) should be installed, as shown, to those term inals that are going to be used.
O utputs 1 and 4 w ill then be high in the reset condition.
W hen the 2240 is triggered (pulse applied to pin 1.1), all output sw itches o f the
counter are closed by the control circuit and outputs 1 to 8 go low. T hus the counter b e
gins its count w ith all outputs essentially grounded. A t the end o f every tim e base period,
the 555 steps the counter once. T he co u n ter’s T sw itch on term inal 1 opens after the first
tim e base period (output 1 goes high) and closes after the second tim e base period. This
counting action o f the tim er is show n in Fig. 13-16(b).
O utput pin 2 is labeled 2 T in Fig. 13-16(a). It is seen from Fig. 13-16(b) that the
output on pin 2 has stayed low for tw o tim e base periods (.2T). T hus the second output
stays low for tw ice the tim e interval of the first output. This conclusion may be g eneral
ized to all outputs o f the binary counter; that is, each output stays low for tw ice the tim e
interval o f the preceding output. T im e intervals for pins 1 to 5 are show n in Fig. 1 3 -16(b)
and are given for all outputs in Table 13-2.
TABLE 13-2 OUTPUT TERMINAL

TIME CHART
Terminal Time output stays low

num ber after trigger pulse
I 7
2 IT
3 4T
4 87
5 167
6 32 7
7 647
8 1287
E x a m p le 13-7
A fter triggering, how long will the follow ing output term inals stay low? (a) pin 3; (b) pin
4; (c) pin 7; (d) pin 8. R = 100 kH and C = 0.01 /jlF.
S o lu tio n By Eq. (13-10), the tim e base period is
T = (100 X 103)(0.01 X 10“ 6) = 1 ms

is low, V0 w ill be low. O nly w hen both outputs go high (output sw itches open) w ill the
output go high. T hus the tim ing cycle for the output bus is found sim ply by calculating
the sum 7 sum o f the individual outputs.
Example 13-8
C alculate the tim ing cycle for (a) Fig. 13-17(a); (b) a circuit w here pins 3, 6, and 7 are
jum pered to a com m on bus. Let 7 = I s .
S o lu tio n (a) 7 sum = 8 7 + 167 = 2 4 7 = 24 X 1 s = 24 s; (b) 7 sum = 4 7 + 3 2 7 + 6 4 7 =

1 0 0 7 = 100 X 1 s = 100 s.
By using sw itches instead o f ju m p e r w ires, 7 sum can be easily ch anged or p ro

gram m ed for any desired tim ing cycle from 7 to 2 5 5 7
13-9 TIMER/COUNTER APPLICATIONS ___________________________________________________
13-3.1 Timing Applications
The 2240 is w ired for m onostable operation in the program m able tim er application in Fig.
13-18. W hen the trigger input goes high, the output bus goes low for a tim ing cycle p e
riod equal to 7 siim (see Section 13-8.3). At the end o f the tim ing cycle, the output bus goes
high. T he connection from output bus via a 51-kH resistor to reset pin 10 forces the tim er
to reset itself w hen the output bus goes high. T hus after each trigger pulse, the 2240 gen
erates a tim ing interval selected by the program sw itches.
E x a m p le 13-9
In Fig.13-18, C = 1.0 /xF and R = 5 M H to establish a tim e base period given by Eq.(13
10) to be 5 s. W hat is (a) the tim ing cycle for switch positions shown in Fig. 13-18; (b) the
m inim um program m able tim ing cycle; (c) the m axim um program m able tim ing cycle?
S o lu tio n (a) 7 sum = 4 7 + 8 7 = 1 27 = 1 2 X 5 s = 6 0 s = l m in; (b) m inim um tim ing

cycle is 17 = 5 s; (c) with all program sw itches closed.
7 SUm = 7 + 2 7 + 4 7 + 8 7 4- 1 6 7 + 3 2 7 + 6 4 7 + 1 2 8 7 - 2 5 5 7
2 5 5 7 = 255 X 5 s = 1275 s = 21 min 15 s

1n i e g r m e o - u i v o u n M m c ia
pow er is applied, R r and CR couple a positive-going pulse into trigger input 11 to start
the internal tim e base oscillator running.
Each output is w ired through an external control sw itch to an individual pull-up re
sistor. A square-w ave output voltage is available at each counter output. T heir frequencies
have a binary relationship. T hat is, the frequency available at each pin is o n e-h alf the fre
quency present at the preceding pin. T he w aveshapes are identical to those in Fig. 13-
16(b). O bserve that the p erio d o f t h e / L frequency at pin 1 is tw ice the tim e base period
rating 7 or 2(7). T h u s /! = 1/271 A t pin 4, the period is 2(87) and f 4 = 1/167!
E x a m p le 13-10
In Fig. 13-19, 7 = 2.5 ms; w hat frequencies are present at (a) output 1; (b) output 2; (c)
output 3; (d) output 4?
S o lu tio n Tabulating calculations, we obtain:
Pin Time base

number rating Period Frequency (Hz)
1 7 27 - 5 ms 200
2 IT 4T= 10 ms 100
3 47 8T = 20 ms 50
4 87- 167 = 40 ms 25
T he connections to pins 10 and 11 may be rem oved to allow the oscillator to be

started with a positive-going trigger pulse at pin 11. To stop oscillation, apply a positive-
going pulse to reset pin 10.
13-9.3 Binary Pattern Signal Generator
Pulse patterns sim ilar to those show n in Fig. 13-20 are generated by a m odified version
of Fig. 13-19. The m odification requires the eight output resistors to be replaced by p ro
gram sw itches and a single 10-kfl resistor sim ilar to that show n in Fig. 13-18, and it elim
inates the 5 1 -k fl resistor betw een the output bus and the self-reset term inal.
T he output is a train o f pulses that depends on w hich program sw itches are closed.
T he period of the pulse pattern is set by the highest program sw itch that is closed, and
the pulse w idth is set by the lowest program sw itch that is closed. For exam ple, if the 4 7
(pin 3) and 17 (pin 1) sw itches are closed, the pulse pattern is repeated every 2 X 4 7 =
8 7 seconds (see Fig. 13-20). The m inim um pulse width is 17 To determ ine the actual
pulse pattern, refer to the tim ing chart in Fig. 13-16(b). If sw itches 1 7 and 4 7 are closed,
392 Chapter 13
Set minimum
pulse width
/
nriTTnnnnnn .
+V
Pin I output
0
A Period of output 8 7 = 2 x 4 7
--------- ''--------------- -
47 47
> Pin 3 output
Pulse pattern
on output bus
FIGURE 13-20 Binary pattern signal generator with outputs T and 4T con
nected to output bus.
there is an output pulse only w hen there are high output pulses from each line. T he re
peating pulse patterns are show n in Fig. 13-20.
13-9.4 Frequency Synthesizer
T he output bus in Fig. 13 -2 1(a) is capable o f generating any one o f 255 related frequen
cies. E ach frequency is selected by closing the desired program sw itches to program a
particular frequency at output V0.
To understand circuit operation, assum e that the output bus goes high. T his will
drive reset pin 10 high and couple a positive-going pulse into trigger pin 11. The reset
term inal going positive resets the 2240 (all outputs low). The positive pulse on pin 10 re
triggers the 2240 tim e base oscillator, to begin generation o f a tim e period that depends
on w hich program sw itches are closed. For exam ple, assum e that sw itches T and 4 T are
closed in Fig. 13-21(a). T he tim ing for these sw itches is show n in Fig. 1 3 -2 1(b). The o u t
put bus stays low for AT from pin 3 plus I T from pin 1 before going high (to initiate a
rese t-re trig g er sequence as noted above). The tim e period and frequency o f the output
signal VD are thus expressed by
period = 7 sum + T (13-1 l a )
and
1
/ = (13-1 lb )
period
w here 7 sum is found by adding the tim e base rating for each output term inal connected to
the output bus.
394 Chapter 13
S o lu tio n From Eq. (13-1 la ), 7 SUIT1 = 17 + 4 7 = 5 7 , and period = (7 sum + 7) = 6 7 :

6 X 1 ms = 6 ms. By Eq. (13-1 lb),
1
= 166 Hz
6 X 10“ 3 s
13-10 SW ITCH PROGRAM M ABLE TIMER
13-10.1 Timing Intervals
We close this chapter with a useful program m able timer. In the version o f Fig. 13-22, the
basic tim ing interval is adjusted for 7 = 5.0 s by tim ing capacitor C and tim ing resistor R.
A 16-pin, eight-circuit D IP sw itch is used to select the desired tim e interval, as show n in
E xam ple 13-9. C lose sw itch I for a 5-s timer. C losing S 2 adds 10 s, S 3 adds 20 s, and so
on. W ith all sw itches closed, the m axim um tim e interval is 2 8 X 5 s = 1280 s or 21 min
20 s. T he basic tim ing interval can be changed by picking new values for R and/or C.
S tart sw itch Ss is opened m om entarily, driving the trigger pin high to start the tim er. All
outputs o f the X R 2240 go low. T his low is extended by any closed select sw itch(es) 5]
through S%, to ( —) pin 2 o f the 301 com parator. T he 30 1 ’s output goes high to light LE D
D y and turn on transistor Q j. T he on-transistor energizes the relay, thus sw itching the co n
tacts from the N C position to the NO position. T his com pletes the pow er circuit to turn
on any appliance for the tim ing interval.
To turn o ff an appliance during the tim ing interval, sim ply m ove the ac com m on
w ire from term inal A o f the relay to term inal C. T he supply voltage m u st be regulated to
obtain repeatable results.
13-11 PSPICE SIMULATION OF 555 TIMER CIRCUITS
In this section, we will use PSpice and sim ulate the perform ance o f two tim ing circuits— the
astable m ultivibrator shown in Fig. 13-7(a) and the tone-burst circuit shown in Fig. 13-9.
13-11.1 Astable or Free-Running Multivibrator
R efer to Fig. 13-7(a) and create the PSpice m odel o f the 555 tim ing circuit. P lace the fo l
low ing parts on the right-hand side o f the w ork area.
FIGURE 13-22 Switch programmable timer. A basic time interval is set to T = 5 s by
R and C. Time select switches S\ through S8 determine how long the appliance load will
be turned on after momentary-open start switch Ss is depressed. Si = 5 s. S2 adds 10 s.
The remaining switches extend the time interval as shown above.
PROBLEMS __________________________________________________________________________
13-1. What are the operating modes of the 555 timer?
13-2. In Fig. 13-6(a), RA = RB = 10 kfl and C = 0.1 fiF. Find (a) ;high; (b) ;,ow; (c) frequency of
oscillation.
13-3. Using the graph of Fig. 13-7, estimate the free-running frequency of oscillation / i f (RA +
2Rb) = 1 MH and C = 0.02 fiF.
13-4. What is the duty cycle in Problem 13-2?
13-5. In Example 13-1 y RA and RB are increased by a factor of 10 to 68 kf) and 33 kCl. Find the
new frequency of oscillation.
13-6. In Fig. 13-8, RA and RB are each reduced to 5 kfl. What is the effect on (a) the duty cycle;
(b) the period T of the output?
13-7. In Fig. 13-9, at what value should the 10-kfl resistor be set for a 2-kHz output from the B
555?
13-8. Capacitor C is changed to 0.1 fiF in Fig. 13-10. Calculate (a) the center frequency f c when
E = 0 V; (b) the frequency shift for E = ± 2 V.
13-9. In Fig. 13-11 (a), RA = 100 kH and C = 0.1 f i ¥ .Find /high.
13-10. Ra is changed to 20 kfl in Example 13-5. Find /high.
13-11. In Example 13-6(b), what value of RA is required to divide a 1-kHz signal by 2?
13-12, Refer to Example 13-7. How long will the following output terminals stay low? (a) pin 1;
(b) pin 2; (c) pin 5; (d) pin 6.
13-13. In Fig. 13-16(a), T is set for 1 ms and pins 2, 4, 6, and 8 are connected to the output bus.
Find the timing interval.
13-14. In Problem 13-13, the odd-numbered pins, 1, 3, 5, and 7, are connected to the output bus.
Find the timing interval.
13-15. In Example 13-9, C is changed to 0.1 fiF and R to 500 k f l Find (a) the time base period; (b)
the timing cycle for switch positions shown in Fig. 13-18; (c) the maximum timing cycle.
13-16. In Example 13-10, what frequencies are present at pins (a) 5; (b) 6; (c) 7; (d) 8?
13-17. In Fig. 13-21, only switches to pins 1, 2, 3, and 4 are closed. Find the output frequency.
CHAPTER 14
Digital-to-Analog
Converters
U pon com pletion o f this chapter on digital-to-analog converters, you will be able to:
• W rite the general in p u t-o u tp u t equation for a digital-to-analog converter (DAC) and
calculate the output for any given input.
• U nderstand basic DAC specifications.
• D istinguish betw een a DAC and an M DAC.
• Tell w hat features m ust be present to m ake a DAC com patible w ith a m icroprocessor.
• E xplain how a m icroprocessor selects only one DAC out o f all peripheral devices and
sends data to it.
• D ynam ically test a m icroprocessor-com patible DAC, the A D 558.
• E xplain the operation o f a serial DAC and how to program a m icroprocessor to send
data to it.
400
Digital-to-Analog Converters 401
14-0 INTRODUCTION _________________________________________________________________________
R eal-w orld processes produce analog signals that vary continuously. T he rate m ay be very
slow, such as a change in tem perature variations, or very fast, such as in an audio system .
A nalog processes are best described by decim al num bers and letters o f the alphabet.
M icroprocessors and com puters, however, use binary patterns to represent num bers, let
ters, or sym bols.
It is not easy to store, m anipulate, com pare, calculate, or retrieve data w ith accuracy
using analog technology. However, com puters can perform these tasks quickly and on an
alm ost unlim ited m ass o f data w ith precision, using digital techniques. Thus the need for
converters to interface betw een the analog and digital w orlds em erged. A nalog-to-digital
converters (A D Cs) allow the analog world to com m unicate w ith com puters. C om puters
com m unicate with people and physical processes via digital-to-analog converters (DACs).
T his chapter and the next study this interconnection betw een the analog and digital w orlds.
T his chapter concentrates on digital-to-analog converters w hile C hapter 15 covers the ana
log-to-digital interface. The reason for studying digital-to-analog converters first is that
som e analog-to-digital converters use DAC circuitry as you will see in C hapter 15.
14-1 DAC CHARACTERISTICS _______________________________________________________________
A digital-to-analog converter converts an input binary pattern o f logic Is and Os to a dis

crete analog output, either voltage or current. The in p u t-o u tp u t relationship for a DAC is
a set o f points corresponding to the input digital code and its equivalent analog output.
T his relationship is the D A C ’s transfer fu n c tio n . D epending on how the DAC is config
ured, the transfer can be unipolar (only positive output values) or bipolar (positive and
negative values). DACs can be purchased with an analog output voltage or w ith a current
output. C urrent output DACs require the user to add an op am p to the D A C ’s output ter
minal. However, this allow s the user to select the best device and set the circuit gain for
the application. This section describes som e of a D A C ’s specifications.
14-1.1 Resolution
T he circuit sym bol and the in p u t-o u tp u t ch aracteristics o f a 3-bit DAC are show n in
Figure 14-l(a). Each digital input requires an electrical signal representing either a logic
1 or a logic 0. D 0 is the least significant bit, LSB, and for this exam ple, D 2 is the most
significant bit, M SB.
R esolution is the num ber o f distinct analog outputs (voltage or current) that can be
produced by a DAC. For an n-bit DAC,
resolution = 2n (14-1)
w here n is the num ber of digital inputs. T herefore, for the 3-input DAC o f Fig. 14-1(a),
there are 23 = 8 distinct outputs. Figure 14-1 (b) is a plot o f the discrete analog outputs
for the corresponding digital input codes. T his plot is referred to as the D A C ’s transfer
function. Figure 14-1(b) is a plot for unipolar operation (all ouput values are positive).
Figure 14-1(c) is a plot o f a transfer function for a 3-bit DAC w ired for bipolar operation.
T he digital input code for bipolar operation may be either offset binary or tw o ’s com ple
ment. Both codes are show n in Fig. 14-1(c).
The resolution value is used to determ ine the change in analog output voltage,
resulting from a change o f 1 LSB at the digital input. See Figs. 14-1 (b) and (c). In o r
der to determ ine this change, we need to know the D A C ’s full-scale output range and its
resolution. In equation form,
full-scale range
(14-2)
C onsider the 3-bit DAC of Fig. 14-1(a) w ith the input reference set at 1.2 V. Then
from Eq. (14-2), the change o f the output voltage for a change o f 1 LSB is 150 m V /bit
(1.2 V/8).
Note: A digital code equal to the full-scale range (FSR) does not exist. However,
the industry standard positive full scale is the full-scale range less 1 LSB and is given by
(14-3)
w here Vfs is the ideal full-scale output voltage w hen the digital inputs are all Is. Vref is
the output reference value, w hich is usually equal to a m ultiple o f the input reference. For
our applications, Vref equals the input reference voltage. This value may be set by a volt
age reference IC as described in Section 2-6.
Example 14-1
An 8-bit DAC w ired for unipolar operation has a full-scale voltage range from 0 to
5.12 V. W hat is (a) the D A C ’s resolution, (b) the output voltage change per bit, and
(c) the ideal full-scale output voltage w hen all logic Is are applied at the input?
Solution
(a) A pplying Eq. (14-1),
resolution = 2 8 = 256
(b) T he output change per bit is the output full-scale range (the reference value) di
vided by the resolution as given by Eq. (14-2).
5 12 V
= 20 mV/bit
256
404 Chapter 14
(c) Applying Eq. (14-3),
V/s = 5.12 V x | l - = 5.1 V
Note: T he full-scale output is alw ays 1 LSB less than the m axim um full-scale voltage-
range (the reference value).
E x a m p le 14-2
An 8-bit DAC has a resolution of 20 mV /bit. W hat is the analog output voltage for the
follow ing digital input codes (the M SB is the leftm ost bit)?
(a) 00010110
(b) 10000000
S o lu tio n O ne m ethod is to obtain the decim al equivalent value o f the binary pattern and
then m ultiply the decim al value by 20 m V /b it T he binary w eighted code for unipolar o p
eration is
D = bn27 + b626 + b52 5 + b424 + b 323 + b2l 2 + b t 2 1 + b^2°
w here D is the decim al equivalent value.

(a) A pplying the binary w eighted code yields
D = 0 + 0 + 0 + (1)24 + 0 + (1)22 + (1 )2 ' + .0 = 22
T hen
V0 = 22 X 20 m V /bit = 0.44 V
(b) A pplying the binary w eighted code yields
D = (1)27 + 0 + 0 + 0 .+ 0 + 0 4 - 0 + 0 = 128
T hen
= 128 X 20 m V /bit = 2.56 V
Example 14-3
If the DAC o f E xam ple 14-1 is w ired for bipolar operation, w hat is the change in output
voltage per bit?
S o lu tio n For bipolar operation, the full-scale output voltage range is tw ice the unipolar
reference value. Hence,
For bipolar operation, each bit change causes tw ice the output change as unipolar operation.
C om pare Fig. 14-1 (c) w ith Fig. 1 4-i(b).
Typical DAC resolutions are 8 ,1 0 ,1 2 , 14, 16, 18, 20 bits. However, DACs with higher
resolutions are available. A D A C ’s digital input circuitry is designed for TTL, ECL, or
CM OS voltage levels and this specification should be checked to m atch your application.
74-7.2 Offset Error
T he transfer functions o f Fig. 14-1 are ideal. They do not show errors that occur in prac
tical devices. Figure 14-2 show s a plot o f a transfer function due to an offset error o f one
L SB . A lthough this plot is for a positive offset error, the error could have been negative.
F or m ost devices, the offset error is usually m easured by applying an input digital code
o f all logic Os and m easuring the analog output— the deviation from zero output is the
offset error. Note: A n offset error does not always occur ju st at zero. T he reason that the
offset erro r is m easured at zero is because th ere usually are no o th er erro rs at zero.
H owever, in som e DAC this is not so, and the user should check w ith the m anufacturer’s
data sheet to see if other techniques have been used. Figure 14-2(b) show s an offset er
ror range, positive and negative, for a DAC w ired for bipolar operation.
E x a m p le 14-4
A 12-bit unipolar DAC has a m axim um offset error specified as 0.05% o f FSR. The input
reference voltage is set at 10.24 V. (a) W hat is the offset voltage? (b) W hat is the offset
value in term s o f least significant bit(s)?
S o lu tio n (a)
O ffset voltage = 0.05% X 10.24 V = 5 mV
(b) In term s o f least significant bit(s)
AI, 10.24 V x/n_.

^ — = 2.5 m V /bit
Optional
current output
Digitally Analog
controlled 1,-to-Vo • output
converter
switches
MSB LSB
DigiLaJ input
D
(a)
DAC Output
Digital inputs
(b)
FIGURE 14-5 Block diagram and circuit symbol for a basic D A C .
sw itches (one for each bit) connected to the resistance network. T he output o f the resis
tance netw ork is in the form of a current. This current may then be converted to a volt
age. As previously m entioned, both current and voltage outputs are analog representations
of the digital input code.
The actual digital-to-analog conversion takes place w ithin the resistance network.
A ccordingly, we begin our study of DAC circuitry by looking next at the standard resis
tance netw ork, called an R -2 R ladder network.
14-2.2 R -2 R Ladder Network
A 4-bit R -2 R ladder netw ork is draw n in Fig. 14-6. Each digital input controls the posi
tion o f its corresponding current sw itch. A current sw itch steers its ladder current either
into a real ground (position 0) or a virtual ground (position 1). T hus the w iper o f each
sw itch is alw ays at ground potential, so that the rung currents are constant except for the
brief transition tim e of each sw itch.
In Fig. 14-6, rail currents flow horizontally; rung currents flow dow n through the
bit sw itches. The rail current /, enters node 0, w here it sees a resistance R 0. R0 is the
equivalent resistance of a 2R resistor via sw itch D 0 to ground in parallel w ith a 2R ter
m inate resistor. Thus R 0 = 2R || 2R = R. As rail current /, leaves node 1, it sees R in se
ries w ith R q = R or 2R. If we w ork our way back from the term ination end to the volt
age source, the value o f resistance “ looking” into a node is R. As show n in Fig. 14-6,
412 Chapter 14
14-3 VOLTAGE OUTPUT DACs
A s show n in Fig. 14-7, the output ladder current can be converted into a voltage by adding
an op am p and a feedback resistor. O utput voltage VQ is given by
Vo ~ Jout Rf ( 1 4 - 10a)
S ubstituting for / out from Eq. (14-8) gives
V0 = - (c u rr e n t resolution X D) X Rf ( 1 4 - 1Ob)
R ew rite Eq. (1 4 -10b) as
V0 = - (c u rr e n t resolution X Rf ) X D ( 14 -10c)
T he coefficient o f D is the voltage resolution and is given as
voltage resolution = loRf ( 1 4 - 1 Od)
and V0 can be w ritten very sim ply as
V0 = - v o lta g e resolution X D ( 1 4 - 1 Oe)
In term s o f the actual hardw are, V0 is expressed as
Vo = -
R
x 2
xD (14-11)
E x a m p le 14-7
For the voltage output DAC o f Fig. 14-7, find (a) its v o ltag e reso lu tio n o f 1 LSB and
(b) VQ w hen the digital input is 1111.
S o lu tio n (a) From Exam ple 14-6, the value o f / 0 - 62.5 \xA- From Eq. (14-1 Od),
voltage resolution = Io R /= 62.5 f i A X 10 k f l = 0.625 V
A I-b it input change causes a 0.625-V output voltage change.

(b) C alculate the D A C ’s perform ance equation from Eq. (14-11).
10 V
vn = - X x 10 k f i 1 X D = - 0 .6 2 5 V X D
lO k f l 2“
For a digital input o f 1111, D = 15. T herefore,
Va = - 0 .6 2 5 V X 15 = - 9 .3 7 5 V
R= l O k f t 10 kQ R= 10 kQ
>•" o
FIGURE 14-7 /oul of the R-2R ladder is converted into a voltage by the op amp and
feedback resistor Rf.
414 Chapter 14
74-4 MULTIPLYING D A C ____________________________________________________________________________
E quation (14-11) can be rew ritten to show how an M DAC or m ultiplying DAC operates
V0 = (constant) X Vref X D ( 14- 12)
w here
constant = -
2n R
E quation (14-12) shows that V0 is the product o f tw o input signals, Vref and D y and both
signals can be variables. O ne exam ple for M DAC use is the volum e control o f an audio
signal controlled by a m icroprocessor
S uppose that Vref is an audio signal that varies from 0 to 10 V in Fig. 14-7. From
E xam ple 14-7, if D = 0001, V0 w ould vary from 0 to 0.625 V. If the digital input is 1000,
D = 8 and the volum e o f V0 w ould increase from 0 to 8 X 0.625 V = 5 V. M axim um vol
um e o f 15 X 0.625 V = 9.375 V w ill occur w hen the digital input w ord is 1111, D = 15.
T hus the M DAC perform s as a digitally operated volum e control.
14-5 8-BIT DIGITAL-TO-ANALOG CONVERTER: THE DAC-08 __________________________
T he D A C -08 is a low -cost, fast M D A C , housed in a 16-pin DIP. Its o p era tin g p rin c i
ples are e x a m in e d by re fe re n c e to th e task p erfo rm ed by ea ch o f its te rm in a ls in
Fig. 14-8.
14-5.1 Pow er Supply Terminals
Pins 13 and 3 are the positive and negative supply term inals, respectively, and can have
any value from ± 4 .5 to ± 1 8 V. They should be bypassed with 0.1-/xF and 0.01-/i,F ca
pacitors, as show n in Fig. 14-8a.
14-5.2 Reference (Multiplying) Terminal
F lexibility o f the DAC-08 is enhanced by having two rather than one reference input. Pins
14 and 15 allow positive or negative reference voltages, respectively. A positive reference
voltage input is shown in Fig. 14-8a.
T he user can adjust the D A C -08’s input ladder current /ref quite easily from 4 fiA
to 4 m A w ith a typical value o f 2 mA.
(14-13)
-1 5 V +15 V
V
TTL or CMOS
compatible
(a) DAC-08 wired for positive output voltages.
Digital inputs Analog output

On ^6 Os £>4 *>3 ^2 D| A) Ôlil Vo
LSB 0 0 0 0 0 0 0 1 7.812 |iA 39 mV

Half scale 1 0 0 0 0 0 0 0 1.000 mA 5.0 V
Full scale 1 I 1 1 1 1 1 1 1.992 mA 9.96 V
(b) Summary of Examples 14-7 and 14-8.

s ir
FIGURE 14-8 An 8-bit DAC-08 is wired for unipolar voltage in (a). /out has values
given in (b) for three digital input words. The op amp converts /oul to voltage VQ.
416 Chapter 14
14-5.3 Digital input Terminals
Pins 5 through 12 identify the digital input term inals. Pin 5 is the m ost significant bit
(M SB ), D 7>Pin 12 is the LSB, D 0. T he term inals are T T L or C M O S com patible. Logic
input “0” is 0.8 V or less. L ogic 441” is 2.0 V or greater, regardless o f the pow er supply
voltages. U sually, pin 1, VLC, is grounded. H ow ever, it can be used to adjust the logic in
p u t threshold voltage VTH according to VTH = VLC + 1.4 V. T hese digital inputs control
eight internal current sw itches. ,
14-5.4 Analog Output Currents
Two current output term inals are provided in Fig. 14-8 to increase the D A C -08’s versa
tility. Pin 4 conducts output current / out and pin 2 conducts its com plem ent, /out. If an in
ternal sw itch is positioned to “ 1,” its ladder rung current flows in the Iout bus. If p o si
tioned to “0,” ladder rung current flow s in the / out bus.
T he current value of 1 LSB (resolution) is found from
V 1
current resolution = (value o f 1 LSB ) = — — X — ( 1 4-1 4a)
/ out is calculated from
/out = (value o f 1 LSB ) X D ( 1 4 - 14b)
w here D is the decim al value o f the digital input word. The full-scale output current in
the pin 4 output bus occurs w hen the digital input is 111 11111, so that D = 255. L e t’s
define this current as Ifs, w here
lfS = (value o f 1 LSB ) X 255 ( 1 4 - 1 5a)
T he sum o f all ladder rung currents in the DAC-08 equals Ifs. Since this sum alw ays di
vides betw een the / out and /out, the value o f / ou{ is given by
(14-15b)
Example 14-8
C alculate (a) the ladder input current / ref o f the DAC-08 in Fig. 14-8; (b) the current value
of 1 LSB.

(b) From Eq. (1 4 -14a),
current value o f 1 LSB = X = 7.812 jjlA
E x a m p le 14-9
For the DAC-08 circuit in Fig. 14-8, find the values o f / out and / out w hen the digital input
w ords are (a) 00000001; (b) 10000000; (c) 1 1 1 1 1 1 11.
S o lu tio n Exam ple 14-8 showed that current output resolution is 7.812 /xA/bit. From Eq.
(1 4 -15a), evaluate lfs.
Ifs = (resolution)255 = 7.812 /xA X 255 = 1.992 mA
T he value of D is 1 for (a), 128 for (b), and 255 for (c). / out can now be found from Eq.
(14-14b):
(a) A>ut - 7.812 /xA X 1 = 7.812 /xA for 00000001 input
(b) /out = 7.812 /jlA X 128 = 1.000 m A for 10000000 input
(c) /out = 7.812 A X 255 = 1.992 mA for 11111111
jjl input
F rom Eq. (14-15b),
(a) 4 u, = 1.992 mA - 7.812 /xA = 1.984 mA
(b) /out - 1-992 m A - 1.0 m A = 0.992 mA
(c) / out = 1.992 m A - 1.992 m A = 0
T he results of E xam ples 14-8 and 14-9 are tabulated in Fig. 14-8(b).
74-5.5 Unipolar Output Voltage
In Fig. 14-8(a), the D A C -08’s current output / oul is converted to an output voltage V0 by
an external op am p and resistor /?/. The voltage output has a resolution o f
voltage resolution o f 1 LSB = X Rf X (14-16a)

^ref 2
and VQ is given by
V0 = voltage resolution X D = IoutR f (1 4 -16b)
Example 14-10
F or the D A C-08 circu it o f Fig. 14-8(a), find V0 for d ig ital inputs o f (a) 00 0 0 0 0 0 1 ; (b)
11111111 . -
418 Chapter 14
S o lu tio n From Eq. (1 4 -16a),
voltage resolution = (10 V) ^ ^ X — = 39.0 m V /bit

5 k il 256
(a) From Eq. (1 4 -16b) w ith the value o f D = 1,
V0 = 39.0 mV X 1 = 39.0 mV for 00000001 input
(b) T he value of D = 255. From Eq. (1 4 -16b),
V0 = 39.0 mV X 255 = 9.961 V for 11111111 input
1 4 -5 .6 B ip o la r A n a l o g O u t p u t V o lta g e
T he versatility o f the DAC-08 is show n by w iring it to give a bipolar analog output volt
age in response to a digital input w ord [Fig. 14-9(a)]. T he op am p and tw o resistors co n
vert the difference betw een 7out and 7out into a voltage VQ:
Vo = (/out - l ^ ) R f (14-17)
7out drives VQ positive and 7out drives V0 negative. If the digital input w ord increases
by 1 bit, 7out increases by 1 L SB . H ow ever, 7out m ust th erefo re d ecrea se by 1 LSB .
T herefore, the differential output current changes by 2 L SB s; thus w e w ould expect the
bipolar output voltage span to be tw ice that o f a unipolar output (see E xam ple 14-3).
Vref has been increased slightly in Fig. 14-9(a) so that 7ref increases to 2.048 mA
[Eq. (14-13)]. T his increases the current value o f 1 LSB to an even 8 /xA [Eq. (1 4 -14a)].
We show how the output voltage responds to digital inputs by an exam ple.
E x a m p le 14-11
F or the circuit o f Fig. 14-9(a), calculate VDfor digital inputs o f (a) 00000000; (b) 01111111;
(c) 10000000; (d) 11111111.
S olution The current value o f 1 LSB equals 8 /xA. From Eq. (1 4 -15a), ifs = (8 jjlA )255 =
2.040 mA. ___
(a) From Eq. (1 4 -14b), 7out = (8 jj,A) X 0 = 0. Then from Eq. (14-15b), 7out =
2.040 m A - 0 = 2.04 mA. Find V0 from Eq. (14-17):
V0 = (0 - 2.04 m A )(5 k fl) = - 1 0 .2 0 V
T he values o f 7out, 7out, and VQ are calculated for (b), (c), and (d) and are sum m arized in
Fig. 14-9(b).
-15 V +1 5 V
8 digital inputs
(a) DAC-08 wired for bipolar output voltage.
Digital inputs Analog outputs

Di 04 *>3 d2 Ox /out(mA) /oul (mA) v0<y)
Negative full scale 0 0 0 0 0 0 0 0 0 2.040 - 10.20

Negative zero 0 1 1 1 I 1 1 1 1.016 1.024 -0.040
Positive zero 1 0 0 0 0 0 0 0 1.024 1.016 0.040
Positive full scale 1 1 1 1 1 1 1 1 2.040 0 10.20
(b) Tabulated solutions for Example 14-9.
FIGURE 14-9 The op amp converts complementary output currents of the DAC-08 into
bipolar output voltages. The op amp is wired as a differential current-to-voltage converter.
420 Chapter 14
N ote that full-scale negative output voltage o f —10.20 V occurs for an all-zero d ig
ital input. A ll ones give a positive full-scale output o f plus 10.20 V. N ote also that V0 never
goes to precisely zero volts. W hen 7out is less than 7oul by 8 /jlA (01111111), V0 equals
—40 mV. Since this is the closest that V0 approaches to 0 V from negative full-scale,
V0 = —40 m V is called negative zero.
M any DACs m ust operate under the control o f a m icroprocessor or com puter. We
therefore next present a m icroprocessor-com patible DAC.
14 6 M ICROPROCESSOR COMPATIBILITY ________________________________________________
14-6.1 Interfacing Principles
T he program m er views the location o f a D A C ’s register(s) or any other peripheral c h ip ’s

registers as an address in the total m em ory space. DACs have “w rite o n ly ” registers. This
m eans that a DAC has a register that the m icroprocessor can send binary digits to via the
data bus. An A D C ’s registers are “read only” registers. T hese devices have registers w hose
contents can be “read” by the m icroprocessor via the data bus. Both D ACs and A D C s
have logic that perm its selection via the address bus.
74-6.2 M em ory Buffer Registers
“Read only” or “w rite only” registers have tw o operating states: transparent and latching.
An idle register always rem em bers (latches) the last digital w ord w ritten into it, and the
register can be disconnected from the data bus. M ore specifically, the interface betw een
data bus and register can be in the high-Z state, or essentially an open circuit.
W hen a register is transparent, it is connected to the data bus. F o r exam ple, an 8-
bit register in a DAC w ould allow its 8 data bits, D 7 through D0, to “read ” the logic Is
and/or 0s present on each corresponding w ire o f the data bus placed there by the m icro
processor (see Fig. 14-10).
How does the m icroprocessor locate one DAC, out o f all other peripherals or m em
ory addresses, that it is selected? T his question is answ ered next.
14-6.3 The Selection Process
Every DAC register has an address ju st like any m em ory location o f the m icroprocessor.
To w rite to one particular DAC, the m icroprocessor places the address o f that DAC on
the address bus (see Fig. 14-10). O ne output o f a local decoder goes low to enable a chip
select, C S, term inal on the selected DAC. T he D A C’s digital input buffer registers do not
yet becom e transparent. T he DAC is only partially selected.
To fully select the DAC, the m icroprocessor places a low on a line to the chip e n
a ble>CE, term inal. T his line is controlled by the_m icroprocessor’s read/w rite line, w hich
m ay also be referred to as MRW, M EM W , or R/W . W hen both the CS and C E term inals
are low, only one DAC can com m unicate w ith the m icroprocessor. Its internal reg ister
is pin-program m able for output ranges o f 0 to 2.56 V or 0 to 10.0 V. O peration o f the

AD558 is studied by analyzing those tasks perform ed by its term inals.
14-7.2 Power Supply
Pin 11 is the pow er supply term inal Vc c in Fig. 14-11(a). It requires a m inim um + 4 .5 V
and has a m axim um rating of + 1 6 .5 V. Pins 12 and 13 are the digital and analog grounds,
resp ectiv ely . T his allow s the u ser to m ain tain se p a ra te an alo g and d ig ital g ro u n d s
throughout a system , jo in in g them at only one point. U sually, pins 12 and 13 are w ired
to g e th er and a 0 .1 - ^ F bypass ca p ac ito r m u st be co n n ected b etw een Vc c and pin 12
or 13.
14-7.3 Digital Inputs
Pins 1 through 8 are the digital inputs D 0 to D 7, w ith D 0 the LSB and D 7 the M SB. They
are com patible with standard T T L or low -voltage CM O S. Logic 1 is 2.0 V m inim um for
a “ 1” bit. Logic 0 is 0.8 V m axim um for a “0 ” bit.
T he digital input pins connect the data bus to the A D 5 5 8 ’s internal m em o ry la tch
ing register, w hen the A D 558 is selected. T his co n d itio n is called tra n sp a ren t. W hen
u nselected, the latching reg ister is essen tially d isco n n ected from the data bus and re
m e m b ers th e la st w ord w ritte n in to the la tc h in g reg ister. T h is c o n d itio n is ca lle d
“ latching.”
14-7.4 Logic Circuitry
T he m icroprocessor executes a write com m and over the address bus via an address d e
coder and w rite line to the A D 558’s logic control pins 9 and 10. They are called chip se
lect (C S ) and chip enable (CE), respectively.
If a “ 1” is present on either CS or CE, the digital inputs are in the “latching’" mode.
They are disconnected from the data bus. T he input latches rem em ber the last w ord w rit
ten by the m icroprocessor over the data bus. If both CS and C E are “0,” the A D 5 5 8 ’s in
puts are “transparent” and connect the input m em ory latch register to the data bus. The
m icroprocessor can now w rite data into the DAC. D igital-to-analog conversion takes place
im m ediately and is com pleted in about 200 ns.
14-7.5 Analog Output
As show n in Fig. 14-11, the analog o u tp u t vo ltag e ( VQ) ap p ears b etw een pins 16 and
13 (analog ground), Pin 14 is called “ se lec t” ( V0 gain). It is w ired to pins 15 and 16
to set the o utput voltage range at 0 to 2.56 V, as in Fig. 1 4 -1 1(b). T he actual analog
output range is 0 to 2.55 V, or 10 m V /b it for a d ig ital input o f 0 0 0 0 0 0 0 0 to 11111111.
A 0-to -1 0 -V o utput range con n ectio n is show n in Fig. 14-1 la . T he actual ran g e is 0 to
9.961 V or 38.9 m V /b it (p o w e r su p p ly v o lta g e m u st e x c e e d m ax im u m V0 by 2 V
424
1 1000-Hz clock 8 bit-binary counter

+5 V +5 V
Ra - A A
47 kft
A/W^ ^+5V
1000-Hz
clock 3 4 9 10 12 13 16 3 4 9 10 12 13 16
CD4029 CD4029
#1 #2
LSB MSB
14 11 6 14 11 6
0.01 pj.F Dy D2 Z>, d 0 «— LSB MSB —►D7 Ds Ds D4
<? 3<> 29 1? 89 7<? 69 0-
£>3 d2 D\ D0 D7 D6 Ds D4
11 ■+5 V
*CT Clock AD558
OiF) frequency (Hz)
cs CE 12 13 14 15 16
0.001 10,000
10
0.01 1,000
0.10 100
1.00 10 V
8-bit D/A converter
FIGURE 14-12 The 555 clock drives an 8-bit binary counter made from two CD4049
ICs. The outputs count in binary from 00000000 to 11111111 and then repeat. The digi
tal count is converted by the DAC into an analog voltage that resembles a staircase.
m inim um ). S ense term inal 15 allow s rem o te lo ad -v o ltag e sensing to elim in ate the e f
fects o f IR drops in long leads to the Joad. It can also be used for cu rren t b o o st as in
Fig. 1 4 -1 1(c).
14-7.6 Dynamic Test Circuit
A single A D 558 can be tested dynam ically without a m icroprocessor by the stand-alone,
low -parts-count test circuit o f Fig. 14-12. Pins 9 and 10 o f the A D 558 are grounded. This
connects the A D 558’s input register (transparent) to an 8-bit synchronous counter that
sim ulates a data bus.
The test circuit consists o f three ICs. O ne 555 tim er is wired as a 1-kHz clock. It
steps an 8-bit synchronous binary counter m ade from two CD 4029s. T he co u n ter’s o u t
puts are w ired to the digital inputs of the DAC. An oscilloscope is connected (dc coupled)
to display V0. It should be externally triggered from the negative edge o f the M SB (pin 8
o f the A D 558 or pin 2 o f the right C D 4029 in Fig. 14-12). T he analog voltage w aveshape
appearing at V0 will resem ble a staircase.
Each clock pulse steps the counter up by one count and increases V0 by 10 mV.
Thus the risers will equal 10 mV and the staircase will have 256 treads from 0 to 2.55 V.
T he tread on each step will occupy about 1 ms. Thus one staircase w aveshape is gener
ated every 256 ms. Any glitch, nonlinearity, or other abnorm ality will be quite apparent.
T he capacitor CT can be changed to give faster or slow er clock frequencies, as indicated
in Fig. 14-12. Any visible glitches can be m inim ized but not elim inated from V0. However,
a sam ple-and-hold or follo w -a n d - ho Id am plifier can be connected to VQ. It w aits until the
glitch settles dow n, sam ples V0, and holds this correct value. The principle o f sam ple-and-
hold is presented in C hapter 15.
14-8 SERIAL DACs ------------------------------------------------------------------------------
14-8.0 Introduction
T his section describes a 12-bit serial D /A converter. T he data is shifted into the DAC one
bit at a tim e usually from a m icroprocessor or a m icrocontroller. T he authors selected the
DA C-8043 from A nalog D evices to show typical operation o f serial DACs. This DAC is
housed in an 8-pin mini-DIP. Figure 14-13 shows the pin designation as w ell as the func
tional block diagram . T he device consists o f a 12-bit seriaJ-in to parallel-out shift regis
ter, a 12-bit DAC register, and a 12-bit digital-to-analog converter. It also contains the nec
essary control logic. Serial data is clocked into the input shift register, one bit on each
rising edge of a clock signal. A fter 12 bits have been shifted in, the data is transferred to
the DAC register by an active low state on the LD pin. D ata in the DAC register is co n
verted to an output current by the D /A converter. Since this particular device produces an
output current, an external op am p m ust be connected to the D A C s output as show n in
Fig. 14-14.
428 Chapter 14
Memory
address t--------D ata---------*
1 -
D000 X XXX 1 1 1 1
-----------r -M SB
D 00 1 i j i i i i i i
-------------------E -LSB FIGURE 14-16 Data to be sent is stored in memory.
D 000 so that the M SB will be sent first. T he follow ing assem bly language code is w rit
ten as a subroutine that is called to send the data one bit at a tim e to the DAC on data bus
line D 7.
Subroutine Code
LDAB #04 Initialize
LD AA $D 000 accum ulators A and B
LOOP L SL A
Shift d o n ’t care data, Xs,
DECB
out o f the way
BNE LOOP
LDAB #04 R einitialize count value,

BSR SH IFT branch to S H IFT subroutine
LD AB #08
R einitialize to send
LDAA $D001
next 8 bits
BSR SH IFT
STAA $0001 Transfer data from shift reg. to DAC reg.

RTS Return from subroutine.
SH IFT STAA $0000

LSLA Subroutine to shift
D ECB data on data bus line
BNE S H IFT D7.
RTS
The 74138 IC in Fig. 14-15 could be used to interface three m ore serial DACs to the m i
croprocessor.
PROBLEMS
14-1. What is the resolution for (a) 10-bit DAC and (b) 14-bit DAC?
14-2. If the input reference voltage is 10 V for each of the DACs of Problem 14-1, what is the
equivalent least significant voltage value?
14-3. What is the maximum output voltage for a 10-bit DAC if the reference voltage is set at
10.24 V?
14-4. A 12-bit DAC has a least significant bit resolution of 2.5 mV/bit, what is the output volt
age if the input binary patterns are:
(a) 100011001000 "
(b) 001100100101
The most significant bit is the leftmost bit,
14-5. The output voltage of an 8-bit DAC is 1.9 V. What is the input digital code if the refer
ence voltage is 5.12 V?
14-6. A 12-bit DAC has an offset error of - 1 /2 LSB and a gain error of - 1 /2 LSB. If the input
reference voltage is 10.24 V, what is the output voltage when the input digital code is all
Is?
14-7. Refer to the R-2R ladder network of Fig. 14-7. Let Vref = 10 V, Rf = 5 kH, R = 5 kO,
and 2R = 10 kCl. Find (a) characteristic ladder resistance, (b) 70; (c) voltage resolution;
(d) output-input equation; (e) V0.
14-8. What is the voltage at pins 2 and 3 of the op amp in Fig. 14-9(a) when the digital inputs
are 1000000? Also calculate the voltage across the feedback resistor to get V0.
14-9. A basic DAC consists of a reference voltage, ladder network, current switches, and op
amp. Name two additional features required to make the DACmicroprocessorcompatible.
14-10. Can the AD558 and DAC-08 be used as multiplying DACs?
14-11. These questions refer to the AD558. (a) Name the terminals that allow this DAC to be se
lected. (b) Describe the digital input register’s latching mode and (c) transparent mode of
operation.
14-12. (a) What is the output-input equation for an AD558 DAC?
(b) Find VQ for an input code of 10000000.
14-13. If the 74138 decoder chip shown in Fig. 14-15 is used to interface three more serial
DACs, at what address would their registers be located?
CHAPTER 15
Analog-to-Digital
Converters
U pon com pletion of this chapter on analog-to-digital converters, you w ill be able to:
• W rite the general o u tp u t-in p u t equations o f an analog-to-digital converter (A D C ) and

calculate its output for any given input. .
• D efine and understand basic A D C specifications and term s.
• N am e the m ost com m on types o f A D C s and tell how each one operates.
• E xplain how a m icroprocessor selects only one A D C out o f all peripherals and reads its
data.
• C alculate the m axim um sine w ave frequency that can be digitized to an accuracy o f
LSB by an A D C or sam ple-and-hold am plifier.
• O perate a m icroprocessor-com patible A D C, the AD 670.
430
Analog-to-Digital Converters 431
15-0 INTRODUCTION ____________________________________________________________________
The previous chapter dealt with converting digital patterns of logic Is and Os to an ana
log signal— digital-to-analog converters (DACs). T hese devices are part o f the output in
terface circuitry of a m icroprocessor-based system. They transform stored data or the re
sults o f digital processing back to real-w orld signals for control applications, for sound
system s, or further analog processing, and so forth. In this chapter, we shall study part of
a com puter’s input interface circuitry— analog-to-digital converters. ADCs are required to
convert real-w orld signals produced by sensors and their signal-conditioning circuits to a
digital pattern used by a com puter. D igital data is easily stored, processed, and transm it
ted; hence, m ost m odern control system s use som e form o f digital processing. R eal-w orld
param eters such as tem perature, pressure, humidity, and so on are first converted by a sen
sor to an electrical quantity and then signal-conditioned analog circuitry before being ap
plied to an A/D converter. T hese analog signals may vary slowly with tim e (for exam ple,
tem perature m easurem ents) or quickly with tim e (for exam ple, audio recording). The lat
ter system s require sam ple-and-hold circuitry before the signal can be applied to an AID
converter.
15-1 ADC CHARACTERISTICS ______________________________________________________________
15-1.1 Resolution
The digital output of an ideal 3-bit ADC is plotted against a norm alized analog input in
Fig. 15-1. Sim ilar to a DAC, the resolution of an ADC is defined as
resolution = T (15-1)
w here n is the num ber o f digital outputs. Since the input is an analog voltage and assum ed
to be continuous, resolution refers to num ber of discrete outputs. The ratio o f the device’s
full-scale input voltage range, FSR, to the resolution gives the m inim um change o f input
voltage to cause a change of one digital count at the output. In equation form
FSR
AVf- for 1 LSB = (15-2)
w here FSR is the full-scale input voltage range specified on the m anufacturer’s data sheet
and n is the num ber of digital outputs. The ratio of Eq. (15-2) is sim ply referred to as
1 LSB as shown in Fig. 15-1. Note: For an A /D converter 1 LSB is a voltage value as we
will see in Exam ple 15-1.
Since the digital count begins at 0, then the m axim um full-scale input voltage to
cause the output to be all logic Is is 1 LSB less than the full-scale range value.
Vifs = FSR - 1 LSB (15-3)
w here V,fS is the m axim um input voltage to cause all logic Is at the A D C ’s output. In gen
eral, the o u tp u t-in p u t equation of an ADC for any input voltage is given by
3-16. A 5-V peak-to-peak sine wave, Eh is applied to ( + ) In of Fig. P3-15. Plot V0 vs. Et if the
3-17. Design a three-channel inverting amplifier. Gains are to be - 1 for channel 1, - 3 for chan-
3-18. Design a two op amp circuit to subtract I V from 3 V. Show the output voltage present at
3-19. Design a circuit to amplify the difference between E x and E2 by 5. The inputs E x and E2
3-20. Redesign the system of Fig. 3-20 to measure a temperature range from 0° to 100°C.
3-21. Obtain the data sheet of the LM 135/335 temperature sensor from National Semiconductor’s
CHAPTER 4
Comparators and Controls
U pon com pletion of this chapter on com parators and controls, you will be able to:
• D raw the circuit for a zero-crossing detector and plot its o u tp u t-in p u t characteristic.
• Identify the upper and lower threshold voltages on an o u tp u t-in p u t characteristic.
• C alculate hysteresis voltage if you know the threshold voltages.
• E xplain how hysteresis gives a m easure o f noise im m unity to com parator circuits.
• Explain why hysteresis m ust be present in all o n -o ff control circuitry, using the fam il
iar wall therm ostat as an exam ple.
• M ake a battery-charger control circuit.
- B uild and calibrate an independently adjustable setpoint co n tro ller
• D escribe the operation of an LM 311 precision com parator.
• Know how to control the strobe term inal o f a com parator with a m icrocontroller signal
Com parators and Controls 85
• Use a com parator circuit in a biom edical application.

• C onnect two LM 311 com parators to m ake a w indow detector.
• G ive the definition of propagation delay and know how to m easure it.
• Sim ulate com parator circuit operation using PSpice.
4-0 INTRODUCTION __________________________________________________________________________
A co m p arato r com pares a signal voltage on one input w ith a referen ce v oltage on the
o ther input. V oltage-level-detector circu its are also co m p arato rs and w ere in troduced
in C h ap ter 2 to show how easy it is to use op am ps to solve som e types o f sig n al co m
parison ap p licatio n s w ith o u t the need to know m uch ab o u t the op am p itself. T he g en
era l-p u rp o se op am p w as used as a su b stitu te fo r IC s d esig n ed only fo r co m p arato r
applicatio n s.
U nfortunately, the general-purpose op am p ’s output voltage does not change very
rapidly. A lso, its output changes betw een lim its fixed by the saturation voltages + Vsa( and
—Vsat that are typically about ± 1 3 V. T herefore, the output cannot drive devices that re
quire voltage levels betw een 0 and -I-5, such as T T L digital logic ICs or input port lines
of a m icrocontroller. T hese disadvantages are elim inated by ICs that have been specifi
cally designed to act as com parators. O ne such device is the 311 com parator. It will be
introduced at the end of this ch a p te r
N either the g eneral-purpose op am p nor the co m p arato r can operate properly if
noise is present at either input. To solve this problem , w e w ill learn how the addition o f
p o sitive fe e d b a c k overcom es the noise problem . N ote that positive feed b ack does not
elim inate the noise but m akes the op am p less responsive to it. T hese circuits will show
how to m ake better voltage-level detecto rs and also build a foundation to understand
square-w ave generators (m ultivibrators) and single-pulse generators (one-shots), w hich
are covered in C hapter 6.
4-1 E FFEC T O F N OISE ON COMPARATOR CIRCUITS ___________________________________
Input signal £, is applied to the ( —) input of a 741 op am p in Fig. 4-1 (the 741 is a g en
eral-purpose op am p). If no noise is present, the circuit operates as an inverting zero-
crossing detector because Vrcf = 0.
N oise voltage is shown, for sim plicity, as a square wave in series w ith E r To show
the effect o f noise voltage, the op am p ’s input signal voltage is draw n both w ith and w ith
out noise in Fig. 4-2. T he w aveshape of Va vs. tim e shows clearly how the addition of
noise causes false output signals. V(, should indicate only the crossings o f E n not the
crossings o f £, plus noise voltage.
If Ei approaches Vref very slowly or actually hovers close to Vref, Va can either fo l
low all the noise voltage oscillations or burst into high-frequency oscillation. T hese false
crossings can be elim inated by positive feedback.
Chapter 4
+v
}• FIGURE 4-1 Inverting zero-crossing

detector
iput
/
The addition of noise voltage at the
input causes false zero crossings.
FIGURE 4-2 Effect of noise on a zero-crossing detector.

4-2 POSITIVE FEEDBACK ____________________________________________________________________
4-2.7 Introduction
Positive fe ed b a c k is accom plished by taking a fraction o f the output voltage V0 and ap

plying it to the ( + ) input. In Fig. 4-3(a), output voltage VQ divides betw een R { and R 2. A
fraction o f Va is fed back to the ( + ) input and creates a reference voltage that depends
on VQ. The idea o f a reference voltage was introduced in C hapter 2. We w ill now study
positive feedback and how it can be used to elim inate false output changes due to noise.
+v
+v
FIG U RE 4-3 /?, and R2 feed back a

reference voltage from the output to
the (+ ) input terminal.
88 Chapter 4
4-2.2 Upper-Threshold Voltage
In Fig. 4-3(a), output voltage V0 divides betw een R x and 7?2- A fraction o f V0 is fed back
to the ( + ) input. W hen Vt) = + Vsat, the fed-back voltage is called the upper-threshold
voltage, VUT. VUT is expressed from the voltage divider as
V//T — (4-1)
For E t values below VUT, the voltage at the ( + ) input is above the voltage at the ( -) in-
put. T herefore, VQ is locked at + V sat.
If E, is m ade slightly m ore positive than VUT, the polarity o f E dy as show n, reverses
and V0 begins to drop in value. Now the fraction o f VQ fed back to the positive input is
sm aller, so Ed becom es larger. VQ then drops even faster and is driven quickly to —Vsal.
T he circuit is then stable at the condition show n in Fig. 4-3(b).
4-2.3 Lower-Threshold Voltage
W hen VQ is at —Vsal, the voltage fed back to the ( + ) input is called low er-threshold volt-
age, VLT> and is given by
V,t = (4-2)
R\ + Rr
N ote that VLT is negative with respect to ground. T herefore, Va will stay at —Vsal as long
as Ei is above, or positive with respect to, VLT. V0 will sw itch back to 4- Vsar if E t goes
m ore negative than, or below, VLT.
We conclude that positive feedback induces a snap action to sw itch V0 faster from
one lim it to the other. O nce V0 begins to change, it causes a regenerative action that m akes
VQ change even faster. If the threshold voltages are larger than the peak noise voltages,
positive feedback w ill elim inate false output transitions. T his principle is investigated in
the follow ing exam ples.
E x a m p le 4-1
If + Vsat = 14 V in Fig. 4-3(a), find VUT.
S o lu tio n By Eq. (4-1),
V / jt ~ (14 V) ~ 14 mV
UT 100,100 n
E x a m p le 4-2
If - Vsa, = - 1 3 V in Fig. 4-3(b), find VLT.

4-3.2 Zero-Crossing Detector with Hysteresis as a

M em ory Elem ent
If Ej has a value that lies betw een V l t and VUT, it is im possible to predict the value o f V0
unless you already know the value o f V0. For exam ple, suppose that you substitute ground
for E, (Ej = 0 V) in Fig. 4-3 and turn on the power. T he op am p w ill go to eith er + Vsat
or - Vsal, depending on the inevitable presence o f noise. If the op am p goes to + Vsat, Et
m ust then go above Vur in order to change the output. If V0 had gone to - Vsal, then E,
w ould have to go below VLT to change V0.
T hus the com parator w ith hysteresis exhibits the property o f m em ory. T h at is, if £ ,
lies betw een VUT and VLT (w ithin the hysteresis voltage), the op am p rem em bers w hether
the last sw itching value o f was above VUT or below VLT.
4-4 VOLTAGE-LEVEL DETECTO RS WITH H Y STER ESIS
4-4.1 Introduction
In the zero-crossing detectors o f Sections 4-2 and 4-3, the hysteresis voltage VH is cen
tered on the zero reference voltage Vref. It is also desirable to have a collection o f circuits
that exhibit hysteresis about a center voltage that is either positive or negative. For ex
am ple, an application may require a positive output, V0> w hen an input £ , goes above an
upper-threshold voltage o f VUT = 12 V. A lso, we m ay w ish V0 to go negative w hen E t
goes below a low er threshold voltage of, for exam ple, VLT = 8 V. T hese requirem ents are
sum m arized on the plot of VD vs. E t in Fig. 4-6. VH is evaluated from Eq. (4-3) as
FIGURE 4-6 Positive-voltage-level

detector. Hysteresis voltage VH is sym
metrical about the center voltage VCLr.
This voltage-level detector is a nonin
verting type because Va goes positive
when Ej goes above VUT.
92 Chapter 4
V h = VUT ~ VLT = 12 V - 8 V = 4 V
T he hysteresis voltage VH should be centered on the average o f VUT and VLT. This aver
age is called center voltage, Vctrt w here
V n T + V ,T 12V + 8V
VVClT— = 10 V
W hen w e try to build this type o f voltage-level detector, it is desirable to have four
features: (1) an adjustable resistor to set the value o f VH\ (2) a separate adjustable resis
tor to set the value of Vctr; (3) the setting o f VH and Vcn. should not interact; and (4) the
center voltage Vclr should equal or be sim ply related to an external reference voltage Vref.
For the low est possible parts count, the op am p ’s regulated supply voltage and a resistor
netw ork can be used for selecting V r e f -
S ections 4-4.2 and 4-4.3 deal w ith circuits that do not have all these features but
are low in parts count and consequently cost. Section 4-5 presents a circuit that has all
four features but at the cost o f a higher parts count.
4-4.2 Noninverting Voltage-Level Detector with Hysteresis
T he positive feedback resistor from output to ( + ) input indicates the presence o f hys
teresis in the circuit o f Fig. 4-7. Ez is applied via R to the ( + ) input, so the circuit is non
inverting. (N ote that £, m ust be a low -im pedance source or the output o f either a voltage
follow er or op am p am plifier.) The reference voltage Vref is applied to the op am p ’s ( - )
input.
T he upper- and low er-threshold voltages can be found from the follow ing equations:
+
1 -Vv s a t
V„ t = V„ (4-4a)
n
r (4-4b)
Vlt = Vref|
ref I + -1 -
n,
H ysteresis voltage VH is expressed by
_ ( + V / Sa t) - ( - V /sat)
L T (4-5)
In zero-crossing detectors, VH is centered on the zero-volts reference. For the cir

cuit o f Fig. 4-7, VH is not centered on Vref but is sym m etrical about the average value of
Vu r and VLT. T his average value is called center voltage Vctr and is found from
Vctr =
Vur±V±r = v /, +1 (4-6)
C om pare the locations o f Vctr and Vret in Fig. 4-6. A lso com pare Eqs. (4-5) and
(4-6) to see that n appears in both equations. This m eans that any adjustm ent in resistor
nR affects both Vctr and VH.
94 Chapter 4
D esign the circuit of Fig. 4-7 to have VUT = 12 V and VLT - 8 V. A ssum e that ± Vsat
± 1 5 V.
1■F rom Eqs. (4-5) and (4-6), calculate VH and VclT:

12 V + 8 V
VH = 12 V - 8 V = 4 V, Vctr = -------- --------- --- 10 V
2. Find n from Eq. (4-5):
+Vsat - ( - V sJ = +15 y - ( - 1 5 V ) =
T/ A
VH 4
3. Find Vref from Eq. (4-6):
VW = Vclr = — 10 V = 8.82 V
1 + 1In 1 + 1/7.5
4. S elect R = 10 k H and nR = 7.5 X 10 k f t = 75 kH . T he relationships betw een £ , and
are show n in Figs. 4-7(b) and (c).
4-4.3 Inverting Voltage-Level Detector with Hysteresis
If Ej and Vref are interchanged in Fig. 4-7(a), the result is the inverting voltage-level d e
tector with hysteresis (see Fig. 4-8). The expressions for VUT and VLT are
V„r = - ^ - ( V ref) + (4-7a)

n + 1 17+1
-(Vref) + (4-7b)
n + r ,CI/ n + 1
Vctr and are then found to be
_ Verr + Vlt _ ( _n_ (4-8)

Vc« = 're f
2 \n + 1
( + V s a » ) - ( - V s ,» )
(4-9)
n + 1
N ote that Vctr and Vh both depend on n and therefore are not independently ad
justable.
+v
11.53 V -
(a) The ratio of nR to R or n and ^ref

determ ines ty/r* ^LT' VH, and Vclr
+V„
(b) V0 and E x vs. time.
FIG U RE 4-8 Inverting voltage-level detector with hysteresis. Center voltage

Vclr and VH cannot be adjusted independently since both depend on n.
Design Example 4-5
C om plete a design for Fig. 4-8 that has VUT = 12 V and VLT = 8 V. To m ake this exam ple
com parable w ith E xam ple 4-4, assum e that ± V sal = ± 1 5 V. T herefore, Vc{r = 10 V and
VH = 4 V.
98 Chapter 4
T he general equation for Vclr seem s com plex. However, if the m agnitudes o f +Vsal and
- V sat are nearly equal, then Vctr is expressed sim ply by
Vc, r = - — ( 4 - 12b)
m
So Vc(r depends only on m and VH depends only on n .
T he follow ing exam ple show s how easy it is to design a battery-charger control cir
cuit using the principles studied in this section.
4-5.2 Battery-Charger Control Circuit
Follow ing is an exam ple o f the design procedure for a battery-charger control circuit.
A ssum e that you w ant to m onitor a 12-V battery. W hen the b attery ’s voltage drops below
10.5 V, you w ant to connect it to a charger. W hen the battery voltage reaches 13.5 V, you
w ant the charger to be disconnected. T herefore, VLT = 10.5 V and VUT = 13.5 V. Let us use
the —V supply voltage for VTef and assum e that it equals - 15.0 V. Further, let us assum e
that ± Vsal = ± 13.0 V. Find (a) VH and l7ctr; (b) resistor m R\ (c) resistor nR.
1. From Eqs. (4-11) and (4 -12a), find VH and Vctr.
Vh = V ur - Vlt = 13.5 V - 10.5 V = 3.0 V
I 3 ' 5 V + l 0 '5 V - 12.0 V
N ote that the center voltage is the battery ’s nom inal voltage.
2. A rb itra rily ch o o se resisto r R to be a read ily av ailab le value o f 10 k f l. F ro m Eq.
( 4 -12b), choose Vref as —15 V to m ake the sign o f m positive:
Vm l \ 12 V
T herefore, m R = 1.25 X 10 k f l = 12.5 k fl.

3. F rom Eq. (4-11), find n.
+ V iM - ( - V sai) _ 13 V - ( - 1 3 V)
vu - 5 “ 8 '66
T herefore, nR = 86.6 kH .
T he final circuit is shown in Fig. 4-10. W hen E f drops below 10.5 V, VQ goes neg
ative, releasing the relay to its norm ally closed position. T he relay ’s norm ally closed (NC)
contacts connect the charger to battery E r D iode D \ protects the transistor against exces
sive reverse bias w hen V0 = — W hen the battery charges to 13.5 V, VD sw itches to
+ y sat> w hich turns on the transistor and operates the relay, w hose NC contacts open to
disconnect the charger. D iode D2 protects both op am p and transistor against transients
developed by the rela y ’s collapsing m agnetic field.
O ne final note. Suppose that the application requires an inverting voltage-level d e
tector w ith hysteresis. T hat is, V0 m ust go low w hen E , goes above V UT and V0 m ust go
high w hen £, drops below VLT. For this application, do not change the circuit or design
procedure for the noninverting voltage-level detectors, sim ply add an inverting am plifier,
or inverting com parator, to the output VQ.
+12 or +15
V V V
-15
FIG U RE 4-10 Battery-charge control for solution to Example 4-6. Adjust mR
for Vclr = 12 V in the test circuit of Fig. 4-9 and adjust nR for VH = 3 V cen
tered on Vc(r.
4-6 ON -OFF CONTROL PRINCIPLES _______________________________________________________
4-6.1 Comparators in Process Control
D esign Exam ple 4-6 illustrates one o f the m ost im portant applications o f positive feed
back circuits w ith hysteresis. They make excellent low -cost o n -o ff controls. T he circuit
o f Fig. 4-10 turns a charger on when battery voltage is below 10.5 V. It also turns the
charger off when battery voltage exceeds 13.5 V. N ote that the 10.5-to-13.5-V area is the
m em ory or hysteresis range. If the battery voltage is 12.0 V, it can be either in the process
o f charging or discharging, depending on the last com m and.
100 Chapter 4
4-6.2 The Room Thermostat as a Comparator
The tem perature control in a room is a fam iliar exam ple o f o n -o ff control. L et’s draw an
analogy to our com parator circuits. You adjust the tem perature pointer to 65°F. This co r
responds to Vctr. The m anufacturer builds in the hysteresis. Turn heat on if the tem pera
ture is below 63°F. Turn heat o ff if the tem perature is above 67°F. If the tem perature is in
the m em ory range (63° to 67°F), rem em ber the last com m and. T he m em ory range co rre
sponds to VH.
4-6.3 Selection/Design Guideline
C ontrols that are to be operated by the general public all share com m on characteristics with
the com parators of Sections 4-4 and 4-5. The custom er can only adjust VclT. VH is present
or, in som e applications, the VH control is brought out for the customer. These types of con
trol circuits are fail safe. If tem perature is set to 50°F, the room sim ply gets colder. They do
not contain the possibility of catastrophic failure. T hat is, they w o n ’t mix up VUT and VLT.
T he control circuit o f the next section gives high-precision adjustm ents for the u p
per and low er setpoints for process control applications. It contains the possibility o f ru n
aw ay operation. C ontrols for VUT and VLT m ust be available only to a know ledgeable p er
son and never to the general public.
4-7 AN INDEPENDENTLY AD JUSTABLE SETPOIN T CONTROLLER __________________
4-7.1 Principle of Operation
T he circuit to be presented will allow both upper setpoint voltage VUT and low er setpoint
voltage VLT to be adjusted independently and with precision. The principle o f operation
is straightforw ard. Set up a voltage with one fixed resistor and two adjustable resistors as
in Fig. 4-11.
W hen a sin g le-p o le do u b le-th ro w (S P D T ) sw itch is throw n to o n e p o sitio n , it
grounds the upper setpoint adjust pot. A djust R u r so that the upper setpoint voltage VUT
appears at the setpoint voltage output, Vset [see Fig. 4 - 1 1(a)]. Then throw the sw itch to its
rem aining position as in Fig. 4 - 1 1(b). A djust R LT so that VLT appears on the Vset line.
B efore we design and analyze the hardw are to m ake an electronically controlled
S PD T sw itch, let us define the required o u tp u t-in p u t characteristics.
4-7.2 Output-Input Characteristics of an Independently

Adjustable Setpoint Controller
Two outputs are required from our basic controller. T he first is shown in Fig. 4 - 12(a). T he
setpoint voltage output Vset is needed for two reasons. First, it will be applied to one in
put o f the in -o u t com parator (num ber I in Fig. 4-13). Second, it m ust be available for
system test or calibration to trained test persons (not the public).
102 Chapter 4
15 V
10V -
5V -
**E:
VLT VUT
(a) Controller setpoint output vs. Er (b) Controller input-output characteristic.
FIGURE 4-12 An on-off controller with independent setpoint voltages, VUT

and VLT, has two distinct characteristics. The setpoint voltage depends on the in
put voltage as in (a). The input-output characteristic exhibits hysteresis as in (b).
4-7.4 Circuit for Independently Adjustable Setpoint Voltage
We only have to add tw o m ore parts to the basic voltage divider o f Fig. 4-11. O ne is a
1 0 -k fi resistor and the other is three-fourths o f an LM 339 open -co llecto r com parator.
R ecall from C h ap ter 2 that the L M 3 3 9 usually w orks sin g le su p p ly w ith a g ro u n d
at pin 12 on its negative rail. If d ifferential input v oltage E d is n eg ativ e for any one o f
its fo u r com p arato rs, the co rresp o n d in g o u tp u t sw itch is closed. T h is g ro u n d s the c o m
p a ra to r’s o u tp u t term inal (and, incidentally , a setp o in t pot). If E d is p ositive [( + ) In
above ( —) In] the ou tp u t sw itch is open (and, in cidentally, d isc o n n ec ts an ad ju stm en t
pot).
T he control circuit is finally presented in Fig. 4 - 13(a). The alignm ent procedure is
presented as a flow chart show ing the cause-and-effect sequence in Fig. 4 - 13(b). Study the
alignm ent procedure carefully. It explains how the circuit works.
You will probably draw the follow ing conclusions from your study.
1. C om parators 2 and 3 form a single-pole, double-throw sw itch to ground the bottom

term inal and activate either R UT or R LT (see Fig. 4-11).
2. C om parator 1 is the o u tp u t-in p u t control. Vsel is either at VUT or at VLT and is ap
plied to l ’s ( —) input. Since £ , is applied to the ( + ) input, the circuit is inherently
noninverting [see Fig. 4 - 12(b)].
3. T his circuit m akes an excellent laboratory experim ent since it has a parts count o f
only five.
In practice, VQ[ will usually drive a relay or optocoupler with triac output. T herefore,
V0] should be buffered or use the rem aining L M 339 co m p arato r to (a) invert the o u t
p u t-in p u t characteristic, or (b) avoid loading R PU below either setpoint voltages.
104 Chapter 4
4-7.5 Precautions
One last tim e, suppose that VUT is adjusted to a value below VLT. U pon pow er up, one o f
tw o events w ill occur: (1) the system will not start up, or (2) the system will turn on and
rem ain on until destruction occurs.
4-8 1C PRECISION COMPARATOR, 111/311 _______________________________________________
4-8.1 Introduction
T he 111 (military) or 311 (comm ercial) com parator is an IC that has been designed and op
timized for superior perform ance in voltage-level-detector applications. A com parator should
be fast. That is, its output should respond quickly to changes at its inputs. The 311 com
parator is much faster than the 741 op amp but not as fast as many of today’s high-speed
com parators. The subject of speed is discussed in Section 4-11, “Propagation D elay ”
T he 311 is an excellent choice for a low -cost com parator because o f its versatility.
Its output is designed not to bounce betw een ± V sat but can be changed quite easily. As a
m atter of fact, if you are interfacing to a system w ith a different supply voltage, you sim
ply connect the output to the new supply voltage via a pull-up resistor. We begin by ex
am ining the operation o f the output term inal.
4-8.2 Output Terminal Operation
A sim plified model of the 311 in Fig. 4 - 14(a) shows that its output behaves like a sw itch
connected betw een output pin 7 and pin 1. Pin 7 can be w ired to any voltage with
m agnitudes up to 40 V m ore positive than the — V supply term inal (pin 4). W hen ( + ) in
put pin 2 is m ore positive than ( —) input pin 3, the 31 l ’s equivalent output sw itch is open.
V0 is then determ ined by V*~+ and is + 5 V.
W hen the ( + ) input is less positive than (below ) the ( —) input, the 31 T s equivalent
output sw itch closes and extends the ground at pin I to output pin 7. H ere is one im por
tant difference betw een the 311 and the 339. T he 339 has no equivalent to pin 1. T here
is no separate sw itch return term inal on the 339 as there is on the 311.
/?/-and Rf add about 50 mV of hysteresis to m inim ize noise effects so that pin 2 is es
sentially at 0 V. W aveshapes for V0 and £, are shown in Fig. 4-14(b). VQis 0 V (switch closed)
for positive half-cycles of E t. V(, is + 5 V (switch open) for negative half-cycles of Er This is
a typical interface circuit; that is, voltages may vary between levels of + 1 5 V and —15 V, but
V0 is restrained between + 5 V and 0 V, which are typical digital signal levels, so the 311 can
be used for converting analog voltage levels to digital voltage levels for interfacing applications.
4-8.3 Strobe Terminal Operation
T he strobe term inal of the 311 is pin 6 (see also A ppendix 3). T his strobe feature allow s
the com parator output either to respond to input signals or to be independent o f input sig
nals. Fig. 4-15 uses the 311 com parator as a zero-crossing detector. A 10-kIl resistor is
108 Chapter 4
tal or a doctor’s office the electrocardiogram w aveform is obtained from a person through
sensors and passes through an isolation/instrum entation am plifier and then to the analog-
to-digital signal conditioning circuit. T hus the patient is alw ays isolated from any ac
pow er source. In the laboratory, function/arbitrary w aveform generators such as H ew lett-
P ack ard ’s H P33120A output an EK G w aveform so that you may design and test b io
m edical equipm ent w ithout having to m onitor a patient.
4-10 WINDOW DETECTOR __________________________________________________________________
4-10.1 Introduction
The circuit of Fig. 4 - 17 is designed to m onitor an input voltage and indicate when this volt
age goes either above or below prescribed limits. For exam ple, IC logic power supplies for
T TL m ust be regulated to 5.0 V. If the supply voltage should exceed 5.5 V, the logic may
be dam aged, and if the supply voltage should drop below 4.5 V, the logic may exhibit m ar
ginal operation. Therefore, the lim its for T T L pow er supplies are 4.5 V and 5.5 V. The
pow er supply should be looking through a window w hose lim its are 4.5 V and 5.5 V, hence
the nam e window detector. This circuit is som etim es called a double-ended limit detector.
In Fig. 4-17 input voltage is connected to the ( —) input of com parator A and the
( + ) input of com parator B. U pper lim it VUT is applied to the ( + ) input o f A, w hile lower
l i mit VLT is ap p lied to the ( —) in p u t o f B. W hen E t lies betw een VLT and VUTf the
light/alarm is off, but w hen £, drops below V/T or goes above VUT, the light/alarm goes
on to signify that E, is not betw een the prescribed limits.
C ircuit operation is as follows. A ssum e that E = 5 V. Since E , is greater than VLT and
less than VUT> the o utput voltage of both com parators is at V++ because both output
sw itches are open. The lam p/alarm is off. N ext, assum e that £, = 6.0 V or E, > VUT. The
input at pin 3 o f A is m ore positive than at pin 2, so the A output is at the potential of pin
1 or ground. This ground lights the lamp, and V0 = 0 V. Now assum e that E t drops to
4.0 V or Ej < VLT. The ( + ) input o f B is less than its ( - ) input, so the B output goes to
0 V (the voltage at its pin 1). O nce again, this ground causes the lam p/alarm to light. Note
that this application shows that output pins of 311 can be connected together and the out
put is at V * + only when the output o f each com parator is at V* +.
4-11 PROPAGATION DELAY _________________________________________________________________
4-11.1 Definition
S uppose that a signal £, is applied to the input o f a com parator as in Fig. 4-18. There will
be a m easurable tim e interval for the signal to propagate through all the transistors within
the com parator. A fter this tim e interval the output begins to change. T his tim e interval is
called response tim e, transit tim ey or propagation delay.
will not sw itch. However, if is brought up quickly to 100 mV plus a sm all am ount o f
overdrive, the overdrive signal will propagate through the com parator. A fter a p ropaga
tion delay the output com es out of saturation and rises to a specified voltage. T his volt
age is typically 1.5 V.
As show n in Fig. 4 -1 8(b), a 5-m V o v erd riv e resu lts in a p ro p ag a tio n d elay o f
4.5 ns for an A D 9696 co m p arato r Typical response tim es for the 311, 522, and 710 co m
parators and the 301 general-purpose op am p are
Response time for Response time for

Com parator 5-mV overdrive (ns) 20-mV overdrive (ns)
311* 170 100

522 17 15
710 40 20
301 > 10,000 > 1 0,000
° V * + = 5 V with a 5 0 0 -fi pull-up resistor.
4-12 USING PSPICE TO MODEL AND SIM ULATE

COMPARATOR CIRCUITS ______________________________________________________________
In this section, we wiU use PSpice and sim ulate the perform ance o f two com parator cir
cuits— the zero-crossing detector with hysteresis and the w indow detector. In the labora
tory, you can test the perform ance o f each and com pare it to the sim ulation so that you can
draw conclusions about both. Your version o f PSpice m ay not have the 301 op am p or the
311 com parator listed, so we will use the 741 op am p and the LM 111 ICs in their place.
T he input signal to these circuits will be a triangle wave, and you will learn how to set the
attributes o f a pulse wave to create a triangle w ave as well as how to plot V0 versus Er
4-12.1 Simulation of the Zero-Crossing Detector

with Hysteresis
R efer to Fig. 4-3 and create the PSpice m odel o f the circuit. We will set the input volt
age o f the triangular w ave to a peak value o f 1 V and a frequency o f 500 Hz. We w ish to
obtain a plot o f VQ versus E h To begin, place the follow ing parts in the w ork area.
Draw => j£et New Part
Part Number Library

= > VPULSE 1 source. sib
=> R 2 analog.slb
= > G LOBAL 4 porLslb
= > AGND 5 port.slb
112 Chapter 4
A rrange the parts as show n in Fig. 4-3. C hange the attributes o f the parts as given in Fig.
4-3. Now we are going to set the attributes o f a pulse wave to generate a trian g u lar wave.
Set up the triangular-w ave attributes by double-clicking the pulse sym bol. In the pop-up
box, we need to set values for DC (dc offset value), VI (m inim um input voltage), V2
(m axim um input voltage), TD (tim e delay), TR (rise tim e), TF (fall tim e), PW (pulse
w idth), and PER (period) as given:
DC = > 0 = > Save Attr

V I = > - I V = > Save Attr = > Change Display = > Both name and value
V 2 = > IV = > Save Attr = > Change Display = > Both name and value
TR = > 1ms = > Save Attr
TF = > 1ms = > Save Attr
PW = > Ins = > Save Attr
PER = > 2ms = > Save Attr
C lose the attribute box. D ouble-click on the lead from the triangle w ave to the op am p
and label it Ei. D ouble-click on the lead from the output term inal o f the op am p and la
bel it Vo. See Figure 4-19.
+v
v* ~
15 V - 15 V
5 VO Vo
v, UA.
+V
Vo
FIG U RE 4-19 PSpice model of Fig. 4-3.
Initialize the T ransient menu.

S elect
Analysis = > Setup = > Transient

C lick Transient = > Print Step: = > 1 fxs

In the Probe w indow, select
Plot = > X Axis Settings = > User Defined = > —IV to IV = > Axis Variable = > V[Ei]
PJot = > Y Axis Settings = > User Defined = > —15V to 15V
N ow select
O btain a printout as shown in Fig. 4-20.
15v r
iov -
5 V -
0V -
-5 V -
-1 0 V -
- 1 5 V __________________i____________ l l = l
- J .0 V - 0 .5 V 0V 0.5 V 1.0 V
FIGURE 4-20 Plot of V0 vs E, from PSpice simulation.
4-72.2 Window Detector
In this section, we w ish to m odel and sim ulate the operation o f the w indow detector cir
cuit show n in Fig. 4 - 17(a). T he input signal is a triangular w ave with a peak value o f
10 V and a frequency of 500 Hz. O btain a plot o f V0 and E t versus tim e as show n in Fig.
4 - 17(b). R efer to Fig. 4-17(a) and create the PSpice m odel o f the circuit. To begin, place
the follow ing parts in the w ork area.
Part Number Library
= > LM111 2 eval.slb

= > V P U L SE 1 source.slb
- > R 1 analog.slb
- > G LOBAL 7 port.slb
- > AGND 7 port .sib
114 Chapter 4
+v -
^3
15 V
VO
15 V +
Vo
V++
1-- +
10 V
Vo
4.5 V
FIGURE 4-21 PSpice model of the window detector circuit of Fig. 4 -17(a).
A rran g e the parts as show n in Fig. 4-21. C h an g e the attrib u tes o f the p arts as given in
Fig. 4 -1 7 (a) w ith a load resisto r set at 10 k f l. N ow w e are going to set the attrib u tes
o f a pulse w ave to gen erate a positive tria n g u lar w ave. T h e trian g u lar-w av e attrib u tes
are set by d o u b le-click in g the pulse sym bol. In the p o p -u p box, the attrib u tes DC (dc
o ffset value), V I (m inim um input v oltag e), V2 (m ax im u m in p u t v o ltag e), TD (tim e
d e la y ), TR (rise tim e), TF (fall tim e), PW (p u lse w id th ), and PER (p erio d ) m u st
be set.
DC = > 0V = > Save Attr

V I = > 0V = > Save Attr —> Change Display = > Both name and value
V2 = > 10V = > Save Attr —> Change Display = > Both name and value
T R = > 1ms = > Save Attr
TF = > 1ms = > Save Attr
PW = > Ins = > Save Attr
PER = > 2ms = > Save Attr
C lose the attribute box. D ouble-click on the lead from the input source to the circuit and
label it Ei. D ouble-click on the lead from the output term inal o f the w indow detector and
label it Vo. See Fig. 4-21.
Initialize the T ransient menu.
CHAPTER 5
Selected Applications
of Op Amps
LEARNING O BJEC TIVES ________________________________________________
U pon com pleting this chapter on selected applications o f op am ps, you w ill be able to:
• A ppreciate how one or tw o op am ps plus a few com ponents can give an inexpensive so
lution to a num ber o f practical applications.
• M ake a universal high-resistance voltm eter.
• T est diodes, LED s, IRED s, and low -voltage zeners w ith a constant current.
• Build a circuit that interfaces a 4-to-20 mA transm itter to a m icrocom puter.
• M easure the pow er received by a solar cell, photodiode, or photoresistor.
• E xplain how to m easure solar energy.
• Shift the phase angle o f a fixed-frequency sine wave by a precise am ount and in d ep en
dent o f its am plitude.
118
Selected Applications of Op A m ps 119
• Show how to design a signal co n d itio n in g circu it for a C elsiu s or F ah ren h e it th e r

m om eter w ith an A D 590 tem perature transducer and a current-to-voltage converter.
• U se integrating and differentiating am plifier circuits.
• U se P Spice to sim ulate circuit perform ance.
5-0 INTRODUCTION __________________________________________________________________________
W hy is the op am p such a popular device? This chapter attem pts to answ er that question
by presenting a w ide selection o f applications. They w ere selected to show that the op am p
can perform as a very nearly ideal device. M oreover, the diversity o f operations that the
op am p can perform is alm ost w ithout limit. In fact, applications that are norm ally very
difficult, such as m easuring short-circuit current, are rendered easy by the op amp. Together
with a few resistors and a pow er supply, the op am p can, for exam ple, m easure the output
from photodetectors, give audio tone control, equalize tones o f different am plitudes, con
trol high currents, and allow m atching o f sem iconductor device characteristics. We begin
w ith selecting an op am p circuit to make a high-resistance dc and ac voltm eter.
5-1 HIGH-RESISTANCE DC VOLTMETER __________________________________________________
5-1.1 Basic Voltage-Measuring Circuit
Figure 5-1 show s a sim ple but very effective high-input-resistance dc voltm eter. T he volt
age to be m easured, E h is applied to the ( + ) input term inal. Since the differential input
voltage is 0 V, E t is developed across The m eter current 1m is set by Ej and Rj ju st as
in the noninverting am p lifier
(5-1)
1-mA m eter movement
FIG U RE 5-1 High-input-resistance

dc voltmeter.
120 Chapter 5
If R( is 1 k a then 1 mA o f m eter current w ill flow for £, = I V dc. T herefore, the mil-
liam m eter can be calibrated directly in volts. As show n, this circuit can m easure any dc
voltage from - 1 V to + I. V.
Example 5-1
Find Im in Fig. 5-1.
Solution From Eq. (5-1), 1m = 0.5 V /l k f l = 0.5 mA. T he needle is deflected halfw ay
betw een 0 and + 1 mA.
O ne advantage o f Fig. 5-1 is that E t sees the very high input im pedance o f the ( + )
input. Since the ( + ) input draw s negligible current, it will not load down or change the
voltage being m easured. A nother advantage o f placing the m eter in the feedback loop is
that if the m eter resistance should vary, it will have no effect on m eter current. Even if
we added a resistor in series w ith the meter, w ithin the feedback loop, it w ould not affect
/„„ because l m is set only by E, and /?,. T he output voltage will change if m eter resistance
changes, but in this circuit we are not concerned w ith VQ. T his circuit is som etim es called
a voltage-to-current converter.
5-1.2 Voltmeter Scale Changing
Since the input voltage in Fig. 5 - 1 m ust be less than the pow er supply voltages ( ± 15 V),
a convenient m axim um lim it to im pose on £, is ± 1 0 V. T he sim plest way to convert Fig.
5-1 from a ± 1 -V voltm eter to a ± 1 0 -V voltm eter is to change /?, to 10 kH . In other
w ords, pick Rj so that the full-scale input voltage E FS equals Rt tim es the full-scale m e
ter current IFS or
R, = 7^
*F S
(5-2)
Example 5-2
A m icroam m eter w ith 50 juA = 1FS is to be used in Fig. 5-1. C alculate R t for E FS = 5 V.
Solution By Eq. (5-2), R t = 5 V/50 fiA = 100 kCl.

Selected A pplications of Op A m ps 121
To m easure higher input voltages, use a voltage-divider circuit. The output o f the
divider is applied to the ( + ) input.
5-2 UNIVERSAL HIGH-RESISTANCE VOLTMETER ____________________________________
The voltage-to-current converter o f Fig. 5-2 can be used as a universal voltm eter. That is,
it can be used to m easure positive or negative dc voltage or the rms, peak, or peak-to-
peak (p-p) value o f a sine wave. To change from one type o f voltm eter to another, it is
necessary to change only a single resistor. T he voltage to be m easured, Eh is applied to
the op am p ’s ( + ) input. Therefore, the m eter circuit has a high input resistance.
W hen Ei is positive, current flows through the m eter m ovem ent and diodes D 3 and
D4. W hen £, is negative, current flows in the sam e direction through the m eter and diodes
D | and D2. Thus m eter current direction is the sam e w hether Ei is positive or negative.
A dc m eter m ovem ent m easures the average value o f current. S uppose that a basic
m eter m ovem ent is rated to give fu ll-scale d eflectio n w hen co n d u ctin g a cu rren t o f
50 ijlA. A voltm eter circuit containing the basic m eter m ovem ent is to indicate at full scale
w hen Ej is a sine wave w ith a peak voltage of 5 V. The m eter fa c e should be calibrated
linearly from 0 to + 5 V instead o f 0 to 50 {xh. The circuit and m eter m ovem ent w ould
then be called a pea k reading voltm eter (for sine waves only) w ith a full-scale deflection
for Eip = 5 V. The follow ing section shows how easy it is to design a universal voltm eter.
FIGURE 5-2 Basic high-resistance universal voltmeter circuit. The meaning

of a full-scale meter deflection depends on the function switch position as fol
lows: 5 V dc on position a, 5 V ac rms on position b, 5 V peak ac on position
c, and 5 V ac p-p on position d.
5-3 VOLTAGE-TO-CURRENT CON VERTERS: FLOATING LOADS ______________________
5-3.1 Voltage Control of Load Current
From S ections 5-1 and 5-2 we learned not ju st how to m ake a voltm eter but that current
in the feedback loop depends on the input voltage and T here are applications w here
we need to pass a constant current through a load and hold it constant despite any changes
in load resistance or load voltage. If the load does not have to be grounded, we sim ply
place the load in the feedback loop and control both input and load current by the p rin
ciple developed in Section 5-1.
5-3.2 Zener Diode Tester
S uppose that w e have to test the breakdow n voltage o f a num ber o f zener diodes at a cu r
rent o f precisely 5 mA. If w e connect the zener in the feedback loop as in Fig. 5-3(a), our
voltm eter circuit of Fig. 5-1 becom es a zener diode tester. T hat is, E, and /?, set the load
or zener current at a constant value. E t forces V0 to go negative until the zener breaks
dow n and clam ps the zener voltage at Vz. R t converts to a current, and as long as R x
and E, are constant, the load current will be constant regardless o f the value o f the zener
voltage. Z ener breakdow n voltage can be calculated from V0 and E t as Vz = V0 -
Example 5-4
In the circuit o f Fig. 5-3(a), VD — 10.3 V, = 5 V, and /?, = 1 kH . Find (a) the zener cu r
rent; (b) the zener voltage.
Solution (a) From Eq. (3-1), / = E JRj or / = 5 V /l kCt = 5 mA. (b) From Fig. 5-3(a),
rew rite the equation for V0.
VZ = V 0 - E ' = 10.3 V - 5 V = 5.3 V
5-3.3 Diode Tester
S uppose that we needed to select diodes from a pro d u ctio n b atch and find pairs w ith
m atching voltage drops at a particular value o f diode current. P lace the diode in the
feedback loop as show n in Fig. 5-3(b). E l and R { w ill set the value o f I. T he ( —) input
draw s negligible current, so / passes through the diode. As long as E, and /?,- are c o n
stant, current through any diode I w ill be co n stan t at I = £;//?;. V0 w ill equal the dio d e
voltage for the sam e reasons that V0 was equal to VR in the inverting am p lifier (see
S ection 3-1).
T here is one disadvantage with the circuit o f Fig. 5-3(b): E, m ust be able to furnish
the current. B oth circuits in Fig. 5-3 can only furnish currents up to 10 mA because of
the op a m p ’s output current lim itation. H igher-load currents can be furnished from the
pow er supply term inal and a current boost transistor as show n in Fig. 5-4.
5-4 UGHT-EMITTING-DIODE TESTER ______________________________________________________
The circuit of Fig. 5-4 converts E { to a 20-m A load current based on the sam e principles
discussed in Sections 5-1 to 5-3. Since the 7 4 T s output term inal can only supply about
5 to 10 mA, we cannot use the circuits o f Figs. 5-1 to 5-3 for higher load currents, but if
we add a transistor as in Fig. 5-4, load current is furnished from the negative supply volt
age. The op am p ’s output term inal is required to furnish only base current, w hich is typ
ically 1/100 of the load current. T he factor 1/100 com es from assum ing that the tran sis
to r’s beta equals 100. Since the op am p can furnish an output current o f up to 5 mA into
the transistor’s base, this circuit can supply a m axim um load current o f 5 m A X 100 =
0.5 A.
A light-em itting diode such as the M L E D 50 is specified to have a typical brightness
o f 750 fL (foot lam berts) provided that the forw ard diode current is 20 mA. E-t and R t will
set the diode current IL equal to EJRi - 2 V /100 f l = 20 mA. N ow brightness o f LED s
can be m easured easily one after another for test or m atching purposes, because the cur
rent through each diode will be exactly 20 mA regardless o f the L E D ’s forw ard voltage.
It is w orthw hile to note that a load o f tw o L E D s can be connected in series with
the feedback loop and both w ould conduct 20 mA. T he load could also be connected in
Fig. 5-4 betw een points A A ' (w hich is in series with the tran sisto r’s collector) and still
conduct about 20 mA. This is because the collector and em itter currents o f a transistor
are essentially equal. A load in the feedback loop is called a flo a tin g load. If one side o f
the load is grounded, it is a grounded load. To supply a constant current to a grounded
load, another type o f circuit m ust be selected, as show n in Section 5-5.
128 Chapter 5
+V = +15 V
A
FIGURE 5-6 Constant-high-current source.
ential input voltage is 0 V, the zener voltage is developed across R s. Rs and Vz set the em it
ter current, IE, constant at Vz/R s. T he em itter and collector currents o f a bipolar ju n ctio n
transistor are essentially equal. Since the collector current is load current IL and I L ~ IE>
the load current 1L is set by Vz and Rs.
If the op am p can furnish a base current drive o f over 5 m A and if the beta o f the
transistor is greater than 100, then IL can exceed 5 mA X 100 = 500 mA. The voltage
across the load m ust not exceed the difference betw een the supply and the zener voltage;
otherw ise, the transistor and the op am p will go into saturation. (If oscillations occur, in
stall a 10 0 -fl resistor betw een term inals 6 and B.)
5-5.3 Interfacing a Microcontroller Output to a 4-to-20-mA

Transmitter
A T T L digital circuit, m icroprocessor, m icrocontroller, or m icrocom puter com m unicates

to the outside world in a binary language that has only tw o sym bols, 0 and 1. T heir co r
responding electrical voltages are low ( < 0 .8 V) and high ( > 2 .4 V). M any valves, actua
tors, and other devices com m only used in process control need a serial pulse train o f e i
ther 20- or 4-m A current pulses. T he 20-m A current pulse m ay be used to energize a
selector m agnet, and the 4-m A current pulse releases the m agnet thus opening and clo s
ing a solenoid. A lthough 4-to-20-m A transm itter devices can be purchased as single ICs,
such as the A D 694, you m ay have an application w here it is necessary to quickly test a
system or only a single interface circuit is needed. T he principles o f operation for an op
am p circuit that w ill interface betw een a m icrocontroller and a 4-to-20-m A current loop
are show n in Fig. 5-7 and analyzed in Section 5-5.4.
5-5.4 Digitally Controlled 4-to-20-mA Current Source
In the circuit o f Fig. 5-7(a), resistors R i and R 2 form an unloaded voltage divider. Since
E d o f the op am p is zero volts, the 2-V drop alw ays appears betw een the positive rail and
em itter o f the current boost transistor QB. O peration o f the circuit is sum m arized in Fig.
5-7(b).
If the 4 0 0 - d resistor is not shorted out, the current through em itter resistor R E (and
collector or loop current /) equals 2 V /500 (1 = 4 mA. If the 4 0 0 -H resistor is shorted out
by Q 2> the loop current I equals 2 V /100 H = 20 mA.
The selection of either 4 or 20 m A is determ ined by E-m. E m can be (I) a T T L or
(other logic fam ily) open-collector gate circuit output, (2) an output port from a m icro
controller, or (3) a discrete (Q x) bipolar junction transistor. (For a stand-alone circuit add
a 2.2-kH resistor in series with the base.)
+15V
(a)
£in e. & Ajut

High = 1 Oo On 2 V/100 Q = 20 mA
Low = 0 Off Off 2 V/500 a = 4 mA
(b)
FIGURE 5-7 Digitally controlled 4-to-20-mA current source
130 Chapter 5
W hen E m is high, Q { saturates and 1Ce 1 equals about 1.4 mA. T he co llecto r c u r
rent o f Q { is the base cu rrent o f Q 2> and Q2 saturates. W hen Q2 saturates, it effectively
shorts out the 4 0 0 -f! resistor and fixes Q q s em itter cu rren t and thus the loop cu rren t
to 20 mA.
W hen £ in is low, Q x is cut off, w hich in turn cuts off Q 2. Q2 then appears as an open
circuit to the 4 0 0 -fl resistor, and the loop current, /, is clam ped at 2 V /500 f i = 4 mA.
T he com pliance voltage of this circuit is 12 V. A llow 12 V for VRI plus 1 V to keep Q B
out o f saturation [15 — (2 + 1) = 12 V].
5-6 SHORT-CIRCUIT CURRENT MEASUREMENT AND CURRENT-

TO-VOLTAGE CONVERSION _____________________________________________________
5-6.7 Introduction
Transducers such as m icrophone pickups and solar cells convert som e physical quantity
into electrical signals. For convenience, the transducers may be m odeled by a signal g en
erator as in Fig. 5-8(a). It is often desirable to m easure their m axim um output current un
der short-circuit conditions; that is, we should place a short circuit across the output ter
m inals and m easure current through the short circuit. This technique is particularly suited
to signal sources with very high internal resistance. For exam ple, in Fig. 5-8(a), the short-
circuit current Isc should be 2.5 V/50 k H = 50 fiA. However, if we place a m icroam m e
ter across the output term inals o f the generator, w e no longer have a short circuit but a
5 0 0 0 -fl resistance. The m eter indication is
50 k a + 5 k a = 45 mA
H igh-resistance sources are better m odeled by an equivalent N orton circuit. This

m odel is sim ply the ideal short-circuit current, Isc> in parallel with its own internal resis
tance as in Fig. 5-8(b). This figure shows how Isc splits between its internal resistance
and the m eter resistance. To elim inate this current split, we will use the op amp.
5-6.2 Using the Op Amp to Measure Short-Circuit Current
The op am p circuit o f Fig. 5-8(c) effectively places a short circuit around the current
source. The ( —) input is at virtual ground because the differential input voltage is alm ost
0 V. The current source “sees” ground potential at both o f its term inals, or the equivalent
o f a short circuit. A ll o f Isc flows toward the ( —) input and on through Rf. /^ c o n v e rts ISc
to an output voltage, revealing the basic nature of this circuit to be a current-to-voltcige
converter.
Selected Applications of Op Amps 133
S o lu tio n From Fig. 5-9 V0 = Rf l. (a) V0 = 10 k f t X 10 /jlA = 0.1 V; (b) V0 = 10 k H x

1 m A = 10 V. T hus the circuit of Fig. 5-9 converts the output current from the photocon-
ductive cell into an output voltage (a current-to-voltage converter).
5-7.2 Photodiode
W hen the sw itch is in position 2 in Fig. 5-9, E t is on one side o f the photodiode and vir
tual ground on the other. T he photodiode is reverse biased, as it m ust be for norm al op
eration. In darkness the photodiode con d u cts a sm all leak ag e cu rren t on the ord er o f
nanoam peres, but depending on the rad ian t energy striking the diode, it will co n d u ct
50 fjuA or more. T herefore, current I depends only on the energy striking the photodiode
and not on E h This current is converted to a voltage by Rf .
Example 5-10
W ith the sw itch in position 2 in Fig. 5-9 and Rf = 100 k£l, find VQ as the light changes pho
todiode current from (a) 1 /jlA to (b) 50 /jlA.
Solution From VQ = Rf Iu (a) V0 = 100 kH X 1 \ x A = 0.1 V; (b) V0 = 100 k f l X 50 /jlA

= 5.0 V.
5-8 CURRENT AMPLIFIER ____________________________________________________________
C h a ra c te ristic s o f h ig h -re sista n c e sig n al so u rce s w ere in tro d u c ed in S ectio n 5 -6 .1 .

T here is no point in converting a cu rren t into an equal cu rren t, but a circu it that c o n
verts a sm all cu rren t into a large current can be very useful. T he circu it o f Fig. 5-10 is
a cu rrent m u ltip lier or current am plifier (technically, a cu rren t-to -cu rre n t converter).
T he signal curren t source Isc is effectively sh o rt-circu ited by the input term in als o f the
op am p. A ll o f ISc flow s th ro u g h re sis to r mR, and th e v o lta g e ac ro ss it is
(R esistor m R is know n as a m ultiplying resisto r and m as the m ultiplier.) S ince R and
m R are in parallel, the voltage across R is also m R ISc ■T h erefo re, the cu rren t th rough R
m ust be m ls c ■ B oth currents add to form load current IL. IL is an am p lified version o f
Is c and is found from
1L = ( 1 + m ) / 5C (5-7)
Selected Applications of Op Amps 135
short-circuit current l s c that ranges from 0 to 0.5 A as sunlight varies from com plete d ark
ness to m axim um brightness.
O ne problem facing users o f these devices is to convert the 0 to 0.5-A solar cell o ut
put current from 0 to 10 V so that its perform ance can be m onitored w ith a strip-chart
recorder. A nother problem is to m easure 1/2 A o f current w ith a low -current m eter m ove
m ent (0 to 0.1 m A ). To solve this problem , Is c m ust be divided so that it can be m easured
on site w ith an inexpensive basic m eter m ovem ent. T he final p roblem is that the value o f
Isc is too large to be used w ith the op am p circuits studied thus far in this chapter.
5-9.2 Converting Solar Cell Short-Circuit Current

to a Voltage
The circuit o f Fig. 5-11 solves several problem s. First, the solar cell sees the ( - ) input o f
the op am p as a virtual ground. T herefore, it can deliver its short-circuit current Is c . A
second problem is solved w hen Is c is converted by Rf to a voltage VQ. To obtain a 0- to
10-V output for a 0- to 0.5-A input, Rf should have a value o f
VQ (full scale) , 10 V
Rf =
ls c (m ax) 0.5 A
V0 should be buffered by a voltage follower. T he solar cell current o f 0.5 A is too large
to be handled by the op amp. This problem is solved by adding an npn current boost tran
sistor.
The solar cell current flow s through the em itter and collector o f the boost tran sis
tor to + V C urrent gain o f the transistor should exceed fi = 100 to ensure that the op am p
has to furnish no m ore than 0.5 A /100 = 5 mA, w hen Is c = 0.5 A.
F IG U R E 5-11 T h is c irc u it forces the so la r c e ll to d e liv e r a s h o rt-c irc u it c u r

re n t I s c . I sc is co n ve rte d to a vo lta g e b y Rf . C u rre n t boost is fu rn is h e d b y the
np n tra n s is to r. T h e d io d e p ro te c ts the b a s e -e m itte r ju n c tio n o f the 2 N 3 0 5 5
against a ccid e n ta l excessive reverse bias.
138 Chapter 5
T he output V0 has the sam e frequency and am plitude but lags E, by 90°. T h at is, VQ goes
through 0 V / 9 0 ° after £ , goes through 0 V. M athem atically, V0 can be expressed by
V0 = Ej / —9 0 °. A general expression for the output voltage o f the phase-shifter circuit
in Fig. 5 - 13(b) is given by
V, - Ei (5-9)
w here 9 is the phase angle and will be found from Eq. (5 -10a).
5-10.2 Phase-Shifter Circuit
As show n in Fig. 5 -13(b) one op am p, three resistors, and one capacitor are all that is re
quired to m ake an excellent phase shifter. T he resistors R m ust be equal, and any conve
nient value from 10 to 220 k 17 may be used. Phase angle 6 depends only on R h C„ and
the frequency / of T he relationship is
6 = 2 arctan In fR iC i ( 5 - 10a)
w here 6 is in d e g r e e s ,/in hertz, R, Ln ohm s, and Ct in farads. E quation (5 -10a) is useful
to find the phase angle if / R h and C, are know n. If the desired phase angle is know n,
choose a value for C, and solve for R
tan (6/2)
R; = (5-10b)
2irfCi
Find Ri in Fig. 5-1 3(b) so that VQ w ill lag E t by 90°. The frequency o f £ , is 1 kH z.
D esign P ro c e d u re Since 6 = 90°, tan (90°/2) = tan (45°) = 1; from Eq. (5 -10b),
1
2 tt X 1000 X 0.01 x 10 --6— = 15.9 k fi
W ith Ri = 15.9 kCl, VQ will have the phase angle show n in Fig. 5- 13(a). T his w aveform
is a negative cosine wave.
A n aly sis E x a m p le 5-14
If Ri — 100 k n in Fig. 5 - 13(b), find the phase angle 6.
S o lu tio n F rom Eq. (5 -10a),

6 = 2 arctan (2tt)(1 X 103)(100 X 103)(0.01 X 10“ 6)
= 2 arctan 6.28
= 2 X 8 1 ° = 162° and VD = E, / - 1 6 2 °
140 Chapter 5
source that depends on tem perature. If, however, w e need a voltage reading to indicate
tem perature, such as 10 m V /°C or 10 mV/°F, a current-to-voltage converter circuit is re
quired.
The circuit sym bol for an A D 590 is the sam e as a current source, as show n in Figs.
5-14(a) and (b). A lso, the A D 590 requires a supply voltage exceeding 4 V to bias its in
ternal tran sisto r circuitry. L e t’s use this device to build a C elsiu s or F ah ren h eit th e r
m om eter.
5-11.2 Celsius Thermometer
In the C elsius therm om eter o f Fig. 5 - 14(a), all o f the A D 5 9 0 ’s current is steered into the
virtual ground at pin 2 and flow s through the 1 0 -k fl feedback resistor, producing a volt
age drop equal to V0. Each m icroam pere o f current thus causes VQto go positive by 1 fjuA
X 10 k f l = 10 mV. A change of l°C causes I T to change by 1 /wA and consequently pro
duces a change in VQ o f 10 mV. T he tem perature-to-voltage converter thus has a conver
sion gain o f 10 m V /°C.
At 0°C , IT = 273 \xA. But we w ant V0 to equal zero volts. For this reason, an equal
and opposite current o f 273 jjlA through the 15-V supply and 5 4 .9 -k fl resistor is required.
This results in the net current through R f to be zero and thus V0 is zero volts. For every
increase o f 1 jnA/°C above 0°C, the net current through /fy increases by 1 f i A and V 0 in
creases by 10 mV.
5-11.3 Fahrenheit Thermometer
A circ u it for a F ah ren h eit th e rm o m ete r is show n in Fig. 5 - 14(b). A t 0 °F we w ant V 0

to eq u al 0 V. S ince IT = 255 jjlA at 0°F, it m u st be nulled o u t by an equal but o p p o
site cu rren t through Rf. T his cu rren t is g en erated by the 15-V supply and the 5 8 .8 -k fl
resistor.
An increase of 1°F corresponds to an increase o f 5/9°C or 0.555°C . T hus the A D 590
increases its output current by 0.555 ju,A/°F. T his increase is converted by Rf into a volt
age of 0.555 jjlA/°F X 18.18 k f l = 10 mV/°F. In conclusion, for every tem perature in
crease o f 1°F above 0°F, V0 will increase by 10 mV above 0 V.
B oth op am p circuits o f Fig. 5-14 are classified as signal co n d itio n in g circu its
(SC C s). T hey are designed to condition the input (w hat you g ot— 0 to 100°C or F) to an
output (w hat you want— 0 to 1 V). If your application requires the output o f the SCC to
be an input to an A /D converter of a m icrocontroller with a 0-to-5-V range, then Rf m ust
be changed. (See Problem 5-22.)
5-12 INTEGRATORS AND DIFFERENTIATORS
If the feedback resistor in an inverting am plifier is replaced by a capacitor as show n in

Fig. 5.15(a), the new op am p circuit is know n as an integrator. Integrators are used in the
c f
(a)
A eJ 0
---------------------------------------------- ►/
(b)
A vo 0 )
(C)
FIGURE 5-15 (a) An integrator circuit. The output voltage ramps negative
in (c) for a positive input step function in (b).
design o f signal generators and signal processing circuits. C hapter 6 describes signal g en
erating circuits, but the basics of an integrator and asignal processing application are de
scribed here. In Fig. 5 - 15(a), the current that charges the capacitor is set by e [n and R t and
is given by
*(0 = - ^ (5-11)
R em em ber that Eq. (5-1 1) assum es that the differentia] voltage o f the op am p, E&
is 0 V. The equation for voltage across a capacitor is
Vc = j ; j i d t (5-12)
142 Chapter 5
From C hapter 3, we learned that for an inverting circuit the output voltage is neg
ative o f the input voltage. Therefore, substituting Eq. (5-11) into Eq. (5-12) and know ing
that the output is negative o f the input yields
(5-13)
E quation (5-13) states that the ouput voltage is directly proportional to the negative
o f the integral o f the input voltage and indirectly proportional to the tim e constant R tCj.
If the input wave is a sine wave, the output is a negative cosine wave. T he period o f the
input w ave should be greater than the tim e constant /?,C/.
If e m is constant, then the cu rrent i(t) is co n stan t and C ch arg es at a co n stan t rate.
In Fig. 5 - 15(b), the input voltage is a po sitiv e step function. For this in p u t signal, V0
aim s to w ard - V sat as C c h a rg e s. S ee F ig. 5 -1 5 (c ). If a n e g a tiv e ste p fu n c tio n is
applied, C charges in the o p p o site directio n and the o u tp u t voltage, V0, aim s tow ard
+ y sa(.
T he conclusion is: If the input voltage is a step function, the output voltage is a
ram p function. Thus the ouput voltage is the integral o f the input voltage. In C hapter 6,
w e w ill alternately apply a positive and a negative voltage at the input o f an integrator to
design a circuit that generates a triangular w aveform . We will now use the integrator fol
low ed by an inverting am plifier to design a servoam plifier.
5-12.2 Servoamplifier
Introduction
A servoam plifier is a circuit w hose output is a delayed response to its input. An ap p lica
tion may be ground-follow ing radar signals by a cruise m issile or the positioning o f an
xy table in a m anufacturing process. In both applications, we may need a circuit that d e
lays the output response due to clutter or noise at the input. Such a circu it is a servoam
plifier as show n in Fig. 5-16. We proceed to answ er two questions about this circu it’s
operation.
1. If E] is in equilibrium , w hat is VQ in equilibrium ?

2. How long w ill it take for V0 to change from one equilibrium to an o th er in response
to a change in E r
Servoamplifier Circuit Analysis

We analyze the circuit behavior of Fig. 5-16 at equilibrium as follows:
1. A ssum e that Et = 2 V, the capacitor C is charged, no current flow s through R h and

its voltage drop is zero.
2. T he voltage at pin 2 equals E t (since R x current equals 0) and negative feedback
m akes voltages equal at pins 2 and 3 o f op am p A.
3. T herefore, VF = Er
144 Chapter 5
Solution From Eqs. (5 -14a) and (5 -14b):
1. E; = 2 V, forcing to 2 V.
2. VF forces V0 to 2V F = 4 V.
3. V0 forces VR to - 4 V.
4. V^p stabilizes at 3E, = 6 V.
Example 5-16
If £■/ is abruptly stepped to 4 V, find the new equilibrium voltages.
Solution
1. Ei = 4 V forces VF to 4 V, forcing to 8 V.
2. decreases toward - 8 V.
3. Vcap m ust charge to 12 V.
Delay Action
E xam ples 5-15 and 5-L6 show that Va m ust servo from 4 to 8 V w hen E t is stepped from
2 to 4 V. A delay w ill occur (as Va servos tow ard 8 V) because the cap acito r m ust charge
from 6 to 12 V. Any noise (clutter) as E,- changes from 2 to 4 V will be zeroed out. T he
tim e constant for the capacitor charge is
T = 3 R tC ( 5 - 15a)
A ssum e that we need 5 tim e constants for the capacitor to fully charge. T hus, equilibrium
will be achieved in
equilibrium tim e = 5 T (5-15b)
Example 5-17
How long does it take for V0 to reach equilibrium in the servoam plifier o f Fig. 5-16?
Solution From Eqs. (5-15a) and (5- 15b):
T = 3R tC = 3(1 X 105 H )(l X 10-6 F) = 0.3 s
equilibrium tim e = 5 T = 5 X 0.3 s = 1.5 s
5-12.3 Differentiators
A differentiator is obtained by interchanging the resistor and the capacitor o f an integrator.

See Fig. 5 - 17(a). This circuit performs the mathem atical operation o f differentiation. The out
put voltage is the negative of the derivative o f the input signal as given in Fig. 5 - 17(a),
(c) A pplying Eq. (15-5)
5.2 V
D = — — t t = 132.99 = 133
39.1 mV
Converting this value to binary yields 10000101.
F igure 15-1 show s the graph for an ideal 3-bit A /D converter. Since there are only 8 d is
crete outputs for this A D C, the analog input range from 0 to full scale m ust be quantized
into these 8 digital outputs. H ence, voltages w ithin the sam e range have the sam e digital
code. T he ideal transition from one digital code to the next is taken to be at the m id-range
value as shown. A /D converters like DACs, have offset, gain, and linearity errors but they
also have a quantization error.
15-1.2 Quantization Error
Figure 15-1 shows that the digital output is 100 for all values o f \ FSR ± \ LSB. H ence,
there is an unavoidable uncertainty about the exact value o f Vln w hen the output is 100.
T his uncertainty is specified as quantization error. Its value is ± \ LSB. Increasing the
num ber o f bits results in a finer resolution and therefore there is a sm aller quantization
error.
75-7.3 Offset Error
S im ilar to DACs, analog-to-digital converters also have an offset error specification. It is

usually given as a fraction o f 1 LSB such as ± \ LSB. Figure 15-2 show s how an A/D
Offset error of 1 FIGURE 15-2 Comparison of the ideal A/D con

Analog input version with a conversion having offset error.
434 Chapter 15
converter's o u tp u t-in p u t plot can be view ed w ith an offset error. T his offset error m odi
fies Eq. (15-3) as show n in the next exam ple.
Example 15-2
C onsider that the 8-bit A /D converter o f P roblem 15-1 has an offset error o f ± { LSB .
W hat analog input voltage w ill cause a digital output code o f all Is?
S o lu tio n F rom the solution o f Problem 15-1, 1 LSB is 39.1 mV. T herefore, \ LSB is
19.5 mV. M odifying Eq. (15-3) by the offset error yields
Vifs = FSR - 1 LSB + j LSB

= 10 V - 39.1 m V + 19.5 m V = 9.9804 V
15-1.4 Gain Error
R efer to Fig. 15-1. In the ideal in p u t-o u tp u t relationship the difference betw een the first
transition and the last transition is FSR — 2 LSB. If this expression is not true, there is a
gain error. See Fig. 15-3 to com pare the ideal relationship w ith an A /D converter that has
a gain error. M a n u fa ctu rers specify gain erro r as a p erc en ta g e o f fu ll-sc a le v o ltag e
(% FSR).
000
0 1 1 3 1 5 3 7 FS
8 4 8 2 8 4 8
A nalog input FIGURE 15-3 Gain error.
436 Chapter 15
varying dc voltages. T he faster successive approxim ation A D C 's conversion tim e is a few
m icroseconds and can digitize audio signals. F astest o f all are the m ore costly fla s h co n
verters, w hich can digitize video signals.
15-2.2 Principles of Operation
T he block diagram of a typical dual-slope integrating A /D converter is show n in Fig. 15

5. A n on-board divide-by-4 counter drives the control logic at a rate o f 12 kH z. T his fre
quency is set by the user via external tim ing resistor R T and CT. It m ust be a m ultiple o f
the local line frequency (50 or 60 H z) to render the A D C im m une to line-frequency noise.
T he control logic unit activates a com plex netw ork o f logic circu its and analog
sw itches to convert analog input voltage Vjn into a digital output. T he analog-to-digital
conversion is perform ed in three phases and requires about one-third o f a second. T hese
operating phases are called signal integrate pha se T x, reference integrate p h a se T2, and
auto-zero pha se Tz. T hese w ill be discussed in sequence.
15-2.3 Signal Integrate Phase, T1
The control logic unit of Fig. 15-5(b) connects Vin to an integrator to begin phase T\. T he
integrator or ram p g enerator's output V0 ram ps up or dow n depending on the polarity o f
Vin and at a rate set by Vin, R mtJ and C int. If Vlu is negative, V0 ram ps up, as show n in Fig.
15-5(a). Tim e T x is set by the logic unit for 1000 clock pulses. Since the 12-kH z clock
has a period o f 83.3 ^ts per count, T x lasts 83.33 ms.
If Vin = - 100 mV, V0 w ill ram p from 0 V to 833 mV. The m axim um allow ed full-
scale value o f Vin is ± 2 0 0 mV. W hen Vin = —200 mV, VQwill rise to a m axim um 1666 mV.
Clearly, V0 is directly proportional to Vin. At the end o f 1000 counts, the logic unit d is
connects Vin and connects Vref to the integrator. T his action ends T x and begins 7 2.
15-2.4 Reference Integrate Phase, T2
D uring phase 7 \, the logic unit determ ined the polarity o f Vin and charged a reference ca
pacitor, Cref (not show n), to a reference voltage Vref = 100 mV. A t the beginning o f phase
T2>the logic unit connects C ref to the integrator so that Vref has a polarity opposite to Vin.
C onsequently, Vref w ill ram p the integrator back tow ard zero. Since Vref is constant, the
integrator’s output VD will ram p dow n at a constant rate, as show n in Fig. 15-5a.
W hen VQ reaches zero, a com parator “tells” the logic unit to term inate phase T2 and
begin the next auto-zero phase. T z is thus proportional to V0 and consequently, Vin. The
exact relationship is
( 15-6a)
Since T { = 83.33 ms and Vref = 100 mV,
(15-6b)
Vo
Auto-zero
438 Chapter 15
E x a m p le 15-4
For the A D C o f Fig. 15-5, calculate T2 if (a) Vin = ± 100 mV; (b) Vin = ± 2 0 0 mV.
S o lu tio n (a) From Eq. (15-6b),
T2 = \ (100 m V) = 83.33 ms
(b)
Ti = \ | (200 m V ) = 166.6 ms
15-2.5 The Conversion
T he actual conversion o f analog voltage V[n into a digital count occurs during T2 as fo l
lows. T he control unit connects the clock to an internal binary-coded-decim al counter at
the beginning o f phase T2. T he clock is disconnected from the counter at the end o f T2.
T hus the co u n ter’s content becom es the digital output. This digital output is set by T2 and
the clock frequency:
digital output = f C° UntSJ \T2 : 15-7a)

second
but T2 is set by Vin from Eq. (15-6a) and therefore
=s)<r>>fe)
Since clock frequency is 12 kH z for the 7106/7107 A D C, 7, = 83.33 m s, and Vref
100 mV, the o u tp u t-in p u t equation is
counts \ / 83.33 ms
digital output = (12,000 Vin
second \ 100 mV
or
, - counts \ ..
digital output = 1 0 -----r— 1 Vin (!5-7c)
mV )
T he co u n ter’s output is connected to an appropriate 3^-digit display.

Example 15-5
Vin equals + 100 m V in the A D C o f Fig. 15-5. Find the digital output.
S o lu tio n From Eq. (15-7c),
digital output = ^10 CQU^ ts j (]0 0 mV) = 1000 counts
E xam ple 15-5 shows the need for som e hum an engineering. T he display reads 1000,
but it m eans that Vin equals 100 mV. You m ust w ire in a decim al point to display 100.0
and paste an “m V ” sign beside the display.
15-2.6 Auto-Zero
The block diagram of Fig. 15-5(b) contains a section labeled “A uto-zero.” D uring the
third and final phase of conversion, TZi the logic unit activates several analog sw itches and
connects an auto-zero capacitor CAZ (not shown).
The auto-zero capacitor is connected across the integrating capacitor, Cint, and any
input offset voltages of both integrating and com parator op am ps. CAZ charges to a volt
age approxim ately equal to the average error voltage due to Cim and the offset voltages.
D uring the follow ing phases, T x and T2, the error voltage stored on CAZ is connected to
cancel any error voltage on Cref. T hus the A D C is autom atically zeroed for every co n
version.
15-2.7 Summary
R efer to the tim ing diagram in Fig. 15-5(a). The logic unit allocates 4000 counts for one
conversion. A t 83.33 fxs per count, the conversion takes 333 ms. The control unit always
allocates 1000 counts or 83.3 ms to phase T x.
The num ber of counts required for T2 depends on Vjn. Zero counts are used for V[n =
0 V and a m axim um o f 2000 counts, or 166.7 ms are used w hen Vin is at its m axim um
lim it of ± 2 0 0 mV.
T2 and Tz alw ays share a total of 3000 counts for a total o f 250 ms. For Vin 0 V,
T2 = 0 counts and Tz = 3000 counts. For Vin = ± 2 0 0 mV, T2 = 2000 counts and Tz =
1000 counts.
Som e m anufacturers of A D C s m arket a com plete 3y-digit digital voltm eter kit. T he
kit contains a 40-pin dual-slope integrating A/D converter, all necessary parts, printed cir
cuit board, and instructions. T he instructions make it easy to construct and easy to use,
and form an excellent tutorial on integrating ADCs.
440 Chapter 15
15-3 S U C C E S S IV E APPROXIMATION ADC
T h e b lo ck d iag ram o f a successive ap p ro x im atio n reg ister (A D C ) is show n in Fig. 15

6. It co n sists o f a DAC, a com parator, and a su ccessive a p p ro xim a tio n reg ister (SA R ).
O ne term in al is required for analog in p u t v oltage Vin. T h e d ig ital o u tp u t is av ailab le
in eith er serial or parallel form . A m in im u m o f th ree co n tro l te rm in als are req u ired .
S ta rt conversion initiates an A /D conversio n seq u en ce and e n d o f co n versio n tells w hen
the conversion is com pleted. A n ex tern al clo ck term inal sets the tim e to co m p lete each
conversion.
R efer to Fig. 15-6. An input start conversion com m and initiates one analog-to-digital co n
version cycle. The successive approxim ation register (SA R) connects a sequence o f d ig
ital num bers, one num ber for each bit to the inputs o f a DAC. T his process was explained
in C hapter 14.
T he DAC converts each digital num ber into an analog output V0. A nalog input volt
age, Vin, is com pared to VG by a com parator. T he co m parator tells the SA R w hether Vin
is greater or less than DAC output VQi once for each bit. For a 3-bit output, three co m
parisons w ould be made.
C om parisons are m ade beginning w ith the M SB and ending w ith the LSB , as will
be explained. A t the end o f the LSB com parison, the SA R sends an end-of-conversion
signal. T he digital equivalent o f Vin is now present at the S A R ’s digital output.
Vm analog in ----
Successive
approximation Serial output
register (SAR)
Clock in Start of conversion

End of conversion
FIGURE 15-6 Block diagram of a successive approximation 3-bit ADC.
442 Chapter 15
15-3.2 Successive Approximation Analogy
Suppose that you had 1-, 2-, and 4-lb w eights (SA R) plus a balance scale (com parator
and DAC). T hink o f the 1-lb w eight as 1 LSB and the m ost significant 4-lb w eight as 4
LSB. R efer to Figs. 15-6 and 15-7. Vin corresponds to an unknow n weight.
L et us convert Vin = 6.5 V to a digital o u tp u t (unknow n w eig h t = 6.5 lb). You
w ould place the unknow n w eight on one platform o f the balance, the 4-lb w eight on the
other, and com pare if the unknow n w eight (Vin) exceeded the 4-lb w eight. T he S A R uses
one clock pulse to apply the M SB 100 to the DAC in Fig. 15-7. Its output, VQ — 4 V, is
com pared w ith V-m. T he M SB (D 2) is set to 1 if V[n > VQ. T his is analogous to your leav
ing the 4-lb w eight on the scale.
The SAR then applies 110 (add a 2-lb w eight) to the DAC, Dj is set to 1 since Vin =
6.5 V is greater than V0 = 6 V. Finally, the SA R applies 111 to the DAC (add 1 lb). Since
Vin = 6.5 V is less than 7 V, D 0 is set to zero (1-lb w eight rem oved).
15-3.3 Conversion Time
F igure 15-7 show s that one clock pulse is required fo r the SA R to co m pare each bit.
H ow ever, an additional clock pulse is usually required to reset the SA R p rio r to p e r
form ing a conversion. T he tim e for one analog-to-digital conversion m ust depend on both
the clo ck ’s period T and num ber o f bits n. The relationship is
Tc = T(n + 1) (15-8)
E x a m p le 15-6
A n 8-bit successive approxim ation A D C is driven by a 1-M Hz clock. Find its conversion
tim e.
S o lu tio n T he tim e for one clock pulse is 1 /xs. From Eq. (15-8),
T c — 1 f i s(8 + 1) = 9 /ms
15-4 ADCs FOR M ICRO PRO CESSO RS ___________________________________________________
O ne o f the principal selling points o f m any m icrocontrollers is an internal A /D converter.

H ow ever, m icroprocessors do not have internal A /D s, so we m ust use an external device
for analog-to-digital conversion. The m icroprocessor “view s” a peripheral A D C sim ply as
a “read only” address in the m icroprocessor’s m em ory map. R efer to Fig. 15-8. T he A D C
m ust have a tristate m em ory buffer register (M BR). In the idle state, the M B R w ill co n
tain a digital code resulting from the A D C ’s last conversion. A lso, the M B R w ill be d is
connected from the data bus.
Clock Address bus

decoder
Anal
i Chip select
SAR Logic Read/write
Status
Digital
out
Tristate
memory buffer
— fX Digital out
DAC
register — i / to data bus
K
FIG U R E 15-8 To be compatible with microprocessors, the ADC of Fig.

15-6 requires selection logic and a memory buffer register.
T he m icroprocessor uses the address bus and decoders to select one A D C out o f all
the others by bringing its chip select term inal low. A low on the chip select term inal in
Fig. 15-8 tells the A D C that a com m and is com ing to its read /w rite term inal. If read /w rite
is brought low by the m icroprocessor, the A D C converts V-in into a digital code and loads
or w rites it into its own M BR. W hen read /w rite is high a nd chip select is low, the A D C ’s
m em ory buffer register is connected (transparent) to the data bus.
It is im portant to look at this operation from the m icroprocessor’s viewpoint. A read
com m and m eans that the m icroprocessor is going to read data stored in the A D C ’s m em
ory buffer register. T he A D C ’s digital tristate outputs m ust go from high-Z (high im ped
ance) to transparent and connect the digital w ord to the data bus. A write com m and is a c
tually a start conversion com m and to the ADC. T he m icroprocessor thus tells the ADC:
(1) perform a conversion; (2) store (and write) it in your m em ory; and (3) d o n ’t tell me
the result until I w ant to read it.
Finally, the m icroprocessor-com patible A D C m ust tell the m icroprocessor via its
status line w hen a conversion is in progress; the status line goes high. If a conversion is
com pleted, the status line goes low to signal the m icroprocessor that data is valid and
ready for reading. We select the A nalog D evices A D 670 to learn how all the foregoing
features are available in a single 20-pin integrated circuit.
75-5 AD670 M ICROPROCESSOR COMPATIBLE ADC __________________________________
The A D 670 is an 8-bit m icroprocessor-com patible successive approxim ation analog-to-

digital converter. The 20-pin package of Fig. 15-9 contains all the features described in
Section 15-3 and Fig. 15-8. In addition, it contains an on-board clock, voltage reference,
and instrum entation am plifier, and needs only a single 5-V supply. To understand how the
A D 670 operates, we exam ine the tasks perform ed by each o f its term inals and associated
circuit blocks.
75-5.1 Analog Input Voltage Terminals
Four analog input term inals are pins 16, 17, 18, and 19 in Fig. 15-9. They are inputs to
an instrum entation am plifier configured to handle unipolar or bipolar analog input volt
ages. They are also pin-program m able to m ake it easy for the user to select resolution.
F ig u re l5 -9 (a ) show s operatio n for an analog input o f 0 to 2.55 V, reso lu tio n =
10 m V /LSB. F igure 15-9(b) shows operation for 0 to 255 mV or 1 m V /LSB.
75-5.2 Digital Output Terminals
P ins 1 through 8 are tristate, buffered, latching digital outputs for the data bus digits, D 0
through Z)7, respectively. W hen a m icroprocessor tells the A D 670 to perform a conver
sion (w rite), the result is latched into its m em ory buffer register. Tristate output sw itches
are held in the high-im pedance (high-Z) state until the m icroprocessor sends a read co m
m and. T hus the A D C ’s m em ory register is norm ally disconnected from the data bus.
15-5.3 Input Option Terminal
Pin 11 is called BPO /U PO and allow s the m icroprocessor to tell the A D 670 w hether to
accept a bipolar analog input voltage range or a unipolar input range. A low on pin 11 se
lects unipolar operation. A range of 0 to 2.55 V or 0 to 255 mV is set by the user as in
Figs. 15-9(a) and (b). A high sent to pin 11 selects bipolar operation. T he Vin range is
then ± 1 .2 8 V [Fig. 15-9(a)] or ± 1 2 8 mV [Fig. 15-9(b)].
15-5.4 Output Option Terminal
In Fig. 15-9, pin 12 is labeled “2 ’s/B IN .” It allows the m icroprocessor to tell the A D 670
to present an output fo rm a t in either 2 ’s-com plem ent code or binary code. A binary out
put code form at w ill be straight binary if Vin is unipolar (pin 11 = low) or offset binary
if Vin is bipolar (pin 11 = high). The four possible options are show n in Fig. 15-10(a).
The digital output responses to analog input Vin are show n in Figs. 15-10(b) and
(c). Vin is the differential input voltage and is defined by
v in = ( + v in) - ( - v in)
w here + Vin and - V in are m easured w ith respect to ground.
75-5.5 M icroprocessor Control Terminals
As show n in Fig. 15-9, pins 13, 14, and 15 are used by a m icroprocessor to control the
A D 670. Term inal 14 is called chip select (CS) and term inal 15 is called chip enable (CE).
Pin 13 is called rea d /w rite (R/W ).
If CS, CE, and R/W are all brought low, the A D C converts continuously. It perform s
one conversion every 10 jjls or less. T he result o f each conversion is latched into the o ut
put buffer register. H ow ever, the digital output code is not co nnected to the data bus
446 Chapter 15
Pin 11 Pin 12
Input range Output format
BPO /U PO 2 ’s/BIN
0 Unipolar 0 Straight binary
1 Bipolar 0 Offset binary
0 Unipolar I 2 ’s com plem ent
1 Bipolar 1 2 ’s com plem ent
(a)
Differential Unipolar/straight binary, Differential Bipolar/offset binary, Bipolar/2’s com plem ent,
pin 1 1 = 0 , 12 = 0 în pin 11 = 1, 12 = 0 pin 11 = 1 ,1 2 = 1
0 0000 0000 -1 2 8 mV 0000 0000 1000 oooo

1 mV 0000 0001 -1 mV 0111 1111 1111 1111
128 mV 1000 0000 0 1000 0000 0000 0000
255 mV 1111 1111 1 mV 1000 0001 0000 0001
127 mV 1111 1111 0111 1111
(b) (c)
FIGURE 15-10 Input ranges are unipolar or bipolar, and output formats are determined
by pins 11 and 12 in (a). Output codes are given for unipolar inputs in (b) and for bipo
lar inputs in (c). (a) Input range and output format are controlled by pins 12 and 11, re
spectively; (b) digital output codes for unipolar Vin inputs wired as in Fig. I5-9a; (c) dig
ital output codes for bipolar Vin inputs wired as in Fig. 15-9b.
because the outputs are high im pedance. This condition is called a write an d convert co m
m and; that is, the m icroprocessor tells the A D 670 to w rite converted data into its own
buffer register. If CS or R/W or CE is high, the A D 670 is unselected (high im pedance)
and retains the last conversion in its register.
T he status term inal, pin 9, stays high during a conversion. W hen a conversion is
co m pleted, pin 9 outputs a low to ' ‘te ll” the m icro p ro cesso r th at d ata is valid in the
A D 6 7 0 ’s buffer register. To read data out o f the A D 670, the m icroprocessor brings R/W
high w hile status and CS and C E are low. T his is a read co m m and fro m the m icro
processor.
T he A D 670’s buffer becom es transparent and connects the eight digital outputs (D 7
through D 0) to the data bus. D ata will rem ain on the bus until the A D 670 is disconnected
by bringing CS high, C E high, or R /W low.
Summary
1. A louôn C E and CS selects the A D 670. W hat happens next depends on R/W .
2. If R/W is low (for at least 0.3 jus), a conversion is perform ed and the result is written
into the buffer register. Outputs are high impedance. The conversion requires 10 jjls.
3. If R /W is high, the last conversion is stored in the buffer and the outputs are trans
parent. N o further conversions are perform ed. T he contents o f the register can now
be read by the m icroprocessor via the data bus.
4 . Status tells the m icroprocessor w hat is going on w ithin the A D 670. Status = high
m eans that conversion is being perform ed. Status = low tells the m icroprocessor that
data are valid. The m icroprocessor is free to read the selected A D 6 7 0 ’s data by plac
ing a high to R/W .
15-6 TESTING THE AD670 _________________________________________________________________
F igure 15-11 shows how to w ire an A D 670 to perform continuous conversions without a
m icroprocessor. This circuit can be used as a laboratory exercise to gain experience op
erating A DCs. Each data output, D 0 through D 7, is connected to an inverter, resistor, and
LED. These com ponents sim ulate a data bus. An LED lights to signify that a logic 1 is
present on its associated data bus w ire.__
Pins 14 and 15 are w ired so_that C S and C E are low. This causes continuous^con
version. The 555 tim er drives R/W low for 5 /xs to sim ulate a w rite com m and. R /W thus
returns high before a conversion is com pleted in the 10-/xs conversion tim e. At the end
o f 10 jJLs, the high on R /W sim ulates a read com m and and data are displayed on the LEDs.
If R r = 1.5 M t h e A D 670 m akes one conversion and one readout 1000 tim es per sec
ond. R educe R r to 120 k f l for convert/reads o f 10,000 tim es per second.
15-7 FLASH CON VERTERS ________________________________________________________________
15-7.1 Principles of Operation
Fastest o f all A/D converters is the fla s h converter, shown in Fig. 15-12(a). A reference
voltage and resistor divider netw ork establishes a resolution o f 1 V/LSB. A nalog input
voltage V[n is applied to the + inputs o f all com parators. T heir outputs drive an 8-line-to-
3-line priority encoder. T he encoder logic outputs a binary code that represents the ana
log input.
For exam ple, suppose that Vin = 5.0 V. The outputs of com parators 1 through 5
w ould go high and 6 through 8 w ould go low. As shown in Fig. 15-12(b), the digital ou t
put w ould be 101.
15-7.2 Conversion Time
The conversion tim e o f the flash converter is lim ited only by the response tim es o f com
parators and logic gates. They can digitize video or radar signals. T he flash converter’s
high speed becom es more expensive as resolution is increased. Figure 15-12 shows that
the flash converter requires seven com parators (or 2 3 — 1) to perform a 3-bit conversion.
The num ber o f com parators required for n-blt resolution is
num ber o f com parators = 2n — 1 (15-10)

448
R în
io k n 0 -4 4 0 mV
10 kQ II820 a 0 -2 .6 0 V
Conversions +5 V
Rr
per second
+5 V +5 V
{
1.5 M Q. 1,000
20
120 k a 10(000
+High
+Low
Do
-H igh D,
-L ow D2
AD670
D*
BPO/UPO
2’s/BIN
R/W
6.8 kQ
D4
Ds
CE
CT - CS D7
0.001 fiF
10
Simulates
data bus
All 270 Q
or 330 Q
1 of 8 LEDs
- M icroprocessor sim ulator - A /D converter ■ Digital display ■
FIGURE 15-11 The operation of the AD670 can be studied without the need for a mi
croprocessor. Pins 14 and 15 can be grounded to simulate a microprocessor selection via
on a H r l r d c c V in e o im n h tp c m n tin n m ie P A m m a n rlc fro m 3 m irrr * -
450 Chapter 15
F or exam ple, an 8-bit flash converter requires (28 — 1) or 255 com parators. E ncoder logic
w ould be m ore com plex, requiring a 256-line-to-8-line priority encoder.
15-8 FREQ U EN CY RESP O N SE O F ADCs
15-8.1 Aperture Error
D uring conversion tim e, T c , the analog in p u t voltage m ust not change by m ore than
± 7 LSB (total 1 LSB), or the conversion w ill be incorrect. T his type o f inaccuracy is
called aperture error. The rate of change o f Vin w ith respect to tim e is called slew rate.
If V-m is a sine wave, its slew rate is m axim um at its zero crossings. T he sine w ave’s slew
rate is determ ined by both its peak voltage and frequency.
For an A /D converter, the m axim um frequency for a sine w ave Vin to be digitized
w ithin an accuracy of LSB is
1
/m ax (15-11)
2 tt (T c )2n
Example 15-7
T he A D 670 is an 8-bit A D C w ith a conversion tim e o f 10 jjls. Find the m axim um frequency
o f an input sine wave that can be digitized w ithout aperture error.
S o lu tio n From Eq. (15-11),
1 1
frrn = 62 Hz
2ir (2 )10 fis 2rr (256)10 X 10“ 6 s
E xam ple 15-7 shows that the frequency response o f even a fast A D C is surprisingly
low. For a 10-bit integrating A D C w ith a conversion tim e o f j s, the highest sine frequency
is about 0.5 m Hz, or 1 cycle per 2000 s.
Summary. An 8-bit converter w ith a conversion tim e can theoretically

perform [1/(10 /Jis)]fxs = 100,000 conversions per second, yet the highest frequency sine
w ave that can be converted w ithout slew -rate lim iting is about 62 cycles per second. To
raise the frequency response, we m ust add another circuit block, the sam ple-and-hold or
follow er-and-hold am plifier.
15-8.2 Sample-and-Hold Amplifier
T he sam ple-and-hold (S/H ) or follow -and-hold am plifier o f Fig. 15-13 is m ade from two
op am ps, a hold capacitor (CH), and a high-speed analog sw itch. This am plifier is co n
nected betw een an analog input signal and the input to an ADC.
VinO-
-1 5 V
Sample/hold
control
FIGURE 15-13 Sample-and-hold amplifier.
W hen the S/H am plifier is in the sam ple m ode, the sw itch is closed and hold ca
pacitor (C H) voltage fo llo w s Vin. A h old com m and opens the sw itch and CH retains a
charge equal to Vin at the m om ent of sw itching. The S/H am plifier thus acts to hold Vin
(stored on CH) constant, w hile the A D C perform s a conversion.
C onversion tim e o f the A D C no longer lim its frequency response. Instead, the lim it
is the aperture tim e of the S/H am plifier, w hich can be m ade m uch less than the conver
sion tim e. A perture tim e is the tim e elapsed betw een a hold com m and and a sw itch o pen
ing. If the hold com m and is advanced by a tim e equal to the aperture tim e, CH will hold
the desired sam ple o f Vin. T hen the only rem aining error is aperture tim e uncertainty, the
sw itch jitte r variation for each hold com m and.
C om m ercial S/H am plifiers have aperture tim e uncertainties low er than 50 ns. An
exam ple show s the im provem ent in frequency response due to an added S/H am plifier.
Example 15-8
An S/H am plifier w ith an aperture tim e uncertainty o f 50 ns is connected to an 8-bit ADC.

Find the highest-frequency sine wave that can be digitized w ithin an error o f 1 LSB.
S o lu tio n R eplace conversion tim e by aperture uncertainty tim e in Eq. (15-11):
1
/m ax = 12.4 kH z
2 tt (2 8)50 X 10“ 9 s
PROBLEMS
15-1. A 10-bit A/D converter is capable of accepting an input voltage 0 to 5.12 V. What is the
digital output code if the input voltage is 2.4 V?
452 Chapter 15
15-2. If the 8-bit A/D converter of Example 15-2 has an offset error of —\ LSB, what analog
input voltage will cause the digital output to be all Is?
15-3. Note that the A/D converter of Example 15-1 has an offset error of LSB and a gain
error of —0.4% of FSR. What is the analog input voltage needed to cause the digital out
put to be all Is?
15-4. Name three types of ADCs and indicate their relative conversion speeds (slow or fast).
15-5. Vjn = 50 mV in the integrating ADC circuit of Fig. 15-5.
(a) What is the duration for integrating phase T{ and the value of VD1
(b) What is the name of phase T2, the value of Vref, and the duration of T21
(c) Find the circuit output.
15-6. Name the three components of a successive approximation 8-bit ADC.
15-7. A microprocessor issues a write command to an ADC. Does the ADC send data to the
microprocessor or perform a conversion?
15-8. An input voltage with a range of 0 to 2.55 V is applied to pin 16 of an AD670 and pin 18
is grounded. Which other input pins should be jumpered or grounded to select this range?
15-9. How do you pin-program the AD670 for straight binary output?
15-10. How does a microprocessor “tell” an AD670 to (a) perform a conversion; (b) place the re
sult on the data bus? (c) How does the microprocessor know when the AD670 has finished
a conversion and its data are valid?
15-11. (a) What is the conversion time for an AD670?
(b) How many conversions can it perform per second?
(c) What is the maximum sine wave frequency that it can convert without adding a sample-
and-hold amplifier?
15-12. If the sample-and-hold amplifier of an 8-bit ADC has an aperture uncertainty time of 10 ns,
what maximum sine wave frequency can it convert within ±{ LSB?
15-13. How many comparators are required to make an 8-bit flash converter?
CHAPTER 16
Power Supplies
LEARNING O B JECTIV ES ____________________________________________________
U pon com pletion o f this chapter on pow er supplies, you will be able to:
• Draw the schem atic for a full-w ave bridge (FW B) rectifier unregulated pow er supply.
• Identify the com ponents o f an FW B and tell w hat each com ponent does in the circuit.
• D esign an FW B rectifier; choose the specifications for the transform er, diodes, and ca
pacitor; purchase these com ponents from standard stock; build the rectifier; test it; and
docum ent its perform ance.
• M easure the percent regulation and percent ripple, draw the load voltage w aveshapes at
no load or full load, and plot the regulation curve for an FW B unregulated pow er supply.
• D esign or analyze a bipolar or tw o-value unregulated pow er supply.
• Explain the need for voltage regulators.
° C on n ect an IC voltage regulator to an unreg u lated FW B rectifier circu it to m ake a
voltage-regulated pow er supply.
453
454 Chapter 16
• D esign, build, and test a ± 1 5 -V regulated pow er supply for analog ICs.
• Build a regulated 5-V supply for T T L logic.
• C onnect an LM 317 to an unregulated supply to obtain a laboratory-type voltage regula
tor that can be adjusted precisely to a required voltage.
16-0 INTRODUCTION _________________________________________________________________________
M ost electronic devices require dc voltages to operate. B atteries are useful in low -pow er
or portable devices, but operating tim e is lim ited unless the batteries are recharged or re
placed. T he m ost readily available source o f pow er is the 60-H z 1 10-V ac wall outlet. T he
circuit that converts this ac voltage to a dc voltage is called a dc p o w e r supply.
T he m ost econom ical dc pow er supply is som e type o f rectifier circuit. U nfortunately,
som e ac ripple voltage rides on the dc voltage, so the rectifier circuit does not deliver pure
dc. An equally undesirable characteristic is a reduction in dc voltage as m ore load current
is draw n from the supply. Since dc voltage is not regulated (that is, constant w ith ch an g
ing load current), this type o f pow er supply is classified as unregulated. U n reg u lated
pow er supplies are introduced in Sections 16-1 and 16-2. It is necessary to know their
lim itations before such lim itations can be m inim ized or overcom e by adding regulation.
It is also necessary to build an unregulated supply before you connect a voltage regulator
to it.
W ithout a good regulated voltage supply, none o f the circuits in this text (or any
other text for that m atter) will work. T herefore, this chapter shows the sim plest w ay to
analyze or design pow er supplies for linear or digital ICs.
It is possible to m ake a good voltage regulator w ith an op am p plus a zener diode,
resistors, and a few transistors. However, it is w iser to use a m odern integrated circuit
voltage regulator. The types of superb regulators are so vast there is no problem in find
ing one that will suit your needs.
We will present an op am p regulator to illustrate the w orkings o f a few o f the fea
tures w ithin an IC regulator. Then we will proceed to a representative sam pling o f som e
o f the w idely used IC voltage regulators. B ut we begin w ith the unregulated supply.
16-1 INTRODUCTION TO THE UNREGULATED POWER SUPPLY _____________________
16-1.1 Power Transformer
A transform er is required for reducing the nom inally 115-V ac wall outlet voltage to the
low er ac value required by transistors, ICs, and other electronic devices. T ransform er volt
ages are given in term s o f rm s values. In Fig. 16-1, the transform er is rated as 115 to
24 V center tap. W ith the 115-V rm s connected to the prim ary, 24-V rm s is developed b e
tw een secondary term inals 1 and 2. A third lead, brought out from the center o f the sec
ondary, is called a center tap, CT. Betw een term inals C T and 1 or C T and 2, the rm s volt
age is 12 V.
Power Supplies 457
nated positive or negative. It is &flo a tin g supply. If you w ant a “ positive” supply, you
m ust "earth ground” the negative term inal.
The third w ire (green) o f the line cord extends earth ground from the “U ”-shaped
term inal of the wall outlet, usually to the metal chassis. This connection is to protect the
user. Sim ply extend the green w ire term inal to the negative term inal and call this term i
nal p o w er supply com m on. All voltage m easurem ents are w ith respect to pow er supply
com m on, and it is designated in a schem atic by a ground sym bol. To m ake a negative sup
ply, sim ply earth ground the positive term inal of the bridge.
76-7.4 Filter Capacitor
T he pulsating dc voltage in Fig. 16-2(a) is not pure dc, so a filter capacitor is placed across
the dc output term inals of the bridge rectifier [see Fig. 16-2(b)]. This capacitor sm ooths
out the dc pulsations and gives an alm ost pure dc output load voltage, VL, w hich is the
unregulated voltage that supplies pow er to the load. The filter capacitor is typically a large
electrolytic capacitor, 500 p F or more.
76-7.5 Load
In Fig. 16-2(b), nothing other than the filter capacitor is connected across the dc output ter
minals. The unregulated pow er supply is said to have no load. This means that the no-load
current, or 0-load current, 1L> is drawn from the output term inals. Usually, the m axim um ex
pected load current, or full-load current, to be furnished by the supply is known. The load
is m odeled by resistor R L as shown in Fig. 16-3(a). As stated in Section 16-0, the load volt
age changes as the load current changes in an unregulated pow er supply. The m anner in
which this occurs is examined next. But the key idea to pow er supply analysis now becom es
clear. The peak value of secondary ac voltage Em determ ines the dc no-load voltage o f VL.
16-2 DC VOLTAGE REGULATION ------------------------------------------------------------ -
16-2.1 Load Voltage Variations
A dc voltm eter connected across the output term inals in Fig. 16-2(b) m easures the dc no
load voltage of VL, or
Vdc no load = Em ( 16-2)
F rom E xam ple 16-1, Vdc no load is 34 V. An oscilloscope w ould also show the sam e value
w ith no ac ripple voltage, as in Fig. 16-3(b). N ow suppose that a load RL was connected
to draw a full-load dc current of lL = 1 A, as in Fig. 16-3(a). An oscilloscope now shows
that the load voltage VL has a low er average, or dc value Vdc. M oreover, the load voltage
has an ac ripple com ponent, AV0, superim posed on the dc value. The average value m ea
sured by a dc voltm eter is 24 V and is called Vdc full load. T he peak-to-peak ripple volt
age is called AV0 and m easures 5 V in Fig. 16-3(b).
458 Chapter 16
Dc output
terminal
To bridge Vl
rectifier ^ Full-load
(Fig. 16-2) 1000 n F ' voltage
(a) Load resistor RL draws current from the power supply.
VL (V)
A
40 ' VL at no load = Vdc no load
30
AV0 = ac ripple voltage

24
CRO measurem ent
20
Vdc full load = 24 V

10 dc voltm eter
B C
■/ (ms)
0 8.3 16.6
(b) Load voltage changes from 34 V at no load to 24 V plus ripple at full load.
FIG U RE 16-3 Variation of dc load voltage and ac ripple voltage from no-load
current to full-load current.
T here are two conclusions to be draw n from Fig. 16-3(b). First, the dc load voltage
goes dow n as dc load current goes up\ how m uch the load voltage drops can be estim ated
by a technique explained in Section 16-2.2. Second, the ac ripple voltage increases from
0 V at no-load current to a large value at full-load current. As a m atter o f fact, the ac rip
ple voltage increases directly w ith an increase in load current. The am ount o f ripple volt
age can also be estim ated, by a technique explained in Section 16-3.
16-2.2 DC Voltage Regulation Curve
In the unregulated pow er supply circuit Fig. 16-4(a), the load R L is varied so that we can
record corresponding values of dc load current and dc load voltage. T he dc m eters re
spond only to the average (dc) load current or voltage. If corresponding values o f current
and voltage are plotted, the result is the dc voltage regulation curve o f Fig. 16-4(b). For
exam ple, point O represents the no-load condition, IL = 0 and Vdc no load = E m = 34 V.
P oint A represents the full-load condition, IL = 1 A and Vdc full load = 24 V.
Power Supplies 461
16-2.4 Percent Regulation
A nother way to describe dc perform ance is by a specification called percent regulation.

You m easure the supply’s no-load voltage and full-load voltage. Percent regulation is then
calculated from
% regulation = ^ dc N.L-----^ dc FL X 100 (16-4)

* d c FL
Example 16-3
Find percent regulation for the dc pow er supply data in Figs. 16-4 and 16-5.
Solution From the data, Vdc NL = 34 V and Vdc FL = 24 V. From Eq. (16-4),
% regulation = — ~ 24) V X 100 = 4] .1%

24 V
P ercent regulation tells you by what percen t the fu ll-lo a d voltage will rise w hen you
rem ove the load.
16-3 AC RIPPLE VOLTAGE
16-3.1 Predicting AC Ripple Voltage
Figure 16-6(b) show s how to m easure both ac and dc perform ance o f a pow er supply. Dc
m easurem ents (average values) are m ade w ith dc m eters. T heir m easured dc values, IL
and Vdc, arc sum m arized and plotted as the (dc) voltage regulation curve o f Fig. l6-4(b).
T he peak-to-peak ac ripple voltage &V0 is centered on Vdc. AV0 can be estim ated
from
AV - II
(l6 -5 a )
200C
w here k V 0 is in volts, IL in am peres, and C is the size o f the filter capacitor in farads. If
load voltage VL is m easured with an ordinary ac voltm eter, it will indicate the rms value
o f the ripple voltage Vrms. A coupling capacitor w ithin the m eter elim inates the dc co m
ponent. Vrms is related to A V 0 by the approxim ation
AV„ - 3.5 Vrr (l6 -5 b )
We need one other characteristic o f the pow er supply that will be used later in the
chapter. It tells us how to design a pow er supply for a voltage regulator. It is called m in
im um instantaneous load voltage and it occurs at full load. As seen in Fig. l6 -6 (b ),
466 Chapter 16
Design Summary We end up w ith an FW B rectifier that has the follow ing parts:
1. T ransform er: 115 V/18 V at 2.0 A
2. Four diodes: each 1 A at PIV = 25 V (or m ore)
3. T hree capacitors: 500 /xF connected in parallel, W V D C = 25 V (or m ore)
We do not have a satisfactory design, but that is often the nature o f practical solu
tions for unregulated pow er supplies. H ow ever, let us use this design to analyze and p re
dict perform ance of an FW B rectifier.
Analysis Example 16-7: FWB Unregulated Supply
Given the pow er supply design schem atic of Fig. 16-7(a), (a) predict its dc perform ance by
plo ttin g a dc reg u la tio n curve and ca lc u latin g p erc en t reg u latio n . A ssu m e: R 0 — 7 f l,
1l f l = 1-0 A; (b) plot the no-load and full-load instantaneous voltage VL that you w ould
expect to see on an oscilloscope. A lso calculate percent ripple.
Solution (a) Since E ^ = 1 8 Vm s, calculate Em and Vdc NL from Eqs. (16-1) and (16-2)
VdcNL = E m = \ A E rms = 25.5 V
C alculate Vdc ^ from Eq. (16-3a):
V/d cN L - l L F L R 0 = 2 5 . 5 V - ( 1 A )(7 f l) = 18.5 V
and percent regulation from Eq. (16-4):
% regulation = Vdc NL ~ Vdc FL X 100 = I 2 5 -5 ~ _18-5 )_ X x 100 = 38%

VdcFL 18.5
(b) C alculate A V 0 from Eq. (16-5a) and from Eq. (16-5b):
1A
AV0 =* ^ ------------- = 5 V
200C 200(1000 X 10“ 6 F)
Finally, calculate percent ripple from Eq. (16-6):
% ripple = 100 = X 100 = 7.7%

Vdc fl 18.5
Dc perform ance o f the unregulated pow er supply is depicted in Fig. 16-7(b). Ac p er
form ance is sum m arized by the tim e plots at both no load and full load in Fig. 16-7(c). N ote
that &V0 = 0 V at no-load current. A lso, A V 0 is (approxim ately) centered on Vdc Fl*
Power Supplies 469
16-5.2 Two-Value Power Supplies
If the center tap o f the pow er supply o f Fig. 16-8 is grounded, we have a bip o la r p o
w er supply. It is show n schem atically in Fig. 16-8(b). If term inal 2 is grounded as in
Fig. I6-8(c), we have a tw o-value positive supply. Finally, by grounding term inal 1 in
Fig. 16-8(d), w e get a tw o-value negative pow er supply. This indicates the versatility of
the center-tapped transform er.
16-6 NEED FOR VOLTAGE REGULATION
Previous sections have show n that the unregulated pow er supply has tw o und esirab le
characteristics: the dc voltage decreases and the ac ripple voltage increases as load cu r
rent increases. B oth disadvantages can be m inim ized by adding a voltage-regulator sec
tion to the unregulated supply as in Fig. 16-9. The resulting pow er supply is classified as
a voltage-regulated supply.
Voltage-regulated supply
A
115 V- Unregulated Voltage

60 Hz ■ supply regulator dc voltage
FIGURE 16-9 Unregulated supply plus a voltage regulator gives a voltage-

regulated power supply.
16-7 THE HISTORY O F LINEAR VOLTAGE REGULATORS
16-7.1 The First Generation
An excellent dc voltage regulator can be built from an op am p, zener diode, two resistors
or one potentiom eter, and one or m ore transistors. In 1968, F airch ild S em ico n d u cto r
Division integrated all of these com ponents (plus others) into a single IC and called it the
/xA723 m onolithic voltage regulator. B ecause o f its flexibility, it has survived to the p res
ent day. It does, however, require a num ber o f support com ponents, has m inim al internal
protection circuitry, and requires the user to add boost transistors for m ore current cap a
bility and a resistor for lim iting short-circuit current.
T he race w as on to m ake a th ree -term in a l fix ed -v o ltag e regulator. N atio n al
S em iconductor won w ith the LM 309, in a close finish w ith F airch ild ’s 7800 series. The
LM 309 and /iA 7805 have three term inals. To use one, all you have to do is connect an
u n reg u lated supply betw een its input and com m on term in als. T h en co n n ect a load
470 Chapter 16
betw een the output and com m on and the design is com plete. (C onnect a decoupling ca
pacitor across both input term inals and output term inals to im prove perform ance.) T hese
devices have internal protection circuitry that w ill be discussed later.
16-7.2 The Second Generation
The success of the + 5-V regulators changed the philosophy of many system designers. There
was no need to have a central regulator supplying current to each circuit board in the system
and suffering the large I2R loss. Now each printed circuit card could have its own on-board
local regulator. T he local regulator also protected its ICs against line voltage transients.
T he + 5-V regulator’s success spaw ned an array o f three-term inal regulators o f 6,
8, 9, 12, 15, 18, and 24 V and their negative counterparts. Now, if you need a 15-V reg
ulator to furnish 1 A, you sim ply buy one.
16-7.3 The Third Generation
L in ear IC regulators w ere so p opular that they created serious p ro b lem s fo r o riginal
equipm ent m anufacturers (O EM s). How do you stock all these sizes, and how do you
m ake enough to suit the grow ing num ber o f voltage requirem ents?
T he L M 117 was the first successful superior-perform ance adjustable positive IC
voltage regulator. It w as follow ed by the LM 137 adjustable negative regulator. We will
present only a few o f the bew ildering array o f linear IC regulators. Space does not per
mit presentation o f the sw itching regulators.
16-8 LINEAR IC VOLTAGE REGULATORS _________________________________________________
16-8.1 Classification
L inear IC voltage regulators are classified by four characteristics:

1. Polarity: negative, positive, or dual tracking.
2. Term inal count: three-term inal or m ultiterm inal.
3. F ixed o r a d ju sta b le o u tp u t voltage: stan d ard fixed voltag es are ± 5 , ± 1 2 , and
± 1 5 V. A djustable range is typically 1.2 to 37 V or - 1 . 2 to —37 V.
4. O utput current: Typical output current capabilities are 0.1, 0.2, 0.25, 0.5, 1.5, and
3 A and the new 5 and 10 A.
16-8.2 Common Characteristics
The instantaneous voltage at the input of an IC regulator m ust always exceed the dc output
voltage by a value that is typically equal to 0.5 to 3 V. This requirem ent is called m inim um
instantaneous input-output voltage, dropout voltage>or simply headroom. As shown in Fig.
16-10(a), the LM 340-15 voltage regulator has an output voltage of 15 V at a load o f 1 A.
472 Chapter 16
S uppose that the unregulated pow er supply that feeds the regulator has a 1000-îF
capacitor and thus a ripple voltage o f = 5 V. As show n in Fig. 16-10(a), you need a
m inim um input voltage of
V l min = Vo reg + headroom (16-8)
or
Vz.m in= 15 V + 3 V = 18 V
This m eans that Vdc FL m ust be 20.5 V at the very least [see Eq. (16-5c)]. A lthough you
m ight be tem pted to m ake Vdc FL high to give plenty o f headroom , you m ust rem em ber
that the w orst regulator heat pow er is IL f l( K jc FL — VQreg). So there is your trade-off. A
higher Vdc w astes m ore heat in the regulator.
16-8.3 Self-Protection Circuits
The internal circuitry of these devices senses the load current. If the load current exceeds
a specified value, the output current is autom atically lim ited until the overload is rem oved.
They also m easure both their in p u t-o u tp u t difference voltage and load current to be sure
that no disallow ed com bination occurs. If it does, the regulator shuts down. T his feature
is called safe area protection.
Finally, these regulators even m easure their own tem perature to see if you heat-
sinked them properly. If the internal die tem perature exceeds 150° to 175°C, they shut
down. If you rem ove the fault, the regulator goes back to work.
16-8.4 External Protection
D espite the w ell-designed internal protection circuitry, regulators can still be dam aged by
m isuse, sabotage, or certain failures o f external circuits. The m easures you can take to
safeguard against these eventualities are given in the data sheets o f a particular regulator.
16-8.5 Ripple Reduction
M anufacturers of linear IC regulators specify their ac perform ance by a p aram eter called
ripple rejection. It is the ratio o f the peak-to-peak input ripple voltage \ V 0 unreg to the
peak-to-peak output ripple voltage AVC reg. It is typically 60 dB or more. T h at is a re
duction in ripple voltage o f at least 1000:1. For exam ple, if 5 V o f ripple is at the reg u
lator’s input, less than 5 mV appears across the load. We now turn our attention to spe
cific applications for IC regulators.
16-9 POWER SUPPLY FOR LOGIC CIRCUITS _____________________________________________
16-9.1 The Regulator Circuit
A + 5 V digital pow er supply for T T L logic or certain m icroprocessors is show n in Fig.

16-11. T he K package o f the L M 340-05 is a steel TO -3 case and should be heat sinked
Power Supplies 473
for a case-to-am bient therm al resistance o f a 6°CAV or less. This m eans that you should
use a 0.002-in.-thick insulating therm al w asher w ith therm al jo in t com pound betw een the
TO -3 case and its heat sink (or use the chassis as a heat sink).
The L M 340K -05 can furnish up to 1.5 A. It has internal current lim it at 2.1 A for
pulse operation. It also has safe area protection that protects its output transistor. It has
therm al shutdow n protection at a junction tem perature o f 150°C to prevent burnout. T he
added diode protects the regulator against short circuits occurring at its input term inals.
IN4002
To
unregulated To load,
supply ' 0.22 (j.F <?2Gnd o.l |iF ' up to 1.5 A
V, mi n — 8 V
FIGURE 16-11 A TTL digital logic regulated power supply (5 V at 1 A .)
16-9.2 The Unregulated Supply
\ l min f ° r the unregulated FW B supply should allow 3 V o f headroom and should be

g reater than (3 + 5) V = 8 V (see Fig. 16-11). C hoose a 12.6-V tran sfo rm er (1.8 X
1 A) at a 2-A current rating. From Sections 16-2 and 16-3: (1) Vdc NL = 12.6 V X 1.4 =
17.8 V. (2) A ssum e that R 0 = 6 f l. If IL FL = 1 A, then Vdc f l - 17.8 V - 6 f t ( l A) =
11.8 V. (3) Pick a 1000- jjF filter capacitor to give a A V 0 = 5 V. Thus, VLmin should be
at least 11.8 V - (5 V /2) = 9.3 V, leaving som e margin. Pick the capacitor W V D C >
25 V and diodes w ith a 25-V PIV rating. The diode current rating should exceed 1 A.
16-10 ± 75-1/ POWER SUPPLIES FOR LINEAR APPLICATION
16-10.1 High-Current ± 15-V Regulator
Figure 16-12(a) presents a bipolar ± 15 V supply that can furnish 1 A from either ( + ) or
( —) term inal. T he L M 340K -15 is a + 1 5 -V regulator w ith load current capability up to
1.5 A. To use it as a stand-alone + 15-V supply, (1) rem ove the diodes, R 2, CN, and the
LM 320-15; and (2) replace R x w ith a short circuit.
T he LM 320K -15 is a - 15-V regulator with current capability up to 1.5 A. B oth reg
ulators have current lim it, safe area, and therm al shutdow n protection. They should be
heat-sinked as directed in Section 16-10.2.
Power Supplies 475
package that can furnish ± 1 0 0 mA. It has internal current lim iting and therm al overload
protection. (Buy a clip-on heat sink, or epoxy about a 2-in. X 2-in. piece o f alum inum to
the top surface.)
N ote that the LM 325 has tw o excellent voltage regulators packed into a single IC.
The output capacitors provide energy storage to im prove transient response. The input ca
pacitors are needed if the unregulated supply is m ore than 4 in. from the LM 325.
16-10.3 Unregulated Supply for the ± 15-V Regulators
The unregulated supply required is show n in Fig. 16-8. Select:

1. C + = C — = 1000 /jlF m inim um for both high- and lo w -cu rre n t su p p lies, w ith
W V D C = 30 V.
2. For the ± 1-A supply, select a transform er o f 115 V/36 V CT at 2 A. For the ± 100-
mA supply, select a 115 V /30 V CT at 0.2 A.
3. D iodes should be rated for / av > 1.0 A for the high-current supply and ^ 0 .1 A for the
low -current supply. PIV ratings for both should exceed 30 V (50 V is a standard size).
16-11 A D JUSTABLE THREE-TERMINAL POSITIVE VOLTAGE REGULATOR (THE

LM317HV) AND NEGATIVE VOLTAGE REGULATOR (THE LM337HV) ________
T here is a need for ( l) regulated load voltages that are variable for laboratory supplies,
(2) supply voltages that are not available as standard fixed-voltage regulators, (3) a very
precisely adjustable supply voltage, or (4) providing a price-break low er cost for users
w ho w ould like to stock a large quantity o f one IC regulator type to furnish a variety of
regulated output voltages.
The L M 1 17 and LM 137 fam ilies o f adjustable three-term inal positive and negative
voltage regulators, respectively, w ere developed. They are superb regulators with all the
internal protection circuitry listed for the regulators in Sections 16-9 and 16-10. Since
they are so versatile, they will encounter a variety o f hostile applications, so it is prudent
to add the external protection circuitry presented in Section 16-12.4.
16-12 LOAD VOLTAGE A D JU STM EN T ------------------------------------------------------
16-12.1 Adjusting the Positive Regulated Output Voltage
The LM 317H V adjustable positive voltage regulator has only three term inals as shown in
Fig. 16-13(a). Installation is sim ple, as shown in Fig. 16-13(b). The LM 317 m aintains a
nominal 1.25 V between its output and adjust term inals. This voltage is called Vref and can
vary from chip to chip from 1.20 to 1.30 V. A 240-H resistor, R u is connected betw een these
term inals to conduct a current of 1.2 V/240 (1 = 5 mA. This 5 m A flows through R 2. If R 2
is adjustable, the voltage drop across it, VR2, will equal R 2 X 5 mA. O utput voltage o f the
regulator is set by V ^ plus the 1.2-V drop across R }. In general terms, V0 is given by
Power Supplies 477
For exam ple, if you need a 5-V supply for T T L logic, m ake R 2 = 760 ft. If you
need a + 15-V supply for an op am p or CM O S, m ake R2 = 2760 fL R 2 = 2160 Ct will
give you 12-V car voltage. M ake R 2 a 3-kH pot and you can adjust Va to any voltage b e
tw een 1.2 V (D -cell battery) and 16.2 V.
16-12.2 Characteristics of the LM317HVK
The LM 317H V K w ill provide a regulated output current o f up to 1.5 A, provided that it
is not subjected to a pow er dissipation o f m ore than about 15 W (TO-3 case). This m eans
it should be electrically isolated from , and fastened to, a large heat sink such as the metal
chassis o f the pow er supply. A 5-in. X 5-in. piece o f alum inum chassis stock also m akes
an adequate heat sink (see Section 16-10.1).
The LM 317 requires a m inim um “dropout” voltage o f 3 V across its input and o u t
put term inals or it will drop out of regulation. T hus the upper lim it o f VD is 3 V below the
m inim um input voltage from the unregulated supply.
It is good practice to connect bypass capacitors C\ and C2 (l-/x F tantalum ) as shown
in Fig. 16- 13(b). C, m inim izes problem s caused by long leads betw een the rectifier and
LM 317. C2 im proves transient response. Any ripple voltage from the rectifier will be re
duced by a factor of over 1000 if R 2 is bypassed by a tantalum capacitor or 10-/xF
alum inum electrolytic capacitor.
T he L M 317H V K protects itself against overheating, too m uch internal pow er d is
sipation, and too m uch current. W hen the chip tem perature reaches 175°C, the 317 shuts
down. If the product o f output current and input-to-output voltage exceeds 15 to 20 W, or
if currents greater than about 1.5 A are required, the LM 317 also shuts down. W hen the
overload condition is rem oved, the LM 317 sim ply resum es operation. All o f these pro
tection features are m ade possible by the rem arkable internal circuitry o f the LM 317.
16-12.3 Adjustable Negative-Voltage Regulator
A n ad ju sta b le th ree -term in a l n e g a tiv e -vo lta g e reg u la to r is also av ailab le [see the
L M 337H V K in Fig. 16-13(c)], T he negative regulator operates on the sam e principle as
the positive regulator except that R } is a 12 0 -fl resistor and the m axim um input voltage
is reduced to 50 V.
V0 is given by Eq. (16-9b). If R\ = 120 f l, then V0 depends upon R 2 according to
V0 = 1.25 V + (10 m A )R2 (16-10)
16-12.4 External Protection *
It is standard practice to connect C\ and C2 to a regulator (see Fig. 16-14) for reasons
stated in Section 16-12.2. Any regulator should have diode D] to protect it against input
shorts; otherw ise, load capacitance can pum p current back into its output and destroy it.
C apacitor C3 is added to greatly im prove ac ripple voltage rejection. However, if a
short circuit occurs across the regulator’s output, C3 w ill try to pum p current back into
the adjust term inal. D iode D 2 steers this current instead into the short circuit.
478
Power Supplies 479
1 A each if the regulators are heat-sinked properly (see Section 16-9.1). Variable resistor
R2 for each regulator may be adjusted for a regulated output voltage betw een approxi
m ately 1.2 and 20 V.
T he unregulated supply has the circuitry o f Fig. 16-8. A conservative design w ould
select (1) a transform er, 115 V /50 V C T at 2 A, (2) diodes 7av > 1 A at PIV > 50 V (IN
4002), and (3) capacitors of 1000 (jlF at W V D C > 50 V.
16-14 OTHER LINEAR REGULATORS ______________________________________________________
W ith the large increase o f battery-pow ered equipm ent and system s that operate from 3 V
or 3.3 V instead o f 5 V or other dc voltage levels, m anufacturers such as M axim and
L inear Technology have responded with a variety o f linear voltage regulators. Som e sys
tem s use both the low voltage (3 V or 3.3 V) and a higher dc voltage. R egulators know n
as step-dow n d c-d c controllers are used in these applications. The output voltage o f these
chips is 3 V or 3.3 V, and a typical input voltage range from 3.6 V to 16 V. O ther d c -d c
controller chips have an adjustable output voltage. As w ith all voltage regulators these d e
vices have short-circuit protection, therm al shutdow n, and rail-to-rail and single-supply
operation. The preceding sections have been written using som e low -cost readily avail
able regulators that you can use to pow er up general-purpose op am ps, but look for these
other regulators in low -pow er portable equipm ent.
PROBLEMS _____________________________________________________________________
16-1. A tra n s fo rm e r is rated at 115 to 28 V rm s at 1 A . W h a t is the peak secondary voltage?
16-2. A 115/28 V tra n s fo rm e r is used in F ig . 16-4(a). F in d Vdc at no load.
16-3. A s dc load cu rre n t increases, w h a t happens to (a) dc load vo lta g e ; (b ) ac rip p le voltage?
16-4. In F ig . 16-4, the tra n s fo rm e r ra tin g is 115 to 28 V at 1 A . W h a t is Vdc at a fu ll-lo a d cu rre n t
o f / L = 0.5 A ?
16-5. D c m easurem ents o f a p o w e r su p p ly give Vdc NL = 17.8 V and Vdc FL = 13.8 V at 1L f l =
0.5 A . C a lcu la te : (a) R0\ (b) p ercent re g u la tio n .
16-6. W h a t vo lta g e readings w o u ld be obtained w ith an ac v o ltm e te r fo r p e a k-to -p e a k rip p le v o lt
ages o f (a) 1 V ; (b) 3 V ?
16-7. T h e dc fu ll-lo a d vo lta g e o f a p o w e r s u p p ly is 28 V and the p e a k-to -p e a k rip p le vo lta g e is
6 V. F in d the m in im u m instantaneous load voltage.
16-8. A 1 1 0 V /2 8 V C T tra n s fo rm e r is in s ta lle d in F ig . 16-8. W h a t n o -lo a d dc v o lta g e w o u ld be
m easured (a) betw een te rm in a ls 1 and 2; (b) fro m 1 to C T ; (c) fro m 2 to C T ?
16-9. F in d the percent rip p le in E xa m p le 16-7 i f C is changed to 2 0 0 0 ;xF.
16-10. D e sig n an F W B u n regulated p o w e r s u p p ly to o u tp u t + 1 5 V at 1 A , w ith less than 5 % r ip
ple. A ssu m e that R0 = 8 Cl. C hoose the tra n s fo rm e r fro m a v a ila b le ra tin g s o f 115/12 V,
115/18 V, and 115/24 V — a ll at 2 A . A va ila b le capacitors are 500 /xF and 1000 /uF at W V D C
= 50 V.
16-11. G iv e n 11 5 /2 5 .2 V at a 3 -A tra n s fo rm e r and C = 1000 /xF in an F W B re c tifie r. A ssu m e
R0 = 6 O and 1L FL = 1 A . C a lcu la te (a) Vdc NL; (b) Vdc fl; (c) percent re g u la tio n ; (d) A
(e) ripple; (f) V L min.
C = 1000 /xF. C a lcu la te A V n i f y o u (a) d o u b le C to 20 0 0 /j l F , o r (b) reduce I to 0.5 A , o r
16-13. A n ac v o ltm e te r indicates a value o f 1.71 V rm s across the F W B su p p ly, and a dc v o ltm e te r
in d ic a te s 12 V dc. D ra w the expected va lu e o f V L th a t w o u ld be seen on a d c -c o u p le d
16-14. I f l L m easures 1 A in P ro b le m 16-13, fin d (a) the value o f C; (b) the value o f R L.
16-15* Y ou need a regulated o u tp u t vo lta g e o f 24.0 V. I f R \ = 240 f l in F ig . 1 6 -13(a), fin d the
16-16. A ssu m e th a t the re g u la to r o f P ro b le m 16-15 d e live rs a load c u rre n t o f 1.0 A . I f its average
16-18. A d ju s ta b le re sistor R 2 = 0 to 2 5 0 0 O in F ig . 1 6 -13(a). F in d the upper and lo w e r lim its o f
16-19. Suppose that a 1 2 0 0 -fl lo w -s to p resistor, and a 2 5 0 0 - fl p o t are connected in series in place
o f the s in g le re sistor R 2 in F ig . 1 6 -13(a). F in d the u p p e r and lo w e r lim its o f VQ as the pot
16-20. I f the d ro p o u t vo lta g e o f an L M 3 1 7 is 3 V, w h a t is the m in im u m in stantaneous in p u t v o lt-
16-21. C a lcu la te the re q u ire d values fo r R 2 in F ig . 16-15 to g ive outputs o f ± 1 2 V.

APPENDIX 1
Frequency-
1 1 X 7 4 1
Compensated
Operational Amplifier*
*Courtesy o f Fairchild Semiconductor, a Division o f Fairchild Camera and Instrument Corporation

Description Connection Diagram
The *iA741 is a high performance Monolithic 8-Pin Metal Package
Operational Amplifier constructed using the Fairchild
Planar epitaxial p ro cess. It is intended for a wide
range of analog applications. High common mode
voltage range and ab sence of latch-up tendencies
make the mA 741 ideal for use as a voltage follower.
The high gain and wide range of operating voltage
provides superior performance in integrator, summing
amplifier, and general feedback applications
■ NO FREQ U EN C Y COMPENSATION REQUIRED

■ SHORT-CIRCUIT PROTECTION
■ O F F S E T VO LTA GE NULL CAPABILITY
■ LARG E COMMON MODE AND D IFFEREN TIA L
VO LTA GE RANGES (Top V i«w )
■ LOW POW ER CONSUMPTION
■ NO LATCH-UP P in 4 c o n n e c t e d to c a s e
Order Information
Connection Diagram Type Package Code Part No.
10-Pin Flatpak MA741 Metal 5W MA741HM
1
/iA7 4 1A Metal 5W MA741AHM
10
NC 1
[ •
MA741C Metal 5W mA741HC
-O FFSET - 2 9 M A741E Metal 5W mA 741EH C
1
N U LL L
_
-IN [C
-IN IC
3
4 w x > -L
8
t -
7
1 Connection Diagram
8-Pin DIP
5 6
O FFSET
v-C
1 ' 1
N U LL
(Top Vi«w )
Order Information
Type P ackage Code Part No.
*iA741 Flatpak 3F ^ A74tFM —| ‘ O FFSET
/iA7 4 1 A Flatpak 3F /iA 7 4 1AFM -J N U LL
(Top V i«w )
Order Information
Type Package Code Part No.
MA741C Molded DIP 9T MA741TC
MA741C Ceram ic DIP 6T Â741RC
Absolute Maximum Ratings Operating Temperature Range
Supply Voltage Military (MA741A, mA 741) - 5 5 ° C to + 1 2 5 °C
Â74 1A, mA741, Â741E ± 22 V Commercial (/iA741E, Â741C) 0 ° C to + 7 0 °C
MA741C ± 18 V Pin Temperature (Soldering 60 s)
Internal Power Dissipation Metal P a ckag e, Flatpak, and
(Note 1) Ceram ic DIP 3 0 0 °C
Metal Packag e 500 MW Molded DIP (10 s) 2 6 0 °C
DIP 310 mW Output Short Circuit Duration
Flatpak 570 mW (Note 3) Indefinite
Differential Input Voltage ± 30 V
Input Voltage (Note 2) ± 15 V
Storage Temperature Range
Metal Pa ckag e and Flatpak -6 5 °C to + 15 0 °C
DIP -5 5 °C to + 1 2 5 ° C
484 A ppendix 1
mA741 and MA 741C

Electrical C h aracteristics Vs = ± 15 V, T a = 2 5 °C unless otherwise specified
MA741 Â741C
Characteristic Condition Min Typ Max Min Typ Max Unit
Input Offset Voltage R s < 10 kQ 1.0 5.0 2.0 6.0 mV
Input Offset Current 20 200 20 200 nA
Input B ias Current 80 500 80 500 nA
V s = +10, - 2 0
Power Supply Rejection Ratio 30 150 30 150 /iV/V
V S = +20, - 1 0 V. R S = 50 0
Input R esistan ce .3 2.0 .3 2.0 MA
Input C apacitance t.4 1.4 PF
O ffset Voltage
± 15 ± 15 mV
Adjustment Range
Input Voltage Range ± 12 ± 13 V
Common Mode
R s < 10 kQ 70 90 dB
Rejection Ratio
Output Short Circuit Current 25 25 mA
Large Signal Voltage Gain R L > 2 kfl, VouT = ± 10 V 50k 200k 20k 200k
Output R e sistan ce 75 75 Q
R l > 10 kft ± 12 ± 14 V
Output Voltage Swing
R l >: 2 kfi ± 10 ± 13 V
Supply Current 1.7 2.8 1.7 2.8 mA
Power Consumption 50 85 50 85 mW
Transient R ise TimeV|N = 20 mV, R l = 2 kfi, .3 .3 ms
R esponse
(Unity Gain) Overshoot C|_ < 100 pF 5.0 5.0 %
Bandwidth (Note 4) 1.0 1.0 MHz
Slew Rate R l > 2 kQ .5 .5 V/^s
0 35
4 C a l c u l a t e d v alu e from B W ( M H z ) = RisG T i m e
5. All V c c = 15 V for ^ A 7 4 I a n d MA 7 4 1C.

6. M a x i m u m s u p p l y c u r r e n t f o r all d e v i c e s
jxA741 Frequency-Compensated Operational Amplifier 485
*iA741 and mA741C

Electrical C h aracteristics (Cont.) The following sp ecifications apply over the range of - 5 5 ° C < T a < 125°C
____________________________________________for mA 741, 0 qC < T A < 7 0 °C for MA741C
mA741 */A741C
Ch aracteristic Condition Min Typ Max Min Typ Max Unit
7.5 mV
Input O ffset Voltage
R s < 10 kQ 1.0 6.0 mV
300 nA
Input Offset Current T a = + 12 5 °C 7.0 200 nA
T a = —55 ° C 85 500 nA
800 nA
Input B ia s Current T a = + 125°C .03 .5 Â
T a = —55° C .3 1.5 mA
Input Voltage Range ± 12 ± 13 V
Common Mode
R S < 10 kQ 70 90 dB
Rejection Ratio
Adjustment for Input Offset
± 15 ± 15 mV
Voltage
Supply Voltage V S = + 10, - 2 0 ; 30 150 MV/V
Rejection Ratio VS = +20, - 1 0 V, R S = 50 Q
R l > 10 kQ ± 12 ± 14 V
Output Voltage Swing
R L > 2 kfi ± 10 ± 13 ± 10 ± 13 V
Large Signal Voltage Gain R l = 2 kQ, VouT = ± 10 V 25k 15k
T a = + 12 5 °C 1.5 2.5 mA
Supply Current
Ta = —5 5 °C 2.0 3.3 mA
T a = + 1 2 5 °C 45 75 mW
Power Consumption
T a = —5 5 °C 60 100 mW
N o ta s 035
4 C a l c u l a t e d v a l u e f r om B W ( M H z ) = Rj se T i m e ( ^ s )
5. All V q c = 15 V for ^ A 7 4 \ a n d ^ A 7 4 1C.

6. M a x im u m s u p p l y c u r r e n t for all d e v i c e s
486 Appendix 1
mA741A and mA741E

Electrical C h aracteristics V s = ± 15 V, T a = 2 5 °C unless otherwise specified
mA 7 4 1 A /E
C haracteristic Condition Min Typ Max Unit

Input Offset Voltage R s < 50 n 0.8 3.0 mV
Average Input Offset Voltage Drift 15 mV / ° C
Input Offset Current 3.0 30 nA
Average Input Offset Current Drift 0.5 n A /°C
Input B ia s Current 30 80 nA
V s = + 10 , - 20 ; V S = +20 V, - 10 V.
Power Supply Rejection Ratio 15 50 m v /v
R s - 50 ft
Output Short Circuit Current 10 25 40 mA
Power Consumption VS = ± 2 0 V 00 150 mW
Input Impedance VS = ± 2 0 V 1.0 6.0 M0
V S = ± 2 0 V, R l = 2 k (I,
Large Signal Voltage Gain 50 200 V/ mV
V q u t = ± 15 v
Transient R esp onse R ise Time 0.25 0.8 ms
(Unity Gain) Overshoot 6.0 20 %
Bandwidth (Note 4) .437 1.5 MHz
Slew R ate (Unity Gain) V[n — ± 10 V 0.3 0.7 | V /us
The following sp ecifications apply over the range of - 5 5 ° C < T a < 125°C for the 741 A,
and 0 ° C < TA < 70 ° C for the 741E.
Input O ffset Voltage 4.0 mV
Input Offset Current 70 nA
Input B ia s Current 210 nA
Common Mode Rejection Ratio V S = ± 2 0 V, V|N - ± 1 5 V, R S = 50 Q 80 95 dB
Adjustment For Input Offset Voltage Vs = ± 20 V 10 mV
Output Short Circuit Current 10 40 mA
-5 5 °C 165 mW
MA741A
Power Consumption VS = ± 20 V + 1 2 5 °C 135 mW
>iA74lE 150 mW
Input Impedance VS = ±20 V 0.5 M12
Rl = 10 kil ± 16 V
Output Voltage Swing VS = ±20 V
Rl = 2 kQ ± 15 V
> >
> >
V S — ± 2 0 V, R L - 2 kil, 32
E E
VQUT = ± 15 V
Large Signal Voltage Gain
V S — ± 5 V, R l - 2 kfl, 10 V/ mV
Vqut = ±2 V
Notes
0.35
4. C a l c u l a t e d v a l u e f r om : B W ( M H z ) = p j se T i m e ( ^ s )
5. Al l V c c = 15 V for > < A 7 4i a n d MA 7 4 1 C .

6. M a x i m u m s u p p l y c u r r e n t for all d e v i c e s
2 5 ° C = 2.8 m A
1 25°C » 2.5 m A
- 5 5 aC - 3 . 3 mA
Typical Perform ance C u rv et for mA741A and jxA741
Output Short-Circuit
Input Bias Currant as a Input Resistance as a Current as a
Function of Function of Function of
Ambient Temperature Ambient Temperature Ambient Temperature
M JO 20 40 100 140
TEM PERATURE - “ C TEU P EH A T U R t - "C
Typical Perform ance Curves for *iA741A and *zA741 (C ont.)
Input Offset Current a s a Power Consumption as a Frequency C h aracteristics as a

Ambient Tem perature Ambient Temperature Ambient Temperature
TEMPERATURE - “C TEM PERATURE — C
Typical Perform ance Curves for mA741E and mA741C
Input Bias Current as a Input R esistan ce as a Input Offset Current as a

j; 3 °
a 2.0
0 10 20 JO 40 SO M ;o 0 10 ?0 30 40 SO 40 *0
TEM PERATURE - C TEM PERATU RE - C
Power Consumption as a Output Short Circuit Current as a Frequency C h aracteristics as a

0 10 20 30 40 10 60 70
tem pera tu re - c fKjH£ - C
General Description
The LM 101A series are general purpose operational capacitor. It has advantages over internally com
amplifiers which feature improved performance pensated amplifiers in that the frequency compen
over industry standards like the LM 709. Advanced sation can be tailored to the particular application.
processing techniques make possible an order of For example, in low frequency circuits it can be
magnitude reduction in input currents, and a overcompensated for increased stability margin. Or
redesign of the biasing circuitry reduces the the compensation can be optimized to give more
temperature drift of input current. Improved than a factor of ten improvement in high frequen
specifications include: cy performance for most applications.
■ Offset voltage 3 mV maximum over tempera
ture ( LM 101A/LM 201 A)
■ Input current 100 nA maximum over tempera In addition, the device provides better accuracy
ture (LM 101A/LM 201 A) and lower noise in high impedance circuitry.
■ Offset current 20 nA maximum over tempera The low input currents also make it particu
ture (LM 101A/LM 201 A) larly well suited for long interval integrators
or timers, sample and hold circuits and low fre
■ Guaranteed drift characteristics
quency waveform generators. Further, replacing
■ Offsets guaranteed over entire common mode circuits where matched transistor pairs buffer
and supply voltage ranges the inputs of conventional IC op amps, it can
give lower offset voltage and drift at a lower cost.
■ Slew rate of 10V/ps as a summing amplifier
This amplifier offers many features which make its

application nearly foolproof: overload protection The LM 101A is guaranteed over a temperature
on the input and output, no latch-up when the range of - 5 5 ° C to +125°C, the LM 201A from
common mode range is exceeded, freedom from - 2 5 ° C to +85°C, and the LM 301A from 0°C
oscillations and compensation with a single 30 pF to 70°C.
Schematic ** and Connection Diagrams (Top Views)
D u a l - l n - L m e Package
O rder Number L M 1 0 1 A H ,
L M 2 0 1 A H or L M 3 0 1 A H
See N S Package H 08 C I 0UTM
JT
-I UlUCI
D u a l I n - L i n e P acka ge
Not* Pin 6 canncctt* to bonam of fMckip
O rder Numb«r L M 1 0 1 A J-1 4

LM 2 0 1 A J-1 4 or L M 3 0 1 A J-1 4
See NS P a c ka g e J 1 4 A
O rder Number
L M 1 0 1 A J , L M 2 0 1 A J, L M 3 0 1 A J
See N S Package J 0 8 A
Order Num ber L M 3 0 1 A N

See N S Package N 0 8 A
•Pin c o n n e c t i o n s s h o w n are f o r m e ta l can.

LM301 Operational A m plifier 493
Absolute Maximum Ratings

LM101A/LM201A LM301A
S up p ly Voltage ±22V ± 1B V
Power Dissipation ( N o : e 1) 500 mW 500 m W
Differential I np ut Voltage ±30V ±30V
Input Voltage ( No t e 2) ± 1 5V ±15V
O u t p u t S hor t C ir cui t Du rati on ( Note 3) I ndefinite Indefinite
Operati ng T em pe ra tu re Range - 5 5 ° C to +125 °C ( L M 1 0 1 A )
- 2 5 ° C to + 85° C ( L M 2 0 1 A )
Storage T em pe ra tu re Range - 6 5 ° C to + 150 °C - 6 5 C to + 150 C
Lead T em pe ra tu re (Soldering, 10 seconds) 300° C 300° C
Electrical Characteristics (Note 4)
LM 101A /LM 201A LM 301A

PA RA M ETER C O N D IT IO N S U N ITS
MIN TYP MAX MIN TYP M AX
Input Offset Voltage TA = 25°C

L M t O I A . LM 20 1A . L M3 0 1A RS < 5 0 k n 0.7 2.0 2.0 75 mV
Input Offset Current T a = 25°c 1.5 10 3.0 50 nA
Input Bias Current T A = 25°C 30 75 70 250 nA
Input Resistance T A - 2S°C 1.5 4.0 0.5 2.0
Supply Current T A = 25° C

V S ^ f- 20V 1.8 3.0 mA
V S = * 15V 1.8 3.0 mA
Large Signal Voltage Gain T A 3 25°C, V s = 115V 50 160 25 160 V/mV

V q u T = *10V. R L > 2 k f 2
Input Offset Voltage RS < 5 0 k f t 3.0 10 mV

RS < 1 0 k n mV
Average Temperature Coeffi RS < 5 0 k f 2 3.0 15 6.0 30 pV/°C

cient of Input Offset Voltage R S < 10 ktt j/V/°C
Input Offset Current 20 70 nA
Ta =■tMax nA
T a = t min nA
Average Temperature Coeffi 25°C < T A < T M A X 0 01 0 1 0.01 0.3 nA/° C

cient of Input Offset Current T m i n < T a <25°C 0 02 0.2 0.02 0.6 nA/4 C
Input Bias Current 0.1 0.3 f iA
Supply Current T a a Tm a x . V S - t2 0 v 1.2 2.5 mA
Large Signal Voltage Gam V S = M 5 V , V 0 U T = ilOV . 25 15 V/ mV

R L > 2k
Output Voltage Swing V S = i15V

R L = 10 kfi ±12 ±14 ±12 ±14 V
R l = 2 kS7 ♦10 - 13 ±10 ±13 V
Inpul Voltage Range V s = ±20V ±15 V

V s - - 15V *15. - 1 3 ±12 ♦15, 13 V
Common Mode Rejection Ratio RS < 50 kfi 80 96 70 90 dB

R S < 1 0k ft dB
Supply Voltage Rejection Ratio RS S 50 k H 80 96 70 96 dB

RS < 10 k n iB
Not# 1: T h e m a x i m u m j u n c t i o n t e m p e r a t u r e of th e L M 1 0 1 A is 1 5 0 ° C , a nd that o f the L M 2 0 1 A / L M 3 0 1 A is 1 0 0 ° C . F o r o p e r a t i n g at elevated

t e mp e r a t u r e s , d evi ces in the T O - 5 p a cka ge m u s t be d e r a t e d based on a t h e r m a l resistance of 1 5 0 ° C / W , j u n c t i o n t o a m b i e n t , or 4 5 ° C / W , j u n c t i o n to
case. T h e t h e r m a l resi stance of the d u a l - i n - l i n e p a cka ge is 1 8 7 ° C A V . j u n c t i o n t o a m b i e n t .
Note 2- F o r s u p p l y v ol tages less t h a n 1 1 5 V , the a bso lu te m a x i m u m i n p u t v ol t ag e is equa l t o the s u p p l y v ol t age .

Note 3 : C o n t i n u o u s s h or t c i rc u i t is a l l o w e d f o r case t e m p e r a t u r e s t o 1 2 5 ° C a nd a m b i e n t t e m p e r a t u r e s to 7 5 ° C f or L M 1 0 1 A / L M 2 0 1 A , a n d 7 0 ° C
an d 5 5 ° C r es pect i ve ly For L M 3 0 1 A .
Note 4: Unl ess o t h e r w i s e spe ci fi ed , these s pe ci fi ca ti on s a p p l y f o r C l = 30 p F , t 5 V < Vs < ± 2 0 V and - 5 5 ° C < T A < +125°C(L M 1 0 1 A ),
+ 5 V < V S < ± 20 V a n d - 2 5 ° C < T A < + 8 5 ° C ( L M 2 0 1 A ) , ± 5 V < V s < i 1 5 V a n d 0 ° C < T A < + 7 0 ° C ( L M 3 0 1 A ) . “ “
Input NoJa* Currant Co m m on M oo* R *i«ctio n Powot S u p p ly R t j« d io n
| »r“
r,- i *n
S
V c»i
f ju e n c y FREQUENCY (Hi)
FREQUENCY (Hi]
CloM d Lo o p O utpu t Im p td anM
FREQUENCY (Hi)
APPENDIX 3
LM311 Voltage
Comparator*
^Courtesy of National Sem iconductor Corporation,
498
500 Appendix 3

Total Supply Voltage (V 8 4 )
Output to Negative Supply Voltage (V 74 }
Ground to Negative Supply Voltage (V [ 4 )
Differential Input Voltage
Input Voltage (Note 1)
Power Dissipation (Note 2)
Output Short Circuit Duration
Operating Temperature Range
Storage Temperature Range
Lead Temperature (soldering, 10 sec)
Voltage at Strobe Pin

PARAM ETER CO N DITIO N S MIN TYP M AX U N ITS
Input Offset Voltage (Note 4} T a = 25°C, R s < 50k 2.0 7.5 mV
Input Offset Current (Note 4) TA = 25°C 6.0 50 nA
Input Bias Current T a = 25°C 100 250 nA

Voltage Gain T a = 25°C 40 200 V/mV
Response Time (Note 5) T a = 25°C 200 ns

Saturation Voltage V ,N < —10 mV, lOUT = 50 mA 0.75 1.5 V
T a = 25°C
Strobe ON Current Ta = 25°C 3.0 mA
Output Leakage Current V|n > 10 mV, V OUT = 35V 0.2 50 nA

TA = 25 C, 1s t r o b e = 3 m A
Input Offset Voltage (Note 4) Rs < 50k 10 mV
Input Offset Current (Note 4) 70 nA

Input Bias Current 300 nA
1nput Voltage Range -14.5 13.8,-14.7 13.0 V
Saturation Voltage V + > 4.5V , V - = 0 0.23 0.4 V
V ifg ^ —10 mV, I s i n k * ^ 8 m A
Positive Supply Current T a = 25° C 5.1 7.5 mA
Negative Supply Current T a = 25°C 4.1 5.0 mA
N ote 1: T his rating applies for ±15V supplies. The positive input voltage lim it is 3 0 V above the negative sup p ly. T h e negative
input voltage lim it is equal to the negative supply voltage or 3 0 V below the positive sup ply, w hich ever is less.
N ote 2: T he m axim um ju nction tem perature of the L M 3 1 1 is 1 10°C. F o r operating at elevated tem peratures, d evicet in the T O -6
package m ust be derated based on a therm al resistance of 150*C/W , ju nction to am bient, or 4 5*C/W , ju n ctio n to caee. T h e therm al
resistance of the dual-in-line package is 100°C/W , ju nction to am bient.
Note 3 : These specifications apply for V § c ± 15V and the G round pin at ground, and 0 ° C < T ^ < + 7 0 °C , un lew otherw ise
specified. The offset voltage, offset curren t and bias current specifications apply for any supply voltage from a single 6 V supply
up to i l 5 V supplies.
Note 4 : T h e offset voltages and offset currents given are the m axim um values required to drive the ou tput w ith in a volt of either
supply w ith 1 m A load. Thus, these param eters define an error band and take into accoun t the w ortt-cate effects of voltage gtkn
and input im pedance.
Note 5 : T h e response tim e specified (see definitions) is for a 100 m V input step w ith 5 m V overdrive.
Note 6 : Do not short the strobe pin to ground; it should be curren t driven at 3 to 5 m A .
LM311 Voltage Comparator
Typical Performance Characteristics

Input B its Cu rran t Input O ffset Current Offset Error
(bA )
\
----- RAISED'
BIAS CURRENT
iSHORT PINS
S. 8. AND t)
INPUT
INPUT RESISTANCE (f2J
input Characteristics Common Mode Limits Tran sfe r F u n c ti o n
NORMAL OUTPUT
REFERRED TO SUPPLY VOLTAGES
faA)
INPUT HAS CURRENT
EM ITTE R —
FOLLOW ER
OUTPUT
r l ■w o n -
D IF F E R E N T IA L IN PU T V O L T A G E (V) D IFFER EN TIA L INPUT VOLTAGE (mV)
Response Time for Various Response Tim e for V arious

Input Overdrives input Overdrives O u t p u t S aturatio n Voltage
(V)
VOLTAGE
O U m jT
( b V)
VOLTAGE
INPUT
OUTPUT CURRENT (mA)

(V)
VOLTAGE
OUTPUT
(» V I
INPUT VOLTAGE
Application Hints
C IR C U IT TECH N IQ U ES FOR AVO ID IN G
O SC ILLA TIO N S IN COM PARATOR APPLICATION S
When a high-speed comparator such as the LM 111 is 4. When comparator circuits use input resistors (eg.
used with fast input signals and low source impedances, summing resistors), their value and placement are
the output response will normally be fast and stable, particularly important. In all cases the body of the
assuming that the power supplies have been bypassed resistor should be close to the device or socket. In
(with 0.1 fuF disc capacitors), and that the output signal other words there should be very little lead length or
is routed well away from the inputs (pins 2 and 3) and printed-circuit foil run between comparator and
also away from pins 5 and 6. resistor to radiate or pick up signals. The same applies
to capacitors, pots, etc. For example, if Rs = 10 k U , as
However, when the input signal is a voltage ramp or a little as 5 inches of lead between the resistors and the
slow sine wave, or if the signal source impedance is high input pins can result in oscillations that are very hard
(1 k£2 to 100 k H ), the comparator may burst into to damp. Twisting these input leads tightly is the
oscillation near the crossing-point. This is due to the only (second best) alternative to placing resistors
high gain and wide bandwidth of comparators like the close to the comparator.
LM 111. To avoid oscillation or instability in such a
usage, several precautions are recommended, as shown 5. Since feedback to almost any pin of a comparator
in Figure 1 below. can result in oscillation, the printed-circuit layout
should be engineered thoughtfully. Preferably there
1. The trim pins (pins 5 and 6) act as unwanted au xil should be a groundplane under the LM 111 circuitry,
iary inputs. If these pins are not connected to a trim- for example, one side of a double-layer circuit card.
pot, they should be shorted together. If they are Ground foil (or. positive supply or negative supply
connected to a trim-pot, a 0.01 (J.A capacitor C l foil) should extend between the output and the
between pins 5 and 6 will minimize the susceptibility inputs, to act as a guard. The foil connections for the
to A C coupling. A smaller capacitor is used if pin 5 is inputs should be as small and compact as possible,
used for positive feedback as in Figure 1. and should be essentially surrounded by ground foil
on all sides, to guard against capacitive coupling from
2. Certain sources will produce a cleaner comparator any high-level signals (such as the output). If pins 5
output waveform if a 100 pF to 1000 pF capacitor and 6 are not used, they should be shorted together.
C2 is connected directly across the input pins. If they are connected to a trim-pot, the trim-pot
should be located, at most, a few inches away from the
3. When the signal source is applied through a resistive LM 111, and the 0.01 /j F capacitor should be installed.
network, R s, it is usually advantageous to choose an If this capacitor cannot be used, a shielding printed-
R s' of substantially the same value, both for DC and circuit foil may be advisable between pins 6 and 7.
for dynamic (AC) considerations. Carbon, tin-oxide, The power supply bypass capacitors should be located
and metal-film resistors have all been used successfully within a couple inches of the LM 111. (Some other
in comparator input circuitry. Inductive wirewound comparators require the power-supply bypass to be
resistors are not suitable. located immediately adjacent to the comparator.)
o 15V
INPUTo-AAV—f-
O OUTPUT
Pin c o n n e c t i o n s s h o w n are fo r L M 1 1 1 H in 8 - le ad T O - 5 h e r m e t i c p ac ka g e
F IG U R E 1. Improved Positive Feedback
503
Application Hints (Continued)
6. It is a standard procedure to use hysteresis (positive ideal. The positive feedback is to pin 5 (one of the
feedback) around a comparator, to prevent oscillation, offset adjustment pins). It is sufficient to cause 1 to
and to avoid excessive noise on the output because 2 mV hysteresis and sharp transitions with inpot
the comparator is a good amplifier for its own noise. triangle waves from a few Hz to hundreds of kHz.
In the circuit of Figure 2, the feedback from the The positive-feedback signal across the 8 2 0 resistor
output to the positive input will cause about 3 mV of swings 240 mV below the positive supply. This signal
hysteresis. However, if R s is larger than 1 0 0 0 , such is centered around the nominal voltage at pin 5, so
as 50 kQ , it would not be reasonable to simply this feedback does not add to the V os of the com
increase the value of the positive feedback resistor parator. As much as 8 mV of V os can be trimmed
above 510 kf2. The circuit of Figure 3 could be used, out, using the 5 kH pot and 3 k f i resistor as shown.
but it is rather awkward. See the notes in paragraph
7 below.
8. These application notes apply specifically to the
7. When both inputs of the LM111 are connected to LM 111, LM 211, LM 311, and LF111 families of
active signals, or if a high-impedance signal is driving comparators, and are applicable to all high-speed
the positive input of the LM 1 11 so that positive feed comparators in general, (with the exception that not
back would be disruptive, the circuit of Figure 7 is all comparators have trim pins).
Pin c o n n e c t i o n s s h o w n are f or L M 111 H in 8 - l e ad T O - 5 h e r m e t i c p acka ge
F IG U R E 2. Conventional Positive Feedback

APPENDIX 4
LM117 3-Terminal
Adjustable Regulator*
*Courtesy of National Sem iconductor Corporation.

General Description
The LM 1 1 7/LM 217/LM31 7 are adjustable 3-terminal Besides replacing fixed regulators, the LM 117 is useful
positive voltage regulators capable of supplying in excess in a wide variety of other applications. Since the regu
of 1.5A over a 1.2V to 37V output range. They are lator is "floating” and sees only the input-to-output
exceptionally easy to use and require only two external differential voltage, supplies of several hundred volts
resistors to set the output voltage. Further, both line can be regulated as long as the maximum input to
and load regulation are better than standard fixed regula output differential is not exceeoed.
tors. Also, the LM117 is packaged in standard transistor
Also, it makes an especially simple adjustable switching
packages which are easily mounted and handled.
regulator, a programmable output regulator, or by
connecting a fixed resistor between the adjustment and
In addition to higher performance than fixed regulators,
output, the LM117 can be used as a precision current
the LM 117 series offers full overload protection
regulator. Supplies with electronic shutdown can be
available only in IC's. Included on the chip are current
achieved by clamping the adjustment terminal to ground
lim it, thermal overload protection and safe area protec
which programs the output to 1.2V where most loads
tion. All overload protection circuitry remains fully
draw little current.
functional even if the adjustment terminal is
disconnected. The LM 117K , LM 217K and LM 317K are packaged in
standard TO-3 transistor packages while the LM 117H,
Features LM 217H and LM317H are packaged in a solid Kovar
base TO-39 transistor package. The LM117 is rated for
■ Adjustable output down to 1.2V operation from -5 5 °C to +150°C, the LM 217 from
■ Guaranteed 1,5A output current -2 5 °C to +150°C and the LM317 from 0°C to +125°C.
■ Line regulation typically 0.01%/V The LM 317T and LM317MP, rated for operation over a
■ Load regulation typically 0.1 % 0°C to + 125°C range, are available in a T0-220 plastic
package and a T0-202 package, respectively
■ Current lim it constant with temperature
■ 100% electrical burn-in For applications requiring greater output current in
■ Eliminates the need to stock many voltages excess of 3A and 5A, see LM 150 series and LM 138
series data sheets, respectively, For the negative comple
■ Standard 3-lead transistor package
ment, see LM137 series data sheet.
■ 80 dB ripple rejection
LM117 Series Packages and Power Capability
Normally, no capacitors are needed unless the device is RATED D ESIG N
situated far from the input filter capacitors in which D EVICE PACKAGE POWER LOAD
case an input bypass is needed. An optional output D ISSIP ATIO N CURRENT
capacitor can be added to improve transient response. LM 117 TO -3 20W 1 5A

The adjustment terminal can be bypassed to achieve LM 217
0 .5A
TO -3 9 2W
very high ripple rejections ratios which are difficult LM317
LM317T T0220 15W 1 ,5A
to achieve with standard 3-terminal regulators.
L M 3 1 7M T 0-202 7 5W 0 5A
LM317LZ TO -9 2 0.6W 0.1 A
Typical Applications
1.2V—25V Adjustable Regulator Digitally Selected Output* 5V Logic Regulator with
Electronic Shutdown*
and rejection of transients.

•Needed if device is fer from
capacitors. ,
nVOUT " 125V S en m a xim u m V r * M in o u t p u t * 1.2 V
Power Dissipation Internally limited
Input-O utput Voltage Differential 40V
Operating Junction Temperature Range
LM117 -55°C to +150°C
LM217 -2 5 °C to+ 150°C
LM317 0°C to +125°C
Storage Temperature -6 5 °C to +1 50°C
Lead Temperature (Soldering, 10 seconds) 300°C
Preconditioning
Burn-In in Thermal Lim it 100% All Devices

LM 117/217 LM 317
PAR A M ETER C O N D IT IO N S UNITS
M IN TYP MAX M IN TYP MAX
Line R e gu lation T A =25°C, 3 V < V ] N - V O U T< 4 0 V 0 . 01 0.02 0.01 0.04 %/V
( N o t e 2)
Lo a d R e gu lation T A = 2 5 ° C , 10 m A < Iq u T < ' M A X
V o u T < 5 V . (N o te 2) 5 15 5 25 mV
V q u T > 5 V , ( N o t e 2) 0.1 0.3 0 1 0.5 %
T h e r m a l R e gu lation T A = 2 5 ° C , 2 0 m s Pulse 0.03 0.07 0.04 0.07 % /W
A d j u s t m e n t Pin C u r re n t 50 100 50 100 #i A
A d j u s t m e n t P in C u r r e n t C h a n g e 10 m A < lL < lM A X 0.2 5 0.2 5 PA
3V < (V |rs j-V 0 U T ) < 4 0 V
Referen ce V olt age 3 V < ( V i^ - V q u T ) < Ô V , ( N o t e 3) 1.20 1.25 1.30 1.20 1.25 1.30 V
10 m A < l 0 U T < ‘M A X . p < P M A X
Line Re gu la tio n . 3V < V in - V 0 U T < 4 0 V . ( N o t e 2) 0.02 0.05 0.02 0.07 %/V
Lo a d R egu lation 10 m A < Iq u T < ' M A X - ( N o t e 2)

V Q U T < 5 V 20 50 20 70 mV
V0 U T > 5 V 0.3 1 0.3 1. 5 %
T e m p e r a t u r e S ta b ili ty t m in < Ti < t m a x 1 1 %
M in im u m Load Current V | | S J -V 0 U T = 4 0 V 3.5 5 3.5 10 mA
Current Lim it V|N "V 0 U T < 15V

K a n d T P a c k ag e 1. 5 2.2 1. 5 2.2 A
H a n d P P a cka ge 0.5 0.8 0. 5 0.8 A
V [ N — V O U T = 4 0 V , T j = +25° C
K a n d T P ac ka g e 0.30 0.4 0.15 0.4 A
H a n d P P a c ka g e 0.15 0.07 0.075 0.07 A
R M S O u t p u t N o i s e . % of V o u T T A = 2 5 °C , 10 H z < f < 10 k H z 0.003 0.003 %
Rip p le R eject ion Ratio V O U T = 1 0 V . f = 120 H z 65 65 dB
C A D J = 10^F 66 80 66 80 dB
L o n g - T e r m Sta b ility T A = 1 25° C 0.3 1 0.3 1 %
T h e r m a l R e s is ta n ce , J u n c t i o n t o Case H P ac ka g e 12 15 12 15 °C/W
K P ac ka g e 2.3 3 2.3 3 °C/W
T P a cka ge 4 °C/W
P P ac ka g e 12 ° C/W
N o te 1: Unless otherwise specified, these specifications apply -5 5 ° C < Tj < +150°C for the LM117, -2 5 ° C < T, < +150°C for the LM217, and
0°C < Tj < +125°C for the LM317; V ,N - V0 U T = 5V; and Iq u T = 0 1A for the T O - 39 and T O -2 0 2 packages and Iq u t = 0 5A for the T O -3 and T O -2 2 0
packages. A ltho ugh power dissipation is internally limited, these specifications are applicable for power dissipations of 2 W for the T O - 3 9 a n d T O -2 0 2 ,
and 2 0 W for the T O - 3 and T 0 ~ 220. Im a x 's 1 5A for the T 0 - 3 and T 0 -2 2 0 packages and 0 .5 A for the T O - 3 9 and T 0 -2 0 2 packages.
N o te 2: Regulation is measured at constant junction temperature, using pulse testing w ith a low duty cycle. Changes in output voltage due to heating
effects are covered under the specification for thermal regulation.
N o te 3: Selected devices with tightened tolerance reference voltage available. 507
Application Hints
In operation, the LM117 develops a nominal 1.25V Although the LM117 is stable with no output capa
reference voltage, V r e f , between the output and citors, like any feedback circuit, certain values of
adjustment terminal. The reference voltage is impressed external capacitance can cause excessive ringing. This
across program resistor R1 and, since the voltage is con occurs with values between 500 pF and 5000 p F.
stant, a constant current li then flows through the A solid tantalum (or 25/iF aluminum electrolytic)
output set resistor R2, g iv in g an output voltage of on the output swamps this effect and insures stability.
V0UT= V r e F lA D J R2 Load Regulation
The LM 1 17 is capable of providing extremely good load

regulation but a few precautions are needed to obtain
maximum performance. The current set resistor con
nected between the adjustment terminal and the output
terminal (usually 240H) should be tied directly to the
output of the regulator rather than near the load. This
eliminates line drops from appearing effectvely in series
v 0UT with the reference and degrading regulation. For exam
ple, a 15V regulator with 0 .0 5 H resistance between the
regulator and load will have a load regulation due to
line resistance of 0.05H x l|_. If the set resistor is con
nected near the load the effective line resistance will be
0.0 5 ft (1 + R 2/R 1) or in this case, 11.5 times worse.
Figure 2 shows the effect of resistance between the regu

lator and 240ft set resistor.
Since the 100jiA current from the adjustment terminal

represents an error term, the LM117 was designed to
minimize l/\D J anc* make it very constant with line
and load changes. To do this, all quiescent operating
current is returned to the output establishing a m ini
mum load current requirement. If there is insufficient
load on the output, the output will rise.
External Capacitors
An input bypass capacitor is recommended. A O.ljuF
disc or I l i F solid tantalum on the input is suitable input
bypassing for almost all applications. The device is more
sensitive to the absence of input bypassing when adjust F IG U R E 2. Regulator with Lina Ratiitanc*
ment or output capacitors are used but the above values in Output Laad
will eliminate the possibility of problems.
The adjustment terminal can be bypassed to ground on

the LM117 to improve ripple rejection. This bypass With the TO-3 package, it is easy to minimize the resis
capacitor prevents ripple from being amplified as the tance from the case to the set resistor, by using two
output voltage is increased. With a lOpF bypass capa separate leads to the case. However, with the TO-5
citor 80 dB ripple rejection is obtainable at any output package, care should be taken to minimize the wire
level. Increases over 10/iF do not appreciably improve length of the output lead. The ground of R2 can be
the ripple rejection at frequencies above 120 Hz. If the returned near the ground of the load to provide remote
bypass capacitor is used, it is sometimes necessary to ground sensing and improve load regulation.
include protection diodes to prevent the capacitor
from discharging through internal low current paths Protection Diodes
and damaging the device.
When external capacitors are used with any IC regulator
In general, the best type of capacitors to use are solid it is sometimes necessary to add protection diodes to
tantalum. Solid tantalum capacitors have low impedance prevent the capacitors from discharging through low
even at high frequencies. Depending upon capacitor current points into the regulator. Most 10/iF capacitors
construction, it takes about 25/uF in aluminum electro have low enough internal series resistance to deliver
lytic to equal 1/iF solid tantalum at high frequencies. 20A spikes when shorted. Although the surge is short,
Ceramic capacitors are also good at high frequencies; there is enough energy to damage parts of the IC.
but some types have a large decrease in capacitance at
frequencies around 0.5 MHz. For this reason, 0.01/jF When an output capacitor is connected to a regulator
disc may seem to work better than a 0.1^F disc as and the input is shorted, the output capacitor will
a bypass. discharge into the output of the regulator. The discharge
508
The bypass capacitor on the adjustment terminal can
discharge through a low current junction. Discharge
V 0 U T = 1-25V
0 1 p r o t e c t s against C1
D 2 p r o t e c t s against C 2
F I G U R E 3 R * 9ul«tor with Protection D iodes
Schematic Diagram
Answers to Selected
Odd-Numbered Problems
CHAPTER 1 ____________________________________________________________________________________
1-1. M athematical operation

1-3. Part identification number
1-5. Package style
1-7. Pin 8
1-9. (a) The comm on connection to the positive and negative supplies or a ground symbol, (b) M ake all volt
age m easurem ents with respect to power supply common.
CHAPTER 2 ____________________________________________________________________________________
2-1. Two for supply power— + V and - V . Two for input signals— inverting and noninverting. One for output.
2-3. (a) pin 2 (b) pin 3 (c) pin 6
2-5. (a) V0 = 0 V (b) l os = 25 mA (typical)
511
512 A nsw ers to Selected Odd-Numbered Problem s
2-7.
A v0
15 \
— +^sal
/ \ / ' \
/ \ y
-
—V
-15
2-9. Problem E-t applied to zero-crossing type:

2-7: ( —) input inverting
2-8; ( .■) input noninverting
2-11. (a) If is above Vref, Vn will be above 0 V at + Vydl. (b) If signal is wired directly (or via a resistor) to
the ( + ) input, the circuit is noninverting.
2-13. (a) Arbitrarily choose first a 0-5 V adjustm ent, (b) We now need a divider of 5 V/50 mV - 100 to 1.
(c) Pick an isolating resistor equal to or greater than 10 X the 5 -k fl pot. Pick 100 k-Q.
+15 V
io kn <
0 to 50 mV
0-5 k£1 pot <
- 0 to 5 V
Therefore, the divider resistor is 100 kH h- 100, or I kH.

514 Answers to Selected Odd-Numbered Problems
CHAPTER 4 _____________________________________________________________________________________
4-1. A fraction o f the output voltage is applied to the ( + ) input.
4-5. (a) 500 Hz (b ) 10 V (c) 6 V (d) - 6 V (e) 12 V

4-7. (a) I-'h = 1.5 V, VCTR = - 1 .2 5 V (b) n = 20 (c) - 1 . 19 V (d) R = 10 kft, nR = 200 k ft
4-9. VH = 1.5 V, VCTR = 1.25 V (a) n = 17.3 for ± V sat = ± 1 3 V. R = 10 kft. nR = 173 k f t (b ) Vrcf =
- 1 5 V. mR = 100 k ft 4-11. = 9.9 in i' (open sw itch) or 4-13. V'„ = V + + 4-15.311
V+jn = 0.4 mV' (closed switch)
V„ = 5 V
CHAPTER 5
5-1. (a) - 1 niA (b) - 2 V 5-5. (a) 4.5 k ft (b) 3.18 k ft (c) 1.59 k ft
5-7. (a) pup (b) 100 mA (c) 5 V 5-9. 500 ft
5-11. (a) - 0 . 2 mA, - 1.0 V, - 2 V (b) 0.2 mA, 1 V, 2 V5-13. / L = 0, VL = 0;V„ = + 5 V
5-15. See Figs. 5.7, 5.8, and 5 .1 1. 5-17. /,_ = 5 mA 5-19. 0 = 64.2°
5-21. C = I /xF, R, = 159 k ft, Rrcsistors = 300 kft
5-23. 100°C = 373 K. The AD590 outputs 373 /aA. In Fig.5-20(a), current through Rf = 373 — 273 i±A
100 M (right to left). VRf = 100 /aA X 10 k ft = 1000 mV = V„. V„ = 10o^ V x 100°C = 1000 rnV.
CHAPTER 6
6-1. (a) 6.9 V (b) - 6 .9 V 6-3. yes; R f = 5 kH 6-5. The time for C to return to its initial state.
6-7. ± 3 V; 1250 Hz 6-9. 9.4 V; 250 Hz 6-11. (a) Switched gain am plifier (b) Am plifier B;
Vn - Vrcf (c) With pin 9 at 1 V, V0 will be a sine wave identical to Vrcf. With pin 9 at — I V. V0 will be
inverted from Vref. 6-13. (a) 60° (b) 1.2 V 6-15. Pick C = 0.1 ( j l F . At 0.5 Hz, R , = 500 kfl; at 50 Hz,
Ri = 5 kCL
A nsw ers to Selected Odd-Numbered Problem s 515
CHAPTER 7 ____________________________________________________________________________________
7-1. 3 V
7-5. See Fig. 7-5. 7-7. Peak detector or follow-and-hold circuit 7-9. See Fig. 7-14.
7-11. See Figs. 7-18(b) and 7-17.
CHAPTER 8
8-1. V0 = -1 V 8-3. V„ = 0 V 8-5. R2 = RA = 100 k fl 8-7. CMRR = 5,623

8-9. (a) - 2 0 0 mV (b) 0 V 8-11. Va = - 2 VI I + 8-13. (a) 0.143 V (b) a = 0.1
8-15. (a) V„ = 5.0 V (b) 2.5 V 8-17. (a) Down (b) 10 mA (c) 1 V (d) 11 V
8-19. (a) Va goes positive (b) Vn decreases 8-21. (a) V„ = 25 mV (b) VD= 50 mV (c) V„ = 100 mV
CHAPTER 9
9-3. IB- = 0.2 fiA 9-5. V0 = 2.2 V 9-7. V„ = -2.5 mV 9-9. Vio = 2 mV
9-11. Rc = 5 kft 9-13. AV„ = ±50.5 mV
9-15. (a) Vio = 1 mV (b) IB- = 0.2 M (c) l„+ = 0.1 9-17. V,„ = 38 fiV
CHAPTER 10
10-1. 200,000 10-3. 5 M Hz 10-9. ACL = 990

10-11. (a) / H = 100 kHz (b) ACL = 70.7 10-13. / mux = 15.92 kHz 10-15. 6
CHAPTER 77
11-3. Band pass 11-5. R = 7.2 kH 11-7. | VD\ = 0.707 a t f c. There is a 45° phase angle a t f. for
each capacitor. 11-9. f c = 11.2 kHz 11-11. = 25 krad/s 11-13. R = 8 k fl
11-15. /?, = 14 kH, /?2 = 7.07 kH 11-17. /?3 = 6.35 kH, /?, = 12.7 k Cl, R2 = 3.17 kH
11-19. (a) 10 Hz (b) 60 Hz (c) 6
11-21. Apply Eq. (11-3) 11-23. Q = 0.35
11-25. (a) Connect the bandpass filter to an inverting adder as in Fig. 11-15. (b) f L = 92 H z ./ H = 177 Hz
516 A n sw e rs to Selected Odd-Numbered Problem s
CHAPTER 12
12-1. (a) Vn = 2.5 V (b) V„ = - 2 .5 V (c) Vlt = - 2 .5 V (d) V„ = 2.5 V

12-5. (a) 3.2 V (b) 3.2 V peak at 800 Hz 12-7. Vn = 4.33 V
12-9. Peak value = 2 V; sum frequency = 18 kHz; difference frequency = 12 kHz
12-11. Carrier = 100 kHz; lower = 90 kHz; upper = 1 1 0 kHz
12-13. 41 kHz, I kHz; 39 kHz, 1 kHz; 40 kHz, 0
CHAPTER 13 ____________________________________________________________
13-1. One-shot, free running 13-3. 70 Hz 13-5. 107 Hz 13-7. 3.1 k ft 13-9. 6.95 ms
13-11. I ms < f|ligh < 2 ms, RA = 15 k ft for /high = 1.65 ms 13-13. 170 ms
13-15. (a) 50 ms (b) 600 ms (c) 12.75 s 13-17. 62.5 Hz
CHAPTER 14
14-1. (a) 1024 (b) 16,384 14-3. Vfs = 9.99 V 14-5. D = 01011111
14-7. (b) lp = 0.125 mA
(c) A V 0 = 0.625 V/bit
(d) Vn = D X 0.625 V/bit
(e) Vfs = 9.375 V __ _
14-9. Mem ory buffer register, selection logic 14-11. (a) CE and CS
14-13. 4000/4001; 8000/8001; C000/C001
CHAPTER 15 ______________________________________________________
15-1. 0 = 0111100000 15-3. Vin = 10.0204 V, Caution: exceeds FSR.

15-5. (a) 7, = 83.33 ms
(b) Vnr = - 5 0 mV, 7% = 41.65 ms
(c) D = 500
15-7. Conversion 15-9. Ground pin 1)
15-11. (a) ~ 10 Ats
(b) 105 conversions
(c) See Exam ple 15-7.
15-13. 255
CHAPTER 16
16-1. 38 V 16-3. (a) Decreases (b) Increases 16-5. (a) 8H (b) 29%
16-7. VdcFL = 25 V 15-9. 6.1%
16-11. (a) £ m = 35.3 V (b) VdcFL = 29.3 V (c) 20% (d) 1.42 V (e) 4.9% (f) 26.8 V
A nsw ers to Selected Odd-Numbered Problem s 517
16-13. (a) 6.0 V (b) \V a centered on V„c = 12 V (c) Waveshape
V.
A
1------------------------ ^ ^ ------------------ 1-----------► (ms)

0 8.2 16.7
16-15. R2 = 4560 0 16-17. (a) 1.2 V (b) -1.2 V 16-19. 7.2 to 19.7 V
16-21. R2 = 1032 n
Bibliography
A n a l o g D e v i c e s , I n c ., Analog-Digital Conversion Handbook (1972), Analog-Digital Conversion

Notes (1977), Non-linear Circuits Handbook (1979), Data Converter Reference Manual Vol. II
(1992), Amplifier Reference Manual (1992), Applications Reference Manual (1993), Special
Reference Manual (1992).
BLH E l e c t r o n i c s , Strain Gages, SR4, BLH, Waltham, Mass. (1979).
B u r r - B r o w n I n t e r n a t i o n a l , Product Data Book, Tucson, Ariz. (1994); Applications Handbook
(1994).
C o u g h l i n , R o b e r t F., a n d V i l l a n u c c i , R o b e r t F., Introductory Operational Amplifiers and Linear
ICs, Theory, and Experimentation, Prentice-Hall, Inc., Englewood C l i f f s , N.J. (1990).
D r i s c o l l , F r e d e r i c k F ., 6800/68000 Microprocessors, Breton Publishers, Boston (1987).
D r i s c o l l , F r e d e r i c k R, a n d C o u g h l i n , R o b e r t F., Solid State Devices and Applications, Prentice-
Hall, Inc., Englewood Cliffs, N.J. (1975).
D r i s c o l l , R, C o u g h l i n , R., V i l l a n u c c i , R., Data Acquisition and Process Control with the
M68HC11 Microcontroller, 2nd Edition, Prentice Hall (2000).
F a i r c h i l d I n s t r u m e n t a n d C a m e r a C o r p o r a t i o n , Linear Division Products (1982), Voltage
Regulator Handbook (1974), F a i r c h il d , M o u n t a in V i e w , C a lif .
F r e d e r i k s e n , T h o m a s M., Intuitive IC Op Amps, National Semiconductor Technology Series,
National Semiconductor Corporation, Santa Clara, Calif. (1984).
518
Bibliography 519
H a r r is C o r p o r a tio n , Linear and Telecom IC, H a r r is , M e l b o u r n e , F la . (1994).

M o r r is o n , R., Grounding and Shielding Techniques in Instrumentation, John Wiley & Sons, Inc.,
New York (1967).
M o t o r o l a S e m i c o n d u c t o r P r o d u c t s , I n c . , More Value Out o f Integrated Operational Amplifier
Data Sheets, AN-273A, Motorola, Pheonix, Ariz. (1970).
N a t i o n a l S e m i c o n d u c t o r C o r p o r a t i o n , Linear Databook (1989), Linear Applications Handbook
(1991), Special Functions Databook (1989), Voltage Regulator Handbook (1986), Audio
Handbook (no date), Linear Supplement Databook (1988), National Semiconductor Corporation,
Santa Clara, Calif.
P e a s e , R o b e r t a . , Troubleshooting Analog Circuits, Butterworth-Heinemann (1991).
P h i l b r i c k R e s e a r c h e s , I n c . , Applications Manual fo r Computing Amplifiers fo r Modeling,
Measuring, Manipulating and Much Else, Nimrod Press, Inc., Boston (1966).
SHErNGOLD, D a n ie l H., Transducer Interfacing Handbook, Analog Devices, Inc., Norwood, Mass.
(1980).
S i g n e t i c s C o r p o r a t i o n , Data Manual, S i g n e t i c s , S u n n y v a l e , C a l i f . (1977).
S m i t h , J.I., Modern Operational Circuit Design, John Wiley & Sons, Inc., New York (1971).
V i l l a n u c c i , R., e t a l . , Electronics Techniques: Shop Practices and Construction, 6th ed., Prentice-
Hall, Inc., Englewood Cliffs, N.J. (1997).
522 Index
sidebands, 3 47-351 introduction, 295, 312 Chip select, 4 2 0 -4 2 2 , 445

standard, 3 4 8 -3 5 1 narrow-band, 314, 317 Clipping, 207
sum frequencies, 3 4 5 -3 4 7 octave, 318 Closed loop gain
universal receiver, 3 5 8 -3 6 0 PSpice-sim uIation, 322 -3 2 7 effect of open loop gain, 2 7 9 -2 8 4
waveshapes, 3 5 0 -3 5 5 w ide-band, 3 1 4 -3 1 6 frequency response, 282
AM radio, 358 Bandwidth introduction, 45
Analog divider, 3 4 0 -3 4 3 filters, 313 CM R, 221, 271
Analog m ultiplier {see M ultipliers) inverting amplifier, 282 Collector current, 128
Analog output current (DAC), non-inverting, 282, 283 Com m on-m ode voltage
4 1 6 -4 1 8 unity-gain, 277 differential amplifier, 221
Analog output voltage (DAC), Band-reject filter, 319 gain, 219
4 1 7 -4 1 9 Basic differential amplifier, 217 input voltage, 220
A nalog system , 2, 3 Basic m eter m ovement, 1J9 rejection, 219
A nalog-to-digital converters Battery charger control, 9 8 -9 9 Com parators
AD670, 4 4 3 -4 4 9 Beta, 128, 135 adjustable set points, 100-103
characteristics, 4 3 1 -4 3 4 Bias current com pensation, 259-261 battery charger, 98 -1 0 1
circuit sym bol, 432 Bias currents {see Input bias circuit sim ulation PSpice, 3 6 -4 0
conversion process, 4 4 0 -4 4 2 currents) definition, 87
flash converter, 4 4 7 ^ 4 9 Biom edical signal, 107 effect of noise, 8 5 -9 0
frequency response, 450 Binary equivalent, 433 level detectors, 2 1 -2 4
high tim e to digital code, 36 Binary pattern signal generator, 391 LJM311, 104-107
integrating, 4 3 5 -4 3 9 Bipolar dead-zone circuit, 208 LM 339, 3 0 -3 5 , 103
m icroprocessor com patibility, Bipolar operation (DAC), 402, 404 positive feedback, 8 7 -9 2
4 4 3 -4 4 7 Bipolar supply, 10, 15-16 process control, 9 9 -1 0 2
m icroprocessor control terminals, Bipolar power regulator supply, 468 propagation delay, 104
445, 448 Bipolar voltage regulator, 474 voltage level detectors, 2 0 -2 6
output-input equation, 4 3 2 -4 3 5 B oost transistor, 125-128, 135 voltage level detectors with hys
quantization error, 433 Bounding, 189 teresis, 9 1 -9 9
resolution, 431 Breadboarding, 10, 11 window detector, 108-110
selection process, 446 Break frequency, 276 zero-crossing detectors, 20, 91
successive approxim ation, 441 Bridge am plifier C om pensating capacitor, 275
testing, 447, 448 basic operation, 244 Com pensating resistor, 259
tem perature m easurem ent inter excitation voltage, 244 Com puter interfacing
face, 7 1 -7 5 high-current transducers, 248 analog-to-digital converters,
with pulse-w idth modulator, introduction, 243 4 4 3 -4 4 5
36, 37 tem perature m easurement, 73, digital-to-analog converters, 421
Angle voltage, 173, 174 2 4 5 -2 4 9 pulse-w idth modulator, 29, 36
A ol (see Open loop gain) zeroing procedure, 245 tem perature m easurem ent, 7 1 -7 7
A perture error, 447 Bridge-balancing, 237 Com pression, 233
Aperture tim e uncertainty, 451 Bridge excitation voltage, 244 Connection diagram , 8
Assembly language program , 427 Buffer amplifier, 61 Constant current source, 126
Astable m ultivibrator, 152 Butterworth filters, 299 Constant high current source,
IC 555 timer, 3 6 2 -3 8 4 127-129, 1 34-136
op amp, 152 Conversion process DAC, 408
Audio detector, 352 Conversion time, 442, 447
Audio mixer, 53 Capacitor charge, 377 Convert com m and, 446
Autom atic gain control, 341 Carrier wave, 342-351 Converters
Auto-zero, 439 AD630, 170 analog-to-digital, 4 3 0 -4 5 2
Average bias current, 254 pulse width modulator, 3 1 -3 4 current-to-current, 133, 136
Averaging amplifier, 56, 57 Cascading filters, 302, 309 current-to-voltage, 130-135
CD4029, 424 digital-to-analog, 4 0 0 -4 2 6
Celsius thermometer, 140 tem perature-to-voltage, 3 1 -3 6 ,
Balance network, 239 Center frequency, 314 7 1 -7 7 , 2 4 5 -2 5 0
Balanced m odulator/dem odulator Center tap transformer, 456, 465 voltage-to-current, 1 2 0 -1 2 6
{see AD633) Center voltage, 9 1 -9 8 voltage-to-frequency, 1 64-169
Balancing a bridge circuit, 238 Characteristic resistance, 409 C om er frequencies, 282
Band-eliraination filter, 295 Charge hold capacitor, 198 Cosine wave, 335
Band-pass filters, 295, 296, 315 Chart recorder, 135 Counter timers, 3 8 4 -3 9 0
cascading, 315 Chip enable, 4 2 0 -4 2 2 , 445 Coupling capacitor, 253
Index 523
Current amplifier, 133-135 full-wave bridge unregulated gain error, 406

Current com pensating resistor, supply, 4 6 4 -4 7 6 ladder network, 4 0 9 -4 1 4
2 5 9 -2 6 2 high-pass filters, 309 microprocessor compatibility,
Current-divider circuit, 136 inverting amplifier, 45 4 2 1 -4 2 4 , 426
Current multiplier (see Current inverting level-detector with m onotonic, 408
amplifier) hysteresis, 95, 96 multiplying DAC, 414
Current set resistor RS, 232 low-pass filter, 298 offset, 406
Current source, 130-136 multi-channel amplifier, 56 output-input equation, 403
Current switch, 4 0 9 -4 1 3 non-inverting am plifier, 59 resolution, 4 0 1 -4 0 5
Current-to-current converter, non-inverting voltage level detec D igital volume control, 414
133, 136 tor, 9 2 -9 4 Diode protection, 134-136
Current-to-voltage conversion, notch filter, 321 Diode tester, 123
130-135 phase shifter, 137, 138 DIP, 6, 7
Cutoff frequencies sawtooth wave generator, 167 Discharge terminal, 366
band-pass, 3 1 2 -3 1 8 sensor equation, 7 2 -7 5 Divider, 340
high-pass filter, 296 signal conditioning, 7 1 -7 5 Doubler circuit, 337
low-pass filter, 2 9 6 -3 0 5 solar cell power, 133-136 Drift, 267
statement of the problem, 71 Droop, 198, 199
tem perature measuring circuit, Dropout voltage, 460, 476
7 1 -7 5 , 139 Double-ended lim it detector, 108
DAC (see D igital-to-analog triangle wave generator, 160-166 Dual-in-line package, 6, 7
converters) universal high-resistance volt Dual-sJope ADC, 437
DAC08, 4 1 4 -4 2 0 meter, 122 Dummy gage, 237
Data acquisition block diagram , 2 Detection, 352 Duty cycle, 3 7 3-375
Data bus, 421, 422, 444 Difference amplifiers, 69 Duty cycle controller, 3 2 -3 4
Data sheets Difference frequencies, 345-351 Dynamic test circuit for AD558, 424
adjustable voltage regulator, Differential amplifiers
5 0 5 -5 1 0 adjustable gain, 2 2 3-225
com m on-mode voltage, 219
Earth ground, 14, 223, 450, 457, 462
comparator, 4 9 8 -5 0 4
ECM, 219
op amp, 4 8 1 -4 9 7 differential gain, 217, 232
{see Differential input voltage)
DB, 276 disadvantage, 219-2 2 3
EFS, 119-122
Dc meter movement, 119-121 introduction, 217
EKG, 107
Dc offset, 53 m easurement with, 219, 222
Electrocardiogram , 107-109
Dc perform ance noise, 222
Electronic single-pole double throw
com pensation, 2 5 9 -2 6 3 reference terminal, 228
switch, 101
drift, 267 sense terminal, 229
Em itter current, 128
input bias currents, 254 Differential gain, 218
Emitting diode, 134
input offset current, 256 Differential input to differential
End of conversion, 443, 438
input offset voltage, 26J output amplifier, 223 -2 2 5
Excitation voltage, 244, 248
Dc voltage regulation curve, Differential input voltage Ed, 5, 6,
457-467 16-19
Dc voltmeter, 120-122 Differential voltage measurement, FC (see Cutoff frequency)
Dead-zone circuits 2 3 6 -2 3 8 Fahrenheit therm ometer, 140
bipolar, 208 Differential voltage-to-current Feedback
negative output, 203 converter, 126-127, 231 negative, 44
positive output, 205 Differentiators, 144-146 positive, 85
precision clipper, 208 Digital codes, 401, 431, 446 resistor, 45
Decade, 276 Digital computers, 2, 3 Filter capacitor, 4 5 6 -4 6 6
Decibels, 276 Digital controlled current source, Filters
Decim al value, 404 129, 130 band-elim ination, 295
Decoder, 422, 427, 443 Digital inputs, 402, 4 1 2 -4 1 5 band-pass, 295, 3 1 2 -3 1 8
Delay for servoamplifier, 144 Digital outputs, 432 cascading, 302, 309
Dem odulation, 352-361 Digitally controlled switches, 409 com ponents, 320
Design exam ples or procedures D igital-to-analog converters, definition, 295
ac voltmeter, 120-122 4 0 0 -4 2 6 high-pass, 295, 30 5 -3 1 2
audio mixer, 53 AD558, 4 2 2 -4 2 4 low-pass, 295 -3 0 5
averager, 57 characteristics, 4 0 1 -4 0 6 nanrow-band, 316-321
band-pass filters, 3 1 2 -3 2 7 circuit symbol, 402 notch, 320
battery charger, 98, 99 conversion process, 408 PSpice sim ulation, 322 -3 2 7
dc voltmeter, 120-122 DAC-08, 4 1 4 -4 2 0 wide band, 3 1 4 -3 1 6
524 Index
555 IC timer, 3 6 2 -3 8 4 non-inverting amplifier, 2 8 1 -2 8 7 IB+ or IB— (see Input bias currents)
applications, 375-381 notch filter, 319 TC voltage references, 2 7 -2 9
astable operation, 364, 3 7 1 -3 7 7 octave equalizer, 318 Ideal closed-loop gain, 279-281
clock, 424 op amp, 253, 279 Ideal diode circuits, 189-192
frequency shifter, 377 wide-band filter, 3 1 4 -3 1 6 Ideal op amp, 14, 15
one-shot operation, 376 Frequency shifting, 343, Ideal voltage source, 64
operating m odes, 364 3 5 6 -3 6 1 , 377 Identification code
packaging, 365 Frequency spectrum, 348 circuit designation. 4 - 1 0
PSpice sim ulation, 396-398 Frequency synthesizer, 393 designator, 9, 15
terminal operation, 365 Full-load current and voltage, letter prefix, 9, ! 5
Flash converters, 447 4 5 7 -4 6 6 letter suffix, 9, 15
Flatpack, 8 Full-power output frequency, 287 package style, 7 - 1 0
Floating differential voltage, 230 Full-wave bridge rectifier, 456, tem perature range, 8 -1 0
Floating loads, 122, 123 4 6 3 -4 6 6 IF amplifier, 360
Foil strain gage, 234 Function switch, 121 Independently adjustable setpoint
Follow-and-hold am plifier, 198 FWB (see Unregulated power controller, 102-104
Force, 2 1 9 -2 2 8 supply) Infrared em itting diode, 118, 125
Free-running m ultivibrator (see Interm ediate frequency, 356-361
M ultivibrator) Input bias currents
Gage factor, 234
Free-running oscillator, synchro average value, 254
Gain
nized outputs, 390 com pensating resistor, 260
closed loop, 4 5 -5 0
Frequency effect on output voltage, 256
com m on mode, 219
divider, 381 introduction, 253
DAC, 407
doubling, 3 3 4 -3 4 6 m easurem ent, 262
differential, 218, 232
m odulation, 168, 3 4 3 -3 5 2 model, 261
open-loop, 1 6 -1 9 ,4 5
multivibrator, 154-156 offset current, 254
Gain error (DAC), 406, 407
op amp, 253, 2 7 5 -2 8 4 Input capacitance, 290
Gate current, 24
precision tri/square wave, 172 Internal frequency com pensation,
G F (see Gage factor)
response, 253 275
Glitch, 425
sawtooth wave, 165-169 Input offset current, 254
Ground
shifter, 3 5 6 - 3 6 1 Input offset voltage
defined, 1 0-16
shift keying, 168, 343 adder circuit, 264
earth, 14, 222, 457, 462
sidebands, 3 4 8 -3 5 1 defined, 261
loop, 218
sine-wave generator, 178 drift, 267
star, 12
spectrum , 347-351 effect on output voltage, 257
sym bol, 10
sum, 345-351 m easurem ent, 262
Grounded transducers, 248
synthesizer, 392 model, 262
triangle-w ave generator, 162, 163 nulling, 266
unipolar tri-wave, 163 Handshake signal, 105 Input pulse circuit, 380
V-to-F, 167-169 Headroom , 4 7 0 -4 7 2 Input term inals, 1 6 -1 8
Frequency doubling, 334 H eatsin k , 135, 136, 475 Instrumentation am plifiers
Frequency of oscillation H eterodyne, 343, 357 basic differential am plifier, 217
555 timer, 3 7 1 -3 7 7 High-current transducers, 135, circuit operation, 220, 2 2 6 -2 2 9
multivibrator, 152-155 136, 248 differential m easurem ents, 230
precision sine-w ave generator, H igh-frequency generator, 178 differential V-to-I converter,
173-177 High frequency limit fHl, 281 23 1 -2 3 3
precision tri-wave generator, High-im pedance state, 445 gain, 217, 230
170-172 High-pass filters, 295, 3 0 5 -3 1 2 referencing output voltage, 228
sawtooth generator, 165-169 com parison, 3 11 remote voltage sensing, 230
tri-wave generator, 160-164 40dB/decade, 308, 309 strain gage application, 2 3 3 -2 3 6
unipolar tri-wave, 163-164 60dB/decade, 309, 312 sense term inal, 229
V-to-F converter, J 6 7 -1 6 9 20dB/decade, 306, 308 Integrated circuit timers
XR 2240, 3 8 5 -3 9 4 PSpice sim ulation, 3 2 3 -3 2 6 555 IC, 3 6 2 -3 8 4
Frequency response High-resistance dc voltmeter, program m able, 385
analog-to-digital converter, 447 121-123 PSpice sim ulation, 3 9 6 -3 9 8
band-pass filters, 3 1 2 -3 1 8 High-time, 3 2 -3 4 XR 2240, 3 8 4 -3 9 7
high-pass filters, 3 05 -3 1 2 High-Z state, 445 Integrating ADC. 4 3 5 -4 3 9
inverting amplifier, 283 Hold capacitor, 198 Integrator, 140-142
low-pass filters, 2 9 7 -3 0 5 H ysteresis, 92-101 Interface
narrow band filter, 317 Hysteresis loop, 368 AD590 to m icrocontroller, 138
Index 525
D A C , 427 L in ea r h alf-w av e rectifiers stress, 2 4 0 - 2 4 2

m ic ro c o n tro ller to load, 2 circ u it o p e ra tio n , 189 tem p eratu re, 140, 245
p u lse-w id th m o d u la to r to m ic ro P S p ice sim u la tio n , 209 unreg u lated p o w e r supply, 4 62
c o n tro ller, 36, 71 L in ea r IC v o ltag e regulators, voltage, 1 1 9 -1 2 3
s en so r to m icro co n tro ller, 2, 71 3 7 0 -3 7 8 w eight, 243
brid g e a m p lifie r to m ic ro c o n L in ea rity error, 4 08, 435 z en e r voltage, 1 2 3 -1 2 4
troller, 248 LM 31 I, 1 0 4 -1 0 7 M em ory, 91, 101, 369
m ic ro p ro ce sso r to telep rin ter, 130 L M 323, 9 M em ory b u ffer registers
Internal resistan ce, 63, 64 LM 335, 7 2 -7 3 D A C, 4 2 0 ,4 4 2
IO S (see Input o ffset c u rren t) L M 3 3 9 , 35, 103 M em ory latching register, 423
Inverting adder, 5 2 - 5 3 , 78 L oad M ete r current, 1 1 9 -1 2 3
Inverting a m p lifiers cu rren t, 4 7 - 5 0 , 1 2 3 -1 2 7 , 134 M icro p h o n e, 24, 130
adder, 5 2 - 5 4 flo atin g , 1 2 3 -1 2 5 M icro co n tro lle r
an aly sis, 51 g ro u n d e d , 125, 127 A D 5 9 0 interface, 139, 140
A O L effect on gain, 279 re sista n c e , 15 d ifferen tial am plifier. 233
averager, 56, 57 v oltage, 126 e le ctro ca rd io g ram , 1 0 6 -1 0 8
b a n d w id th , 2 8 1 -2 8 5 L o ad c u rre n t c o n trol, 1 2 3 -1 2 7 in data a cq u isitio n sy stem s, 2
c lo sed loop g ain , 4 5 - 4 7 L o cal o scillato r, 360 in terfacin g to 4 -to -2 0 m A
d esig n , 51, 56 L ogic c ircu it p o w e r supply, 472 transm itter, 128
input resistan ce, 55, 63 Low freq u en cy lim it, fL, 281 han d sh ak e signals, 105
in tro d u ctio n , 4 5 - 4 7 L o w er c u to ff frequency, 282 p ulse w idth m odulator, 36
m u lti-ch an n el, 5 3 - 5 7 L o w er side b and, 347 M icro p ro c esso r
o u tp u t cu rren t, 4 6 - 4 8 , 58 L o w er th re sh o ld voltage, 8 9 - 9 7 b rid g e am plifier, 245
sin g le supply, 67, 68 L o w -p ass filters control term in als, 445
PS pice sim u la tio n , 7 6 - 8 0 4 0 d B /d e ca d e , 300 co n tro lle d A D C , 4 4 3 - 4 4 7
Inverting input term in al, 4, 16, 45 6 0 d B /d e ca d e , 302 co n tro lle d c u rre n t source, 128
Invertin g lin ear h alf-w av e rectifier 2 0 d B /d ecad e, 2 96 co n tro lle d D A C, 4 2 0 - 4 2 3 , 427
circu it an aly sis, 1 9 0 -1 9 2 P S p ice sim u latio n , 323 in te rfac e -to -te le p rin te r, 129
P S p ice sim u latio n , 209, 210 L S B (see L east sig n ifican t bit) w ith pu lse w idth m odulator, 36
Inverting z ero -c ro ssin g d etecto r, L S R (se e L ig h t-sen sitiv e resistor) M ilitary sp ec ifica tio n code, 9
8 5 -9 1 M ini-D IP , 4 - 8
h y steresis, 9 0 - 9 2 M issing p ulse d etector, 383
in tro d u ctio n , 20, 21 Manufacturer codes, 7 -1 0 M o d ulation
noise, 8 5 - 9 0 M atc h in g L E D s, 125, 126 A D 630, 1 7 0 -1 7 4
positive feed b ack , 8 5 - 8 9 M ath e m a tic s o p eratio n s, 2, 14 am p litu d e, 3 4 3 - 3 4 6
th resh o ld vo ltag es, 8 8 - 9 8 MAV, 2 0 0 - 2 0 2 b alan ced , 3 4 3 - 3 4 6
IR E D , 53 M ax im u m sin e frequency, 287 frequency, 167, 168
Iso latio n am plifier, 61 M C 6 8 0 0 , 427 freq u en cy sp ectru m , 348, 351
M ean ab so lu te v alue a m p lifie r integrated circu it for A D 633, 354
circ u it an aly sis, 2 0 0 - 2 0 2 m ix er (see A ud io m ixer)
Kelvin, 145, 146
P S p ice sim u latio n , 213, 214 pulse w idth, 31 - 3 6
M ea su re m en t single sid eb a n d , 356
Ladder bias cu rren ts, 262 stan d ard A M , 348
c u rre n ts, 4 1 0 - 4 1 2 cu rren t, 131 sup p ressed carrier, 352
eq u atio n , 411 d ifferen tial vo ltage, 2 3 0 M o d u latin g w ave, 3 4 2 -3 4 5
netw o rk , 4 0 9 -4 1 3 d io d e v oltage, 123, 124 M o d u lato r/d e m o d u la to r (see
Large sig n al freq u en cy lim its, force, 243 A D 633)
2 8 5 -2 8 7 freq u en cy re sp o n se , 64, 253, 282 M o dulus o f elasticity, 242
L atch in g , 4 2 0 input o ffset c u rrent, 2 5 9 -2 6 1 M o n o sta b le m ultivibrator,
L ead less ceram ic ch ip carrier, 7 input o ffset vo ltage, 262 1 5 6 -1 6 0 , 378
Least sig n ific a n t b it (L S B ), 4 01, 431 lig h t-em ittin g diode, 125 M o n o sta b le op eratio n , 156
L E D (see L ig h t e m ittin g dio d e) phase angle, 337 M o n o to n ic, 408
Level shifter, 6 p h ase sh ift, 1 3 7 -1 4 1 M ost sig n ific a n t bit (M S B ),
L ig h t co lu m n voltm eter, 24, 25 p h o to co n d u ctiv e cell, 132, 133 401, 4 80
Light e m ittin g dio d e, 2 4 - 2 6 photo d io d e, 132, 133 M u lti-c h a n n el am plifier, 55, 56
L ig h t-e m ittin g d io d e tester, 125, 126 p ressu re, 243 M ultip liers
L ig h t-sen sitiv e resistor, 26 pro p a g a tio n delay, 110 a m p litu d e m od u latio n , 3 4 3 - 3 5 2
L im it detector, 1 0 8 -1 1 0 re sista n c e c h an g e, 235 a nalog divider, 3 4 0 - 3 4 2
L in ea r circuit d esig n p ro c e d u re , short c irc u it cu rren t, 1 2 8 -1 3 3 de m o d u la tio n , 3 5 5 - 3 5 8
7 1 -7 7 so lar cell pow er, 1 3 3 -1 3 6 frequency do u b lin g , 334
frequency shifting, 343, 356-361 O ctave, 277 m ultivibrators, 152-155
modulator, 343 Octave equalizers, 318, 319 non-inverting am plifiers, 5 9 -6 7
m ultiplying dc voltages, 3 3 1 -3 3 4 Octave filter, 318, 319 nulling offsets, 263
phase angle detection, 3 3 7 -3 4 0 Offset binary, 402, 446 phase shifter, 138
quadrants, 332 Offset current (see Input offset photo detector, 132-134
scale factor, 33 1, 341 current) PSpice sim ulation (see PSpice
squaring, 334 Offset error, 406, 433 sim ulation)
square roots, 342 Offset voltage (see Input offset signal generators, 151-176
M ultiplying DAC, 414 voltage) solar cell power, 134, 135
M ultivibrators O ne-shot m ultivibrator universaJ voltmeter, 120-122
555 timer, 364, 3 7 1 -3 7 8 555 timer, 368, 3 7 8 -3 8 4 voltage-level detectors, 2 1 -2 8
free running, 1 52-154 op am p 156-160, 177 zero-crossing detectors, 2 0 -2 2 ,
one-shot, 1 5 6 -159 O n-off control principles, 99 8 5 -9 3
PSpice sim ulation, 175, 181, On-off controller, 100-102 Op amps with diodes
3 9 6 -3 9 8 Op amps absolute value circuits, 194-196
ac limits, 2 7 3 -2 8 3 ac-to-dc converter, 200
BiM OS, 3 dead-zone circuits, 2 0 3 -2 0 4
Narrow-band filters block diagram , 5 linear half-wave rectifier,
introduction, 316 circuit symbol, 4, 14 189-191
octave filter, 318, 319 connection diagram , 7, 8 MAV circuit, 200
perform ance, 319 dc limits, 253-2 71 peak detectors, 198
Negative feedback, 45 definition, 2 peak follower, 199
Negative level detector, 21, 22 differential input, 16-20 precision clipper, 208
Negative peak follow -and-hold, 200 dual, 3 signal polarity separator, 193, 194
Negative saturation voltage, 16-23 effect of open-loop gain, 2 7 9 -2 8 4 triangle-to-sine wave shaper, 208
Negative supply frequency response, 253, 276 Open collector, 3 0 -3 3
op amp term inal, 4, 8 -1 1 ideal, 14 Open loop gain, 45, 275
voltage regulated, 457 identification code, 4 —10 effect on am plifier gain, 273, 283
Noise input bias currents, 18 frequency dependence, 2 79-281
com parators, 8 5 -9 0 input offset current, 255 introduction, 18, 19, 45
currents, 222 input offset voltage, 261 Operating modes for 555 timer, 364
gain, 290 input term inals, 17, 18 Optocoupler, 134
op amp circuits, 289 internal circuitry, 5, 6 Oscillators
reduction, 223 level shifter stage, 6 555 timer, 371
Non-inverting am plifiers noise, 85, 289 multivibrator, 152-155, 37 L
adder, 66 open loop voltage gain, 45, 276 precision triangle wave, 170-171
circuit analysis, 5 8 -6 0 output voltage swing, 16, 285 PSpice sim ulation, 179-185
closed-loop gain, 5 8 -6 0 , PIN, 4, 8 -1 0 sawtooth wave, 173-178
2 7 9 -2 8 7 pinout, 7 - 9 square wave, 152-164
design procedure, 60 power supply, 4, 10-15 triangle wave, 160-164, 172
input resistance, 58, 59 saturation voltage, 16, 17 XR2240, 388, 389
PSpice sim ulation, 7 8 -8 0 slew rate, 253, 2 8 5 -2 8 9 Output current limit, 16, 472
single-supply operation, 67 symbol, 4, 14 Output format, 443
voltage follower, 6 1 -6 4 tem perature range code, 9 Output register, 445
waveshapes, 60 term inals, 14 Output term inals
No-load current and voltage, Op amp applications op amp, 4 - 8 , 1 5 -1 7
4 5 7 -4 6 6 bridge amplifiers, 243 quad voltage com parator, 3 0 -3 4
Non-inverting input term inal, 4, 16 com parators, 2 0 -3 2 Output voltage swing, 16-20, 285
Non-inverting level detector, 92, 96 constant-current source, 126, function of frequency, 285
N on-inverting zero-crossing detec 127, 134
tor, 2 0 -2 7 current-to-current converters,
Non-linearity, 247, 408 133-135 Package code, 8
Norton equivalent circuit, 129 current-to-voltage converters, Packaging, 6 - 9
Notch filters 130-135 Parasitic capacitance, 290
design procedure, 321 dead-zone circuits, 205 Part identification number, 4 - 9 , 1 1
introduction, 319 differential amplifiers, 6 9 -7 0 Passband, 295, 31 4 -3 1 8
theory, 320 differential V-i.o-1 converter, Passive filters, 295
Null procedure, 267 126, 127 Peak detector, 198
Nulling effects of Vio and Iost filters, 2 9 4 -3 2 6 Peak follower, 199
2 6 5 -2 6 7 inverting amplifiers, 4 5 -6 1 Peak inverse voltage, 465
Index 527
Peak reading voltmeter, 121 Priority encoder, 447 Read only address, 420, 447
Peak-to-peak ac voltmeter, 121, 122 Process control, 9 9 -101 Read only register, 420
Peak-to-peak ripple voltage, Program m able tim er/counter R ead/write line, 420, 421
4 5 7 -4 6 8 XR2240 Recovery time, 159
Pen position, 228 binary pattern signal Rectifier diodes, 456, 4 6 4 -4 6 6
Percent regulation, 4 6 1 generator, 391 REF-02, 2 7 -2 9 , 66
Percent ripple, 463 circuit description, 384 Reference
Period (T), 35, 373, 394 counter operation, 3 8 6 -3 8 9 designator, 4
Phase-angle detection, 337 free-running oscillator, 390 output voltage Vref, 228
Phase-angle meter, 339 frequency synthesizer, 393 resistance, 245
Phase shifter, 143, 144 introduction, 384 term inal, 228, 414
Photo conductor, 26 program m ing the outputs, 388 Relay, 98, 99
Photo conductive cell, 132, 144, 150 switch program m able timer, 390 Remote voltage sensing, 230
Photo diode, 132, 133 timing applications, 387-391 Resonant frequency, 3 1 3 -3 1 6
Photovoltaic cell (see solar cell) Propagation delay, 108-111 Resistance bridge, 234-241
PIN (see Part identification number) PSpice simulation Resistance ladder (see R-2R ladder
Pinout, 5 - 9 band-pass filter, 327 network)
PIV, 465 bipolar triangle-wave generator, Resolution, 27, 4 0 1 -4 0 3 , 431
Plastic lead-chip carrier, 7 160-163 Resonant frequency, 295, 313
Positive feedback, 8 5 -9 0 com parator operation, 36-41 Response time, 108
Positive level detector, 21, 24 differential voltage-to-currem Rfi 4 5 -5 0
Positive peak follower and hold, 198 conversion, 146, 147 R h 4 5 -5 0
Positive saturation voltage, 16-23 free running multivibrator, Ripple rejection, 472
Positive supply 179-181 Ripple voltage, 4 5 7 -4 7 2
op amp term inal, 4, 8-11 high-pass filter, 325 Rise time, 278
voltage regulator, 457 inverting adder, 78 RMS ac voltmeter, 121, 122
Positive voltage level detector, 91 -9 3 inverting amplifier, 7 8 -8 0 R-2R ladder network, 4 0 5 -4 1 6
Power-on tim e delay, 368 linear half-wave rectifier, Roll-off, 299, 301, 303
Power supplies (see Unregulated 209, 210 Room thermostat, 100-104
power supplies) low-pass filter, 323 Rung currents, 4 0 9 -4 1 2
Power supplies for linear ICs, MAV circuit, 213, 214
4 7 3 -4 7 8 m ultivibrator using 555, 396
Power supply com m on, 457 non-inverting, amplifier, 81, 82 Safe area protection, 472
Power supply rejection ratio, one-shot multivibrator, 181, 182 Sample and hold amplifier, 198,
271, 272 precision rectifier, 211 450, 451
Power transformer, 4 5 4 -4 6 8 tone-burst, 397 SAR (see Successive approxim ation
Practical ideal voltage source, unipolar tri-wave generator, 163 ADC)
64, 65 window detector, 113, 114 Saturation voltages, 1 6-20
Precision clipper, 208 zero-crossing detector, 111-113 Sawtooth wave generator, 3 1 -3 4 ,
Precision comparator, 104-106 PSR, 271 165-172
Precision full-wave rectifiers Pull-up resistor, 3 0 -3 4 Scale factor, 331, 341
high input impedance, 197 Pulse stretcher, 156 SCC (see Signal conditioning
PSpice sim ulation, 211 Pulse width m odulator, 2, 6 circuits)
with equal resistors, 196 interface to bridge amplifier, 248 SCR, 2, 2 4 -2 6
with grounded sum m ing interface to microcontroller, Second sources, 10
inputs, 202 36, 37 Selection process DAC, 4 2 0 -4 2 2
Precision rectifiers, 188 inverting and non-inverting, Selectivity, 314
ac-to-dc conversion, 200 -2 0 3 2 9 -3 6 Sense term inal, 229
absolute value circuit, 194 PW M (see Pulse width m odulator) Sensitivity
full-wave, 195, 202 resistance bridge, 241
dead-zone circuits, 20 3 -2 0 5 tem perature sensor, 7 1 -7 3
introduction, 188 Quadrants, 333 Sensor
inverting half-wave, 190 Quad voltage comparator, 3 0 -3 5 AD590, 139, 140
linear half-wave rectifier, 189 Quality factor, 314 deriving equation, 72
m ean absolute value, 200, 201 Quantization error, 433 LM335, 7 1 -7 5
peak followers, 198 tem perature, 7 1 -7 5
PSpice sim ulation, 2 0 9 -2 1 2 photoconductive cell, 132, 144
signal polarity separator, 193 Radiant energy, 133, 134 photodiode, 132, 133
Precision sine-wave generator, 175 Rail currents, 4 0 9 -4 1 3 Serial DACs, 4 2 5 -4 2 7
Precision voltage source, REF-02, Ramp generator, 165, 166 Servoamplifier, 142-144
27, 66 Read com m and, 420, 446 Setpoint controller, 100-103
528 Index
Short circuit current measurements Star grounding, 11 Temperature-to-voltage conversion

photoconductive cell, 132 Start conversion, 440 AD590, 139, 140
photo diode, 133 Start up pulse, 368 block diagram, 30
principles, 130 Static charge, 219 bridge circuit, 245
solar cell, 135, 136 Status line, 446 design procedure, 71-75
Short circuit limit, 28 Stereo equalizer octave filters, input-output characteristics, 30
Side bands, 347, 348 318, 319 LM335, 71-75
Side frequencies, 347-350 Stop band, 295,296,319 pulse-width modulator, 29, 33-36
Signal generators, 151-186 Straight binary, 446 thermistor, 243-245
multivibrators, 152-154, 381 Straight line equation, 71-75 Tension, 233
precision tri/square wave, 170-174 Strain, 235 Terminals, 14-18
PSpice simulation, 175-181 Strain gage Testing the AD670, 447
sawtooth, 165-168 application, 241 Thermal effects on bridge
sine, 172-178 bridge-balancing, 238 balance, 237
square, 152, 175 compression, 234 Thermal resistance, 473
triangle, 160, 170-172 dummy gage, 237 Thermal shutdown, 478
unipolar triangle wave, 163 gage factor, 234 Thermistor, 245
\/-to-F converter, 167 introduction, 233 Thermostat, 100
Signal conditioning circuits material, 233 Threshold terminal, 366
design procedure, 74, 75 modulus of elasticity, 242 Time delays, 368
equation, 75 mounting, 235 Timer counter (see Programmable
instrumentation amplifier, 233 resistance bridge, 235-239 timer/counter)
temperature sensors, 139, 140 strain, 234 Timing loop, 36
Signal polarity separator, 193 stress, 234, 242 Timing state, 157
Silicon controlled rectifier, 2, 24-26 temperature compensation, Tone-burst oscillator
Silicon diode, 188 237-240 operation, 375
Sine function operation, 173, 174 tension, 238 PSpice simulation, 397
Sine-to-square-wave converter, 29 unit strain, 235 Touch switch, 381
Sine-wave generator, 173-176 working gage, 237, 238 Transducers
Single-ended output, 16, 17 Stress, 234, 242 AD590, 139, 140
Single pole double throw switch, Strobe terminal, 104-106 grounded, 248
100-102 Stroboscopic flash unit, 24 high current, 249
Single side-band demodulation, Subtractor, 70 high resistance, 249
356 Successive approximation (SAR) in bridge amplifier, 244-249
Single supply operation, 30-34, 66 analog, 441, 442 LM335, 71-75
Slew rate register, 440 microphone, 130
A/D conversion, 447 time, 442 photo conductive cell, 26,
cause, 285 conversion control, 442-446 132, 239
definition, 284 Sum frequencies, 345 photo diode, 133
introduction, 253 Summing amplifier, 55, 56 solar cell, 130-136
limiting sine waves, 285 Superheterodyne, 359 temperature, 74, 139, 243
Slope, 73-75, 407 Suppressed carrier modulation, 352 thermistor, 245
Small outline integrated circuit, 7 Surface mounted technology, 7 Transient protection, 99
Small signal bandwidth, 281-285 Switched gain amplifier, 169 Transient response, 277
Small signal response, 275 Switch programmable timer, 394 Transient response rise time, 108, 277
Small signal unity gain bandwidth, Transit time, 108
277, 278 Transistors, 125-129
Smoke detector, 26, 27 Teleprinter, 128 Transparent, 420
Solar cell, 133-136 Temperature compensation gage, 237 Transverse axis, 234
Solenoid, 128, 129 Temperature measurements Triangle-to-sine wave converter, 208
Sound activated switch, 22-24 AD590, 139, 140 Triangle-wave generator
SPDT switch, 100-102 block, diagram, 30 op amp bipolar, 160-164
Speed control, 384 bridge circuit, 245 precision 166-168, 172
Square root, 342 LM335, 71-75 PSpice simulation, 170-172,
Squaring a number, 334 pulse-width modulator, 29, 33-36 180-183
Square-wave generators thermistor, 244-247 two op amp, 183-185
bipolar, 161, 170 Temperature range code, 9 unipolar, 163, 183-185
multivibrators, 152-154 Temperature sensor Trigger terminal, 366
precision, 170-175 AD590, 139-140 Trigonometric
Standard amplitude modulation, LM335, 70-75 functions, 173
348-351 thermistor, 244-247 identities, 337
Tri-state memory buffer Voltage controlled oscillator, follow and hold, 200
register, 443 166, 377 frequency shifter, 348, 350
Tri-state outputs, 445 Voltage follower, 61 inverting amplifier, 45-47
20 dB/decade, 297 Voltage level detectors level detectors, 21-24
Two’s complement, 402, 446 adjustable reference, 21-24 linear half-wave rectifier,
Two-value power supply, 468 negative and positive level, 22-25 194, 195
Types of ADCs, 405 precision reference, 27 MAV circuit* 201
pulse width modulator, 29-32 modulators, 346, 350
REF-02, level detector applica multivibrator, 152-160
Unipolar triangle wave tion, 27-29, 66 non-inverting amplifier, 60
operation, 163 temperature conversion, 29 one-shot multivibrator, 157
PSpice simulation, 179 zero-crossing, 20, 21 phase angle detection, 338
Unit strain, 235 Voltage measurement, 119-123 phase shifter, 137, 138
Unity gain bandwidth, 277, 278 Voltage offset nulling, 265-267 power supplies, 455, 458, 462
Universal AM receiver, 360 Voltage output DACs, 411-420 precision full-wave rectifier,
Universal high-resistance voltmeter, Voltage reference, 66, 409 195,196
121-123 Voltage reference ICs, 27-29, 66 pulse width modulator, 29-36
Universal radio receiver, 358 Voltage regulators sawtooth wave generator, 31-34,
Universal trigonometric function adjustable, 465-479 164, 166
generator, 173 characteristics, 469-471 sine wave, 177
Unregulated power supply classification, 470 square wave, 154, 160, 161, 164
analysis example, 466 external protection, 472-478 triangle wave, 177
bipolar, 468, 469 headroom, 470, 472 window detector, 109
design example, 464, 465 high current, 473 zero-crossing detectors, 20-22,
for logic circuits, 472, 473 history, 469, 470 90-92
filter capacitor, 457, 464 laboratory type, 478 Wheatstone bridge, 235
model, 459 linear ICs, 473, 474 Wide-band filter, 314
negative, 456, 468 negative, 474 Window detector
percent regulation, 464-467 positive, 475, 478 operation, 108-110
positive, 466, 468 ripple reduction, 472 PSpice simulation, 1 13—115
power transformer, 454-468 Voltage regulation curve, 458, Wire-OR, 388
headroom, 473 459, 467 Working gage, 240
regulation curve, 458-465 Voltage-to-current converters, Working volts dc, 465, 473
ripple voltage, 458-465 120-126 Write command, 420, 446
two-value, 469 Voltage-to-frequency converter, 167 Write only register, 420
Upper cutoff frequency, 281, 312 Voltage-to-high current converter, WVDC (see Working volts dc)
Upper side band, 347 125-J28
Upper threshold voltage, 87-97 Voltmeters, 119-123
UUA41J1 thermistor, 243-248 V'ref XR2240 (see Programmable
comparator voltage, 92-97 timer/counter)
precision tri/square wave,
Vcc, 4 170-174
l/clr, 91-99 V-to-F converter, 167 Zener diode tester, 123, 124
Vsat, 16-23 Zero-crossing detectors
Vestigial side band modulator, 356 V.emp, 32-35 introduction, 20, 21, 29
VH, 87-97 VUTy 89-104, 152-155 with hysteresis, 85-93
Vio, (see Input offset voltage) Zeroing procedure
Virtual ground, 46 bridge circuit, 245
VLSI, 4 Water-level fill control,381 offset voltage, 265-267
VLT, 87-97, 101, 152-153 Waveshapes
Voltage comparator (see absolute value circuits, 194, 195
Comparators) AM comparison, 354, 355
Voltage controlled frequency shifter, dead-zone circuits, 204, 206
166, 376 demodulator, 355
Voltage controlled load current, 555 timer, 372, 374, 376
124-L26 frequency doubler, 334
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Operational Amplifiers and

Linear Integrated Circuits
6th Edition
This best-selling texi presents a clear and interesting approach to

operational amplifiers and linear integrated circuits. The authors
provide many detailed, practical design and analysis examples to
relate theory to the workplace. The Sixth Edition also includes:
Ml
Two chapters on digital-to-analog and analog-to-digital converters.

A new laboratory manual to accompany this text. Experiments
previously relegated to the text are expanded upon and new
J v ' j |
experiments are presented to offer greater flexibility in the laboratory
environment.
Updating of newer ICs to replace older versions found in previous
4 editions.
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Library o f Congress Cataloging-in-Publication Data

Vice President and Publisher: Dave Garza

1-1 Is There Still a Need for Analog Circuitry? 2

1-2 741 General-Purpose Op Amp 4

1-2.3 Input Stage—Differential Amplifier, 6

1-3 Packaging and Pinouts 7

1-4 How to Identify or Order an Op Amp 9

1-5 Second Sources 10

FIRST EXPERIENCES WITH AN OP AMP 13

2-2 Open-Loop Voltage Gain 18

2-3 Zero-Crossing Detectors 20

2-4 Positive- and Negative-Voltage-Level Detectors 21

2-5 Typical Applications of Voltage-Level Detectors 21

2-5.2 Sound-Activated Switch, 22

2-6 Voltage Reference ICs 27

2-7 Signal Processing with Voltage-Level Detectors 29

2-8 Computer Interfacing with Voltage-Level Detectors 32

2-9 A Pulse-Width Modulator Interface to a Microcontroller

INVERTING AND NONINVERTING AMPLIFIERS

3-2 Inverting Adder and Audio Mixer 52

3-4 Inverting Averaging Amplifier 56

3-6 Voltage Follower 61

3-7 The "Ideal" Voltage Source 64

3-8 Noninverting Adder 66

3-11 Designing a Signal Conditioning Circuit

COMPARATORS AND CONTROLS

OP AMPS WITH DIODES

7-2 Precision Rectifiers: The Absolute-Value Circuit 194

7-3 Peak Detectors 198

7-4 AC-to-DC Converter 200

7-5 Dead-Zone Circuits 203

7-6 Precision Clipper 208

DIFFERENTIAL, INSTRUMENTATION, AND BRIDGE AMPLIFIERS

Basic Differential Amplifier 217

Differential versus Single-Input Amplifiers 221

Improving the Basic Differential Amplifier 223

Instrumentation Amplifier 226

Sensing and Measuring with the Instrumentation

The Instrumentation Amplifier as a Signal Conditioning

Measurement of Small Resistance Changes 235

Balancing a Strain-Gage Bridge 238

Increasing Strain-Gage Bridge Output 239

8-12 Basic Bridge Amplifier 243

8-13 Adding Versatility to the Bridge Amplifier 248

DC PERFORMANCE: BIAS, OFFSETS, AND DRIFT

9-4 Effect of Offset Current on Output Voltage 259

9-5 Input Offset Voltage 261

9-6 Input Offset Voltage for the Adder Circuit 264

9-7 Nulling-Out Effect of Offset Voltage and Bias

9-8 Drift 267

AC PERFORMANCE: BANDWIDTH, SLEW RATE, NOISE

10-2 Amplifier Gain and Frequency Response 279

10-3 Slew Rate and Output Voltage 284

10-4 Noise in the Output Voltage 289

10-5 Loop Gain 291

11-2 Introduction to the Butterworth Filter 299

11-4 -60-dB/Decade Low-Pass Butterworth Filter

11-5 High-Pass Butterworth Filters 305

11-6 Introduction to Bandpass Filters 312

11-7 Basic Wideband Filter 315

11-8 Narrowband Bandpass Filters 316

11-9 Notch Filters 319

11-11 Simulation of Active Filter Circuits Using PSpice 322

MODULATING, DEMODULATING, AND FREQUENCY CHANGING