MULTI-STACKED THROUGH-SILICON-VIA EFFECTS ON SIGNAL INTEGRITY AND POWER INTEGRITY FOR

APPLICATION OF 3-DIMENSIONAL STACKED-CHIP-PACKAGE

Jun So Pak, Chunghyun Ryu and Joungho Kim

Paper Number: 2218
Terahertz Interconnection and Package Lab., Dept. of EECS, KAIST, Daejeon, Korea
E-mail) chitoong@eeinfo.kaist.ac.kr
Terahertz Interconnection and Package Laboratory

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Abstract

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We investigate the multi-stacked through-silicon-via (TSV) effects on signal integrity (SI) and power

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integrity (PI) depending on the number of stacked TSVs. A single SG (Signal/Ground)-TSV-pair shows very
small serial inductance (< 30 pH) due to its small height (80 µm), but very large serial resistance (70 mΩ) due

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to its small diameter (~80 µm) and shunt capacitance (> 4 pF) due to its thin SiO2 (0.2 µm) between TSV and

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silicon substrate. In multi-stacked TSV case of high frequency application, SI becomes worse due to its large
resistance and large capacitance, but PI becomes better due to its small inductance and large capacitance.

3D Stacked Chip Package

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TSV (Through Silicon Via)

b
Planar Type Multi-Chip Package (2-D) Definition

Low System Speed & Large Size Package - TSV Æ Through Silicon Via

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- Large Space between Chips (2-D) - Route the electrical signal through all die in the stack,
rather than wire bonding around lower die to the substrate below

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- Shortest interconnection distance
Development of 3-D Stacked Chip Package
Pitch=150㎛

Another Motivations Cu/Sn

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2nd Chip Bump
- To Increase Density: Mobile Application
TSV
- To Increase Electrical Performance Si Substrate

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Shortest Interconnection Length h=90㎛ ∅=75㎛ (ρ=10 Ω•cm)
Best Isolation between Chips 1st Chip
- To Get Heterogeneous Integration in Small Area

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RF + Memory + Logic + Sensor PKG Substrate
Different Substrate
- To Reduce Development Cost

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Advantages

• Short Interconnection
3rd Chip
(Thinned TSV Æ Reduced RC Delays
Substrate) Æ Low Impedance for Power Distribution Network
Under fill Æ Low Power Consumption
Dielectric
2nd Chip Æ Good Heat Dissipation (Shortest Thermal Via)
(Thinned
Substrate) • No Space Limitation for Interconnection
Dielectric Æ High Density Chip Wiring
Under fill
Æ No Limitation of I/O Number
Multi-level
1st Chip
On-chip Interconnect Æ No Limitation of I/O Pitch
SiO2 Æ Small Area Package
Si-Substrate • Simple Interposer
Æ Short Redistribution Interconnection
3-D TSV Stacked Chip Package Æ No Limitation of Vertical Interconnect Number
 3-D Electrical Model of TSV

Structures of SG-TSV-Pair Insertion Loss of SG-TSV-Pair

0.00
0.00
Exposed TSV : 1 µm

S21 Magnitude [dB]

S21 magnitude [dB]
Si Thickness: 80 µm -0.25
-0.25 Large Resistance
Pitc SiO2: 0.2 µm
h: 2 Large Capacitance (Large Slope)
00 µ -0.50
-0.50
m
TSV Height: 82 µm Embedded TSV : 80 µm Large Insertion Loss
-0.75
-0.75
Si R TSV
Si E esis Size
dge tivit : 80 -1.00
-1.00
Len y : 10 Ω µm
Terahertz Interconnection and Package Laboratory

1E8
0.1 1E9
1 1E10
10 3E10
30

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gth: ⋅ cm
1m Frequency
Frequency [Hz]
[GHz]
m

SI (Signal Integrity) of Multi-

Multi-Stacked TSVs
TSVs

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Insertion Loss of Multi-Stacked SG-TSV-Pairs Variation of Eye Diagram depending on Number of Stacked SG-TSV-Pairs

a
0.00
2 Stacked 5 Stacked 10 Stacked

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2 Stacked
Incr citance
S21 Magnitude [dB]

Cap istance

0.5
-0.25 Increased Signal Loss due to Larger Capacitance & Resistance
Increased
ease
Res

5 Stacked
a

0.4
Insertion Loss

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Voltage [V]
d To &

-0.50 0.3
0.4 V
tal

-0.75 10 Stacked 0.2 0.3 V

0.2 V

b
0.1
-1.00
0.0

a
0.1 1 10 30
Frequency [GHz] 200 psec. 200 psec. 200 psec.

PI (Power Integrity) of Multi-

Multi-Stacked TSVs
TSVs

L PSP Impedance of Wire-bonding & TSV

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PSP Impedance of Package Substrate
Inp ut P S P Im p e d a nc e o f P a c ka g e S ub s tra te
onC Package Substrate
o m p a ris o n o f Inp ut P S P Im p e d a nc e
Input PSP Impedance Input PSP Impedance 5E 2
500 5E 2
500
75 pF H
[Ω]

with TSVs with Wire-bondings

[Ω]

1E 2
100 nH 1E 2
100 2.6 n
Impedance [Ohm]

Impedance [Ohm]

1.69

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Impedance
Impedance

1E 1 110
E1
10 75 pF
Power Ground 36 0 p F
Power Ground H
1 1
430 MHz 11 1.8 n

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TSV N × 82 µm Wire-bonding 10.1
E -1 10.1
E -1
1E 7 1E 8 1E 9 3E 9 1E 7 1E 8 1E 9 3E 9
0.01 0.1 1 3 0.01 0.1 1 3
F re q ue nc y [H z ] F re q ue nc y [H z ]
Frequency [GHz] Frequency [GHz]

T
TSV Wire-bonding
φ = 300 µm
φ = 300 µm

Ground Plane pF MHz nH pF MHz nH

Ground Plane
200 µm @ 10 MHz @ 1.5 GHz @ 10 MHz @ 1.5 GHz
Power Plane Power Plane
PKG 75 430 1.69
Package Substrate Package Substrate PKG + 2 Stacked 105 425 1.73 75 375 2.3
(20 mm × 20 mm) (20 mm × 20 mm)
PKG + 5 Stacked 191 445 1.75 75 335 2.5
N = # of Stacked Chips
PKG + 10 Stacked 360 440 1.8 75 320 2.6

Reducing PKG Raising

PSP Impedance Dominant PSP Impedance
Conclusions
ƒ Investigated Multi-Stacked TSV (Through Silicon Via) Effects on SI (Signal Integrity) & PI (Power Integrity)
ƒ To Enhance SI of 3-D TSV Stacked Chip Package, Choose Larger Size TSV and Thicker SiO2 to Reduce Resistance & Capacitance
ƒ To Enhance PI of 3-D TSV Stacked Chip Package, Choose Shorter Length TSV and Thinner SiO2 to Reduce Inductance & Increase
Capacitance