TPS51120
SLUS670C – JULY 2005 – REVISED JANUARY 2015
TPS51120 Dual, Synchronous Step-Down Controller With 100-mA Standby Regulators for
Notebook System Power
1 Features 3 Description
1• 3.3-V and 5-V 100-mA Bootstrapped Standby The TPS51120 is a highly sophisticated dual,
Regulators with Independent Enables synchronous step-down controller. It is a full featured
controller designed to run directly off a three- or four-
• Selectable D-CAP™ Mode Enables Fast cell Li-ion battery and provide high-power and 5-V
Transient Response Less than 100 ns and/or 3.3-V standby regulation for all the
• Selectable Low Ripple Current Mode downstream circuitry in a notebook computer system.
• Less than 1% Internal Reference Accuracy High-current, 100-mA, 5-V or 3.3-V on-board linear
regulators have glitch-free switch over function to
• Selectable PWM-only/Auto-skip Modes SMPS and can be kept alive independently during
• Low-side RDS(on) Loss-less Current Sensing standby state. The pseudo-constant frequency
• RSENSE Accurate Current Sense Option adaptive on-time control scheme supports full range
of current mode operation including simplified loop
• Internal Soft-Start and Integrated VOUT Discharge
compensation, ceramic output capacitors as well as
Transistors seamless transition to reduced frequency operation at
• Integrated 2-V Reference light-load condition. Optional D-CAP mode operation
• Adaptive Gate Drivers with Integrated Boost Diode optimized for SP-CAP or POSCAP output capacitors
allows further reduction of external compensation
• Powergood for Each Channel with Delay Timer
parts. Dynamic UVP supports VIN line sag without
• Fault Disable Mode latch off by hitting 5-V UVP. No negative voltage
• Supply Input Voltage Range: 4.5 V to 28 V appears at output voltage node during UVLO, UVP,
and OCP, OTP or loss of VIN.
2 Applications The TPS51120 32-pin QFN package is specified from
Notebook Computers System Bus and I/O –40°C to 85°C ambient temperature.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
TPS51120 VQFN (32) 5.00 mm × 5.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
VO1
VFB1
GND
COMP2
VO2
VFB2
EN_LDO5 9 32
P_GOOD2 EN5 SKIPSEL P_GOOD1
VBAT
11 PGOOD2 PGOOD1 30
VREG5
V5FILT
16 25
PGND2
CS2
CS1
VIN
17 18 19 20 21 22 23 24
− VO1_GND
VO2_GND −
PGND1
R22
PGND2 3.3 kΩ R50
R12
5.1Ω
3.6 kΩ
VBAT
C30
C30 NA
C51 C50
10 µF 1 µF 10 µF
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS51120
SLUS670C – JULY 2005 – REVISED JANUARY 2015 www.ti.com
Table of Contents
1 Features .................................................................. 1 7.4 Device Functional Modes........................................ 22
2 Applications ........................................................... 1 7.5 Programming........................................................... 27
3 Description ............................................................. 1 8 Application and Implementation ........................ 28
4 Revision History..................................................... 2 8.1 Application Information............................................ 28
8.2 Typical Application ................................................. 28
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 5 9 Power Supply Recommendations...................... 31
6.1 Absolute Maximum Ratings ...................................... 5 10 Layout................................................................... 31
6.2 Recommended Operating Conditions....................... 5 10.1 Layout Guidelines ................................................. 31
6.3 Thermal Information .................................................. 6 10.2 Layout Example .................................................... 32
6.4 Electrical Characteristics.......................................... 6 11 Device and Documentation Support ................. 33
6.5 Typical Characteristics ............................................ 10 11.1 Trademarks ........................................................... 33
7 Detailed Description ............................................ 15 11.2 Electrostatic Discharge Caution ............................ 33
7.1 Overview ................................................................. 15 11.3 Glossary ................................................................ 33
7.2 Functional Block Diagram ....................................... 16 12 Mechanical, Packaging, and Orderable
7.3 Feature Description................................................. 17 Information ........................................................... 33
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
• Added Pin Configuration and Functions section, Feature Description section, Device Functional Modes, Application
and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section ............................................................... 1
RHB Package
32-Pin VQFN
Bottom View
COMP1
COMP2
VREF2
VFB1
VFB2
GND
VO1
VO2
1 2 3 4 5 6 7 8
SKIPSEL 32 9 EN5
TONSEL 31 10 EN3
PGOOD1 30 11 PGOOD2
EN1 29 12 EN2
VBST1 28 13 VBST2
DRVH1 27 14 DRVH2
LL1 26 15
LL2
DRVL1 25 16
24 23 22 21 20 19 18 17 DRVL2
PGND1
PGND2
VREG5
VREG3
CS1
CS2
V5FILT
VIN
Pin Functions
PIN
I/O DESCRIPTION
NAME NO.
COMP1 2 O Loop compensation pin (error amplifier output). Connect RC from this pin to GND for proper loop
COMP2 7 O compensation with current mode operation. Tie this pin to V5FILT for D-CAP mode operation.
CS1 23 I Current sense comparator input (-) for resistor sensing scheme. Or, overcurrent trip setting input for
CS2 18 I RDS(on) current sense scheme if connected to V5FILT through the threshold setting resistor.
DRVH1 27 O High-side MOSFET gate drive output. Source 3.5 Ω, sink 1.5 Ω, LL-node referenced floating driver. Drive
DRVH2 14 O voltage corresponds to VBST to LL voltage.
DRVL1 25 O Rectifying (low-side) MOSFET gate drive output. Source 3.5 Ω, sink 1.5 Ω, PGND referenced driver. Drive
DRVL2 16 O voltage is VREG5 voltage.
EN1 29 I Channel 1 and Channel 2 SMPS enable pins. Connect to 5 V to turn on with internal 3-ms soft-start.
Slower soft-start is possible by applying an external capacitor from each of these pins to ground to
EN2 12 I program ramp rate.
VREG3, 3.3-V low dropout linear regulator enable pin. Connect to GND to disable. Float or tie to enabled
EN3 10 I
VREG5 to turn on the regulator.
VREG5, 5-V low dropout linear regulator enable pin. Connect to GND to disable. Float or tie to VBAT to
EN5 9 I
turn on the regulator.
GND 5 I Signal ground pin.
LL1 26 I/O High-side MOSFET gate driver return. Also serve as current sense comparator input (-) for RDS(on)
LL2 15 I/O sensing, and input voltage monitor for on-time control circuitry
PGND1 24 I/O Ground return for rectifying MOSFET gate driver. Connect PGND2, PGND1 and GND strongly together
near the source of the rectifying FET or the GND connection of the current sense resistor. Also serve as
PGND2 17 I/O current sense comparator input (+).
PGOOD1 30 O Power-good window comparator open drain output. Pull up with resistor to V5FILT or appropriate signal
voltage. Current capability is 5-mA. PGOOD goes high 1-ms after VFB is within specified limits. Power
PGOOD2 11 O bad (terminal goes low) is within 10 μs.
SKIPSEL 32 I Skip and fault mode selection pin. Refer to Table 5
TONSEL 31 I On-time selection pin. Refer to Table 1 and Table 5.
V5FILT 20 I 5-V supply input for the entire control circuit. Should be provided from VREG5 via RC filter.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range unless otherwise noted (1)
MIN MAX UNIT
VBST1, VBST2 –0.3 36
VBST1, VBST2 wrt LL –0.3 6
Input voltage VIN, EN5 –0.3 30 V
SKIPSEL, TONSEL, EN1, EN2, CS1, CS2,
–0.3 6
V5FILT, VFB1, VFB2, EN3, VO1, VO2
DRVH1, DRVH2 –1 36
DRVH1, DRVH2 (wrt LL) –0.3 6
LL1, LL2 –1 30
Output voltage V
VREF2, VREG3, VREG5, PGOOD1, PGOOD2,
–0.3 6
DRVL1, DRVL2, COMP1, COMP2
PGND1, PGND2 –0.3 0.3
VREF2 1
Source/sink current VBST 100 mA
VREG5, VREG3 (source only) 200
TA Operating ambient temperature –40 85
TJ Junction temperature –40 125
°C
Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds 255
Tstg Storage temperature –55 150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage
values are with respect to the network ground terminal unless otherwise noted.
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
900 900
600 600
500 500
IINNOCAP= D−CAP Mode IINNOCAP= D−CAP Mode
400 400
300 300
200 200
100 100
0 0
−50 0 50 100 150 5 10 15 20 25
TJ − Junction Temperature − °C VIN − VIN Input Voltage − V
Figure 1. VIN Supply Current vs Junction Temperature Figure 2. VIN Supply Current vs Input Voltage
140 140
120 120
IIN532 − Standby Current − µA
80 80
60 60
40 40
20 20
0 0
−50 0 50 100 150 5 10 15 20 25
TJ − Junction Temperature − °C VIN − VIN Input Voltage − V
Figure 3. VIN Standby Current vs Junction Temperature Figure 4. VIN Standby Current vs Input Voltage
20 20
18 18
IIN(SHDN) − Shutdown Current − µA
IIN(SHDN) − Shutdown Current − µA
16 16
14 14
12 12
10 10
8 8
6 6
4 4
2 2
0 0
−50 0 50 100 150 5 10 15 20 25
TJ − Junction Temperature − °C VIN − VIN Input Voltage − V
Figure 5. VIN Shutdown Current vs Junction Temperature Figure 6. VIN Shutdown Current vs Input Voltage
14
12
10
0.3
0.2
6
4
0.1
AUTO−SKIP 2
280 kHz (CH1)
430 kHz (CH2)
0 0
8 12 16 20 24 −50 0 50 100 150
VIN − VIN Input Voltage − V TJ − Junction Temperature − °C
Figure 7. No-Load Battery Current vs Input Voltage Figure 8. Current Sense Current vs Junction Temperature
600 600
TONSEL = GND CH2 TONSEL = 2 V
500 500
CH2
400 400
CH1
300 300
CH1
200 200
100 100
0 0
6 10 14 18 24 28 6 10 14 18 24 28
VIN − VIN Input Voltage − V VIN − VIN Input Voltage − V
Figure 9. Switching Frequency vs Input Voltage Figure 10. Switching Frequency vs Input Voltage
400 400
TONSEL = FLOAT TONSEL = 5 V
350 350
fSW − Switching Frequency − kHz
CH2
fSW − Switching Frequency − kHz
300 300
CH2
250 250
200 200
CH1 CH1
150 150
100 100
50 50
0 0
6 10 14 18 24 28 6 10 14 18 24 28
VIN − VIN Input Voltage − V VIN − VIN Input Voltage − V
Figure 11. Switching Frequency vs Input Voltage Figure 12. Switching Frequency vs Input Voltage
CH2
100 100
0 0
0.001 0.01 0.1 1 10 0.001 0.01 0.1 1 10
IOUT − Output Current − A IOUT − Output Current − A
Figure 13. Switching Frequency vs Output Current Figure 14. Switching Frequency vs Output Current
400 400
TONSEL = FLOAT TONSEL = 5 V
CH2 Auto−skip
200 200
CH1−PWM Only
CH1−PWM Only
100 100
Figure 15. Switching Frequency vs Output Current Figure 16. Switching Frequency vs Output Current
150 5.100
140
VOVP, VUVP − OVP/UVP Threshold − %
130
120 OVP
5.050
100
90
80
5.000
70
60 UVP
50
0 4.950
−50 0 50 100 0 20 40 60 80 100
TJ − Junction Temperature − °C IVREG5 − VREG5 Output Current − mA
Figure 17. OVP/UVP Threshold Voltage vs Junction Figure 18. VREG5 Output Voltage vs Output Current
Temperature
3.320 2.015
VREG3 − VREG3 Output Voltage − V
2.005
3.280
2.000
3.260
1.995
3.240
1.990
3.220 1.985
3.200 1.980
0 20 40 60 80 100 −100 −80 −60 −40 −20 0 20 40 60 80 100
IVREG5 − VREG3 Output Current − mA IREF2 − VREF2 Output Current − µA
Figure 19. VREG3 Output Voltage vs Output Current Figure 20. VREF2 Output Voltage vs Output Current
5.050 3.390
PWM Only
PWM Only
VOUT1 − 5-V Output Voltage − V
5.000 3.330
Auto−skip
Auto−skip
4.975 3.300
4.950 3.270
0.001 0.01 0.1 1 10 0.001 0.01 0.1 1
IOUT1 − 5-V Output Current − A IOUT2 − 3.3-V Output Current − A
Figure 21. 5-V Output Voltage vs Output Current Figure 22. 3.3-V Output Voltage vs Output Current
5.050 3.32
3.32
VOUT2 − 3.3-V Output Voltage − V
VOUT1 − 5-V Output Voltage − V
5.025
3.31
5.000 3.33
IO = 6 A IO = 6 A
3.30
4.975
IO = 0 A 3.28 IO = 0 A
4.950 3.27
6 8 10 12 14 16 18 20 22 24 26 6 8 10 12 14 16 18 20 22 24 26
VIN − VIN Input Voltage − V VIN − VIN Input Voltage − V
Figure 23. 5-V Output Voltage vs Input Voltage Figure 24. 3.3-V Output Voltage vs Input Voltage
80 80
VIN = 8 V VIN = 8 V
η − Efficiency − %
η − Efficiency − %
VIN = 12 V
VIN = 12 V VIN = 8 V VIN = 8 V
60 60
VIN = 20 V
VIN = 20 V
40 40 VIN = 12 V
VIN = 12 V
20 20 VIN = 20 V
Figure 25. 5-V Efficiency vs Output Current Figure 26. 3.3-V Efficiency vs Output Current
7 Detailed Description
7.1 Overview
The TPS51120 is a highly sophisticated dual synchronous buck controller targeted for notebook I/O and system
bus supply solutions. It support both D-CAP mode and current mode. With D-CAP control mode implemented,
compensation network can be removed. Besides, the fast transient response also reduced the output
capacitance. In case very low output ripple voltage needed, current mode can be implemented with simplified
loop compensation and ceramic output capacitors.
1
ǒV IN * V OUTǓ V OUT
I OUT(LL) +
2 L f V IN (1)
where f is the PWM switching frequency which is determined by TONSEL pin. Switching frequency versus output
current in the light load condition is a function of L, f, VIN and VOUT, but it decreases almost proportional to the
output current from the IOUT(LL) given in Equation 1.
7.3.10 Soft-Start
The TPS51120 has an internal 3-ms voltage-servo soft start for each channel. When the EN1 or EN2 pin
exceeds 0.9 V, an internal DAC begins ramping up the reference voltage. Smooth control of the output voltage
during start up is maintained. However, if a slower soft-start is required, an external capacitor may be tied from
the EN1 or EN2 pin to GND. In this case, the TPS51120 charges the external capacitor with the integrated 2-μA
current source. The lower of either the EN voltage slew rate or the internal soft start slew rate dominates the
start-up ramp. In addition, if tracking discharge is required, the EN pin can be used to control the output voltage
discharge smoothly. An approximate value for the soft start reference voltage as a function of EN voltage is
VSSREF = (VENX – 0.9)/1.5 < 1 V. At the beginning of soft-start period, the rectifying MOSFET maintains an off
state until the top MOSFET is turned on for at least once. This prevents high negative current to flow back from
the output capacitor in the event of output capacitor pre-charged condition.
7.3.11 Soft-Stop
Discharge mode or ‘Soft Stop’ is always on during Faults or Disable. In this mode, an event that would cause the
switcher to be turned off (EN1 or EN2 low, OVP, UVP, UVLO) causes the output to be discharged through 10-Ω
transistor inside the VO terminal. The external rectifying MOSFET is not turned on for the soft off operation to
avoid a chance to cause negative voltage at the output. Soft-stop time constant is a function of the output
capacitance and the resistance of the discharge transistor. This discharge ensures that, upon restart, the
regulated voltage always starts from zero volts. In case a SMPS is restarted before discharge completion, soft-
stop is terminated and the switching resumes after the reference level comes back to the remaining output
voltage.
(1) Because of Switch-over, the 5-V switcher MUST be turned off with the LDO in order to shut down the device. EN5 does NOT function as
a master DISABLE.
(2) Forcing VREF2 output to ground disables SMPS1 and SMPS2 without latch.
Copyright © 2005–2015, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Links: TPS51120
TPS51120
SLUS670C – JULY 2005 – REVISED JANUARY 2015 www.ti.com
C23 C13
180 pF 220 pF
C31
1 nF GND
8 7 6 5 4 3 2 1
V5FILT GND V5FILT
COMP2
COMP1
VREF2
VO2
VFB2
VFB1
VO1
GND
EN_LDO5 9 32
EN5 SKIPSEL
R21 R11
100 kΩ EN_LDO3 10 EN3 TONSEL 31
PowerPad 12 mΩ
GND
13 VBST2 VBST1 28
Q3 C21 C11 Q1
L2 L1
IRF7821 0.1 μF 0.1 μF IRF7821
1.2 μH 2.2 μH
14 DRVH2 DRVH1 27
VO2 VO1
+ +
1.5 V/6 A 1.8 V/6 A
15 LL2 LL1 26
Q4 20 mF
IRF7832 DRVL2 Q2
DRVL1 IRF7832
PGND1
VREG3
VREG5
V5FILT
16 25
PGND2
CS2
CS1
VIN
20 μF
C1B
C2A C2B 17 18 19 20 21 22 23 24 EEFUE0E221R
EEFUE0E221R EEFUE0E221R
R50
5.1 Ω VBAT
R20 R10
12 mΩ 12 mΩ
VO2_GND − C30 C50 − VO1_GND
10 μF C51 10 μF C1A
1 μF EEFUE0E221R
PGND2 PGND1
Figure 28. Current Mode, External 1.8-V / 6-A, 1.5-V / 6-A, RSENSE Sensing
f0 + 1 R2 Gm RC + 1 1.0 Gm R C
2p R1 ) R2 CO RS 2p VOUT CO RS (11)
Based on small signal analysis above, the external components can be selected by following manner.
1. Choose the inductor.The inductance value should be determined to give the ripple current of approximately
1/4 to 1/2 of maximum output current.
1
ǒVIN(max) * VOUTǓ VOUT
2
ǒV IN(max) * V OUTǓ V OUT
L+ +
I IND(ripple) f VIN(max) I OUT(max) f V IN(max)
(12)
The inductor also needs to have low DCR to achieve good efficiency, as well as enough room above peak
inductor current before saturation. The peak inductor current can be estimated in Equation 13.
V5FILT
C31
1 nF
COMP1
VREF2
VO1
VFB1
GND
COMP2
VO2
VFB2
EN_LDO5 9 32
P_GOOD2 EN5 SKIPSEL P_GOOD1
VBAT
11 PGOOD2 PGOOD1 30
PGND1
VREG3
VREG5
V5FILT
16 25
PGND2
CS2
CS1
VIN
17 18 19 20 21 22 23 24
− VO1_GND
VO2_GND −
PGND1
R22
PGND2 3.3 kΩ R50
R12
5.1Ω
3.6 kΩ
VBAT
C30
C30 NA
C51 C50
10 µF 1 µF 10 µF
Figure 30. D-Cap Mode, Fixed 5-V / 6-A, 3.3-V/6-A, RDS(on) Sensing
The VO voltage is compare with internal reference voltage after divider resistors (Internal resistor mode. For
adjustable mode, the comparison is directly at VFB). The PWM comparator determines the timing to turn on top
MOSFET. The gain and speed of the comparator is high enough to keep the voltage at the beginning of each on
cycle (or the end of off cycle) substantially constant. The DC output voltage may have line regulation due to
ripple amplitude that slightly increases as the input voltage increase.
For the loop stability, the 0-dB frequency, f0, defined below need to be lower than 1/3 of the switching frequency.
1 f
f0 + v SW
2p ESR CO 3 (19)
7.5 Programming
The TPS51120 has varieties of configurations choice. It is important to tailor appropriately with regard to the
system design requirements. Table below shows programming table for the control scheme selection, frequency
selection, output voltage selection and skip selection. Faults-off disables UVP, OVP and UVLO. This is mainly
intended for debugging purpose. Enable states and possible connections for the LDO’s EN3, EN5 pins and
SMPS’s EN1, EN2 pins are also shown.
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
COMP1
VREF2
VO1
VFB1
GND
COMP2
VO2
VFB2
EN_LDO5 9 32
P_GOOD2 EN5 SKIPSEL P_GOOD1
VBAT
11 PGOOD2 PGOOD1 30
VREG5
V5FILT
16 25
PGND2
CS2
CS1
VIN
17 18 19 20 21 22 23 24
− VO1_GND
VO2_GND −
PGND1
R22
PGND2 3.3 kΩ R50
R12
5.1Ω
3.6 kΩ
VBAT
C30
C30 NA
C51 C50
10 µF 1 µF 10 µF
Figure 32. D-Cap Mode, Fixed 5-V / 6-A, 3.3-V/6-A, RDS(on) Sensing
Figure 33. 5-V Load Transient Response Figure 34. 3.3-V Load Transient Response
VO1 (5 V/div)
VO2 (5 V/div)
Figure 39. 5-V Soft-Stop Waveforms Figure 40. 3.3-V Soft-Stop Waveforms
10 Layout
VOUT1
OUTPUT
INDUCTOR
OUTPUT
CAPACITOR
LL1
GND
D
S
S
ROUTE ON
OPPOSITE
D
S
S
SIDE
D
S
S
D
D
G
G
DRVL1
VBST1
DRVH1
LL1
PGOOD1
EN1
SKIPSEL
TONSEL
VO1 PGND1
COMP1 CS1
VIN
VFB1 VIN
INPUT
CAPACITOR
VREF2
SGND
VREG5
GND VIN
GND V5FILT
VFB2 VREG3
SGND
COMP2 CS2
VO2
PGOOD2
PGND2
DRVH2
DRVL2
VBST2
EN5
EN3
EN2
LL2
V5FILT
D
S
S
CONNECTED
TO POWER
D
D
S
S
GND ON
INTERNAL OR
D
D
S
S
BOTTOM
LAYER GND
D
D
G
OUTPUT LL2
CAPACITOR
VOUT2 OUTPUT
INDUCTOR
11.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
www.ti.com 5-Nov-2014
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
TPS51120RHBR ACTIVE VQFN RHB 32 3000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS
& no Sb/Br) 51120
TPS51120RHBT ACTIVE VQFN RHB 32 250 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS
& no Sb/Br) 51120
TPS51120RHBTG4 ACTIVE VQFN RHB 32 250 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS
& no Sb/Br) 51120
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
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PACKAGE MATERIALS INFORMATION
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Pack Materials-Page 2
GENERIC PACKAGE VIEW
RHB 32 VQFN - 1 mm max height
5 x 5, 0.5 mm pitch PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224745/A
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PACKAGE OUTLINE
RHB0032E SCALE 3.000
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
5.1 B
A
4.9
5.1
4.9
C
1 MAX
SEATING PLANE
0.05
0.00 0.08 C
2X 3.5
3.45 0.1 (0.2) TYP
9 16 EXPOSED
THERMAL PAD
28X 0.5
8
17
2X SYMM
33
3.5
0.3
32X
0.2
24 0.1 C A B
1
0.05 C
32 25
PIN 1 ID SYMM
(OPTIONAL) 0.5
32X
0.3
4223442/A 11/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RHB0032E VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
( 3.45)
SYMM
32 25
32X (0.6)
1 24
32X (0.25)
(1.475)
28X (0.5)
33 SYMM
(4.8)
( 0.2) TYP
VIA
8 17
(R0.05)
TYP
9 16
(1.475)
(4.8)
SOLDER MASK
METAL OPENING
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RHB0032E VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4X ( 1.49)
(R0.05) TYP (0.845)
32 25
32X (0.6)
1 24
32X (0.25)
28X (0.5)
(0.845)
SYMM
33
(4.8)
8 17
METAL
TYP
9 16
SYMM
(4.8)
4223442/A 11/2016
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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