8085 Architecture: Microcomputer, Microprocessors & Microcontroller Inside The Microprocessor

8/13/2019
Syllabus
8085 Architecture
Dr. Ashok Kherodia
IIIT Kota
Dr. Ashok Kherodia (ECT-201)
Microcomputer, Microprocessors &

Inside the Microprocessor
Microcontroller

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Architecture of Intel 8085 Microprocessor INTEL 8085 Pin Configuration
Dr. Ashok Kherodia (ECT-201) Dr. Ashok Kherodia (ECT-201)
 Microprocessor consists of:

 ALU: performs data processing function.
 Registers: provide storage internal to CPU.
 Timing & Control unit: control microprocessor
operations.
 Address and Data bus
 Interrupts
 Serial I/O control
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Arithmetic Logic Unit Registers of 8085:

 The computing functions on data (arithmetic and logical)  The 8085 have six general-purpose registers to store 8-bit data
performed here. during program execution.
 Have the arithmetic & logic circuits, the accumulator which is part  These registers are identified as B, C, D, E, H, and L.They can be
of every arithmetic & logic operation. combined as register pairs-BC, DE, and HL to perform 16-bit
 The ALU also includes a temporary register used for holding data operations.
temporarily during the execution of the operation. This temporary
register is not accessible by the programmer. Accumulator (A):
 The accumulator is an 8-bit register that is part of the
Control Unit arithmetic/logic unit (ALU).
 Provides the necessary timing and control signals to all the  This register is used to store 8-bit data and to perform arithmetic
operations in microprocessor and logical operations.
 Control the flow of data between MP and peripherals including  The result of an operation is stored in the accumulator.
memory
Flags  Sign Flag (S): After execution of any arithmetic and logical
operation, if D7 of the result is 1, the sign flag is set. Otherwise it is
 The ALU includes five flip-flops that are set or reset according to reset. D7 is reserved for indicating the sign; the remaining is the
the result of an operation in the accumulator and registers. magnitude of number. If D7 is 1, the number will be viewed as
 The microprocessor uses the flags for testing the data conditions for negative number. If D7 is 0, the number will be viewed as positive
decision making. number.
 They are Zero (Z), Carry (CY), Sign (S), Parity (P), and Auxiliary  Zero Flag (z): If the result of arithmetic and logical operation is
Carry (AC) flags. The most commonly used flags are Sign, Zero, and zero, then zero flag is set otherwise it is reset.
Carry.  Auxiliary Carry Flag (AC): If D3 generates any carry when doing
any arithmetic and logical operation, this flag is set. Otherwise it is
reset.
 Parity Flag (P): If the result of arithmetic and logical operation
D7 D6 D5 D4 D3 D2 D1 D0 contains even number of 1's then this flag will be set and if it is odd
S Z X AC X P X CY
number of 1's it will be reset.
 Carry Flag (CY): If any arithmetic and logical operation result any
carry then carry flag is set otherwise it is reset.
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Program Counter (PC) Program Status Word
 This 16-bit register is used to sequence the execution of

instructions. It is a memory pointer.
 The function of the program counter is to point to the memory
address of the next instruction to be executed.
 When an opcode is being fetched, the program counter is
incremented by one to point to the next memory location.
Non Programmable Registers
Stack Pointer (SP)
 Instruction Register & Decoder
 The stack pointer is also a 16-bit register used as a memory pointer.  Instruction is stored in IR after fetched by processor
 It points to a memory location in R/W memory, called the stack  Decoder decodes instruction in IR
The beginning of the stack is defined by loading a 16-bit address in
the stack pointer (register).  Internal Clock generator
 Worked in LIFO fashion.  3.125 MHz internally
 6.25 MHz externally
The Address and Data Busses The 8085 Bus Structure
 The address bus has 8 signal lines A8 – A15 which are

unidirectional.
 The other 8 address bits are multiplexed (time shared) with
the 8 data bits.
 The bits AD0 – AD7 are bi-directional and serve dual
purpose as A0 – A7 (address) and D0 – D7 (data) at the
same time.
 During the execution of the instruction, these lines carry
the address bits during the early part, then during the
later part of the execution, they carry the 8 data bits.
 To separate the address from the data: A latch used to save
the value before the function of the bits changes.
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De-multiplexing AD7-AD0 De-multiplexing AD7-AD0

8085
A15-A8
 ALE is a positive going pulse during T1, to latch the address.

ALE
 When ALE goes low, the address is saved and the AD7– AD0
AD7-AD0
Latch
A7-A0 lines can be used for their purpose as the bi-directional data lines.
 The address AD7 – AD0 is connected as inputs to the latch
D7- D0 74LS373.
 The high order bits of the address remain on the bus for three clock  The ALE signal is connected to the enable (G) pin of the latch
periods. However, the low order bits remain for only one clock period and the OC – Output control – of the latch is grounded
and they would be lost if they are not saved externally.
 To make sure we have the entire address for the full three clock cycles, an
external latch save the value of AD7– AD0 when it is carrying the
address bits. We use the ALE signal to enable this latch.
De-multiplexing AD7-AD0 8085 Demultiplexed Address and Data bus with Control signals
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Some Definitions
The Overall Picture
Microprocessor performs task in following manner:
 Fetch
A15- A10 Chip Selection
Circuit
 Decode
 Execute
8085
A15-A8 CS
 Instruction Cycle(IC): The time required to complete the

ALE
A9-A0 1K Byte
execution of an instruction.
AD7-AD0 Latch
A7- A0 Memor
y Chip
 The 8085 IC consists of one to six machine cycles (one to six
operations).
WR RD IO/M D7- D0  Machine Cycle: The time required to complete the execution of
RD WR
an instruction of accessing memory, I/O, or acknowledging an
external request. This cycle may consists of three to six T-states or
clock cycle.
 T-state: It is one subdivision of the operation performed in one
Dr. Ashok Kherodia (ECT-201) clock period.
Dr. Ashok One clock cycle is known as T-state.
Kherodia (ECT-201)
Fetch, Decode, Execute cycle
IC = FC + EC
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Operation Types in a Microprocessor Microprocessor Initiated operations

Memory Read
Three types of operations:
Memory Write
Microprocessor Initiated operations
I/O Read (Get data from an input device)
Internal operations
I/O write (send data to an output device)
Peripheral initiated operations
All the operations are part of the communication between the MPU and
peripheral device (including memory):
 Step 1: Identify the peripheral or memory by address(Address bus)
 Step 2: Transfer binary information (data and instructions) (Data bus)
 Step 3: Provide timing and synchronization signals (Control bus)
Memory Read Operation

Data Flow from Memory to the MPU
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 Internal Data Operations Externally Initiated Operations

External devices can initiate one of the following operations:
 Store 8-bit data Reset:
 Perform arithmetic and logical operations  All operations are stopped and the program counter is reset to 0000.
 Test for conditions Interrupt:
 Sequencing the execution of Instructions  The MP operations are interrupted and the MP executes the interrupt service
 Storing the data temporarily in the defined R/W memory locations routine.
called the Stack  This ISR handles the interrupt, perform the necessary operations. Then the MP
returns to its previous operations and continues.
Ready:
 This 8085 pin is used by external devices to stop the 8085 until they catch up (to
communicate with slower devices). Till Ready signal is low, the 8085 will be in wait
state.
Hold:
 This 8085 pin is used by external devices to have control of the 8085 buses.
 When the HOLD signal is activated by an external device, the 8085 stops executing
instructions and stops using the buses.
 This allows external devices to control the information on buses, example: DMA
Opcode Fetch Cycle

8085 Machine Cycle
The first machine cycle of every instruction is opcode fetch which decides
the nature of instruction to be executed.
 The processor places the contents of program counter on the address
line and reads the opcode of the instruction.
 The length of this machine cycle varies from 4T to 6T states per
instruction.
 Step I: In T1 state, the 8085 places the contents of program counter (PC)
on the address bus. The higher order byte of the PC is placed on the A8-
A15 lines. The lower order byte of the PC is placed on the AD0-AD7
lines which stays on only during T1. The ALE signal is activated in this
T1 state and latch the lower order of address byte before it disappears
from AD0-AD7 lines.
 In T1, IO/M = 0, S1= 1 and S0=1 indicates that this is memory read
operation.
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Opcode Fetch Cycle Opcode Fetch Cycle

Step II: In T2, low-order address disappears from AD0-AD7 lines
(however, A0-A7 remain available as they were latched during T1). In T2,
8085 sends RD signal low to enable the addressed memory location. The
memory device then places the contents of addressed memory location on
the data bus AD0-AD7.
Step III: In T3, 8085 loads the data from the data bus in its instruction
register and raises RD to high which disables the memory.
Step IV: In T4, microprocessor decodes the opcode, and on the basis of the
instruction received, it decides whether to enter state T5 or to enter state T1
of the next machine cycle. One byte instructions those operate on 8 bit
operand are executed in T4.
Example: MOV A,B, ANA D, ADD B, INR L, DCR C, RAL etc.
Step V: States T5 and T6 are used for internal operations required by the
instruction. During T5 and T6, 8085 performs stack write, internal 16 bit
and conditional return operations depending upon the type of instructions.
One byte instructions those operate on sixteen bit data (16 bit operand) are
executed inKherodia
Dr. Ashok T5 and T6. Example: DCX H, PCHL, INX H etc.
(ECT-201) Dr. Ashok Kherodia (ECT-201)
Data (opcode) flow from memory to microprocessor Memory Read Cycle
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Data flow from memory to microprocessor Memory Write Cycle
Data flow from microprocessor to memory I/O Read Cycle
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Data flow from input device to microprocessor I/O Write Cycle
Data flow from microprocessor to output device
8085 Instructions
Dr. Ashok Kherodia
IIIT Kota
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Instruction Format and Addressing Modes

 An instruction is a binary pattern designed inside a Each Instruction has two parts:
microprocessor to perform a specific function. The first part is called “OPCODE” which tells the task or the operation to
be performed.
 The entire group of instructions that a microprocessor The second part is called the “OPERAND” which tells the data to be
operated on. Example: MVI B,08H
supports is called Instruction Set . Determines
what functions the microprocessor can perform Addressing modes is the technique used to fetch the desired operand
during the execution of an instruction. Instructions can be categorized
 8085 has 246 instructions, 74 Opcodes. according to their method of addressing the hardware register and/or
memory.
 Each instruction is represented by an 8-bit binary
value. The 8085 MPU uses five addressing modes:
1. Immediate addressing mode
2. Register addressing mode
 These 8-bits of binary value is called Op-Code or 3. Direct addressing mode
Instruction Byte. 4. Register Indirect Addressing mode
5. Implied or Implicit addressing mode
Immediate Addressing Mode:

 Data immediately follow the opcode in the program memory. Register Indirect Addressing Mode:
 The operand comes from the next byte in program memory.  The instructions reference memory using the contents of a register pair.
Examples: ADI 05H , MVI A, 12 H  Instructions specifies register pair containing address, where the data is
located.
Register Addressing Mode: Examples: MOV M,C and ADD M
 The operand is retrieved from internal CPU register. The instruction MOV M,C moves the contents of the C register into the
 The data is provided through the registers. memory address stored in the H and L register pair.
Examples: MOV A,D, ADD B
Implied Addressing Mode:
Direct Addressing Mode:  Certain instructions is implied by the instructions function.
 Used to accept data from outside device to store in the accumulator or  Not a real addressing mode.
send the data stored in the accumulator to the outside device. Example: STC deals only with the carry flag.
 In this type address of data is directly provided as part of the HLT: terminate the program
instruction. CMA: complement accumulator
Examples: LDA 2050H, IN 25H, OUT 62H
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Instruction size Instruction Types
Depending on the operand type, the instruction may have different

sizes.
It will occupy a different number of memory bytes. Typically, all
instructions occupy one byte only. The exception is any instruction
that contains immediate data or a memory address.
 Instructions that include immediate data use two bytes: one for
opcode and another for the 8 bit data.
 Instructions that include a memory address occupy three bytes:

one for opcode and the other two for the 16-bit address.
Instruction Types Instruction Types
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Data TransferInstructions
Classification of InstructionSet
 Data Transfer Instruction  These instructions move data between registers, or

between memory and registers.
 Arithmetic Instructions
 These instructions copy data from source to
 Logical Instructions destination.
 Branching Instructions
 While copying, the contents of source are not
 Machine Control Instructions modified.
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Data TransferInstructions Data TransferInstructions
This is 3 byte instruction; the second byte

specifies the lower–order address and the third
byte specifies the contents of the high-order address.
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This is 3 byte instruction; the second byte

specifies the lower–order address and the third
byte specifies the contents of the high-order address.
Dr. Ashok Kherodia (ECT-201) This Dr.

is Ashok
the Kherodia
only instruction
(ECT-201) that can load a 16-bit address in stack pointer register
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This instruction is equivalent to a 1-byte unconditional jump instruction.

A program sequence can be changed to any location by simply loading the H and
L register with the appropriate address and by using this instruction.
Instruction Bytes M-cycle T-states Flags Example

PCHL 1 1 6 None PCHL
S
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ArithmeticInstructions Addition
 These instructions perform the operations like:  Any 8-bit number, or the contents of register, or the
contents of memory location can be added to the
 Addition contents of accumulator.
 Subtract  The result (sum) is stored in the accumulator.
 No two other 8-bit registers can be added directly.

 Increment
 Example: The contents of register B cannot be added
 Decrement directly to the contents of register C.
Subtraction Increment / Decrement
 Any 8-bit number, or the contents of register, or the  The 8-bit contents of a register or a memory location can
contents of memory location can be subtracted from the be incremented or decremented by 1.
contents of accumulator.
 The 16-bit contents of a register pair can be
 The result is stored in the accumulator. incremented or decremented by 1.
 Subtraction is performed in 2’s complement form.  Increment or decrement can be performed on any
register or a memory location.
 If the result is negative, it is stored in 2’s complement form.
 No two other 8-bit registers can be subtracted directly.
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ArithmeticInstructions
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ArithmeticInstructions ArithmeticInstructions
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LogicalInstructions
 These instructions perform logical operations on data
stored in registers, memory and status flags.
 The logical operations are:
 AND
 OR
 XOR
 Rotate
 Compare
 Complement
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AND,OR,XOR Rotate
 Any 8-bit data, or the contents of register, or memory
location can logically have  Each bit in the accumulator can be shifted either left or
right to the next position.
 AND operation
 OR operation
 XOR operation
 with the contents of accumulator.
 The result is stored in accumulator.

Compare Complement
 Any 8-bit data, or the contents of register, or memory  The contents of accumulator can be complemented.
location can be compares for:
 Each 0 is replaced by 1and each 1is replaced by 0.
 Equality
 Greater Than
 Less Than
 with the contents of accumulator.
 The result
Dr. Ashok is reflected in status flags.
Kherodia (ECT-201) Dr. Ashok Kherodia (ECT-201)
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LogicalInstructions
LogicalInstructions
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LogicalInstructions
LogicalInstructions
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LogicalInstructions
LogicalInstructions
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LogicalInstructions
LogicalInstructions
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LogicalInstructions
LogicalInstructions
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LogicalInstructions
LogicalInstructions
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LogicalInstructions
BranchingInstructions
Jump Unconditionally
JMP 16 bit address The program sequence is transferred to
 The branching instruction alter the normal sequential
the memory location specified by the
flow. 16-bit address given in the operand.
 These instructions alter either unconditionally or Example: JMP 2034 H.

conditionally.
Opcode Bytes M- T-states Flags Example
cycle
JMP 3 3 10 None JMP 2050H
FRR
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Jump Conditionally
Jx 16 bit address The program sequence is transferred to
the memory location specified by the
16-bit address given in the operand if
condition is fulfilled otherwise
continue to next instruction based on
the specified flag of the PSW.
Example: JZ 2050 H.
Opcode Bytes M-cycle T-states Flags Example
Jx 3 3 7/10 None JZ 2050H
F R (If condition
not true)/F R R
(If condition is
true)
JumpConditionally
Opcode Description Status Flags
JC Jump if Carry CY = 1
JNC Jump if No Carry CY = 0
JP Jump if Positive S= 0
JM Jump if Minus S= 1
JZ Jump if Zero Z= 1
JNZ Jump if No Zero Z= 0
JPE Jump if Parity Even P =1
JPO Jump if Parity Odd P =0

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Unconditional Subroutine Call

CALL 16 bit address The program sequence is transferred to
the address specified by the 16-bit address
given in the operand. Before the
transfer, the address of the next
instruction to CALL (the contents of the
program counter) is pushed on the stack.
Example: CALL 2050 H.

CALL 3 5 18 None CALL 2050H
SRRWW
Conditional Call to Subroutine
CALL 16 bit address The program sequence is transferred to
the memory location specified by the 16-
bit address given in the operand based
on the specified flag of the PSW.
Before the transfer, the address of the next
instruction after the call (the contents of
the program counter) is pushed onto the
stack.
Example: CALL 2050 H.
Cx 3 2 (If condition 9/18 None CZ 2050H
not true)/5 (If
condition is true)
SRRWW
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CallConditionally BranchingInstructions
Opcode Description Status Flags Return from Subroutine Unconditionally
CC Call if Carry CY = 1 RET None The program sequence is transferred from the
subroutine to the calling program.
CNC Call if No Carry CY = 0
The two bytes from the top of the stack are copied
CP Call if Positive S= 0 into the program counter, and program execution
begins at the new address. The instruction is
CM Call if Minus S= 1 equivalent to POP program counter
CZ Call if Zero Z= 1
Example: RET.
CNZ Call if No Zero Z= 0
CPE Call if Parity Even P =1 Opcode Bytes M-cycle T-states Flags Example
CPO Call if Parity Odd P =0 RET 1 3 10 None RET
FRR
Return Conditionally
Rx None The program sequence is transferred from the
subroutine to the calling program based on the
specified flag of the PSW..
The two bytes from the top of the stack are copied
into the program counter, and program execution
begins at the new address.
Example: RZ

Rx 1 1 (If condition 6/12 None RZ
not true)/3 (If
condition is true)
SRR
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ReturnConditionally Restart (Software Interrupt)
Opcode Description Status Flags RST N (0-7) The RST instruction jumps the control to one of
eight memory locations depending upon the
RC Return if Carry CY = 1
number.
RNC Return if No Carry CY = 0 These are used as software instructions in a program
to transfer program execution to one of the eight
RP Return if Positive S= 0
locations.
RM Return if Minus S= 1 Example: RST 0
RZ Return if Zero Z= 1
RNZ Return if No Zero Z= 0 Opcode Bytes M-cycle T-states Flags Example

RST 1 3 12 None RST 0
RPE Return if Parity Even P =1
SWW
RPO Return if Parity Odd P =0
Restart AddressTable
Instructions Restart Address
RST 0 0000 H
RST 1 0008 H
RST 2 0010 H
RST 3 0018 H
RST 4 0020 H
RST 5 0028 H
RST 6 0030 H
RST 7 0038 H
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ControlInstructions
ControlInstructions
 The control instructions control the operation of

microprocessor.
ControlInstructions
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DI: ControlInstructions
ControlInstructions
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Opcode Table
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Dr. Ashok Kherodia (ECT-201)

Microcomputer, Microprocessors &

Dr. Ashok Kherodia (ECT-201)

Architecture of Intel 8085 Microprocessor INTEL 8085 Pin Configuration

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 Microprocessor consists of:

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Arithmetic Logic Unit Registers of 8085:

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Program Counter (PC) Program Status Word

 This 16-bit register is used to sequence the execution of

The Address and Data Busses The 8085 Bus Structure

 The address bus has 8 signal lines A8 – A15 which are

De-multiplexing AD7-AD0 De-multiplexing AD7-AD0

 ALE is a positive going pulse during T1, to latch the address.

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 Instruction Cycle(IC): The time required to complete the

Fetch, Decode, Execute cycle

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Operation Types in a Microprocessor Microprocessor Initiated operations

Memory Read Operation

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 Internal Data Operations Externally Initiated Operations

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Opcode Fetch Cycle

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Opcode Fetch Cycle Opcode Fetch Cycle

Data (opcode) flow from memory to microprocessor Memory Read Cycle

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Data flow from memory to microprocessor Memory Write Cycle

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Data flow from microprocessor to memory I/O Read Cycle

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Data flow from input device to microprocessor I/O Write Cycle

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Data flow from microprocessor to output device

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Instruction Format and Addressing Modes

Immediate Addressing Mode:

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Instruction size Instruction Types

Depending on the operand type, the instruction may have different

 Instructions that include a memory address occupy three bytes:

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Instruction Types Instruction Types

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 Data Transfer Instruction  These instructions move data between registers, or

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Data TransferInstructions Data TransferInstructions

This is 3 byte instruction; the second byte

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This is 3 byte instruction; the second byte

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Data TransferInstructions Data TransferInstructions

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Dr. Ashok Kherodia (ECT-201) Dr. Ashok Kherodia (ECT-201)