EE 457

Digital Integrated Circuits

Lecture 02
Dr. Bruce Kim

Note: Do not disseminate this lecture note without consent.

Today’s Lecture Outline

• Read chapter 5.1-5.3, 5.4, 5.5
• Designing CMOS inverter,
 Theory
 Objectives
 Noise Margins
• Introduction to CAD Tool – Electric,
• Examples of Electric layouts and techniques,
• Electric LT Spice

2
 Why CMOS?
• Low power consumption device. Power is drawn only during
switching of states in CMOS.
• Manufacturing is easier for CMOS.
• CMOS is voltage controlled device.
• CMOS has very high input impedance.
• CMOS is more sensitive to electrostatic discharge.
• CMOS has high noise margin.
• Integration density is better in CMOS.
• CMOS produces less amount of heat.

Device Structure and Symbols

Enhancement mode
conductor gate
gate
drain source
body
n+ n+ drain source
insulator body
p-Doped Substrate

conductor gate
drain source gate
body
p+ p+
drain source
insulator body
n-Doped Substrate
 CMOS Structure

Source: Wiki 5

CMOS transistors
Conditions
Vin = HIGH Vin = LOW

Vdd
S
G
Vin PMOS OFF ON

D
Vin G ON
NMOS OFF
S
Ground

6
 Basic Circuit Model

G
g RDS
S D
s d Cgs+Csb Cgd+Cdb

2.5
Rp 
 p Cox
Wp
Lp
V DD  Vtp 
2
Rn 
 nCox
Wn
VDD  Vtn 
Ln

Definitions
• µn,p  Mobility
• L,W  Length and Width of transistor gate
• Cox  Oxide Capacitance
• VGS  Gate to source voltage
• Vtn,p  Threshold voltage of transistor
• Rn, Rp  Channel resistances
conductor gate
drain source
body
n+ n+
insulator
p-Doped Substrate
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 MOS Resistances

 2.5
Rp 
 pCox
Wp
V DD  Vtp 


 p VDD  Vtp  ;   1  2. 5 PMOS Resistance
Lp

 2
Rn   ;  1  2 NMOS Resistance
 nCox n VDD  Vtn 
W  n VDD  Vtn 
Ln

Example
• Consider n-channel MOSFET with the following:

tox = 100Å, VTn = 0.45V, µn = 580 cm2/V-sec, W=12µm, L = 1.2µm

Compute Oxide Capacitance: Cox

Find Gate Capacitance: Cg

Compute Process Transconductance: K’n

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 Calculations

 r 0 3.9 0 3.9  8.854  1014 F / cm

( A)Cox    4
 3.45  1015 F / m 2
tox tox 0.01  10 cm

( B )Cg  Cox  AG  3.45  1015 F / m 2  12 m  1.2 m  49.68 fF

(C ) K ' n  n  Cox  580cm 2 / V  S  3.45  107 F / cm 2  200A / V 2

W  12 m
( D )  n  K ' n  n   200A / V 2   2000 A / V 2
 n
L 1. 2 m

Examples: 100Å = 100 Angstroms = 100x10-10 m, 1cm = 10mm = 10,000 m,

Farad = Amp*Sec/Volt, Few microns = few x 10-4cm
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Example
Suppose VGS = 1.5V and VDS = 1.5V. Compute ID.
Vsat  VGS  VTn  1.5  0.45  1.05V
VDS  1.5V  Vsat (The MOSFET is in saturation.)
K' W 
 ID  n (VGS  VTn ) 2  n (1.5  0.45) 2  1,102 A
2 L 2
Find Rn if the power supply is 3V
2 2
 Rn    392 
 n (Vdd  VTn ) A
2000 ( 3  0.45)V
V2
Use µp = 220 cm2/V-sec and repeat the steps for PMOS.

12
 The Ideal Inverter
• The ideal gate should have
 infinite gain in the transition region
 a gate threshold located in the middle of the logic swing
 high and low noise margins equal to half the swing
 input and output impedances of infinity and zero, respectively.
Vout

Ri = 

Ro = 0

NMH = NML = VDD/2

Vin

Inverter with NMOS

• NMOS: no active pull-up device
Vdd
3.3V
Rpu
100 Ω
Vout
IN
Vout
NMOS
4Ω
Rpd
Ground

• Consider Rpu = 100Ω, Rpd = 4Ω, Vdd = 3.3V

• Then Vout = 3.3 x 4/(104) = 13.1 mV
 CMOS Inverter
Signals IN OUT
0 = 0V 0 1
1 = 1.8V 1 0

Closed
Vdd
when IN
== LOW
OUT
IN
CL

Closed
when IN ==
HIGH
15

CMOS Inverter Modeling

• Consider two transistors connected below.

Vdd Vdd
Vdd
S
G Vin Vin
OFF
Vin Vout Vout
D Vout
D Cload
G Vin Vin
S OFF
Gnd
Ground
Vin = HIGH Vin = LOW
Vout = LOW (Gnd) Vout = HIGH (Vdd)

16
 CMOS Voltage Transfer Characteristics

Vdd
S
G
PMOS
Vin Vout
D
D Cload
G
NMOS
S
Ground

• Cut-off Region: VGS < Vth

• Linear Region (Ohmic): 0 < VDS < VGS – Vth
• Saturation Region: 0 < VGS – Vth < VDS
• Note: VGS = Vin

17

Noise Margins
• Measure of a gate sensitivity to noise
• Quantize the size of legal “0” and “1”
• Represents level of noise that can be tolerated when gates
are cascaded
• NML (noise margin low)
 NML = VIL - VOL

• NMH (noise margin high)

 NMH = VOH - VIH

• Should be large as possible for good noise immunity

18
 Mapping Logic Levels

V V(y)
"1" OH Slope = -1
V
V
IH OH

Undefined
Region
Slope = -1
V
IL VOL
"0"
V
OL V V V(x)
IL IH

Voltage and Logic Levels VIL and VIH (see Fig. 1.12 in text)

19

Definition of Noise Margins

Source: Rabaey et al. 20

 Examples
• Determine the noise margins of a CMOS
inverter with VDD=5V, VIL=2.2V, VIH=2.7V,
VOL=0.2V and VOH=4.8V.

 The noise Margins are:

NM L  VIL  VOL  2.2  0.2  2.0V
NM H  VOH  VIH  4.8  2.7  2.1V

We want large as possible for good noise immunity

21

Noise Immunity
• Circuit ability to overcome noise
• Sources of Noise
 Power supply noise
 cross talk
 Interference
 Offset

• Noise immunity - ability of system to process and transmit

information correctly in the presence of noise
• For good noise immunity
 Voltage swing should be large ( VOH – VOL)
 Noise margin should be large
 Digital Waveforms
Vin

Ideal Input

t
Vin
90%

Practical Input

10%
t
tr tf

23

CMOS Inverter Model

Cout = CL + CDn + CDp

CG = ?
24
 Time Constants
 n  RnCout RC time constant to discharge

t f  2 .2   n Time for output to change from high to low

(90% to 10%)

 p  R p Cout RC time constant to charge

t r  2 .2   p Rise time (10% to 90%)

25

Input Maximum Frequency

1
f max 
(t r  t f )
The output cannot settle if run faster than this frequency.

26
 Delay Definitions
Vin Vout Propagation delay

Vin tp = (tpHL + tpLH)/2

input
t p  0.35( n   p )
50%
waveform

t
tpHL tpLH
Vout
90% 90%
output
waveform 50%

10% 10%
t
tf tr

Electric Download Link

• Electric download link:
http://cmosedu.com/cmos1/electric/electric.htm

• Electric lecture videos – Prof. David Baker

http://www.cmosedu.com/videos/electric/Electri
c_video_1/Electric_video_1.wmv

• LTSpice Download link

http://www.linear.com/designtools/software/#LTspice

• IRSIM Download link

http://opencircuitdesign.com/irsim/download.html#Dow
nload
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 Start Electric
• Double click on “electric-9.04” jar file to start electric

Technology (Lambda)
• Set technology scale to 350nm (1λ=350nm; Gate Length =
2λ = 700nm
• File  Preference  Technology  Scale
 New Library
• Start new Library
• Name the library as “inverter

New Cell
• Start New cell – Schematic
• Name Schematic as inverter
 Toggle Grid
• Goto Windows  Toggle Grid, to turn grid on. Each individual
grid length is 1λ
• If background is Grey, goto Windows  Color Schemes and
choose White background

The CMOS Inverter

VDD

Vin Vout
CL
 Transistor Schematic
• Select Components Palette. Select PMOS and draw.

4-port Transistor
• Select the transistor. Goto Edit  Change, and select 4 port transistor
“pmos-4”. Click Change and then Done.

36
 Scaling
• Double click on device and enter length and width of
transistor gate
• Enter gate length as 2. PMOS Width as 8 and NMOS width
as 4

Mirroring PMOS
• Select the PMOS transistor and goto Edit  Mirror  Up-Down
• This is done to keep the body and source terminals of the PMOS
connected to VDD.

38
 Connecting Arcs
• Left click on node to select. Right click and drag to
make wire connections.

Connected Arcs
 Exporting nodes
• Select node to export, goto Export  Create new export.
• Select type of export characteristics – input/output/power/ground

Spice model
• Generating Spice model for transistor
• Goto Tools  Simulation (Spice)  Set Spice Model
• Rename Model name to N and P for NMOS and PMOS, respectively.
 Moving text
• To move text: Select Node, hold Ctrl and select text to move.
• To access text behind the node: Select the node, Go to Edit  Object Properties
(Ctrl + I), uncheck the easy to select option. Now the cursor won’t highlight the
node.
• To be able to select the node again, Toggle the special select cursor on the toolbar.

Spice Code
• In the Components palette select Miscellaneous  Spice Code
• Double click the Spice code, press Ctrl + I, choose multi-line code
and enter the Spice code as shown
 DRC Check
• Design Rule Check (DRC) – F5
• If you see any errors, press ‘<‘ or ‘>’ to navigate to error
description and correct them.

Write Spice Deck

• Select Tools  Simulation (Spice)  Write Spice Deck
• Save as ‘inverter_schematic.spi’
 LT Spice
• Double click on “inverter_schematic.spi”. LT-Spice will open.
• There is an inherent MOS model file that comes with LT-Spice, shown in
braces.
• Since we are using a text model file. We will delete the model provided
in Spice.

Select & Delete

LT Spice Simulation
• Press Run to simulate the code
• Right click on plot plane and add traces, V(in) and V(out)
• To change background to white, Go to Tools  Color Preferences
 Click on the waveform background  Set R,B,G to 255 each and
select Apply.
 CMOS Structure

Source: Wikipedia 49

Layout Design Rules

• Absolute-value Design Rules P-Mos
Based on absolute distances
Not scalable
• λ – based Design Rules
Scalable with technology
Current technology 22nm P-Active
Region

Polysilicon

50
Design Rules on MOS Layout
2λ
2λ
2λ

2λ

2λ 2λ
Polysilicon
2λ
Contact

Active Region
51

Design Rules for Contacts

Poly

Contact

4λ 2λ 3λ

Metal 1

3λ
52
 Starting Layout
• Select Library  Start New Cell  Select layout. Name cell as
inverter.
• This will group the schematic and layout together.

53

PMOS Transistor
• Select Components palette.
Select pMOS and drag.
• Select Node, rotate (Ctrl+J) as
shown and goto Node
Properties (Ctrl+I). Enter nWell
pMOS length and width.
P select
• Select pAct and connect nodes
to source and drain of pMos P active

• Select nWell and place on top

of pMos for Vdd connection. polysilicon pMos

54
 Metal Connection
• Select one of the contacts,
Right click and drag to other
contact to establish metal
interconnection.
• Polysilicon to Metal contact –
Choose the Metal-1-
Polyicilicon-1 Contact from
Metal
the left palette. Connect the
polysilicon to the contact.
Select pin node from the
Pin node
palette and place in window.
Left click and drag to establish
metal connection.
Polysilicon – Metal
Contact
55

Layout
• Add Spice code from
schematic
• Export nodes similar to
schematic NWELL
• Write Spice deck and
save as “inverter-
layout.spi”

PWELL

56
 Write Spice Deck
• Select Tools  Simulation (Spice)  Write Spice Deck
• Save as ‘inverter_layout.spi’
• Double click on “inverter_layout.spi”. LT-Spice will open.
• Delete the inherent model provided in Spice.
• Hit F5 to run the simulation.
• If there are any errors, debug the SPICE code, go back to Electric
and correct the layout, and re-simulate the code.
• If there are no errors, plotting plane will open up.
• Right click on plot plane and add traces, V(in) and V(out)
• To change background to black. Goto Tools  Color Preferences 
Click on the waveform background  Set R,B,G to 255 each and
select Apply.

LT Spice

Select & Delete

Spice Simulation

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