PERFORMANCE EVALUATION OF

VARIABLE FREQUENCY SINGLE PHASE

CASCADED MULTILEVEL INVERTER

A PROJECT REPORT

Submitted by

PRIYANKA.A 421615105063

RAGAVI.R 421615105065

SINDHUJA.S 421615105081

in partial fulfilment for the award of the degree

of

BACHELOR OF ENGINEERING

in

ELECTRICAL AND ELECTRONICS ENGINEERING

MAILAM ENGINEERING COLLEGE

MAILAM-604304

ANNA UNIVERSITY::CHENNAI 600025

MARCH 2019

ANNA UNIVERSITY:: CHENNAI 600 025

i
 BONAFIDE CERTIFICATE

Certified that this project report titled “Performance Evaluation of

Variable Frequency Single Phase Cascaded Multilevel Inverter” is the
bonafide work of “Priyanka.A , Ragavi.R and Sindhuja.S , who
carried out the project work under my supervision.

SIGNATURE SIGNATURE
Dr. N.MURALI KRISHNAN Dr.G.IRUSAPPARAJAN
PROFESSOR SUPERVISOR

HEAD OF THE DEPARTMENT PROFESSOR

Electrical and Electronics Engineering Electrical and Electronics Engineering

Mailam Engineering College, Mailam Engineering College,

Mailam-604304 Mailam-604304

Submitted to project work and viva-voce Examination held on ………………

INTERNAL EXAMINER EXTERNAL EXAMINER

ii
 ACKNOWLEDGEMENT

I take immense pleasure in thinking our honorable Chairman and Managing

Director, Sree.M.DHANASEKARAN, our honorable Vice chairman
Dr.K.SUGUMARAN,M.L.A and our honorable Secretary
Dr.K.NARAYANASAMY for providing me with an environment to complete
my project successfully.

I wish to express my deep sense of gratitude to our principal Dr.SENTHIL for

giving us this opportunity to showcase my technical ability with this project.

I would like to express my sincere thanks to our Dean Dr.R.RAJAPPAN for

this kind patronage.

I am deeply indebted to our Head of the Department

Dr.N.MURALIKRISHNAN for his unwavering support during the entire
course of this project.

It is a great pleasure to express our gratitude and thanks towards our supervisor
Dr.G.IRUSAPPARAJAN. for his uninterruptable suggestions and words of
improvements regarding this project, which played a major role in guiding us in
my track.

Works are inadequate in offering my thanks to all staff members of our

department for their constant encouragement and support throughout the course,
especially for the useful suggestions given during the project period.

Finally, yet importantly, I would like to express my heartfelt thanks to my

beloved parents for their blessings, my family and friends for their help and
wishes for the successful completion of this project. I also thank all the others
who directly or indirectly were a source of help to mean accomplishing this
project.

iii
 ABSTRACT

It is proposed that, a new group of single phase cascaded 27 level inverter

with reduced switch count that operates in asymmetrical state. The proposed

multilevel inverter produced DC voltage levels similar to other topologies with

less number of semiconductor switches. Due to involvement of less

semiconductor switches it dramatically reduces the harmonics, switching losses

and cost. Asymmetrical reduced switch multilevel inverter is triggered by

sinusoidal PWM techniques. These PWM techniques include Phase Disposition

(PD), Alternate Phase Opposition Disposition (APOD), and Carrier Overlapping

(CO). Performance factor like Total Harmonic Distortion (THD), V RMS

(fundamental), Crest Factor, Form Factor, Distortion Factor are evaluated for

various modulation indices, APOD produces output voltage with less amount ,

of harmonics COP produces higher margin output voltage. The simulation of

proposed circuit is carried out using MATLAB/Simulink.

iv
 ததடடட சரகடகமட

ஒறடறற கடடடதடததனட ஒர பததய கழ 27 சமனட அளவதலலன சழறடசதறயகட ககலணடடத, இத

சமசடசசரறடற நதறலயதலட கசயலடபடமட சவதடடசட எணடணதகடறக கறறகடகபடபடடடத. மனடகமலழதயபடபடடட
பலவழத மதனடவழஙடகலட கறறவலன எணடணதகடறகயதலலன கறறகடகடதடதத சவதடடசகளட ககலணடட பதற
பரபடபளறவபட பபலல ட.சத. மதனடனழதடதமட அளவகறள உரவலகடகதயத. கறறவலன கறறகடகடதடதத
சவதடடசகளட ஈடபடவதனட கலரணமலக அத நலதவறடறறத கறறகடகதறத, இழபடபகடகளட மறடறமட
கசலவதனஙடகறள மலறடறதயறமகடகதறத. சமசடசசரறடற கறறவலன சவதடடசட பனடமறனகவலட
இனடகவரடடரட PWM நடடபஙடகளட தணடடபடபடகதறத. இநடத PWM நடடபஙடகளதலட கடடட நதறலறம
(PD), மலறடற நதறல எததரடவ வதழதபடபணரடவ (APOD) மறடறமட பகரதயரட ஓவரடபலபடபதஙட (CO)
ஆகதயறவ அடஙடகமட. கசயலடததறனட கலரணத கமலதடத ஹலரடபமலனதகட டஸடபடலரதஷனட (THD),
VRMS (அடபடபறட), கதகரஸடடட கலரணத, படவமட கலரணத, டஸடபடலஷனட கலரணத பலடபவற
பணடபபறடறமட கறதயசடகளகடக மததபடபசட கசயடயபடபடகதனடறன, APOD கறறவலன அளவ
கவளதயசட மதனடனழதடதமட உறடபதடதத கசயடகதறத, இணகடகமதனடறம COP உயரட வதளதமடப கவளதயசட
மதனடனழதடதமட உறடபதடதத கசயடகதறத. மனடகமலழதயபடபடடட சறடற உரவகபடபடதடததலட MATLAB /
Simulink ஐபட பயனடபடதடதத பமறடககலளடளபடபடகதறத.

TABLE OF CONTENTS

CHAPTER TITLE PAGE NO.

NO. ABSTRACT i
ACKNOWLEDGEMENT ii
LIST OF TABLES v
LIST OF FIGURES vii
SYMBOLS xi

v
 ABBREVIATIONS xii
1 INTRODUCTION 1
1.1 Diode Clamped Multilevel Inverter 2
1.2 Flying Capacitor Multilevel Inverter 5
1.3 Cascaded Multilevel Inverter 8
2 LITERATURE SURVEY 11
3 PROPOSED TOPOLOGY 15
3.1 Proposed Solution 15
3.2 Asymmetrical Reduced Switch Nine
Level Inverter 15
3.3 Operation 16
4 MODULATION TECHNIQUES 19
4.1 Introduction 19
4.2 PWM Control Strategies 19
4.2.1 Sinusoidal Pulse Width Modulation
Scheme 19

4.2.1.1Unipolar Sinusoidal Phase

Disposition PWM 19
4.2.1.2 Unipolar Sinusoidal
Alternative Phase Opposition
Disposition PWM 21
4.2.1.3 Unipolar Sinusoidal Carrier
Overlapping PWM 22
5 SIMULATION RESULTS 23
5.1 R Load 23
5.2 RL Load 29
6 ADVANTAGES 36
7 APPLICATION 37

vi
 8 CONCULSION 38
REFERENCE 39

LIST OF TABLES

TABLE NO. TITLE PAGE NO

1.1 Switching states and leg output voltages for

Three-level and four-level diode clamped
Inverter. 4

1.2 Switching states and leg output voltages for

Three-level flying capacitor inverter. 8
1.3 Switching states and leg output voltages
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 for Three-level cascaded H-bridge inverter. 8
1.4 Switching states and leg output voltages for
Five-level cascaded H-bridge inverter. 9
1.5 Comparisons of power component
Requirements Per phase leg among three
multilevel inverters 10
3.1 Comparisons between symmetrical and
asymmetrical Inverter. 15
3.2 Switching table for proposed inverter. 18
5.1 % THD for different modulation indices
(R load) 26
5.2 VRMS for different modulation indices
(R load) 26
5.3 Form Factor for different modulation
indices (R load) 27

5.4 Crest Factor for different modulation

indices (R load) 27
5.5 Distortion Factor for different modulation
Indices (R load) 27
5.6 % THD for different modulation indices
(RL load) 32
5.7 VRMS for different modulation indices
(RL load) 32
5.8 Form Factor for different modulation
indices (RL load) 33
5.9 Crest Factor for different modulation
indices (RL load) 33
5.10 Distortion Factor for different modulation
indices (RL load) 33

viii
 LIST OF FIGURES

FIGURE NO TITLE PAGE NO

1.1 Diode Clamped Multilevel Inverter

(a) three level and (b) four level 3

1.2 Flying Capacitor Multilevel Inverter

(a) three level and (b) four level 6
1.3 Cascaded Multilevel Inverter
(a) three level and (b) five level 9
3.1 Proposed Multilevel Inverter 16
4.1 Carrier arrangement for USPDPWM

ix
 strategy 20
4.2 Carrier arrangement for USAPODPWM
strategy 21
4.3 Carrier arrangement for USCOPWM
strategy 22
5.1 Simulink model of proposed Multilevel
Inverter for R load 23
5.2 Simulated 27level output voltage
Generated by USPDPWM strategy
(ma=0.9,mf=40) 23
5.3 FFT-harmonic spectrum of output of
USPDPWM strategy (ma=0.9,mf=40) 24

5.4 Simulated 27 level output voltage generated

by USAPODPWM strategy (ma=0.9,mf=40) 24
5.5 FFT-harmonic spectrum of output of USAPOD
strategy (ma=0.9,mf=40) 25
5.6 Simulated 27 level output voltage generated
by USCOPWM strategy (ma=0.9,mf=40) 25
5.7 FFT-harmonic spectrum of output of
USCOPWM Strategy (ma=0.9,mf=40) 26
5.8 Simulink model of proposed Multilevel
Inverter for RL load 29
5.9 Simulated 27 level output voltage generated
by USPDPWM strategy (ma=0.9,mf=40) 29
5.10 FFT-harmonic spectrum of output of
USPDPWM strategy (ma=0.9,mf=40) 30
5.11 Simulated 27 level output voltage generated
by USAPODPWM strategy (ma=0.9,mf=40) 30

x
 5.12 FFT-harmonic spectrum of output of USAPOD
strategy (ma=0.9,mf=40) 31
5.13 Simulated 27 level output voltage generated
by USCOPWM strategy (ma=0.9,mf=40) 31
5.14 FFT-harmonic spectrum of output of
USCOPWM strategy (ma=0.9,mf=40) 32

SYMBOLS

Ac Amplitude of Carrier Wave

Am Amplitude of Reference Wave

fc Frequency of Carrier Wave

fm Frequency of Reference Wave

m Number of Levels

ma Modulation Indices

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mf Modulating Frequency

ABBREVIATIONS

CF Crest Factor

CMLI Cascaded Multilevel Inverter

DCMLI Diode Clamped Multi Level Inverter

DF Distortion Factor

FCMLI Flying Capacitor Multi Level Inverter

FF Form Factor

THD Total Harmonic Distortion

xii
USPDPWM Unipolar Sinusoidal Phase Disposition Pulse

Width Modulation

USAPODPWM Unipolar Sinusoidal Alternating Phase

Opposition Disposition Pulse Width Modulation

USCOPWM Unipolar Sinusoidal Carrier Phase Disposition Pulse

Width Modulation

CHAPTER-1

INTRODUCTION
The multilevel inverter uses a series of power semiconductor switches with
several lower voltage dc sources to perform the power conversion by
synthesizing a staircase voltage waveform. Capacitors, batteries, and renewable
energy voltage sources can be used as the multiple dc voltage sources.
Multilevel inverters generate the output voltages with very low distortion,
produce smaller common mode voltage, draw input current with low distortion
and can operate at both fundamental switching frequency and high switching

xiii
frequency PWM. Despite these advantages, the major disadvantage is that a

multilevel inverter uses more number of semiconductor switches. Lower

voltage rated switches can be utilized but each switch requires an appropriate
gate drive circuit. This may cause the overall system to be more expensive and
complex.
The types of multilevel inverter is
 Diode Clamped multilevel inverter
 Flying Capacitor multilevel inverter
 Cascaded multilevel inverter
The flying capacitor inverter is difficult to realize because each capacitor
must be charged with different voltages as the voltage level increases. The
diode clamped inverter is difficult to expand to multilevel because of the
natural problem of the DC link voltage unbalancing. Though the cascaded
multilevel inverter requires separate dc sources, it can be expanded to
multilevel easily and the problem of the dc link voltage unbalancing does not
occur. Due to these advantages, the cascaded inverter has been widely applied
to such applications as HVDC, SVC, stabilizer, high power motor drive and so
on. This topology of inverter is suitable for high voltage and high power
inversion because of its ability to synthesize waveforms with better harmonic
spectrum.

1.1 Block Diagram of MLI

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 Figure 1.1
Input Supply:
DC input voltage in order of 1:3:9 Trinary multilevel inverters. Its Produce nine
level output voltage
Firing Pulse
Multicarrier single reference pulse width modulation techniques are used for
this project it need eight carrier signal for nine level inverter. Different types of
pulse width modulation (PWM) controls have been discussed. Carrier Based
Pulse Width Modulation (CBPWM) and Space Vector based Pulse Width
Modulation (SVPWM) are the most popular schemes. But, CBPWM is often
used for higher voltage levels. Whereas the SVPWM is difficult for generating
pulses for more than five levels due to the redundancy of switching states.
Therefore, CBPWM control is chosen as the control technique for the proposed
topology in this article. Different types of CBPWM are used to generate
switching pulses in the proposed topology. In CBPWM method, multiple
carriers (“m” level inverter output require “(m–1)/2” carriers) are formed
together which are continuously compared with sinusoidal reference
and creates the PWM signals. The multiple carriers can be arranged in many
ways based on control freedom technique. This paper focuses on four different
carriers by using unipolar reference with multiple carriers.

The unipolar scheme requires half of the carriers as compared to conventional

(bipolar) PWM scheme which is the major advantage. The four different types
of carrier arrangements are examined in this work such as PDPWM,
APODPWM, COPWM and VFPWM. The reference waveform is a

xv
as unipolar sinusoidal signal and 13 carrier waveforms considered as triangular
signal. The reference Unipolar sinusoidal waveform is continuously compared
with each triangular carrier signals. If the reference sinusoidal wave
is more than a triangular carrier signal, then the active switching devices
equivalent to the triangular carriers are turned ON. Otherwise, the switching
device is turned OFF. In this paper, the carrier frequency ratio is considered as
60 and a modulation index varies from0.9 to 1.
1.2 DIODE CLAMPED MULTILEVEL INVERTER
This converter is based on a modification of the classic two level converter
topology adding new power semiconductors per phase. The simplest NPC
converter is shown in Fig. 1.1(a), implementing three leg voltage levels by
doubling the number of switches and adding the same number of diodes to each
additional switch. An additional level is clamped through the diodes (clamping
diodes) connected to so-called neutral point of the source, as denoted in Fig.
1.1(a). Using this new topology, each power device has to stand, at the most,
half voltage compared with the two-level case with the same dc-link voltage.
Therefore, having the same power semiconductors ratings as the two-level
case, the output voltage can be doubled.
Note that for number of leg voltage levels nhigher than three there is no
single clamped point, (for even number of levels there is no neutral point at
all). Based on the parity of the n converters are divided in neutral point
clamped (NPC) for an odd number, and multi-point clamped, when n is even.
The principle of the switching is quite simple: for n-level inverter highest (n-1
switches need to be turned on together to achieve maximum leg voltage, next
(n-1) switches to be turned on for (n-2)-th output level etc, up to the last (n-1)
switches, which turned on together give zero leg voltage.
There are also limitations: turning on n adjacent switches would lead to shoot-
through. This can be illustrated on a three-level and four-level examples (Fig.
1.1), which are also of the highest practical interest, with the switching
combinations given in Tab. 1.1. There are only three useful combinations for

xvi
three-level case, whereas the other lead to undefined states. Therefore, this
multilevel inverter has no redundant states (i.e. different switching
combinations leading to the same output voltage). Similar conclusion can be
made from four level inverter switching states (Tab. 1.1).

(a)Three Level

(b)Four Level
Fig. 1.1 Diode clamped multilevel inverter
State of switches 3-level
Ta1 Ta2 Ta3 Ta4 Leg Voltage
1 1 0 0 Vdc
Value
0 1 1 0 0
0 0 1 1 -Vdc

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 Tab.1.1 Switching states and leg output voltages for three-level and four-level diode-
clamped inverters

State of switches 4-level

Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Leg
Voltage
1 1 1 0 0 0 1.5Vdc
Value
0 1 1 1 0 0 0.5Vdc
0 0 1 1 1 0 -0.5Vdc
0 0 0 1 1 1 -1.5Vdc

However, four-level inverter has a serious drawback compared to three-level

one: additional diodes do not have equal reverse voltage. Indeed, when Ta5 and
Ta6 are on, diode Da2 has to withstand reverse voltage equal to 2Vdc, which is
double of the transistors rated voltage. Furthermore, for inverters with higher
number of levels this voltage further increases. In addition, switches are not
directly clamped to the dc link capacitors by the opposite freewheeling diodes,
except for the outmost two, in contrast to two-level inverter. In this way static
or stray inductance overvoltage can appear across the switches. These two are
the biggest drawbacks of NPC inverters with higher number of levels, because
it practically turns back the problem to the initial series connection of switches.
For these reasons, three-level inverter is the most popular within its
class. In order to solve these problems for higher number of levels a different
diode-clamped topology has been proposed. The structure provides a more
direct clamping both diodes and switches to the dc capacitors.

The main features of diode clamped inverter are:

 High voltage rating for blocking diodes
 Unequal switching device rating
 Capacitor voltage unbalance
The major advantages are:
 When the number of levels is high enough, the harmonic content is low
enough to avoid the need for filters
xviii
 Inverter efficiency is high because all devices are switched at the fundamental
frequency
 The control method is simple
The major disadvantages are:
 Excessive clamping diodes when the number of levels is high
 It is difficult to control the real power flow of the individual converter in multi
converter system
1.3 FLYING CAPACITOR MULTILEVEL INVERTER
The flying capacitor (FC) topology is in some way derived from it diode
clamped predecessor by the simplification – elimination of the clamping
diodes. FC inverter uses additional capacitors oppositely charged to be
included in series with dc supply, since after the elimination of the diodes it is
not possible to connect leg output directly to the desired dc voltage. These
capacitors have the same function of the clamping diodes in diode-clamped
converter: they keep constant the voltage drop between the busses to which
they are connected. For this reason, they are called clamping capacitors, giving
the name to the converter. Another name that can be found in the literature is
the nest cell converter. The principle of the switching is similar to the DCI, and
will be explained for three-level and four-level examples shown in Fig. 1.2.
However, there is adifference in the principle: clamping capacitors need to be
connected in series, and must not be short-circuited by turning on switches
connected in parallel.
The switching table is given in Tab. 1.2, showing redundancy for leg
output voltage equal to zero which is another difference with respect to DCI.
These voltage-level redundancies can be used as extra degrees of freedom for
control or optimization purposes. However, the main and most important
difference with the NPC topology is that the FC has a modular structure that
can be more easily extended to achieve more voltage levels, for this reason
sometimes called multicell inverter.
7

xix
 (a)Three Level

(b)Four Level
Fig. 1.2Flying capacitor inverter
The main drawback of the FCI is complex control algorithm and many
voltage sensors for high number of capacitor voltages to be controlled. Another

xx
problem is capacitors flying connection that requires both initialization and
control, which requires the use of the redundant states. The hardware
disadvantage is requirement for significant number of capacitors.
Since the applications are at lower carrier frequencies the high values of
capacitors is the major disadvantage of the FCI. In addition, capacitors are
unequally rated, as can be noted in Fig. 1.2(b), where the outer capacitors need
to withstand almost full dc voltage, compared to DCI where all capacitors were
equal and relatively small. In addition, the drawback of unequal switch currents
common with DCI remained. To conclude, the youngest among the common
multilevel configurations (proposed less than twenty years ago), this converter
remained in the shadow of the other two competitors.
The main features of flying capacitor inverter are:
(i) Large number of capacitors
(ii) Balancing capacitor voltages
The major advantages are:
(i) Large amounts of storage capacitors can provide capabilities during power
(ii) These inverters provide switch combination redundancy for balancing
different voltage levels
(iii) Like the diode clamped inverter with more levels, the harmonic content is
low enough to avoid the need for filters.
(iv) Both real and reactive power flow can be controlled
The major disadvantages are:
(i) An excessive number of storage capacitors is required when the number of
levels is high.
(ii) High level inverters are more difficult to package with the bulky power
capacitors and are more expensive too.
(iv) The inverter control can be very complicated, and the switching frequency
and the switching losses are high for real power transmission Tab.

1.2 Switching states and leg output voltages for three-level flying capacitor inverter

State of switches 3-level

Ta1 Ta2 Ta3 Ta4 Leg Voltage
1 1 0 0 Vdc
xxi
1 0 1 0 0
Value 0 1 0 1 0
0 0 1 1 -Vdc
0 1 1 0 Short-Circuit
1.4 CASCADED MULTILEVEL INVERTER
Figure.1.3 shows 3-level and 5-level cascaded H-bridge legs. As usual,
the 3-level converter analysis is the simplest and lets understand the operating
principle of the modules composing the leg of a generic n-level converter;
these modules are often called cells. It is well known that H-bridge converters
can be modulated with 2-level or 3-level output. In this kind of multilevel
converter, all the possible cell output levels are exploited. Some switches
configurations are harmful for the converter and they must be avoided; for
instance, the switches T1 and T1′are not allowed to be turned on at the same
time because this situation causes a shortcut of the source.Table.3 shows the
relationship between the allowed switches configurations and the output of a 3-
level cascaded inverter.

Table.1.3Switching states and leg output voltages for three-level cascaded H-Bridge inverter
Switches State Output Voltage

T1 T2 T1′ T2′ VAO

1 0 0 1 E

1 1 0 0 0

0 0 1 1 0

xxii
 0 1 1 0 -E

It can be seen that even cascaded converter presents an intra-phase redundancy

because there are two different ways to obtain the level 0. Moreover,
considering the same DC source voltage, the output level amplitude and the
switches reverse voltage drop are greater here than in the diode-clamped or
flying-capacitor.

(a)Three Level

(b)Five Level
Figure.1.3cascaded H-bridge

xxiii
 In order to increase the number of levels more cells have to be cascaded.
High and low couple of switches can be defined in the respect of voltage output
direction. Considering the couple of switches composed by T1 and T1′is the
high one, whereas T2 and T2′constitute the low couple. The high output of one
cell is shortcut to the low output of another one to realize a cascade connection
between two cells.

Table.1.5 Comparison of power component requirements per phase leg among three
Multilevel Inverter
Switches State Output
Voltage
T11 T12 T21 T22 T11′ T12′ T21′ T22′ VAO
1 0 1 0 0 1 0 1 2E
1 1 1 0 0 0 0 1 E
1 0 0 0 0 1 1 1 E
1 0 1 1 0 1 0 0 E
0 0 1 0 1 1 0 1 E
1 1 1 1 0 0 0 0 0
1 1 0 0 0 0 1 1 0
1 0 0 1 0 1 1 0 0
0 1 1 0 1 0 0 1 0
0 0 1 1 1 1 0 0 0
0 0 0 0 1 1 1 1 0
0 1 1 1 1 0 0 0 -E
0 0 0 1 1 1 1 0 -E
0 1 0 0 1 0 1 1 -E
1 1 0 1 0 0 1 0 -E
0 1 0 1 1 0 1 0 -2E

xxiv
 Table.1.4Switching states and leg output voltages for five-level cascaded H-Bridge inverter
The cascade H-bridge was the founder of cascade converter family and
the simplest one. Each type of single-phase multilevel converter can be
cascaded to obtain a leg. In this way, the level each cell adds increase and is a
good compromise between the required insulated sources and the number of
output levels.
The main features of cascaded inverter are:
 For real power conversions from ac to dc and then dc to ac, the cascaded
inverters need separate dc sources.
 The structure of separate dc sources is well suited for various renewable energy
sources such as fuel cell, photovoltaic, and biomass.
 Connecting dc sources between two converters in a back to back fashion is not
possible because a short circuit can be introduced when two back to back
converters are not switching synchronously
The major advantages are:
 Compared with the diode clamped and flying capacitors inverters, it requires the
least number of components to achieve the same number.
 Optimized circuit layout and packaging are possible because each level has the
same structure and there are no extra clamping diodes or voltage balancing
capacitors.
 Soft switching techniques can be used to reduce switching losses and device
stresses
Inverter Diode-Clamp Flying- Cascaded
Configuration Inverter Capacitors Inverters
Inverter
Main Switching 2(m-1) 2(m-1) 2(m-1)
Devices
Main 2(m-1) 2(m-1) 2(m-1)
Diodes
Clamping (m-1)(m-2) 0 0
Diodes
DC Bus (m-1) (m-1) (m-1)/2

xxv
 Capacitors
Balancing 0 (m-1)(m-2)/2 0

CHAPTER-2
LITERATURE SURVEY
G. Pandian and S. Rama Reddy “Implementation of Multilevel Inverter-
Fed Induction Motor Drive Journal of Industrial Technology”, Volume 24,
Number 2, June 2008.

This paper introduces a symmetrical multilevel inverter fed induction

motor. This method highly reduces harmonics present in the circuit and also
produce a high torque

KaralapatiPreethi, G.Anil, E.Vani, ”Speed Control of Induction Motor

Using Eleven Levels Multilevel Inverter”, International Journal of Science
and Modern Engineering (IJISME) , Volume-1, Issue-5, April 2013

In this paper diode clamped MLI are used to control the speed of
Induction Motor. Stator control method are used to control the speed. By this
method harmonics was highly reduced and motor torque was increased.

Johannes Kolb, Felix Kammerer, Mario Gommeringer, and Michael

Braun,“ Cascaded Control System of the Modular Multilevel Converter
for Feeding Variable-Speed Drives”, IEEE TRANSACTIONS ON
POWER ELECTRONICS, VOL. 30, NO. 1,pp 349-357, JANUARY 2015

The modular multilevel converter (MMC) is an up- coming topology for

high-power drive applications especially in the medium voltage range. This
paper presents the design process of a holistic control system for a MMC to

xxvi
feed variable-speed drives. By this method minimize current stress and
additional voltage pulsations.

Yuhei Okazaki, Makoto Hagiwara, and Hirofumi Akagi,”A Speed-Sensor

less Start-Up Method of an Induction Motor Driven by a Modular
Multilevel Cascade Inverter” (MMCI-DSCC) IEEE TRANSACTIONS
ON INDUSTRY APPLICATIONS, VOL. 50, NO. 4, pp 2671-
2680JULY/AUGUST 2014.

This paper presents theoretical and experimental discussions on a

practical speed-sensor less start-up method for an induction motor driven by a
modular multilevel cascade inverter based on double-star chopper cells
(MMCI-DSCC) from stand- still to middle speed. It reduces voltage
fluctuation. Obrad Dordevic, Martin Jones, and Emil Levi, A,”
Comparison of Carrier-Based and Space Vector PWM Techniques for
Three-Level Five-Phase Voltage Source Inverters”, IEEE Transactions on
Industrial Informatics, VOL. 9, NO. 2,pp 609-618, may 2013.

This paper deals with a three-level neutral point clamped (NPC) inverter
supplied five-phase induction motor drive and analyses five PWM strategies:
three are carrier-based (CBPWM) and two are space vector based
(SVPWM).The aim is to provide a detailed comparison and thus conclude on
proposed and concept of each solution, providing a guide- line for the selection
of the most appropriate PWM technique

AshwiniN.Kadam,” Simulation And Implementation Of Multilevel

Inverter Based Induction Motor Drive Based On PWM Techniques”,
International Journal of Industrial Electronics and Electrical Engineering,
ISSN: 2347-6982 Volume- 2, Issue- 1, Jan.-2014.

The main objective of this paper is to control the speed of an induction

motor by using three level diode clamped multilevel inverter.

xxvii
To obtain high quality sinusoidal output voltage with reduced harmonics,
multicarrier PWM control scheme is proposed for diode clamped multilevel
inverter

EbrahimBabaei, SomayehAlilu, Sara Laali,“A New General Topology for

Cascaded Multilevel Inverters With Reduced Number of Components
Based on Developed H-Bridge”, IEEE transactions on industrial
electronics, vol. 61, no. 8, pp 3932-3939, august 2014.

In this paper, a new general cascaded multilevel inverter using developed

H-bridges is proposed. The proposed topology requires a lesser number of dc
voltage sources and power switches and consists of lower blocking voltage on
switches, which results in decreased complexity and total cost of the inverter

Sumit K. Chattopadhyay, and Chandan Chakraborty,” A New Multilevel

Inverter Topology With Self-Balancing Level Doubling Network”, IEEE
transactions on industrial electronics, VOL. 61, NO. 9, Pp 4622-4631,
september 2014

A new multi level inverter (MLI)topology is proposed using a level

doubling network (LDN). The LDN takes the form of a half-bridge inverter to
almost double the number of output volt- age levels. The concept (of the
proposed LDN) has the capability of self-balancing during positive and
negative cycles without any closed-loop control/algorithm, and it does not
consume or supply any power. It significantly improves the power quality,
reduces the switching frequency, and reduces the cost and size of the power
filter

Bahr Eldin S. Mohammed and K.S.RamaRao, “A New Multicarrier Based

PWM For Multilevel Converter”, IEEE applied power electronics
colloquium (IAPEC)., 2011.This paper introduced a multicarrier based pwm
for modulation for multilevel converter, which is used to reduce the total

xxviii
harmonic distortion and improve the power quality. A various modulation
techniques are used in this method.

Fang ZhengPeng, “A Generalized Multilevel Inverter Topology with Self

Voltage Balancing,”IEEE Trans.Ind.Appl.,Vol.37,no.2,March/April 2001.
This paper presents reduced number of switches for asymmetrical
multilevel inverter. The disadvantage is that the small voltage steps are
typically produced by isolated voltage source.
S.Mekhilaf and A.M.Omar, “Modeling of Three Phase Uniform
Symmetrical Sampling Digital PWM for Power Converter,” IEEE Trans.
Ind. Electron, Vol.54, no.1, PP.427-432, Feb 2007.
This paper introduced a multilevel converter, which has reduced the number
of switches, harmonics and cost and improves the power quality and efficiency.
Mariusz Malinowski, K.GopaKumar, Jose Rodriguez and Marcelo
A.Perez, “A Survey on Cascaded Multilevel Inverters”, IEEE Trans. On
Ind. Electrons, Vol.57, no. 7, July 2010.
This paper developed a multicarrier pulse width modulation based
cascaded inverter, which works in minimum voltage to improve the harmonic
performance of the output voltage and efficiency.
S.Malathy, U.Shajith Ali, “Performance Analysis of Multi-Carriers PWM
based Cascaded Multilevel Inverter”, Vol.22, pp.32-40, 2012.This paper
developed introduced a cascaded multilevel inverter to achieve a high quality
output voltage.
Here the numbers of voltage levels are increased and the power
electronic components are reduced. From this the lower harmonics
Nho-Van, Nguyen, Bac-Xuan Nguyen and Hong-Hee Lee, “An Optimized
Discontinuous PWM Method to Minimize Switching Loss For Multilevel
Inverters”, copyright (c). IEEE 2009.

xxix
 This paper proposed a discontinuous pulse width modulation method for
multilevel inverter to reduce the switching losses, harmonics and improves the
efficiency.
J.Rodriguez, J.Lai and F.Peng, “Multilevel Inverter: A Survey of
topologies, controls and applications,” IEEE Trans. On Ind. Electronics,
Vol.49, no.4, PP.724-738, 2002.
They introduced various topologies which controls of multilevel inverter. The
main advantages are lower harmonic components, lower switching losses and
improves power quality.
J.Rodriguez, S.Kouro, J.Rebolledo and J.Pontt, “A Reduced Switching
Frequency Modulation Algorithm for High Power Multilevel Inverter,”
IEEE Trans. Ind. Electron, 2005.This paper developed an algorithm for high
power multilevel inverter used in frequency modulation. For high power
application, there are many problems occur in asymmetrical multilevel inverter.
But it can produce lower harmonics for high switching frequencies.
Rajesh Gupta, ArindamGhosh and Avinash Joshi, “Switching
Characterization of Cascaded Multilevel Inverter Controlled Systems,”
IEEE Trans. Ind. Electron, Vol.55, no.3, March 2008.
This paper proposed the characteristics of controlled systems, which results
in the reduction of number of switches, harmonics, losses, installation area and
converter cost.

No.of level 2S+1 2S+1-1 3S

S=No.of stage 7 level 15 level 27 level
S=3
Input Dc voltage Vdc 2s-1 Vdc 3s-1 Vdc
1 Vdc 4Vdc 9Vdc

K.Surya Suresh and M.Vishnu Prasad, “Analysis and Simulation of New

Seven Level Inverter Topology”, Inter. Jou. Of Scientific and research
publications, (ISSN 2250-3153), Vol.2, Issue.4, April 2012.
xxx
 This paper introduced a new topology for conventional H-bridge
multilevel inverter.

CHAPTER-3
PROPOSED TOPOLOGY
3.1 PROPOSED SOLUTION
 Newer Topology of MULTILEVEL inverter
 We have to reduce the total harmonic distortion as much as possible.
 By this we can :
 Increase the performance of drive.
 Increase the efficienc

Tab.3.1 Comparison between Hybrid and New Hybrid Inverter

3.2 TRINARY MULTILEVEL INVERTER
The proposed asymmetric multilevel inverter can be shown in the fig.3.1.
Each phase consists of two conversion cells and H-bridge. Each cell consists of
V1, and V2 voltages connected in cascaded form. This inverter consists of 24
switches. Depending upon the switching condition the positive and negative
polarity output will be produced by the H-bridge.
Expected output voltage level,
Vn=3n , Where n=number of stages

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 Figure.3.1 Proposed Multilevel Inverter

3.3 OPERATION
The proposed asymmetric cascaded Trinary multilevel inverter consists of

two full Bridges. The first full bridge consists of a DC source 1V DC, while the

second full bridge consists of a DC source 3V DC as shown in Figure1. Every

DC source is associated to a three phase Trinary inverter. Every inverter level

can produce a three dissimilar voltage outputs, positive level, zero level, and

negative level by dissimilar combining of the four switchesT1, T2, T3 and T4.

Whenever switch T1 and T4 are turned ON, then the output voltage is

positive VDC, whenever T2 and T3 are turned ON, then the output voltage is

negative VDC, whenever anyone pair of switch T1 and T2 or T3and T4 are

turned ON, then the output voltage is zero VDC.

Then the output voltage of the first full bridge can be made equal to

negative 1VDC, 0 VDC, or positive 1VDC, while correspondingly then the output

voltage of the second full bridge can be made equal to negative 3Vdc, 0VDC, or

positive 3VDC by opening and closing its switches properly. Therefore, then the
xxxii
 output voltage of the inverters can have the values −4VDC, −3VDC, −2VDC,

−VDC, 0, 4VDC, 3VDC, 2VDC, VDC, can be produced, as shown in Figure 1. Then

the output voltage of the first bridge is indicated by V1 and the second full

bridge is indicated by V2. Then the final output voltage is V= 1V DC+3VDC.The

firing signals for a selected nine level inverter is generated with help of

MATLAB-SIMULINK. The development of firing signals and it is qualified

for a different value of modulation indices ma and for a variety pulse width..

CHAPTER-4
PULSE WIDTH MOULATION TECHNIQUES
4.1 INTRODUCTION
Fundamental Frequency switching PWM
 Sinusoidal PWM
 Space vector PWM
 Selective harmonic elimination
4.2PWM CONTROL STRATEGIES:
4.2.1 SINUSOIDAL PULSE WIDTH MODULATION SCHEME
This scheme consists of three bipolar PWM strategies. The reference is
the sine signal and carrier is the triangular signal. The multicarrier is positioned
above zero level and the carriers are depending upon the output voltage levels.
For m level inverter, (m-1)/2 carriers are used.
The three Bipolar PWM strategies are
 PD(Phase Disposition)
 APOD(Alternative Phase Opposition Disposition)
 CO(Carrier Overlapping)
 VF (Variable Frequency)
The advantages of this scheme is

xxxiii
 Reduces the harmonics
 Efficiency is high
 Increase the drive performance
4.2.1.1UNIPOLAR SINUSOIDALPHASE DISPOSITION PWM
(USCPDPWM):
BSPDPWM strategy uses (m-1) triangular carriers with the same frequency f c
and same peak-to-peak amplitude Ac which are disposed so that the bands they
occupy are contiguous.

The carrier set is placed above the zero reference. Two modulation
waveforms having amplitude Am and frequency fm. and it is centred about the
zero level and are used to sample the triangular carriers to generate the gating
pulses. The carrier arrangement for nine level inverter using BSPDPWM is
shown in Fig.4.1
Amplitude of modulation index can be given by
ma=Am/Ac
Frequency ratio is
mf=fc/fm
Where,
fc= frequency of carrier signal
fm=frequency of reference signal
Am=amplitude of reference signal
Ac=amplitude of carrier signal

xxxiv
 Figure.4.1 Carrier arrangement for USPDPWM strategy(ma=0.85 and mf=50)
4.2.1.2 UNIPOLAR SINUSOIDAL ALTERNATIVE PHASE
OPPOSITION DISPOSITION PWM (USAPODPWM):
For m-level inverter, the carriers are arranged in 180 degree out of phase. The
carrier arrangement for nine level inverter using BSAPODPWM is shown in
Fig.4.2
Amplitude of modulation index can be given by
ma=Am/Ac
Frequency ratio is
mf=fc/fm
Where,
fc= frequency of carrier signal
fm=frequency of reference signal
Am=amplitude of reference signal
Ac=amplitude of carrier signal

xxxv
 Figure.4.2 Carrier arrangement for USAPODPWM strategy(ma=0.85 and
mf=50)
4.2.1.3 UNIPOLAR VARIABLE AMPLITUDE CARRIER
OVERLAPPING IN PHASE DISPOSITION WITH SINUSOIDAL PWM
(USPDPWM):
In this scheme all carriers have the same frequency, same phase and
changeable amplitude. This method is also called as Variable Amplitude Carrier
Overlapping In the Phase Disposition Pulse Width Modulation (VACOIPD)
system shown in figure 4.3. Since all the carriers are preferred with the same
phase, in this technique is related to conventional In Phase Disposition control
scheme apart from with changeable amplitude and carrier overlapping of A c/8=
0.5, where Ac=2 is the carrier amplitude of the carrier. It is originated from
literature review of that this pulse width modulation technique providing a
lesser value of total harmonic distortion and reasonably higher value of
fundamental RMS output voltage while comparing to above established carrier
overlapping pulse width modulation system.

xxxvi
Figure.4.3 Carrier arrangement for USAPDPWM strategy(ma=0.85 and mf=50)
4.2.1.4 UNIPOLAR SINUSOIDAL VARIABLE AMPLITUDE CARRIER
OVERLAPPING ALTERNATIVE PHASE OPPOSITION DISPOSITION
PWM (USAPODPWM):
In this topology, the carriers are 180 degree alternation phase displaced
from each other. It may be recognized as pulse width modulation with an
amplitude overlapping and neighboring phases are interleaved carriers. Really,
then the pattern of VCOIPD and VCOPOD has been looked on as a second
control freedom transforms besides offsets in vertically: the carriers' has a
horizontal phase shift from pattern of VACOIPD. This method is also called as
Variable Amplitude Carrier Overlapping Alternate Phase Opposition
Disposition Pulse Width Modulation (VACOAPOD) system shown in
figure.4.4. Since all the carriers are preferred with the out of phase, in this
technique is related to conventional In the Phase Disposition control scheme
apart from with changeable amplitude and carrier overlapping of A c/8= 0.5,
where Ac=2 is the carrier amplitude of the carrier.

xxxvii
 Figure.4.4 Carrier arrangement for USAPDPWM strategy(ma=0.85 and
mf=50)
27

CHAPTER-5
SIMULATION RESULTS
5.1 SIMULATION CIRCUIT

xxxviii
 Fig.5.1 Simulink model of proposed multilevel inverter
The three phase asymmetrical cascaded multilevel inverters with Trinary DC
sources nine level inverters are modeled in SIMULINK using power systems
block set. The Switching signals of asymmetrical Trinary multilevel inverter
using bipolar pulse width modulation technology are simulated.
Simulations are performed for a choice of ma varied from 0.8 to 1 and
the resultant %THD is measured using the FFT block and their values are
shown in Table 1. Table 5 shows the fundamental Vrms of inverter output
voltage for similar values of modulation indices. Table 3 and 4 shows the
consequent values of crest factor and form factor. Table 2 shows the percentage
distortion factor of the inverter output.
Figures 8-19 shows the simulation output voltage and FFT plot of an
asymmetrical cascaded multilevel inverter with Trinary DC source and their
appropriate harmonic order of a spectrum with bipolar pulse width modulation
technology but for only one sample of the modulation indices.
For modulation indices (ma=0.85) it is observed from the figures (9, 11,
13, 15, 17 and 19) the harmonic energy level is governing in: Figure 9
represent the harmonic energy level in COIPD PWM techniques shows 40 th
order of harmonic. Figure 11 represent the harmonic energy level in COPOD
PWM techniques shows 38th 40th order of harmonic. Figure 13 represent the
harmonic energy level in COAPOD PWM techniques shows 29 th, 31st, 39th
order of harmonic. Figure 15 represent the harmonic energy level in VACOIPD
PWM techniques shows 40th order of harmonic. Figure 17 represent the
harmonic energy level in VACOPOD PWM techniques shows 39 th 40th order of
harmonic. Figure 19 represent the harmonic energy level in COAPOD PWM
techniques shows 29th, 31st, 35th and 39th order of harmonic.Simulations are
performed for various values of m a ranges from 0.8 to 1 and the results are
obtained by using following parameter such as Vdc = 25V , 3Vdc = 75V, load
resistance is 100Ω, carrier frequency fc is 2000Hz, carrier amplitude Ac1 is 1.5
and Ac2 is 2 and modulation frequency fm is 50Hz. VACOPID, and VACOAPOD

xxxix
pulse width modulation techniques no more than one pulse modulation
techniques such as (Carrier overlapping alternate phase opposition disposition)
it hold minimum quantity of harmonic distortion. Table 5 and Figure 21
represent the VRMS contrast of COIPD, COAPOD, VACOPID and
VACOAPOD pulse width modulation techniques no more than one pulse
modulation techniques such as COP (Carrier overlapping Alternate Phase
Opposition Disposition) it hold maximum quantity of fundamental RMS output
voltage

Figure 5.2: Output voltages generated by carrier overlapping in phase

disposition PWM control with sinusoidal reference

xl
 Figure 5.3: FFT plot for output voltages of carrier overlapping in phase
disposition PWM control with sinusoidal reference

Figure 5.4: Output voltages generated by carrier overlapping alternate phase

opposition disposition PWM control with sinusoidal reference

Figure 5.5: FFT plot for output voltage of carrier overlapping alternate phase
opposition disposition PWM control with sinusoidal reference

xli
 Figure 5.6: Output voltages generated by variable amplitude carrier
overlapping in phase disposition PWM control with sinusoidal reference

Figure 5.7: FFT plot for output voltage of variable amplitude carrier
overlapping in phase disposition PWM control with sinusoidal reference

xlii
 Figure 5.8: Output voltages generated by variable amplitude carrier
overlapping alternate phase opposition disposition PWM control with
sinusoidal reference

Figure 5.9: FFT plot for output voltage of variable amplitude carrier
overlapping alternate phase opposition disposition PWM control with
sinusoidal reference
Table 1: % THD for Different Kind of Modulation Indices
Sine Reference
ma
COIPD VACOIPD COAPOD VACOAPOD
1 20.67 20.87 22.02 19.96
0.95 22.02 22.64 23.67 21.75

xliii
 0.9 23.48 24.44 25.36 23.47
0.85 24.89 26.98 27.18 25.24
0.8 26.62 29.53 29.52 29.95

Table 2: Distortion Factor for Different Kind of Modulation Indices

Sine Reference
Ma
COIPD VACOIPD COAPOD VACOAPOD
1 0.005889304 0.006585086 0.002982 0.002271
0.95 0.004651257 0.006790328 0.001929 0.001215
0.9 0.003384598 0.006877493 0.002178 0.000762
0.85 0.001994265 0.007320252 0.002178 0.00143
0.8 0.001272022 0.007846039 0.005569 0.001702
Table 3: Crest Factor for Different Kind of Modulation Indices

Ma
CF 1 0.95 0.9 0.85 0.8
COIPD 1.4144291 1.4144834 1.4141829 1.4142989 1.41410
COAPOD 1.4120372 1.4133674 1.4142794 1.4142455 1.41432
VACOIPD 1.4144291 1.4144835 1.4141829 1.4142989 1.41413
VACOAPOD 1.4120371 1.4133674 1.4142794 1.4142455 1.41432

xliv
 Table 4: Form Factor for Different Kind of Modulation Indices

Ma
FF 1 0.95 0.9 0.85 0.8
49.42670 1.1704
COIPD 58.017309 49.567039 5 45.509487 8
95351856 91495715 13876.41 82298496 1.0421
COAPOD 7 4 6 0 5
49.42670 1.1704
VACOIPD 58.017309 49.567039 5 45.509487 8
95351856 91495715 13876.41 82298496 1.0421
VACOAPOD 7 4 6 0 5

CHAPTER 6

xlv
 ADVANTAGES
MULTILEVEL CASCADE INVERTER IS DISCUSSED TO
ELIMINATE

(1) Bulky transformers required by conventional multi pulse inverters,

(2) Clamping diodes required by multilevel diode-clamped inverters, and

(3) Flying capacitors required by multilevel flying-capacitor inverters.

(4) The Regulation of DC buses is simple

FEATURES OF MULTILEVEL CASCADE INVERTER

(1) It is much more suitable to high-voltage, high-power applications than the

conventional inverters.

(2) It switches each device only once per line cycle and generates a multistep
staircase voltage waveform approaching a pure sinusoidal output voltage by
increasing the number of levels.

(3) Since the inverter structure itself consists of a cascade connection of

many single- phase, full-bridge Inverter units and each bridge is fed with a
separate DC source, it does not require voltage balance circuits or voltage
matching of the switching devices.

xlvi
 CHAPTER 7
APPLICATIONS
 UPS
 Adjustable Speed Drives
 HVDC System
 Industrial Application

xlvii
 CHAPTER 8
CONCLUSION
In this Project, a nine level multilevel inverter has been developed using
MATLAB/SIMULINK. A proposed asymmetric multilevel inverter gives
higher output voltage level. The Performance parameters like %THD, V rms, CF
and FF have been analysed and presented. From that the UPD technique
provides lower %THD and Vrms is higher in BSAPOD. From a high voltage
level with low distortion performance of induction motor was increased.

xlviii
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