Product Datasheet
Version 1.0
December 15, 2017
CADENCE CONFIDENTIAL
Version 1.0 Cadence DDR Controller Product Databook December 15, 2017
The table below lists possible acronyms and terms used in this document.
Term Description
AHB Advanced High-Performance Bus, also known as AMBA 2, the 2nd generation of the AMBA pro-
tocol
AMBA™ Advanced Micro-controller Bus Architecture, a JEDEC bus interface standard
ASIC Application-Specific Integrated Circuit
AXI Advanced Extensible Interface Bus, also known as AMBA 3 or AXI 3, the 3rd generation of the
AMBA protocol
AXI3 The 3rd generation of the AMBA protocol
AXI4 The 4th generation of the AMBA protocol
BIST Built-in self test, a hardware logic scheme which allows chip testing to identify certain types of
memory faults
DED Dual-error detection, a subset of ECC where it is known that exactly two bits are erroneous, but
the exact bits can not be identified
Denali Protocol A privately developed bus interface now owned by Cadence Design Systems
DFI A JEDEC standard regulating the interface between a memory controller and a PHY
DFS Dynamic Frequency Scaling, a system to modify the operating frequency of a memory controller
without a full system re-initialization
DRAM Dynamic Random Access Memory
ECC Error Correction Code, a system for verifying accuracy of data
FIFO First-in, first-out, a hardware element that is used for storage of data
IP Intellectual Property
JEDEC An industry group that develops standards for microelectronics
LRDIMM Load-Reduction DIMM to support higher densities than RDIMMs and contains a memory buffer
chip instead of a register
MBIST Memory Built-in Self-Test
MOVI A BIST algorithm based on Computer Design Magazine’s May 1976 article “Moving Inversions
Test Pattern is Thorough, Yet Speedy” by J. Henk de Jonge and Andre J. Smulders
MOVI3N A BIST algorithm based on Computer Design Magazine’s May 1976 article “Moving Inversions
Test Pattern is Thorough, Yet Speedy” by J. Henk de Jonge and Andre J. Smulders
MRAM Magneto-resistive Random Access Memory, memory that stores its information using magnetic
charges
NVM Non-volatile memory, memory that retains its data even if power is removed
PCPCS Power Control Per Chip Select
PHY Physical layer, the IP that interfaces between the memory controller and the actual memory
device
QoS Quality of Service signals, specific to the AXI4 interface
RDIMM Registered Memory
RDL Register Description Language
RTL Register-Transfer Level, the high-level logic provided from Cadence
SEC Single-error correction, a subset of ECC where the exact bit that is erroneous can be identified
SoC System on a Chip
SoDimm Small-outline DIMM
SRAM Static random-access memory, memory that retains its data as long as power is constant and
does not require refreshes
ST-MRAM Spin-Torque MRAM
STA Static Timing Analysis
SSTE32882 A control chip specific to DDR3 memories
Trustzone™ An ARM standard of a hardware-based security logic
UDIMM Unregistered memory
XML Extensible Markup Language
ZQ A calibration method which connects a precision resistor to the ZQ ball of each DRAM to calibrate
output driver impedance across process, temperature and voltage
1 General Information
Devices today require quick response time and high resolution images, resulting in electronics systems processing higher volumes of data
and video. The Cadence Denali® DDR Controller addresses these critical bandwidth requirements by providing low latency and
throughput up to 4266 Mbps while supporting extensive value added features, including reliability.
The Cadence Denali® DDR controller is configurable for different market segments and supports a range of memory classes and data
rates. The controller maximizes the performance of lower-cost DRAM devices and reduces the overall product bill of materials. Developed
by experienced teams with industry-leading domain expertise and validated with multiple hardware platforms, the Cadence Denali® DDR
Controller is silicon proven and can provide customers with ease of integration and faster time-to-market.
Cadence is an active member of the JEDEC standards organization. Cadence can provide IP for emerging standards early in their life
cycles, and can identify and adapt to important changes to published standards. Table 1 lists the standards that the Cadence Denali® DDR
Controller IP supports.
Table 1: Supported Standards
Standard Supported Versions or Types
JEDEC JESD209-4, JESD209-3, JESD209-2, JESD209, JESD79-4, JESD79-3 plus
extensions, JESD79-2 and extensions, JESD79-1
DFI 1.0, 2.0, 2.1, 3.0, 3.1, 4.0
System Bus AMBA 2 (AHB), AMBA 3 (AXI), AMBA 4 (AXI4), Denali Protocol
DIMMs UDIMMs, SoDIMMs, RDIMMs, and LRDIMMs (DDR4)
2 Benefits
• Maximum flexibility with highly configurable and programmable solution supporting multiple protocols and features
• Configurable to generate application optimized DDR controller configurations
• Providing maximum data throughput and lowest latency across various applications
• High reliability supported by error correction and error identification features
-- Setting of different priorities for each command that goes to the controller. This benefit improves latency and controller quality
of service (QoS), especially for transactions that arrive through an interconnect fabric.
-- Setting a closed-page policy for transactions with low locality of reference and setting an open-page policy for transactions
with a high locality of reference. These policies optimize power and latency for mixed transaction types within an SoC.
• ECC scheme of Single-Error-Correction, Double-Error-Detection (SEC-DED) for 32 or 64 bits on buses of 16, 32, or 64 bits
• Capability for operation on full or half data width while retaining the same memory map
-- Low-latency synchronous
3 Applications
The Cadence Denali® DDR Controller is configurable for different market segments and supports a range of memory classes and data
rates. The controller maximizes the performance of lower-cost DRAM devices and reduces the overall product bill of materials.
The controller maximizes performance with the lowest possible power. It also delivers quality of service, advanced error correction, data
protection, and connectivity to UDIMM, SoDIMM, and RDIMM. The controller works with the memory to support the following uses and
products:
There is a limitation on minimum supported frequency for DDR protocols that is defined by JEDEC;
• DDR4: 600 MHz
• DDR3: 333 MHz
• LPDDR4: 10 MHz
• LPDDR3: 10 MHz
BIST
Option
PHY External
Command
Arbitration Transaction Memory
Queue
Processing
Placement
AHB,
Logic
AXI,
AXI4 or Priority
DEN Engine Command Clocks
Port Selection and
Interface Logic Reset
Look-Ahead
Write Queue Optimization
Read Queue
The multi-port memory controller offers a high degree of flexibility and low latency not typically found in other memory controller or
interconnect solutions. The multi-port controller can be configured to support a mix of ASIC-side port interface types—AXI4, AXI, or AHB,
or a combination.
Each port can have configurable widths and programmable synchronicity. Each port can have its own command and data FIFOs that allow
for different speed masters elsewhere on the SoC. The multiport solution for multiple port types uses combinational logic to communicate
with the appropriate port protocols without the latency associated with traditional bridge solutions. Up to 32 ports are supportable.
An AXI port communicates on the standard AXI bus and functions as an AXI slave to external AXI masters, such as CPUs, DMAs, DSPs,
and other peripherals. The QoS inputs are supported for AXI4. In AXI3, a sideband is available for performing priority-per-command
operations.
An AHB port communicates by using the standard AMBA AHB-Lite bus protocol and functions as an AHB slave to external AHB masters.
The port implementation is designed for Multi-Layer AHB architectures. Because AHB is a single-threaded protocol, AHB ports are used
in only multi- port controllers.
A native port uses a simple hand-shake protocol to provide an efficient and high- performance interface. Native ports are synchronous
only and can be used with either single- or multi-port controllers.
For AXI or AHB ports, each port on the memory controller has four firmware programmable modes of operation as follows:
• Synchronous: The port clock and the controller core clock must be aligned in frequency in phase. The controller port interface block
is not required to perform any clock synchronization in any of the FIFOs.
• 1:2 Port: Core Pseudo-Synchronous: The port operates at half the frequency of the controller’s core frequency, with clocks that are
aligned in phase.
• 2:1 Port: Core Pseudo-Synchronous: The port operates at twice the frequency of the controller’s core frequency, with clocks that
are aligned in phase. One stage of the two-stage synchronization logic of the FIFOs is to be used for synchronizing commands,
writing data, and reading data to the appropriate clock domain.
• Asynchronous: The port bus and the controller core operate on clocks that are mismatched in frequency and phase. The port FIFOs
use two to five configurable stages of synchronization logic for synchronizing commands, writing data, and reading data to the
appropriate clock domain.
For low power DRAM and some designs that use very high speed libraries, Cadence offers the “Matched Frequency” option, sometimes
called a “2:1 Controller”, where the memory controller clock is synchronized with the PHY clock and DRAM clock. In this configuration, the
on-chip busses are nominally 2x the nominal memory data width. However, the busses are configurable to equal the nominal memory
width.
For high-speed DRAM and some designs that use low power libraries, Cadence offers the “High-Frequency” option, sometimes called a
“4:1 Controller”, where the PHY and DRAM operate at double the memory controller frequency. In this configuration, the on-chip busses
are nominally 4X the nominal memory data width. However, the busses are configurable to be double the normal memory width.
The DFI training interface enables increased accuracy at higher speeds in the alignment of critical timing signals on DDR4, DDR3, DDR2,
DDR1, LPDDR4, LPDDR3, LPDDR2, and LPDDR1 devices. The MC is compliant with the DFI 4.0, 3.1, 3.0, and 2.1 specifications. The
programmable parameters are options defined by the MC, PHY, or system, and programmed into the MC, the PHY, or both.
Note: The DFI protocol does not encompass all of the features of the MC or the PHY, nor does the protocol put any restrictions on
how the MC or the PHY connect to other parts of the system.
4.3 Arbiter
The Arbiter arbitrates requests from the ports and sends requests to the controller core. Each transaction that the Arbiter receives from
the port has an associated priority. The associated priority works with each port's arbitration logic for determining how ports issue requests
to the controller core. The Cadence Denali® memory controller can be configured to support any one of the following arbitration schemes:
• Simple Round-Robin: This system uses a counter that rotates through the port numbers, incrementing every time a port request is
granted and returning to zero when no more arbitrations remain to perform. This arbitration is ideal for systems that do not require
requests to be treated preferentially for maintaining bandwidth or minimizing latency.
• Bandwidth Allocation/Priority Round-Robin: this system combines the concepts of round- robin operation, priority, bandwidth, and
port bandwidth hold-off. The incoming commands are separated into priority groups, based on the user-assigned command priority.
Within each priority group, the Arbiter evaluates the requesting ports, the command queue, and the priority of the requests for
determining the priority of the arbitration. Ports that exceed their bandwidth allocation might receiver lower priority servicing when
the controller is busy.
• Weighted-Priority Round-Robin: This quality-of-service (QoS) oriented algorithm combines the concepts of round-robin operation,
priority, relative priority, port ordering, and relaxation. The incoming commands are separated into priority groups, based on the
command priority or the priority of the associated port for that type of command. Ports with higher weights might receive arbitration
more often to allow ratioed access. Relaxation prevents lockout by periodically servicing lower-priority transactions.
Placement of and removal from the various memory low power modes is controlled through programming of registers in the Cadence DDR
Controller. You can monitor the status of the memory devices also through a programmable register. This interface supports a lock option
where the arbiter does not release the low power control module and the user may execute additional commands through this interface
without worrying about state changes through other interfaces.
Placement of and removal from the various memory low power modes is controlled through top-level signals on the Cadence DDR
Controller. The user will request control of the low power module, and once granted, will send a command through another signal. The
state change will be acknowledged and the user must manually release a request signal to release the low power control module.
Hardware dynamic frequency scaling are supported through this interface.
Automatic interface:
This interface is a separate configuration option when the low power option is chosen. If selected, counters in the logic will monitor idle
cycles and place memories into low power modes based on counter expiration. The counter values are controlled through programmable
registers.
All Cadence controllers support a full look-ahead facility that reduce the effect of page misses by pre-conditioning rows for upcoming
requests by using “spare” cycles in preceding transactions. The size of this look-ahead window can be program-set.
The 2-stage placement queue determines the order that commands run in the controller core. The placement logic follows many rules for
determining placement of new commands into the queue, relative to the contents of the command queue at that time. Placement is
determined by considering coherency, address collisions, source collisions, data collisions, user-assigned priority, latency, age, and
command type to offer low latency for critical masters while optimizing bandwidth for all masters. A second reordering stage allows ready-
to-run commands to start even if the head-of-queue command is not yet ready to run.
Many of the rules used in placement can be individually enabled and disabled from firmware. In addition, the queue can be disabled
completely, resulting in an in-line queue that services requests in the order that they arrive.
Commands for running are based on bank readiness, availability of at least 1 burst of data (writes), availability of storage for at least 1
burst of data (reads), bus turnaround timing (JEDEC-specified and programmable), and conflicts. Similar to the placement rules, a
command does not run before a command that was placed ahead of it in the command queue if it conflicts with address, source ID, or
bank commands. Lower priority commands can run ahead of higher priority commands if the higher priority commands are not ready to
run, as long as they do not conflict with commands that are ahead in the command queue.
The figure below shows the command selection logic, relative to the rest of the placement logic.
Figure 1. Selection Logic
Command Queue
If the BIST option is included in the controller, it is a firmware register-controlled initiation, and the BIST results are reported back to the
register map. BIST testing is controlled through programming. The controller supports BIST on ECC lanes for out-of-band ECC
configuration.
The Controller can detect single-bit and double-bit data errors, and can correct single-bit errors. The logic is user-controllable to support
interrupts, register storage of ECC error signatures, signaling of ECC errors, ECC scrubbing and write-back, automatic ECC corruption
and ECC error forcing.
The controller can support both inline ECC and out of band ECC. In Inline ECC, a portion of the memory device connected to the controller
is reserved for storing the ECC check codes and is not available to the user. For out-of-band ECC, a separate memory device is used to
store the ECC check codes.
ECC operation does not change the functionality of the SoC buses, which maintain their address mapping and width whether ECC is
enabled or not. If the ECC option is included in the Cadence controller, it can be enabled or disabled through programming. When enabled,
all read data is checked for ECC (and optionally corrected) and ECC is computed and stored on all write data. Single-bit errors can be
corrected and double-bit errors can be flagged. ECC information is not returned and ECC scrubbing is supported to maintain memory
contents.
• ZQ calibration
• Address mirroring
• Address Inversion
• Support for registered DIMMs (RDIMM)
• Support for load-reduced DIMMs (LRDIMM)
The mapping of the address space to the internal data storage structure of the DRAM memories is based on the actual size of the DRAM
memories available. The size is stored in user-programmable parameters that must be initialized at power up.Certain DRAM memories
allow for different mapping options to be chosen, while other DRAM memories depend on the memory burst length chosen.
Autoprecharge-per-command allows you to mark a particular master or transaction (for example, a CPU cache) as a closed-page
transaction. This type of transaction reduces power and improves latency for the next transaction to a different row in the same DRAM
bank. Other transactions (for example, DMA transactions) can be marked as open-page transactions. This type of transaction reduces
power and improves latency and bandwidth to the next transaction to the same row in the same DRAM bank.
The port clock and the controller core clock must be aligned in frequency in phase. The controller port interface block is not required
to perform any clock synchronization in any of the FIFOs.
• 1:2 Port:Core Pseudo-Synchronous
• 2:1 Port:Core Pseudo-Synchronous
The port operates at half or twice the frequency of the controller core frequency, with clocks that are aligned in phase. One
stage of the two-stage synchronization logic of the FIFOs is used to synchronize commands, write data, and read data to the appropriate
clock domain.
• Asynchronous
The port bus and the controller core operate on clocks that are mismatched in frequency and phase. The port FIFOs use two to
five configurable stages of synchronization logic to synchronize commands, write data, and read data to the appropriate clock
domain.
The Cadence Denali® DDR Controller expects to receive an external clock input from the ASIC clock tree. The controller uses a clock
forwarding scheme where a clock is input into the controller from an on-chip source (likely to be a PLL) and then the PHY drives the clock
to memory. The controller also supports system clock frequency change by initiating the change through the controller’s low power
interface.
6 Configuration Options
The Cadence Denali DDR Controller offers a high degree of flexibility and low latency not typically found in other controller or interconnect
solutions. Most elements in the Controller are configurable or resizable to match the exact system needs. During the specification process,
you can select desired features and specify options; the Controller RTL, scripts and documentation are then customized to match those
selections.
Buses are configurable for type, width, FIFO arrangement, synchronization, and more. After the buses are configured, programming
controls further behavior. Depending on configured options, a Controller may contain bridge blocks to translate various protocols to native
protocols, interface blocks with FIFOs and arrays for storage; an arbitration block to control multiple port requests; and all the logic to
handle clocking and communication with the memory devices. Each interface supports the majority of the protocol, with very few
limitations. You can limit the size of the logic by de-selecting features of each protocol such as the synchronization of each port, parity,
exclusive access, locked access and address protection regions, and also by minimizing the sizes of FIFOs within each port.
Table 3 shows the parameters that you select during the specification process and Table 4 shows the programmable or definable options.
Table 3: Parameters
Parameter Description Option
Product
Memory Class Multiple combinations are possible. DDR1, LPDDR1, DDR2, LPD-
DR2, DDR3, LPDDR3, DDR4,
LPDDR4, DDR3/2 Combo, LPD-
DR3/2 Combo, DDR4/3 Combo,
LPDDR4/3 Combo, LPDDR4/
DDR4 Combo, Custom
Architecture
Port Interface Single port with in order command queue: Single port interface to the SoC. With Single port with in order com-
an in order command queue, the commands in the command queue will be pro- mand queue
cessed in the order it was received. In order queue is used when incoming com- Single port with placement com-
mands are already optimized or traffic patterns are such that out of order mand queue
placement is not required. In order command queue is only available with Denali Multi-port with placement com-
SoC ports. mand queue
Single port with placement command queue: Single port interface to the SoC.
The placement command queue uses the out-of-order placement of commands
for improved bandwidth performance.
Multi port with placement command queue: More than one port interface to the
SoC. The placement command queue uses the out-of-order placement of com-
mands for improved bandwidth performance.
Width of Memory Bus This selection is only for the data bits and should not include any ECC bits. 16, 32, 64
(bits)
Max memory clock You can specify a maximum target speed for the Controller. This value should 200 (DDR-400), 400 (DDR-800),
frequency (MHz) be based on the maximum frequency of the memory devices being used. 533 (DDR-1066), 666 (DDR-
1333), 800 (DDR-1600), 933
(DDR-1866), 1066 (DDR-2133),
1200 (DDR-2400), 1333 (DDR-
2667), 1400 (DDR-2800), 1600
(DDR-3200), Custom
Interfacing
Table 3: Parameters
Parameter Description Option
Number of CPU You may have a mix of different ports for the AMBA interfaces (AXI4, AXI3 and AXI4: None, 1, 2, 3, 4, 5, 6, 7, 8,
Ports AHB). The AMBA interfaces may not be mixed with Denali ports. A Denali type Custom
port is a simple proprietary interface. AXI3:None, 1, 2, 3, 4, 5, 6, 7, 8,
Custom
AHB: None, 1, 2, 3, 4, 5, 6, 7, 8,
Custom
DEN: None, 1, 2, 3, 4, 5, 6, 7, 8,
Custom
DQ:DQS Ratio The Controller can provide support for memories with both 4:1 and 8:1 data to 8:1
data strobe ratios. Unless by-4 memories and a by-4 PHY are being used, you 8:1 and 4:1
must optimally disable this option. Adding this feature does impact area and the
Controller/PHY pin count. If the option is selected, the actual ratio to be used will
be defined through programming at power-up
4:1 DQ:DQS ratio is required to support x4 memories. Nibble masking is not sup-
ported. With a 4:1 ratio, the DM pins become differential pins and are used for the
additional DQS. 8:1 DQ:DQS ratio supports both x8 and x16 memories.
DIMM Support Select DIMM option. LRDIMM is currently only supported for DDR4. UDIMM
RDIMM, UDIMM
LRDIMM, RDIMM, UDIMM
None
System Interface
DFI Frequency Ratio The Cadence DDR Controller supports all versions of the DFI specification. Dif- 2:1 Ratio: Controller operates at
ferent versions of the specification have different interfaces, supported features, half the clock frequency of the
and timing requirements. The specific version of the specification that is sup- DRAM
ported by a configuration is limited based on the newest generation of memory 1:1 Ratio: Controller operates at
supported. Match the DFI version supported by the PHY or ensure that the ver- the same clock frequency with
sion chosen is compatible with the PHY. DRAM
Memory BIST Sup- This is a memory BIST used only to test the external DRAMs. This option will Yes
port report pass/fail, where the failure occurred and what the expected and received No
result was. The address test implements a walking ones test and the data test
implements a MOVI3n pattern.
Support for AXI bus Provides data path parity across the AXI interface for both read and write data Yes
parity and for command and response buses. No
Memory Device
Support for 3DS Supported for DDR4 only. Higher stack counts can support lower stack counts. No, 2H, 4H, 8H
Stack (e.g. 4H stack can support 2H stack). Note, higher stack counts will have a large
impact to compile times.
Number of Chip Select the total number of chip selects required. Non "power of two" number of 1, 2, 4, 8
Selects chip selects will be supported by the next higher "power of two" chip select selec-
tion. (e.g. The need for 5 chip selects will require a selection of 8 chip selects.)
Number of Ranks Applies only to 3DS systems. In all other memory classes, the number of ranks 1, 2, 4, 8, N/A
equals the number of chip selects.
Support for Per Rank Allows each rank to be leveled (Write leveling, read leveling, gate training) inde- Yes
Leveling pendently. Registers used to store timing information will be duplicated for each No
rank.
Max Number of Row These are the PC-DDR DRAM interface pins. Not applicable for LPDDR memory 12, 13, 14, 15, 16, 17, 18, Cus-
Address Pins class. tom
If you don't know, then select "Custom", and enter the information regarding the
devices you will connect to.
Max Number of Col- These are the PC-DDR DRAM interface pins. Not applicable for LPDDR memory 10, 11, 12, Custom
umn Address Pins class.
If you don't know, then select "Custom", and enter the information regarding the
devices you will connect to.
Power
Low Power Support Applies to PC-DDR class memory controllers only. This option enables Automatic Yes
transition between low power modes and gated clock for the controller and mem- No
ory. This is automatically included with LPDDR class memory controllers.
Table 3: Parameters
Parameter Description Option
Support for Low Applies to LPDDR class memories only. Allows different chip selects to be in a Yes
Power per chip select different low power mode. No
Dynamic Frequency Low Power Support option is required for this feature. Implements hardware sup- 2 frequencies, 3 frequencies, 4
Scaling (hardware port for fast frequency changes. The controller timing registers are duplicated for frequencies, No
support) each frequency required.
Support for DFI Low Low Power Support option is required for this feature. Implements the DFI low Yes
Power Interface power interface to allow the PHY to be put in light sleep or deep sleep. No
Support for refresh Use cases include: Yes
per chip select 1. Heterogenous timing for different ranks that have different refresh timing. No
2. Refresh other inactive ranks while holding off the refresh on the active rank so
as not to interrupt current critical data transfers.
3. Reduce the peak current resulting from refreshing all chip selects simultane-
ously.
User Interface
Address Mapping Select the address mapping scheme. CS/Row/Bank is the most common. This is CS/Row/Bank
Scheme how AXI addresses get converted to DRAM addresses CS/Bank/Row
Bank Addressing Bits Applies only to DDR4. Bank/Bank Group is more common. Bank/Bank Group
Bank Group/Bank
ECC Support Single Error Correct, Double Error Detect (SECDED) ECC. No, ECC on 32 bits, ECC on 32
ECC over 32 bits adds 7-bits of checksum per 32 data bits. bits Region Specific, ECC on 64
ECC over 64 bits adds 8-bits of checksum per 64 data bits. bits, ECC on 64 bits Region Spe-
ECC protection can be enabled on a programmable region specific portion of the cific
address space.
Inline or out-of-band ECC
CRC Support Generates CRC on write and retries writes if CRC error identified by DRAM. Sup- Yes
ported only for DDR4. No
Arbitration Simple Round Robin: Each port gets the same level of priority. One command is Round Robin, Weighted Round
selected per port before looking at the next port. Robin, Priority Bandwidth Round
Weighted Round Robin: Can program the priority per port. For example, Port one Robin, None (Single Port)
can send two commands for every one command of port two.
Priority Bandwidth Round Robin: Can provide priority per port. Port with higher
priority gains arbitration. Can assign bandwidth limitations to prevent port lock
out. Port is held off if it exceeds its allocated bandwidth.
Port
Support of Priority Selectable for only AXI3 ports. This feature is always available for Denali and Yes
per Command AXI4 ports. Priority can be provided on a per command basis. Priority is provided No
through sideband signals. When this feature is not selected, priority is determined
on a per port basis. Read and writes can have different priority per port.
Support for write Enables out of order execution of write commands from the same port. Yes
command re-ordering No
within a port
Support for read data Implements a read data FIFO for each port. If not selected, one read data FIFO is Yes
FIFO per port placed in the controller for all ports. No
Width of SoC I/F Bus Each port can have a different data path width. Port 1: (16, 32, 64, 128, 256)
(bits) (Select one)
Port 2: (16, 32, 64, 128, 256)
(Select one)
Port 3: (16, 32, 64, 128, 256)
(Select one)
Port 4: (16, 32, 64, 128, 256)
(Select one)
Add additional ports as required
AXI/AMBA Data Port
Width of AXI ID Width of the IDs input from the AXI master (AWID, ARID, WID, RID and BID). The 4, 5, 6, 7, 8, Custom
minimum value for this option is 4.
Table 3: Parameters
Parameter Description Option
Support for Port Select the number of regions per port for address protection. Each port will have None, 2, 4, 8, 16, Custom
Address Protection a set of registers that specifies a valid address range and instruction type for
each port. Incoming port addresses are compared to the specified address range
for a specific instruction type. If it is out of range, a bus error will occur and the
controller will generate an interrupt. The error address, type and port numbers
are stored for debugging.
AMBA Protocol bus Manually enter the frequency in MHz of the speed the AMBA bus will be running
Clock Speed (MHz) at. This can be synchronous or asynchronous to the memory controller clock.
Denali Architecture
Maximum transfer Manually enter in the maximum transfer size in Bytes for the Denali port interface.
size (Bytes)
Width of Denali Specifies the maximum number of outstanding transactions. Minimum value is 4 4, 5, 6, 7, 8, Custom
Requestor ID Bus bits.
(bits)
Firmware Register Port
Register I/F Protocol Specify the bus protocol to be used for the register programming interface. AXI, AHB, DEN
If AHB is selected for SoC, Register I/F must be AHB.
If DEN is selected for SoC, Register I/F must be DEN.
If AXI is selected for SoC, Register I/F must be AXI or AHB
Width of Register I/F Select the width of the register programming interface bus in bits. 8, 16, 32, 64
Bus (bits)
Memory Datapath
Heterogeneous This is needed to connect to other types of memory (e.g. MRAM) and to imple- Yes
Memory Support ment different size devices per rank. This is automatically selected when MRAM No
is selected.
Heterogenous Tim- This is needed to connect to other types of memory that have different memory Yes
ing Support timing (e.g. MRAMs). This is automatically selected when MRAM is selected. No
Command Queue
Depth of Core Com- Select the depth of the memory controller command queue. Typical depth is 8. 2, 4, 8, 16
mand Queue Each entry stores a full transaction (not a burst). Larger command queue sizes
will make timing closure more difficult due to the larger logic needed for the place-
ment engine. Port command queues are separate from this.
Number of Priority Select the number of priority levels the command queue can support. Priority 2, 4, 8, 16
Levels level for read and writes can be specified separately.
7 Pin Description
The Cadence DDR Controller provides extensive top-level signaling between the ASIC and Controller, and the Controller and PHY.
Specific pins are configuration and feature dependent.
Table 5: Signal Groups
Signal Category Description
Controller Command/Data Interface Communication between the Controller and the ASIC including
Signals the low power interface (if configured)
Port Signals AXI, AHB or Denali interface-specific signals
Controller/SRAM Interface Signals Supports the use of an SRAM instead of FIFOs (if configured)
Controller Register Interface Signals AXI, AHB, APB or Denali interface-specific signals for register
communication
DFI Signals DFI communication signals. The Controller optionally supports
DFI versions 1.0, 2.0, 2.1, 3.0, 3.1 and 4.0
One set of the signals listed in Table 8, “Controller Command/Data (AXI Port) Signal List” exists for each AXI port.
dfi_init_complete PHY MC Note: Until the initialization complete interrupt (bit [4])
is set in the int_status parameter and the
dfi_init_complete signal is asserted from the PHY,
commands will not be accepted into the Cadence
DDR Controller core command queue.
dfi_init_start MC PHY MC frequency change request.
Low power acknowledge. The PHY is not required to
dfi_lp_ack PHY MC
acknowledge this request.
Low power opportunity request. This signal is used by
dfi_lp_req MC PHY the MC to inform the PHY of an opportunity to switch
to a low power mode.
Low power wakeup time. This signal indicates which
dfi_lp_wakeup MC PHY one of the 16 wakeup times the MC is requesting for
the PHY.
Defines the training pattern used for read leveling and
dfi_lvl_pattern_X MC PHY
CA training.
Indication from the MC to PHY whether the current
dfi_lvl_periodic MC PHY training command is for tuning or a full training
algorithm.
Memory on-die termination control signal for the
phase 0 information. This signal is the equivalent of
dfi_odt MC PHY
the dfi_odt_p0 signal mentioned in the DFI 4.0
specification.
Memory on-die termination control signal for the
dfi_odt_p1 MC PHY
phase 1 information.
One set of the signals listed in Table 8, “Controller Command/Data (AXI Port) Signal List” exists for each AXI port.
Because the Cadence DDR Controller is a very highly configurable product, exact area usage and power consumption information can
not be defined precisely. The following tables list performance and area data for three examples of the Cadence DDR4/3 and LPDDR3/
LPDDR4 Memory Controller.
Performance
Maximum clock frequency 800 Mhz
Maximum data transfer rate 3200 Mbps
Total estimated power
Leakage power 9 mW
Dynamic power 266 mW
Area
Total area 232481 um2
9 Testability
Cadence will deliver a fully regressed RTL suite to the customer. A script will be provided that will simulate a sample pattern and
demonstrate basic functionality of the Controller. This simulation is a limited scenario with a fixed memory burst length, pattern and
frequency and a pre-set memory part and CAS latency. Additional Cadence simulations will also be provided with a full delivery.
Cadence will also deliver synthesis scripts for the Cadence RTL Compiler and STA scripts for the Cadence Encounter Timing System.
The synthesis methodology used for the Cadence DDR Controller uses a top-down approach. Synthesis is done with a zero wire load
model and 25% over-constrain of the clock period. The ASIC is allocated a 1/3 clock period for the timing budget.
The synthesis script generates an SDC file which may be used in layout. Layout generates a gate-level net-list which is the input to the
STA scripts. The layout may need to be modified to resolve STA issues.
10 Deliverables
Cadence offers the High-Speed DDR PHY as a separate IP. If both controller and PHY are licensed then both IPs are
delivered as an integrated solution, making integration process much simpler. Before delivery, a full release flow is run to ensure IP
quality.
Table 21: List of Deliverables
Deliverables Description
RTL Verilog files Synthesize for all modules except data, address/control, and memory clock
slices
Verilog sample test that instantiates the memory controller, PHY, IO, Memory Model, DFI
Verilog test bench Monitor, and Verification IP.
If the Cadence PHY and IO are purchased with the controller, the integrated solution is
delivered. Otherwise, a behavioral PHY model is delivered with the controller.
Scripts are designed to create SDC inputs to layout and also validate timing of
Synthesis and STA scripts
final design.
Designed for integration which includes defines for the customer (*.h), register
Header files representation (*.rdl, *.xml), example programmings (regconfigs). define.h allows post-
configuration, pre-simulation changes to things like port FIFO depths.
Cadence High-Speed DDR Controller User Guide
Documentation Cadence High-Speed DDR Controller-PHY Integration Guide
RDL and XML files
Change Log