indicates that frequencies may be generated that are integer COUNT VALUE REDEFINITION
multiples of the reference frequency. The frequency generated
is determined by the divide ratio of the programmable divider. According to the state sequences for these counters shown in
This paper will first describe the design of a programmable Figure 2, they appear to be counting up instead of down. To
divider for an FM receiver. consider these counters as counting down, it is necessary only
to reassign the numeric value of each count state. In the
programmable divider application it is most convenient to con-
sider the numeric value assigned to each count state to be
equal to the 9's complement (or 15's complement) of the
PROGRAMING commonly accepted numeric value. If this reassignment is
f OUT INPUT made, then the counters appear to be counting down. This
ALt
assignment simplifies the switches required to program (preset)
the divider. The 9's complement and 15's complement coded
VOLTAGE FREQUENCY REFERENCE
digital switches are standard products.
PROGRAMABLE
CONTROLLED DIVIDER AND PHASE FREQUENCY
OSCILLATOR COMPARATOR GENERATOR BASIC PROGRAMMABLE DIVIDER
Figure 3 shows a three-stage, decade programmable divider that
is controlled by three 9's complement-coded, decade switches.
Only one two-input NAND gate is required in addition to the
Fig. 1. Basic digital frequency synthesizer. three MSI general purpose counters needed to perform this
programmable dividing function. The single two-input gate
utilizes the TC output of the most significant counter stage
FM DIGITAL FREQUENCY SYNTHESIZER and the Q3 output of the least significant counter stage to de-
REQUIREMENTS tect the 99810 state of the counter. The 99810 state corres-
ponds to the 00110 state when we perform the 9's complement
The FM broadcast band consists of 100 channels 200kHz wide conversion. When 001 10 state occurs, the output of the NAND
starting at 88.0 MHz. Therefore, the carrier for the first chan- gate goes low and the next clock pulse will preset (or parallel
nel is at 88.1 MHz, and the carrier for the last channel is 107.9 load) the counter to the value stored on the selector switches.
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X=-OOR 6
01 Q2 Q3
cpF [C°E PoPI P P13 -- 0 0 0
CEPI BASIC COUNTER 0 0 0
1 0 0
1 0 0
0 1 0
0 1 0
1 1 0
1 1 0
O 0 1
0 0 1 JTERMINAL
COUNT FOR
0 1 0 1 l 9310
CE COUNT ENABLE * INVERTERS USED ONLY IN 9310 1 1 0 1
CEP COUNT ENABLE PARALLEL 1316 0 0 1
CEP COUNT ENABLE TRICKLE 1 0 1 1
PE PARALLEL LOAD ENABLE
(COUNTER IS LOADED FROM Po-P3 ON NEXT CLOCK WHEN PE IS LOW)
O 1 1 1
I 1 1 TERMINAL
COUNT FOR
9316
FREQUENCY
INPUT FREQUENCY
OUTPUT
. L PE ~~~~~~P P2 P L PG Po Pi P2 P3 L PO P P1 P P3
l~~
~ ~ ~ ~ ~~~~~E 931 CE CEP 9310 tC p 9310 LI
MR 00 al Q2 03 -4 00 Ql'I 03 Gr MR 00 al OZ Q3l
This design satisfies the basic requirement of a programmable quency out of the mixer is selected as an input to the program-
divider, and will work quite well in many applications. How- mable divider. With heterodyne conversion, the 20 MHz width
ever, several modifications of this basic design are required for of the FM band remains unchanged; and since 20 MHz is a
this frequency synthesizer application. higher speed than we would like to work with, we will look
at another method.
HIGH-SPEED SCALING TECHNIQUES
B. The Prescaler Method
The programmable divider design just described can operate up
to 12 MHz. Fifteen MHz operation can be obtained by adding Construction of a programmable divider that operates at 120
a single flip-flop to this design. This is still a long way from MHz with off-the-shelf integrated circuits does present a prob-
the 118.6 MHz that is required in the FM tuner application. lem. However, construction of a fixed divider at this frequency
There are a number of ways to accomodate this difference. is relatively simple. If a fixed divide-by-10 was placed between
Listed below are three possible solutions to this problem: the VCO and programmable divider as shown in Figure 4b, the
maximum frequency of the signal input to the programmable
A. The Heterodyne Down Converter Method divider would be less than 12 MHz. Twelve MHz is well within
In Figure 4a, the output signal of the VCO is mixed with a sig- the capability of the MSI programmable divider described;
nal from a crystal-controlled oscillator, and the difference fre- however, there is another consideration. If we prescale by 10
we must also divide the comparison frequency by 10. This
can readily be seen from equation (2). This results in an FM
comparison frequency of 20 kHz, which is low in relation to
VCO MIXER the channel spacing and therefore, not optimum.
CONTROL VOLTAGE
OFFSET
CRYSTAL VCi 4FIXEDmetod
Pea
f /lo
OSCI LLATOR
Fig. 4a. The heterodyne down method. Fig. 4b. Prescaler method.
236
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CONTROLLABLE
PRESCALER
FREQUENCY IN PO OR 11
f/10 ENABLE
FREQUENCY OUTPUT
L PE Po PI P2 P3 L f Po Pi P2 P3 L E PI P2 P3
Fig. 4c. Pulse swallowing method - high frequency decade programmable divider.
1/49002 /49002
Fig. 5. Programmable divider for FM frequency synthesizer.
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units counter is considered as a separate counter. The .7 MHz THE DIGITAL FREQUENCY AND PHASE COMPARATOR
part of the 10.7 MHz IF frequency is accounted for only in The frequency and phase comparator generates a pulse dura-
the units counter. The units counter causes 4, 5, 6, 7, or 8 tion modulation signal that is proportional to the phase rela-
pulses to be swallowed depending upon the position of the tionship between the signal from the programmable divider and
least significant switch. the signal from the reference divider.
Two NAND gates are required to add the necessary frequency
MODIFICATION FOR AM OPERATION comparison capability to the digital phase comparator. These
For the AM application the most significant switch must have two gates are used to force the outputs of the reference divider
12 positions; 05 - 16. This includes the positions 08, 09, and and programmable divider to occur alternately. This is accom-
10 that are used in the FM mode. The modulo of the most sig- plished by halting the operation of a divider if it has reached
nificant counter must be increased by the addition of the dis- its terminal state, and the latch has not been set or reset by the
crete flip-flop, since, in the AM mode, this counter must have opposite divider. Figures 7a-7f show the output waveforms of
at least 21 states. In the AM mode the units counter is not the comparator for different frequency relationships between
used, since all AM station frequencies end in zero. In this the reference divider output and the programmable divider
synthesizer design, the least significant digit selects between output.
AM and FM operation. AM is selected when the least signifi- 7a) In this waveform, fp-d is too low. Consequently, the
cant switch is positioned at zero. The selection of the AM reference divider is held up until the output of the
mode causes three changes in the operation of the frequency programmable divider has a change to reset the latch.
synthesizer: Then the reference divider is released, resulting in an
1. The clock input to the counters are switched from the almost immediate setting of the latch.
divide-by-5 or 6 output to the AM VCO's output, 7b, 7c) Wave forms b and c show the result of an increase in
2. The FM terminal count decode (which occurs prior to fp-d-
the AM terminal count) is disabled, and 7d) In waveform d, fp-d and fr-d are equal, but 180° out
3. The divide ratio of the reference divider is changed to of phase.
produce a 10 kHz comparison frequency. 7e, 7f) Waveforms e and f are identical. fp-d is higher for
The complete logic diagram for the AM/FM frequency synthe- these two waveforms than in waveforms a, b, c, and d.
sizer is shown in Figure 6. Also shown in this diagram is the
reference frequency divider and the digital, frequency and a
phase comparator.
THE REFERENCE FREQUENCY DIVIDER b L )
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PHASE ERROR TO VOLTAGE CONVERTER CIRCUIT OPERATION
The phase-to-voltage converter converts the phase comparator's When the leading edge derivative of the input pulse is applied
pulse duration modulation (PDM) output signal into d-c vol- to the base of Q2, C1 is momentarily shorted to ground, and
tage. This voltage is fed back to change the frequency of the the ramp goes to zero volts at the beginning of the cylce. As
VCO in the direction required to provide phase lock. As the long as the input remains high, (+5 volts), switch Q3 is closed,
duty cycle of the phase comparator varies from 0 per cent to and the current source Ql charges C1 in a positive direction.
100 per cent, the output of the control voltage generator The control voltage generator periodically updates the control
varies from around +2 volts to +8V for AM and +2V to +18V voltage at the comparator sampling rate. To optimize the
for FM. range of the control voltage generator, pot P1 is adjusted in
the factory so that the ramp rate and the sample rate are equal.
CIRCUIT DESCRIPTION
TABLE I
The phase-to-voltage converter (Figure 8a) is a ramp generator
and a sample-and-hold circuit. Current source Q1 charges C1 APPROACHES TO ACHIEVING TRACKING
to generate the ramp. Switch Q2 sets the initial voltage on
capacitor Cl to zero. Switch Q3 turns the current source on TUNING
VARACTOR (S) VOLTAGE(S) COIL FOR
when the input goes high and off when the input goes low. Q4 FOR RF AND FOR RF AND RF AND
is connected as an emitter-follower and is used to minimize APPROACH OSCILLATOR TUNING OSCILLATOR OSCI LLATOR
the loading of Cl while charging the filter R7C4. The wave-
forms of the circuit are shown in Figure 8b. 1
2
Same
Same
Different
Different
Same
Different
3 Different Same Same
4 Same Same Different
+30 V *5V
.01 470 02
ION greater than 1 volt peak-to-peak from 100 ohms. The autodyne
oscillator's signal output is only 60 mV; therefore, to provide
adequate drive to the logic, an additional two-stage amplifier
is required between the autodyne oscillator and the logic. This
two-stage amplifier would not be required if a separate device
Fig. 8b. Phase-to-voltage converter. were used as the oscillator. Another way would be to use an
239
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integrated circuit comparator such as thegA71oC to amplify The VCO output signal (-- 3V p-p) to the mixer is taken from
the autodyne oscillator signal, providing a logic drive signal. a tap on the tuning inductor. The VCO output signal to the
logic (1V p-p) is developed across a 100-ohm resistor in the
Figure 10 illustrates AM VCO frequency vs. control voltage. collector circuit. By obtaining one signal from the collector
and another from the emitter, good isolation results and "cross
talk" between the logic and the mixer is greatly reduced.
"Back-to-back" varactors are used in the oscillator's tank cir-
VOLTS MHz 1kHz/VOLTS cuit to reduce large signal distortion and to improve tracking.
10 2.070 _
9 2,060 _
The voltage vs frequency characteristics of the FM VCO are
8 2.020 40
illustrated in Figure 11. Note that the MHz/volt scale factor
7 1.953 67
is not constant across the band. It ranges from 3.3 MHz/volt
at the low frequency end of the band to .9 MHz/volt at the
6 1.870 83
5 1.750 120
high end of the band. The effects of these nonlinear character-
4 1.452 298
istics of the VCO are discussed in the section on phase locked
3 1.115 337
loop characteristics.
2 .970 145
PHASE LOCKED LOOP (PLL) CHARACTERISTICS
Figure 12 illustrates a block diagram for the digital frequency
synthesizer. The blocks are labeled indicating whether or not
the blocks' transfer function is linear. Loop stability is not a
problem until you look at the number of nonlinear transfer
functions in the loop.
(1) The VCOs are nonlinear; this is shown in Figure 10
and 11.
(2) The program divider changes the gain of the loop in
its linear mode, but becomes nonlinear under slip
conditions.
(3) The phase comparator can be considered linear for
small errors and nonlinear for large errors.
Fig. 10. AM VCO control voltage vs. frequency. (4) The phase-to-voltage converter can be considered
linear for small errors and nonlinear for large errors.
(5) The filter is composed of an R-C section and super-
FM VOLTAGE CONTROLLED OSCILLATOR (VCO) position holds; therefore, it is linear.
A high FT PNP transistor that has good performance character-
(6) The reference divider is nonlinear under slip conditions.
istics at 10 mA collector current is used as the FM VCO. The Note that under large signal conditions, such as adjusting to a
PNP Hartley oscillator's varactor tuning diodes are referenced new frequency, the loop contains many nonlinear elements
to the plus supply, which is also the reference for the RF am- which make a formal analysis of the loop characteristics con-
plifier's tuning varactors. siderably beyond the scope of this paper
,,108 - - - -
The practical method of determining the gain margin and
phase margin of the PLL is to measure them. A wide-band
_ operational amplifier can be inserted between the loop filter
102 - - - - - - - and the VCO. The amplifier's gain is increased until the loop
100 - - - - - l- 1 oscillates. The amount of gain required to induce oscillation
98 -
2
-
4
-
6
-
8
-
10 12
- -
14
-
16
-
18
-
is the gain margin. Phase margin can be determined by insert-
CONTROL VOLTAGE ing an additional lag filter section between the loop filter and
the VCO. Again the procedure is to increase the lag until the
Fig. 11. FM VCO control voltage vs. frequency. loop oscillates.
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A small gain margin is probably adequate in the synthesizer, TABLE II
since much of the loop gain is obtained from digital circuits PERFORMANCE OF THE FM RADIO
which should provide stable gain.
Varactor-Tuned FM Front-End Specifications
It should be noted that there are two modes of operation for
phase locked loops: the capture mode, followed by a lock Tuning Range: 88.0MHz + 108.0MHz
mode. The optimal characteristics for each of the two modes Tuning Voltage: 14.0 + 1.0 volts
are different and contradictory. An optimal loop response does Tracking Error: 4dB
Voltage Gain: 23.5dB
not exist, but a trade does exist between the speed of capture Power Gain: 1 1dB (50Q2 input to 1k2 output)
and the "smoothness" of the VCO control voltage. 'I.H.F. Sensitivity: 92MHz 2.OpV
98MHz 2.2,V
Again the actual circuit problems are not too serious, since in 106MHz 1.5pV
*Distortion: 0.7% @ 75kHz 400Hz deviation
home receivers speed of lock is not a critical parameter. Choose *Hum and Noise: -55dB
the amount of filtering desired and accept the lock time you *Selectivity: 1400kHz off channel) 42dB
get. The loop described in this paper will lock in less than one *Image Rejection: 65dB
second.
FM RF AMPLIFIER AND MIXER WWith H. H. Scott IF strip, 342C
Dual gate FETs are used as the RF amplifier and mixer in the
FM front end - Figure 13. They are biased at about 8 mA The performance of the FM front end is listed in Table I I.
with a 120-ohm source resistor, with Gl connected to the
source with a 100k resistor. G2 is biased at approximately 4
volts. The G2 voltage is reduced on the RF amplifier to pro- AM RECEIVER
vide gain reduction. Stability of tuned RF amplifiers is dis- The AM receiver is of conventional- design with three-point
cussed in references 1, 2, and 3. tracking. Figure 14 illustrates the AM receiver, and its per-
formance is listed in Table III.
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+12
AUDIO
OUTPUT
OSCILLATOR AMPLIFIER
FM i HAE0739
AMP~~~~~A M
VARACTORFAVARACT R A0A 71 STERC
SIGNA AUI PRAM
FILTER CONVERTER ~ ~ ~ ~ OWE
< *- a AM OR FMAMAUI
SWTCE
< I~ ~ ~ ~ ~ ~ ~ ~ ~ ~ M
AM SELECT
Fig. 15. System block diagram of AM-FM radio with digital tuning.
242
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TABLE IlIl ACKIElOWLEIlaEMENT
SPECI FICATIONS: VARACTOR-TUNED AM TUNER Paul MacdonMld and John Gregory did the testing and bread-
boarding of-the AI -PM radio. Their efforts were a significant
Sensitivity: 200,AV/meter for 10dB S/N ratio @ 30% modulation contribution to the-project.
ACG Figure of Merit: 60dB
Overload Capability: >1.0 volt/meter REFERENCES
Audio Output: 2.0 volts p-p @ 400Hz 60% mod. @ 10 mV/meter input
6dB Bandwidth: -
8.0kHz
Tuning Range: .550kHz + 1620kHz 1) Transistors and Active Circuits - J.G. Linvill and J.F. Gib-
Harmonic Distortion:
Noise Level:
3% @ 400Hz 60% mod.
-45dB @ 100 mV/meter from 400Hz 30% mod.
bons,%4cGraw-Hill Co. Inc., New York 1961.
Tuning Voltage: 2 to 8 volts 2) StabIlity and Power Gain of Tuned Transistor Amplifiers -
Arthur P. Stern, Proc. I RE, March 1957.
SSYSTEM BLOCK DIAGRAM 3) An FM Front End with a High Gain Un-neutralized JFET -
T. Hanna and P. Froess, Fairchild Semiconductor, 1968.
Figure -15, the system block diagram, illustrates the intercon-
nections between the AM, FM, frequency synthesizer logic and 4) Phase Locked Techniques - F.M. Gardner, Ph.D., John
audio. Wiley,& Sons, New York 1967.
The switching is controlled by the least significant position in 5) Matrix Analysis of Oscillators and Transistors Appications
the selector switch. Since all FM channel frequencies end with A.J. Cote, Jr., I RE Trans Cir Theory, September 1958.
an odd integer (1, 3, 5, 7, 9), and all AM stations end in zero,
6) An Avionics Digital Frequency-Synthesizer J.Nichols and
we can use decks on this switch to perform all the switching
J. Stinehelfer, Application Note 176, Fachild Semicon-
required. ductor, 1969.
CONCLUSION
The design of a digital frequency synthesizer suitable for a
high quality AM FM receiver has been described. The fre- -
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BIOGRAPHY
Jake Stinehelfer earned the AB degree from Colo-
rado State College and the AM degree from Stanford
University. From 1963 to 1968 he was a senior en-
gineer at Kaiser Aerospace and Electronics. Since 1968
he has been at Fairchild Semiconductor as a senior
engineer in communications systems and applications.
Mr. Stinehelfer has published three technical papers
and is the co-holder of two pending U. S. patents.
BIOGRAPHY
John L. Nichols graduated in 1960 from California
State Polytechnic'College at San Luis Obispo with a
degree in mathematics. The next five years were spent
with Philco Western Department Labs in Palo Alto,
California, where he participated in both the design of
special computer input and output equipment and the
computer programming for real time control of satel-
lite ground station operation.
In 1965 Mr. Nichols joined the Systems Engineer-
ing Section of Fairchild Semiconductor where he has
been working on the application of digital integrated
circuits to present and future system applications.
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