e
pp
ti
s
pr
ep
ar
ed
by
D
r.
Sre
ed
ev
iV
.T
Inverters
,V
IT
U
ni
ve
rsi
ty
,C
he
nn
ai
ai
Introduction
nn
he
,C
ty
si
• A static power converter that converts dc input
r
ve
ni
U
power into ac output power at any specified voltage
IT
,V
and frequency is called an inverter.
.T
iV
• Important applications
ev
ed
• Adjustable speed ac drives re
S
r.
D
nn
he
,C
ty
si
• Based on the number of output phases
r
ve
ni
U
• Single phase
IT
,V
.T
• Three phase
iV
ev
•
ed
Based on the nature of dc sources feeding the
inverter re
S
r.
D
by
nn
he
,C
ty
• A voltage fed inverter is the one fed by a stiff voltage
si
r
ve
source, whose voltage is constant and independent of the
ni
U
load.
IT
,V
• In this type, the load voltage is determined by the inverter
.T
iV
• But the load current waveform is dependent on the load
ev
ed
• In contrast, a current fed inverter is supplied by a stiff
re
current source that is constant and independent of the
r.
S
load.
D
by
ni
ve
rsi
ty
,C
he
nn
ai
Single phase bridge voltage source
ai
nn
he
inverter
,C
ty
si
• Bridge inverters can produce single phase or three
r
ve
ni
phase outputs.
U
IT
• The input to a voltage source inverter is a stiff dc
,V
.T
voltage supply , which may be a battery or the output
iV
ev
of a phase controlled rectifier.
ed
re
• Both single phase and three phase voltage source
S
r.
D
switching devices
pr
s
ti
configuration
Th
Schematic of single phase voltage
ai
nn
he
source half bridge inverter
,C
ty
si
r
ve
ni
U
IT
,V
.T
iV
ev
ed
re
S
r.
D
by
ed
ar
ep
pr
s
ti
pp
e
Th
single phase voltage source half bridge
ai
nn
inverter
he
,C
ty
si
• The dc input to the half bridge is from a split dc
r
ve
ni
power supply
U
IT
,V
• That is besides positive and negative outer
.T
iV
terminals, a mid-point terminals is also available
ev
ed
making it a three-wire dc supply.
re
S
• Switches S1 and S2 are ON/OFF solid state switches.
r.
D
by
diodes.
ep
pr
and S2
e
Th
Th
e
pp
ti
s
pr
ep
ar
ed
by
D
r.
Sre
ed
ev
iV
.T
,V
IT
U
ni
ve
rsi
ty
Mathematical Analysis
,C
he
nn
ai
Th
e
pp
ti
s
pr
ep
ar
ed
by
D
r.
Sre
ed
ev
iV
.T
,V
IT
U
ni
ve
rsi
ty
,C
Mathematical Analysis
he
nn
ai
Th
e
pp
ti
s
pr
ep
ar
ed
by
D
r.
Sre
ed
ev
iV
.T
,V
IT
U
ni
ve
rsi
ty
,C
Mathematical Analysis
he
nn
ai
Th
e
pp
ti
s
pr
ep
ar
ed
by
D
r.
Sre
ed
ev
iV
.T
,V
IT
U
ni
ve
rsi
ty
Mathematical Analysis
,C
he
nn
ai
Th
e
pp
ti
s
pr
ep
ar
ed
by
D
r.
Sre
ed
ev
iV
.T
,V
IT
U
ni
ve
rsi
ty
,C
Mathematical Analysis
he
nn
ai
ai
Single phase full bridge inverter
nn
he
,C
ty
si
• The main drawback of half bridge inverter is that it
r
ve
ni
U
requires a three-wire dc supply.
IT
,V
• This difficulty can overcome by the use of a full
.T
iV
ev
bridge inverter.
ed
re
• The amplitude of output voltage is also doubled in
S
r.
D
bridge inverter.
ar
ep
pr
s
ti
pp
e
Th
Th
e
pp
ti
s
pr
ep
ar
ed
by
D
r.
Sre
ed
ev
iV
.T
,V
IT
U
ni
ve
rsi
ty
,C
he
nn
ai
Single phase full bridge inverter
ai
Operation
nn
he
,C
ty
• For the full bridge inverter, load voltage is V when S1
si
r
ve
and S2 are ON and when S3 and S4 conduct, load
ni
U
voltage is –V as shown in fig.
IT
,V
• The sequence of gating signals and output voltage are
.T
iV
shown in fig.
ev
• Frequency of output voltage can be controlled by
ed
re
varying time period T r.
S
• For resistive loads, SCRs are sufficient making the
D
by
nn
he
,C
ty
si
• It should be ensured that two switches in the same
r
ve
ni
U
branch, such as S1 and S2 do not conduct
IT
,V
simultaneously as this would lead to a direct short
.T
iV
circuit of the source.
ev
ed
re
• For RL, RLC loads current Io will not be in phase
r.
S
D
he
nn
ai
Th
e
pp
ti
s
pr
ep
ar
ed
by
D
r.
Sre
ed
ev
iV
.T
,V
IT
U
ni
ve
rsi
ty
,C
he
nn
ai
Th
e
pp
ti
s
pr
ep
ar
ed
by
D
r.
Sre
ed
ev
iV
.T
,V
IT
U
ni
ve
r
PWM Techniques
si
ty
,C
he
nn
ai
Voltage control in single phase
ai
nn
he
inverters
,C
ty
• This section examines various methods of output
si
r
ve
voltage control by means of inverter gain control.
ni
U
IT
• The inverter gain is defined as the ratio of the output ac
,V
voltage to input dc voltage.
.T
iV
• Such gain control is useful in many applications where
ev
ed
the variations of ac output voltage cannot be tolerated
re
S
due to variations in dc input voltage.
r.
D
by
magnetic circuit.
e
Th
Voltage control in single phase inverters
ai
nn
he
• Various techniques are available for varying the inverter
,C
ty
gain.
si
r
ve
• The most efficient method of controlling the gain and
ni
U
therefore the output voltage is to incorporate PWM
IT
,V
control within the inverters.
.T
iV
• PWM-Pulse width Modulation Control
ev
ed
• In addition to PWM method, there are methods
re
S
involving external control of ac output voltage and dc
r.
D
input voltage
by
ed
nn
he
,C
ty
• A fixed dc input voltage is given to the inverter and a
si
r
ve
controlled ac output voltage is obtained by adjusting
ni
U
the on and off period periods of the inverter
IT
,V
components.
.T
iV
• This is the most popular method.
ev
ed
• The advantages of PWM control technique are
re
S
The output voltage control with this method is
r.
D
by
nn
he
,C
ty
si
• PWM pulses are characterized by constant
r
ve
ni
U
amplitude pulses.
IT
,V
• The width of these pulses is, however modulated to
.T
iV
ev
obtain inverter output voltage control and to
ed
re
reduce simultaneously its harmonic content.
r.
S
D
ai
nn
he
,C
ty
si
• In single–pulse width modulation control,
r
ve
ni
U
there is only one pulse per half cycle and the
IT
,V
width of the pulse is varied to control the
.T
iV
inverter output voltage.
ev
ed
re
S
r.
D
by
ed
ar
ep
pr
s
ti
pp
e
Th
Th
e
pp
ti
s
pr
ep
ar
ed
by
D
r.
Sre
ed
ev
iV
.T
,V
IT
U
ni
ve
rsi
ty
,C
he
nn
ai
Th
e
pp
ti
s
pr
ep
ar
ed
by
D
r.
Sre
ed
ev
iV
.T
,V
IT
U
ni
ve
rsi
ty
,C
he
nn
ai
Single Pulse Width Modulation
Single Pulse Width Modulation
ai
nn
he
control
,C
ty
• The output voltage from a single phase full bridge inverter is
si
r
shown in fig (a)
ve
ni
• When this waveform is modulated the output voltage obtained is
U
IT
of the form shown in fig (a).
,V
• It consists of a pulse of width 2d located symmetrically about pi/2
.T
iV
and another pulse of same width 2d located symmetrically about
ev
3pi/2.
ed
re
• The pulse width is varied from 0 to pi.
r.
S
• The output voltage is controlled by varying the pulse width 2d.
D
by
• Positive and negative half cycles are symmetrical about pi/2 and
ep
3pi/2
pr
s
ai
nn
he
control
,C
ty
• The rms value of output voltage,
si
r
ve
• Vor=V√2d/pi
ni
U
IT
• The gating pulses can be generated to achieve this kind of
,V
modulation as depicted in fig.
.T
iV
• The gating signals are generated by comparing a rectangular
ev
ed
reference signal of amplitude Ar with triangular carrier wave
re
of amplitude Ac. r.
S
D
Ar/Ac.
e
Th
ai
Disadvantages
nn
he
,C
ty
si
• In this method of voltage control, a great deal
r
ve
ni
U
of harmonic content is introduced in the
IT
,V
output voltage.
.T
iV
ev
ed
re
S
r.
D
by
ed
ar
ep
pr
s
ti
pp
e
Th
Multiple pulse width modulation
ai
nn
he
,C
ty
si
• The harmonic content can be reduced by using
r
ve
ni
U
several pulses in each half cycle of the output
IT
,V
voltage instead of a single pulse as in single pulse
.T
iV
width modulated converters.
ev
ed
re
• The turning on and off of transistors or any other
r.
S
D
carrier wave.
pp
e
Th
Multiple pulse width modulation
ai
nn
he
• The harmonic content can be reduced by using several
,C
ty
si
pulses in each half cycle of output voltage.
r
ve
ni
• The carrier frequency determines the number of pulses
U
IT
per half cycle, p.
,V
.T
• The modulation index controls the output voltage.
iV
ev
ed
• This type of modulation is also referred as uniform
pulse width modulation (UPWM) re
S
r.
D
from
ar
ep
• P= fc/2fo=mf/2
pr
s
ti
nn
he
,C
ty
si
• Since this type of modulation employs large number of
r
ve
ni
pulses, p, involving larger number of switch ONs and
U
IT
switch OFFs, switching losses are more.
,V
.T
• Larger P reduces the amplitudes of lower order
iV
ev
harmonics but increases the amplitudes of some higher
ed
re
order harmonics at the same time.
r.
S
D
nn
he
,C
ty
si
• In this method of modulation also, several
r
ve
ni
U
pulses per half cycle are used as in the case of
IT
,V
UPWM.
.T
iV
• The pulses are of equal width in UPWM
ev
ed
re
• But in SPWM the pulse width varies as a
S
r.
D