IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, VOL. 36, NO.

8, AUGUST 1989 1113

200kR 2200pF (91 G. M. Wierzba, “Op-amp relocation: A topological active network

synthesis,” IEEE Trans. Circuits Svst., vol. CAS-33, pp. 469-475, May
1986.
[lo] R. Palomera-Garcia and H. Hidalgo, “Algunos circuitos oscilladores,”
Proc. IEEE Maxicon, pp. 139-142, 1981.
I A
[ l l ] V. Singh. “A new active-RC realization of floating inductance,” Proc.
Fig. 15. Passive prototype example IEEE, vol. 67, pp. 1659-1660. Dec. 1979.
[12] _ , “Novel active RC realizations of tunable floating inductors,”
Electron. Len., vol. 16, p. 758. 1980.
[13] V. Nagarajan and S. C. Dutta Roy, “Active RC synthesis of a floating
immittance using operational amplifiers,” Proc. I € € € Int. Symp. on
Circuit Theory, pp. 304-307. Apr. 1973.
[14] V. Singh, “On floating impedance simulation,” IEEE Trans. Circuits
- themetical Svst., vol. 36, pp. 161-162, Jan. 1989.

”O
0.81
I
t fl X \
Detecting and Locating Electrical Shorts Using
Group Testing
C, C. CHEN A N D F. K. HWANG

Abstract-In this paper, we consider the problem of detecting and

0.2t
0.0‘
0.1 0.2 0.5 1 2 5 10 20
frequency,k Hz
Fig. 16. Frequency response of the network shown in Fig. 15. (Resistors of
5-percent tolerance and capacitors of 10-percent tolerance were used in the
experimental setup.)
Note that if one employs back-to-back approach [l], [13] or the
approach of [3] for FI realization in this case, that would mean
losing the above-mentioned non-interacting potentiometric con-
trol (and, of course, requiring an extra capacitor).
With a view to check the practical working of the floating
series R L circuit presented in Fig. 14, the network shown in Fig.
15 was set up in the laboratory. The circuit of Fig. 14 (using pA
741 op amps with 12-V dc supply; R, = R , = 100 kSt, C = 2200
pF) has been used for the floating series RL impedance in Fig.
15. For the element values shown in Fig. 15, the theoretical
frequency response is plotted in Fig. 16. Measured points corre-
sponding to two design sets are added, confirming the applicabil-
ity of the present FI circuit.
REFERENCES
Le qui The and T. Yanagisawa, “A synthesis of floating impedance,” (in
Japanese), IECE Japan. monograph CST 76-47, 1976.
Le qui The and T. Yanagisawa, “Some new lossless floating inductance
circuits,” Proc. IEEE, vol. 65, pp. 1071-1072, July 1977.
P. R. Bryson and G. M. Wierzba, “Theory and application of semiindef-
inite networks,” Proc. Inst. Elect. Eng., part G , Electronic Circuits and
Systems, vol. 129, no. 6, pp. 285-290, Dec. 1982.
V. Singh, “On Hilberman’s theorem and the characterization of ideal
op-amp semi-indefinite network,” IEEE Trans. Circuits Svst.. vol. 35. p.
251, Feb. 1988.
J. L. Huertas, “Circuit implementation of current conveyor,” Electron.
Lett., vol. 16, pp. 225-226, 1980.
H. J. Orchard and A. N. Willson, “New active-gyrator circuit”, Elec-
tron. Lett., vol. 10, pp. 261-262. 1974.
P. Horn and G. S . Moschytz, “Active RC single op-amp design of
driving point impedances,” IEEE Trans. Circuits S-vst., vol. CAS-26, pp.
22-29, Jan. 1979.
D. Hilberman, “Input and ground as complements in active filters.”
IEEE Trans. Circuit Theory, vol. CT-20, pp. 540-547, Sept. 1973.
locating electrical shorts among a set of nets using an apparatus which,
when connected to two groups of nets, can detect, but not locate, the
presence of a short between the two groups of nets. This problem was
previously considered by Skilling and a clever method was patented by
him. We relate this short locating problem to the well-studied group testing
problem and borrow some results from there to devise a procedure for the
former problem. We show that the proposed procedure compares favorably
with Skilling’s method and also consider the case in which one of the two
50
groups of nets being tested is restricted in sue, as is true in many practical
applications.
I. INTRODUCTION
A prevalent type of fault in the manufacture of electrical
circuits is the presence of a short circuit (“short”) between two
nets of a circuit. Short testing constitutes a significant part of the
manufacturing process. Several fault patterns can be described as
the variation or combination of these types of faults. Application
of short testing ranges from printed circuit board testing and
circuit testing (such as solder bridge, capacitor, resistor or diode)
to functional testing (e.g., in AT&T 5ESSTM,verifying the in-
tegrity of gate diode cross points).
A short testing procedure can have two different objectives; a
detecting procedure aims simply to detect the presence of a short,
while a locating procedure identifies the shorted pairs of nets. A
short detector in common use is an apparatus involving two
connecting leads which, when connected respectively to two nets
or groups of nets, can detect, but not locate, the presence of a
short between these nets or groups of nets. An obvious way to
use this device for short location is the so called n-square testing,
which checks each pair of nets separately. If the circuit has n nets
to start with, then this location procedure requires (;)
tests.
Garey, Johnson, and So [2] proposed a procedure for detecting
shorts between nets in printed circuit boards. They showed that
no more than 5, 8, or 12 tests (depending on the particular
assumptions) will ever be required, independent of the number of
nets. However, it is not a locating procedure, and their assump-
Manuscript received May 2, 1988; revised December 23, 1988. This paper
was recommended by Associate Editor M. Ilic.
C. C. Chen is with AT&T Bell Laboratories, Piscataway, NJ 08540.
F. K. Hwang is with AT&T Bell Laboratories, Murray Hill, NJ 07974.
IEEE Log Number 8928274.
TM
Registered trademark of AT&T Bell Laboratories.

0098-4094/89/0800-1113$01.00 01989 IEEE

~~ ~~ - --

Authorized licensed use limited to: M S RAMAIAH INSTITUTE OF TECHNOLOGY. Downloaded on April 24,2010 at 07:23:32 UTC from IEEE Xplore. Restrictions apply.
 1114 IEEE TRANSACTIONS ON CIRCUITSAND SYSTEMS, VOL.
36, NO. 8, AUGUST 1989

short pair between the nets in a , and the nets in h, for at least
one i. Let [Cfi=la,]denote the configuration where there exist k
disjoint sets with U,; . ., ak nets such that no short pair exists
between the U , nets and the a, nets for any i and j . Let 1x1(1x1)
denote the greatest (smallest) integer not greater (smaller) than x.
Theorem I: A short pair can be located in the configuration
[ a x h ] in [log, ab] tests.
Proof: We show that the problem of locating one short pair
in the configuration [ a x h ] is mathematically equivalent to the
Fig. 1. A diagonal short between two nets. problem of using group testing to locate the two defectives in two
disjoint sets of a and b items, respectively, where each set
contains exactly one defective [l]. A group test is a simultaneous
tions allow only shorts occurring vertically or horizontally, not
test on a subset of items with two possible outcomes: the subset
diagonally, as shown in Fig. 1.
contains no defectives (negative outcome) or it contains at least
Skilling [3] proposed a clever locating procedure much more
one defective (positive outcome). We can associate with the group
efficient than the n-square testing. In his method each net is
testing problem an a x h complete bipartite graph where each
tested individually against all other nets, collectively. Thus after n
edge represents a possible solution to the problem-a pair of
tests we obtain all the shorted nets, though we do not know to
defectives. Suppose we test a subset consisting of c of the a items
which other nets they are shorted. If there are d shorted nets,
and d of the h items. Then the two outcomes partition the
then (;) more tests are required to determine which of these are bipartite graph into two disjoint subgraphs where one of them is
shorted to which others. Thus the total number of tests is the subgraph induced by the a - c and 6 - d untested items
n+ ( ;), which can be significantly less than
(1) for n much (corresponding to the negative outcome). For the [ a X h ] short
testing problem again we can associate an a x b complete bipar-
larger than d .
tite graph where each edge represents the short pair to be located
In this paper we propose a locating procedure which requires
approximately 2(d + l)log, n tests. For values of n and d for next (there may exist more than one short pair but only one is
located at a time). When we connect a - c of the a nets to one
which Skilling compared his method with the n-squared testing,
our method compares very favorably with Skilling’s method, lead and b - d of the b nets to the other lead, then the same
especially for larger values of n. We also consider a practical partition as before is obtained. Namely, when the short-detector
constraint that one of the two groups being tested can include at shows a presence of short, then the subgraph consistent with this
most I nets. outcome is induced by the a - c and the b-d nets. It is easily
seen that the correspondence between the negative outcome in a
group test and the presence of short in a short test holds not just
11. THEPROPOSED PROCEDURE for the first test but for all tests. Therefore the two problems are
The unique characteristic of the proposed algorithm is that the mathematically equivalent. By a result in [ l ]the group testing
fault detection and fault location are considered simultaneously. problem can be done in [log, ah] tests. This verifies Theorem 1.
Consider a circuit board with n networks. Without loss of We now define the halving procedure H for the short testing
generality we assume n = 2“. This algorithm can be described as problem. For the configuration [Xfi=lo,] we split each set of a,
a process of sequentially partitioning the n networks into 2‘ nets half and half (as closely as possible); connect one half to one
disjoint subsets at the ith stage; half of these 2’ subsets are lead and the other half to the other lead. When no short is
connected to the “FROM” side and the other half to the “TO” side present, we move into the configuration [C;b,a,!] each a, splits
such that within the “FROM” side and “TO” side all subsets are into a,‘ and a,’+A. When a short is present, we move into the
free from short with each other. A testing signal is then applied configuration [ X f = , [ a , / 2 J X [ a , / 2 ] ]We
. then use binary splitting
to the networks on the “FROM” side and are monitored at the on the k pairs, to identify one pair [a,/2jX[af/2] that contains
“TO” side. Two possible outcomes of the ith stage will lead to the a short, in [log, k ] tests. By Theorem 1 we can then locate a
following subsequent actions: shorted pair from the configuration [la,/ 2 J x [ a ,/21].
Theorem 2: The halving procedure H can locate a shorted pair
If the ith stage passes, we repeat the above procedure for the in n nets in 2[log, nl - 1 tests, or ascertain the nonexistence of a
(i + l ) t h stage. Note that when i = a =log, n, all the 2“ shorted pair in [log, n ] tests.
subsets are singletons. The passing of the a th stage would Proof: Since we start from the configuration [n],it is clear
imply that the networks are free from short defects because that all configurations of the form [C,k=la,]Hencounters has k a
the networks on the same side are also free from the short power of 2 and each U , Q 2a-‘ng2k where a = [log, n ] . Conse-
defect. quently, all the [ I f = , a ,X h,] configurations H encounters also
If the i th stage fails for some stage i, a binary search begins have k a power of 2 and each a,h, < 22(U-’ng2kp1). Suppose that
on each side, and with 210g, i tests, we will obtain one pair the first time we obtain the configuration of the form Cfi=,a, x b,
of subsets (T,, c)-one from each side such that at least one is when k = 2“’. Then m + 1 tests have been used. In another m
network in F; is shorted to one network in 7;. Repeating the tests we obtain a pair a , X h, which contains a short pair. Finally,
binary search again on both E; and T,, we will be able to we locate the short pair in 2[10g, n1-2m - 2 more tests. Adding
identify one pair of networks from F; and 7; which are up the tests we obtain 2[10g, nl- 1. If after [log, nl tests we
shorted together. We then go back to stage 1. obtain the configuration C~OL,a,with each U , ~ 1then , clearly we
know that no short pair exists.
This testing process can be mathematically described as follows: We now consider two modes of operation, R and R , depend-
Let [Cf=,(a , X b,)]denote the configuration where there exist 2 k ing on whether a located short is immediately repaired or not. An
disjoint sets with a,, b,; . ., a k ,b, nets such that there exists a important difference is that when detecting a short we do not

Authorized licensed use limited to: M S RAMAIAH INSTITUTE OF TECHNOLOGY. Downloaded on April 24,2010 at 07:23:32 UTC from IEEE Xplore. Restrictions apply.
 IEEE TRANSACTIONSON CIRCUITS AND SYSTEMS, VOL. 36, NO. 8, AUGUST 1989 1115

TABLE I
OF THREE METHODS
A COMPARISON

n-square Skilling method Procedure H (mode R )

n method d=O d=2 d=4 d=6 d=8 d=O d=2 d=4 d=6 d=8
64 201 6 64 65 70 79 92 6 28 50 72 94
128 8128 128 129 134 143 156 I 33 59 85 111
256 32640 256 257 262 271 284 8 38 68 98 128
512 130816 512 513 518 527 540 9 43 77 111 145
1024 523776 1024 1025 1030 1039 1052 10 48 86 124 162
2048 2096128 2048 2049 2054 2063 2076 11 53 95 137 179

have to worry about the presence of previously located shorts TABLE I1

under mode R . PROCEDURE
H UNDER CONSTRAINT
Theorem 3: If the n nets contain d short pairs, then d + l d/l 1 2 4 8 16 32 64 128 256 512
runs of H will locate all short pairs in at most (2d + l)[log, nl- d
tests under mode R . 0 1024 768 512 320 192 112 64 36 20 11
Remarks: In practice, if we learn that no short pair exists 2 1046 790 534 342 214 134 90 66 54 49
4 1068 812 556 364 236 156 116 96 88 87
between a set of Xf=lal nets and a set of Ef-lbl nets in a run,
6 1090 834 578 386 258 178 142 126 122 125
then we certainly can skip that test in all later runs.
8 1112 856 600 408 280 200 168 156 156 163
Corollary: At most (Ld + l)[log, nl tests are required if mode
R is replaced by mode R.
Proof: After H located a short pair (x, y ) , remove y and exist k between-group short pairs and d - k within-group short
test x against the other n -2 nets. If a short is detected, we can pairs. We first locate the k between-group short pairs by con-
(
locate another short pair in 1+ log, ( n - 2) G 1+ [log, 11 tests ducting [n/ll tests where each test pitches a distinct group
by Theorem 1. If no short is detected, then we know (x, y ) is the against all other groups. By Theorem 1 it takes at most kllog, nl
only short pair involving x. Remove x and apply H to the other tests to locate the k short pairs and at most another k tests (one
n - 1 nets ( y is put back). Thus the detection of each short pair test after each short pair is located) to make sure that there exist
may consume one extra test. rn no other between-group short pairs. rn
Skilling [3] compared the number of tests required by his To locate the within-group short pair we merge any two
method with the n-square method for n = 64,128,. ..,2048 and groups. The purpose of merging is to reduce the number of tests;
d = 0,2; . .,8. We now add the corresponding numbers for H the choice of merging groups is not unique, but all possible
into the comparison. choices have the same testing complexity. We then apply the
Thus we see that procedure H can save significant numbers of procedure H to the combined group with the first test pitting one
tests over Skilling’s method for practical values of n and d. group again the other. Let k , denote the number of short pairs in
the ith combined group, i =1;. .,[n/211. By Theorem 3 we can
111. LOCATING
SHORTS WITH HARDWARE RESTRICTION locate all E!y<2‘lk,= d - k short pairs in
Previous sections assumed no restriction on the number of nets ln/2/1

that can be included in a test. However, in practice, this is

I
c
=1
{(2k, +l)llog* 211 - k, - 1)
sometimes not the case. For example, in the high-voltage break-
down test (a test to detect the current leakage resulting from the = ( 2 d - 2 k + [ n / 2 1 ] ) [ l o g 2 2 1 ] - d + k+[n/211
voltage difference between two networks caused by a sudden tests. Thus the total number of tests is
surge of high voltage) for the printed wiring boards, such as
TN838, TN335 boards in line unit of SESS, the operating voltage [~/ll+llog,nl+k
is approximately 320 V. In order to ensure that the printed wiring + ( 2 d -2k + [ n/2l1)[log2 2Il- d + k - [n/21]
boards are free from high impedance shorts (the current leakage
resulting from the high voltage difference between two networks), = [ ./I1 + k [log, n1+ (2d 2 k + [ n/2Il) [log, I ] + d
-

each board needs to perform a breakdown test with lo00 V.
Connecting too many nets on the “From” lead (the lead where
the testing signal is applied) during the test is hazardous to the
test equipment. The SID Breakdown test set (an in-house con-
structed test set used for testing Reed-relay switches in Oklahoma
City Works) can accommodate up to 32 nets. Therefore, in order
to have practical implementation of the proposed algorithm, we
need to modify the algorithm to accommodate hardware restric-
tions, as stated in the following theorem.
Theorem 4: Suppose that at most I nodes can be included
in one of the two groups. Then there exists a procedure for
mode R which requires at most [ n / l l + [n/2llf1og2 I1 +
d flog, max { n, 1, }1+ d tests.
Proof: Partition the n nets into [ n / l l groups where each
group has 1 nets except possibly one group. Suppose that there
which achieves the maximum
[./I] + ( 2 d + [ n / 2 1 ~ ) [ l o g 2 1 ) +d
at k = 0 for I fi and achieves the maximum
[n/I]+d[log,n]+[n/21][log21]+d
at k = d for I < fi.Theorem 4 follows immediately.
Corollary: At most d more tests are needed if mode R is
replaced by mode R .
Let n =lo24 in the following table for numbers of tests with
various values of d and 1.
We note that procedure H requires a slightly greater number
of tests than Skilling’s method for I = 1. We also note that for d
large the number of tests is not increasing in I for 1 &. This
suggests two things. First, the benefit of having larger 1 is

Authorized licensed use limited to: M S RAMAIAH INSTITUTE OF TECHNOLOGY. Downloaded on April 24,2010 at 07:23:32 UTC from IEEE Xplore. Restrictions apply.
 1116
decreasing for I 6. Second, for I large we may not want to use
the full capacity. It is clear that we never need I > n/2 since we
can always apply the capacity constraint to the smaller group of
nets. Therefore I = 512 corresponds to the case of no capacity
constraint. A discrepancy of one test between I = 512 in Table I1
and n =lo24 for procedure H in Table I is due to a slight
difference in analysis.
IV. CONCLUSION
If the capacity constraint I equals one, then Skilling’s method
is still the best. However, in many practical applications I is
greater than one and can go as high as 32. Then the proposed
procedure H with constraint 1 does save a lot of tests from
Skilling’s method. The procedure H with constraint I also in-
cludes the procedure H with no constraint as a special case by
setting I = [n/2J.
The test patterns for procedure H are more complicated than
those corresponding to the n-square method and Skilling’s
method. However, the time required to set up the patterns is
usually dominated by the time required for a test. For example,
for SID breakdown test set in Oklahoma City Works, it takes
approximately 120 ms to perform a test and the switching speed
to set up the test pattern is in order of microseconds. This
justifies the use of the number of tests as the evaluation criterion.
REFERENCES
[I] G. J. Chang and F. K. Hwang, “A group testing problem on two disjoint
sets,” SIAM J. Alg. Discrefe Meth., vol. 2, pp. 35-38, 1981.
[2] M. R. Garey, D. S . Johnson, and H. C. So, “An application of graph
coloring to printed circuit testing, IEEE Tram. Circuits Sysf.,vol. CAS-23,
pp. 591-599.1916.
[3] J. K. Skilling, “Method of electrical short testing and the like,” U.S.
Patent 4 342 959, Aug. 3, 1982.
A Parallel A/D Converter Array Structure with
Common Reference Processing Unit
KEPING CHEN AND CHRISTER SVENSSON
Abstract -successive approximation A / D converter array, with a paral-
lel architecture, is proposed. The circuit is realized using switched-capaci-
tor (SC) technique. The architecture of the A/D converter array is based
on a common reference processing unit and multi-channel parallel input
signal processing units. Input signal processing units, which are the main
part of the A / D converter array, are insensitive to the capacitor ratio
mismatch and the gain of the amplifiers. The linearity of the A/D
converter array is insensitive to parasitic capacitors and offset of ampli-
fiers. The Conversion time of the A / D converter array is linearly propor-
tional to the number of bits required. Due to the small amount of
components needed and simplicity of the circuit realization, the proposed
A/D solution is suitable for VLSI implementation of an A / D converter
array. A typical application of such a kind of A / D converter array would
be in a smart sensor system, where a sensor array, parallel A/D converters
and parallel digital processors are integrated in a single chip.
Manuscript received May 19, 1988; revised November 11, 1988. This work
was supported by the National Swedish Board for Technical Development.
This paper was recommended by Associate Editor C. A. T. Salama.
The authors are with the LSI Design Center, IFM, Linkoping University,
S582-83 Linkoping, Sweden.
IEEE Log Number 8928275.
~98-4094/89/08OO-1116$01 .OO 01989 IEEE
Authorized licensed use limited to: M S RAMAIAH INSTITUTE OF TECHNOLOGY. Downloaded on April 24,2010 at 07:23:32 UTC from IEEE Xplore. Restrictions apply.
IEEE TRANSACTIONS ON CIRCUITSAND SYSTEMS, VOL.
36, NO. 8, AUGUST 1989
I. INTRODUCTION
Recently, various types of sensors using integrated circuit
technology have been developed. Effective interfaces between a
sensor array and a parallel digital processor array are becoming
of crucial importance, in particular when it is desirable to have a
large sensor array and parallel digital processors on a single chip.
The continuous progress of the VLSI technology has provided
the possibility of integration of such systems. However, the area,
speed and power consumption of the A/D converter array have
become the bottleneck. To alleviate this problem, an architecture
for an efficient A/D converter array is required. For a multi-
channel parallel converter array, we are interested in A/D con-
verter structures which reduce the number of components (capa-
citors and amplifiers) as well as the accuracy requirement of these
components.
In a system where a parallel A/D converter array is used
together with an on-chip sensor array and parallel digital proces-
sors, the requirement on speed of the A/D converter is not
necessarily very high. The reduction of the size and power
consumption for the A/D converter is more important. The high
speed requirement of a video A/D converter is due to the
pixelwise read-out principle of a video system. For an integrated
vision system, suppose that the sensor array has a size of 512 x 512
pixels, with a frame rate of 48 frames per second. When a 512
channel A/D converter array is used, the required conversion
rate of each A/D converter is only 25 kS/s. Suppose that 8 bit
resolution is needed, then the clock frequency will be 200 kHz,
which can be well handled by switched-capacitor (SC) technique.
The possibility of higher clock frequencies will be interesting for
high-frame rate cameras or time-sharing of A/D converters.
Various A/D conversion algorithms operate by modifying the
input signal or the reference signal or both in an A/D converter.
Input signal processing can not be space-shared in a multi-chan-
ne1 parallel system. If reference signal processing can be sepa-
rated from input signal processing, an independent reference
processing unit can be used for all the A/D converter channels.
Integrating type A/D converters are examples of this approach,
where the output of the reference signal processing unit is a ramp
signal. The approach of a common reference processing unit for
an A/D converter array has been used and shown to be space
efficient [l], [2]. Danielsson has proposed an A/D converter
array structure, where a common reference signal is used for all
channels of an A/D converter array [l]. A common reference
source and a common digital counter have also been proposed
for a multi-channel A/D converter array [2]. The drawback of
these two A/D conversion array structures is due to low speed.
For a k-bit conversion, 2k - 1 clock cycles are required. In this
paper, we demonstrate that a common reference processing ap-
proach can be exploited in successive approximation type con-
verters. The extraction of the common reference processing from
the input signal processing not only reduces the total number of
components but also makes input signal processing insensitive to
the component ratio mismatch.
11. ALGORITHM
FOR A BINARY
SEARCH
A/D
CONVERTER ARRAY
There exist two types of binary search A/D conversion meth-
ods. One type of converter is commonly referred to as a succes-
sive approximation A/D converter. Another type of converter is
called an algorithmic A/D converter, which can be implemented