EE 361

16-Bit Single-Cycle LEGLite Project

Summary: You will implement, in SystemVerilog, a simpified version of the single-cycle LEGv8, which we will
refer to as LEGLite.

LEGLite Description:

• Its data and address buses are 16-bits wide.

• All instructions and operands are 16-bits, i.e., “halfwords”.
• Memory is byte addressable and is organized as Little Endian. Note that memory addresses of
halfwords are divisible by two. In other words, the address of the first halfword is 0, the second is 1,
and so on. The first halfword has bytes 0 and 1, the second halfword has bytes 2 and 3, and so on.

General Purpose Registers: X0, X1, ..., X7

Name Reg # Usage

X0-X6 0-6 General purpose registers

(X6 is the link register LR)
XZR 7 Zero register (always zero valued)

Instruction Formats

Format Fields Examples

4 bits 3 bits 3 bits 3 bits 3 bits
[15:12] [11:9] [8:6] [5:3] [2:0]
R opcode NA Xd Xm Xn ADD Xd,Xn,Xm
(register)
I opcode constant Xm Xn ST Xm,[Xn,#const]
(immediate) LD Xm,[Xn,#const]
ADDI Xm,Xn,#const
CB opcode offset constant Xn CBZ Xn,Label
(conditional (PC-Relative offset)
branch)
B opcode offset constant B Label (unconditional branch)
(unconditional (PC-Relative offset) BL (branch-and-link)
branch)
NP opcode NA NOP
(instructions RET
with no
parameters)

1
Instructions

Name Mnemonic Format Opcode Operation Example

Add ADD R 0 Xd = Xn + Xm ADD Xd,Xn,Xm
Subtract SUB R 1 Xd = Xn - Xm SUB Xd,Xn,Xm
And AND R 2 Xd = Xn & Xm AND Xd,Xn,Xm
Or OR R 3 Xd = Xn | Xm OR Xd,Xn,Xm
Add immediate ADDI I 4 Xm = Xn + const ADDI Xm,Xn,#const
Subtract SUBI I 5 Xm = Xn - const SUBI Xm,Xn,#const
immediate
And immediate ANDI I 6 Xm = Xn & const ANDI Xm,Xn,#const
Or immediate ORI I 7 Xm = Xn | const ORI Xm,Xn,#const
Store in memory ST I 8 Memory[Xn+const] = Xm ST Xm,[Xn,#const]
Load from LD I 9 Xm = Memory[Xn+const] LD Xm,[Xn,#const]
memory
Conditional CBZ CB 10 if Xn = 0 then CBZ Xn,Label
branch if Zero PC = PC + (offset<<1)
else
PC = PC + 2
Conditional CBNZ CB 11 if Xn = 0 then CBNZ Xn,Label
branch if not PC = PC + 2
zero else
PC = PC + (offset<<1)
Unconditional B B 12 PC = PC + (offset << 1) B Label
branch
Branch-and-link BL B 13 X6 = PC+2 BL Label
(subroutine call) PC = PC + (offset << 1)
No operation NOP R 14 No operation NOP
(delay)
Return from BR R 15 PC = Xn BR Xn
subroutine

2
Below is a circuit diagram for the single cycle LEGLite.

• reset: Resets the PC to 0

• Not shown are clock signal and connections from Controller to the datapath
• PC-offsets are in instr[11:0] including the PC offsets for the B and CB instructions. The PC Update Logic uses this
along with sign extensions and shifting to compute 16-bit PC-offsets for the B and CB instructions.
• This doesn’t implement all instructions. For example, BL (branch-and-link) can’t be implemented. You can
include this instruction by modifying the controller and datapath.

branchUncond
branchCond
aluSrcSel
Controller aluSel[2:0]
memRead
Instr[15:12]
memWrite
writeRegDataSel
writeRegIndexSel
regWrite
branchUncond
PC Update branchCond
Logic
Reset memRead memWrite
regWrite
regReadIndex1 aluSel[2:0]
Instr[2:0] Read regReadData1 ALUZero 128 memory
Read Read cells, 16-bits
PC Instr Reg1 Data1
Address regReadIndex2 aluResult per cell
Instr[5:3] aluSrcSel Address Cell
Read Read regReadData2
Instruction ALU addreses,
Reg2 Data2
Memory 0, 2, 4, 6, ...
Mux Mux aluInput2
(IM) For LD
regWriteData
Write Read
Instr[8:6] Write Data Mux
Data
Reg
For ADD, regWriteIndexSel memReadData
ADDI, etc Write
Data
writeRegDataSel

writeRegData
Instr[11:6]
SignExt
Instr[11:0]
PC-offsets

3
The computer must run the following testbench code, each having its own instruction memory (IM)
tb0.sv: The instruction memory for this testbench has the following short program that checks if arithmetic-R-type,
arithmetic-immediate, and unconditional branch instructions work

ADD X1,XZR,XZR
Loop: ADDI X1,X1,#1
B Loop

tb1.sv: The instruction memory for this testbench has the following program that repeatedly multiplies 2 x 5 and stores
the product in X2. This tests the instructions in the testbench 0 and the conditional branch.

Loop1: ADDI X1,XZR,#2

ADD X2,XZR,XZR
Loop2: CBZ X1,Loop1
SUBI X1,X1,#1
ADDI X2,X2,#5
B Loop2

tb2.sv: The instruction memory for this testbench has the following program that repeatedly multiplies 2 x 5 and stores
the product in Memory [4] and X0. This tests the memory access instructions ST and LD.

Loop1: ADDI X0,XZR,#2

ST X0,[XZR,#2]
ST XZR,[XZR,#4]
Loop2: LD X0,[XZR,#4]
CBZ X0,Loop1
SUBI X0,X0,#1
ST X0,[XZR,#2]
LD X0,[XZR,#4]
ADDI X0,X0,#5
ST X0,[XZR,#4]
B Loop2

tb3.sv: The instruction memory for this testbench is modified from tb2.sv with the subroutine Funct. You should
change the datapath.

Loop1: BL Funct
Loop2: LD X0,[XZR,#4]
CBZ X0,Loop1
SUBI X0,X0,#1
ST X0,[XZR,#2]
LD X0,[XZR,#4]
ADDI X0,X0,#5
ST X0,[XZR,#4]
B Loop1
Funct: ADDI X0,XZR,#2
ST X0,[XZR,#2]
ST XZR,[XZR,#4]
BR X6

4
Tasks:

Grading:
Complete Points
tb1.sv 15
tb2.sv 24
tb3.xv 30

Submission Instructions:

Find a Windows folder with

• leglite.sv: The Leglite computer
• tb0.sv
• tb1.sv
• tb2.sv // Not available yet.
• tb3.sv // Not available yet.

Upload the following in laulima:

1. Your leglite.sv
2. The last testbench file that works, i.e., one of tb1.sv, tb2.sv, or tb3.sv. Do not include multiple testbench files.
Do not modify the testbench file unless instructed to do so.
3. README file which includes
a. Your name
b. Description of what you have completed (and not completed). For example “I have completed
testbench 2 but not testbench 3”.

Upload the files individually. Do not compress them (e.g., zip) or put them in folders.

Hints:
The code is not tiny but it’s not large either. The final version of systemverilog code should be around 300 lines without
the spaces, etc. So it’s very manageable. Start early and get tb1.sv done within the first week. It’s actually easy. Take
a look at the entire code. It follows the block diagram above.

Note that if-else and case statements are used to implement multiplexers. Also, the PC is updated with if-else
statements. This is a behavioral method of implementing multiplexing.

Don’t forget that you can use $display when debugging. You can also modify the $monitor statement to display values
including signals within submodules.

I used edaplayground. I lost my code at some point because the website was sensitive with touchscreens and the
mouse.