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Indian Institute of Technology Palakkad
Electrical Engineering
Research Admissions - January 2020 Semester
The candidates shortlisted for tests/interviews in the different advertised areas are given below.
Written tests and interviews will be held from November 25-27, 2019. Intimation emails will be sent on
October 29, 2019. Check the intimation email for more details.
Instructions and Information:
1. Test/Interview:
a) Dates: 25 – 27 November, 2019
b) Reporting Time: 12:30 pm, November 25, 2019
c) Reporting Venue: Academic Block, Ahalia Integrated Campus, IIT Palakkad, Kozhippara
P.O., Kerala
2. It is mandatory that the candidates confirm their attendance via email latest by 15 November,
2019 (ee-admissions@iitpkd.ac.in)
3. Last date for contacting department if there are any discrepancies: 5 November, 2019 (ee-
admissions@iitpkd.ac.in)
4. Institute has limited hostel facility (only cots and no beddings) on campus, which will be
allotted on first-request first-serve basis. There will be charge of Rs 50/- per day, for shared
accommodation in a double seated room. If you want to avail the hostel facility, please send an
email to hostelmanager@iitpkd.ac.in with your Application Number, Name, Check-in and
Check-Out time.
5. Please be prepared to stay for the three days of test/interview (25 – 27 November, 2019). The
accommodation is available only to the candidate, and only for the period of test/interview.
List of Things to Carry for Test/Interview:
1. A printout of the Application Summary page from the portal

2. A valid Photo Identity Card
3. Class 10 and 12: Original mark sheets and pass certificates
4. Undergraduate and postgraduate degree: Original certificates and original mark lists
5. National Level Tests mentioned in your application: Original Scorecards (GATE)
6. Other Ph.D. Fellowships mentioned in your application: Award Letters
7. A recent colour passport-sized photograph
8. Updated resume
9. Candidates who have not paid the application fee: A DD for Rs. 100/- drawn in favour of "IIT
Palakkad", payable at Palakkad, when they come for the test/interview.
Area 1: Communication and Signal Processing
Shortlisting Criteria:
Unreserved OBC/GEN-EWS SC/ST/PWD
MS Valid GATE score > 500 Valid GATE score > 450 Valid GATE score > 400
MTech from CFTI/Foreign MTech from CFTI/Foreign MTech from CFTI/Foreign
university with score ≥ 75% university with score ≥ 70% university with score ≥ 65%
OR OR OR
MTech from non-CFTI with MTech from non-CFTI with MTech from non-CFTI with
PhD
score ≥ 87% score ≥ 82% score ≥ 77%
OR OR OR
Best GATE score > 500 Best GATE score > 450 Best GATE score > 400
Shortlisted Candidates:
PhD
A19-EE4627 A19-EE4857 A19-EE4985 A19-EE5122 A19-EE5395 A19-EE5680

A19-EE4768 A19-EE4963 A19-EE5050 A19-EE5362 A19-EE5620
Syllabus of Written Test:
Linear Algebra: Vector space, basis, linear dependence and independence, matrix algebra, eigen values
and eigen vectors, rank, solution of linear equations – existence and uniqueness
Probability and Random Process: Mean, median, mode and standard deviation; combinatorial
probability, probability distribution functions - binomial, Poisson, exponential and normal; Joint and
conditional probability; Central limit theorem, law of large numbers, stationarity, autocorrelation and
power spectral density, properties of white noise.
Signals and Systems: Fourier series and Fourier transform representations, sampling theorem and
applications; Discrete-time signals: discrete-time Fourier transform (DTFT), DFT, FFT, Z-transform,
interpolation of discrete-time signals; LTI systems: definition and properties, causality, stability,
impulse response, convolution, poles and zeros, parallel and cascade structure, frequency response,
group delay, phase delay.
Communications: Analog communications – amplitude modulation and demodulation, angle

modulation and demodulation, super-heterodyne receivers; Digital communications – PCM, DPCM,
digital modulation schemes, ASK, PSK, FSK, QAM, MAP and ML decoding, matched filter receiver,
calculation of bandwidth, SNR and BER for digital modulation; inter-symbol interference and its
mitigation.
Area 2: Control and Robotics
Valid GATE score. If Institute Valid GATE score. If Institute Valid GATE score. If Institute
Staff, GATE score is not Staff, GATE score is not Staff, GATE score is not
MS needed. needed. needed.
BTech score ≥ 60% BTech score ≥ 55% BTech score ≥ 50%
PG score ≥ 65% PG score ≥ 60% PG score ≥ 55%

PhD
MS PhD
A19-EE4672 A19-EE4645 A19-EE4838 A19-EE5008 A19-EE5196 A19-EE5429 A19-EE5625

Control systems: Basic control system components; Feedback principle; Transfer function; Block
diagram representation; Signal flow graph; Transient and steady-state analysis of LTI systems;
Frequency response; Routh-Hurwitz and Nyquist stability criteria; Bode and root-locus plots; Lag,
lead and lag-lead compensation; State variable model and solution of state equation of LTI system
Electrical circuits: RLC circuits; Simple op-amp circuits; Active filters; Sinusoidal oscillators:
criterion for oscillation, single-transistor and op- amp configurations; Function generators,
wave-shaping circuits
Network theory: nodal and mesh analysis; Network theorems: superposition, Thevenin and
Norton’s, maximum power transfer; Wye‐Delta transformation; Steady state sinusoidal analysis
using phasors; Time domain analysis of simple linear circuits; Solution of network equations
using Laplace transform; Frequency domain analysis of RLC circuits; Linear 2‐port network
parameters: driving point and transfer functions; State equations for networks.
Signals and systems: Fourier series and Fourier transform representations, sampling theorem
and applications; Discrete-time signals: discrete-time Fourier transform (DTFT), DFT, FFT, Z-
transform, interpolation of discrete-time signals; LTI systems: definition and properties, causality,
stability, impulse response, convolution, poles and zeros, parallel and cascade structure, frequency
response, group delay, phase delay, digital filter design technique
Linear algebra: Vector space, basis, linear dependence and independence, matrix algebra, eigenvalues
and eigen vectors, rank, solution of linear equations – existence and uniqueness
Differential equations: First order equations (linear and nonlinear), higher order differential
equations, Cauchy's and Euler's equations, methods of solution using variation of parameters,
complementary function and particular integrals
Area 3: Digital VLSI Design
Valid GATE score Valid GATE score Valid GATE score

MS
BTech score ≥ 60% BTech score ≥ 55% BTech score ≥ 50%
PG score ≥ 70% PG score ≥ 65% PG score ≥ 60%

PhD
MS PhD
A19-EE4691 A19-EE4635 A19-EE5065 A19-EE5686

A19-EE4801 A19-EE4652 A19-EE5174 A19-EE5707
A19-EE4949 A19-EE4758 A19-EE5241
A19-EE5053 A19-EE4847 A19-EE5301
A19-EE5255 A19-EE4855 A19-EE5307
A19-EE5432 A19-EE4862 A19-EE5317
A19-EE5565 A19-EE4963 A19-EE5378
A19-EE5618 A19-EE4981 A19-EE5425
A19-EE5700 A19-EE5007 A19-EE5460
A19-EE5701 A19-EE5011 A19-EE5491
A19-EE5714 A19-EE5027 A19-EE5553
A19-EE5718 A19-EE5054 A19-EE5599
Digital System Design: Introduction to Digital systems and Boolean Algebra : Binary, octal and
hexadecimal number systems; Basic logic operation and logic gates; Logic families -- TTL, CMOS;
Combinational Logic : Decoder, encoders, multiplexers, demultiplexers and their applications;
Arithmetic circuits; Representation of signed numbers; Adders -- ripple carry, carry look ahead, BCD
adders; Sequential Logic : Latches and flip flops -- SR latch, D latch, D flip-flop, JK flip-flop, T flip-flop;
Setup and hold parameters; Timing analysis; Registers and counters; Shift register; Synchronous
counter design using D, SR, JK flip-flops; State Machine Design : Definition of state machines; State
machine as a sequential controller; Moore and Mealy state machines; Derivation of state graph and
tables; Sequence detector; State table reduction using Implication table; Design state machine using
ASM charts; Memory and Programmable Logic Devices : Read Only Memories, read/write memory --
SRAM/DRAM; PLAs and their applications; PLDs and their applications; FPGAs; Hardware description
language: Modeling combinational and sequential circuits using Verilog/VHDL.
Area 4: Measurements and Instrumentation
Valid GATE score with UG Valid GATE score with UG Valid GATE score with UG
OR OR OR
MS
IIT Palakkad staff with UG IIT Palakkad staff with UG IIT Palakkad staff with UG
UG score ≥ 70% and PG UG score ≥ 65% and PG UG score ≥ 60% and PG

OR OR OR
PhD
UG and PG score ≥ 65% and at UG and PG score ≥ 60% and at UG and PG score ≥ 55% and at
least 1 journal publication least 1 journal publication least 1 journal publication
MS PhD

Electrical Circuits: Voltage and current sources: independent, dependent, ideal and practical; v-i
relationships of resistor, inductor, mutual inductor and capacitor; transient analysis of RLC circuits with
dc excitation. Kirchoff’s laws, mesh and nodal analysis, superposition, Thevenin, Norton, maximum
power transfer. Peak-, average- and rms values of ac quantities; series and parallel resonance,
realization of basic filters with R, L and C elements.
Analog Electronics: Characteristics and applications of the diode, Zener diode, BJT and MOSFET; small-
signal analysis of transistor circuits, feedback amplifiers. Characteristics of operational amplifiers;
applications of opamps: difference amplifier, adder, subtractor, integrator, differentiator,
instrumentation amplifier, precision rectifier, active filters and other circuits. Oscillators, signal
generators, voltage-controlled oscillators and phase-locked loop.
Measurements: SI units, systematic and random errors in measurement, propagation of errors. dc
potentiometer; bridges for measurement of R, L and C. digital voltmeter, digital multimeter;
oscilloscope, shielding and grounding.
Signals and Systems: Periodic, aperiodic and impulse signals; Laplace, Fourier and z-transforms;
transfer function, frequency response of first and second-order linear time-invariant systems, impulse
response of systems; convolution, correlation. Discrete-time system: impulse response, frequency
response.
Area 5: Nanoelectronics, Plasmonics & Semiconductor Devices
Valid GATE score Valid GATE score Valid GATE score

[GATE score is not required for [GATE score is not required for [GATE score is not required for
part-time candidates] part-time candidates] part-time candidates]
with UG score ≥ 60% with UG score ≥ 55% with UG score ≥ 50%
MS
OR OR OR
UG from CFTI with CGPA ≥ 8/10 UG from CFTI with CGPA ≥ 7.5/10 UG from CFTI with CGPA ≥ 7/10
UG & MTech/ME score ≥ 60% UG & MTech/ME score ≥ 55% UG & MTech/ME score ≥ 50%
OR OR OR
Valid GATE score or UGC/CSIR- Valid GATE score or UGC/CSIR- Valid GATE score or UGC/CSIR-
NET/NBHM/INSPIRE or NET/NBHM/INSPIRE or NET/NBHM/INSPIRE or
PhD equivalent qualification with UG equivalent qualification with UG equivalent qualification with UG
& MSc score ≥ 60% & MSc score ≥ 55% & MSc score ≥ 50%
OR OR OR
[for Direct PhD] UG from CFTI [for Direct PhD] UG from CFTI [for Direct PhD] UG from CFTI
with CGPA ≥ 8/10 with CGPA ≥ 7.5/10 with CGPA ≥ 7/10
MS PhD

Syllabus:
Solid-state devices – Energy band formation, Concept of holes, Density of states and Fermi level;
equilibrium carrier concentration, intrinsic and extrinsic semiconductors, Recombination and
generation of carriers, carrier transport: drift and diffusion, Equations of state, Continuity and Poisson
equation; excess carriers, injection level, carrier lifetime; energy band-diagrams, p-n junctions:
equilibrium condition, contact potential, forward and reverse bias, I-V characteristics; metal-oxide-
semiconductor devices: MOS capacitor, MOSFET: physics and I-V characteristics; Schottky junctions.
Resources:
[1] B. G. Streetman and S. Banerjee, “Solid State Electronic Devices,” Pearson Education India; Seventh
edition (2015).
[2] S. Karmalkar, “Solid state devices,” NPTEL video lectures: http://nptel.ac.in/courses/117106091/.
Area 6: Power System Engineering
Valid GATE score [GATE score is Valid GATE score [GATE score is Valid GATE score [GATE score is
not required for part-time not required for part-time not required for part-time
MS
candidates] and B.Tech. score ≥ candidates] and B.Tech. score ≥ candidates] and B.Tech. score ≥
75% 70% 65%
Masters in Engg/Tech with score Masters in Engg/Tech with score Masters in Engg/Tech with score
≥ 70% ≥ 65% ≥ 60%
OR OR OR
Best GATE score ≥ 430 Best GATE score ≥ 380 Best GATE score ≥ 330
PhD
OR OR OR
IIT Palakkad staff with IIT Palakkad staff with IIT Palakkad staff with
postgraduate score ≥ 70% postgraduate score ≥ 65% postgraduate score ≥ 60%
MS PhD

Power systems: Transmission line modeling, characteristics of transmission lines, load flow studies,
power system dynamics and control, automatic generation and voltage control, fault analysis, power
system transients, power system protection, over-current relay, distance protection, differential
protection,power system stability, voltage stability, high voltage DC transmission,power quality, state
estimation in power system, compensation in power systems, renewable energy systems.
References:
[1] Stevenson, W.D., Elements of Power System Analysis,4TH edn, McGraw-Hill,New York, 1982.
[2] Kundur, P., Power System Stability and Control, McGraw-Hill, New York, 1994.
Area 7: RF and Microwave
B.Tech. score ≥ 65 % and B.Tech. score ≥ 60 % and B.Tech. score ≥ 55 % and

PhD
M.Tech. score ≥ 65 % M.Tech. score ≥ 60 % M.Tech. score ≥ 55 %
PhD

A19-EE4768 A19-EE5042 A19-EE5240 A19-EE5504
Electromagnetics - Time varying fields and Maxwell’s equations, Plane electromagnetic waves in free
space, Reflection and transmission of an interface, Rectangular Waveguides, Transmission lines and
Antennas.
Resources
[1] Pozar, D.M.: ‘Microwave engineering’ (John Wiley & Sons, 1998, 2nd edn.)
[2] Collins, R.E.: ‘Foundations for microwave engineering’ (Wiley-IEEE Press, 1984, 2nd edn.)
[3] R. Garg, P. Bhartia, I. Bahl, and A. Iittipiboon, Microstrip Antenna Design Handbook. Boston, MA:
Artech House, 2001.

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Indian Institute of Technology Palakkad

Instructions and Information:

List of Things to Carry for Test/Interview:

1. A printout of the Application Summary page from the portal

Unreserved OBC/GEN-EWS SC/ST/PWD

A19-EE4627 A19-EE4857 A19-EE4985 A19-EE5122 A19-EE5395 A19-EE5680

Syllabus of Written Test:

Communications: Analog communications – amplitude modulation and demodulation, angle

Unreserved OBC/GEN-EWS SC/ST/PWD

BTech score ≥ 60% BTech score ≥ 55% BTech score ≥ 50%

PG score ≥ 65% PG score ≥ 60% PG score ≥ 55%

A19-EE4672 A19-EE4645 A19-EE4838 A19-EE5008 A19-EE5196 A19-EE5429 A19-EE5625

Syllabus of Written Test:

Unreserved OBC/GEN-EWS SC/ST/PWD

Valid GATE score Valid GATE score Valid GATE score

PG score ≥ 70% PG score ≥ 65% PG score ≥ 60%

A19-EE4691 A19-EE4635 A19-EE5065 A19-EE5686

Syllabus of Written Test:

Unreserved OBC/GEN-EWS SC/ST/PWD

UG score ≥ 70% and PG UG score ≥ 65% and PG UG score ≥ 60% and PG

A19-EE4712 A19-EE4659 A19-EE4917 A19-EE5027 A19-EE5211 A19-EE5395 A19-EE5637

Syllabus of Written Test:

Unreserved OBC/GEN-EWS SC/ST/PWD

Valid GATE score Valid GATE score Valid GATE score

A19-EE4744 A19-EE4635 A19-EE4970 A19-EE5124 A19-EE5378 A19-EE5713

Unreserved OBC/GEN-EWS SC/ST/PWD

A19-EE4648 A19-EE4960 A19-EE4953 A19-EE5258 A19-EE4700 A19-EE5045 A19-EE5300

Unreserved OBC/GEN-EWS SC/ST/PWD

B.Tech. score ≥ 65 % and B.Tech. score ≥ 60 % and B.Tech. score ≥ 55 % and

A19-EE4627 A19-EE4827 A19-EE5050 A19-EE5261 A19-EE5507

Syllabus of Written Test:

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