A Hardware Based Low Temperature Solution for
VLSI Testing using Decompressor Side Masking
Arpita Dutta1, Subhadip Kundu2, Santanu Chattopadhyay1, Bijit Kumar Das1
Dept. of E&ECE, Indian Institute of Technology Kharagpur, India1, Synopsys India Pvt. Ltd2.
dutta.arpita2011@gmail.com1,subhadip@synopsys.com2, santanu@ece.iitkgp.ernet.in1, bijitbijit@gmail.com1
Abstract— The temperature of a block (a region in the chip)
depends on both heat generation (caused by power
consumption) and heat dissipation among neighbors. Power
aware test solutions targeting low power consumption during
testing, may not produce an acceptable thermal aware
solution. In this paper, a hardware based solution using an
AND-OR block between the decompressor and each scan
chain, has been utilized to deactivate some scan chains
during loading to reduce peak temperature during testing.
The proposed schemes require negligible hardware overhead
and do not require any special patterns. Experimental results
of our proposed approach on ISCAS’89 and ITC’99
benchmark circuits show a good reduction in peak
temperature.
Keywords— HotSpot, AND-OR block, Decompressor side
masking, Scan Cell Clustering.
I. Introduction
High test power may lead to permanent or temporal
malfunction of a good chip leading to yield loss. Excessive
switching activity increases the overall circuit temperature
and creates localized heating, called hotspots [1].
Advanced cooling techniques are effective to solve the
high temperature problems, but they substantially increase
the overall system cost and/or require larger area.
Minimizing power consumption can reduce the overall
temperature of the circuit under test (CUT). However this
need not necessarily minimize the peak [2], as it may lead
to localized heating called hotspots due to non-uniformity
in the spatial power distribution. The peak temperature of a
block depends on its own power density, as well as heat
transfer or heat exchange between the adjacent blocks [2].
Reducing power consumption can control heat generated,
but heat dissipation is a function of the thermal gradient
between CUT and the ambient air resulting temperature
differences across the circuit. Thus with increasing chip
density, power aware testing has proven inadequate and
has to be replaced by thermal aware strategies.
Several temperature aware techniques are described in
the literature. PEAKASO algorithm of [3] minimizes the
peak temperature by scan vector reordering based on
overheat pre-compensation. [4], [5], [6], [8] describe
thermal safe test scheduling techniques. Several thermal
aware X filling techniques such as [7], [9] concentrate
more on minimizing peak temperature and thermal
variance as well as circuit power.
In [11], a design for diagnosis (DFD) architecture to
diagnose single and multiple faults in a scan chain has
been proposed which inserts an “AND" and an “OR" gate
*This work is partially supported by the research project “Thermal Aware Testing of VLSI Circuits and Systems”, sponsored by the DeitY, Govt. of India.
978-1-4799-8391-9/15/$31.00 ©2015 IEEE
in between the on-chip decompressor and every scan chain
to control values that are applied to chains. Similar
structure, using only AND gate, has been proposed in [13]
to reduce power during testing. Another structure has been
proposed in [14] for low power BIST scheme.
In this paper, we have evaluated the AND-OR block
[11] for low temperature solutions. Initially, scan flip-flops
are distributed among scan chains in order to distribute the
input cone of scan flip-flops for each output over a
minimum number of chains. Then, a thermal aware mask
generation algorithm for the AND-OR block has been
described. The mask generation utilises the fact that a
compressed test set has redundancy in fault detection. For
example, a single fault may be detected by multiple
patterns at multiple outputs; out of which, detection by
only one test pattern at any one output is sufficient. This
redundancy can be intelligently used to deactivate some
chains during shifting. Since the AND-OR block can feed
a constant zero or a constant one to any chain, it can be
used to mask the chains which are not required to detect
important faults for the pattern. Thus the strategy is to
identify the chains required to detect only the important
faults for a test pattern. The remaining chains can be fed
with constant zero or one using the AND-OR block. So,
there will not be any transition in those chains during
loading, leading to a significant reduction in power as well
as temperature with no loss in fault coverage. It is to be
noted that scan out power reduction requires special
circuitry to control the individual scan clocks, so that they
can be turned off during unloading which in turn increases
hardware overhead and design complexity. Most of
the work [11], [14] have not controlled unloading process.
In this work as our objective is to evaluate the AND-OR
based architecture proposed in [11] for a low temperature
mask generation, controlling unloading process has not
been taken into consideration.
The rest of the paper is organized as follows. Section II
presents the AND-OR architecture, which is used in the
work. Section III details low temperature mask generation
algorithm. Experimental results have been presented in
Section IV. Section V summarizes our conclusion.
II. AND-OR based Decompressor Side Masking
In [11], an “AND” and an “OR” gate are inserted in
between the on-chip decompressor and every scan chain.
The AND-OR network is controlled using pairs of control
signals (C11, C12) to (Cn1 and Cn2) which are generated
based on flush (chain) test result by an interactive ATE.
The test patterns go through the AND-OR network before
637
being loaded into the scan chains and are modified
according to the control values. The structure is given in
Figure 1.
In the tester, along with each pattern, their low
temperature mask signals will be stored in a compressed
format. First flush patterns will be applied. If the flush test
passes, stored low temperature mask signals will be
applied to the chains. Otherwise, the FSM will generate the
diagnostic mask signals for each pattern based on the flush
test responses [11]. The multiplexer will select the low
temperature mask signals and apply it to the CUT. There
will be an on chip decompressor which will decode the
compressed mask signal and apply it to the AND-OR block
of different chains. The basic block diagram of the tester is
shown in Figure 2.
Fig.1. Proposed Masking Scheme
Fig.2: Proposed Architecture
III. Low Temperature Scan Chain Masking
The technique first tries to group the scan flip-flops into
scan chains in order to distribute the input cone of flip-
flops for each output over a minimum number of chains.
Then an algorithm has been proposed to select some
outputs based on its importance for each pattern. Chains
containing the flip-flops in the input cone of the selected
outputs are observed. The rest of the chains are fed with
either constant one or zero using the AND-OR block
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leading to a significant reduction in temperature. In the
following, each step has been discussed in details.
A. Grouping of DFFs into Scan chains
A hypergraph is built by choosing an output for a
particular fault and finding its input cone. A hyperedge is
constructed by considering the flip-flops present in the
output’s input cone of influence. Once the hypergraph has
been created, the partitioning has been performed using:
the heuristic given in [12]. It is based on a linear time
heuristic to partition the hypergraph. The heuristic
algorithm is divided into three major steps: initial
configuration, graph partitioning, and post processing.
The proposed heuristic given in [12] is test set
independent and does not imply any scan chain reordering.
Scan chain clustering by the method does not introduce
any additional impact in the tool flow.
B. Low Temperature MASK Generation
We have proposed two masking techniques in this paper.
I. Maximum number of chains masking
II. Thermal aware masking
The following variables are used in the proposed
algorithms.
Detection Count: Detection count for a fault is the count
for the number of patterns (including the current one) that
still detect that fault.
Essential Faults: Essential faults for a pattern are those
faults detected by only this pattern (Detection Count 1).
Essential Outputs: The outputs in which at least one
essential fault has been detected by a pattern are termed as
essential outputs for that pattern.
Scan Distribution List: List of chains in which DFFs of an
output’s cone of influence are distributed. The number of
the chains in an output’s Scan Distribution List is stored in
the variable Distribution Count.
Weight of an output: We have used this term for the
generation of mask for maximum chain masking. It
depends on the faults detected at an output by a test pattern
and on the output’s Distribution Count.
Let k faults be detected in an output Oj by a test pattern ti.
Let each fault’s Detection Count be denoted by Dl (1 ≤ l ≤
k). Let the Distribution Count for the output Oj be Distrij .
Let Max Distri be the maximum of Distribution Count
over all the outputs.The weight of an output is given by the
following equation:
∑
W(Oij) = …(Eq. 1)
_
The weight of an output indicates how important that
output is for the current test pattern. The importance not
only depends on how many faults are detected on that
output but also on the faults’ detection count. When an
output detects faults with the lower detection count, its
weight goes up. For the chosen output, all chains in its scan
distribution list, are kept unmasked, while the remaining
chains are masked off. Since, we are trying to mask as
many chains as possible, output’s distribution count should
also be accounted for. An output with higher distribution
count will have lower weight. Max Distri is used to
normalize the denominator.
Peak Temperature of an output: We have used this term
for generation of low temperature mask. It depends upon
the Scan Distribution List of a particular output. The
floorplan of the circuit has been divided into number of
blocks. When all the chains in its Scan Distribution List are
active together, the block temperatures have been found
out by simulating in thermal tool HotSpot [10]. Then the
maximum temperature has been found out. This maximum
temperature is termed as Peak Temperature of that
particular output.
The peak temperature of an output indicates how “hot”
the circuit can be due to simultaneous activation of the
scan chains in its Scan Distribution List.
The algorithm (given in Algorithm 1) first performs
fault simulation and finds the essential faults and essential
outputs for a pattern. For the first masking technique
termed as (I), it calculates the weight of each essential
output and finds the output with maximum weight. For the
second masking scheme termed as (II), it calculates the
peak temperature of each essential output and selects the
output with minimum peak temperature. Then, the chains
in the selected output’s Scan Distribution List are marked.
Faults detected on this output are dropped from the rest.
Now, usually, Scan Distribution List of the other essential
outputs has some common chains with the selected one’s.
Since the marked chains will not be masked anyway, their
presence on the other chain’s Distribution Count can be
removed. So, Distribution Count for all the other chains is
modified. The weight for each output is calculated again
taking account of the fault dropping and modified
Distribution Count. The same procedure continues until all
the essential faults are detected.
All the marked chains are kept unmasked. The rest of
the chains are masked with either feeding all zeros or all
ones. For the first pattern, all the unmarked chains are
masked to load all zero. For all other patterns, loading
values to the masked chains are selected to minimize
temperature.
Once the mask signals have been decided for all the
chains, the pattern is modified according to it. A fault
simulation has been performed with the modified pattern.
Faults detected by the pattern are dropped. The Detection
Count of the faults which are not detected by the modified
pattern but were detected by the original one, are reduced
by one. This step ensures that even if a fault is not an
essential one in the start of the process, it can become
essential for some pattern later in the process. When it
becomes essential, it has to get detected - ensuring that the
fault coverage remains same.
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Distribution Count for each output has been restored to
its original value. All chains are unmarked and the
procedure continues for the rest of the patterns.
Algorithm 1: Maximum Number of Chains Masking
and Low Temperature MASK Generation
1. Begin
2. for all patterns ti in TS do
3. Unmark all the chains;
4. Perform fault simulation;
5. Find the essential faults and in turn essential
outputs for the pattern;
6. while there is an essential fault still to be
detected do
7. Find weight according to Eqn. 1 and the
peak temperature of essential outputs which
are not selected yet for (I) masking scheme
and for (II) masking scheme respectively;
8. Find maximum weight output for (I) scheme
and the minimum peak temperature output
for (II) scheme and mark the chains in the
Scan Distribution List of the selected one as
unchanged;
9. Drop the faults detected on the output by the
pattern on other output;
10. Change the Detection Count of other essential
outputs according to the selected one;
11. end while;
12. Mask the unmarked chains and modify the pattern
according to the mask signals and perform fault
simulation;
13. Drop the detected faults from the fault list;
14. Restore the original Distribution Count for each
output;
15. Modify the Detection Count for the faults
according to the detection status;
16. end for;
17. end;
IV. Experimental Results
We have obtained results on ISCAS’89 and ITC’99 full
scan benchmark circuits. The scan cells are distributed
over multiple chains. Fully compressed test patterns are
generated using Synopsys TetraMAX tool. Circuits are
synthesized using Design Vision logic synthesis tool using
the Faraday 90nm library (fsd0a generic core, best case).
Floorplan have been generated by Cadence Encounter and
converted into blocks. Thermal simulation has been
performed by the tool HotSpot [10] feeding the total shift
power of the circuit blocks using the mask signal
generated. Table 1 reports the peak temperature in degree
Kelvin attained by the proposed methods as well as the
percentage reduction achieved over a normal compressed
test set. Results are reported in the pairs (a, b), where a
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Table 1: Peak Temperature in degree Kelvin (K) and % Reduction in Peak Temperature for Proposed Masking Techniques
over Normal Test Set
Normal (I) Masking Scheme (II) Masking Scheme
Circuit Compressed Proposed Normal Proposed Normal
Test Set Partitioning Partitioning Partitioning Partitioning
s5378 700.72 624.86, 10.83% 664.00, 5.24% 615.86, 12.11% 660.24, 5.78%
s9234 772.66 730.72, 5.43% 765.79, 0.89% 712.84, 7.74% 760.00,1.64%
s13207 840.90 768.44, 8.62% 823.08, 2.12% 758.48, 9.80% 811.83, 3.46%
s15850 835.89 767.21, 8.22% 823.39, 1.50% 759.41, 9.15% 817.49, 2.20%
s38417 821.81 759.59, 7.57% 752.60, 8.42% 747.55, 9.04% 746.66, 9.14%
s38584 993.93 920.88, 7.35% 982.67, 1.13% 903.34, 9.11% 975.03, 1.90%
b13 748.10 643.03, 14.04% 705.18, 5.74% 640.03, 14.45% 700.18, 6.41%
b14 737.13 646.26, 12.33% 703.25, 4.60% 638.07, 13.44% 698.34, 5.26%
b15 722.09 568.20,21.31% 644.16, 10.79% 556.19, 22.97% 640.41, 11.31%
b20 790.39 724.98, 8.28% 746.60, 5.54% 715.28, 9.50% 739.33, 6.46%
b21 793.18 753.35, 5.02% 764.33, 3.64% 740.67, 6.62% 758.58, 4.36%
Avg. % Reduction 9.91 4.51 11.27 5.27

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