On the Ultimate Limits of IC Inductors-An RF MEMS Perspective

Hector J. De Los Santos

COVENTOR, Inc.
7 Corporate Park, Suite 260, Irvine, CA 92606

Trace resistance, due to its finite conductivity and width; (3)

Abstract
Substrate capacitance and ohmic losses, due to their shunting
Inductors are playing an ever-increasing role in RFICs, of the input signal to ground and, thus, causing less than the
motivating extensive work on the development of structures to
input signal to reach the output. These loss elements are
achieve optimized performance. In this paper we review the embodied by the circuit model of Fig. 2 [ 101.
different approaches being explored to achieve high inductor
Q and self-resonance frequency, in the context of conventional
CMOS and BiCMOS processes, and examine how the
application of RF MEMS techniques may effect superior
monolithic inductor performance, and at what expense.
Introduction
Inductors are playing an ever-increasing role in RFICs [ 1-
41. In addition to being frequently employed in passive tunkg Silic
circuits, or as high-impedance chokes, many novel techniques
to achieve low-voltage operation in advanced silicon IC
processes rely on the negligible DC voltage drop across
inductors when utilized as loads or as emitterhource
degenerators [3-41. When fabricated in a planar process, the
trace capacitance to ground tends to lower the inductor self- Figure 1. Planar inductor [SI.
resonance frequency, and the substrate conductivity tends to
lower its quality factor (Q) [5]. While optimization of the
spiral geometry and line width [2], 15-61 is essential to tailor
the frequency of maximum Q, this exercise only addresses
minimization of the trace o h c losses and substrate
capacitance. Thus, a number of attempts to use conventional
processing techniques to diminish the substrate losses created
by eddy currents induced by the magnetic field of the spiral COXL COX
have been pursued. For instance, while [5] introduced
blocking p-n-p junctions in the path of the eddy current
T T
flowing in an underlying p+ layer, [7] introduced a patterned
metal ground shield to also block the eddy current. These, and
similar approaches, however, only achieve modest relative
improvements and, certainly, do not achieve Qs much greater
than 10, or self-resonance frequencies greater than a few GHz.
The fabrication flexibility afforded by Figure 2. Equivalent circuit model of planar inductor
microelectromechanical systems (MEMS) technology is [lo].
expected to greatly enhance the performance of monolithic RF
passive devices but, by how much and at what expense? In this A multitude of ways to address one or more of the above
paper, for the first time, we present an analysis of RFIC inductor performance-limiting factors, in the context of
inductors build in both conventional and RF MEMS conventional Si processes, have been advanced. Next,
technologies, and establish a projection of their ultimate respective typical cases are reviewed.
achievable performance limits. Eddy current blocking structures are shown in Fig. 3. In
these structures, the eddy current, which flows in paths around
Conventional RFIC Inductors the axis of the spiral, is reduced by introducing structures that
The fundamental monolithic inductor is usually increase the path resistance. In the example of Fig. 3(a) [5],
implemented as a spiral trace disposed on the passivation layer this is accomplished by inserting narrow stripes of n+ regions
over a silicon substrate, Fig. 1. The connection to the perpendicular to the current flow such as to create blocking p-
innermost turn is effected either through an underpass, or via n-p junctions. This blocking structure resulted in a Q
an airbridge. An examination of the fundamental structure improvement from 5.3 to 6.0 (13.2%) at 3.5 GHz on a 1.8nH
reveals the following sources of performance degradation [9]: inductor, obtaining an inductance-per-tum of 0.9nH.
(1) Eddy current-induced losses, due to magnetic field
penetration into both the substrate and adjacent traces; (2)

0-7803-7430-4/02/$17.0002002 IEEE 1027 2002 Electronic Components and Technology Conference

 Si substrate ( p - 5 - io n . cm ), implanting ions in
- ~3 x 1019~ 1 1 2 -,~
concentrations ranging from 1x 1019~ r n to
resulted in Qs between 3.8 and 5.8, respectively, at about 2
GHz for 1.lnH to 1.25nH inductance values, obtaining an
inductance-per-turn of -0.781-H.
Approaches to reduce metal trace losses, Fig. 4, invcdve
A reduction of both conduction- and magnetically-induced
losses.

I
, I, ! ! SpiralLines
E Field \/ ' SoiralTrace

\ ll/ j j
I +I-
i j I ,
p Substrate
I \, I /

n+ Blocking Structure
(a)
I

r kcitation
mat
Eddy CduTult Loops

Figure 4. Losses in inductor metal trace [12].

Slots between Strips
(b)
Figure 3 (a) Eddy-current blocking approaches: (a) p-n-p
junction perpendicular to current flow path [SI. (b)
Patterned metal ground plane with open slots [7].
In the pattemed-ground approach, Fig. 3(b) [7], slots,
oriented perpendicularly to the spiral, are etched in the ground
plane. These, act as open circuits to impede the path of the
eddy currents. The slots are made with a width narrow enough
to preclude the vertical electric field from penetrating down to
the underlying silicon, and merge together at a metal strip
around the periphery. Implementation of this scheme has
resulted in a Q improvement from 5.08 to 6.76 (33%) at 2
GHz on a 7.5 nH inductor, obtaining an inductance-per-turn of
1.07nH.
In the substrate damage approach [l 11, the low-resistivity
of the Si substrate is increased by disordering the lattice sites,
i.e., by damaging the lattice structure with high-energy-
implanted (2OOkeV) si:, ions. Starting with a low-resistivity
From a study of the field distribution in a spiral [2], [91], it
was determined that ohmic losses are predominant in the outer
tums, while, since the magnetic field reaches a maximum near
the axis, magnetic losses predominate in the inner tums.
Accordingly, an algorithm to vary the trace width from a small
width for the inner tums, to a larger width for the outer tums,
resulted in a layout-optimized structure, Fig. 5. For inductors
realized over an etched bulk (so as to not have substrate losses
present) with metal traces exhibiting 20rn!2 sheet
resistances, this approach yielded a measured Q of 17 at 1.5
GHz for a 34nH inductor, and predicted Q values greater lhan
40 for a 20nH inductor at 3.5 GHz, which represen1.s a
projected Q improvement of 60%, with respect to single stip-
width inductors operating also at 3.5GHz [9].
Figure 5. Metal loss-optimized inductor layout [91.
Recent work [131 aimed at obtaining both increased Q and
self-resonance frequency, without process modifications, have
concluded that differentially driven inductors have the
potential to exhibit (ideally) double the Q and increased Iself-
resonance frequency, with respect to single-ended inductors,
due to the reduced effect of the substrate shuntparasitic:s in
the differential case. With the voltages and currents at Ports 1

1028 2002 Electronic Components and Technology Conference

and 2 excited 180” out of phase, when differentially excited, R F MEMS-Enabled Inductors
Fig. 6, a useful property of the structure is that the trace In RF MEMS technology, the power of surface and bulk
currents flow in the same directions and this increases the micromachining fabrication techniques [ 171 is exploited to
inductance per unit area. either suspend within the bulk [18], or elevate above the wafer
surface [19], inductor structures, thus eliminating the major
Underpass i Axis of Symmetry
sources of performance degradation.
Bulk micromachined inductors, similar to that shown in
Fig. 7, are realized by removing the substrate under the
Node inductor spiral via top-side etching [18]. This type of structure
resulted in a self-resonance frequency enhancement from 800
MHz to 3 GHz, upon substrate removal, and a Q of 22 at 270
MHz on an 115nH inductor, obtaining an inductance-per-turn
ratio of 5nH [11.

Figure 6. Symmetrical differentially driven microstrip

inductor [13].
The approach has resulted in Qs of 6.6 and 9.3 at 1.6 GHz
and 2.5 GHz, respectively, for an inductor of 8nH [13].
As may be surmized by examining the approaches
presented thus far for optimizing planar inductors in
conventional silicon processes, these fall into two fundamental Figure 7. Bulk-micromachined inductor 1181.
categories, namely, substrate insulation techniques, and layout While the performance of bulk micromachined inductors
optimization techniques. Two other opportunities for improves upon that of their conventional counterparts,
performance enhancement may be also available, depending questions have been raised regarding their ruggedness to
on the number of top metal interconnect lavels and the ability withstand subsequent wafer processing, lack of a good RF
to increase the thickness of the traces. Pertaining to these, the ground, and susceptibility of their characteristics to
following examples are relevant: (1) A 1.88nH inductor with a electromagnetic coupling. This issues were addressed in the
Q of 6-10 at 4GHz fabricated on a 10 Q . cm / I - 3 p m elevated structure of Fig. 8 [19]. The structure consists of an
single-metal process, demonstrated by Long and Copeland elevated inductor suspended over a 3 0 p -deep copper-lined
[14]; (2) A 13nH inductor with a Q of 12 at 3GHz fabricated cavity etched in Si bulk. The cavity depth is chosen such that
on a 2 kn . cm 1 2 p m double-metal process, demonstrated the eddy currents induced in the metal shield are small.
by Park et al. [l5]; and (3) A 2.2nH inductor with a Q of 16 at Cu-Encapdated
2GHz fabricated on a 12 k~ . cm / 4 . 3 p m triple-metal
process, demonstrated by Burghartz et al. [16].
Clearly, in light of the fact that most commercial silicon
bipolar and BiCMOS processes employ wafers with
resistivities in the neighborhood 10 Q . cm , and that to
reduce hot-electron induced substrate currents, as well as
isolate sensitive analog circuits from noisy digital circuits,
most sub-micron CMOS wafers employ substrates with
resistivities around 0.01 n . cm [2], it is not difficult to see
that the substrate poses the ultimate limitation on the Figure 8. Schematic of a copper-encapsulated polysilicon
performance of IC inductors. Some estimates [ 141, in fact, set inductor suspended over a copper-lined cavity beneath
this limit at approximately a Q less than 10 in the 1-3GHz 1191.
range for a 1nH inductor. This approach yielded a Q of 30 at 8 GHz on a 10.4nH
The potential of RF MEMS technology to overcome the inductor with a self-resonance frequency of 10.1 GHz,.and an
“substrate barrier” limiting the performance of IC inductors is inductance-per-turn of 1.48nH.
presented next.

1029 2002 Electronic Components and Technology Conference

 While substrate removal and shielding, and spiral
elevation do improve inductor performance, the remaining
parasitic capacitance, between metals trace and the substrate,
poses the ultimate limitation on improvement. The solenoid
inductor, Fig. 9, addresses these issues [20].
Figure 9. SEM photograph of 20-turn, on-Si, air-core, all-
copper solenoid inductor(upper: overview, lower:
magnified view) [20].
This approach yielded a Q of 16.7 at 2.4 GHz on 2.67 nH
inductors, with an inductance per-tum of 0.136nH. One
advantage of solenoid inductors, over spiral ones, is that they
exhibit a linear relationship between inductance and number
of turns.
Another approach aimed at decoupling inductor properties
from those of the substrate is the self-assembly principle, Fig.
10 [21].
Figure 10. 4lh-tu1-nmeander inductor after self-assembly
1211.
In this approach, solder surface tension self-assembly is
used to bring planar inductor structures perpendicular to the
substrate. It has yielded improvements in the Q of 2nH
meander inductors from 4 at lGHz, for the planar realization,
to 20 at 3 GHz for the self-assembly implementation, with
0.44nH per turn [21].
1030
RF MEMS Perspective on RFIC Inductors
As demonstrated in the previous section, the versatility of
RF MEMS fabrication technology to decouple IC inductor
performance from substrate characteristics is unquestionable.
It might appear, however, that, to take advantage of it, one
would have to incur “extra” processing steps, and this is
indeed the case. Nevertheless, the fact that these estra
processing steps may be implemented as a “post-process
module” [22], that does not require chip manufacturer!; to
modify their high-volume fabrication processes, makes the
approach extremely appealing, given the enabling capability
of RF MEMS. Indeed, as the frequency capability of advanced
silicon IC processes increases to many multiples of GHz, the
concomitant manifestation of substrate losses will become
progressively more difficult to circumvent. The future, thus,
will inexorably lead to RF MEMS.
Conclusions
The performance of monolithic RFIC inductors has made
great strides, despite the limits set by poor subslrate
characteristics, in particular, low resistivity. In this context, it
is expected that inductors with Qs and inductance markedly
greater than 10 and lnH, respectively, in the 1-4GHz
frequency range will not be possible. Therefore, the extension
of silicon processes to higher frequency wireless applications
will inexorably lead to the exploitation of RF MEMS, via
post-processing techniques.
Acknowledgments
I would like to thank ECTC 2002 Program Committee
member Ms. Lei Mercado, of Motorola, Inc., for the invita.tion
to contribute this paper.
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