January 2002
IRF640N/IRF640NS/IRF640NL
N-Channel Power MOSFETs
200V, 18A, 0.15Ω
Features • Peak Current vs Pulse Width Curve
GATE D
SOURCE
DRAIN G
(FLANGE)
S
TO-263 TO-262 TO-220
Thermal Characteristics
RθJC Thermal Resistance Junction to Case TO-220, TO-262, TO-263 1.0 oC/W
RθJA Thermal Resistance Junction to Ambient TO-263, 1in2 copper pad area 40 oC/W
Off Characteristics
BVDSS Drain to Source Breakdown Voltage ID = 250µA, VGS = 0V 200 - - V
VDS = 200V, VGS = 0V - - 25
IDSS Zero Gate Voltage Drain Current µA
VDS = 160V TC = 150o - - 250
IGSS Gate to Source Leakage Current VGS = ±20V - - ±100 nA
On Characteristics
VGS(TH) Gate to Source Threshold Voltage VGS = VDS, ID = 250µA 2 - 4 V
rDS(ON) Drain to Source On Resistance ID = 11A, VGS = 10V - 0.102 0.15 Ω
gfs Forward Transconductance VDS = 50V, ID = 11A (Note 2) 6.8 - - S
Dynamic Characteristics
CISS Input Capacitance - 2200 - pF
VDS = 25V, VGS = 0V,
COSS Output Capacitance - 400 - pF
f = 1MHz
CRSS Reverse Transfer Capacitance - 120 - pF
Qg(TOT) Total Gate Charge at 20V VGS = 0V to 20V 117 152 nC
Qg(10) Total Gate Charge at 10V VGS = 0V to 10V V =100V - 64 83 nC
DD
Qg(TH) Threshold Gate Charge VGS = 0V to 2V ID = 22A - 5 7 nC
Ig = 1.0mA
Qgs Gate to Source Gate Charge - 9 - nC
Qgd Gate to Drain “Miller” Charge - 24 - nC
Notes:
1: Starting TJ = 25°C, L = 4.2mH, IAS = 11A.
2: Pulse width ≤ 400µs; duty cycle ≤ 2%.
1.2 20
1.0
POWER DISSIPATION MULTIPLIER
15
0.6 10
0.4
5
0.2
0 0
0 25 50 75 100 125 150 175 25 50 75 100 125 150 175
TC , CASE TEMPERATURE (oC) TC, CASE TEMPERATURE ( C) o
2
DUTY CYCLE - DESCENDING ORDER
0.5
1 0.2
0.1
THERMAL IMPEDANCE
0.05
ZθJC, NORMALIZED
0.02
0.01
PDM
0.1
t1
t2
NOTES:
SINGLE PULSE DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
0.01
10-5 10-4 10-3 10-2 10-1 100 101
t, RECTANGULAR PULSE DURATION (s)
300
TC = 25oC
FOR TEMPERATURES
IDM, PEAK CURRENT (A)
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
10
10-5 10-4 10-3 10-2 10-1 100 101
t, PULSE WIDTH (s)
200 100
100
100µs
1ms
10 STARTING TJ = 25oC
STARTING TJ = 150oC
10ms 10
1
OPERATION IN THIS If R = 0
SINGLE PULSE
AREA MAY BE tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
TJ = MAX RATED
LIMITED BY rDS(ON)
TC = 25oC If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
0.1 1
1 10 100 300 0.001 0.01 0.1 1 10
VDS, DRAIN TO SOURCE VOLTAGE (V) tAV, TIME IN AVALANCHE (ms)
Figure 5. Forward Bias Safe Operating Area Figure 6. Unclamped Inductive Switching
Capability
40 40
PULSE DURATION = 80µs
VGS = 10V
DUTY CYCLE = 0.5% MAX
VDD = 15V VGS = 5V
30 30
ID, DRAIN CURRENT (A)
VGS =4.5V
20 20
TJ = -55oC
TJ = 175oC
10 10
PULSE DURATION = 80µs
TJ = 25oC DUTY CYCLE = 0.5% MAX
TC = 25oC
0 0
2 3 4 5 6 0 1 2 3 4 5 6
VGS, GATE TO SOURCE VOLTAGE (V) VDS, DRAIN TO SOURCE VOLTAGE (V)
3.5 1.2
PULSE DURATION = 80µs VGS = VDS, ID = 250µA
3.0 DUTY CYCLE = 0.5% MAX
NORMALIZED DRAIN TO SOURCE
2.5
THRESHOLD VOLTAGE
NORMALIZED GATE
1.0
ON RESISTANCE
2.0
1.5
0.8
1.0
0.5
VGS = 10V, ID = 22A
0 0.6
-80 -40 0 40 80 120 160 200 -80 -40 0 40 80 120 160 200
Figure 9. Normalized Drain To Source On Figure 10. Normalized Gate Threshold Voltage vs
Resistance vs Junction Temperature Junction Temperature
1.3 10000
ID = 250µA VGS = 0V, f = 1MHz
CISS = CGS + CGD
NORMALIZED DRAIN TO SOURCE
1.2
BREAKDOWN VOLTAGE
1000
C, CAPACITANCE (pF)
1.1
0.9
CRSS = CGD
0.8
10
-80 -40 0 40 80 120 160 200
0.1 1 10 100 200
TJ , JUNCTION TEMPERATURE (oC) VDS , DRAIN TO SOURCE VOLTAGE (V)
Figure 11. Normalized Drain To Source Figure 12. Capacitance vs Drain to Source
Breakdown Voltage vs Junction Temperature Voltage
10
VDD = 100V
VGS , GATE TO SOURCE VOLTAGE (V)
4
WAVEFORMS IN
DESCENDING ORDER:
2 ID = 22A
ID = 5A
0
0 10 20 30 40 50 60 70
Qg, GATE CHARGE (nC)
VDS BVDSS
tP
VDS
L
IAS
VARY tP TO OBTAIN VDD
+
REQUIRED PEAK IAS RG
VDD
VGS -
DUT
tP
0V IAS 0
0.01Ω
tAV
Figure 14. Unclamped Energy Test Circuit Figure 15. Unclamped Energy Waveforms
VDS
VDD Qg(TOT)
RL
VDS
VGS = 20V
VGS Qg(10)
+
DUT VGS = 2V
Ig(REF) 0
Qg(TH)
Qgs Qgd
Ig(REF)
0
Figure 16. Gate Charge Test Circuit Figure 17. Gate Charge Waveforms
td(ON) td(OFF)
RL tr tf
VDS
90% 90%
+
VGS
VDD 10% 10%
- 0
DUT 90%
RGS
VGS 50% 50%
PULSE WIDTH
VGS 10%
0
Figure 18. Switching Time Test Circuit Figure 19. Switching Time Waveforms
RθJA (oC/W)
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.
( T JM – T A )
(EQ. 1) 40
P DM = -------------------------------
Z θJA
19.84
R θJA = 26.51 + ------------------------------------- (EQ. 2)
( 0.262 + Area )
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*38),2.5))}
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -8.5 VOFF= -1)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1 VOFF= -8.5)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.1 VOFF= 0.2)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.2 VOFF= -0.1)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/38))** 2.5))
}
}
CTHERM1 th 6 2.8e-3
CTHERM2 6 5 4.6e-3 RTHERM1 CTHERM1
CTHERM3 5 4 5.5e-3
CTHERM4 4 3 9.2e-3
CTHERM5 3 2 1.7e-2
6
CTHERM6 2 tl 4.3e-2
RTHERM1 th 6 5e-4
RTHERM2 6 5 1.5e-3 RTHERM2 CTHERM2
RTHERM3 5 4 2e-2
RTHERM4 4 3 9e-2
RTHERM5 3 2 1.9e-1 5
RTHERM6 2 tl 2.9e-1
RTHERM3 CTHERM3
SABER Thermal Model
IRF640N
template thermal_model th tl 4
thermal_c th, tl
{
ctherm.ctherm1 th 6 = 2.8e-3
RTHERM4 CTHERM4
ctherm.ctherm2 6 5 = 4.6e-3
ctherm.ctherm3 5 4 = 5.5e-3
ctherm.ctherm4 4 3 = 9.2e-3
ctherm.ctherm5 3 2 = 1.7e-2 3
ctherm.ctherm6 2 tl = 4.3e-2
rtherm.rtherm1 th 6 = 5e-4
RTHERM5 CTHERM5
rtherm.rtherm2 6 5 = 1.5e-3
rtherm.rtherm3 5 4 = 2e-2
rtherm.rtherm4 4 3 = 9e-2
rtherm.rtherm5 3 2 = 1.9e-1 2
rtherm.rtherm6 2 tl = 2.9e-1
}
RTHERM6 CTHERM6
tl CASE
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failure to perform when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can be effectiveness.
reasonably expected to result in significant injury to the
user.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Advance Information Formative or This datasheet contains the design specifications for
In Design product development. Specifications may change in
any manner without notice.
No Identification Needed Full Production This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Rev. H4
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