MAJOR PROJECT SYNOPSIS

A project on

“LOW POWER CIRCUITS USING REVERSIBLE

GATES”

Submitted in partial fulfillment of the requirements

for the award of the degree of

Masters of Technology

in

Electronics and Communication Engineering

Submitted by:

MEHAR SHARMA

Enroll No.A50115317001

Under the guidance of

Mr. Neeraj Gupta Ms. Shruti Karkra

Assistant Professor Assistant Professor

ECE department ECE department

Department of Electronics and Communication Engineering

Amity School of Engineering & Technology

AMITY UNIVERSITY GURGAON, HARYANA

January 2019

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 AIM AND OBJECTIVES OF THE PROJECT
Reversible circuits can generate unique output vector from each input vector, and vice versa,
that is, there is a one-to one mapping between the input and output vectors. Reversible logic
is considered as one of the promising practical strategies for power-efficient computing.
Reversible logic also finds application in emerging nanotechnologies such as quantum dot
cellular automata, optical computing etc. Other major applications of reversible logic lies in
quantum computing, as the quantum networks must be built from reversible logical
components. Minimizing quantum cost, delay and the number of garbage outputs is the
primary goal in reversible logic design and synthesis. The garbage outputs (garbage output
refers to the output that is not used as a primary output or as an input to other gate) are the
unutilized outputs in reversible circuits which exist just to maintain reversibility but do not
perform any useful operations. The field of reversible computing now ranges from the
seminal theoretical work to small working devices and circuits. However, the theoretical
work is typically couched in terms of idealized apparatus such as, Turing machines, which
bear little resemblance to modem digital computers. As the technology is advancing we are
building more and more portable devices by integrating more number of devices. Therefore
energy dissipation is becoming key issue to be solved. R. Landauer in the year 1960 has
demonstrated that energy dissipation due to information loss is high when circuits are
constructed using irreversible logic. According to Landauers principle, the loss of one bit of
information lost, will dissipate KT*ln2 (2) joules of energy where, k is the Boltzmann’s
constant and k=1.38x10−23 J/K, T is the absolute temperature in Kelvin [1]. The basic
combinational circuits dissipate heat energy for every bit of information lost during the
operation. This is because according to second law of thermodynamics, information once lost
cannot be recovered by any methods. In 1973, Bennett, showed that in order to avoid kTln2
joules of energy dissipation in a circuit it must be built from reversible circuits [2]. According
to Moore’s law the numbers of transistors will double every 18 months. Thus energy
conservative devices are in need today. Reversible circuits are those circuits that do not lose
information. The most important application of reversible logic lies in quantum computers
[3]. A quantum computer will be viewed as a quantum network composed of quantum logic
gates, with applications in various research areas like Low Power CMOS design, quantum
computing, nanotechnology and DNA computing. Reversible computation in a system can be
performed only when the system comprises of reversible gates. A gate is said to be reversible
if the input vector can be uniquely recovered from the output vector and there is a one-to-one
mapping between its input and output assignments [4-5].The main challenges of designing
reversible circuits are to reduce the number of gates, garbage outputs, constant inputs and
quantum cost.

OBJECTIVES
Design of low power circuits:

• Designing of combinational circuits (multiplexer, decoder, encoder etc)

• Designing of sequential circuits (counters, shift register etc).

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 BACKGROUND STUDY

Reduction of power dissipation remains one of the major goals in the VLSI circuit designing
from many years even though some significant work have been already done in the field of
reversible gates.

Reversible Gates are circuits in which number of outputs is equal to the number of
inputs.And there is a one to one mapping between the vector of inputs and outputs. It helps to
determine the outputs from the inputs as well as helps to uniquely recover the inputs from the
outputs. Avishek Bose et.al [11] presented a design of compact reversible online testable
ripple carry adder. The main property of this design is that one input line of the adder has no
control on the other input line. This design has improvement of 25% on number of gates,
42.30% on quantum cost and 50% on number of constant inputs. In 2016, Umesh Kumar et.al
[7] proposed a paper that describes the performance evaluation of reversible logic gates. In
this paper classical gates and quantum gates are compared on the various parameters. It is
analyzed that power consumption, heat dissipation can be minimized using various reversible
logic gates such as Toffoli, Fredkin and Peres gate. Deeptha A et.al [8] proposed a design of
Reversible 8-bit ALU by cascading 1-bit ALUs. Control unit and the adder unit were the
major units of 1-bit ALUs. Control Output Gate (COG) and Haghparast Navi Gate (HNG)
have been used for control unit and adder unit respectively. The proposed design was
compared with the previous design and has lesser propagation delay.

MojtabaValinataj et.al [9] proposed a design of a new low-cost gate with the quantum cost of
10. This new low-cost gate was used as a parity preserving full adder with the minimum
hardware complexity. Some new low-cost fault-tolerant adders are carry skip, carry look-
ahead and BCD adders which are highly proficient in terms of quantum cost, total logical
calculation and transistor count as compared to the previous designs

A.V.Ananthalakshmi et.al [2] proposed a design of Reversible floating-point square root

using modified non-restoring algorithm. Non-restoring method consumed less number of
logical resources and the remainder was not restored in each step. GST algorithm was used
for this floating-point square root which has reduced the area and power consumption. This
design is efficient in terms of number of reversible gates, constant inputs, garbage outputs
and quantum cost.

A.Kamaraj et.al [1] presented a design of Arithmetic Logic Unit using Novel reversible gates
and it was evaluated in Quantum Cellular Automata. This Arithmetic Logic Unit can be used
for low power applications. This design mitigates quantum cost, garbage outputs. It has
improvement of 50% on constant inputs, 58.3% on gate counts and 62% on number of cells.

Dhoumendra Mandal et.al [2] presented a design of all optical one bit binary comparator
using reversible logic gates. In this design, reversible logic gates based on frequency encoded
data were used for designing one bit comparator. This comparator circuit can be used to
propose all optical Arithmetic Logic Unit.

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 METHODOLOGY
Some important characteristics synthesis of a reversible circuit:

• Use as many outputs of every gate as possible, and thus minimize the garbage outputs.
• Do not create more constant inputs to gates that are absolutely necessary.
• Avoid leading output signals of gates to more than one input, because each such fan
out of two requires adding one copying circuit.
• Use as less number of reversible gates as possible to achieve the goal.

Beside those points, we are also presenting some other few points that lead us to construct the
circuit:

• Selection of appropriate reversible gates according to outputs.

• Appropriate use of constants bits.
• Backward data flow analysis and appropriate positioning of gate according to the
analysis.

PROPOSED FLOWCHART
DESIGNING OF SEQUENTIALCIRCUITS
AND COMBINATIONAL CIRCUITS USING
PROPOSED REVERSIBLE GATES

CALCULATE POWER
DISSIPATION

CALCULATE DELAY

FIGURE OF MERIT

COMPARE THE OUTPUTS

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 TOOLS AND TECHNIQUES TO BE USED

1. HARDWARE CONFIGURATION

i. Processor: 1.3GHz
ii. RAM :128Mb
iii. Free Space Required on Hard Disk :15 Mb

2. SOFTWARE REQUIRED

i. Mentor graphics
ii. Xilinx

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 PROPOSED WORK

1. PROPOSED REVERSIBLE GATES

A. TOFOLLI GATE AND FEYNMAN GATE

TOFOLLI AND FEYNMAN GATE is a 3*3 gate .The inputs (A, B,C) and outputs(P,Q,R). P=A, Q=
A  B ,C=AB  C

A B A

B TOFOLLI FEYNMAN AB

GATE B GATE
C
ABC ABC

Fig1. TOFOLLI AND FEYNMAN GATE

B. TOFOLLI AND PERES GATE

The input vector is I (A, B, C) and the output vector is O (P, Q, R). The outputs are defined
by P=A, Q=A  B, R=AB  (ABC).

A A A

TOFOLLI B PERES
B A B
GATE GATE
C AB C
AB(ABC)

Fig 2. TOFOLLI AND PERES GATE

C. TOFOLLI AND FREDKIN GATE

The input vector is I (A, B, C) and the output vector is O (P, Q, R). The output is defined by
P=A, Q=A′B ᵻ AC and R=AB ᵻ A’(ABC).

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 A
A A

TOFOLLI FREDKIN
B B A’B ᵻ AC
GATE
GATE
C ABC AB ᵻ A’(AB C)

Fig 3. TOFOLLI AND FREDKIN GATE

D. DOUBLE TOFOLLI GATE

The input vector is I (A, B, C) and the output vector is O (P, Q, R). The output is defined by
P = A, Q = B and R=AB (ABC).

A A A

TOFOLLI TOFOLLI
B B
GATE GATE B

C ABC
AB(ABC)

Fig 4. DOUBLE TOFOLLI GATE

E. FEYNMAN GATE AND TOFOLLI GATE

The FEYNMAN GATE AND TOFOLLI GATE is a 3 inputs 3 outputs (x3) reversible gate
having the mapping (A, B, C) to (P, Q, R). P=A, Q=B, R= A⊕B, S = A (A⊕B) ⊕C, where
A, B, C are the inputs and P,Q,R are the outputs respectively.

A A
A FEYNMAN
GATE
A⊕B
TOFOLLI A⊕B
B GATE

C A(A⊕B) ⊕C
A

Fig 5. FEYNMAN GATE AND TOFOLLI GATE

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 F. FEYNMAN GATE AND PERES GATE

The input vector is I (A, B, C) and the output vector is O (P, Q, R). The output is defined by
P = A, Q = A⊕(A⊕B) and R= A(A⊕B) + C

A A A
A A A
FEYNMAN PERES
B A⊕B
GATE GATE
A⊕(A⊕B)
A A

C A(A⊕B) ᵻ C
A

Fig 6 FEYNMAN GATE AND PERES GATE

G. FEYNMAN GATE AND FREDKIN GATE

The input vector is I (A, B, C) and the output vector is O (P, Q, R). The output is defined by
P = A, Q = A⊕(A⊕B) and R= A(A⊕B) + C

A A A
A A
FEYNMAN FREDKIN
B A⊕B A’(A⊕(A⊕B)
GATE GATE
A
C A’(A⊕B)A’C)
A

Fig 7 FEYNMAN GAE AND FREDKIN GATE

H. PERES GATE AND TOFOLLI GATE

The input vector is I (A, B, C) and the output vector is O (P, Q, R). The output is defined by
P = A, Q = A⊕B) and R= A(A⊕C) ⊕AB⊕C

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 A A
A

B PERES TOFOLLI
A⊕B A⊕B
GATE GATE
C
AB⊕C
A(A⊕C) ⊕AB⊕C)

Fig 8 PERES GATE AND TOFOLLI GATE

I. PERES GATE AND FEYNMAN GATE

The input vector is I (A, B, C) and the output vector is O (P, Q, R). The output is defined by
P = A, Q = A⊕ (A⊕B) and R= AB⊕C

A A A

B PERES FEYNMAN
A⊕B
GATE GATE A⊕(A⊕B)

C
AB⊕C

Fig 9 PERES GATE AND FEYNMAN GATE

J. PERES GATE AND FREDKIN GATE

The input vector is I (A, B, C) and the output vector is O (P, Q, R). The output is defined by
P = A, Q = A’(A⊕B)+ A’(AB⊕C) and R= A(A⊕B)+A’(AB⊕C)

A A A

B PERES FREDKIN
A⊕B A’(A⊕B)+A(AB⊕C)
GATE
GATE
C AB⊕C A(A⊕B)A’(AB⊕C)

Fig.10 PERES GATE AND FREDKIN GATE

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 K. FREDKIN GATE AND TOFFOLI GATE

The input vector is I (A, B, C) and the output vector is O (P, Q, R). The output is defined by
P = A, Q = A’B+ AC and R= A(A’B+AC) ⊕(AB⊕A’C)

A A A

FREDKIN TOFOLLI A’B+AC

B A’B+AC
GATE
GATE
C AB+A’C AB+A’C

Fig.11 FREDKIN GATE AND TOFFOLI GATE

L. FREDKIN GATE AND FEYNMAN GATE

The input vector is I (A, B, C) and the output vector is O (P, Q, R). The output is defined by
P = A, Q = A⊕(A’B+AC) and R= AB+A’C

A C A

B FREDKIN A’B+AC FEYNMAN A⊕(A’B+AC)

GATE
GATE
C
AB+A’C

Fig12 FREDKIN GATE AND FEYNMAN GATE

M. FREDKIN GATE AND PERES GATE

The input vector is I (A, B, C) and the output vector is O (P, Q, R). The output is defined by
P = A, Q = A⊕(A’B+AC) and R= A(A’B+AC) ⊕(AB+A’C).

A A A

FREDKIN PERES
B A’B+AC
A⊕(A’B+AC)
GATE
GATE
C AB+A’C A(A’B+AC) ⊕(AB+A’C)

Fig.13 FREDKIN GATE AND PERES GATE

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 FUTURE WORK AND CONCLUSION
As such, there are still many challenges before actually turning reversible logic into a practical
competitive technology. Due to irreversible gates, the power loss is negligible for current logic
technologies using adiabatic design. A major limitation for the today’s CMOS technology is
represented by increased heat dissipation of the silicon chips. Therefore, reversible circuits
present the promise of very low power computation. In addition, reversible logic synthesis has
a close relation with quantum logic synthesis, and the method of reversible logic synthesis can
be used to implement quantum logic synthesis. Thus, the study of reversible logic synthesis
will contribute to the progresses in the related research fields, including design of the ultra-low
power IC and quantum computing.

Future work related to building of the proposed reversible logic by using technologies such as
CMOS, in particular adiabatic CMOS, optical, thermodynamic technology, nanotechnology
and DNA technology is another important aspect. The proposed method will have broad
applications in hardware implementations of many DSP algorithms. The proposed structure is
capable of implementing multipliers using add and shift method, i.e. by taking advantage of
reversible barrel shifter, the efficient multipliers can be designed which could be better than
presently available approaches. An interesting future work could be to develop efficient
reversible counters and barrel shifter circuits and further it could be advantageous to design an
arithmetic and logic unit. Reversible logic contributes to the progresses in the related research
fields, including design of the low power and high speed devices. A promising way to secure
funding for the required technology development would be to join forces with a high priority
problem that can be solved by computers but exceeds the limits of conventional technology.

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REFERENCES

[1] R. Landauer, “Irreversibility and Heat Generation in the Computational Process,” IBM
Journal of Research and Development, 5, pp. 183-191, 1961.
[2] C.H. Bennett, “Logical Reversibility of Computation,IBM J.Research and
Development,” pp.525-532, November 1973.
[3] Vlatko Vedral, Adriano Bareno and Artur Ekert, “QUANTUM Networks for
Elementary Arithmetic Operations,” arXiv:quantph/ 9511018 v1, Nov 1995.
[4] A. Mishchenko, M. Azad Khan, A. Coppola, S.Yanushkevich, “A general
decomposition for reversible logic,” IEEE transactions Proc. RM2001, Starkville, pp: 119-
138, 2001.

[5] Haz Md. Hasan and A.R. Chowdhury, “Design of Reversible Binary Coded decimal
Adder by using Reversible 4 bit Parallel Adder,” IEEE Trans. Very Large Scale Integr.
(VLSI) Jan. 2005.
[6] Abu Sadat Md. Sayem, Masashi Ueda, “Optimization of reversible sequential circuits
Journal of Computing,” Volume 2, Issue 6, June 2010, ISSN 2151-9617.
[7] H.Thapliyal and N. Ranganathan, “Design of reversible sequentialcir-cuits optimizing
quantum cost, delay and garbag outputs,” ACM Journal of Emerging Technologies in
Computing Systems, vol. 6, no.4, Article 14, pp. 14:114:35, Dec. 2010.
[8] J.Smoline and David P.DiVincenzo, “Five two-qubit gates are su cient to implement the
quantum fredkin gate Physics Review A,” vol. 53, no.4, pp. 2855-2856,1996.
[9] Yang G., Song X, Hung WNN, and Marek Perkowski, “Bi-direction Synthesis for
Reversible circuits,” IEEE Computer Society Annual Symposium on VLSI New Frontiers in
VLSI Design, 2007.
[10] D. Maslov and G.W. Dueck, “Reversible cascades with Minimal Garbage,” IEEE
Transactions on CAD, vol.23(11), pp. 1497-1509, November 2004.
[11] Richard P.Feynman, “Quantum mechanical computers Foundations of Physics,”
vol.16, no. 6, pp.507-531,1986.

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