RESUME

Lakshmeesha D R
s/o Revanna
Dandinashivara (V & P)
Turuvekere (Tq)
Tumkur (Dist)
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E-mail: lakkipuni @ gmail.com
Contact: +91-8317368410 ,8549049108
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CAREER OBJECTIVE:
To be part of a successful and innovative team with a challenging job profile that provides ample
opportunity to contribute towards goals and enables continuous learning.
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ACADEMIC PROFILE:

Bachelor of Engineering (B.E.) in Electronics & Communication.

Year of Percentage
Exam Institute Board
Passing %
Govt. engineering college, Vishweshwaraiah
B.E.
(E & C Branch)
K R pet Technology University 2013 63
(VTU)
Vivekananda PU college Karnataka Pre-university
II PUC Turuvekere Boards 2009 59

Govt. junior college Karnataka Secondary

Dandinashivara Educational Examination
SSLC 2007
Board 71.04

PROJECTS

B.E Project: Fast And Reconfigurable Packet Classification Engine In FPGA

Based Firewalls . (Jan 2013- April 2013)
High end network security application demand high speed operation and large rule set support. Packet
classification is the core functionality that demands high throughput in such applications.In data
communication via internet , security is becoming one of the most influential aspects. One way to
support it is by classifying and filtering Ethernt packets within network devices.Packet classification is a
fundamental task for network devices such as routers, firewalls, and intrusion detection systems. In this
project we present architecture of fast and reconfigurable packet classification engine (PCE).This engine
is used in FPGA- based firewall. Our PCE inspects multi- dimensional field of packet header sequentially
based on tree-based algorithm.
 This algorithm simplifies overall system to a lower scale and leads to a more secure system. The
PCE works with an adaptation of single cycle processor architecture in the system. Ethernet packet is
examined with PCE based on Source IP Address, Destination IP Address, Source Port, Destination Port
and Protocol fields of the packet header. These are basic fields to known whether it is a dangerous or
normal packet before inspecting the content. Using implementation of tree based algorithm in the
architecture, firewall rules are rebuilt into 24 bit sub rules which are read as processor instruction in the
inspection process. The inspection process is comparing on one sub rule with input field of header every
clock cycle.

TECHNICAL SKILLS :
 Languages : C.
 Software : matlab, masm, HDL.
 Operating systems : Windows XP, Windows 7.
 CMOS VLSI : Basic stick diagram.

PERSONAL STRENGTHS:

• Self-motivated, Confident, hardworking and dedicated.

• Takes initiative and works independently or as part of group.

• Flexible to any environment.

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WORK EXPERIENCE :

 May 2016-Feb 2018 : Accontant Cum M&E

Magadi road tollgate Bangalore.
 Feb 2016-Apirl 2016 : Airtel technician
Katruguppe Bangalore.
 Jun 2015-Dec 2015 : Teacher
Govt high school Dandinashivara Tumkur.
 Nov 2013-Oct 2014 : Lecture for Maths and Electronics
SSVPU College Turuvekere Tumkur.

EXTRA CURRICULUM ACTIVITIES:

• Participated in singing competitions .

• Had participated in college games competition .
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HOBBIES:

Reading books, listening to music, playing cricket, singing, typing Kannada nudi, chating with
friends.
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PERSONAL PROFILE:
DOB : 30-07-1991.
Nationality : Indian.
Languages Known : English, Kannada, Hindi and Urdu.

DECLARATION:
I declare that the information given above is true to the best of my knowledge.

(LAKSHMEESHA D R)