• 0 (zero, false),
• 1 (one, true),
• x which if seen as output means that Verilog does not know how to compute the value for this output
(either because it is driven by incompatible signals simultaneously or because no imput is driving it),
and
• z high-impedance value.
x and z combine with 0 and 1 in interesting ways. For example, x AND 1 = x, but x AND 0 = 0.
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