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PENGUKUR LAMA WAKTU KERJA ALAT
( HOUR METER )
TUGAS AKHIR
Diajukan Untuk Memenuhi Salah Satu Syarat

Memperoleh Gelar Sarjana Teknik
Program Studi Teknik Elektro
Disusun oleh:
I WAYAN SANTRA
00 5114 006
PROGRAM STUDI TEKNIK ELEKTRO

JURUSAN TEKNIK ELEKTRO
FAKULTAS TEKNIK
UNIVERSITAS SANATA DHARMA
YOGYAKARTA
2007
PENGUKUR LAMA WAKTU KERJA ALAT
TUGAS AKHIR
Diajukan Untuk Memenuhi Salah Satu Syarat

Memperoleh Gelar Sarjana Teknik
Program Studi Teknik Elektro
Disusun oleh:
I WAYAN SANTRA
00 5114 006
PROGRAM STUDI TEKNIK ELEKTRO

JURUSAN TEKNIK ELEKTRO
FAKULTAS TEKNIK
UNIVERSITAS SANATA DHARMA
YOGYAKARTA
2007
i
HOUR METER
Final Project
Presented as Partial Fulfillment of the Requirements
To Obtain the Sarjana Teknik Degree
In Electrical Engineering Study Program
By:
I WAYAN SANTRA
00 5114 006
Electrical Engineering Study Program

Electrical Engineering Department
Faculty of Engineering
Sanata Dharma University
Yogyakarta
2007
ii
MOTTO
KEGAGALAN ADALAH PROSES
UNTUK
MENUJU KEBERHASILAN
vi
Halaman Persembahan
Dengan rasa syukur kepada Tuhan, sekripsi ini

saya persembahkan untuk:
Kedua orang tuaku tercinta
Adik-adikku tersayang
Kekasihku yang aku sayangi
Sahabat – sahabatku yang terbaik
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Judul : Pengukur Lama Waktu Kerja Alat ( Hour Meter )
Nama Mahasiswa : I Wayan Santra
No. Mahasiswa : 005114006
INTISARI
Hour meter adalah alat yang dapat digunakan untuk mengetahui berapa
lama kerja suatu peralatan. Alat ini secara khusus digunakan untuk peralatan
elektronika yang menggunakan catu daya AC ( Alternating Current ) 5 sampai
500 Watt 220 Volt.
Dalam penelitian ini hour meter dikendalikan dengan sebuah

mikrokontroler MC68HC908QY4 buatan Motorola, antarmuka I2C ( Inter
Integrated Circuit ) dengan RTC ( Real Time Clock ) DS1307 sebagai sumber
informasi waktu. Data hasil pengukuran ditampilkan dengan sebuah modul LCD (
Liquid Crystal Display ) M1632 16x2. Hour meter juga dilengkapi dengan 2 buah
tombol push button untuk pengaturan waktu dan memilih menu yang hendak
ditampilkan pada LCD.
Hour meter ini sudah dicoba dan dapat bekerja pada beban resistif 5 Watt,
10 Watt, 25 Watt, 35 Watt, 40 Watt, 50 Watt, 65 Watt, 100 Watt, 150 Watt, 200
Watt, 300, Watt, 400 Watt dan 500 Watt AC 220 Volt, juga pada beban induktif
72 Watt AC 220 Volt. Data yang ditampilkan berupa informasi tanggal peralatan
pertama dan terakhir digunakan, lama penggunaan peralatan terakhir serta total
penggunaan dari awal sampai akhir.
Kata kunci : Hour meter, MC68HC908QY4.
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Title : Hour Meter
Student Name : I Wayan Santra
Student ID : 005114006
ABSTRACT
Hour meter is appliance which can be used to know how long work an
equipments. This appliance peculiarly to be used at electronics equipments using
power supply AC 5 until 500 Watt 220 Volt.
In this research is hour meter controlled with a microcontroller

MC68HC908QY4 made in Motorola, with Inter Integrated Circuit ( I2C ) interface
Real Time Clock ( RTC ) DS1307 as source of time information. Result of
measurement presented with a module Liquid Crystal Display ( LCD ) M1632
16x2. Hour meter also provided by 2 tactile switch for the arrangement of time
and chosen the menu which will be presented at LCD.
This hour meter have been tried and can put hand to the 5 Watt, 10 Watt,
25 Watt, 35 Watt, 40 Watt, 50 Watt, 65 Watt, 100 Watt, 150 Watt, 200 Watt, 300,
Watt, 400 Watt and 500 Watt AC 220 Volt resistive load, also at 72 Watt AC 220
Volt inductive load. Data presented by the form of information date of used last
and first equipments, how long last equipments use and also totalize the use from
early to the last.
Keyword : hour meter, MC68HC908QY4.
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KATA PENGANTAR
Puji dan syukur penulis panjatkan kepada Tuhan Yang Maha Esa atas
anugerah dan rahmatNya yang dilimpahkan kepada penulis, sehingga penulis
dapat menyelesaikan skripsi dengan judul “Hour Meter” guna memperoleh gelar
Sarjana Teknik pada Jurusan Teknik Elektro, Fakultas Teknik, Universitas Sanata
Dharma.
Penulis menyadari bahwa selesainya laporan ini tidak terlepas dari adanya
bantuan dari berbagai pihak baik moril ataupun material, untuk itu penulis
menyampaikan terima kasih yang sebesar – besarnya kepada:
1. Bapak Djoko Untoro Suwarno, S.Si, MT selaku dosen pembimbing
dengan penuh kesabaran membimbing dan mengarahkan penulis sehingga
dapat menyelesaikan tugas akhir ini.
2. Bapak Martanto, ST, MT, Bapak Damar Wijaya, ST, MT dan Ir. Th.
Prima Ari Setiyani, MT selaku dosen penguji yang telah banyak memberi
masukan yang bermanfaat bagi penulis.
3. Seluruh staf dosen teknik elektro yang tidak bisa saya sebutkan satu per
satu yang telah menbimbing penulis selama menempuh perkuliahan.
4. Seluruh staf sekretariat serta laboran teknik elektro yang tidak bisa saya
tulis satu per satu terima kasih atas bantuan dan pelayanannya.
5. Kedua orang tua, I Wayan Samah dan Ni Nyoman Apti, dengan ketabahan
dan kasih sayangnya selalu memberikan dukungan moral serta materi
kepada penulis dalam menempuh pendidikan.
6. Kedua adikku, Nengah Budiani dan Nyoman Suratni, seluruh keluarga
serta saudara – saudaraku tersayang yang telah memberi dukungan
semangat kepada penulis.
7. Sayangku, Gst. Ayu Made Anita Dwi Damayanti dengan ketulusan cinta
dan sayangnya yang selalu sabar memberi dukungan semangat saat penulis
lemah serta ikut berbagi dalam suka maupun duka.
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8. Pak Man Suarka atas dukungan dan semangatnya serta teman – temanku
seperjuangan Kesyug, Dexma, Kawi, Bli Ngurah, Moron, Dode, Putu 82,
Putu Tina, D’Dwix, D’GABENG “selamat melanjutkan perjuangan
kawan!”.
9. Bapak Raymond Weisling, Mas dodo, Mas Ikhwanto, Mas Yusuf dan Mas
Wijaya yang telah memberi masukan-masukan dan ide-ide sehingga
skripsi ini bisa diselesaikan.
10. Rekan – rekan mahasiswa teknik elektro yang tidak bisa disebutkan satu
per satu telah memberikan dukungan selama kuliah dan pengerjaan tugas
akhir ini.
11. Semua pihak yang turut berperan dalam memberi dorongan dan arahan
kepada penulis.
Penulis menyadari bahwa skripsi ini masih banyak kekurangan, karena

terbatasnya pengetahuan dan kemampuan penulis. Oleh karena itu penulis
mengharapkan saran dan kritik pembaca yang bersifat membangun guna
kelengkapan tugas akhir ini.
Yogyakarta, Januari 2007
Penulis
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DAFTAR ISI
HALAMAN JUDUL (INDONESIA) .............................................................. i

HALAMAN JUDUL (INGGRIS).................................................................... ii
LEMBAR PENGESAHAN PEMBIMBING................................................... iii
LEMBAR PENGESAHAN PENGUJI ............................................................ iv
LEMBAR PERNYATAAN KEASLIAN KARYA......................................... v
MOTTO ........................................................................................................... vi
HALAMAN PERSEMBAHAN ...................................................................... vii
INTISARI......................................................................................................... viii
ABSTRACT....................................................................................................... ix
KATA PENGANTAR ..................................................................................... x
DAFTAR ISI.................................................................................................... xii
DAFTAR GAMBAR ....................................................................................... xv
DAFTAR TABEL............................................................................................ xvii
BAB I PENDAHULUAN............................................................................... 1
1.1 Latar Belakang.................................................................................. 1
1.2 Perumusan Masalah .......................................................................... 2
1.3 Batasan Masalah ............................................................................... 3
1.4 Tujuan ............................................................................................... 3
1.5 Manfaat ............................................................................................. 4
1.6 Metodologi Penelitian....................................................................... 4
1.7 Sistematika Penulisan ....................................................................... 5
BAB II DASAR TEORI................................................................................. 6

2.1 Komunikasi IIC ................................................................................ 6
2.2 Hour Meter........................................................................................ 8
2.3 Real Time Clock (RTC) DS1307 ..................................................... 10
xii
2.3.1 Deskripsi Pin............................................................................... 12
2.3.2 Osilator ....................................................................................... 13
2.3.3 Peta Memori RTC....................................................................... 13
2.3.4 Clock dan Kalender .................................................................... 14
2.4 Mikrokontroler Motorola MC68HC908QY4 ................................... 15
2.4.1 Penempatan Pin .......................................................................... 17
2.4.2 Port A.......................................................................................... 18
2.4.2.1 Port A Data Register ............................................................ 18
2.4.2.2 Data Direction Port A (DDRA) ........................................... 19
2.4.2.3 Port A Input Pullup Enable Register (PTAPUE) ................. 20
2.4.3 Port B.......................................................................................... 21
2.4.3.1 Port B Data Register ............................................................ 21
2.4.3.2 Data Direction Register B (DDRB) ..................................... 22
2.4.3.3 Port B Input Pullup Enable Register (PTBPUE) ................. 22
2.4.4 Interupsi Eksternal (IRQ) ........................................................... 23
2.4.4.1 IRQ Status and Control Register (ISCR) ............................. 24
2.5 Shift Register 74HC595 .................................................................... 25
2.5.1 Deskripsi Pin............................................................................... 25
2.6 Modul LCD M1632 .......................................................................... 26
2.6.1 Pin-pin Modul M1632 ................................................................ 27
2.7 Rangkaian Detektor Beban ............................................................... 28
BAB III RANCANGAN PENELITIAN....................................................... 31

3.1 Proses Perancangan .......................................................................... 32
3.1.1 Spesifikasi perancangan ............................................................. 32
3.2 Perancangan Perangkat Keras........................................................... 35
3.2.1 Perancangan Antarmuka Mikrokontroler dengan DS1307......... 36
3.2.2 Rangkaian Mikrokontroler dengan Tombol Push Button........... 37
3.2.3 Perancangan Mikrokontroler dengan LCD M1632 .................... 38
3.2.4 Perancangan Mikrokontroler Dengan Detektor Beban .............. 39
3.3 Perancangan Perangkat Lunak.......................................................... 42
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3.3.1 Perancangan Sistem Secara Umum ............................................ 43
3.3.2 Rutin Inisialisasi ......................................................................... 47
3.3.3 Rutin program utama .................................................................. 48
3.3.4 Subrutin Ambil Data dari RTC................................................... 49
3.3.5 Rutin Kirim Data ke RTC........................................................... 50
3.3.6 Subrutin Kondisi Start dan Stop serial ....................................... 51
3.3.7 Subrutin Penampil ke LCD......................................................... 52
3.3.8 Subrutin IRQ............................................................................... 55
3.3.9 Subrutin Transmitter Data .......................................................... 56
3.3.10 Subrutin Receiver Data ............................................................. 57
BAB IV HASIL DAN PEMBAHASAN ....................................................... 59

4.1 Hasil Perancangan Alat..................................................................... 59
4.1.1 Data Hasil Pengamatan............................................................... 62
BAB V KESIMPULAN DAN SARAN ......................................................... 80

5.1 Kesimpulan ....................................................................................... 80
5.2 Saran ................................................................................................. 80
DAFTAR PUSTAKA ..................................................................................... 82

LAMPIRAN LISTING PROGRAM ............................................................... L1
LAMPIRAN DATASHEET ............................................................................ L2
LAMPIRAN GAMBAR RANGKAIAN ......................................................... L3
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DAFTAR GAMBAR
Gambar 2.1 Sistem Bus I2C ............................................................................. 6
Gambar 2.2 Transfer Data dalam Bus Serial I2C ............................................ 8
Gambar 2.3 Diagram Blok Antarmuka Mikrokontroler dengan DS1307........ 9
Gambar 2.4 Diagram Blok Antarmuka Mikrokontroler dengan LCD............. 10
Gambar 2.5 Konfigurasi Pin DS1307 .............................................................. 12
Gambar 2.6 Diagram Blok MC68HC908QY4 ................................................ 16
Gambar 2.7 Penempatan Pin MC68HC908QY4 ............................................. 17
Gambar 2.8 Port A Data Register .................................................................... 18
Gambar 2.9 Data Direction Register A (DDRA) ............................................ 19
Gambar 2.10 Port A Input Pullup Enable Register (PTAPUE)....................... 20
Gambar 2.11 Port B Data Register (PTB) ...................................................... 21
Gambar 2.12 Data Direction Register B (DDRB) ........................................... 22

Gambar 2.13 Port B Input Pullup Enable Register (PTBPUE) ....................... 23
Gambar 2.14 IRQ Status dan Control Register (INTSCR) ............................. 24
Gambar 2.15 Penempatan pin 74HC595.......................................................... 25
Gambar 2.16 Konfigurasi Kaki M1632 Hitachi............................................... 28
Gambar 2.17 Rangkaian Detektor Beban ........................................................ 29
Gambar 2.18 Rangkaian Pengubah AC ke DC ................................................ 30
Gambar 3.1 Layout Hour Meter Tampak Depan ............................................ 32
Gambar 3.2 Layout Hour Meter Tampak Belakang......................................... 33

Gambar 3.3 Diagram Blok Hour Meter ........................................................... 33
xv
Gambar 3.4 Koneksi Mikrokontroler dengan DS1307 .................................... 37
Gambar 3.5 Rangkaian Mikrokontroler dengan Tombol Push Button ........... 38
Gambar 3.6 Koneksi Mikrokontroler dengan LCD ......................................... 39

Gambar 3.7 Rangkaian Detektor Beban........................................................... 40
Gambar 3.8 Koneksi MikrokontrolerDetektor Beban...................................... 42
Gambar 3.9 Diagram Alir Umum Program...................................................... 43
Gambar 3.10 Diagram Blok Sistem Program .................................................. 44

Gambar 3.11 Layout Mode Pengaturan ........................................................... 45
Gambar 3.12 Layout Mode Mulai Penggunaan ............................................... 45
Gambar 3.13 Layout Mode Akhir Penggunaan................................................ 45
Gambar 3.14 Layout Mode Lama Penggunaan................................................ 46
Gambar 3.15 Layout Mode Total Penggunaan ................................................ 46
Gambar 3.16 Diagram Alir Program Inisialisasi.............................................. 47
Gambar 3.17 Diagram Alir Program Utama .................................................... 48
Gambar 3.18 Diagram Alir Pengambilan Data RTC ....................................... 50
Gambar 3.19 Diagram alir Subrutin Kirim Data ke RTC ................................ 51
Gambar 3. 20 Diagram Alir Start dan Stop Serial ........................................... 52

Gambar 3.21 Diagram Alir Tampilkan Data ke LCD...................................... 53
Gambar 3.22 Diagram Alir Kirim Data Serial ke Shift Register...................... 54
Gambar 3.23 Diagram Alir IRQ ...................................................................... 55
Gambar 3.24 Diagram Alir Transmitter Data .................................................. 56
Gambar 2.25 Diagram Alir Receiver Data....................................................... 57
Gambar 4.1 Tampilan Alat Sebelum Digunakan untuk Pengukuran............... 59

Gambar 4.2 Tampilan Alat Ketika Salah Satu Beban Dinyalakan .................. 60
Gambar 4.3 Hour Meter Tampak Depan ......................................................... 61
Gambar 4.4 Hasil Pengamatan dengan Osiloskop Digital .............................. 64
xvi
DAFTAR TABEL
Tabel 2.1 Peta Alamat Untuk RTC DS1307 dan RAM ................................... 14
Tabel 4.1 Data Lama Waktu Hasil Pengamatan Stop Kontak
Beban Pertama.................................................................................. 63
Tabel 4.2 Data Lama Waktu Hasil Pengamatan Stop Kontak
Beban Kedua .................................................................................... 64
Tabel 4.3 Data Lama Waktu Hasil Pengamatan Beban Resistif 5 W
pada Stop Kontak Pertama.................................................................66
pada Stop Kontak Kedua...................................................................66
Tabel 4.9 Data Lama Waktu Hasil Pengamatan Beban Induktif
Tabel 4.10 Data Lama Waktu Hasil Pengamatan Beban Induktif
Tabel 4.11 Data Tegangan Hasil Pengamatan untuk Beban Resistif
Tabel 4.13 Data Tegangan Hasil Pengamatan untuk Beban Induktif
pada Stop Kontak Pertama dan Kedua..............................................73
Tabel 4.14 Data Tegangan Hasil Pengamatan Beban dengan Kondisi
On dan off otomatis...........................................................................78
xvii
Tabel 4.15 Data Tegangan Hasil Pengamatan Beban dengan Kondisi
On dan Standby..................................................................................78
xviii
BAB I
PENDAHULUAN
1.1 Latar Belakang
Perkembangan teknologi sekarang sangat memegang peranan penting dalam
peradaban manusia. Seiring dengan perkembangan teknologi yang semakin modern,
banyak dijumpai beranekaragam peralatan elektronika yang tersedia di pasaran,
sehingga banyak pekerjaan dapat dilakukan dengan memanfaatkan teknologi
terutama teknologi elektronika. Sekarang penggunaan mesin atau peralatan
elektronika sudah menjadi kebutuhan hampir setiap sudut kehidupan manusia.
Tentunya pemakaian suatu peralatan memerlukan perawatan, karena komponen
penyusun peralatan tersebut pasti memiliki batas waktu pemakaian. Selain itu
pemakaian yang tanpa memperhatikan lama waktu penggunaan secara langsung
akan merugikan pemakai. Menjadi hal yang menarik apabila setiap penggunaan suatu
peralatan dapat diketahui lama waktu penggunaannya. Hal ini bisa menjadi
pertimbangan berapa besar biaya yang akan diperlukan jika telah digunakan dalam
rentang waktu tertentu. Selain dapat mengetahui informasi lama penggunaan untuk
dijadikan pertimbangan biaya operasional, bisa juga dapat mengetahui berapa jam
umur dari peralatan tersebut.
Karena pada suatu mesin atau peralatan elektronik juga memiliki kemampuan
kerja yang dibatasi oleh waktu, menjadi dasar bagi penulis untuk mengangkat ide
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tersebut menjadi topik penelitian hour meter jika digunakan untuk lampu atau
peralatan yang memakai tenaga listrik sebagai catu daya.
1.2 Perumusan Masalah
Karena masih terbatasnya mesin atau peralatan yang menggunakan tenaga
listrik sebagai catu daya memiliki sistem pewaktu (timer) yang secara otomatis
menyala pada saat peralatan tersebut digunakan. Selain itu juga untuk bisa diperoleh
informasi yang jelas tentang lama penggunaan dari suatu peralatan. Penulis mencoba
mengembangkan pewaktu (timer) yang telah ada menjadi sebuah alat ukur waktu
yang memiliki fungsi khusus yaitu hour meter. Sebuah mikrokontroler sebagai
pengendali utama dari alat dengan antarmuka Real Time Clock (RTC) yang dalam
bentuk satu kemasan rangkaian terintergrasi (Integrated Circuit). Selain itu juga
diperlukan rangkaian pendeteksi beban untuk mengetahui peralatan yang akan diukur
telah dinyalakan atau belum. Sementara informasi yang telah diolah akan ditampilkan
pada sebuah layar LCD (Liquid Crystal Display). Yang menjadi pokok permasalahan
dari penelitian ini adalah bagaimana merancang dan menimplementasikan
mikrokontroler motorola MC68HC908QY4 sebagai pengendali utama dengan
antarmuka I2C (Inter-Integrated Circuit) serial DS1307 dan LCD matrik HD44780.
Selain itu mikrokontroler juga terhubung dengan beberapa piranti masukan lain yaitu
dua detektor beban, dan dua buah tombol push button.

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1.3 Batasan Masalah
Dalam penelitian ini penulis akan mencoba merancang suatu alat, yaitu hour
meter dengan batasan-batasan sebagai berikut:
1. Alat dikendalikan oleh sebuah mikrokontroler motorola MC68HC908QY4
dengan antarmuka IC serial RTC DS1307 dan LCD sebagai penampil
informasi data waktu. Alat bisa menyimpan data waktu meskipun catu
daya primer diputus.
2. Alat dapat digunakan untuk lampu atau piranti lain yang memakai catu
daya AC 220 Volt 50 Hz dan dibatasi hanya untuk pemakaian pada dua
peralatan yang berbeda dengan daya 5 VA sampai 500 VA. Nilai cacahan
total mulai dari 000000 sampai 999999 jam.
Data yang dapat ditampilkan berupa;
1. Informasi tanggal, bulan dan tahun mulai alat digunakan.
2. Informasi tanggal, bulan dan tahun digunakan terakhir.
3. Informasi lama hidup total penggunaan hanya berupa jam.
4. Informasi lama pengukuran terakhir berupa jam, menit, dan detik.
1.4 Tujuan
Tujuan dari penelitian ini adalah sebagai berikut;
1. Merancang hour meter yang dikendalikan oleh mikrokontroler motorola
MC68HC908QY4.
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2. Menghasilkan suatu alat berupa hour meter yaitu sebuah alat ukur waktu
kerja sebuah peralatan yang menggunakan daya 5 VA sampai 500 VA
AC 220 Volt.
1.5 Manfaat
Penelitian ini sangat bermanfaat bagi penulis terutama dalam hal pemahaman
lebih jauh tentang pemrograman mikrokontroler dan aplikasinya. Selain itu juga dapat
menambah pemahaman tentang perangkat keras (hardware). Manfaat bagi dunia
pendidikan diharapkan bisa menjadi literatur baru tentang penggunaan
mikrokontroler, pengembangan hour meter dan akan memunculkan ide-ide baru
untuk pengembangan topik ini.
1.6 Metodologi Penelitian
Dalam penelitian ini penulis mulai dengan langkah-langkah untuk
menentukan arah penelitian. Adapun langkah-langkah tersebut adalah;
1. Dengan mencari bahan pendukung baik berupa perangkat keras, perangkat
lunak serta literatur yang dapat mendukung penyelesaian masalah.
2. Mempelajari literatur dan melakukan perencanaan penelitian. Kemudian
dilanjutkan dengan mulai melakukan perancangan.
3. Perakitan perangkat keras dan perangkat lunak, dilanjutkan dengan
pengecekan dan pengamatan alat hasil penelitian.

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1.7 Sistematika Penulisan
Agar pembahasan pokok masalah dalam penulisan laporan tugas akhir ini
tidak menyimpang dari pokok permasalahan, maka ditetapkan sistematika penulisan
sebagai berikut;
BAB I PENDAHULUAN, membahas latar belakang, perumusan masalah,
batasan masalah, tujuan, manfaat, metodologi penelitian serta sistematika penulisan.
BAB II DASAR TEORI, membahas tentang teori yang mendukung dari
komponen yang dipakai dalam hour meter.
BAB III RANCANGAN PENELITIAN, membahas tentang perancangan
perangkat keras dan perangkat lunak.
BAB IV HASIL DAN PEMBAHASAN, membahas perihal hasil dari
perakitan, cara kerja alat serta hasil pengamatan dalam pengujian alat.
BAB V KESIMPULAN DAN SARAN, berisi kesimpulan dan saran.

BAB II
DASAR TEORI
2.1 Komunikasi IIC
Komunikasi IIC adalah suatu konsep komunikasi dua arah antar IC (
Integrated Circuit ) yang dikembangkan oleh Philips Semiconductor, IIC atau biasa
ditulis I2C merupakan singkatan dari Inter Intergrated Circuit . Komunikasi I2C
hanya melibatkan 2 kabel yaitu SDA ( Serial Data Line ) dan SCL ( Serial Clock
Line ). Pada setiap IC yang terhubung dengan I2C memiliki alamat tertentu sehingga
dapat diakses secara software. Gambar 2.1 menunjukkan contoh sistem bus
komunikasi I2C.
Gambar 2.1 Sistem Bus I2C
Terdapat beberapa istilah dasar dalam komunikasi ini yaitu;
1. Transmitter yaitu device yang mengirim data ke dalam bus.
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2. Receiver yaitu device yang menerima data dari bus.
3. Master yaitu device yang mengendalikan clock dan memiliki inisiatif
memulai dan mengakhiri pesan.
4. Slave yaitu device yang dikendalikan atau diakses oleh master.
Salah kelebihan komunikasi I2C adalah dalam suatu sistem I2C bisa terdapat
lebih dari satu master dan tidak akan menyebabkan terjadinya korupsi data. Data
dikirim atau diterima melalui jalur SDA sedangkan clock dikirim atau diterima
melalui jalur SCL. Kondisi-kondisi yang dipakai dalam sebuah komunikasi I2C.
1. Bus not busy, yaitu kondisi yang ditunjukkan dengan kedua jalur data
dan clock dalam keadaan high.
2. Start, yaitu kondisi berubahnya status logika jalur data dari high ke
low, ketika jalur clock berstatus high.
3. Stop, yaitu kondisi berubahnya status logika jalur data dari low ke
high, ketika jalur clock bersatus high.
4. ACK ( Acknowledge ) , yaitu kondisi receiver menarik SDA ke status
low selama 1 sinyal clock.
Terdapat 2 macam data yaitu address byte dan data byte. Data berukuran 8
bit dengan MSB ( Most Significant Bit ) ditransfer lebih dulu. Setelah kondisi start
data akan dianggap valid jika SDA tetap stabil pada 1 clock high dan data harus
berubah pada saat status clock low. Secara umum transfer data pada bus serial
komunikasi I2C digambarkan dalam Timing diagram pada Gambar 2.2

8
Gambar 2.2 Transfer Data dalam Bus Serial I2C
2.2 Hour Meter
Hour meter merupakan salah satu alat penghitung waktu dimana secara
khusus untuk memberikan informasi berapa lama penggunaan suatu peralatan, yang
dapat dijadikan acuan seberapa lama kemampuan peralatan tersebut bisa bekerja dan
juga bisa dimanfaatkan sebagai pengingat untuk pengantian sebuah komponen
penyusun peralatan tersebut. Pada Gambar 2.3 diagram blok hour meter dengan
sebuah mikrokontroler MC68HC908QY4 antarmuka serial RTC (Real Time Clock)
DS1307. Mikrokontroler mengambil data jam, menit, detik dan data kalender dari
RTC DS1307. Komunikasi antara mikronkontroler dengan RTC DS1307
menggunakan sistem komunikasi serial antar IC dengan 2-kabel. Satu kabel untuk
jalur clock yang dibangkitkan oleh mikrokontroler dan satu kabel lagi untuk jalur
data serial dua arah dari mikrokontroler ke RTC dan sebaliknya.

9
Mikrokontroler
MC68HC908QY4
Clock Data
RTC Serial bus Address

interface register
Control Logic
Register jam,
kalender dan
Osilator dan RAM 56x8
pembagi
frekuensi
Gambar 2.3 Diagram Blok Antarmuka Mikrokontroler dengan DS1307
Pada bagian penampil, dalam penelitian ini akan dipakai sebuah LCD
(Liquid Crystal Display) matrik 16x2 dan sebuah IC shift register 74HC595 untuk
menghemat pin input output mikrokontroler. Dapat digambarkan dengan diagram
blok pada gambar 2.4 berikut;

10
Mikrokontroler
MC68HC908QY4
Shift Register
74HC595
LCD 16x2
Gambar 2.4 Diagram Blok Antarmuka Mikrokontroler dengan LCD
Untuk mengurangi penggunaan I/O pada mikrokontroler dipakai sebuah IC
shift register serial in parallel out yang dihubungkan ke jalur data LCD dengan
antarmuka 8 bit.
2.3 Real Time Clock (RTC) DS1307
Bagian ini merupakan sumber jam dan penanggalan digital, alat ini bisa
memberikan informasi detik, menit, jam ,hari, tanggal, bulan, dan tahun. Tanggal
terakhir pada akhir bulan disesuaikan secara otomatis untuk bulan yang lebih kecil
dari 31 hari, termasuk koreksi pada tahun kabisat. DS1307 berkomunikasi dengan
mikrokontroler dengan sistem komunikasi I2C. Data yang dikirim mulai dari bit
11
terbesar ( MSB ). Cara kerja dari DS1307 akan diatur oleh mikrokontroler. DS1307
Serial RTC (Real Time Clock ) merupakan IC clock/kalender dengan 56 byte RAM.
Kemampuan DS1307
1. Real Time Clock detik , menit, jam, tanggal sebulan, bulan, hari
seminggu, dan tahun termasuk tahun kabisat, kebenarannya valid lebih
dari tahun 2100.
2. 56 byte nonvolatile RAM untuk menyimpan data.
3. Antarmuka dengan I2C serial.
4. Dapat memberikan sinyal keluaran gelombang kotak yang terprogram
5. Secara otomatis dapat mendeteksi kegagalan daya dan memilki rangkaian
saklar yang bisa medeteksi kegagalan daya dan secara otomatis
berpindah ke mode baterai backup.
6. Konsumsi arus kurang dari 500nA pada mode baterai backup dengan
osilator tetap aktif.
7. Jangkauan temperatur kerja – 40 derajat celcius sampai + 85 derajat
celcius.
8. Tersedia dalam kemasan 8 pin DIP atau SO.

12
2.3.1 Deskripsi Pin
Gambar 2.5 Konfigurasi Pin DS1307
1. Pin 1 (X1) dan pin 2 (X2) untuk dihubungkan dengan standar kristal kuarsa
32,768 KHz.
2. Pin 3 (VBat) untuk masukan catu daya cadangan (backup) dengan standar
baterai lithium 3 V atau sumber energi lainnya.
3. Pin 4 (GND) ground
4. Pin 5 (SDA) Serial Data Input/Output. SDA merupakan pin input/output
untuk antarmuka IC serial, pin ini memerlukan sebuah resistor pullup.
5. Pin 6 (SCL) Serial Clock Input.
6. Serial Clock Input merupakan clock masukan data input/output untuk
hubungan antarmuka serial dan digunakan untuk mensinkronkan
perpindahan data dalam antarmuka serial.
7. Pin 7 (SWQ/OUT) Square Wave Output Driver. Jika diaktifkan , SQWE bit
diset ‘1’, SQW/OUT pin dapat mengeluarkan salah satu dari empat frekuensi
gelombang kotak (1 Hz, 4 KHz, 8 KHz, 32 KHz). SQW pin memerlukan

13
sebuah resistor pullup untuk dapat mengalirkan data. SQW/OUT dapat
beroperasi dengan mengunakan salah satu dari dua catu daya Vcc atau VBat.
8. Pin 8 (Vcc) Untuk catu daya primer, ketika tegangan ini dioperasikan secara
normal.
2.3.2 Osilator
Sesuai dengan data sheet DS1307 memerlukan sebuah eksternal kristal
32,768 KHz. Rangkaian osilator ini beroperasi tanpa memerlukan tambahan resistor
atau kapasitor eksternal.
2.3.3 Peta Memori RTC
Tabel 2.1 menunjukkan peta alamat register untuk RTC DS1307 dan alamat
RAM. Register RTC berlokasi pada lokasi alamat 00h sampai 07h. RAM berlokasi
pada lokasi alamat 08h sampai 3Fh. Selama akses multibyte, ketika pointer alamat
menunjuk 3Fh, alamat RAM terakhir, maka pointer akan kembali ke lokasi 00h.
14
Tabel 2.1 Peta Alamat untuk RTC DS1307 dan RAM
2.3.4 Clock Dan Kalender
Informasi penanggalan dan waktu diperoleh dengan pembacaan byte
register. Penanggalan dan waktu diseting atau diinisialisasi sesuai dengan penulisan
pada byte register. Isi dari register waktu dan kalender adalah dalam format BCD.
Register hari bertambah pada saat tengah malam. Nilai – nilai yang sesuai dengan
hari dalam seminggu harus ditentukan pemakai contohnya jika 1 sama dengan
minggu, kemudian 2 sama dengan senin dan seterusnya. Masukan waktu dan tanggal
yang tidak sesuai akan mengakibatkan operasi yang tidak diinginkan. Bit ke-7 dari
register 0 adalah bit penghentian clock. Jika bit ini diset ke logika 1, osilator akan
tidak aktif. Jika di clear menjadi 0, osilator diaktifkan.
DS1307 dapat berjalan pada mode 12 jam atau mode 24 jam. Bit ke-6 dari
register jam adalah untuk memilih mode 12 jam atau 24 jam. Jika dalam keadaan
tinggi (high) yang dipilih adalah mode 12 jam. Dalam mode 12 jam, bit ke-5 adalah
15
bit AM/PM dengan logika tinggi menjadi PM. Dalam mode 24 jam, bit ke-5 adalah
bit sepuluh jam kedua.
2.4 Mikrokontroler Motorola MC68HC908QY4
Bagian ini merupakan pengendali utama dari setiap blok, yang terdiri dari
sebuah mikrokontroler MC68HC908QY4. Mikrokontroler menerima informasi telah
terjadi pemakaian alat dari sebuah detektor beban, dimana sensor ini akan
mengirimkan sinyal saat perangkat yang diukur dinyalakan. Kemudian
mikrokontroler mengambil data waktu dan penanggalan dari RTC setelah itu data
ditampilkan pada LCD berupa informasi lama penggunaan serta tanggal,bulan dan
tahun. Mikrokontroler juga terhubung dengan tiga buah tombol push button yang
berfungsi untuk masuk mode, pilih dan reset.
Mikrokontroler MC68HC908QY4 adalah mikrokontroler 8 bit yang
termasuk dalam keluarga motorola M68HC08. MC68HC908QY4 memiliki 4096
byte flash memory, 128 byte Random Access Memory (RAM), 2 saluran, 16 bit
Timer Interface Module (TIM), 4 saluran Analog to Digital Converter (ADC) 8 bit
dan juga memiliki kemampuan Auto Wakeup dari intruksi stop. Secara umum
Mikrokontroler MC68HC908QY4 terdiri atas bagian – bagian yang digambarkan
pada diagram blok seperti pada Gambar 2.6.

16
Gambar 2.6 Diagram Blok MC68HC908QY4
CPU berperan sebagai otak dari mikrokontroler. Bagian ini bertanggung
jawab untuk mengambil dan mengeksekusi instruksi. M68HC08 Central Processor
Unit (CPU) terhubung ke bagian-bagian mikrokontroler. MC68HC908QY4 terdiri
dari 2 buah port input/output, ADC, Random Access Memory (RAM), osilator,
System Integration Modul, Single interrupt Module, Break Module, Power On Reset
17
Module, Keyboard Interrupt Module, Timer Module, Computer Oprational Properly
(COP) dan Monitor ROM.
2.4.1 Penempatan Pin
Gambar 2.7 menunjukan penempatan pin MC68HC908QY4.
Gambar 2.7 Penempatan Pin MC68HC908QY4
Mikrokontroler MC68HC908QY4 diproduksi dalam kemasan 16 pin PDIP
(Plastic Dual In Line) dan 16 pin SO (Small Outline). Sedangkan yang dipakai
dalam penelitian ini adalah dalam kemasan PDIP. Terdiri dari 13 pin input/output
yaitu PTA0-PTA5, PTB0-PTB7 dan PTA2 hanya untuk input, ada beberapa pin juga
memiliki fungsi lebih dari satu, yaitu selain sebagai I/O juga sebagai oslilator, input
18
ADC (Analog to Digital Converter), input KBI (Keyboard Interuppt), timer
TCH0:1. dan 2 pin untuk catu daya (Vdd) dan ground (Vss).
2.4.2 Port A
Port A adalah port 6 bit yang juga keenam pinnya berbagi fungsi dengan
interupsi keyboard (KBI). Setiap pin port A juga memiliki sebuah piranti pullup
resistor yang dikonfigurasikan dengan perangkat lunak, jika pin port A digunakan
sebagai masukan.
2.4.2.1 Port A Data Register
Gambar 2.8 Port A Data Register
Port A Data Register (PTA) seperti Gambar 2.8, berisi sebuah pengunci data
(latch) untuk masing-masing pin port A. Bit Port A (PTA0 - PTA5), merupakan bit
baca/tulis yang dikendalikan dengan perangkat lunak. Arah data dari masing-masing
19
bit diatur oleh bit yang sesuai pada data direction register A. Reset tidak memberi
berpengaruh pada data port A.
Auto Wakeup Latch Data Bit (AWUL), merupakan bit baca yang berisi nilai
dari adanya permintaan auto wakeup interrupt. Sinyal permintaan wakeup
dibangkitkan secara internal.
Port A Keyboard Interrupts (KBI0-KBI5), bit ini untuk memperbolehkan
interupsi keyboard, KBIE0—KBIE5, dalam Keyboard Interrupt Control Enable
Register (KBIER) mengaktifkan pin port A sebagai pin interupsi eksternal.
2.4.2.2 Data Direction Register A (DDRA)
Data direction register A (DDRA) menentukan apakah masing-masing pin
port A adalah sebagai input atau sebagai output. Menulis logika 1 pada bit DDRA
memperbolehkan output buffer dihubungkan dengan pin port A, sedangkan menulis
logika 0 adalah sebaliknya. Gambar 2.9 menunjukkan register DDRA.
Gambar 2.9 Data Direction Register A (DDRA)
Bit Data Direction Register A (DDRA0 - DDRA5), merupakan bit baca/tulis yang
mengendalikan arah data port A. Reset membuat bit DDRA5– DDRA0 menjadi 0.
20
1 = Mengatur port A sebagai output
0 = Mengatur port A sebagai input
2.4.2.3 Port A Input Pullup Enable Register (PTAPUE)
Port A Input Pullup Enable Register (PTAPUE) dikendalikan dengan
perangkat lunak untuk mengatur pullup device pada masing-masing pin port A. Tiap
bit dapat dikonfigurasikan secara individual dan berhubungan dengan arah data pada
DDRA yang dikonfigurasikan sebagai input. Tiap pullup device secara otomatis
diputus ketika bit DDRAx dikonfigurasikan sebagai output. Gambar 2.10
menunjukkan register PTAPUE.
Gambar 2.10 Port A Input Pullup Enable Register (PTAPUE)
OSC2EN, bit untuk mengaktifkan PTA4 sebagai pin OSC2. Merupakan bit
baca/tulis yang mengkonfigurasikan pin OSC2 ketika pilihan osilator dipilih.
1 = pin OSC2 sebagai osilator
0 = pin OSC2 sebagai port I/O

21
Bit Port A Input Pullup Enable (PTAPUE0 - PTAPUE5), bit baca/tulis yang
diatur dengan perangkat lunak untuk mengaktifkan pullup device pada pin port A.
1 = internal pullup diaktifkan
0 = pullup device tidak terhubung pada pin port A
2.4.3 Port B
Port B yang tersedia pada MC68HC908QY4 adalah port 8 bit input/output.
2.4.3.1 Port B Data Register
Port B Data Register (PTB) berisi sebuah data latch untuk masing-masing
dari 8 pin port B. Gambar 2.11 menunjukkan Port B Data Register (PTB)
Gambar 2.11 Port B Data Register (PTB)
Bit Data Port B (PTB0 - PTB7), merupakan bit baca/tulis yang diatur dengan
perangkat lunak. Arah data dari masing-masing bit dikendalikan oleh bit sesuai
dengan bit pada Data Direction Register B. Reset tidak memberi pengaruh pada data
port B.
22
2.4.3.2 Data Direction Register B (DDRB)
Data Direction Register B (DDRB) menentukan apakah setiap pin port B
digunakan sebagai input atau output. Menulis logika 1 pada bit DDRB mengaktifkan
output buffer dihubungkan dengan pin port B, sedangkan menulis logika 0 adalah
sebaliknya. Gambar 2.12 menunjukkan register DDRB
Gambar 2.12 Data Direction Register B (DDRB)
Bit Data Direction Register B (DDRB0 – DDRB7), merupakan bit baca/tulis
yang mengendalikan arah data port B. Reset membuat bit DDRB0 – DDRB7
menjadi nol.
1 = Mengatur port B sebagai output
0 = Mengatur port B sebagai input
2.4.3.3 Port B Input Pullup Enable Register (PTBPUE)
Port B Input Pullup Enable Register (PTBPUE) berisi sebuah perangkat
lunak yang mengatur pullup device untuk masing-masing pin port B. Tiap bit dapat
dikonfigurasikan secara individual dan berhubungan dengan arah data sesuai dengan
bit pada DDRB yang dikonfigurasikan sebagai input. Tiap pullup device secara
23
otomatis diputus ketika bit DDRBx dikonfigurasikan sebagai output. Gambar 2.13
menunjukkan register PTBPUE.
Gambar 2.13 Port B Input Pullup Enable Register (PTBPUE)
Bit Port B Input Pullup Enable (PTBPUE0 – PTBPUE7), bit baca/tulis yang
diprogram secara perangkat lunak untuk mengaktifkan pullup device pada pin port
B.
1 = internal pullup diaktifkan
0 = internal pullup tidak aktif
2.4.4 Interupsi Eksternal (IRQ)
Pin IRQ berbagi fungsi dengan PTA2, PTA2 yang berfungsi sebagai general
input pin dan pin interupsi keyboard. Kemampuan dari modul IRQ adalah terdapat
sebuah pin interupsi ekskternal, memiliki kontrol bit interupsi IRQ, hysterisis buffer,
sensitivitas interupsi yang dapat diprogram, terdapat pilihan internal pullup resistor.
24
2.4.4.1 IRQ Status and Control Register (ISCR)

IRQ Status dan Control Register ( INTSCR ) yang ditunjukkan pada Gambar
2.14, mengendalikan dan mengawasi operasi dari modul IRQ. INTSCR mempunyai
empat fungsi:
1. Menunjukkan status dari flag IRQ.
2. Menghapus interupsi latch IRQ.
3. Menutupi (mask) permintaan interupsi IRQ.
4. Mengendalikan sensitivitas picuan dari pin IRQ.
Gambar 2.14 IRQ Status dan Control Register (INTSCR)
IRQ Flag ( IRQF ) merupakan bit status yang hanya bisa dibaca. IRQF akan
berlogika tinggi pada saat interupsi IRQ menunggu. Logika 1 menandakan adanya
interupsi IRQ yang menunggu dan logika 0 menandakan tidak ada interupsi IRQ
yang menunggu.
Bit Interrupt Request Acknowledge (ACK) dengan menulis logika 1 pada bit
yang hanya bisa ditulis ini akan membuat nol IRQ lacth. ACK selalu dibaca sebagai
logika 0. Kondisi reset akan membuat ACK menjadi nol.
Interrupt Mask ( IMASK ), dengan menulis logika 1 pada bit baca tulis ini
akan membuat interupsi IRQ tidak aktif. Kondisi reset membuat IMASK1 menjadi
nol. Logika 1 akan membuat permintaan interupsi IRQ tidak aktif dan logika 0 akan
membuat permintaan interupsi IRQ aktif.

25
Edge/Level Select ( MODE ), bit baca/tulis ini mengendalikan sensitivitas
picuan dari pin IRQ. Kondisi reset membuat MODE menjadi nol. Logika 1 membuat
permintaan interupsi IRQ pada tepi turun dan tingkat rendah dan logika 0 membuat
permintaan interupsi IRQ hanya pada tepian turun.
2.5 Shift Register 74HC595
Shift register 74HC595 merupakan IC shift register dengan 8 bit masukan
serial dengan 8 bit keluaran secara serial dan parallel. Untuk memasukkan data seri
diperlukan shift clock, dimana untuk 1 bit data diperlukan 1 clock. Sedangkan untuk
mengeluarkan 8 bit data secara parallel diperlukan 1 clock pada pin output enable.
2.5.1 Deskripsi Pin 74HC595
Gambar 2.15 menunjukkan penempatan pin 74HC595
Gambar 2.15 Penempatan Pin 74HC595

26
1. Q0—Q7 merupakan pin untuk mengeluarkan 8 bit data secara parallel.
2. Q7’ untuk mengeluarkan data serial.
3. DS untuk masukan data serial.
4. STCP untuk clock masukan data serial.
5. OE (Output Enable) mengaktifkan keluaran data parallel.
6. SHCP untuk clock masukan data serial.
7. MR (Master Reset) untuk reset pada register.
8. VCC catu daya 5 Volt dan GND untuk ground.
2.6 Modul LCD M1632
Bagian ini terdiri dari sebuah modul LCD Hitachi M1632 yang bisa
menampilkan 2 baris dan 16 kolom karakter sekaligus. LCD akan menampilkan
menu dan informasi hasil pengukuran yang telah diolah oleh mikrokontroler. M1632
merupakan modul LCD HD44780 matrik dengan konfigurasi 16 karakter dan 2 baris
dengan setiap karakternya dibentuk oleh 8 baris pixel dan 5 kolom pixel. Modul ini
dilengkapi dengan mikrokontroler yang didisain khusus untuk mengendalikan LCD.
Mikrokontroler HD44780 buatan Hitachi yang berfungsi sebagai pengendali LCD
ini mempunyai CGROM (Character Generator Read Only Memory), CGRAM
(Character Generator Random Access Memory) dan DDRAM (Display Data
Random Access Memory).

27
2.6.1 Pin –Pin Modul M1632
Untuk keperluan antarmuka dengan komponen elektronika lain, perlu diketahui
fungsi dari setiap kaki yang ada pada modul LCD M1632. Konfigurasi kaki modul
LCD M1632 seperti Gambar 2.16.
1. Pin 1 (Vcc): Kaki ini berhubungan dengan tegangan +5 volt yang merupakan
tegangan untuk sumber daya dari HD44780.
2. Pin 2 (GND): Kaki ini berhubungan dengan tegangan 0 volt (Ground) dari
modul LCD.
3. Pin 3 (VEE/VLCD): Tegangan pengatur kontras LCD, kontras mencapai
nilai maksimum pada saat kondisi kaki ini pada tegangan 0 volt.
4. Pin 4 (RS): Register Select, kaki pemilih register yang akan diakses. Untuk
akses ke Register Data, logika dari kaki ini adalah 1 dan untuk akses ke
Register Perintah, logika dari kaki ini adalah 0.
5. Pin 5 (R/W): Logika 1 pada ini menunjukkan bahwa modul LCD sedang
pada mode pembacaan dan logika 0 menunjukkan bahwa modul LCD sedang
pada mode penulisan.
6. Pin 6 (E): Enable Clock LCD, kaki untuk mengaktifkan clock LCD. Logika 1
pada kaki ini diberikan pada saat penulisan atau pembacaan data.
7. Pin 7-14 (D0-D7): Kedelapan kaki modul LCD ini adalah jalur Data Bus,
dimana data sebanyak 4 bit atau 8 bit saat proses penulisan maupun
pembacaan data.
28
8. Pin 15 (Anoda): Terhubung dengan kabel coklat berfungsi untuk tegangan
positif backlight.
9. Pin 16 (Katoda): tegangan negatif backlight.
Gambar 2.16 Konfigurasi Kaki M1632 Hitachi
2.7 Rangkaian Detektor Beban
Dalam perancangan ini diperlukan dua buah rangkaian untuk mendeteksi
beban yang diukur telah dinyalakan atau tidak. Secara umum pedeteksi beban terdiri
dari 2 unit rangkaian yaitu detektor beban dan rangkaian pengubah AC ke DC.
Gambar 2.17 menunjukkan rangkaian detektor beban. Tegangan pada dioda D1 dan
D2 atau dioda D3 dan D4 diharapkan bisa menjadi tegangan masukan untuk gate
triac. Beberapa parameter triac yang perlu diperhatikan antara lain, IGT (Gate
Trigger Current), VGT ( Gate Trigger Voltage) yang menyebabkan triac menjadi
29
aktif. Dari kedua parameter tersebut dapat dihitung tegangan Vin yang diperlukan
agar triac dapat aktif sebesar:
Vin = (IGT x RGT) + VGT ............................................. (2-1)
D3
D1
T1
TRIAC
220 Vac D2 D4
T2
RGT
AC ke DC
BEBAN
Gambar 2.17 Rangkaian Detektor Beban
Rangkaian pengubah AC (Alternating Current) ke DC (Direct Current)
diperlukan karena untuk sinyal masukan mikrokontroler dari detektor beban yang
dalam bentuk tegangan searah. Keluaran dari pedeteksi beban yang masih berupa
tegangan tinggi diturunkan dengan trafo, kemudian disearahkan, kemudian difilter
agar dapat menjadi tegangan searah. Selain difilter juga terhubung dengan regulator
tegangan LM7805. Rangkaian pengubah tegangan bolak-balik menjadi tegangan
searah ditunjukkan pada gambar 2.18.

30
T1
1
220 12
7805
DETEKTOR BEBAN
4 - + 2 1 2
VIN VOUT Keluaran 5 V
GND
C1
3
C2
3
0
Gambar 2.18 Rangkaian Pengubah AC ke DC

BAB III
RANCANGAN PENELITIAN
Bab ini berisikan tentang bagaimana cara merancang sebuah pewaktu (timer)
yang akan diaplikasikan sebagai hour meter yaitu alat ukur lama penggunaan suatu
peralatan. Dalam perancangan ini hour meter dikhususkan untuk perangkat
elektronika. Alat ini dikendalikan oleh sebuah mikrokontroler motorola
MC68HC908QY4 dengan antarmuka I2C RTC (Real Time Clock) DS1307 sebagai
sumber detik, menit, jam dan kalender. Kemudian data akan ditampilkan dengan
sebuah LCD (Liquid Crystal Display) matrik 16x2. Rangkaian pendeteksi beban
diperlukan untuk mengetahui beban yang diukur telah dinyalakan atau tidak, juga
tombol push button sebagai piranti masukan yaitu untuk mode dan pilih. Selain
perancangan perangkat keras (hardware) juga diperlukan perancangan perangkat
lunak (software) yang berupa bahasa rakitan (assembly) untuk mikrokontroler
motorola MC68HC908QY4.
31
32
3.1 Proses Perancangan
3.1.1 Spesifikasi Perancangan
Spesifikasi dari hour meter yang diharapkan adalah bisa memberikan
informasi lama pemakaian sebuah peralatan elektronika. Informasi yang ditampilkan
pada layar LCD berupa;
1. Informasi tanggal, bulan dan tahun mulai alat digunakan.
2. Informasi tanggal, bulan dan tahun penggunaan terakhir.
3. Informasi lama pengukuran terakhir berupa jam, menit, detik.
4. Informasi lama pengukuran total hanya berupa jam.
Dan beberapa sepesifikasi lain seperti yang sudah dicantumkan pada Bab I. Secara
fisik dirancang bentuk berupa layout dari hour meter seperti Gambar 3.1 dan Gambar
3.2.
LCD 16x2
Switch Tombol
power pengaturan
Gambar 3.1 Layout Hour Meter Tampak Depan

33
Stop
kontak
untuk
beban
Gambar 3.2 Layout Hour Meter Tampak Belakang
Diagram blok dari hour meter dapat ditunjukkan pada Gambar 3.3
Detektor Detektor Tombol Tombol

beban beban mode pilih
Real Time Clock MC68HC908QY4

(RTC)
Shift Register
74HC595
Penampil
LCD
Gambar 3.3 Diagram Blok Hour Meter

34
1. Blok IC Real Time Clock (RTC) DS1307
Bagian ini merupakan sumber jam dan penanggalan digital, alat ini bisa
memberikan informasi detik, menit, jam ,hari, tanggal, bulan, dan tahun. Tanggal
terakhir pada akhir bulan disesuaikan secara otomatis untuk bulan yang lebih kecil
dari 31 hari, termasuk koreksi pada tahun kabisat. DS1307 berkomunikasi dengan
mikrokontroler melalui jalur 2-kabel, diantaranya 1 untuk data dan satu untuk clock.
Data yang dikirim mulai dari bit terbesar (MSB). Cara kerja dari DS1307 akan diatur
oleh mikrokontroler.
2. Blok Mikrokontroler
Bagian ini merupakan pengendali utama dari setiap blok, yang terdiri dari
sebuah mikronkontroler MC68HC908QY4. Mikrokontroler menerima informasi telah
terjadi pemakaian alat dari sebuah sensor arus, dimana sensor ini akan mengirimkan
sinyal saat perangkat yang diukur dinyalakan. Kemudian mikrokontroler mengambil
data waktu dan penanggalan dari RTC setelah itu data ditampilkan pada LCD berupa
informasi lama penggunaan serta tanggal,bulan dan tahun. Mikrokontroler juga
terhubung dengan tiga buah tombol push button yang berfungsi untuk masuk
mode,seting dan reset.
3. Blok Detektor Beban
Bagian ini terdiri dari rangkaian detektor beban, yaitu piranti yang
memberikan informasi ke mikrokontroler bahwa perangkat yang diukur telah

35
dinyalakan atau tidak. Sinyal keluaran dari detektor beban hanya berupa sinyal on-off
4. Tombol Push Button
Dalam perancangan ini terdapat 2 buah tombol push button yang masing –
masing memiliki fungsi berbeda. Fungsi dari masing – masing tombol tersebut
adalah;
a. Tombol mode berfungsi untuk memilih jenis pengaturan dan jenis data
yang akan ditampilkan pada layar LCD.
b. Tombol pilih berfungsi untuk menyesuaikan data yang akan
ditampilkan.
5. Blok Penampil
Bagian ini terdiri dari sebuah modul LCD Hitachi M1632 yang bisa
menampilkan 2 baris dan 16 kolom karakter sekaligus dan sebuah shift register. LCD
akan menampilkan menu dan informasi hasil pengukuran yang telah diolah oleh
mikrokontroler. Data dikirim oleh mikrokontroler secara serial ke shift register
kemudian diteruskan secara paralel ke LCD.
3.2 Perancangan Perangkat Keras
Dalam perancangan ini akan dibangun sebuah system yang berbasiskan
mikrokontroler. Mikrokontroler memerlukan beberapa piranti tambahan supaya dapat

36
bekerja sesuai dengan tujuan penelitian ini. Proses perancangan ini dibagi dalam
beberapa langkah
3.2.1 Perancangan Antarmuka Mikrokontroler dengan DS1307
Real Time Clock DS1307 merupakan perangkat keras yang memberikan
informasi jam dan kalender serta menyediakan memori 56 byte. Untuk bisa bekerja
pin X1 dan X2 DS1307 dihubungkan dengan kristal 32,768 KHz. Baterai 3 Volt
dihubungkan dengan pin Vbat DS1307 untuk catu daya cadangan supaya pada saat
catu daya utama terputus sistem jam, kalender dan data pada memori tidak hilang.
Komunikasi antara mikrokontroler dengan DS1307 melalui 2-kabel yaitu 1 kabel
untuk jalur data dan 1 kabel untuk clock. Mikronkontroler mengirim dan mengambil
data melalui pin PTB0 yang terhubung dengan pin SDA DS1307. Resistor
dihubungkan dengan tegangan VCC digunakan sebagai pullup eksternal pada jalur
SDA,SCL dan SQW. Jika diharapkan arus yang diserap mikrokontroler pada setiap
pin maksimal 0.5 mA pada VCC = 5 V, maka perhitungan Rpullup adalah :
Vcc 5V
R pullup = = = 10000Ω
I 0.5mA
Pada saat pembacaan dan penulisan data DS1307 memerlukan sinyal clock
melalui pin SCL, oleh karena itu mikrokontroler harus menyediakan sinyal clock. Pin
PTB1 mikrokontroler difungsikan untuk mengeluarkan sinyal clock yang diatur
melalui perangkat lunak dan dihubungkan dengan pin SCL DS1307. Koneksi
mikrokontroler dengan DS1307 ditunjukkan pada Gambar 3.4

37
XTAL
VCC
32.768 KHZ
DS1307
1 8
2 X1 VDD 7
3 X2 SQW/OUT 6
4 Vbat SCL 5
GND SDA
DS1307
3V
VCC
VCC 0 0
10K 10K 10K
U1
1 15
16 VDD PTB0 14
VSS PTB1
9
IRQ/TCLK
0
MC68HC908QY 4
Gambar 3.4 Koneksi Mikrokontroler dengan DS1307
Pin IRQ/TCLK mikrokontroler dihubungkan dengan pin SQW/OUT DS1307 yang
diatur secara software untuk mengeluarkan sinyal 1 Hz dan digunakan sebagai
sumber interupsi eksternal.
3.2.2 Rangkaian Mikrokontroler Dengan Tombol Push Button
Dalam perancangan ini terdapat 2 buah tombol push button yang dihubungkan
dengan 2 pin port A mikrokontroler. Tombol pertama dihubungkan dengan pin PTA0
dan ground yang akan difungsikan untuk masuk mode seting dalam proses
pengaturan waktu. Tombol kedua dihubungkan dengan pin PTA1 dan ground
difungsikan untuk pemilihan pengaturan. Dua resistor dihubungkan pada pin PTA0
38
dan PTA1 dengan catu tegangan 5 V berfungsi untuk pullup eksternal. Rangkaian
mikrokontroler dengan tombol push button ditunjukkan pada Gambar 3.5
VCC
10K 10K
SW1
SW2 13
12 PTA0
PTA1
MODE
MC68HC908QY 4
0
Gambar 3.5 Rangkaian Mikrokontroler dengan Tombol Push Button
3.2.3 Perancangan Mikrokontroler Dengan LCD M1632
Sistem penampil yang digunakan dalam perancangan alat ini adalah modul
LCD M1632 dengan menggunakan driver HD47780. LCD ini dapat digunakan untuk
menampilkan 2 baris 16 karakter sekaligus. Data ASCII dikirim secara serial oleh
mikrokontroler melalui pin PTB4 ke shift register 74HC595 kemudian diteruskan ke
LCD secara parallel dengan antarmuka 8 bit data. Pin PTB2 berfungsi untuk clock
data storage dihubungkan dengan pin STcp dan pin PTB3 berfungsi untuk clock data
serial dihubungkan dengan pin SHcp. Pin PTB5 dihubungkan dengan pin E (Enable
Clock LCD) untuk clock pengiriman data. Pin PTB6 langsung dihubungkan dengan
pin RS (Register Select) untuk pemilihan jenis data yang dikirim ke LCD. Pin VEE
untuk mengatur kontras tampilan LCD langsung dihubungkan dengan ground untuk
39
memperoleh tampilan kontras yang maksimal. Karena mikrokontroler tidak dipakai
untuk membaca data dari LCD maka pin R/W LCD langsung dihubungkan ke
ground. Koneksi mikrokontroler dengan LCD ditunjukkan pada Gambar 3.6
VCC
Vcc
GND LCD 16 X 2
VEE
RS
0 E R/W D0 D1 D2 D3 D4 D5 D6 D7
VCC
13 15
11 OE Q0
1 PTB2 10 1
Vdd PTB3 7 12 Q1
PTB4 6 STcp 2
16 PTB5 3 Q2
Vss PTB6 10 3
MR Q3
4
11 Q4
MC68HC908QY 4 SHcp 5
Q5
14 6
DS Q6
7
Q7
0 74HC595
9
Q7'
Gambar 3.6 Koneksi Mikrokontroler dengan LCD
3.2.4 Perancangan Mikrokontroler Dengan Detektor Beban
Detektor beban merupakan rangkaian yang dipakai untuk mendeteksi
peralatan yang akan diukur telah dinyalakan atau tidak dinyalakan. Rangkaian ini
akan memberikan sinyal on-off kepada mikrokontroler seperti fungsi sebuah saklar
on-off biasa tetapi bekerja secara otomatis mengikuti perubahan keadaan beban. Pada
perancangan alat ini terdapat dua rangkaian detektor beban yang diharapkan bila
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beban dinyalakan rangkaian detektor beban akan memberikan sinyal berlogika tinggi
pada mikrokontroler. Keluaran rangkaian detektor beban dihubungkan dengan pin
PTA3 dan PTA4 mikrokontroler. Dengan adanya logika tinggi dari detektor beban
maka mikrokontroler akan memulai proses pencacahan dan pengambilan data dari
RTC. Rangkaian detektor beban ditunjukkan pada Gambar 3.7
D1 D4
1N5408 1N5408
T1
600V 4 A
Q1
220 Vac
D2
1N5408
D3
1N5408
RGT
280
T2
AC ke DC
BEBAN
Gambar 3.7 Rangkaian Detektor Beban
Rangkaian seri 2 buah dioda dipasang bolak-balik selain menjadi jalur arus ke
beban juga menjadi pembatas tegangan gerbang triac. Dari datasheet diketahui
tegangan bias dioda 1N5408 sebesar 1,2 Volt pada saat arus maju 3 Ampere jadi
diharapkan tegangan masukan gerbang triac pada saat beban penuh sama dengan;
Vin = 2 x 1,2 Volt = 2.4 Volt

41
Dari datasheet jika diinginkan tegangan trigger pada gate (VGT) sebesar 1 V
dan arus gate trigger (IGT) sebesar 5 mA, dengan persamaan (2-1) dapat dihitung nilai
RGT yaitu;
Vin − VGT 2 , 4V −1V

RGT = I GT
= 5 mA
= 280Ω
Terminal 2 triac akan menghasilkan tegangan jika beban yang diukur telah
dinyalakan, karena besarnya tegangan sama dengan tegangan sumber sekitar 220 Volt
AC maka sebelum masuk penyearah diturunkan terlebih dahulu dengan menggunakan
trafo. Untuk mengurangi ripple dan menjaga tegangan agar tetap stabil ditambahkan
sebuah kapasitor dan sebuah regulator tegangan LM7805. Rangkaian detektor beban
yang telah dihubungkan dengan mikrokontroler ditunjkkan pada Gambar 3.8

42
D1 D4
1N5408 1N5408
T1
600V 4 A
T2
D2 D3 RGT1
1
1N5408 1N5408 280 1 T1 5
7805
4 - + 2 1 3
4 8 VIN VOUT
500 mA
GND
BEBAN 1 330
3
220 Vac 47uF 47uF
2
LED
0 0 MC68HC908QY4
PTA3
D5 D8
1N5408 1N5408 PTA4
T1
600V 4 A
T2
D6 D7 RGT2 10K 10K
1
1N5408 1N5408 280 1 T1 5
7805
4 - + 2 1 3
4 8 VIN VOUT 0 0
500 mA
GND
BEBAN 2 330
3
47uF 47uF
2
LED
0 0
Gambar 3.8 Koneksi Mikrokontroler Detektor Beban
Sinyal dari kedua detektor beban yang sudah disesuaikan dengan kemanpuan
masukan mikrokontroler akan mendeteksi salah satu beban yang dinyalakan.
3.3 Perancangan Perangkat Lunak
Perancangan perangkat lunak mikrokontroler dimulai dengan proses inisialisasi
yang berisi perintah-perintah inisialisasi RAM juga menghapus isi RAM,
menginisialisasi perangkat keras dan register seperti mengatur fungsi port sebagai
masukan atau keluaran., inisialisasi interupsi timer dan interupsi eksternal, interupsi
keyboard, serta menginisialisasi perangkat keras yang menjadi antarmuka
mikrokontroler antara lain inisialisasi LCD dan RTC. Setelah proses inisialisasi
selesai, mikrokontroler sepenuhnya dikendalikan oleh sebuah rutin program utama

43
yang berfungsi sebagai pengatur dari keseluruhan rutin yang masing-masing rutin
memiliki tugas untuk mengerjakan sesuatu. Selain rutin program utama juga terdapat
rutin interupsi yang bisa dikerjakan secara mendadak oleh mikrokontroler bila
terdapat sinyal interupsi dari interupsi timer, interupsi eksternal dan interupsi
keyboard. Diagram alir umum program ditunjukkan pada Gambar 3.9
Gambar 3.9 Diagram Alir Umum Program
3.3.1 Perancangan Sistem Secara Umum
Perancangan ini untuk mengarahkan program bila terjadi sebuah interupsi,
penekanan tombol dan adanya sinyal dari pedektsi beban akan menyebabkan masuk
ke dalam rutin interupsi. Jika terjadi penekanan tombol reset, rutin intrupsi akan
mengecek interupsi mana yang aktif, kemudian akan mengahapus isi memori RTC.
Jika tombol mode ditekan maka akan masuk ke mode pengaturan waktu (mode1),
mulai penggunaan (mode 2), akhir penggunaan (mode 3), lama penggunaan (mode 4)
44
dan total penggunaan (mode 5). Diagram blok sistem secara umum ditunjukkan pada
Gambar 3.10
Gambar 3.10 Diagram Blok Sistem Program
Berikut beberapa rancangan layout tampilan bila program masuk ke sistem mode;
a. Pengaturan Waktu (mode 1)
Mode pengaturan berfungsi untuk mengatur data waktu pada register RTC ,
penekanan tombol mode pertama akan menampilkan mode pengaturan pada layar
LCD 16 x 2. pada mode ini terdapat alur program untuk pengaturan jam, menit,
tanggal, bulan dan tahun. Layout mode pengaturan ditunjukkan pada Gambar 3.11.
p e n g a t u r a n ?
Gambar 3.11 Layout Mode Pengaturan

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b. Mulai Penggunaan (mode 2)
Mode mulai penggunaan untuk menampilkan data 1 atau data awal pengukuran, data
tersebut berupa tanggal, bulan dan tahun. Layout mode 2 ditunjukkan pada Gambar
3.12. misalnya mulai pengukuran peralatan pertama tanggal 12 April 2006. Mulai
pengukuran peralatan kedua tanggal 10 Maret 2006
m u l a i 1 : 1 2 - 0 4 - 0 6
m u l a i 2 : 1 0 - 0 3 - 0 6
Gambar 3.12 Layout Mode Mulai Menggunaan
c. Akhir Penggunaan (mode 3)
Mode akhir penggunaan untuk menampilkan data 2 atau data akhir pengukuran, data
tersebut berupa tanggal, bulan dan tahun. Layout mode 2 ditunjukkan pada gambar
3.13. Misalnya akhir pengukuran peralatan pertama tanggal 13 April 2006. Akhir
pengukuran peralatan kedua tanggal 10 Maret 2006.
a k h i r 1 : 1 3 - 0 4 - 0 6
a k h i r 2 : 1 0 - 0 3 - 0 6
Gambar 3.13 Layout Mode Akhir Penggunaan

46
d. Lama Penggunaan (mode 4)
Mode lama penggunaan untuk menampilkan data 3 atau data lama pengukuran, data
tersebut berupa jam, menit dan detik. Layout mode 3 ditunjukkan pada gambar 3.14.
Misalnya lama pengukuran peralatan pertama 1 jam, 30 menit, 11 detik.
l a m a 1
0 0 0 0 0 1 : 3 0 : 1 1
l a m a 2
0 0 0 0 0 1 : 0 5 : 0 2
Gambar 3.14 Layout Mode Lama Penggunaan
e. Total Penggunaan (mode 5)
Mode total penggunaan untuk menampilkan data 4 atau data total pengukuran dari
awal sampai akhir sebelum direset, data tersebut hanya berupa jam, data maksimal
sampai 999999 jam . Layout mode 5 ditunjukkan pada gambar 3.15. Misalnya total
penggunaan pertama adalah 1 jam dan total penggunaan peralatan kedua adalah 103
jam.
t o t a l 1 : 0 0 0 0 0 1
t o t a l 2 : 0 0 0 1 0 3
Gambar 3.15 Layout Mode Total Penggunaan

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3.3.2 Rutin Inisialisasi
Secara umum program pada mikrokontroler berisi subrutin-subrutin yang
mempunyai tugas tertentu. Subrutin tersebut digabung menjadi satu kesatuan
membentuk suatu rangkaian program yang diharapkan bisa berjalan sesuai dengan
tujuan. Sebelum program utama terdapat sebuah rutin program untuk inisialisasi
perangkat keras mikrokontroler beserta antarmukanya. Gambar 3.16 menunjukkan
diagram alir program inisialisasi.
Gambar 3.16 Diagram Alir Program Inisialisasi

48
Rutin inisialisasi dimulai dari reset stack pointer, menghapus isi register,
menonaktifkan LVI dan COP timer dan menghapus isi RAM. Kemudian dilanjutkan
dengan inisialisasi I/O, RTC dan LCD. Setelah itu diakhiri dengan mengaktifkan
semua interupsi yang dipakai.
3.3.3 Rutin Program Utama
Gambar 3.17 Diagram Alir Program Utama

49
Rutin program utama dimulai dari pembacaan memori RTC, data yang
disimpan apakah sudah maksimal, jika belum maka ke proses pengambilan data
waktu, jika data sudah maksimal akan ditampilkan pilihan reset pada LCD, pada reset
semua data pada RAM RTC akan terhapus. Proses selanjutnya adalah pengecekan
beban apakah ada beban yang dinyalakan atau tidak, pada saat tidak ada beban yang
menyala maka program akan menampilkan jam digital. Secara umum rutin program
utama ditunjukkan dengan diagram alir Gambar 3.17. Selain rutin utama juga terdapat
beberapa subrutin program yang memiliki peranan penting dalam program
mikrokontroler ini.
3.3.4 Subrutin Ambil Data dari RTC
Rutin program ini berperan saat mikrokontroler mengambil data dari RTC,
diawali dengan pengambilan alamat, kemudian memulai komunikasi dengan
mengirimkan kondisi sinyal start serial, hal ini dilakukan setiap mulai berkomunikasi
dengan RTC dan selalu diakhiri dengan kondisi stop serial. Ini merupakan kondisi
yang dipakai dalam komunikasi I2C. Subrutin ambil data dari RTC ditunjukkan
dengan diagram alir Gambar 3.18

50
Gambar 3.18 Diagram Alir Pengambilan Data RTC
3.3.5 Rutin Kirim Data ke RTC
Subrutin kirim data berisi perintah-perintah untuk mengirimkan data dari
mikrokontroler ke RTC. Seperti pada pengambilan data pada saat pengiriman data
51
juga diawali dengan kondisi start serial dan diakhiri dengan stop serial. Subrutin
kirim data ditunjukkan pada diagram alir Gambar 3.19.
Gambar 3.19 Diagram Alir Subrutin Kirim Data ke RTC
3.3.6 Subrutin Kondisi Start dan Stop Serial.
Subrutin ini merupakan bagian penting dari komunikasi mikrokontroler
dengan RTC dan selalu dipakai setiap berkomunikasi dengan RTC. Subrutin start dan
stop serial ditunjukkan dengan diagram alir pada Gambar 3.20.

52
Gambar 3.20 Diagram Alir Start dan Stop Serial
3.3.7 Subrutin Penampil ke LCD
Subrutin ini berisi perintah-perintah untuk menampilkan data ke layar LCD.
Data dikirim secara serial dari mikrokontroler ke shift register kemudian dikeluarkan
secara paralel ke modul LCD. Data di simpan pada Accumulator kemudian dengan
memberi logika 1 pada RS yang berarti pengiriman karakter, clock LCD juga
diberikan logika 1 untuk mengirim data. Diagram alirnya ditunjukkan dengan
Gambar 3.21.
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Gambar 3.21 Diagram Alir Tampilkan Data ke LCD
Pada proses menampilkan data ke LCD terdapat sebuah subrutin untuk
memasukkan data serial menuju shift register kemudian data dikirim paralel ke modul
LCD. Mikrokontroler mengirim 8 bit data secara serial menuju IC shift register
74HC595 jika data yang digeser sudah 8 bit kemudian dengan memberi sebuah sinyal
clock maka data akan dikirim secara serentak ke modul LCD. Proses tersebut dapat
ditunjukkan dengan diagram alir seperti pada Gambar 3.22.

54
Gambar 3.22 Diagram Alir Kirim Data Serial ke Shift Register

55
3.3.8 Subrutin IRQ
Dalam subrutin IRQ jika salah satu beban dinyalakan program akan masuk ke
dalam rutin cacahan waktu. Dengan adanya sinyal 1 Hz dari RTC maka terjadi
interupsi ekternal setiap 1 detik. Hal ini mengakibatkan bertambahnya counter detik
setiap terjadi interupsi. Kemudian detik akan di-nol-kan dan menaikkan counter
menit jika detik sudah sampai 60. Secara lengkap proses di dalam rutin IRQ dapat
ditunjukkan dengan diagram alir pada Gambar 3.23
Gambar 3.23 Diagram Alir IRQ

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3.3.9 Subrutin Transmitter Data
Gambar 3.24 Diagram Alir Transmitter Data
Subrutin transmitter data merupakan bagian program untuk mengirim data
dari mikrokontroler ke RTC dengan komunikasi I2C. Diagram alir program

57
transmitter data ditunjukkan dengan Gambar 3.24. subrutin ini berisi proses
pengiriman data serial ke RTC.
3.3.10 Subrutin Receiver Data
Gambar 2.25 Diagram Alir Receiver Data

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Subrutin program receiver data dipakai dalam program pembacaan data RTC
oleh mikrokontroler. Data diterima oleh mikrokontroler secara serial dengan
pembacaan carry kemudian accumulator termasuk carry diproses rotate left. Diagram
alir receiver data ditunjukkan dengan Gambar 2.25.

BAB IV
HASIL DAN PEMBAHASAN
Bab ini menguraikan hasil dan pembahasan perangkat keras. Dari
perakitan perangkat keras dan perangkat lunak dihasilkan alat yang bisa
menampilkan data hasil pengukuran lama suatu perangkat elektronika bekerja.
4.1 Hasil Perancangan Alat
Pada saat alat dinyalakan tanpa terhubung dengan perangkat elektronika
yang akan diukur, alat menampilkan jam digital pada baris pertama LCD, tanggal,
bulan dan tahun pada baris kedua LCD. Jam, menit, detik, tanggal, bulan beserta
tahun dapat disesuaikan dengan masuk ke menu pengaturan. Tampilan alat pada
saat belum terhubung dengan beban ditunjukkan pada Gambar 4.1.
Gambar 4.1 Tampilan Alat Sebelum Digunakan untuk Pengukuran
Ketika beban dinyalakan LCD menampilkan digit cacahan lama beban
yang diukur tersebut telah dinyalakan seperti yang ditunjukkan oleh gambar 4.2,
ini merupakan tujuan utama alat yang dirancang. Setelah selesai melakukan
59
60
pengukuran secara otomatis data hasil pengukuran tersimpan pada memori dan
tidak akan hilang kecuali direset atau baterai backup RTC dilepaskan. Data hasil
pengukuran dapat dilihat kembali melalui penekanan tombol yang tersedia pada
sisi depan alat.
Gambar 4.2 Tampilan Alat Ketika Salah Satu Beban Dinyalakan
Dua buah tombol berfungsi untuk menampilkan menu dan memilih menu
yang hendak ditampilkan sesuai dengan spesifikasi perancangan selain itu juga
terdapat beberapa menu tambahan yaitu menu pengaturan jam, menit, detik,
tanggal, bulan dan tahun.
Gambar 4.3 menunjukkan hour meter yang sudah selesai dirakit, gambar
diambil dari sisi depan alat, dari gambar dapat dilihat pada sisi depan alat terdapat
satu buah switch power, dua buah tombol dan sebuah LCD.
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Tombol
menu
Tombol
select
Switch
power
Gambar 4.3 Hour Meter Tampak Depan
Setelah alat ukur hour meter selesai dirakit sesuai dengan perancangan
perangkat keras dan perangkat lunak yang ada pada bagian bab rancangan
penelitian, dilakukan pengujian untuk mengetahui kemampuan kerja alat. Dari
hasil pengujian dengan menggunakan beban berupa lampu pijar mulai dari 5 Watt
220 Volt sampai dengan lima buah lampu pijar 100 Watt 220 Volt, setelah beban
dinyalakan alat menampilkan hasil cacahan beban yang diukur. Digit cacahan
yang ditampilkan yaitu detik, menit dan jam. Digit detik dan menit yang
ditampilkan mulai dari 00 sampai 59 sedangkan digit jam yang ditampilkan
dengan enam digit dari 000000 sampai 999999. Sinyal 1 Hz yang dikeluarkan
oleh RTC DS1307 digunakan untuk membangkitkan interupsi eksternal
mikrokontroler, sehingga didapatkan sinyal interupsi setiap 1 detik.

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4.1.1 Data Hasil Pengamatan
Tabel 4.1 dan tabel 4.2 menunjukkan data hasil pengamatan alat dengan
perbandingan stopwatch hand phone Nokia 2100 dan lampu pijar 100W 220V
digunakan sebagai beban. Tabel 4.1 berisi data hasil pengamatan alat pada stop
kontak beban pertama, sedangkan Tabel 4.2 berisi data hasil pengamatan alat pada
stop kontak kedua. Pengamatan dilakukan dengan nilai awal alat maupun
stopwatch mulai dari 00:00:00. Kolom lama waktu alat berisi data lama
penggunaan alat terakhir, data ini mulai dari nol lagi setelah kondisi beban tidak
menyala, data yang disimpan berupa jam, menit dan detik. Kolom total waktu alat
menunjukkan total penggunaan beban yang sama dari penggunaan pertama
sampai terakhir, data ini merupakan hasil akumulasi dari data penggunaan alat
pertama sampai terakhir, hasil penjumlahan yang ditampilkan hanya dalam bentuk
satuan jam. Data ini mulai dari nol lagi setelah masuk pada kondisi reset. Kolom
lama waktu HP berisi data hasil pengamatan dengan menggunakan stopwacth
hand phone yaitu dengan menekan tombol start pada waktu beban dinyalakan dan
menekan tombol stop pada waktu beban dipadamkan. Hasil pengukuran dengan
hand phone untuk membandingkan ketelitian alat, data dibandingkan dengan data
penggunaan alat terakhir pada kolom lama waktu alat. Kolom selisih waktu alat
dengan HP berisi data selisih antara lama pengukuran alat dengan lama
pengukuran dengan hand phone.

63
Tabel 4.1 Data Lama Waktu Hasil Pengamatan Stop Kontak Beban Pertama
No. Lama waktu alat Total Lama waktu HP Selisih waktu alat
(Jam:menit:detik) waktu alat (Jam:menit:detik) dengan HP
(Jam) (Jam:menit:detik)
1. 00:14:08 000000 00:14:08 00:00:00
2. 08:21:05 000008 08:21:05 00:00:00
3. 01:42:30 000010 01:42:29 00:00:01
4. 03:33:29 000013 03:33:28 00:00:01
5. 02:46:18 000016 02:46:19 00:00:01
6. 04:43:05 000021 04:43:05 00:00:00
7. 09:28:58 000030 09:28:57 00:00:01
8. 03:34:26 000034 03:34:26 00:00:00
9. 00:54:04 000035 00:54:04 00:00:00
10. 01:20:09 000036 01:20:09 00:00:00
11. 03:11:45 000039 03:11:45 00:00:00
12. 06:40:21 000046 06:40:21 00:00:00
13. 02:13:28 000048 02:13:27 00:00:00
14. 01:49:03 000050 01:49:03 00:00:00
15. 09:34:52 000060 09:34:52 00:00:00
16. 07:34:29 000067 07:34:28 00:00:01
17. 03:15:07 000070 03:15:07 00:00:00
18. 05:44:19 000076 05:44:19 00:00:00
19. 08:37:53 000085 08:37:53 00:00:00
20. 04:50:31 000090 04:50:31 00:00:00
21. 07:12:02 000097 07:12:02 00:00:00
22. 01:59:37 000099 01:59:38 00:00:01
23. 03:32:16 000102 03:32:16 00:00:00
24. 08:47:10 000111 08:47:10 00:00:00
25. 06:22:32 000117 06:22:32 00:00:00
64
Tabel 4.2 Data Lama Waktu Hasil Pengamatan Stop Kontak Beban Kedua
No. Lama waktu alat Total Lama waktu HP Selisih waktu alat
(Jam:menit:detik) waktu alat (Jam:menit:detik) dengan HP
(Jam) (Jam:menit:detik)
1. 01:22:18 000001 01:22:19 00:00:01
2. 03:13:26 000004 03:13:26 00:00:00
3. 02:10:43 000006 02:10:43 00:00:00
4. 01:49:35 000008 01:49:35 00:00:00
5. 04:37:53 000013 04:37:53 00:00:00
6. 03:24:02 000016 03:24:02 00:00:00
7. 05:40:17 000022 05:40:16 00:00:01
8. 07:56:11 000030 07:56:11 00:00:00
9. 02:41:08 000032 02:41:08 00:00:00
10. 00:55:39 000033 00:55:39 00:00:00
11. 06:31:50 000040 06:31:50 00:00:00
12. 03:25:54 000043 03:25:53 00:00:01
13. 01:18:07 000045 01:18:07 00:00:00
14. 07:23:45 000052 07:23:44 00:00:01
15. 02:56:03 000055 02:56:03 00:00:00
16. 08:13:41 000063 08:13:41 00:00:00
17. 04:20:36 000067 04:20:35 00:00:01
18. 09:49:15 000077 09:49:15 00:00:00
19. 02:31:48 000080 02:31:48 00:00:00
20. 06:57:33 000087 06:57:33 00:00:00
21. 08:14:51 000095 08:14:51 00:00:00
22. 03:25:27 000098 03:25:27 00:00:00
23. 07:43:10 000106 07:43:11 00:00:01
24. 01:28:01 000108 01:28:00 00:00:01
25. 05:51:44 000113 05:51:44 00:00:00
Dari data hasil pengamatan beban pertama dan kedua terdapat beberapa
data yang meiliki selisih antara data dari alat dengan data dari stopwacth HP.
Kolom lama waktu alat menunjukkan hasil pengukuran waktu dengan hour meter
data yang ditampilkan yaitu jam, menit, detik Hal ini terjadi karena;
1. Saat pengambilan data penekanan tombol stop pada HP tidak
bersamaan dengan penekanan saklar beban pada alat. Padahal jika

65
diamati sebelum penekanan tombol stop dan saklar beban beban
data antara alat dengan stopwatch HP terlihat sama.
2. Waktu beban dinyalakan atau waktu penekanan saklar on beban
tidak bersamaan dengan penekanan tombol start pada stopwacth.
Jadi perbedaan data antara alat dengan stopwacth dipengaruhi oleh
kurangnya ketelitian dalam pengambilan data.
Pengamatan selanjutnya menggunakan osiloskop digital sebagai acuan dan
digunakan beban resistif untuk pengambilan data, beban resistif yang dipakai
berupa berupa lampu pijar 5 Watt, 100 Watt dan 500 Watt. Beban 500 Watt
dipakai 5 buah lampu pijar 100 Watt. Data hasil pengamatan beban resistif
ditunjukkan pada Tabel 4.3 sampai Tabel 4.8. Pengambilan data dilakukan dengan
melihat hasil yang ditampilkan oleh alat dan sebagai acuan juga dengan melihat
data yang ditampilkan oleh osiloskop digital. Data dari alat dicantumkan pada
kolom “Hasil pengukuran alat ( jam:menit:detik )”, data yang ditampilkan pada
alat berupa informasi waktu lama pengunaan beban dalam bentuk 5 digit dengan
satuan jam, 2 digit dengan satuan menit dan 2 digit dengan satuan detik. Data
yang sama juga ditampilkan osiloskop digital dan dicantumkan pada kolom “Hasil
pengukuran osiloskop (s)”, data pada osiloskop digital hanya dalam satuan detik.
Bentuk sinyal on – off beban resistif yang ditampilkan osiloskop digital
ditunjukkan pada Gambar 4.4

66
Tabel 4.3 Data Lama Waktu Hasil Pengamatan Beban Resistif 5 W pada
Stop Kontak Pertama
No. Hasil Hasil
pengukuran alat pengukuran
(jam:menit:detik) osiloskop (s)
1. 000000:01:20 80,0
2. 000000:00:52 52,8
3. 000000:01:22 82,4
4. 000000:01:13 73,2
5. 000000:01:28 88,0
6. 000000:01:08 68,6
7. 000000:01:37 97,8
8. 000000:02:21 141,1
9. 000000:01:25 85,4
10. 000000:01:05 65,8
Stop Kontak Kedua
No. Hasil Hasil

1. 000000:00:42 42,4
2. 000000:01:02 62,0
3. 000000:01:10 70,1
4. 000000:01:00 60,0
5. 000000:00:56 56,8
6. 000000:00:47 47,2
7. 000000:01:14 74,0
8. 000000:01:26 86,0
9. 000000:01:13 73,2
10. 000000:01:24 84,0
67
Stop Kontak Pertama
No. Hasil Hasil

1. 000000:00:16 16,4
2. 000000:01:11 71,1
3. 000000:00:40 39,9
4. 000000:00:59 58,8
5. 000000:01:09 69,2
6. 000000:01:06 66,4
7. 000000:00:12 12,0
8. 000000:00:25 25,1
9. 000000:00:21 21,0
10. 000000:01:26 86,0
Stop Kontak Kedua
No. Hasil Hasil

1. 000000:00:36 36,4
2. 000000:00:58 58,4
3. 000000:00:45 45,2
4. 000000:01:24 84,0
5. 000000:01:32 92,1
6. 000000:01:20 80,4
7. 000000:01:00 60,0
8. 000000:00:44 44,4
9. 000000:01:15 75,2
10. 000000:01:09 69,4
68
Stop Kontak Pertama
No. Hasil Hasil

1. 000000:00:44 44,0
2. 000000:01:05 65,2
3. 000000:01:10 70,4
4. 000000:01:35 95,3
5. 000000:00:50 50,8
6. 000000:02:05 125,4
7. 000000:02:27 147,3
8. 000000:01:18 78,0
9. 000000:01:09 69,1
10. 000000:00:54 54,0
Stop Kontak Kedua
No. Hasil Hasil

1. 000000:00:47 47,2
2. 000000:00:58 58,0
3. 000000:01:12 72,8
4. 000000:01:23 83,2
5. 000000:00:44 44,8
6. 000000:01:28 88,8
7. 000000:00:40 40,0
8. 000000:00:59 59,2
9. 000000:01:15 75,4
10. 000000:00:40 40,0
69
Gambar 4.4 Bentuk Sinyal dari Beban Resistif
Selain menggunakan beban resistif pengamatan juga menggunakan beban
induktif yaitu berupa kipas angin 72W 220V 50Hz, data hasil pengamatan beban
induktif pada stop kontak pertama ditunjukkan dengan Tabel 4.3 dan data hasil
pengamatan beban induktif pada stop kontak kedua ditunjukkan dengan Tabel 4.4.
Data hasil pengamatan Tabel 4.3 dan Tabel 4.4 menggunakan beban induktif yang
sama yaitu kipas angin 72W 220V 50Hz. Pengamatan dilakukan dengan melihat
data yang ditampilkan alat dan data yang ditampilkan osiloskop digital. Kolom
hasil pengukuran alat berisi data yang ditampilkan alat berupa informasi lama
penggunaan dengan satuan jam, menit dan detik. Sedangkan kolom pengukuran
70
osiloskop berisi data pengamatan dengan osiloskop digital dengan satuan second
(s).
Tabel 4.9 Data Lama Waktu Hasil Pengamatan Beban Induktif pada
Stop Kontak Pertama
No. Hasil Hasil

1. 000000:00:42 42
2. 000000:01:24 84
3. 000000:01:32 92
4. 000000:01:07 67,8
5. 000000:02:06 126,2
6. 000000:03:03 183,1
7. 000000:01:33 93,1
8. 000000:01:40 100,5
9. 000000:01:58 118,9
10. 000000:01:03 62,9
Tabel 4.10 Data Lama Waktu Hasil Pengamatan Beban Induktif pada
Stop Kontak Kedua
No. Hasil Hasil

1. 000000:01:21 81,2
2. 000000:01:07 67,2
3. 000000:00:26 26
4. 000000:01:17 77
5. 000000:00:46 46
6. 000000:02:08 128,4
7. 000000:01:19 79,8
8. 000000:02:51 171,2
9. 000000:01:27 87,9
10. 000000:01:35 95,4
71
Pengamatan dengan menggunakan osiloskop digital waktu yang dapat
dilakukan maksimal 3 menit, maka pengambilan data dengan osiloskop digital
tidak bisa dilakukan untuk sebuah pengamatan dalam satuan jam. Terdapat
beberapa selisih data hasil pengamatan antara alat dengan osiloskop hal ini karena
pada alat tidak bisa menampilkan data yang lebih cepat dari satuan detik. Bentuk
sinyal dari beban induktif yang diamati dengan osiloskop digital dapat
ditunjukkan dengan Gambar 4.5
Gambar 4.5 Bentuk Sinyal dari Beban Induktif
Pengamatan berikutnya yaitu dengan mengambil data tegangan dari
pendeteksi beban, data yang diamati yaitu tegangan seri 2 dioda (Vdioda), tegangan
resistor pada kaki gate triac (VRGT) dan tegangan kaki gate triac (VGT). Data hasil
72
pengamatan dengan beban resistif dicantumkan pada Tabel 4.11 untuk stop kontak
beban pertama dan Tabel 4.12 untuk stop kontak beban kedua. Untuk beban
induktif data hasil pengamatan dicantumkan pada Tabel 4.13, beban induktif yang
dipakai berupa kipas angin AC 72 Watt 220 Volt.
Tabel 4.11 Data Tegangan Hasil Pengamatan untuk Beban Resistif pada Stop
Kontak Pertama
No. Beban resistif Vdioda VRGT2 VGT1

(Watt) (Volt) (Volt) (Volt)
1. 5 1,52 0,78 0,72
2. 10 1,50 0.77 0,72
3. 25 1,56 0,79 0,74
4. 35 1,56 0,79 0,73
5. 40 1,61 0,79 0,73
6. 50 1,64 0,85 0,73
7. 65 1,66 0,87 0,73
8. 100 1,70 0,93 0,75
9. 150 1,71 0,96 0,75
10. 200 1,76 0,98 0,75
11. 300 1,81 1,02 0,75
12. 400 1.84 1,02 0,75
13.. 500 1.84 1,04 0,75
73
pada Stop Kontak Kedua
No. Beban resistif Vdioda VRGT2 VGT2

1. 5 1,46 0,76 0,66
2. 10 1,48 0,78 0,69
3. 25 1,53 0,78 0,69
4 35 1,53 0,79 0,70
5. 40 1,55 0,78 0,71
6. 50 1,55 0,79 0,71
7. 65 1,57 0,81 0,71
8. 100 1,62 0,89 0,72
9. 150 1,64 0,89 0,72
10. 200 1,69 0,96 0,72
11. 300 1,70 1,00 0,72
12. 400 1.74 1,00 0,72
13. 500 1.79 1,22 0,72
Tabel 4.13 Data Tegangan Hasil Pengamatan untuk Beban Induktif
pada Stop Kontak Pertama dan Kedua
Stop kontak Beban induktif Vdioda VRGT VGT

1 72 1,64 0,83 0,71
2 72 1,62 0,87 0,68
Dari data hasil pengamatan dengan perhitungan menggunakan persamaan
2-1 pada Bab II maka arus pada gate triac dapat dihitung sebagai berikut,
Untuk stop kontak beban pertama:
1. Beban resistif 5 Watt
1,52V − 0,72V
IGT1 = = 2,667 mA
300Ω
74
1,50V − 0,72V
IGT1 = = 2,600 mA
300Ω
1,56V − 0,74V
IGT1 = = 2,733mA
300Ω
1,56V − 0,73V
IGT1 = = 2,767 mA
300Ω
1,61V − 0,73V
IGT1 = = 2,933mA
300Ω
1,64V − 0,73V
IGT1 = = 3,033mA
300Ω
1,66V − 0,73V
IGT1 = = 3,100mA
300Ω
8. Beban resitif 100 Watt
1,70V − 0,75V
IGT1 = = 3,167 mA
300Ω

75
1,71V − 0,75V
IGT1 = = 3,200 mA
300Ω
1,76V − 0,75V
IGT1 = = 3,367 mA
300Ω
1,81V − 0,75V
IGT1 = = 3,533mA
300Ω
1,84V − 0,75V
IGT1 = = 3,633mA
300Ω
1,84V − 0,75V
IGT1 = = 3,633mA
300Ω
Untuk stop kontak beban kedua:
1,46V − 0,66V
IGT2 = = 2,667 mA
300Ω
1,48V − 0,69V
IGT2 = = 2,633mA
300Ω
1,53V − 0,69V
IGT2 = = 2,800mA
300Ω
76
1,53V − 0,70V
IGT2 = = 2,767 mA
300Ω
1,55V − 0,71V
IGT2 = = 2,800 mA
300Ω
1,55V − 0,71V
IGT2 = = 2,800 mA
300Ω
1,57V − 0,71V
IGT2 = = 2,867 mA
300Ω
1,62V − 0,72V
IGT2 = = 3,000mA
300Ω
1,64V − 0,72V
IGT2 = = 3,067 mA
300Ω
1,69V − 0,72V
IGT2 = = 3,233mA
300Ω
1,70V − 0,72V
IGT2 = = 3,267 mA
300Ω

77
1,74V − 0,72V
IGT2 = = 3,400mA
300Ω
1,79V − 0,72V
IGT2 = = 3,567 mA
300Ω
Beban Induktif pada stop kontak pertama:
1,64V − 0,71V
IGT1 = = 3,100 mA
300Ω
Beban Induktif pada stop kontak kedua:
1,62V − 0,68V
IGT2 = = 3,133mA
300Ω
Dari data hasil pengamatan kemudian dilakukan perhitungan dengan
hambatan tetap pada gate triac diperoleh arus gate minimum sebesar 2,600 mA,
jadi dengan arus sebesar itu triac bisa aktif.
Pada saat melakukan pengamatan hour meter tanpa beban ketika switch
power alat diubah dari posisi off ke posisi on terjadi sinyal on sesaat pada
detektor beban. Hal ini menyebabkan alat mendeteksi ada beban yang menyala
tetapi hanya terjadi selama 1 detik. Dalam pengamatan dengan beban sebuah
seterika otomatis 300 Watt AC 220 Volt dan televisi 65 Watt AC 220 Volt.
Pengamatan beban sebuah seterika otomatis alat dapat mendeteksi dengan baik
kondisi beban on atau off secara otomatis. Data hasil pengamatan dengan beban
seterika terdapat pada Tabel 4.14.

78
Tabel 4.14 Data Hasil Pengamatan Beban dengan Kondisi On dan off
otomatis
Kondisi Stop kontak Vdioda VRGT VGT

(Volt) (Volt) (Volt)
On 1 1,6 0,8 0,7
2 1,8 0,8 0,7
off 1 0 0 0
2 0 0 0
Data hasil pengamatan dengan beban televisi saat beban dalam kondisi on
dan standby dicantumkan pada Tabel 4.15.
Tabel 4.15 Data Hasil Pengamatan Beban dengan Kondisi On dan Standby
Kondisi Stop kontak Vdioda VRGT VGT

(Volt) (Volt) (Volt)
On 1 1,6 0,7 0,7
2 1,5 0,8 0,6
Standby 1 1,3 0,8 0,6
2 1,3 0,6 0,6
Hasil pengamatan alat masih mendeteksi on pada saat televisi dalam keadaan
standby karena pada saat kondisi standby gate triac masih dapat terpicu yang
menyebabkan beban dideteksi on.
Untuk mengetahui lebih lanjut tingkat ketelitian alat dilakukan
pengamatan dengan osiloskop. Data yang diamati yaitu frekuensi clock yang
membangkitkan interupsi eksternal. Karena sinyal clock tersebut sangat
mempengaruhi tingkat ketelitian jam. Sinyal clock 1 Hz dibangkitkan oleh RTC
kemudian dijadikan pemicu interupsi setiap 1 detik. Setiap terjadi interupsi

79
eksternal maka variabel detik dalam program akan bertambah 1 dari 00 sampai
maksimal 59.
Gambar 4.6 Hasil Pengamatan Sinyal 1 Hz
Dari osiloskop digital dapat dilihat sinyal clock untuk interupsi eksternal
terukur tepat 1 Hz. Gambar 4.6 menunjukkan hasil pengamatan sinyal 1 Hz dari
RTC dengan menggunakan osiloskop digital. Data waktu hasil pengamatan yang
tersimpan pada hour meter dapat ditampilkan dengan penekanan tombol menu
dan select. Tombol – tombol ini dapat berfungsi baik sesuai dengan fungsinya.
BAB V
KESIMPULAN DAN SARAN
5.1 Kesimpulan
Setelah selesai dari proses perancangan dan perakitan serta berdasarkan
hasil pengamatan, maka dapat ditarik beberapa kesimpulan sehubungan dengan
alat yang dimaksud, yaitu hour meter sebagai berikut;
1. Hour meter ini dapat bekerja pada beban resistif 5 Watt, 10 Watt,
25 Watt, 35 Watt, 40 Watt, 50 Watt, 65 Watt, 100 Watt, 150 Watt,
200 Watt, 300, Watt, 400 Watt dan 500 Watt pada tegangan AC
220 Volt, juga dapat bekerja pada beban induktif 72 Watt AC 220
Volt.
2. Hour meter ini masih mendeteksi on pada beban dalam kondisi
standby.
3. Tombol menu dan select dapat berfungsi secara baik sesuai dengan
fungsinya.
5.2 Saran
Hasil penelitian ini masih banyak kekurangan dan kelemahan, maka
penulis dapat menyarankan sebagai berikut;
80
81
1. Pengembangan pada rangkaian pendeteksi beban karena belum
berfungsi dengan baik.
2. Pada saat hour meter ini tidak digunakan untuk melakukan
pengukuran dapat difungsikan sebagai jam digital.

DAFTAR PUSTAKA
1. “3.0 A Rectifier, 1N5400 thru 1N5408”, STAD –JAN.07.2005
http://www.dataseheetcatalog.com
2. “BT136 Series D”, Rev 1.400 June 2001,http://www.datasheetcatalog.com
3. “DS1307 6x8, Serial, I2C Real Time Clock”, copyright 2004 Maxim
Integrated Product. Printed USA http://www.maxim-
ic.com/TechSupport/QA/ntrl.htm.
4. “Data Sheet 74HC/HCT595 8-bit serial – in / serial or parallel – out shift
register with output lacthes; 3 – state”, Philips Semiconductors. 1994 June 04.
http://www.datasheetcatalog.com
5. Graf, Rudolf F. & William Sheets. 1995. Encyclopedia of ELEKTRONIC
CIRCUITS. Volume 5. TAB BOOKs Division of McGraw-Hill, Inc.
6. “M68HC08 Microcontrollers, MC68HC908QY4/D, Rev 1.0, 8/2003”,
http://www.datasheetcatalog.com/datasheets_pdf/M/C/6/8/MC68HC908QY4.s
html
7. Nalwan, P A. 2004. Panduan Praktis Penggunaan dan Antarmuka Modul
LCD M1632. PT Elex Media Komputindo Kelompok Gramedia, Jakarta.
8. Rusdianto, Eduard. 2002. Penerapan Konsep Dasar Listrik dan Elektronika,
Penerbit Kanisius, Yogyakarta.
82
83
9. “The I2C Bus Spefisication, Version 2.1”, January 2000.
http://www.semiconductors.philips.com/markets/mms/protocols/i2c/.
L1
LAMPIRAN LISTING PROGRAM

finalTGA_IWS_HM.asm Assembled with CASM08Z 28/09/2006 09:35:24
PAGE 1
1
****************************************************
**
2 ;HOUR METER
3 ;BASE ON MOTOROLA MC68HC908QY4
4 ;I WAYAN SANTRA
5 ;005114006
6 ;UNIVERSITAS SANATA DHARMA
7
****************************************************
**
8 ;definisi macro dari: Raymond Weisling
9
0000 10 $MACRO bitset bitname
11 bset %1-(%1\8)*8,%1\8
0000 12 $MACROEND
13
0000 14 $MACRO bitclr bitname
15 bclr %1-(%1\8)*8,%1\8
0000 16 $MACROEND
17
0000 18 $MACRO braset bitname,bra_dest
19 brset %1-(%1\8)*8,%1\8,%2
0000 20 $MACROEND
21
0000 22 $MACRO braclr bitname,bra_dest
23 brclr %1-(%1\8)*8,%1\8,%2
0000 24 $MACROEND
25
****************************************************
****
26 *************************
Inisialisasi**************
****
27
****************************************************
****
28
29 * inisialisai Port I/O *
30
0000 31 PortA equ $00
;port I/O
0000 32 PTA0 equ PortA*8+0
38
0000 39 DDRA equ $04
;Data
Direction
Register B
0000 40 DDRA0 equ DDRA*8+0
46
0000 47 PortB equ $01
;PortB
0000 48 SDA equ PortB*8+0
;
0000 49 SCL equ PortB*8+1
;
0000 50 Lclk_SPI equ PortB*8+2
;12

PAGE 2
STcp
0000 51 Sclk_SPI equ PortB*8+3
;11
SHcp
0000 52 Data_SPI equ PortB*8+4
;14
data
53
0000 54 Eclock equ PortB*8+5
;E lcd
warna hijau
0000 55 RS equ PortB*8+6
;RS lcd
0000 56 PTB7 equ PortB*8+7
57
58
;=================================================
59 ; PTA0 untuk switch 2
60 ; PTA1 untuk switch 1
61 ; PTA2 untuk IRQ
62 ; PTA3 untuk beban 1
63 ; PTA4 untuk beban 2
64 ; PTA5 untuk belum terpakai
65
66 ; PTB0 untuk SDA DS1307
67 ; PTB1 untuk serial clock (SCL) DS1307
68 ; PTB2 untuk Lacth clock shift register
terhubung
dengan pin 12
74HC595
69 ; PTB3 untuk Shift clock 74HC595
70 ; PTB4 untuk data serial
71 ; PTB5 untuk clock LCD
72 ; PTB6 untuk RS LCD
73 ; PTB7 belum terpakai
74
;=================================================
75
0000 76 DDRB equ $05
;Data
Direction
Register B
0000 77 ambil_data equ DDRB*8+0
0000 78 DDRB1 equ DDRB*8+1
0000 85 PTBPUE equ $0C
86 ;BFCR equ $FE03
87 ;BCFE equ BFCR*8+7
88
*********************************************
89 * inisialisai IRQ
*
90
*********************************************
0000 91 ISCR equ $1D
0000 92 ACK equ ISCR*8+2
93
94
*********************************************
95 * inisialisasi timer
*
96
*********************************************
0000 97 TCNTH equ $21
0000 98 TCNTL equ $22
0000 99 TMODH equ $23
0000 100 TMODL equ $24
0000 101 TSC equ $20
0000 102 TIM_STOP equ TSC*8+5

PAGE 3
;bit
ke 5 TSC
0000 103 TRST equ TSC*8+4
;bit
ke 4 TSC
0000 104 TOF equ TSC*8+7
;bit
ke 7 TSC
105
106 ********************************************
107 * inisialisasi keyboard interrupt *
108 ********************************************
0000 109 KBSCR equ $1A
0000 110 IMASKK equ KBSCR*8+1
0000 111 ACKK equ KBSCR*8+2
0000 112 KBIER equ $1B
0000 113 KBIE0 equ KBIER*8+0
;enable
bit KBI0
;enable
bit KBI1
;enable
bit KBI2
;enable
bit KBI3
;enable
bit KBI4
;enable
bit KBI5
119
120 *******************************************
121 * inisialisasi memori *
122 *******************************************
0000 123 UserRAM equ $80
0000 124 RAM equ $9E
0000 125 ROM equ $EE00
126
127 *******************************************
128 *inisialisasi register config *
129 *******************************************
0000 130 CONFIG2 equ $1E
0000 131 OSC1 equ CONFIG2*8+3
0000 132 IRQEN equ CONFIG2*8+6
0000 133 CONFIG1 equ $1F
0000 134 OSCSTAT equ $36
0000 135 ECGST equ OSCSTAT*8+0
0000 136 ECGON equ OSCSTAT*8+1
137
138
139
*********************************************
140 *BAGIAN RTC
*
141
*********************************************
0000 142 DS_tulis equ $D0
;alamat register DS1307
untuk tulis
0000 143 DS_baca equ $D1
untuk baca
0000 144 detik equ $00
untuk detik
0000 145 menit equ $01
untuk menit
0000 146 jam equ $02
untuk jam

PAGE 4
0000 147 hari equ $03

untuk hari
0000 148 tanggal equ $04
;alamat register DS1307 untuk
tanggal
0000 149 bulan equ $05
untuk bulan
0000 150 tahun equ $06
untuk tahun
0000 151 control equ $07
;alamat register DS1307 untuk
kontrol
152
153 ;RAM untuk menyimpan data hasil
154 ;pengukuran
155
156 ;RAM untuk alat pertama
0000 157 exram1 equ $08
;3 byte data mulai
08,09,0A
0000 158 exram2 equ $0B
;3 byte data akhir
0B,0C,0D
0000 159 exram3 equ $0E
;3 byte data total
0E,0F,10
0000 160 exram4 equ $11
;3 byte data jam
11,12,13
161
162 ;RAM untuk alat kedua
0000 163 exram5 equ $14
;3 byte data mulai
14,15,16
0000 164 exram6 equ $17
;3 byte data akhir
17,18,19
0000 165 exram7 equ $1A
;3 byte data total
1A,1B,1C
0000 166 exram8 equ $1D
;3 byte data jam
1D,1E,1F
167
0000 168 exram9 equ $20
;1
byte flag
169
170
171
0080 172 ORG UserRAM
173 *-------------------------------------------
----*
174 *--------penyimpanan data untuk rtc---------
----*
175 *-------------------------------------------
----*
0080 176 data1_mulai ds 3
;data mulai alat
digunakan
0083 177 data1_akhir ds 3
;data tanggal,bulan,tahun
terakhir
0086 178 data1_total ds 3
;data
jam total
0089 179 data1_jam ds 3
;data jam pengukuran
terakhir
180 *-------------------------------------------
----*
008C 181 data2_mulai ds 3
;data
mulai alat
digunakan
008F 182 data2_akhir ds 3
;data
tanggal,bulan,tahun
terakhir
0092 183 data2_total ds 3
;data
jam total

PAGE 5
0095 184 data2_jam ds 3
;data jam pengukuran
terakhir
185 *-------------------------------------------
----*
0098 186 data1_menit ds 1
0099 187 data1_detik ds 1
009A 188 data2_menit ds 1
009B 189 data2_detik ds 1
190
009C 191 key ds 1
009D 192 savekey1 equ key*8+0
009D 193 savekey2 equ key*8+1
009D 194 datamak equ key*8+2
009D 195 sisamenit ds 1
009E 196 sisamenit1 ds 1
009F 197 sisamenit2 ds 1
00A0 198 sisajam ds 1
199 ;sisajam1 ds 1
200 ;sisajam2 ds 1
201
009E 202 ORG RAM
;alamat
awal RAM
203
009E 204 jam_set ds 1
;00-23
009F 205 menit_set ds 1
;00-59
00A0 206 detik_set ds 1
00A1 207 tgl_set ds 1
;
00A2 208 bulan_set ds 1
;01-12
00A3 209 tahun_set ds 1
;
00A4 210 tgld1 ds 1
00A5 211 buland1 ds 1
00A6 212 tahund1 ds 1
213
214
215
00A7 216 flag ds 1
00A8 217 IRQ_flag equ flag*8+0
00A8 218 setting equ flag*8+1
00A8 219 f_tabel equ flag*8+2
00A8 220 key1 equ flag*8+3
00A8 221 key2 equ flag*8+4
00A8 222 timedelay equ flag*8+5
223
00A8 224 countsave ds 1
00A9 225 waktu ds 1
00AA 226 count ds 1
00AB 227 regdata ds 1
228
229 *--------------------------------*
00AC 230 atur ds 1
00AD 231 aturjam equ atur*8+0
00AD 232 viewdata equ atur*8+1
00AD 233 space20 equ atur*8+2
234 *--------------------------------*

PAGE 6
235
00AD 236 Data_Serial ds 1
237
238
00AE 239 switch ds 1
00AF 240 sw00 equ switch*8+0
;tombol 2
;tombol 1
;
;device10
;device11
;device20
;device21
247
248
00AF 249 switch1 ds 1
00B0 250 sw11 equ switch1*8+0
;tombol 2
253
254
255
00B0 256 sisa ds 2
257
258 ;-------------------------------------------
-------
00B2 259 detik_temp ds 1
;RTC
00B3 260 menit_temp ds 1
00B4 261 jam_temp ds 1
00B5 262 hari_temp ds 1
00B6 263 tanggal_temp ds 1
00B7 264 bulan_temp ds 1
00B8 265 tahun_temp ds 1
266
267
268 ;-------------------------------------------
-------
00B9 269 detik1 ds 1
00BA 270 menit1 ds 1
00BB 271 jam1 ds 3
00BE 272 detik2 ds 1
00BF 273 menit2 ds 1
00C0 274 jam2 ds 3
275
276
EE00 277 ORG ROM ;alamat
awal
ROM
278
EE00 [01] 9C 279 RESET rsp
;reset
stack
pointer
EE01 [01] 4F 280 clra
;hapus
accumulator
EE02 [01] 8C 281 clrh
;hapus

PAGE 7
isi
register H
EE03 [01] 5F 282 clrx
;hapus
isi
register X
EE04 [02] AE80 283 ldx #!128
EE06 [03] E77F 284 HAPUS sta UserRAM-1,x ;hapus
RAM
EE08 [03] 5BFC 285 dbnzx HAPUS
EE0A [04] 6E311F 286 mov #$31,CONFIG1
;disable
watchdog
EE0D [04] 6E401E 287 mov #$40,CONFIG2
;internal
osilator
288 ;mov #$04,ISCR
289 ;-------------------------------------------
------
290 ;init I\0
EE10 [04] 6EE404 291 mov #%11100100,DDRA
EE13 [04] 6E7F05 292 mov #%01111111,DDRB
;PTB0-->PTB6 for
output PTB7
EE16 [04] 6EFF01 293 mov #$FF,PortB
;untuk input
EE19 [04] 6EE700 294 mov #$E7,PortA
EE1C [04] 6E030C 295 mov
#%00000011,PTBPUE
;aktifksn pullup
internal
296 ;-------------------------------------------
------
297 ;init timer
298 ;mov #$50,TSC
;1100
0111-->TSC
299 ;mov #$FF,TMODH
;
300 ;mov #$FF,TMODL
301 ;-------------------------------------------
------
302 ;init keyboard
303 ;mov #$01,KBSCR
304 ;mov #$03,KBIER
;0000 0011
305 ;-------------------------------------------
------
EE1F [04] 6EFFAE 306 mov #$FF,switch
307 ;mov #$FF,switch1
308
309
310 ;init_flag
EE22 [03] 3FA7 311 clr flag
EE24 [03] 3FA9 312 clr waktu
EE26 [03] 3FAA 313 clr count
EE28 [03] 3FA8 314 clr countsave
EE2A [03] 3FAC 315 clr atur
EE2C [03] 3FAF 316 clr switch1
317
318 *------------------------------------*
EE2E [05] CDF272 319 jsr Init_LCD
;inisialisas
i LCD
EE31 [05] CDF67E 320 jsr WAVE_ON
;inisialisas
i RTC
321 *------------------------------------*
EE34 [02] 9A 322 cli
;aktifkan semua
interupsi
323
324 *-------------------------------------------
--------
-*
325 *-----program utama-----*

PAGE 8
326 *-------------------------------------------
--------
-*
327 ;jsr bacakey
EE35 [05] CDF2EC 328 main1 jsr bacaRAM
EE38 macro 329 braset datamak,resetmak
EE38 [05] 049C1B 330 BRSET %1-(%1\8)*8,%1\8,%2
EE3B [05] CDF6B2 331 mainloop jsr datawaktu
EE3E macro 332 braset PTA3,dev1_on
;jika
dev1 nyala
EE3E [05] 060018 333 BRSET %1-(%1\8)*8,%1\8,%2
EE41 macro 334 scandev2 bitclr sw11
;else
matikan sw03
EE41 [04] 11AF 335 BCLR %1-(%1\8)*8,%1\8
EE43 macro 336 braset PTA4,dev2_on
;jika
dev2 nyala
EE43 [05] 08005F 337 BRSET %1-(%1\8)*8,%1\8,%2
EE46 macro 338 bitclr sw12
;else
matikan sw04
EE46 [04] 13AF 339 BCLR %1-(%1\8)*8,%1\8
340
341 ;braset key1,simpan
;flag
simpan alat 1
342
343 ;braclr key2,look_TB
;flag
simpan alat 2
344 ;bitclr key2
345 ;simpan bitclr key1
346 ; jsr savetoRTC
EE48 [05] CDF789 347 look_TB jsr SCAN_TB
EE4B macro 348 main braclr sw01,jpmenu1
;
EE4B [05] 03AE05 349 BRCLR %1-(%1\8)*8,%1\8,%2
EE4E [05] CDEEF2 350 main0 jsr viewtime
EE51 [03] 20E8 351 bra mainloop
352 *-------------------------------------------
--------
---*
EE53 [03] CCEEFB 353 jpmenu1 jmp menu1
354
EE56 [03] CCF020 355 resetmak jmp viewtotmak
356 ;bra
357 *-------------------------------------------
--------
---*
358 *===================================*
359 *jika alat pertama dinyalakan program akan
360 *masuk ke bagian program berikut
361 *-------------------------------------------
--------
---*
362
EE59 [03] 3FB9 363 dev1_on clr detik1
EE5B [03] 3FBA 364 clr menit1
EE5D [03] 3FBB 365 clr jam1+0
366 ;bitset key1
EE5F macro 367 braset savekey1,dev1_on0
EE5F [05] 009C0A 368 BRSET %1-(%1\8)*8,%1\8,%2
EE62 macro 369 bitset savekey1
EE62 [04] 109C 370 BSET %1-(%1\8)*8,%1\8
371
;mengetahui alat
pernah hidup
EE64 [02] A608 372 lda #exram1

PAGE 9
EE66 [05] CDF298 373 jsr toRAM

EE69 [05] CDF2B8 374 jsr toTEMP1A
EE6C macro 375 dev1_on0 bitset sw11
;flag
pada IRQ
EE6C [04] 10AF 376 BSET %1-(%1\8)*8,%1\8
EE6E [05] CDF268 377 jsr clrscr
EE71 [01] 5F 378 clrx
;hapus
isi reg x
EE72 [04] D6F876 379 bacatab9 lda Tabel9,x
;baca
tabel
EE75 [04] 410F06 380 cbeqa #$0F,back0
;tampilkan
EE78 [05] CDF28A 381 jsr Kirim_Karakter
; ALAT
1 ON
EE7B [01] 5C 382 incx
;pada
layar LCD
EE7C [03] 20F4 383 bra bacatab9
;
EE7E [01] 5F 384 back0 clrx
385
EE7F macro 386 back1 braclr IRQ_flag,back1
EE7F [05] 01A7FD 387 BRCLR %1-(%1\8)*8,%1\8,%2
EE82 macro 388 bitclr IRQ_flag
EE82 [04] 11A7 389 BCLR %1-(%1\8)*8,%1\8
EE84 [02] A6C2 390 lda #$C2
EE86 [05] CDF28E 391 jsr Kirim_Perintah
;
EE89 [05] CDF583 392 jsr view_JAM1
EE8C macro 393 braset PTA3,back1
;baca
terus alat1
EE8C [05] 0600F0 394 BRSET %1-(%1\8)*8,%1\8,%2
EE8F [05] CDF6B2 395 jsr datawaktu
;ambil data
tanggal,bulan,tahun
396 ;lda #exram2
397 ;jsr toRAM
EE92 [05] CDF2C5 398 jsr toTEMP1B
;
EE95 [05] CDF42F 399 jsr saveTOTAL1
;simpan ke
temp mikro
EE98 [05] CDF409 400 jsr save_JAM1
;simpan ke
temp mikro
EE9B [05] CDF694 401 jsr savetoRTC
EE9E macro 402 bitset timedelay
EE9E [04] 1AA7 403 BSET %1-(%1\8)*8,%1\8
EEA0 macro 404 looping1 braset timedelay,looping1
EEA0 [05] 0AA7FD 405 BRSET %1-(%1\8)*8,%1\8,%2
EEA3 [03] 2096 406 bra mainloop
;
407
408 *-------------------------------------------
--------
-
-------*
409 *======================================*
410 *jika alat kedua dinyalakan program akan
411 *masuk ke bagian program berikut
412 *-------------------------------------------
--------
-
-------*
413
EEA5 [03] 3FBE 414 dev2_on clr detik2
EEA7 [03] 3FBF 415 clr menit2
EEA9 [03] 3FC0 416 clr jam2+0
417 ;bitset key2

PAGE 10
EEAB macro 418 braset savekey2,dev2_on0

EEAB [05] 029C0A 419 BRSET %1-(%1\8)*8,%1\8,%2
EEAE macro 420 bitset savekey2
EEAE [04] 129C 421 BSET %1-(%1\8)*8,%1\8
422
;mengetahui alat
pernah hidup
EEB0 [02] A614 423 lda #exram5
EEB2 [05] CDF298 424 jsr toRAM
EEB5 [05] CDF2D2 425 jsr toTEMP2A
EEB8 macro 426 dev2_on0 bitset sw12
EEB8 [04] 12AF 427 BSET %1-(%1\8)*8,%1\8
EEBA [05] CDF268 428 jsr clrscr
EEBD [01] 5F 429 clrx
;hapus
isi reg x
EEBE [04] D6F888 430 bacatab10 lda Tabel10,x
;baca
tabel
EEC1 [04] 410F06 431 cbeqa #$0F,back2
;tampilkan
EEC4 [05] CDF28A 432 jsr Kirim_Karakter
; ALAT
2 ON
EEC7 [01] 5C 433 incx
;pada
layar LCD
EEC8 [03] 20F4 434 bra bacatab10
;
EECA [01] 5F 435 back2 clrx
436
EECB macro 437 back3 braclr IRQ_flag,back2
;baca flag
interupsi
EECB [05] 01A7FC 438 BRCLR %1-(%1\8)*8,%1\8,%2
EECE macro 439 bitclr IRQ_flag
;clear flag
EECE [04] 11A7 440 BCLR %1-(%1\8)*8,%1\8
EED0 [02] A6C2 441 lda #$C2
EED2 [05] CDF28E 442 jsr Kirim_Perintah
;
EED5 [05] CDF5AA 443 jsr view_JAM2
EED8 macro 444 braset PTA4,back3
;baca
terus alat 2
EED8 [05] 0800F0 445 BRSET %1-(%1\8)*8,%1\8,%2
EEDB [05] CDF6B2 446 jsr datawaktu
;ambil data
tanggal,bulan,tahun
447 ;lda #exram6
448 ;jsr toRAM
;
EEDE [05] CDF2DF 449 jsr toTEMP2B
EEE1 [05] CDF4D9 450 jsr saveTOTAL2
EEE4 [05] CDF41C 451 jsr save_JAM2
EEE7 [05] CDF694 452 jsr savetoRTC
EEEA macro 453 bitset timedelay
EEEA [04] 1AA7 454 BSET %1-(%1\8)*8,%1\8
EEEC macro 455 looping1b braset timedelay,looping1b
EEEC [05] 0AA7FD 456 BRSET %1-(%1\8)*8,%1\8,%2
EEEF [03] CCEE3B 457 jmp mainloop
458 ;jmp mainloop
459 *-------------------------------------------
--------
-
-------*
460 *==================================*
EEF2 macro 461 viewtime braclr IRQ_flag,tomain
EEF2 [05] 01A705 462 BRCLR %1-(%1\8)*8,%1\8,%2
EEF5 macro 463 bitclr IRQ_flag

PAGE 11
EEF5 [04] 11A7 464 BCLR %1-(%1\8)*8,%1\8

EEF7 [05] CDF20D 465 jsr tampilwaktu
EEFA [04] 81 466 tomain rts
467
468 *-------------------------------------------
-*
469 *program untuk menampilkan menu 'pengaturan'
*
470 *pada layar lcd
*
471 *-------------------------------------------
-*
472 menu1 ;mov #$00,CONFIG2
EEFB [05] CDF668 473 jsr WAVE_OFF
;diasble
sinyal 1 Hz
EEFE macro 474 bitset sw01
EEFE [04] 12AE 475 BSET %1-(%1\8)*8,%1\8
EF00 [05] CDF268 476 jsr clrscr
;hapus
display lcd
EF03 [01] 5F 477 clrx
;hapus reg x
EF04 [01] 8C 478 clrh
;hapus
reg h
EF05 [04] D6F82D 479 bacatab lda Tabel1,x
;ambil tabel
480 *-------------------------------------------
*
EF08 [04] 410F06 481 cbeqa #$0F,lagi
;tampilkan
pada lcd
EF0B [05] CDF28A 482 jsr Kirim_Karakter
;PENGATURAN
EF0E [01] 5C 483 incx
EF0F [03] 20F4 484 bra bacatab
EF11 [01] 5F 485 lagi clrx
486 *-------------------------------------------
*
EF12 [05] CDF789 487 scan01 jsr SCAN_TB
EF15 macro 488 braclr sw00,setjamz
;cek flag
setjamz
EF15 [05] 01AE05 489 BRCLR %1-(%1\8)*8,%1\8,%2
EF18 macro 490 braclr sw01,menu2
EF18 [05] 03AE29 491 BRCLR %1-(%1\8)*8,%1\8,%2
EF1B [03] 20F5 492 bra scan01
493 *-------------------------------------------
-*
EF1D [05] CDF09C 494 setjamz jsr setjam
;jump
to setjam
495
EF20 macro 496 bitset sw01
;set
flag
EF20 [04] 12AE 497 BSET %1-(%1\8)*8,%1\8
EF22 [05] CDF268 498 bacatab70 jsr clrscr
;hapus
layar lcd
EF25 [01] 5F 499 clrx
;kosongkan reg x
EF26 [01] 8C 500 clrh
;kosongkan reg h
EF27 [04] D6F859 501 bacatab7 lda Tabel7,x
;baca
tabel7
EF2A [04] 410F06 502 cbeqa #$0F,lagi7
;akhir
karakter?
EF2D [05] CDF28A 503 jsr Kirim_Karakter
;tampilkan SIMPAN
SETTING
EF30 [01] 5C 504 incx
;naikkan x

PAGE 12
EF31 [03] 20F4 505 bra bacatab7

;kembali
baca tabel
EF33 [05] CDF789 506 lagi7 jsr SCAN_TB
;baca tombol
;simpan
setting?
EF36 [05] 03AE0B 508 BRCLR %1-(%1\8)*8,%1\8,%2
EF39 macro 509 braset sw00,lagi7
;
EF39 [05] 00AEF7 510 BRSET %1-(%1\8)*8,%1\8,%2
EF3C macro 511 bitset sw00
;
EF3C [04] 10AE 512 BSET %1-(%1\8)*8,%1\8
EF3E [05] CDF60F 513 jsr toRTC
;setting
di simpan
EF41 [03] CCEE4E 514 jmp main0
515
*===================================================
==*
EF44 macro 516 menu2 bitset sw01
EF44 [04] 12AE 517 BSET %1-(%1\8)*8,%1\8
EF46 [05] CDF268 518 menu20 jsr clrscr
EF49 [01] 5F 519 clrx
EF4A [01] 8C 520 clrh
EF4B [04] D6F83A 521 bacatab2 lda Tabel2,x
;ambil
tabel
EF4E [04] 410F06 522 cbeqa #$0F,lagi2
;sampai karakter
terakhir
EF51 [05] CDF28A 523 jsr Kirim_Karakter
;tampilkan
MULAI ke LCD
EF54 [01] 5C 524 incx
;naikkan x
;
EF57 [01] 5F 526 lagi2 clrx
;x=0
527 ;jsr bacatmbl
EF58 macro 528 braset
space20,space20_1
;flag
space 2
EF58 [05] 04AC16 529 BRSET %1-(%1\8)*8,%1\8,%2
530 ;jsr bacaRAM1
;ambil data
dari RAM
EF5B [02] A631 531 lda #$31
;tampilkan 1
EF5D [05] CDF28A 532 jsr Kirim_Karakter
;
EF60 [02] A63A 533 lda #$3A
;tampilkan :
EF62 [05] CDF28A 534 lagi2a jsr Kirim_Karakter
EF65 [05] CDF31B 535 jsr VIEW_MULAI1
EF68 [02] A6C0 536 lda #$C0
;mulai
baris 2
EF6A [05] CDF28E 537 jsr Kirim_Perintah
;
EF6D macro 538 bitset space20
;aktifkan flag
baris 2
EF6D [04] 14AC 539 BSET %1-(%1\8)*8,%1\8
EF6F [03] 20DA 540 bra bacatab2
;baca
tabel
EF71 macro 541 space20_1 bitclr space20
;
EF71 [04] 15AC 542 BCLR %1-(%1\8)*8,%1\8
EF73 [02] A632 543 lda #$32

PAGE 13
;tampilkan 2
;
EF78 [02] A63A 545 lda #$3A
;
EF7A [05] CDF28A 546 lagi2b jsr Kirim_Karakter
;
EF7D [05] CDF339 547 jsr VIEW_MULAI2
EF80 [05] CDF789 548 menu2a jsr SCAN_TB
;
EF83 [05] 03AE02 550 BRCLR %1-(%1\8)*8,%1\8,%2
EF86 [03] 20F8 551 bra menu2a
;
552
553
EF88 macro 554 menu3 bitset sw01
EF88 [04] 12AE 555 BSET %1-(%1\8)*8,%1\8
EF8A [05] CDF268 556 jsr clrscr
EF8D [01] 5F 557 clrx
EF8E [01] 8C 558 clrh
EF8F [04] D6F840 559 bacatab3 lda Tabel3,x
;ambil
tabel3
EF92 [04] 410F06 560 cbeqa #$0F,lagi3
;tampilkan AKHIR
;ke LCD
EF98 [01] 5C 562 incx
564
EF9B [01] 5F 565 lagi3 clrx
EF9C macro 566 braset
space20,space30_1
;flag
space 2
EF9C [05] 04AC16 567 BRSET %1-(%1\8)*8,%1\8,%2
EF9F [02] A631 568 lda #$31
EFA1 [05] CDF28A 569 jsr Kirim_Karakter
EFA4 [02] A63A 570 lda #$3A
EFA6 [05] CDF28A 571 lagi3a jsr Kirim_Karakter
EFA9 [05] CDF356 572 jsr VIEW_AKHIR1
EFAC [02] A6C0 573 lda #$C0
;mulai
baris 2
EFAE [05] CDF28E 574 jsr Kirim_Perintah
;
EFB1 macro 575 bitset space20
;aktifkan flag
baris 2
EFB1 [04] 14AC 576 BSET %1-(%1\8)*8,%1\8
EFB3 [03] 20DA 577 bra bacatab3
;baca
tabel
EFB5 macro 578 space30_1 bitclr space20
;
EFB5 [04] 15AC 579 BCLR %1-(%1\8)*8,%1\8
EFB7 [02] A632 580 lda #$32
;tampilkan 2
EFB9 [05] CDF28A 581 jsr Kirim_Karakter
;
EFBC [02] A63A 582 lda #$3A
;
EFBE [05] CDF28A 583 lagi3b jsr Kirim_Karakter
;
EFC1 [05] CDF374 584 jsr VIEW_AKHIR2
EFC4 [05] CDF789 585 menu30 jsr SCAN_TB
EFC7 macro 586 braclr sw01,menu4
EFC7 [05] 03AE02 587 BRCLR %1-(%1\8)*8,%1\8,%2
EFCA [03] 20F8 588 bra menu30
589
EFCC macro 590 menu4 bitset sw01
EFCC [04] 12AE 591 BSET %1-(%1\8)*8,%1\8

PAGE 14
EFCE [05] CDF268 592 jsr clrscr

EFD1 [01] 5F 593 clrx
EFD2 [01] 8C 594 clrh
EFD3 [04] D6F846 595 bacatab4 lda Tabel4,x
;ambil
tabel3
EFD6 [04] 410F06 596 cbeqa #$0F,lagi4
;tampilkan
‘ LAMA ‘
EFD9 [05] CDF28A 597 jsr Kirim_Karakter
;ke LCD
EFDC [01] 5C 598 incx
EFDD [03] 20F4 599 bra bacatab4
600 ;braset space20,space40_1
;flag
space 2
EFDF [01] 5F 601 lagi4 clrx
EFE0 [02] A631 602 lda #$31
EFE2 [05] CDF28A 603 jsr Kirim_Karakter
EFE5 [02] A6C0 604 lda #$C0
EFE7 [05] CDF28E 605 jsr Kirim_Perintah
EFEA [05] CDF3BA 606 jsr VIEW_LAMA1
EFED [05] CDF789 607 menu40 jsr SCAN_TB
EFF0 macro 608 braclr sw01,menu4b
EFF0 [05] 03AE02 609 BRCLR %1-(%1\8)*8,%1\8,%2
EFF3 [03] 20F8 610 bra menu40
611
EFF5 macro 612 menu4b bitset sw01
EFF5 [04] 12AE 613 BSET %1-(%1\8)*8,%1\8
EFF7 [05] CDF268 614 jsr clrscr
EFFA [01] 5F 615 clrx
EFFB [01] 8C 616 clrh
EFFC [04] D6F846 617 bacatab4b lda Tabel4,x
;ambil
tabel3
EFFF [04] 410F06 618 cbeqa #$0F,lagi4b
;tampilkan
‘ LAMA ‘
F002 [05] CDF28A 619 jsr Kirim_Karakter
;ke LCD
F005 [01] 5C 620 incx
F006 [03] 20F4 621 bra bacatab4b
;flag
space 2
F008 [01] 5F 623 lagi4b clrx
F009 [02] A632 624 lda #$32
F00B [05] CDF28A 625 jsr Kirim_Karakter
F00E [02] A6C0 626 lda #$C0
F010 [05] CDF28E 627 jsr Kirim_Perintah
F013 [05] CDF3E2 628 jsr VIEW_LAMA2
F016 [05] CDF789 629 menu40b jsr SCAN_TB
F019 macro 630 braclr sw01,menu5
F019 [05] 03AE02 631 BRCLR %1-(%1\8)*8,%1\8,%2
F01C [03] 20F8 632 bra menu40b
633
F01E macro 634 menu5 bitset sw01
F01E [04] 12AE 635 BSET %1-(%1\8)*8,%1\8
F020 [05] CDF268 636 viewtotmak jsr clrscr
F023 [01] 5F 637 clrx
F024 [01] 8C 638 clrh
F025 [04] D6F84B 639 bacatab5 lda Tabel5,x
;ambil
tabel3
F028 [04] 410F06 640 cbeqa #$0F,lagi5
;tampilkan '
TOTAL '
F02B [05] CDF28A 641 jsr Kirim_Karakter
;ke LCD

PAGE 15
F02E [01] 5C 642 incx

F02F [03] 20F4 643 bra bacatab5
;flag
space 2
F031 [01] 5F 645 lagi5 clrx
F032 macro 646 braset
space20,space50_1
;flag
space 2
F032 [05] 04AC16 647 BRSET %1-(%1\8)*8,%1\8,%2
F035 [02] A631 648 lda #$31
F03A [02] A63A 650 lda #$3A
F03C [05] CDF28A 651 lagi5a jsr Kirim_Karakter
F03F [05] CDF392 652 jsr VIEW_TOTAL1
F042 [02] A6C0 653 lda #$C0
;mulai
baris 2
F044 [05] CDF28E 654 jsr Kirim_Perintah
;
F047 macro 655 bitset space20
;aktifkan flag
baris 2
F047 [04] 14AC 656 BSET %1-(%1\8)*8,%1\8
F049 [03] 20DA 657 bra bacatab5
;baca
tabel
F04B macro 658 space50_1 bitclr space20
;
F04B [04] 15AC 659 BCLR %1-(%1\8)*8,%1\8
F04D [02] A632 660 lda #$32
;tampilkan 2
F04F [05] CDF28A 661 jsr Kirim_Karakter
;
F052 [02] A63A 662 lda #$3A
;
F054 [05] CDF28A 663 lagi5b jsr Kirim_Karakter
;
F057 [05] CDF3A6 664 jsr VIEW_TOTAL2
F05A [05] CDF789 665 menu50 jsr SCAN_TB
F05D macro 666 braclr sw01,menu6
F05D [05] 03AE02 667 BRCLR %1-(%1\8)*8,%1\8,%2
F060 [03] 20F8 668 bra menu50
669
F062 macro 670 menu6 bitset sw01
F062 [04] 12AE 671 BSET %1-(%1\8)*8,%1\8
F064 [05] CDF268 672 resetmakRAM jsr clrscr
F067 [01] 5F 673 clrx
F068 [01] 8C 674 clrh
F069 [04] D6F851 675 bacatab6 lda Tabel6,x
;baca
tabel 3
F06C [04] 410F06 676 cbeqa #$0F,lagi6
;tampilkan '
RESET ?'
;pada
layar LCD
F072 [01] 5C 678 incx
F073 [03] 20F4 679 bra bacatab6
F075 [01] 5F 680 lagi6 clrx
F076 [05] CDF789 681 menu60 jsr SCAN_TB
F079 macro 682 braclr sw00,rst
F079 [05] 01AE05 683 BRCLR %1-(%1\8)*8,%1\8,%2
F07C macro 684 braclr sw01,menu7A
F07C [05] 03AE15 685 BRCLR %1-(%1\8)*8,%1\8,%2
F07F [03] 20F5 686 bra menu60
687
F081 macro 688 rst bitset sw00
F081 [04] 10AE 689 BSET %1-(%1\8)*8,%1\8

PAGE 16
F083 [05] CDF5E3 690 jsr resetRAM

F086 [05] CDF789 691 ll jsr SCAN_TB
F089 macro 692 braset sw01,ll
F089 [05] 02AEFA 693 BRSET %1-(%1\8)*8,%1\8,%2
694
F08C macro 695 menu7 bitset sw01
F08C [04] 12AE 696 BSET %1-(%1\8)*8,%1\8
F08E [05] CDF67E 697 jsr WAVE_ON
F091 [03] CCEE35 698 jmp main1
699
F094 macro 700 menu7A bitset sw01
F094 [04] 12AE 701 BSET %1-(%1\8)*8,%1\8
F096 [05] CDF67E 702 jsr WAVE_ON
F099 [03] CCEE4E 703 jmp main0
704
705 *=====================================*
F09C macro 706 setjam bitset sw00
;set flag
F09C [04] 10AE 707 BSET %1-(%1\8)*8,%1\8
F09E [05] CDF268 708 jsr clrscr
;hapus
layar lcd
F0A1 [01] 8C 709 clrh
F0A2 [01] 5F 710 clrx
;hapus
isi reg x
F0A3 [04] D6F89A 711 bacatab11 lda Tabel11,x
;baca
tabel
F0A6 [04] 410F06 712 cbeqa #$0F,back11
;tampilkan
F0A9 [05] CDF28A 713 jsr Kirim_Karakter
; set
jam
F0AC [01] 5C 714 incx
;pada
layar LCD
F0AD [03] 20F4 715 bra bacatab11
;
F0AF [01] 5F 716 back11 clrx
717
718 setjam0 ;jsr clrscr
F0B0 [05] CDF1CB 719 jsr setdata
;tampilkan data
setting jam
F0B3 [05] CDF789 720 scanjam jsr SCAN_TB
;cek tombol
F0B6 macro 721 braclr sw01,setmenit
;set menit?
F0B6 [05] 03AE15 722 BRCLR %1-(%1\8)*8,%1\8,%2
F0B9 macro 723 braclr sw00,setjam1
;set jam?
F0B9 [05] 01AE02 724 BRCLR %1-(%1\8)*8,%1\8,%2
F0BC [03] 20F5 725 bra scanjam
;loop
baca tombol
726
727 *=====================================*
F0BE macro 728 setjam1 bitset sw00
;set flag
F0BE [04] 10AE 729 BSET %1-(%1\8)*8,%1\8
F0C0 [04] 3C9E 730 inc jam_set
;naikkan jam
F0C2 [03] B69E 731 lda jam_set
;ambil
jam
F0C4 [04] 411802 732 cbeqa #!24,noljam

PAGE 17
;apakah sama
dengan 23?
F0C7 [03] 20E7 733 bra setjam0
;loop
F0C9 [01] 4F 734 noljam clra
;nolkan jam
F0CA [03] B79E 735 sta jam_set
;ambil
jam
F0CC [03] 20E2 736 bra setjam0
;loop
737
738 *=====================================*
F0CE macro 739 setmenit bitset sw01
;set
flag
F0CE [04] 12AE 740 BSET %1-(%1\8)*8,%1\8
F0D0 [05] CDF268 741 jsr clrscr
;hapus
layar lcd
F0D3 [01] 8C 742 clrh
F0D4 [01] 5F 743 clrx
;hapus
isi reg x
F0D5 [04] D6F8A2 744 bacatab12 lda Tabel12,x
;baca
tabel
F0D8 [04] 410F06 745 cbeqa #$0F,back12
;tampilkan
F0DB [05] CDF28A 746 jsr Kirim_Karakter
; set
menit
F0DE [01] 5C 747 incx
;pada
layar LCD
F0DF [03] 20F4 748 bra bacatab12
;
F0E1 [01] 5F 749 back12 clrx
750
751 setmenit0 ;jsr clrscr
F0E2 [05] CDF1CB 752 jsr setdata
;tampilkan data
setting menit
F0E5 [05] CDF789 753 scanmenit jsr SCAN_TB
;baca
tombol
F0E8 macro 754 braclr sw01,setdetik
;set
tanggal?
F0E8 [05] 03AE15 755 BRCLR %1-(%1\8)*8,%1\8,%2
F0EB macro 756 braclr sw00,setmenit1
;set menit?
F0EB [05] 01AE02 757 BRCLR %1-(%1\8)*8,%1\8,%2
F0EE [03] 20F5 758 bra scanmenit
759 *=====================================*
F0F0 macro 760 setmenit1 bitset sw00
;set
flag
F0F0 [04] 10AE 761 BSET %1-(%1\8)*8,%1\8
F0F2 [04] 3C9F 762 inc menit_set
;naikkan menit
F0F4 [03] B69F 763 lda menit_set
;ambil
menit
F0F6 [04] 413C02 764 cbeqa #!60,nolmenit
;jika sama
dengan 59
F0F9 [03] 20E7 765 bra setmenit0
;kembali
ke loop
F0FB [01] 4F 766 nolmenit clra
;nolkan menit
F0FC [03] B79F 767 sta menit_set
;ambil
F0FE [03] 20E2 768 bra setmenit0
769
770

PAGE 18
771 *=====================================*
F100 macro 772 setdetik bitset sw01
;set
flag
F100 [04] 12AE 773 BSET %1-(%1\8)*8,%1\8
F102 [05] CDF268 774 jsr clrscr
;hapus
layar lcd
F105 [01] 8C 775 clrh
F106 [01] 5F 776 clrx
;hapus
isi reg x
F107 [04] D6F8AC 777 bacatab13 lda Tabel13,x
;baca
tabel
F10A [04] 410F06 778 cbeqa #$0F,back13
;tampilkan
F10D [05] CDF28A 779 jsr Kirim_Karakter
; set
detik
F110 [01] 5C 780 incx
;pada
layar LCD
F111 [03] 20F4 781 bra bacatab13
;
F113 [01] 5F 782 back13 clrx
783
784 setdetik0 ;jsr clrscr
F114 [05] CDF1CB 785 jsr setdata
;tampilkan data
setting menit
F117 [05] CDF789 786 scandetik jsr SCAN_TB
;baca
tombol
F11A macro 787 braclr sw01,settgl
;set
tanggal?
F11A [05] 03AE15 788 BRCLR %1-(%1\8)*8,%1\8,%2
F11D macro 789 braclr sw00,setdetik1
;set menit?
F11D [05] 01AE02 790 BRCLR %1-(%1\8)*8,%1\8,%2
F120 [03] 20F5 791 bra scandetik
792 *=====================================*
F122 macro 793 setdetik1 bitset sw00
;set
flag
F122 [04] 10AE 794 BSET %1-(%1\8)*8,%1\8
F124 [04] 3CA0 795 inc detik_set
;naikkan menit
F126 [03] B6A0 796 lda detik_set
;ambil
menit
F128 [04] 413C02 797 cbeqa #!60,noldetik
;jika sama
dengan 59
F12B [03] 20E7 798 bra setdetik0
;kembali
ke loop
F12D [01] 4F 799 noldetik clra
;nolkan menit
F12E [03] B7A0 800 sta detik_set
;ambil
F130 [03] 20E2 801 bra setdetik0
802
803 *=====================================*
F132 macro 804 settgl bitset sw01
;set flag
F132 [04] 12AE 805 BSET %1-(%1\8)*8,%1\8
;hapus
layar lcd
F137 [01] 8C 807 clrh
F138 [01] 5F 808 clrx
;hapus
isi reg x

PAGE 19
F139 [04] D6F8B6 809 bacatab14 lda Tabel14,x

;baca
tabel
F13C [04] 410F06 810 cbeqa #$0F,back14
;tampilkan
; set
tanggal
F142 [01] 5C 812 incx
;pada
layar LCD
F143 [03] 20F4 813 bra bacatab14
;
F145 [01] 5F 814 back14 clrx
815 settgl0 ;jsr clrscr
F146 [05] CDF1EC 816 jsr datad1
;tampilkan data setting
tanggal
F149 [05] CDF789 817 scantgl jsr SCAN_TB
;baca tombol
F14C macro 818 braclr sw01,setbln
;set bulan?
F14C [05] 03AE16 819 BRCLR %1-(%1\8)*8,%1\8,%2
F14F macro 820 braclr sw00,settgl1
;set
tanggal?
F14F [05] 01AE02 821 BRCLR %1-(%1\8)*8,%1\8,%2
F152 [03] 20F5 822 bra scantgl
823 *=====================================*
F154 macro 824 settgl1 bitset sw00
;set flag
F154 [04] 10AE 825 BSET %1-(%1\8)*8,%1\8
F156 [04] 3CA1 826 inc tgl_set
;naikkan
tanggal
F158 [03] B6A1 827 lda tgl_set
;ambil
tanggal
F15A [04] 412002 828 cbeqa #!32,noltgl
;jika sama
dengan 31
F15D [03] 20E7 829 bra settgl0
;tidak,kembali
ke loop
F15F [02] A601 830 noltgl lda #$01
;tanggal
diisi 01
F161 [03] B7A1 831 sta tgl_set
;
F163 [03] 20E1 832 bra settgl0
;kembali
ke loop
833 *=====================================*
F165 macro 834 setbln bitset sw01
;set flag
F165 [04] 12AE 835 BSET %1-(%1\8)*8,%1\8
;hapus
layar lcd
F16A [01] 8C 837 clrh
F16B [01] 5F 838 clrx
;hapus
isi reg x
F16C [04] D6F8C2 839 bacatab15 lda Tabel15,x
;baca
tabel
F16F [04] 410F06 840 cbeqa #$0F,back15
;tampilkan
; set
bulan
F175 [01] 5C 842 incx
;pada
layar LCD
F176 [03] 20F4 843 bra bacatab15
;
F178 [01] 5F 844 back15 clrx

PAGE 20
845 setbln0 ;jsr clrscr

F179 [05] CDF1EC 846 jsr datad1
;tampilkan data
setting bulan
F17C [05] CDF789 847 scanbln jsr SCAN_TB
;baca tombol
F17F macro 848 braclr sw01,setthn
;set tahun?
F17F [05] 03AE16 849 BRCLR %1-(%1\8)*8,%1\8,%2
F182 macro 850 braclr sw00,setbln1
;tidak,set bulan?
F182 [05] 01AE02 851 BRCLR %1-(%1\8)*8,%1\8,%2
F185 [03] 20F5 852 bra scanbln
;tidak,kembali
baca tombol
853 *=====================================*
F187 macro 854 setbln1 bitset sw00
;set flag
F187 [04] 10AE 855 BSET %1-(%1\8)*8,%1\8
F189 [04] 3CA2 856 inc bulan_set
;naikkan bulan
F18B [03] B6A2 857 lda bulan_set
;ambil
bulan
F18D [04] 410D02 858 cbeqa #!13,nolbln
;jika sama
dengan 12
F190 [03] 20E7 859 bra setbln0
;tidak,kembali loop
F192 [02] A601 860 nolbln lda #$01
;bulan
diisi 01
F194 [03] B7A2 861 sta bulan_set
;
F196 [03] 20E1 862 bra setbln0
;kembali
ke loop
863 *=====================================*
F198 macro 864 setthn bitset sw01
;set flag
F198 [04] 12AE 865 BSET %1-(%1\8)*8,%1\8
F19A [05] CDF268 866 jsr clrscr
;hapus
layar lcd
F19D [01] 8C 867 clrh
F19E [01] 5F 868 clrx
;hapus
isi reg x
F19F [04] D6F8CC 869 bacatab16 lda Tabel16,x
;baca
tabel
F1A2 [04] 410F06 870 cbeqa #$0F,back16
;tampilkan
; set
tahun
F1A8 [01] 5C 872 incx
;pada
layar LCD
F1A9 [03] 20F4 873 bra bacatab16
;
F1AB [01] 5F 874 back16 clrx
875 setthn0 ;jsr clrscr
F1AC [05] CDF1EC 876 jsr datad1
;tampilkan data
setting tahun
F1AF [05] CDF789 877 scanthn jsr SCAN_TB
;baca tombol
F1B2 macro 878 braclr sw01,exitset
;keluar
setting?
F1B2 [05] 03AE15 879 BRCLR %1-(%1\8)*8,%1\8,%2
F1B5 macro 880 braclr sw00,setthn1

PAGE 21
;tidak,set tahun
F1B5 [05] 01AE02 881 BRCLR %1-(%1\8)*8,%1\8,%2
F1B8 [03] 20F5 882 bra scanthn
;tidak,kembali
baca tombol
883 *=====================================*
F1BA macro 884 setthn1 bitset sw00
;set flag
F1BA [04] 10AE 885 BSET %1-(%1\8)*8,%1\8
F1BC [04] 3CA3 886 inc tahun_set
;naikkan tahun
F1BE [03] B6A3 887 lda tahun_set
;ambil
tahun
F1C0 [04] 416402 888 cbeqa #!100,nolthn
;jika sama
dengan 99
F1C3 [03] 20E7 889 bra setthn0
;tidak,kembali loop
F1C5 [01] 4F 890 nolthn clra
;nolkan tahun
F1C6 [03] B7A3 891 sta tahun_set
;
F1C8 [03] 20E2 892 bra setthn0
;kembali
ke loop
F1CA [04] 81 893 exitset rts
894 *======================================*
895
896
897
898 *-----------------------------------------*
899 *------subrutin set data waktu------------*
900 * untuk menampilkan data jam:menit:detik *
901 * tanggal-bulan-tahun yang akan diatur *
902 *-----------------------------------------*
F1CB [02] A6C0 903 setdata lda #$C0
;mulai
baris 2
F1CD [05] CDF28E 904 jsr Kirim_Perintah
;
F1D0 [02] AE0A 905 ldx #!10
F1D2 [03] B69E 906 lda jam_set
;ambil
data jam
F1D4 [05] CDF753 907 jsr tampil1
;tampilkan ke lcd
F1D7 [02] A63A 908 lda #$3A
;karakter ':'
F1D9 [05] CDF28A 909 jsr Kirim_Karakter
;tampilkan
F1DC [03] B69F 910 lda menit_set
;ambil
data menit
F1DE [05] CDF753 911 jsr tampil1
;tampilkan ke lcd
F1E1 [02] A63A 912 lda #$3A
;karakter ':'
F1E3 [05] CDF28A 913 jsr Kirim_Karakter
;
F1E6 [03] B6A0 914 lda detik_set
;ambil
data detik
F1E8 [05] CDF753 915 jsr tampil1
;tampilkan ke lcd
F1EB [04] 81 916 rts
917
F1EC [02] A6C0 918 datad1 lda #$C0
;mulai
baris 2

PAGE 22
F1EE [05] CDF28E 919 jsr Kirim_Perintah

;
F1F1 [02] AE0A 920 ldx #!10
F1F3 [03] B6A1 921 lda tgl_set
;ambil
data
tanggal
F1F5 [05] CDF753 922 jsr tampil1
;tampilkan ke lcd
F1F8 [02] A62D 923 lda #$2D
;karakter '-'
F1FA [05] CDF28A 924 jsr Kirim_Karakter
;tampilkan ke lcd
F1FD [03] B6A2 925 lda bulan_set
;ambil
data bulan
F1FF [05] CDF753 926 jsr tampil1
;tampilkan ke lcd
F202 [02] A62D 927 lda #$2D
;karakter '-'
;
F207 [03] B6A3 929 lda tahun_set
;ambil
data tahun
F209 [05] CDF753 930 jsr tampil1
;tampilkan ke lcd
F20C [04] 81 931 rts
;kembali dari
subrutin
932
933 *===============================*
934 *====sub ambil data waktu=======*
935 *===============================*
F20D [05] CDF268 936 tampilwaktu jsr clrscr
F210 [01] 8C 937 clrh
F211 [01] 5F 938 clrx
F212 [04] D6F8D6 939 bacatab17 lda Tabel17,x
F215 [04] 410F06 940 cbeqa #$0F,time1
F21B [01] 5C 942 incx
F21C [03] 20F4 943 bra bacatab17
F21E [02] AE10 944 time1 ldx #$10
F220 [03] B6B4 945 lda jam_temp
;ambil
data jam
;tampilkan
F225 [02] A63A 947 lda #$3A
;
;
F22A [03] B6B3 949 lda menit_temp
;ambil
data menit
F22C [05] CDF753 950 jsr tampil1
;tampilkan
F22F [02] A63A 951 lda #$3A
;
;
F234 [03] B6B2 953 lda detik_temp
;ambil
detik
;tampilkan
955
F239 [02] A6C0 956 lda #$C0
F23B [05] CDF28E 957 jsr Kirim_Perintah
F23E [01] 8C 958 clrh
F23F [01] 5F 959 clrx
F240 [04] D6F8DF 960 bacatab18 lda Tabel18,x

PAGE 23
F243 [04] 410F06 961 cbeqa #$0F,time2

F249 [01] 5C 963 incx
F24A [03] 20F4 964 bra bacatab18
F24C [02] AE10 965 time2 ldx #$10
F24E [03] B6B6 966 lda tanggal_temp
F253 [02] A62D 968 lda #$2D
F255 [05] CDF28A 969 jsr Kirim_karakter
F258 [03] B6B7 970 lda bulan_temp
F25A [05] CDF753 971 jsr tampil1
F25D [02] A62D 972 lda #$2D
F25F [05] CDF28A 973 jsr Kirim_karakter
F262 [03] B6B8 974 lda tahun_temp
F267 [04] 81 976 rts
977 *=======================================*
978 * subrutin untuk menghapus layar LCD *
979 *=======================================*
F268 [02] 87 980 clrscr psha
F269 [02] A601 981 lda #$01
F26B [04] AD21 982 bsr Kirim_Perintah
F26D [05] CDF794 983 jsr delay
F270 [02] 86 984 pula
F271 [04] 81 985 rts
986 *============================*
987 *subrutin inisialisasi LCD *
988 *============================*
F272 macro 989 Init_LCD bitset RS
F272 [04] 1C01 990 BSET %1-(%1\8)*8,%1\8
F274 macro 991 bitclr Eclock
F274 [04] 1B01 992 BCLR %1-(%1\8)*8,%1\8
F276 [05] CDF794 993 jsr delay
F279 [02] A601 994 lda #$01
;2 baris
F27B [04] AD11 995 bsr Kirim_perintah
F27D [02] A638 996 lda #$38
;2 baris
F27F [04] AD0D 997 bsr Kirim_perintah
F281 [02] A60E 998 lda #$0E
F283 [04] AD09 999 bsr Kirim_Perintah
F285 [02] A606 1000 lda #$06
F287 [04] AD05 1001 bsr Kirim_Perintah
F289 [04] 81 1002 rts
1003
*=============================================*
1004 *subroutine kirim perintah
*
1005
*=============================================*
1006 Kirim_Karakter
F28A macro 1007 bitset RS
F28A [04] 1C01 1008 BSET %1-(%1\8)*8,%1\8
F28C [03] 2002 1009 bra Kirim_Datalcd
1010
1011 Kirim_Perintah
F28E macro 1012 bitclr RS
F28E [04] 1D01 1013 BCLR %1-(%1\8)*8,%1\8
1014
1015 Kirim_Datalcd
F290 macro 1016 bitset Eclock

PAGE 24
F290 [04] 1A01 1017 BSET %1-(%1\8)*8,%1\8

F292 [05] CDF76E 1018 jsr SPI
F295 macro 1019 bitclr Eclock
F295 [04] 1B01 1020 BCLR %1-(%1\8)*8,%1\8
F297 [04] 81 1021 rts
1022 *=====================================
1023 *baca data tanggal,bulan tahun
1024 *pertama mulai alat yang diukur
1025 *dinyalakan kemudian data disimpan
1026 *pada RAM RTC
1027 *=====================================
1028
F298 [02] 87 1029 toRAM psha
F299 [05] CDF6F0 1030 jsr SER_start
;mulai
komunikasi
F29C [02] A6D0 1031 lda #DS_tulis
;perintah tulis
F29E [05] CDF700 1032 jsr TXD
;kirim
perintah
F2A1 [02] 86 1033 pula
;ambil
alamat RAM
F2A2 [05] CDF700 1034 jsr TXD
;kirim
perintah
F2A5 [03] B6B6 1035 lda tanggal_temp
;ambil
data
tanggal
F2A7 [05] CDF700 1036 jsr TXD
;simpan ke RAM
F2AA [03] B6B7 1037 lda bulan_temp
;ambil
data bulan
F2AC [05] CDF700 1038 jsr TXD
;simpan ke RAM
F2AF [03] B6B8 1039 lda tahun_temp
;ambil
data tahun
F2B1 [05] CDF700 1040 jsr TXD
;simpan ke RAM
F2B4 [05] CDF6F9 1041 jsr SER_stop
;stop
komunikasi
F2B7 [04] 81 1042 rts
;kembali
dari rutin
1043
F2B8 [03] B6B6 1044 toTEMP1A lda tanggal_temp
F2BA [03] B780 1045 sta data1_mulai+0
F2BC [03] B6B7 1046 lda bulan_temp
F2BE [03] B781 1047 sta data1_mulai+1
F2C0 [03] B6B8 1048 lda tahun_temp
F2C2 [03] B782 1049 sta data1_mulai+2
F2C4 [04] 81 1050 rts
1051
F2C5 [03] B6B6 1052 toTEMP1B lda tanggal_temp
F2C7 [03] B783 1053 sta data1_akhir+0
F2C9 [03] B6B7 1054 lda bulan_temp
F2CB [03] B784 1055 sta data1_akhir+1
F2CD [03] B6B8 1056 lda tahun_temp
F2CF [03] B785 1057 sta data1_akhir+2
F2D1 [04] 81 1058 rts
1059
F2D2 [03] B6B6 1060 toTEMP2A lda tanggal_temp
F2D4 [03] B78C 1061 sta data2_mulai+0

PAGE 25
F2D6 [03] B6B7 1062 lda bulan_temp

F2D8 [03] B78D 1063 sta data2_mulai+1
F2DA [03] B6B8 1064 lda tahun_temp
F2DC [03] B78E 1065 sta data2_mulai+2
F2DE [04] 81 1066 rts
1067
F2DF [03] B6B6 1068 toTEMP2B lda tanggal_temp
F2E1 [03] B78F 1069 sta data2_akhir+0
F2E3 [03] B6B7 1070 lda bulan_temp
F2E5 [03] B790 1071 sta data2_akhir+1
F2E7 [03] B6B8 1072 lda tahun_temp
F2E9 [03] B791 1073 sta data2_akhir+2
F2EB [04] 81 1074 rts
1075
*============================================*
1076 *subrutin untuk membaca data dari memori RTC
*
1077 *data disimpan sementara pada memori
*
1078 *mikrokontroler
*
1079
*============================================*
F2EC [05] CDF6F0 1080 bacaRAM jsr SER_start
;mulai
komunikasi
F2EF [02] A6D0 1081 lda #DS_tulis
;perintah tulis
F2F1 [05] CDF700 1082 jsr TXD
;kirim
perintah
F2F4 [02] A608 1083 lda #exram1
;ambil
alamat RAM
F2F6 [05] CDF700 1084 jsr TXD
;kirim
perintah
alamat RAM
F2F9 [05] CDF6F9 1085 jsr SER_stop
;stop
komunikasi
1086
F2FC [05] CDF6F0 1087 jsr SER_start
;mulai
komunikasi
F2FF [02] A6D1 1088 lda #DS_baca
;perintah baca
F301 [05] CDF700 1089 jsr TXD
;kirim
perintah
F304 [02] 89 1090 read pshx
F305 [05] CDF722 1091 jsr RXD
;terima data
F308 [02] 88 1092 pulx
F309 [03] E780 1093 sta data1_mulai,x
;simpan
ke bufer
F30B [01] 5C 1094 incx
F30C [02] A320 1095 cpx #!32
1096 ;pshx
F30E [03] 26F4 1097 bne read
F310 [02] 89 1098 pshx
F311 [05] CDF73B 1099 jsr RXD_last
;terima data
terakhir
F314 [02] 88 1100 pulx
F315 [03] E780 1101 sta data1_mulai,x
;simpan
ke bufer
F317 [05] CDF6F9 1102 jsr SER_stop
;stop
komunikasi
F31A [04] 81 1103 rts
1104
1105 *====================================*

PAGE 26
1106 *tampilkan data mulai alat digunakan *

1107 *berupa data tanggal,bulan dan tahun *
1108 * MULAI1:XX-XX-XX *
1109 * MULAI2:XX-XX-XX *
1110 *====================================*
1111 ;untuk data alat pertama
1112
F31B [02] AE10 1113 VIEW_MULAI1 ldx #$10
F31D [03] B680 1114 lda data1_mulai+0
;ambil data
tanggal
F31F [05] CDF753 1115 jsr tampil1
;tampilkan
pada LCD
F322 [02] A62D 1116 lda #$2D
;ambil
karakter -
;tampilkan
pada LCD
F327 [03] B681 1118 lda data1_mulai+1
;ambil
data bulan
F329 [05] CDF753 1119 jsr tampil1
;tampilkan
pada LCD
F32C [02] A62D 1120 lda #$2D
;ambil
karakter -
F32E [05] CDF28A 1121 jsr Kirim_Karakter
;tampilkan
pada LCD
F331 [03] B682 1122 lda data1_mulai+2
;ambil
data tahun
F333 [05] CDF753 1123 jsr tampil1
;tampilkan
pada LCD
F336 [01] 5F 1124 clrx
F337 [01] 8C 1125 clrh
F338 [04] 81 1126 rts
;kembali dari
subrutin
1127
1128 ;untuk data alat kedua
1129
F339 [02] AE10 1130 VIEW_MULAI2 ldx #$10
F33B [03] B68C 1131 lda data2_mulai
F33D [05] CDF753 1132 jsr tampil1
;tampilkan
pada LCD
F340 [02] A62D 1133 lda #$2D
;ambil
karakter -
;tampilkan
pada LCD
1135 ;ldx #$10
F345 [03] B68D 1136 lda data2_mulai+1
;ambil
data bulan
F347 [05] CDF753 1137 jsr tampil1
;tampilkan
pada LCD
F34A [02] A62D 1138 lda #$2D
;ambil
karakter -
F34C [05] CDF28A 1139 jsr Kirim_Karakter
;tampilkan
pada LCD
1140 ;ldx #$10
F34F [03] B68E 1141 lda data2_mulai+2
;ambil
data tahun
F351 [05] CDF753 1142 jsr tampil1
;tampilkan
pada LCD
F354 [01] 8C 1143 clrh

PAGE 27
F355 [04] 81 1144 rts

;kembali dari
subrutin
1145
1146 *====================================*
1147 *tampilkan data akhir alat digunakan *
1148 *berupa data tanggal,bulan dan tahun *
1149 * AKHIR1:XX-XX-XX *
1150 * AKHIR2:XX-XX-XX *
1151 *====================================*
1152 ;untuk data alat pertama
1153
F356 [02] AE10 1154 VIEW_AKHIR1 ldx #$10
F358 [03] B683 1155 lda data1_akhir+0
;ambil data
tanggal akhir
F35A [05] CDF753 1156 jsr tampil1
;tampilkan
pada LCD
F35D [02] A62D 1157 lda #$2D
;tampilkan
karakter -
;pada
layar LCD
1159 ;ldx #$10
F362 [03] B684 1160 lda data1_akhir+1
;ambil data
bulan akhir
F364 [05] CDF753 1161 jsr tampil1
;tampilkan
pada LCD
F367 [02] A62D 1162 lda #$2D
;tampilkan
karakter -
;pada
layar LCD
F36C [03] B685 1164 lda data1_akhir+2
;ambil data
F36E [05] CDF753 1165 jsr tampil1
;tampil
F371 [01] 5F 1166 clrx
F372 [01] 8C 1167 clrh
F373 [04] 81 1168 rts
;kembali dari
subrutin
1169
F374 [02] AE10 1171 VIEW_AKHIR2 ldx #$10
F376 [03] B68F 1172 lda data2_akhir+0
;ambil data
tanggal akhir
F378 [05] CDF753 1173 jsr tampil1
;tampilkan
pada LCD
F37B [02] A62D 1174 lda #$2D
;tampilkan
karakter -
F37D [05] CDF28A 1175 jsr Kirim_Karakter
;pada
layar LCD
F380 [03] B690 1176 lda data2_akhir+1
;ambil data
bulan akhir
F382 [05] CDF753 1177 jsr tampil1
;tampilkan
pada LCD
F385 [02] A62D 1178 lda #$2D
;tampilkan
karakter -
;pada
layar LCD
F38A [03] B691 1180 lda data2_akhir+2
;ambil data

PAGE 28
;tampil
F38F [01] 5F 1182 clrx
F390 [01] 8C 1183 clrh
F391 [04] 81 1184 rts
;kembali dari
subrutin
1185
1186 *=======================================*
1187
F392 [02] AE0A 1188 VIEW_TOTAL1 ldx #!10
F394 [03] B688 1189 lda data1_total+2
;ambil data
tanggal akhir
F396 [05] CDF753 1190 jsr tampil1
;tampilkan
pada LCD
F399 [03] B687 1191 lda data1_total+1
;ambil data
bulan akhir
F39B [05] CDF753 1192 jsr tampil1
;tampilkan
pada LCD
F39E [03] B686 1193 lda data1_total+0
;ambil data
F3A0 [05] CDF753 1194 jsr tampil1
;tampil
F3A3 [01] 5F 1195 clrx
F3A4 [01] 8C 1196 clrh
F3A5 [04] 81 1197 rts
;kembali dari
subrutin
1198
F3A6 [02] AE0A 1200 VIEW_TOTAL2 ldx #!10
F3A8 [03] B694 1201 lda data2_total+2
;ambil data
tanggal akhir
F3AA [05] CDF753 1202 jsr tampil1
;tampilkan
pada LCD
F3AD [03] B693 1203 lda data2_total+1
;ambil data
bulan akhir
F3AF [05] CDF753 1204 jsr tampil1
;tampilkan
pada LCD
F3B2 [03] B692 1205 lda data2_total+0
;ambil data
F3B4 [05] CDF753 1206 jsr tampil1
;tampil
F3B7 [01] 5F 1207 clrx
F3B8 [01] 8C 1208 clrh
F3B9 [04] 81 1209 rts
;kembali dari
subrutin
1210
1211
1212 *=========================================*
F3BA [02] AE0A 1213 VIEW_LAMA1 ldx #!10
F3BC [03] B68B 1214 lda data1_jam+2
;ambil data
lama jam
F3BE [05] CDF753 1215 jsr tampil1
;tampilkan
pada LCD
F3C1 [03] B68A 1216 lda data1_jam+1
F3C3 [05] CDF753 1217 jsr tampil1
F3C6 [03] B689 1218 lda data1_jam+0
F3CB [02] A63A 1220 lda #$3A

PAGE 29
;tampilkan
karakter :
F3CD [05] CDF28A 1221 jsr Kirim_Karakter
;pada
layar LCD
F3D0 [03] B698 1222 lda data1_menit
;ambil data
lama menit
F3D2 [05] CDF753 1223 jsr tampil1
;tampilkan
pada LCD
F3D5 [02] A63A 1224 lda #$3A
;tampilkan
karakter :
F3D7 [05] CDF28A 1225 jsr Kirim_Karakter
;pada
layar LCD
F3DA [03] B699 1226 lda data1_detik
;ambil data
lama detik
F3DC [05] CDF753 1227 jsr tampil1
;tampil
F3DF [01] 5F 1228 clrx
F3E0 [01] 8C 1229 clrh
F3E1 [04] 81 1230 rts
;kembali dari
subrutin
1231
F3E2 [02] AE0A 1233 VIEW_LAMA2 ldx #!10
F3E4 [03] B697 1234 lda data2_jam+2
;ambil data
lama jam
F3E6 [05] CDF753 1235 jsr tampil1
;tampilkan
pada LCD
F3E9 [03] B696 1236 lda data2_jam+1
F3EB [05] CDF753 1237 jsr tampil1
F3EE [03] B695 1238 lda data2_jam+0
F3F0 [05] CDF753 1239 jsr tampil1
F3F3 [02] A63A 1240 lda #$3A
;tampilkan
karakter :
F3F5 [05] CDF28A 1241 jsr Kirim_Karakter
;pada
layar LCD
F3F8 [03] B69A 1242 lda data2_menit
;ambil data
lama menit
F3FA [05] CDF753 1243 jsr tampil1
;tampilkan
pada LCD
F3FD [02] A63A 1244 lda #$3A
;tampilkan
karakter :
F3FF [05] CDF28A 1245 jsr Kirim_Karakter
;pada
layar LCD
F402 [03] B69B 1246 lda data2_detik
;ambil data
lama detik
F404 [05] CDF753 1247 jsr tampil1
;tampil
F407 [01] 8C 1248 clrh
F408 [04] 81 1249 rts
;kembali dari
subrutin
1250
1251 *====================================*
F409 [03] B6BD 1252 save_JAM1 lda jam1+2
F40B [03] B78B 1253 sta data1_jam+2
F40D [03] B6BC 1254 lda jam1+1
F40F [03] B78A 1255 sta data1_jam+1
F411 [03] B6BB 1256 lda jam1+0
F413 [03] B789 1257 sta data1_jam+0
F415 [05] 4EBA98 1258 mov menit1,data1_menit

PAGE 30
F418 [05] 4EB999 1259 mov detik1,data1_detik

F41B [04] 81 1260 rts
1261
F41C [03] B6C2 1262 save_JAM2 lda jam2+2
F41E [03] B797 1263 sta data2_jam+2
F420 [03] B6C1 1264 lda jam2+1
F422 [03] B796 1265 sta data2_jam+1
F424 [03] B6C0 1266 lda jam2+0
F426 [03] B795 1267 sta data2_jam+0
F428 [05] 4EBF9A 1268 mov menit2,data2_menit
F42B [05] 4EBE9B 1269 mov detik2,data2_detik
F42E [04] 81 1270 rts
1271
1272 *=====================================*
1273 *subrutin penjumlahan data total hasil*
1274 *pengukuran lama total beban menyala *
1275 *=====================================*
F42F [03] B6BA 1276 saveTOTAL1 lda menit1
;ambil menit
F431 [03] BB9E 1277 add sisamenit1
;tambahkan dengan menit
sebelumnya
F433 [05] CDF5D1 1278 jsr bagimenit
;hasil dibagi
F436 [05] 4E9D9E 1279 mov sisamenit,sisamenit1
F439 [03] BB86 1280 add data1_total+0
;hasil bagi tambahkan
dengan jam
F43B [02] A164 1281 cmp #!100
;
F43D [03] 2404 1282 bhs nextsave1
;lebih besar sama
dengan 100
F43F [03] B786 1283 sta data1_total+0
;tidak,simpan
F441 [03] 2029 1284 bra nextsum
F443 [05] CDF5DA 1285 nextsave1 jsr bagijam
1286 ;mov sisajam,sisajam1
F446 [05] 4EA086 1287 mov
sisajam,data1_total+0
;jumlahkan hasil
F44B [02] A164 1289 cmp #!100
;bandingkan
dengan 100
F44D [03] 2404 1290 bhs nextsave2
;jika lebih besar
sama dengan
;tidak,simpan hasil
F451 [03] 2019 1292 bra nextsum
;
F456 [05] 4EA087 1294 mov
;simpan
sisa bagi
;jumlahkan hasil
F45B [02] A164 1296 cmp #!100
;bandingkan dengan
seratus
F45D [03] 2404 1297 bhs nextsave3
F461 [03] 2009 1299 bra nextsum
F463 macro 1300 nextsave3 bitset datamak
F463 [04] 149C 1301 BSET %1-(%1\8)*8,%1\8
F465 [03] 3F86 1302 clr data1_total+0
F467 [03] 3F87 1303 clr data1_total+1

PAGE 31
F469 [03] 3F88 1304 clr data1_total+2

F46B [04] 81 1305 rts
1306 *-------------------------------------------
---*
F46C [03] B686 1307 nextsum lda data1_total+0
F46E [03] BBBB 1308 add jam1+0
F470 [02] A164 1309 cmp #!100
F472 [03] 2404 1310 bhs nextsave4
F474 [03] B786 1311 sta data1_total+0
F476 [03] 2027 1312 bra nextsum1
F47B [05] 4EA086 1314 mov
F47E [03] BB87 1315 add data1_total+1
F480 [02] A164 1316 cmp #!100
;bandingkan
dengan 100
F482 [03] 2404 1317 bhs nextsave5
;jika lebih besar
sama dengan
F484 [03] B787 1318 sta data1_total+1
;tidak,simpan hasil
F486 [03] 2017 1319 bra nextsum1
;
F48B [05] 4EA087 1321 mov
;simpan
sisa bagi
F48E [03] BB88 1322 add data1_total+2
;jumlahkan hasil
F490 [02] A164 1323 cmp #!100
;bandingkan dengan
seratus
F492 [03] 2402 1324 bhs nextsave6
F494 [03] B788 1325 sta data1_total+2
F496 macro 1326 nextsave6 bitset datamak
F496 [04] 149C 1327 BSET %1-(%1\8)*8,%1\8
F498 [03] 3F86 1328 clr data1_total+0
F49A [03] 3F87 1329 clr data1_total+1
F49C [03] 3F88 1330 clr data1_total+2
F49E [04] 81 1331 rts
1332
F49F [03] B687 1333 nextsum1 lda data1_total+1
F4A1 [03] BBBC 1334 add jam1+1
F4A3 [02] A164 1335 cmp #!100
F4A5 [03] 2404 1336 bhs nextsave7
F4A7 [03] B787 1337 sta data1_total+1
F4A9 [03] 2019 1338 bra nextsum2
F4AB [05] CDF5DA 1339 nextsave7 jsr bagijam
F4AE [05] 4EA087 1340 mov
F4B1 [03] BB88 1341 add data1_total+2
F4B3 [02] A164 1342 cmp #!100
;bandingkan
dengan 100
F4B5 [03] 2404 1343 bhs nextsave8
;jika lebih besar
sama dengan
F4B7 [03] B787 1344 sta data1_total+1
;tidak,simpan hasil
F4B9 [03] 2009 1345 bra nextsum2
F4BB macro 1346 nextsave8 bitset datamak
F4BB [04] 149C 1347 BSET %1-(%1\8)*8,%1\8
F4BD [03] 3F86 1348 clr data1_total+0
F4BF [03] 3F87 1349 clr data1_total+1
F4C1 [03] 3F88 1350 clr data1_total+2
F4C3 [04] 81 1351 rts
1352

PAGE 32
F4C4 [03] B688 1353 nextsum2 lda data1_total+2

F4C6 [03] BBBD 1354 add jam1+2
F4C8 [02] A164 1355 cmp #!100
F4CA [03] 2404 1356 bhs nextsave9
F4CC [03] B788 1357 sta data1_total+2
F4CE [03] 2008 1358 bra keluarsave
F4D0 macro 1359 nextsave9 bitset datamak
F4D0 [04] 149C 1360 BSET %1-(%1\8)*8,%1\8
F4D2 [03] 3F86 1361 clr data1_total+0
F4D8 [04] 81 1364 keluarsave rts
1365
1366 *====================================*
1367 *peralatan kedua
1368
F4D9 [03] B6BF 1369 saveTOTAL2 lda menit2
;ambil menit
F4DB [03] BB9F 1370 add sisamenit2
;tambahkan dengan menit
sebelumnya
F4DD [05] CDF5D1 1371 jsr bagimenit
;hasil dibagi
F4E0 [05] 4E9D9F 1372 mov sisamenit,sisamenit2
;sisa disimpan pada
temp menit2
F4E3 [03] BB92 1373 add data2_total+0
;hasil bagi tambahkan
dengan jam
F4E5 [02] A164 1374 cmp #!100
;
F4E7 [03] 2404 1375 bhs nextsave1b
;lebih besar sama
dengan 100
F4E9 [03] B792 1376 sta data2_total+0
;tidak,simpan
F4EB [03] 2029 1377 bra nextsumb
F4ED [05] CDF5DA 1378 nextsave1b jsr bagijam
F4F0 [05] 4EA092 1379 mov
F4F3 [03] BB93 1380 add data2_total+1
;jumlahkan hasil
F4F5 [02] A164 1381 cmp #!100
;bandingkan
dengan 100
F4F7 [03] 2404 1382 bhs nextsave2b
;jika lebih besar
sama dengan
F4F9 [03] B793 1383 sta data2_total+1
;tidak,simpan hasil
F4FB [03] 2019 1384 bra nextsumb
F4FD [05] CDF5DA 1385 nextsave2b jsr bagijam
;
F500 [05] 4EA093 1386 mov
;simpan
sisa bagi
;jumlahkan hasil
F505 [02] A164 1388 cmp #!100
;bandingkan dengan
seratus
F507 [03] 2404 1389 bhs nextsave3b
F509 [03] B794 1390 sta data2_total+2
F50B [03] 2009 1391 bra nextsumb
F50D macro 1392 nextsave3b bitset datamak
F50D [04] 149C 1393 BSET %1-(%1\8)*8,%1\8
F50F [03] 3F92 1394 clr data2_total+0
F511 [03] 3F93 1395 clr data2_total+1
F513 [03] 3F94 1396 clr data2_total+2

PAGE 33
F515 [04] 81 1397 rts

1398 *-------------------------------------------
---*
F516 [03] B692 1399 nextsumb lda data2_total+0
F518 [03] BBC0 1400 add jam2+0
F51A [02] A164 1401 cmp #!100
F51C [03] 2404 1402 bhs nextsave4b
F51E [03] B792 1403 sta data2_total+0
F520 [03] 2027 1404 bra nextsum1b
F522 [05] CDF5DA 1405 nextsave4b jsr bagijam
F525 [05] 4EA092 1406 mov
F52A [02] A164 1408 cmp #!100
;bandingkan
dengan 100
;jika lebih besar
sama dengan
;tidak,simpan hasil
F530 [03] 2017 1411 bra nextsum1b
;
F535 [05] 4EA093 1413 mov
;simpan
sisa bagi
;jumlahkan hasil
F53A [02] A164 1415 cmp #!100
;bandingkan dengan
seratus
F540 macro 1418 nextsave6b bitset datamak
F540 [04] 149C 1419 BSET %1-(%1\8)*8,%1\8
F542 [03] 3F92 1420 clr data2_total+0
F544 [03] 3F93 1421 clr data2_total+1
F546 [03] 3F94 1422 clr data2_total+2
F548 [04] 81 1423 rts
1424
F549 [03] B693 1425 nextsum1b lda data2_total+1
F54B [03] BBC1 1426 add jam2+1
F54D [02] A164 1427 cmp #!100
F54F [03] 2404 1428 bhs nextsave7b
F551 [03] B793 1429 sta data2_total+1
F553 [03] 2019 1430 bra nextsum2b
F558 [05] 4EA093 1432 mov
F55B [03] BB94 1433 add data2_total+2
F55D [02] A164 1434 cmp #!100
;bandingkan
dengan 100
F55F [03] 2404 1435 bhs nextsave8b
;jika lebih besar
sama dengan
F561 [03] B793 1436 sta data2_total+1
;tidak,simpan hasil
F563 [03] 2009 1437 bra nextsum2b
F565 macro 1438 nextsave8b bitset datamak
F565 [04] 149C 1439 BSET %1-(%1\8)*8,%1\8
F567 [03] 3F92 1440 clr data2_total+0
F569 [03] 3F93 1441 clr data2_total+1
F56B [03] 3F94 1442 clr data2_total+2
F56D [04] 81 1443 rts
1444
F56E [03] B694 1445 nextsum2b lda data2_total+2

PAGE 34
F570 [03] BBC2 1446 add jam2+2

F572 [02] A164 1447 cmp #!100
F574 [03] 2404 1448 bhs nextsave9b
F576 [03] B788 1449 sta data1_total+2
F578 [03] 2008 1450 bra keluarsaveb
F57A macro 1451 nextsave9b bitset datamak
F57A [04] 149C 1452 BSET %1-(%1\8)*8,%1\8
F57C [03] 3F92 1453 clr data2_total+0
F57E [03] 3F93 1454 clr data2_total+1
F580 [03] 3F94 1455 clr data2_total+2
F582 [04] 81 1456 keluarsaveb rts
1457 *=====================================*
1458
F583 [02] AE0A 1459 view_JAM1 ldx #!10
F585 [03] B6BD 1460 lda jam1+2
F587 [05] CDF753 1461 jsr tampil1
F58A [03] B6BC 1462 lda jam1+1
F58F [03] B6BB 1464 lda jam1+0
F591 [05] CDF753 1465 jsr tampil1
F594 [02] A63A 1466 lda #$3A
F599 [03] B6BA 1468 lda menit1
F59B [05] CDF753 1469 jsr tampil1
F59E [02] A63A 1470 lda #$3A
F5A3 [03] B6B9 1472 lda detik1
F5A5 [05] CDF753 1473 jsr tampil1
F5A8 [01] 5F 1474 clrx
F5A9 [04] 81 1475 rts
1476
F5AA [02] AE0A 1477 view_JAM2 ldx #!10
F5AC [03] B6C2 1478 lda jam2+2
F5AE [05] CDF753 1479 jsr tampil1
F5B1 [03] B6C1 1480 lda jam2+1
F5B6 [03] B6C0 1482 lda jam2+0
F5BB [02] A63A 1484 lda #$3A
F5BD [05] CDF28A 1485 jsr Kirim_Karakter
F5C0 [03] B6BF 1486 lda menit2
F5C5 [02] A63A 1488 lda #$3A
F5C7 [05] CDF28A 1489 jsr Kirim_Karakter
F5CA [03] B6BE 1490 lda detik2
F5CC [05] CDF753 1491 jsr tampil1
F5CF [01] 5F 1492 clrx
F5D0 [04] 81 1493 rts
1494
F5D1 [01] 8C 1495 bagimenit clrh
F5D2 [03] 3F9D 1496 clr sisamenit
F5D4 [02] AE3C 1497 ldx #!60
F5D6 [07] 52 1498 div
F5D7 [04] 359D 1499 sthx sisamenit
F5D9 [04] 81 1500 rts
1501
F5DA [01] 8C 1502 bagijam clrh
F5DB [03] 3FA0 1503 clr sisajam

PAGE 35
F5DD [02] AE64 1504 ldx #!100

F5DF [07] 52 1505 div
F5E0 [04] 35A0 1506 sthx sisajam
F5E2 [04] 81 1507 rts
1508 *====================================*
1509 *subrutin untuk menghapus isi RAM RTC*
1510 *====================================*
F5E3 [05] CDF6F0 1511 resetRAM jsr SER_start
;mulai
komunikasi
F5E6 [02] A6D0 1512 lda #DS_tulis
;perintah tulis
F5E8 [05] CDF700 1513 jsr TXD
;kirim
perintah
F5EB [02] A608 1514 lda #exram1
;ambil
alamat RAM
F5ED [05] CDF700 1515 jsr TXD
;kirim alamat
F5F0 [02] AE37 1516 ldx #!55
;counter RAM
F5F2 [01] 4F 1517 clear clra
;hapus
accumulator
F5F3 [02] 89 1518 pshx
;simpan isi reg x
pada stack
F5F4 [05] CDF700 1519 jsr TXD
;kosongkan RAM
F5F7 [02] 88 1520 pulx
;ambil
isi reg x
F5F8 [03] 5BF8 1521 dbnzx clear
;kurangi
isi reg x
F5FA [05] CDF6F9 1522 jsr SER_stop
; apakah
reg x = 0?
F5FD [01] 8C 1523 clrh
;
tidak, kembali
ke loop
F5FE [05] CDF268 1524 jsr clrscr
; ya,stop
komunikasi
F601 [04] D6F869 1525 ulang8 lda Tabel8,x
;tampilkan
karakter
F604 [04] 410F06 1526 cbeqa #$0F,lagi8
; RAM
TERHAPUS
; pada
layar LCD
F60A [01] 5C 1528 incx
F60B [03] 20F4 1529 bra ulang8
F60D [01] 5F 1530 lagi8 clrx
F60E [04] 81 1531 rts
1532
;kembali dari
subrutin
1533 *=================================*
1534 *subrutin untuk menyimpan data *
1535 *ke memori RTC *
1536 *data yang disimpan meliputi data *
1537 *=================================*
F60F [05] CDF6F0 1538 toRTC jsr SER_start
;mulai
komunikasi
F612 [02] A6D0 1539 lda #DS_tulis
;perintah tulis
F614 [05] CDF700 1540 jsr TXD
;kirim
perintah

PAGE 36
F617 [02] A607 1541 lda #control

;ambil
alamat
F619 [05] CDF700 1542 jsr TXD
;
register
kontrol RTC
F61C [02] A610 1543 lda #$10
;
aktifkan
clock 1 Hz
F61E [05] CDF700 1544 jsr TXD
;
kirim ke register
kontrol
;stop
komunikasi
1546 ;rts
1547 *=======================================*
1548
;mulai
komunikasi
F627 [02] A6D0 1550 lda #DS_tulis
;perintah tulis
F629 [05] CDF700 1551 jsr TXD
;kirim
perintah
F62C [02] A600 1552 lda #detik
;alamat menit
F62E [05] CDF700 1553 jsr TXD
;kirim
alamat
F631 [03] B6A0 1554 lda detik_set
;ambil
seting menit
F633 [05] CDF764 1555 jsr convH_B
;konversi dalam
bentuk BCD
F636 [05] CDF700 1556 jsr TXD
;kirim
ke
alamat menit
F639 [03] B69F 1557 lda menit_set
;ambil
seting menit
F63B [05] CDF764 1558 jsr convH_B
;konversi dalam
bentuk BCD
F63E [05] CDF700 1559 jsr TXD
;kirim
ke
alamat menit
F641 [03] B69E 1560 lda jam_set
;ambil
seting jam
F643 [05] CDF764 1561 jsr convH_B
;konversi dalam
bentuk BCD
F646 [05] CDF700 1562 jsr TXD
;kirim ke
alamat jam
F649 [03] B6B5 1563 lda hari_temp
;ambil
seting hari
F64B [05] CDF700 1564 jsr TXD
;kirim ke
alamat hari
F64E [03] B6A1 1565 lda tgl_set
;a
F650 [05] CDF764 1566 jsr convH_B
F653 [05] CDF700 1567 jsr TXD
F656 [03] B6A2 1568 lda bulan_set
F658 [02] 72 1569 daa
F659 [05] CDF700 1570 jsr TXD
F65C [03] B6A3 1571 lda tahun_set
F65E [05] CDF764 1572 jsr convH_B
F661 [05] CDF700 1573 jsr TXD
F667 [04] 81 1575 rts
1576

PAGE 37
1577 *======================================*
1578 *subrutin untuk disable sinyal 1 Hz
1579 *dari RTC
1580 *======================================*
F668 [05] CDF6F0 1581 WAVE_OFF jsr SER_start
;mulai
komunikasi
F66B [02] A6D0 1582 lda #DS_tulis
;perintah tulis
F66D [05] CDF700 1583 jsr TXD
;kirim
perintah
F670 [02] A607 1584 lda #control
;alamat register
kontrol
F672 [05] CDF700 1585 jsr TXD
;kirim alamat
F675 [02] A600 1586 lda #$00
;disable
sinyal 1 Hz
F677 [05] CDF700 1587 jsr TXD
;kirim
perintah
F67A [05] CDF6F9 1588 jsr SER_stop
;stop
komunikasi
F67D [04] 81 1589 rts
;kembali dari
subrutin
1590
1591
F67E [05] CDF6F0 1592 WAVE_ON jsr SER_start
;mulai
komunikasi
F681 [02] A6D0 1593 lda #DS_tulis
;perintah tulis
F683 [05] CDF700 1594 jsr TXD
;kirim
perintah
F686 [02] A607 1595 lda #control
;alamat register
kontrol
F688 [05] CDF700 1596 jsr TXD
;kirim alamat
F68B [02] A610 1597 lda #$10
;disable
sinyal 1 Hz
F68D [05] CDF700 1598 jsr TXD
;kirim
perintah
;stop
komunikasi
F693 [04] 81 1600 rts
;kembali dari
subrutin
1601 *==========================================
1602 *subrutin untuk menyimpan data keseluruhan
1603 *dari hasil pengukuran
1604 *==========================================
F694 [01] 5F 1605 savetoRTC clrx
F698 [02] A6D0 1607 lda #DS_tulis
F69A [05] CDF700 1608 jsr TXD
F69D [02] A608 1609 lda #exram1
F69F [05] CDF700 1610 jsr TXD
F6A2 [03] E680 1611 savelagi lda data1_mulai,x
F6A4 [02] 89 1612 pshx
F6A5 [05] CDF700 1613 jsr TXD
F6A8 [02] 88 1614 pulx
F6A9 [01] 5C 1615 incx
F6AA [02] A320 1616 cpx #!32

PAGE 38
F6AC [03] 26F4 1617 bne savelagi
F6AE [05] CDF6F9 1618 jsr SER_stop
F6B1 [04] 81 1619 rts
1620
1621
1622 *==========================================*
1623 * baca data waktu simpan pada bufer
1624 * ditampilkan apabila masuk ke menu untuk
1625 * menampilkan informasi waktu
1626
1627 *==========================================*
F6B2 [01] 5F 1628 datawaktu clrx
F6B3 [01] 8C 1629 clrh
F6B4 [04] AD3A 1630 bsr SER_start
1631
F6B6 [02] A6D0 1632 lda #DS_tulis
F6B8 [05] CDF700 1633 jsr TXD
F6BB [02] A600 1634 lda #detik
F6BD [05] CDF700 1635 jsr TXD
F6C0 [04] AD37 1636 bsr SER_stop
F6C2 [01] 9D 1637 nop
1638
1639 * baca data dari RTC
F6C3 [04] AD2B 1640 bsr SER_start
F6C5 [02] A6D1 1641 lda #DS_baca
;panggil alamat
DS_baca
F6C7 [05] CDF700 1642 jsr TXD
F6CA [05] CDF722 1643 jsr RXD
F6CD [03] B7B2 1644 sta detik_temp
F6CF [05] CDF722 1645 jsr RXD
F6D2 [03] B7B3 1646 sta menit_temp
F6D4 [05] CDF722 1647 jsr RXD
F6D7 [03] B7B4 1648 sta jam_temp
F6D9 [05] CDF722 1649 jsr RXD
F6DC [03] B7B5 1650 sta hari_temp
F6DE [05] CDF722 1651 jsr RXD
F6E1 [03] B7B6 1652 sta tanggal_temp
F6E3 [05] CDF722 1653 jsr RXD
F6E6 [03] B7B7 1654 sta bulan_temp
F6E8 [05] CDF73B 1655 jsr RXD_last
F6EB [03] B7B8 1656 sta tahun_temp
F6ED [04] AD0A 1657 bsr SER_stop
F6EF [04] 81 1658 rts
1659
1660
1661
*===============================================*
1662 *sub
*
1663
*===============================================*
F6F0 macro 1664 SER_start bitset SCL
F6F0 [04] 1201 1665 BSET %1-(%1\8)*8,%1\8
F6F2 macro 1666 bitset SDA
F6F2 [04] 1001 1667 BSET %1-(%1\8)*8,%1\8
F6F4 macro 1668 bitclr SDA
F6F4 [04] 1101 1669 BCLR %1-(%1\8)*8,%1\8
F6F6 macro 1670 bitclr SCL
F6F6 [04] 1301 1671 BCLR %1-(%1\8)*8,%1\8
F6F8 [04] 81 1672 rts
1673

PAGE 39
F6F9 macro 1674 SER_stop bitset SCL

F6F9 [04] 1201 1675 BSET %1-(%1\8)*8,%1\8
F6FB macro 1676 bitclr SDA
F6FB [04] 1101 1677 BCLR %1-(%1\8)*8,%1\8
F6FD macro 1678 bitset SDA
F6FD [04] 1001 1679 BSET %1-(%1\8)*8,%1\8
F6FF [04] 81 1680 rts
1681
*===============================================*
F700 [02] AE08 1682 TXD ldx #!8
;counter 8
1683
F702 [01] 48 1684 TULIS asla
F703 [03] 2404 1685 bcc lom1
F705 macro 1686 bitset SDA
;SDA=1
F705 [04] 1001 1687 BSET %1-(%1\8)*8,%1\8
F707 [03] 2004 1688 bra lom2
F709 macro 1689 lom1 bitclr SDA
;SDA=0
F709 [04] 1101 1690 BCLR %1-(%1\8)*8,%1\8
F70B [01] 9D 1691 nop
F70C [01] 9D 1692 nop
1693
1694
F70D macro 1695 lom2 bitset SCL
F70D [04] 1201 1696 BSET %1-(%1\8)*8,%1\8
F70F macro 1697 bitclr SCL
F70F [04] 1301 1698 BCLR %1-(%1\8)*8,%1\8
F711 [01] 5A 1699 decx
F712 [03] 26EE 1700 bne TULIS
1701 *cek ACK
F714 macro 1702 bitclr ambil_data
F714 [04] 1105 1703 BCLR %1-(%1\8)*8,%1\8
F716 macro 1704 bitset SCL
F716 [04] 1201 1705 BSET %1-(%1\8)*8,%1\8
F718 macro 1706 braclr SDA,lom3
F718 [05] 010102 1707 BRCLR %1-(%1\8)*8,%1\8,%2
1708
1709
F71B [03] 2000 1710 ACK_ERROR bra lom3
1711
F71D macro 1712 lom3 bitclr SCL
F71D [04] 1301 1713 BCLR %1-(%1\8)*8,%1\8
F71F macro 1714 bitset ambil_data
;output data
F71F [04] 1005 1715 BSET %1-(%1\8)*8,%1\8
F721 [04] 81 1716 rts
1717
1718
1719
*=============================================*
1720 **routine untuk membaca data dari RTC
1721
*=============================================*
F722 macro 1722 RXD bitclr ambil_data
;baca
data
dari RTC
F722 [04] 1105 1723 BCLR %1-(%1\8)*8,%1\8
F724 [02] AE08 1724 ldx #!8
F726 [01] 4F 1725 clra
F727 macro 1726 BACA bitset SCL
;SCL=1
F727 [04] 1201 1727 BSET %1-(%1\8)*8,%1\8

PAGE 40

;carry
bit = SDA
F729 [05] 010100 1729 BRCLR %1-(%1\8)*8,%1\8,%2
F72C [01] 49 1730 lom4 rola
;simpan carry bit ke
msb Acc
F72D macro 1731 bitclr SCL
;SCL=0
F72D [04] 1301 1732 BCLR %1-(%1\8)*8,%1\8
F72F [01] 5A 1733 decx
F730 [03] 26F5 1734 bne BACA
1735
1736 *ACK ke slave
F732 macro 1737 bitset ambil_data
;portA3
sebagai output
F732 [04] 1005 1738 BSET %1-(%1\8)*8,%1\8
F734 macro 1739 bitclr SDA
F734 [04] 1101 1740 BCLR %1-(%1\8)*8,%1\8
F736 macro 1741 bitset SCL
F736 [04] 1201 1742 BSET %1-(%1\8)*8,%1\8
F738 macro 1743 bitclr SCL
F738 [04] 1301 1744 BCLR %1-(%1\8)*8,%1\8
F73A [04] 81 1745 rts
1746
1747
***********************************************
F73B macro 1748 RXD_last bitclr ambil_data
;baca
data
dari RTC
F73B [04] 1105 1749 BCLR %1-(%1\8)*8,%1\8
F73D [02] AE08 1750 ldx #!8
1751
F73F macro 1752 BACA_last bitset SCL
;SCL=1
F73F [04] 1201 1753 BSET %1-(%1\8)*8,%1\8
;carry
bit = SDA
F741 [05] 010100 1755 BRCLR %1-(%1\8)*8,%1\8,%2
F744 [01] 49 1756 lom5 rola
;simpan carry bit ke
msb Acc
;SCL=0
F745 [04] 1301 1758 BCLR %1-(%1\8)*8,%1\8
F747 [01] 5A 1759 decx
F748 [03] 26F5 1760 bne BACA_last
1761
1762 *tanpa ACK ke slave
F74A macro 1763 bitset ambil_data
;portA3
sebagai output
F74A [04] 1005 1764 BSET %1-(%1\8)*8,%1\8
F74C macro 1765 bitset SDA
F74C [04] 1001 1766 BSET %1-(%1\8)*8,%1\8
F74E macro 1767 bitset SCL
F74E [04] 1201 1768 BSET %1-(%1\8)*8,%1\8
F750 [04] 1301 1770 BCLR %1-(%1\8)*8,%1\8
F752 [04] 81 1771 rts
1772
1773
1774 *===================================*
1775 *subroutin hek ke ASCII *
1776 *===================================*

PAGE 41
F753 [01] 8C 1777 tampil1 clrh

;kosongkan
reg h:x
1778 ;clrx
;
1779 ;ldx #$10
;
F754 [07] 52 1780 tampil3 div
;detik
dibagi 10
F755 [04] 35B0 1781 sthx sisa
;simpan satuan
ke stack
F757 [02] AB30 1782 add #$30
;tambah
30 heksa
F75C [03] B6B0 1784 lda sisa
F75E [02] AB30 1785 add #$30
;ambil
satuan
F760 [05] CDF28A 1786 jsr Kirim_karakter
;
F763 [04] 81 1787 rts
1788
F764 [01] 8C 1789 convH_B clrh
F765 [02] AE0A 1790 ldx #!10
F767 [07] 52 1791 div
F768 [03] 62 1792 nsa
F769 [04] 35AB 1793 sthx regdata
F76B [03] BAAB 1794 ora regdata
F76D [04] 81 1795 rts
1796
*==============================================*
1797 *Sub Rutin Untuk SPI serial_in/paralel_out
*
1798
*==============================================*
F76E [04] 6E08AD 1799 SPI mov #!8,Data_Serial
;Banyaknya
bit data
F771 macro 1800 bitclr Sclk_SPI
;Matikan shift clock
untuk SPI
F771 [04] 1701 1801 BCLR %1-(%1\8)*8,%1\8
F773 [01] 48 1802 Shift_Seri lsla
;Data
digeser kekiri
F774 [03] 2504 1803 bcs SPI_set
;Bila carry set ke
SPI_set
F776 macro 1804 bitclr Data_SPI
F776 [04] 1901 1805 BCLR %1-(%1\8)*8,%1\8
F778 [03] 2002 1806 bra SPI2
F77A macro 1807 SPI_set bitset Data_SPI
F77A [04] 1801 1808 BSET %1-(%1\8)*8,%1\8
1809
F77C macro 1810 SPI2 bitset Sclk_SPI
;Hidupkan
shift clock
F77C [04] 1601 1811 BSET %1-(%1\8)*8,%1\8
F77E macro 1812 bitclr Sclk_SPI
;Matikan
shift clock
F77E [04] 1701 1813 BCLR %1-(%1\8)*8,%1\8
F780 [05] 3BADF0 1814 dbnz
Data_Serial,Shift_Seri
F783 macro 1815 bitset Lclk_SPI
;keluarkan data
F783 [04] 1401 1816 BSET %1-(%1\8)*8,%1\8
F785 [01] 9D 1817 nop
;Berhenti sebentar baru
lanjutkan
F786 macro 1818 bitclr Lclk_SPI
;Matikan
sinyal latch
F786 [04] 1501 1819 BCLR %1-(%1\8)*8,%1\8

PAGE 42
F788 [04] 81 1820 rts

1821
1822
F789 [05] 4E00AE 1823 SCAN_TB mov PortA,switch
F78C [04] 6EFFA9 1824 delay1 mov #!255,waktu
;4 siklus
F78F [04] AD06 1825 bsr balikONE
;4 x 255 x 255
= 260100
F791 [04] AD01 1826 bsr delay
;total = 260104x0.3125uS =
81.2825 mS
F793 [04] 81 1827 rts
;81.2825 mS + 22.45 ms = 103.7325 mS
~ 0.1 S
1828
1829
1830 ;-------------------------------------------
--------
-----
1831 ;delay ~ 22 mS
1832 ;-------------------------------------------
--------
-----
1833
F794 [04] 6E28A9 1834 delay mov #!40,waktu
;
4 siklus
F797 [04] 6EFFAA 1835 balikONE mov #$FF,count
; 4 x
40 =160
F79A [04] 3AAA 1836 balikTWO dec count
; 4 x 255 x 40
= 40800
F79C [03] 26FC 1837 bne balikTWO
; 3 x 255 x 40
= 30600
F79E [04] 3AA9 1838 dec waktu
; 4 x
40 = 160
F7A0 [03] 26F5 1839 bne balikONE
; 3 x
40 = 120
F7A2 [04] 81 1840 rts
; 4 -->total =71848x0.3125uS=
22.45 mS
1841
F7A3 [07] 80 1842 keyboard rti
1843
1844
1845
F7A4 [07] 80 1846 TIM_over rti
1847
1848
*===========================================*
1849 *subrutin interupsi eksternal yang terjadi
1850 *tiap satu detik jika alat dinyalakan atau
1851 *jika sedang menampilkan menu jam
1852 *==========================================*
F7A5 macro 1853 IRQ bitset ACK
F7A5 [04] 141D 1854 BSET %1-(%1\8)*8,%1\8
F7A7 macro 1855 bitset IRQ_flag
F7A7 [04] 10A7 1856 BSET %1-(%1\8)*8,%1\8
F7A9 macro 1857 braset timedelay,saveall
F7A9 [05] 0AA70E 1858 BRSET %1-(%1\8)*8,%1\8,%2
F7AC macro 1859 braclr sw11,task1
F7AC [05] 01AF03 1860 BRCLR %1-(%1\8)*8,%1\8,%2
F7AF [05] CDF7C7 1861 jsr taskdev1
F7B2 macro 1862 task1 braclr sw12,outIRQ
F7B2 [05] 03AF11 1863 BRCLR %1-(%1\8)*8,%1\8,%2
F7B5 [05] CDF7FA 1864 jsr taskdev2

PAGE 43
F7B8 [03] 200C 1865 bra outIRQ

F7BA [04] 3CA8 1866 saveall inc countsave
F7BC [03] B6A8 1867 lda countsave
F7BE [02] A104 1868 cmp #!4
F7C0 [03] 2604 1869 bne outIRQ
F7C2 [03] 3FA8 1870 clr countsave
F7C4 macro 1871 bitclr timedelay
F7C4 [04] 1BA7 1872 BCLR %1-(%1\8)*8,%1\8
F7C6 [07] 80 1873 outIRQ rti
1874
1875
1876
**********************************************
F7C7 [04] 3CB9 1877 taskdev1 inc detik1
F7C9 [03] B6B9 1878 lda detik1
F7CB [02] A13C 1879 cmp #!60
F7CD [03] 262A 1880 bne outtask1
F7CF [03] 3FB9 1881 clr detik1
F7D1 [04] 3CBA 1882 inc menit1
F7D3 [03] B6BA 1883 lda menit1
F7D5 [02] A13C 1884 cmp #!60
F7D7 [03] 2620 1885 bne outtask1
F7D9 [03] 3FBA 1886 clr menit1
F7DB [04] 3CBB 1887 inc jam1+0
F7DD [03] B6BB 1888 lda jam1+0
F7DF [02] A164 1889 cmp #!100
F7E1 [03] 2616 1890 bne outtask1
F7E3 [03] 3FBB 1891 clr jam1+0
F7E5 [04] 3CBC 1892 inc jam1+1
F7E7 [03] B6BC 1893 lda jam1+1
F7E9 [02] A164 1894 cmp #!100
F7EB [03] 260C 1895 bne outtask1
F7ED [03] 3FBC 1896 clr jam1+1
F7EF [04] 3CBD 1897 inc jam1+2
F7F1 [03] B6BD 1898 lda jam1+2
F7F3 [02] A164 1899 cmp #!100
F7F5 [03] 2602 1900 bne outtask1
F7F7 [03] 3FBD 1901 clr jam1+2
F7F9 [04] 81 1902 outtask1 rts
1903
1904
************************************************
1905
F7FA [04] 3CBE 1906 taskdev2 inc detik2
F7FC [03] B6BE 1907 lda detik2
F7FE [02] A13C 1908 cmp #!60
F800 [03] 262A 1909 bne outtask2
F802 [03] 3FBE 1910 clr detik2
F804 [04] 3CBF 1911 inc menit2
F806 [03] B6BF 1912 lda menit2
F808 [02] A13C 1913 cmp #!60
F80A [03] 2620 1914 bne outtask2
F80C [03] 3FBF 1915 clr menit2
F80E [04] 3CC0 1916 inc jam2+0
F810 [03] B6C0 1917 lda jam2+0
F812 [02] A164 1918 cmp #!100
F814 [03] 2616 1919 bne outtask2
F816 [03] 3FC0 1920 clr jam2+0
F818 [04] 3CC1 1921 inc jam2+1
F81A [03] B6C1 1922 lda jam2+1

PAGE 44
F81C [02] A164 1923 cmp #!100

F81E [03] 260C 1924 bne outtask2
F820 [03] 3FC1 1925 clr jam2+1
F822 [04] 3CC2 1926 inc jam2+2
F824 [03] B6C2 1927 lda jam2+2
F826 [02] A164 1928 cmp #!100
F828 [03] 2602 1929 bne outtask2
F82A [03] 3FC2 1930 clr jam2+2
F82C [04] 81 1931 outtask2 rts
1932
1933
F82D 50454E47 1934 Tabel1 fcb 'PENGATURAN
?',$0F
41545552
414E203F
0F
F83A 4D554C41 1935 Tabel2 fcb 'MULAI',$0F
490F
F840 414B4849 1936 Tabel3 fcb 'AKHIR',$0F
520F
F846 4C414D41 1937 Tabel4 fcb 'LAMA',$0F
0F
F84B 544F5441 1938 Tabel5 fcb 'TOTAL',$0F
4C0F
F851 52455345 1939 Tabel6 fcb 'RESET ?',$0F
54203F0F
F859 53494D50 1940 Tabel7 fcb 'SIMPAN
SETTING?',$0F
414E2053
45545449
4E473F0F
F869 52414D20 1941 Tabel8 fcb 'RAM
TERHAPUS',$0F
54455248
41505553
0F
1942 ; ‘0123456789ABDEF’
F876 20202020 1943 Tabel9 fcb ' ALAT 1 ON
',$0F
414C4154
2031204F
4E202020
200F
F888 20202020 1944 Tabel10 fcb ' ALAT 2 ON
',$0F
414C4154
2032204F
4E202020
200F
F89A 73657420 1945 Tabel11 fcb 'set jam',$0F
6A616D0F
F8A2 73657420 1946 Tabel12 fcb 'set menit',$0F
6D656E69
740F
F8AC 73657420 1947 Tabel13 fcb 'set detik',$0F
64657469
6B0F
F8B6 73657420 1948 Tabel14 fcb 'set tanggal',$0F
74616E67
67616C0F
F8C2 73657420 1949 Tabel15 fcb 'set bulan',$0F
62756C61
6E0F

PAGE 45
F8CC 73657420 1950 Tabel16 fcb 'set tahun',$0F

74616875
6E0F
F8D6 484F5552 1951 Tabel17 fcb 'HOUR ',$0F
20202020
0F
F8DF 4D455445 1952 Tabel18 fcb 'METER ',$0F
52202020
0F
1953
1954
FFE0 1955 org $FFE0
FFE0 F7A3 1956 fdb keyboard
FFF2 1957 org $FFF2
FFF2 F7A4 1958 fdb TIM_over
FFFA 1959 org $FFFA
FFFA F7A5 1960 fdb IRQ
FFFE 1961 org $FFFE
FFFE EE00 1962 fdb RESET
1963
Symbol Table
ACK 00EA
ACKK 00D2
ACK_ERROR F71B
AMBIL_DATA 0028
ATUR 00AC
ATURJAM 0560
BACA F727
BACARAM F2EC
BACATAB EF05
BACATAB10 EEBE
BACATAB11 F0A3
BACATAB12 F0D5
BACATAB13 F107
BACATAB14 F139
BACATAB15 F16C
BACATAB16 F19F
BACATAB17 F212
BACATAB18 F240
BACATAB2 EF4B
BACATAB3 EF8F
BACATAB4 EFD3
BACATAB4B EFFC
BACATAB5 F025
BACATAB6 F069
BACATAB7 EF27
BACATAB70 EF22
BACATAB9 EE72
BACA_LAST F73F
BACK0 EE7E
BACK1 EE7F
BACK11 F0AF
BACK12 F0E1
BACK13 F113
BACK14 F145
BACK15 F178

PAGE 46
BACK16 F1AB
BACK2 EECA
BACK3 EECB
BAGIJAM F5DA
BAGIMENIT F5D1
BALIKONE F797
BALIKTWO F79A
BULAN 0005
BULAND1 00A5
BULAN_SET 00A2
BULAN_TEMP 00B7
CLEAR F5F2
CLRSCR F268
CONFIG1 001F
CONFIG2 001E
CONTROL 0007
CONVH_B F764
COUNT 00AA
COUNTSAVE 00A8
DATA1_AKHIR 0083
DATA1_DETIK 0099
DATA1_JAM 0089
DATA1_MENIT 0098
DATA1_MULAI 0080
DATA1_TOTAL 0086
DATA2_AKHIR 008F
DATA2_DETIK 009B
DATA2_JAM 0095
DATA2_MENIT 009A
DATA2_MULAI 008C
DATA2_TOTAL 0092
DATAD1 F1EC
DATAMAK 04E2
DATAWAKTU F6B2
DATA_SERIAL 00AD
DATA_SPI 000C
DDRA 0004
DDRA0 0020
DDRA1 0021
DDRA2 0022
DDRA3 0023
DDRA4 0024
DDRA5 0025
DDRB 0005
DDRB1 0029
DDRB2 002A
DDRB3 002B
DDRB4 002C
DDRB5 002D
DDRB6 002E
DDRB7 002F
DELAY F794
DELAY1 F78C
DETIK 0000
DETIK1 00B9
DETIK2 00BE
DETIK_SET 00A0
DETIK_TEMP 00B2

PAGE 47
DEV1_ON EE59
DEV1_ON0 EE6C
DEV2_ON EEA5
DEV2_ON0 EEB8
DS_BACA 00D1
DS_TULIS 00D0
ECGON 01B1
ECGST 01B0
ECLOCK 000D
EXITSET F1CA
EXRAM1 0008
EXRAM2 000B
EXRAM3 000E
EXRAM4 0011
EXRAM5 0014
EXRAM6 0017
EXRAM7 001A
EXRAM8 001D
EXRAM9 0020
FLAG 00A7
F_TABEL 053A
HAPUS EE06
HARI 0003
HARI_TEMP 00B5
IMASKK 00D1
INIT_LCD F272
IRQ F7A5
IRQEN 00F6
IRQ_FLAG 0538
ISCR 001D
JAM 0002
JAM1 00BB
JAM2 00C0
JAM_SET 009E
JAM_TEMP 00B4
JPMENU1 EE53
KBIE0 00D8
KBIE1 00D9
KBIE2 00DA
KBIE3 00DB
KBIE4 00DC
KBIE5 00DD
KBIER 001B
KBSCR 001A
KELUARSAVE F4D8
KELUARSAVEB F582
KEY 009C
KEY1 053B
KEY2 053C
KEYBOARD F7A3
KIRIM_DATALCD F290
KIRIM_KARAKTER F28A
KIRIM_PERINTAH F28E
LAGI EF11
LAGI2 EF57
LAGI2A EF62
LAGI2B EF7A
LAGI3 EF9B

PAGE 48
LAGI3A EFA6
LAGI3B EFBE
LAGI4 EFDF
LAGI4B F008
LAGI5 F031
LAGI5A F03C
LAGI5B F054
LAGI6 F075
LAGI7 EF33
LAGI8 F60D
LCLK_SPI 000A
LL F086
LOM1 F709
LOM2 F70D
LOM3 F71D
LOM4 F72C
LOM5 F744
LOOK_TB EE48
LOOPING1 EEA0
LOOPING1B EEEC
MAIN EE4B
MAIN0 EE4E
MAIN1 EE35
MAINLOOP EE3B
MENIT 0001
MENIT1 00BA
MENIT2 00BF
MENIT_SET 009F
MENIT_TEMP 00B3
MENU1 EEFB
MENU2 EF44
MENU20 EF46
MENU2A EF80
MENU3 EF88
MENU30 EFC4
MENU4 EFCC
MENU40 EFED
MENU40B F016
MENU4B EFF5
MENU5 F01E
MENU50 F05A
MENU6 F062
MENU60 F076
MENU7 F08C
MENU7A F094
NEXTSAVE1 F443
NEXTSAVE1B F4ED
NEXTSAVE2 F453
NEXTSAVE2B F4FD
NEXTSAVE3 F463
NEXTSAVE3B F50D
NEXTSAVE4 F478
NEXTSAVE4B F522
NEXTSAVE5 F488
NEXTSAVE5B F532
NEXTSAVE6 F496
NEXTSAVE6B F540
NEXTSAVE7 F4AB

PAGE 49
NEXTSAVE7B F555
NEXTSAVE8 F4BB
NEXTSAVE8B F565
NEXTSAVE9 F4D0
NEXTSAVE9B F57A
NEXTSUM F46C
NEXTSUM1 F49F
NEXTSUM1B F549
NEXTSUM2 F4C4
NEXTSUM2B F56E
NEXTSUMB F516
NOLBLN F192
NOLDETIK F12D
NOLJAM F0C9
NOLMENIT F0FB
NOLTGL F15F
NOLTHN F1C5
OSC1 00F3
OSCSTAT 0036
OUTIRQ F7C6
OUTTASK1 F7F9
OUTTASK2 F82C
PORTA 0000
PORTB 0001
PTA0 0000
PTA1 0001
PTA2 0002
PTA3 0003
PTA4 0004
PTA5 0005
PTB7 000F
PTBPUE 000C
RAM 009E
READ F304
REGDATA 00AB
RESET EE00
RESETMAK EE56
RESETMAKRAM F064
RESETRAM F5E3
ROM EE00
RS 000E
RST F081
RXD F722
RXD_LAST F73B
SAVEALL F7BA
SAVEKEY1 04E0
SAVEKEY2 04E1
SAVELAGI F6A2
SAVETORTC F694
SAVETOTAL1 F42F
SAVETOTAL2 F4D9
SAVE_JAM1 F409
SAVE_JAM2 F41C
SCAN01 EF12
SCANBLN F17C
SCANDETIK F117
SCANDEV2 EE41
SCANJAM F0B3

PAGE 50
SCANMENIT F0E5
SCANTGL F149
SCANTHN F1AF
SCAN_TB F789
SCL 0009
SCLK_SPI 000B
SDA 0008
SER_START F6F0
SER_STOP F6F9
SETBLN F165
SETBLN0 F179
SETBLN1 F187
SETDATA F1CB
SETDETIK F100
SETDETIK0 F114
SETDETIK1 F122
SETJAM F09C
SETJAM0 F0B0
SETJAM1 F0BE
SETJAMZ EF1D
SETMENIT F0CE
SETMENIT0 F0E2
SETMENIT1 F0F0
SETTGL F132
SETTGL0 F146
SETTGL1 F154
SETTHN F198
SETTHN0 F1AC
SETTHN1 F1BA
SETTING 0539
SHIFT_SERI F773
SISA 00B0
SISAJAM 00A0
SISAMENIT 009D
SISAMENIT1 009E
SISAMENIT2 009F
SPACE20 0562
SPACE20_1 EF71
SPACE30_1 EFB5
SPACE50_1 F04B
SPI F76E
SPI2 F77C
SPI_SET F77A
SW00 0570
SW01 0571
SW02 0572
SW03 0573
SW04 0574
SW05 0575
SW06 0576
SW11 0578
SW12 0579
SW17 057F
SWITCH 00AE
SWITCH1 00AF
TABEL1 F82D
TABEL10 F888
TABEL11 F89A

PAGE 51
TABEL12 F8A2
TABEL13 F8AC
TABEL14 F8B6
TABEL15 F8C2
TABEL16 F8CC
TABEL17 F8D6
TABEL18 F8DF
TABEL2 F83A
TABEL3 F840
TABEL4 F846
TABEL5 F84B
TABEL6 F851
TABEL7 F859
TABEL8 F869
TABEL9 F876
TAHUN 0006
TAHUND1 00A6
TAHUN_SET 00A3
TAHUN_TEMP 00B8
TAMPIL1 F753
TAMPIL3 F754
TAMPILWAKTU F20D
TANGGAL 0004
TANGGAL_TEMP 00B6
TASK1 F7B2
TASKDEV1 F7C7
TASKDEV2 F7FA
TCNTH 0021
TCNTL 0022
TGLD1 00A4
TGL_SET 00A1
TIME1 F21E
TIME2 F24C
TIMEDELAY 053D
TIM_OVER F7A4
TIM_STOP 0105
TMODH 0023
TMODL 0024
TOF 0107
TOMAIN EEFA
TORAM F298
TORTC F60F
TOTEMP1A F2B8
TOTEMP1B F2C5
TOTEMP2A F2D2
TOTEMP2B F2DF
TRST 0104
TSC 0020
TULIS F702
TXD F700
ULANG8 F601
USERRAM 0080
VIEWDATA 0561
VIEWTIME EEF2
VIEWTOTMAK F020
VIEW_AKHIR1 F356
VIEW_AKHIR2 F374
VIEW_JAM1 F583

PAGE 52
VIEW_JAM2 F5AA
VIEW_LAMA1 F3BA
VIEW_LAMA2 F3E2
VIEW_MULAI1 F31B
VIEW_MULAI2 F339
VIEW_TOTAL1 F392
VIEW_TOTAL2 F3A6
WAKTU 00A9
WAVE_OFF F668
WAVE_ON F67E
L2
LAMPIRAN DATASHEET
Philips Semiconductors Product specification
Triacs BT136 series D

logic level
GENERAL DESCRIPTION QUICK REFERENCE DATA

Passivated, sensitive gate triacs in a SYMBOL PARAMETER MAX. UNIT
plastic envelope, intended for use in
general purpose bidirectional switching BT136- 600D
and phase control applications. These VDRM Repetitive peak off-state voltages 600 V
devices are intended to be interfaced IT(RMS) RMS on-state current 4 A
directly to microcontrollers, logic ITSM Non-repetitive peak on-state current 25 A
integrated circuits and other low power
gate trigger circuits.
PINNING - TO220AB PIN CONFIGURATION SYMBOL

PIN DESCRIPTION
tab
1 main terminal 1
T2 T1
2 main terminal 2
3 gate
tab main terminal 2 1 23 G
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
-600D
VDRM Repetitive peak off-state - 600 V
voltages
IT(RMS) RMS on-state current full sine wave; Tmb ≤ 107 ˚C - 4 A
ITSM Non-repetitive peak full sine wave; Tj = 25 ˚C prior to
on-state current surge
t = 20 ms - 25 A
t = 16.7 ms - 27 A
I2t I2t for fusing t = 10 ms - 3.1 A2s
dIT/dt Repetitive rate of rise of ITM = 6 A; IG = 0.2 A;
on-state current after dIG/dt = 0.2 A/µs
triggering T2+ G+ - 50 A/µs
T2+ G- - 50 A/µs
T2- G- - 50 A/µs
T2- G+ - 10 A/µs
IGM Peak gate current - 2 A
VGM Peak gate voltage - 5 V
PGM Peak gate power - 5 W
PG(AV) Average gate power over any 20 ms period - 0.5 W
Tstg Storage temperature -40 150 ˚C
Tj Operating junction - 125 ˚C
temperature
THERMAL RESISTANCES
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Rth j-mb Thermal resistance full cycle - - 3.0 K/W
junction to mounting base half cycle - - 3.7 K/W
Rth j-a Thermal resistance in free air - 60 - K/W
junction to ambient
June 2001 1 Rev 1.400


logic level
STATIC CHARACTERISTICS
Tj = 25 ˚C unless otherwise stated
IGT Gate trigger current VD = 12 V; IT = 0.1 A
T2+ G+ - 2.0 5 mA
T2+ G- - 2.5 5 mA
T2- G- - 2.5 5 mA
T2- G+ - 5.0 10 mA
IL Latching current VD = 12 V; IGT = 0.1 A
T2+ G+ - 1.6 10 mA
T2+ G- - 4.5 15 mA
T2- G- - 1.2 10 mA
T2- G+ - 2.2 15 mA
IH Holding current VD = 12 V; IGT = 0.1 A - 1.2 10 mA
VT On-state voltage IT = 5 A - 1.4 1.70 V
VGT Gate trigger voltage VD = 12 V; IT = 0.1 A - 0.7 1.5 V
VD = 400 V; IT = 0.1 A; Tj = 125 ˚C 0.25 0.4 - V
ID Off-state leakage current VD = VDRM(max); Tj = 125 ˚C - 0.1 0.5 mA
DYNAMIC CHARACTERISTICS
Tj = 25 ˚C unless otherwise stated
dVD/dt Critical rate of rise of VDM = 67% VDRM(max); Tj = 125 ˚C; - 5 - V/µs
off-state voltage exponential waveform; RGK = 1 kΩ
tgt Gate controlled turn-on ITM = 6 A; VD = VDRM(max); IG = 0.1 A; - 2 - µs
time dIG/dt = 5 A/µs
June 2001 2 Rev 1.400


logic level
Ptot / W Tmb(max) / C IT(RMS) / A

8 101 5
7 104
107 C
= 180 4
6 1
107
120
5 110
90 3
60
4 113
30
3 116 2
2 119
1
1 122
0 125 0
0 1 2 3 4 5 -50 0 50 100 150
IT(RMS) / A Tmb / C
Fig.1. Maximum on-state dissipation, Ptot, versus rms Fig.4. Maximum permissible rms current IT(RMS) ,
on-state current, IT(RMS), where α = conduction angle. versus mounting base temperature Tmb.
ITSM / A IT(RMS) / A
1000 12
IT ITSM
10
T time
8
Tj initial = 25 C max
100 6
dIT /dt limit
4
T2- G+ quadrant
10 0
10us 100us 1ms 10ms 100ms 0.01 0.1 1 10
T/s surge duration / s
Fig.2. Maximum permissible non-repetitive peak Fig.5. Maximum permissible repetitive rms on-state
on-state current ITSM, versus pulse width tp, for current IT(RMS), versus surge duration, for sinusoidal
sinusoidal currents, tp ≤ 20ms. currents, f = 50 Hz; Tmb ≤ 107˚C.
ITSM / A BT136 VGT(Tj)

30 VGT(25 C)
1.6
IT I TSM
25
1.4
T time
20 Tj initial = 25 C max 1.2
15
1
10 0.8
5 0.6
0 0.4
1 10 100 1000 -50 0 50 100 150
Number of cycles at 50Hz Tj / C
Fig.3. Maximum permissible non-repetitive peak Fig.6. Normalised gate trigger voltage
on-state current ITSM, versus number of cycles, for VGT(Tj)/ VGT(25˚C), versus junction temperature Tj.
sinusoidal currents, f = 50 Hz.
June 2001 3 Rev 1.400


logic level
IGT(Tj) IT / A
12
IGT(25 C) Tj = 125 C
3
T2+ G+ Tj = 25 C typ max
T2+ G- 10
2.5 Vo = 1.27 V
T2- G- Rs = 0.091 ohms
T2- G+ 8
2
6
1.5
4
1
0.5 2
0 0
-50 0 50 100 150 0 0.5 1 1.5 2 2.5 3
Tj / C VT / V
Fig.7. Normalised gate trigger current Fig.10. Typical and maximum on-state characteristic.
IGT(Tj)/ IGT(25˚C), versus junction temperature Tj.
IL(Tj) Zth j-mb (K/W)

10
IL(25 C)
3 unidirectional
2.5 bidirectional
1
2
1.5
0.1 P tp
D
1
t
0.5
0.01
0 10us 0.1ms 1ms 10ms 0.1s 1s 10s
-50 0 50 100 150
Tj / C tp / s
Fig.8. Normalised latching current IL(Tj)/ IL(25˚C), Fig.11. Transient thermal impedance Zth j-mb, versus
versus junction temperature Tj. pulse width tp.
IH(Tj) dVD/dt (V/us)

1000
IH(25C)
3
2.5
100
2
1.5
1 10
0.5
0 1
-50 0 50 100 150 0 50 100 150
Tj / C Tj / C
Fig.9. Normalised holding current IH(Tj)/ IH(25˚C), Fig.12. Typical, critical rate of rise of off-state voltage,
versus junction temperature Tj. dVD/dt versus junction temperature Tj.
June 2001 4 Rev 1.400


logic level
MECHANICAL DATA
Dimensions in mm
4,5
Net Mass: 2 g max
10,3
max
1,3
3,7
2,8 5,9
min
15,8
max
3,0 max
3,0
not tinned
13,5
min
1,3
max 1 2 3
(2x) 0,9 max (3x)
0,6
2,54 2,54 2,4
Fig.13. SOT78 (TO220AB). pin 2 connected to mounting base.
Notes
1. Refer to mounting instructions for SOT78 (TO220) envelopes.
2. Epoxy meets UL94 V0 at 1/8".
June 2001 5 Rev 1.400


logic level
DEFINITIONS
DATA SHEET STATUS
DATA SHEET PRODUCT DEFINITIONS
STATUS1 STATUS2
Objective data Development This data sheet contains data from the objective specification for
product development. Philips Semiconductors reserves the right to
change the specification in any manner without notice
Preliminary data Qualification This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in ordere to improve the design and supply the best possible
product
Product data Production This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in
order to improve the design, manufacturing and supply. Changes will
be communicated according to the Customer Product/Process
Change Notification (CPCN) procedure SNW-SQ-650A
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
 Philips Electronics N.V. 2001
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
1 Please consult the most recently issued datasheet before initiating or completing a design.
2 The product status of the device(s) described in this datasheet may have changed since this datasheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
June 2001 6 Rev 1.400

This datasheet has been download from:
www.datasheetcatalog.com
Datasheets for electronics components.

DATA SHEET
1N5400~1N5408
HIGH CURRENT PLASTIC SILICON RECTIFIER
3.0 Ampere DO-201AD Unit: inch(mm)
VOLTAGE 50 to 1000 Volts CURRENT
FEATURES
• Plastic package has Underwriters Laboratories .052(1.3)
Flammability Classification 94V-O utilizing
1.0(25.4)MIN.
.048(1.2)
Flame Retardant Epoxy Molding Compound.
• High current capability
• Low leakage
• Exceeds environmental standards of MIL-S-19500/228
• Pb free product are available : 99% Sn above can meet Rohs environment
substance directive request
.375(9.5)
.285(7.2)
MECHANICALDATA
Case: DO-201AD Molded plastic .210(5.3)
1.0(25.4)MIN.
.188(4.8)
Lead: Axial leads, solderable per MIL-STD-202G,
Method 208 guaranteed
Polarity: Color band denotes cathode end
Mounting Position: Any
Weight: 1132mg
MAXIMUM RATINGS AND ELECTRICAL CHARACTERISTICS

Ratings at 25°C ambient temperature unless otherwise specified. Single phase, half wave, 60 Hz, resistive or inductive load.
For capacitive load,derate current by 20%.
PAR AME T E R S YM B OL 1 N 5 4 0 0 1 N 5 4 0 1 1 N 5 4 0 2 1 N 5 4 0 3 1 N 5 4 0 4 1 N 5 4 0 5 1 N 5 4 0 6 1 N 5 4 0 7 1 N 5 4 0 8 U N IT S
M a xi m um R e c ur r e nt P e a k R e ve r s e V o l t a g e V RRM 50 100 200 300 400 500 600 800 1000 V
M a xi m um R M S V o l t a g e V RMS 35 70 140 210 280 350 420 560 700 V
M a xi m um D C B l o c k i ng V o l t a g e V DC 50 100 200 300 400 400 600 800 1000 V
M a xi m um A ve r a g e F o r w a r d C ur r e nt . 3 7 5 " ( 9 . 5 m m )
IAV 3 .0 A
l e a d l e ng t h a t T A = 5 5 OC
P e a k F o r w a r d S ur g e C ur r e nt : 8 . 3 m s s i ng l e ha l f s i ne - w a ve
IF S M 200 A
s up e r i m p o s e d o n r a t e d l o a d ( J E D E C m e t ho d )
M a xi m um F o r w a r d V o l t a g e a t 3 . 0 A VF 1 .2 V
M a xi m um D C R e ve r s e C ur r e nt a t T A = 2 5 OC 5 .0
IR uA
R a t e d D C B l o c k i ng V o l t a g e T A = 1 0 0 OC 1000
Ty p i c a l J u n c t i o n c a p a c i t a n c e ( N o t e 1 ) CJ 30 pF
O
Ty p i c a l T h e r m a l R e s i s t a n c e ( N o t e 2 ) Rθ J A 20 C / W
O
O p e r a t i n g J u n c t i o n a n d S t o r a g e Te m p e r a t u r e R a n g e T J , T S TG - 5 5 TO + 1 5 0 C
NOTES:
1. Measured at 1 MHz and applied reverse voltage of 4.0 VDC.

2. Thermal Resistance from Junction to Ambient and from junction to lead at 0.375”(9.5mm)lead length P.C.B.mounted.
STAD-JAN.07.2005 PAGE . 1
RATING AND CHARACTERISTIC CURVES
5 240
AVERAGEFORWARDRECITIFIED
PEAK FORWARD SURGE CURRENT,

4 200
CURRENTAMPERES
160
3
AMPERES
120
2
80
1
40
0
0 20 40 60 80 100 120 140 160 0
1 10 100
O
AMBIENT TEMPERAURE, C NO. OF CYCLE AT 60HZ
Fig.1- FORWARD CURRENT DERATING CURVE Fig.2- MAXIMUM NON - REPETITIVE SURGE CURRENT
100 100
INSTANTANEOUS REVERSE CURRENT, uA
INSTANTANEOUS FORWARD CURRENT
O
TJ = 150 C
10 10
AMPERES
O
TJ = 100 C
1.0 1.0
O
TJ = 25 C
0.1 0.1
0.01 0 .01
20 40 60 80 100 120 140
0.5 0.7 0.9 1.1 1.3 1.5 1.7
PERCENTAGE OF PEAK REVERSE VOLTAGE,% INSTANTANEOUS FORWARD VOLTAGE, VOLTS
Fig.3- TYPICAL REVERSE CHARACTERISTIC Fig.4- TYPICAL INSTANTANEOUS FORWARD

CHARACTERISTIC
100
CAPACITANCE, pF
10
1
.1 1 10 100
REVERSE VOLTAGE, VOLTS
Fig.5- TYPICAL JUNCTION CAPACITANCE
STAD-JAN.07.2005 PAGE . 2
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT595
8-bit serial-in/serial or parallel-out
shift register with output latches;
3-state
Product specification 1998 Jun 04
Supersedes data of September 1993
File under Integrated Circuits, IC06
8-bit serial-in/serial or parallel-out shift

74HC/HCT595
register with output latches; 3-state
FEATURES DESCRIPTION
• 8-bit serial input The 74HC/HCT595 are high-speed Si-gate CMOS devices
• 8-bit serial or parallel output and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
• Storage register with 3-state outputs
standard no. 7A.
• Shift register with direct clear
The “595” is an 8-stage serial shift register with a storage
• 100 MHz (typ) shift out frequency register and 3-state outputs. The shift register and storage
• Output capability: register have separate clocks.
– parallel outputs; bus driver Data is shifted on the positive-going transitions of the
– serial output; standard SHCP input. The data in each register is transferred to the
storage register on a positive-going transition of the STCP
• ICC category: MSI.
input. If both clocks are connected together, the shift
register will always be one clock pulse ahead of the
APPLICATIONS storage register.
• Serial-to-parallel data conversion The shift register has a serial input (DS) and a serial
• Remote control holding register. standard output (Q7’) for cascading. It is also provided with
asynchronous reset (active LOW) for all 8 shift register
stages. The storage register has 8 parallel 3-state bus
driver outputs. Data in the storage register appears at the
output whenever the output enable input (OE) is LOW.
QUICK REFERENCE DATA

GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns.
TYP.
SYMBOL PARAMETER CONDITIONS UNIT
HC HCT
tPHL/tPLH propagation delay CL = 15 pF; VCC = 5 V
SHCP to Q7’ 16 21 ns
STCP to Qn 17 20 ns
MR to Q7’ 14 19 ns
fmax maximum clock frequency SHCP, STCP 100 57 MHz
CI input capacitance 3.5 3.5 pF
CPD power dissipation capacitance per package notes 1 and 2 115 130 pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑(CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC; for HCT the condition is VI = GND to VCC − 1.5 V.
1998 Jun 04 2

74HC/HCT595
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME DESCRIPTION VERSION
74HC595N DIP16 plastic dual in-line package; 16 leads (300 mil); long body SOT38-1
74HC595D SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
74HC595DB SSOP16 plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1
74HC595PW TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
74HCT595N DIP16 plastic dual in-line package; 16 leads (300 mil); long body SOT38-1
74HCT595D SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
PINNING
SYMBOL PIN DESCRIPTION

Q0 to Q7 15, 1 to 7 parallel data output
GND 8 ground (0 V)
Q7’ 9 serial data output
MR 10 master reset (active LOW)
SHCP 11 shift register clock input
STCP 12 storage register clock input
OE 13 output enable (active LOW)
DS 14 serial data input
VCC 16 positive supply voltage
handbook, halfpage 11 12
handbook, halfpage
Q1 1 16 VCC SHCP STCP
9
Q7'
Q2 2 15 Q0
15
Q0
Q3 3 14 DS 1
Q1
Q4 4 13 OE 2
Q2
595 14 3
Q5 5 12 STCP DS Q3
4
Q4
Q6 6 11 SHCP
5
Q5
Q7 7 10 MR 6
Q6
GND 8 9 Q7' 7
Q7
MLA001 MR OE
10 13
MLA002
Fig.1 Pin configuration. Fig.2 Logic symbol.
1998 Jun 04 3

74HC/HCT595
handbook, halfpage 13
OE EN3
12
STCP C2
10
MR R SRG8
11
SHCP C1/
14 15
DS 1D 2D 3 Q0
1
Q1
2
Q2
3
Q3
4
Q4
5
Q5
6
Q6
7
Q7
9
Q7'
MSA698
Fig.3 IEC logic symbol.
handbook, full pagewidth
14 DS
11 SHCP
8-STAGE SHIFT REGISTER
10 MR
Q7 ' 9
12 STCP
8-BIT STORAGE REGISTER
Q0 15
Q1 1
Q2 2
Q3 3
13 OE
3-STATE OUTPUTS Q4 4
Q5 5
Q6 6
Q7 7
MLA003
Fig.4 Functional diagram.
1998 Jun 04 4

74HC/HCT595

STAGE 0 STAGES 1 TO 6 STAGE 7
DS D Q D Q D Q Q7'
FF0 FF7
CP CP
R R
SHCP
MR
D Q D Q
LATCH LATCH
CP CP
STCP
OE
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 MLA010
Fig.5 Logic diagram.
1998 Jun 04 5

74HC/HCT595
FUNCTION TABLE
INPUTS OUTPUTS
FUNCTON
SHCP STCP OE MR DS Q7’ QN
X X L L X L NC a LOW level on MR only affects the shift registers
X ↑ L L X L L empty shift register loaded into storage register
X X H L X L Z shift register clear. Parallel outputs in high-impedance
OFF-state
↑ X L H H Q6’ NC logic high level shifted into shift register stage 0. Contents
of all shift register stages shifted through, e.g. previous
state of stage 6 (internal Q6’) appears on the serial output
(Q7’)
X ↑ L H X NC Qn’ contents of shift register stages (internal Qn’) are
transferred to the storage register and parallel output
stages
↑ ↑ L H X Q6’ Qn’ contents of shift register shifted through. Previous
contents of the shift register is transferred to the storage
register and the parallel output stages.
Notes
1. H = HIGH voltage level; L = LOW voltage level
↑ = LOW-to-HIGH transition; ↓ = HIGH-to-LOW transition
Z = high-impedance OFF-state; NC = no change
X = don’t care.
1998 Jun 04 6

74HC/HCT595
handbook,
SHfull
CPpagewidth
DS
STCP
MR
OE
Q0
high-impedance OFF-state
Q1
Q6
Q7
Q 7'
MLA005 - 1
Fig.6 Timing diagram.
1998 Jun 04 7

74HC/HCT595
DC CHARACTERISTICS FOR 74HC

For the DC characteristics see chapter “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: parallel outputs, bus driver, serial output, standard ICC category: MSI.
AC CHARACTERISTICS FOR 74HC

GND = 0 V; tr = tf = 6 ns; CL = 50 pF.
Tamb (°C) TEST CONDITION

SYMBOL PARAMETER +25 −40 to +85 −40 to +125 UNIT V
CC
WAVEFORMS
min typ max min max min max (V)
tPHL/tPLH propagation delay − 52 160 − 200 − 240 ns 2.0 Fig.7

SHCP to Q7’ − 19 32 − 40 − 48 4.5
− 15 27 − 34 − 41 6.0
tPHL/tPLH propagation delay − 55 175 − 220 − 265 ns 2.0 Fig.8
STCP to Qn − 20 35 − 44 − 53 4.5
− 16 30 − 37 − 45 6.0
tPHL propagation delay − 47 175 − 220 − 265 ns 2.0 Fig.10
MR to Q7’ − 17 35 − 44 − 53 4.5
− 14 30 − 37 − 45 6.0
tPZH/tPZL 3-state output − 47 150 − 190 − 225 ns 2.0 Fig.11
enable time − 17 30 − 38 − 45 4.5
OE to Qn
− 14 26 − 33 − 38 6.0
tPHZ/tPLZ 3-state output − 41 150 − 190 − 225 ns 2.0 Fig.11
disable time − 15 30 − 38 − 45 4.5
OE to Qn
− 12 26 − 33 − 38 6.0
tW shift clock pulse 75 17 − 95 − 110 − ns 2.0 Fig.7
width HIGH or 15 6 − 19 − 22 − 4.5
LOW
13 5 − 16 − 19 − 6.0
tW storage clock 75 11 − 95 − 110 − ns 2.0 Fig.8
pulse width HIGH 15 4 − 19 − 22 − 4.5
or LOW
13 3 − 16 − 19 − 6.0
tW master reset 75 17 − 95 − 110 − ns 2.0 Fig.10
pulse width LOW 15 6.0 − 19 − 22 − 4.5
13 5.0 − 16 − 19 − 6.0
tsu set-up time DS to 50 11 − 65 − 75 − ns 2.0 Fig.9
SHCP 10 4.0 − 13 − 15 − 4.5
9.0 3.0 − 11 − 13 − 6.0
tsu set-up time SHCP 75 22 − 95 − 110 − ns 2.0 Fig.8
to STCP 15 8 − 19 − 22 − 4.5
13 7 − 16 − 19 − 6.0
1998 Jun 04 8

74HC/HCT595

CC
WAVEFORMS
th hold time DS to 3 −6 − 3 − 3 − ns 2.0 Fig.9

SHCP 3 −2 − 3 − 3 − 4.5
3 −2 − 3 − 3 − 6.0
trem removal time MR 50 −19 − 65 − 75 − ns 2.0 Fig.10
to SHCP 10 −7 − 13 − 15 − 4.5
9 −6 − 11 − 13 − 6.0
fmax maximum clock 9 30 − 4.8 − 4 − MHz 2.0 Figs 7 and 8
pulse frequency 30 91 − 24 − 20 − 4.5
SHCP or STCP
35 108 − 28 − 24 − 6.0
1998 Jun 04 9

74HC/HCT595
DC CHARACTERISTICS FOR 74HCT

For the DC characteristics see chapter “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: parallel outputs, bus driver; serial output, standard ICC category: MSI.
Note to HCT types

The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
GND = 0 V; tr = tf = 6 ns; CL = 50 pF.
INPUT UNIT LOAD COEFFICIENT

DS 0.25
MR 1.50
SHCP 1.50
STCP 1.50
OE 1.50
1998 Jun 04 10

74HC/HCT595
AC CHARACTERISTICS FOR 74HCT

GND = 0 V; tr = tf = 6 ns; CL = 50 pF.

CC
WAVEFORMS
tPHL/ tPLH propagation delay − 25 42 − 53 − 63 ns 4.5 Fig.7

SHCP to Q7’
tPHL/ tPLH propagation delay − 24 40 − 50 − 60 ns 4.5 Fig.8
STCP to Qn
tPHL propagation delay − 23 40 − 50 − 60 ns 4.5 Fig.10
MR to Q7’
tPZH/ tPZL 3-state output enable − 21 35 − 44 − 53 ns 4.5 Fig.11
time OE to Qn
tPHZ/ tPLZ 3-state output disable − 18 30 − 38 − 45 ns 4.5 Fig.11
time OE to Qn
tW shift clock pulse 16 6 − 20 − 24 − ns 4.5 Fig.7
width HIGH or LOW
tW storage clock pulse width 16 5 − 20 − 24 − ns 4.5 Fig.8
HIGH or LOW
tW master reset 20 8 − 25 − 30 − ns 4.5 Fig.10
pulse width LOW
tsu set-up time DS to 16 5 − 20 − 24 − ns 4.5 Fig.9
SHSP
tsu set-up time SHCP 16 8 − 20 − 24 − ns 4.5 Fig.8
to STCP
th hold time DS to SHCP 3 −2 − 3 − 3 − ns 4.5 Fig.9
trem removal time MR 10 −7 − 13 − 15 − ns 4.5 Fig.10

to SHCP
fmax maximum clock 30 52 − 24 − 20 − MHz 4.5 Figs 7 and 8
pulse frequency
SHCP or STCP
1998 Jun 04 11

74HC/HCT595
AC WAVEFORMS
handbook, full pagewidth 1/fmax
SHCP INPUT VM(1)
tW
tPLH tPHL
90%
Q7' OUTPUT VM(1)
10%
tTLH tTHL MSA699
(1) HC: VM = 50%; VI = GND to VCC

HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.7 Waveforms showing the clock (SHCP) to output (Q7’) propagation delays, the shift clock pulse width and
maximum shift clock frequency.
SHCP INPUT VM(1)
tsu 1/fmax
STCP INPUT VM(1)
tW
tPLH tPHL
Qn OUTPUT VM(1)
MSA700

Fig.8 Waveforms showing the storage clock (STCP) to output (Qn) propagation delays, the storage clock pulse
width and the shift clock to storage clock set-up time.
1998 Jun 04 12

74HC/HCT595
SHCP INPUT VM(1)
tsu tsu
th th
DS INPUT VM(1)
Q7' OUTPUT VM(1)
MLB196

Fig.9 Waveforms showing the data set-up and hold times for the DS input.
MR INPUT VM(1)
tW trem
SHCP INPUT VM(1)
tPHL
Q7' OUTPUT VM(1)
MLB197

Fig.10 Waveforms showing the master reset (MR) pulse width, the master reset to output (Q7’) propagation delay
and the master reset to shift clock (SHCP) removal time.
1998 Jun 04 13

74HC/HCT595
handbook, full pagewidth tr tf
90%
OE INPUT VM(1)
10%
tPLZ tPZL
Qn OUTPUT
LOW-to-OFF VM(1)
OFF-to-LOW 10%
tPHZ tPZH
90%
Qn OUTPUT
HIGH-to-OFF VM(1)
OFF-to-HIGH
outputs outputs outputs

enabled disabled enabled
MSA697

Fig.11 Waveforms showing the 3-state enable and disable times for input OE.
1998 Jun 04 14

74HC/HCT595
PACKAGE OUTLINES
DIP16: plastic dual in-line package; 16 leads (300 mil); long body SOT38-1
D ME
seating plane
A2 A
A1
L
c
Z e w M
b1
(e 1)
b
16 9 MH
pin 1 index
E
1 8
0 5 10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A A1 A2
b b1 c D (1) E (1) e e1 L ME MH w Z (1)
max. min. max. max.
1.40 0.53 0.32 21.8 6.48 3.9 8.25 9.5
mm 4.7 0.51 3.7 2.54 7.62 0.254 2.2
1.14 0.38 0.23 21.4 6.20 3.4 7.80 8.3
0.055 0.021 0.013 0.86 0.26 0.15 0.32 0.37
inches 0.19 0.020 0.15 0.10 0.30 0.01 0.087
0.045 0.015 0.009 0.84 0.24 0.13 0.31 0.33
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC EIAJ PROJECTION
92-10-02
SOT38-1 050G09 MO-001AE
95-01-19
1998 Jun 04 15

74HC/HCT595
SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
D E A
X
y HE v M A
16 9
Q
A2
(A 3) A
A1
pin 1 index
θ
Lp
1 8 L
e w M detail X
bp
0 2.5 5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A
UNIT max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ
0.25 1.45 0.49 0.25 10.0 4.0 6.2 1.0 0.7 0.7
mm 1.75 0.25 1.27 1.05 0.25 0.25 0.1 o
0.10 1.25 0.36 0.19 9.8 3.8 5.8 0.4 0.6 0.3 8
0.010 0.057 0.019 0.0100 0.39 0.16 0.244 0.039 0.028 0.028 0o
inches 0.069 0.01 0.050 0.041 0.01 0.01 0.004
0.004 0.049 0.014 0.0075 0.38 0.15 0.228 0.016 0.020 0.012
Note

ISSUE DATE
95-01-23
SOT109-1 076E07S MS-012AC
97-05-22
1998 Jun 04 16

74HC/HCT595
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1
D E A
X
c
y HE v M A
16 9
Q
A2 A
A1 (A 3)
pin 1 index
θ
Lp
L
1 8 detail X
w M
e bp
0 2.5 5 mm
scale
DIMENSIONS (mm are the original dimensions)

A
UNIT A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ
max.
o
0.21 1.80 0.38 0.20 6.4 5.4 7.9 1.03 0.9 1.00 8
mm 2.0 0.25 0.65 1.25 0.2 0.13 0.1
0.05 1.65 0.25 0.09 6.0 5.2 7.6 0.63 0.7 0.55 0o
Note

ISSUE DATE
94-01-14
SOT338-1 MO-150AC
95-02-04
1998 Jun 04 17

74HC/HCT595
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
D E A
X
y HE v M A
16 9
Q
A2 (A 3)
A
A1
pin 1 index
θ
Lp
L
1 8
detail X
w M
e bp
0 2.5 5 mm
scale
DIMENSIONS (mm are the original dimensions)

A
UNIT A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ
max.
o
0.15 0.95 0.30 0.2 5.1 4.5 6.6 0.75 0.4 0.40 8
mm 1.10 0.25 0.65 1.0 0.2 0.13 0.1
0.05 0.80 0.19 0.1 4.9 4.3 6.2 0.50 0.3 0.06 0o
Notes
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

ISSUE DATE
94-07-12
SOT403-1 MO-153
95-04-04
1998 Jun 04 18

74HC/HCT595
SOLDERING SO, SSOP and TSSOP

Introduction REFLOW SOLDERING
There is no soldering method that is ideal for all IC Reflow soldering techniques are suitable for all SO, SSOP
packages. Wave soldering is often preferred when and TSSOP packages.
through-hole and surface mounted components are mixed
Reflow soldering requires solder paste (a suspension of
on one printed-circuit board. However, wave soldering is
fine solder particles, flux and binding agent) to be applied
not always suitable for surface mounted ICs, or for
to the printed-circuit board by screen printing, stencilling or
printed-circuits with high population densities. In these
pressure-syringe dispensing before package placement.
situations reflow soldering is often used.
Several techniques exist for reflowing; for example,
This text gives a very brief insight to a complex technology.
thermal conduction by heated belt. Dwell times vary
A more in-depth account of soldering ICs can be found in
between 50 and 300 seconds depending on heating
our “Data Handbook IC26; Integrated Circuit Packages”
method.
(order code 9398 652 90011).
Typical reflow temperatures range from 215 to 250 °C.
DIP Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
SOLDERING BY DIPPING OR BY WAVE
45 °C.
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact WAVE SOLDERING
with the joint for more than 5 seconds. The total contact
Wave soldering can be used for all SO packages. Wave
time of successive solder waves must not exceed
soldering is not recommended for SSOP and TSSOP
5 seconds.
packages, because of the likelihood of solder bridging due
The device may be mounted up to the seating plane, but to closely-spaced leads and the possibility of incomplete
the temperature of the plastic body must not exceed the solder penetration in multi-lead devices.
specified maximum storage temperature (Tstg max). If the
If wave soldering is used - and cannot be avoided for
printed-circuit board has been pre-heated, forced cooling
SSOP and TSSOP packages - the following conditions
may be necessary immediately after soldering to keep the
must be observed:
temperature within the permissible limit.
• A double-wave (a turbulent wave with high upward
REPAIRING SOLDERED JOINTS pressure followed by a smooth laminar wave) soldering
technique should be used.
Apply a low voltage soldering iron (less than 24 V) to the
• The longitudinal axis of the package footprint must be
lead(s) of the package, below the seating plane or not
parallel to the solder flow and must incorporate solder
more than 2 mm above it. If the temperature of the
thieves at the downstream end.
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.
1998 Jun 04 19

74HC/HCT595
Even with these conditions: REPAIRING SOLDERED JOINTS

• Only consider wave soldering SSOP packages that Fix the component by first soldering two diagonally-
have a body width of 4.4 mm, that is opposite end leads. Use only a low voltage soldering iron
SSOP16 (SOT369-1) or SSOP20 (SOT266-1). (less than 24 V) applied to the flat part of the lead. Contact
• Do not consider wave soldering TSSOP packages time must be limited to 10 seconds at up to 300 °C. When
with 48 leads or more, that is TSSOP48 (SOT362-1) using a dedicated tool, all other leads can be soldered in
and TSSOP56 (SOT364-1). one operation within 2 to 5 seconds between
270 and 320 °C.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
DEFINITIONS
Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1998 Jun 04 20
This datasheet has been download from:
www.datasheetcatalog.com
Datasheets for electronics components.

DS1307
64 x 8, Serial, I2C Real-Time Clock
GENERAL DESCRIPTION FEATURES

The DS1307 serial real-time clock (RTC) is a § Real-Time Clock (RTC) Counts Seconds,
low-power, full binary-coded decimal (BCD) Minutes, Hours, Date of the Month, Month,
clock/calendar plus 56 bytes of NV SRAM. Day of the week, and Year with Leap-Year
Address and data are transferred serially through Compensation Valid Up to 2100
an I2C™, bidirectional bus. The clock/calendar § 56-Byte, Battery-Backed, Nonvolatile (NV)
provides seconds, minutes, hours, day, date, RAM for Data Storage
month, and year information. The end of the § I2C Serial Interface
month date is automatically adjusted for months § Programmable Square-Wave Output Signal
with fewer than 31 days, including corrections for § Automatic Power-Fail Detect and Switch
leap year. The clock operates in either the 24- Circuitry
hour or 12-hour format with AM/PM indicator. § Consumes Less than 500nA in Battery-
The DS1307 has a built-in power-sense circuit Backup Mode with Oscillator Running
that detects power failures and automatically § Optional Industrial Temperature Range:
switches to the battery supply. -40°C to +85°C
§ Available in 8-Pin DIP or SO
§ Underwriters Laboratory (UL) Recognized
ORDERING INFORMATION
TEMP PIN- TOP
PART
RANGE PACKAGE MARK
PIN CONFIGUATIONS
DS1307 0°C to +70°C 8 PDIP DS1307
TOP VIEW
DS1307Z 0°C to +70°C 8 SO DS1307
X1 1 8 VCC
DS1307N -40°C to +85°C 8 PDIP DS1307*
X2 2 7 SQW/OUT
DS1307ZN -40°C to +85°C 8 SO DS1307N VBAT 3 6 SCL
GND 4 5 SDA
* An ‘N’ is added to the lower right-hand corner of the top brand.
PDIP (300 mils)
I2C is a trademark of Philips Corp. Purchase of I2C components of

Maxim Integrated Products, Inc., or one of its sublicensed
X1 1 8 VCC
Associated Companies, conveys a license under the Philips I2C
X2 2 7 SQW/OUT
Patent Rights to use these components in an I2C system, provided
VBAT 3 6 SCL
that the system conforms to the I2C Standard Specification as
defined by Philips Corp. GND 4 5 SDA
SO (150 mils)
Typical Operating Circuit appears at end of data sheet.
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
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DS1307 64 x 8, Serial, I C Real-Time Clock
ABSOLUTE MAXIMUM RATINGS

Voltage Range on Any Pin Relative to Ground……………………………………………….…………....-0.5V to +7.0V
Operating Temperature Range (noncondensing)……………………………………………0°C to +70°C (Commercial),
-40°C to +85°C (Industrial)
Storage Temperature Range………………………………………………………...…………..…………-55°C to +125°C
Soldering Temperature (DIP, leads)…………………………………………………………….....+260°C for 10 seconds
Soldering Temperature (surface mount)……………………………………….See JPC/JEDEC Standard J-STD-020A
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is
not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS

(TA = 0°C to +70°C, TA = -40°C to +85°C.) (Notes 1, 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Supply Voltage VCC 4.5 5.0 5.5 V
Logic 1 Input VIH 2.2 VCC + 0.3 V
Logic 0 Input VIL -0.3 +0.8 V
VBAT Battery Voltage VBAT 2.0 3 3.5 V
DC ELECTRICAL CHARACTERISTICS
(VCC = 4.5V to 5.5V; TA = 0°C to +70°C, TA = -40°C to +85°C.) (Notes 1, 2)
Input Leakage (SCL) ILI 1 mA
I/O Leakage (SDA, SQW/OUT) ILO 1 mA
Logic 0 Output (IOL = 5mA) VOL 0.4 V
Active Supply Current
ICCA 1.5 mA
(fSCL = 100kHz)
Standby Current ICCS (Note 3) 200 mA
VBAT Leakage Current IBATLKG 5 50 nA
1.216 x 1.25 x 1.284 x
Power-Fail Voltage (VBAT = 3.0V) VPF V
VBAT VBAT VBAT
DC ELECTRICAL CHARACTERISTICS
(VCC = 0V, VBAT = 3.0V; TA = 0°C to +70°C, TA = -40°C to +85°C.) (Notes 1, 2)
VBAT Current (OSC ON);
IBAT1 300 500 nA
SQW/OUT OFF
VBAT Current (OSC ON);
IBAT2 480 800 nA
SQW/OUT ON (32kHz)
VBAT Data-Retention Current
IBATDR 10 100 nA
(Oscillator Off)
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AC ELECTRICAL CHARACTERISTICS
(VCC = 4.5V to 5.5V; TA = 0°C to +70°C, TA = -40°C to +85°C.)

SCL Clock Frequency fSCL 0 100 kHz
Bus Free Time Between a STOP and
tBUF 4.7 ms
START Condition
Hold Time (Repeated) START
tHD:STA (Note 4) 4.0 ms
Condition
LOW Period of SCL Clock tLOW 4.7 ms
HIGH Period of SCL Clock tHIGH 4.0 ms
Setup Time for a Repeated START
tSU:STA 4.7 ms
Condition
Data Hold Time tHD:DAT 0 ms
Data Setup Time tSU:DAT (Notes 5, 6) 250 ns
Rise Time of Both SDA and SCL
tR 1000 ns
Signals
Fall Time of Both SDA and SCL
tF 300 ns
Signals
Setup Time for STOP Condition tSU:STO 4.7 ms
CAPACITANCE
(TA = +25°C)
Pin Capacitance (SDA, SCL) CI/O 10 pF
Capacitance Load for Each Bus
CB (Note 7) 400 pF
Line
Note 1: All voltages are referenced to ground.

Note 2: Limits at -40°C are guaranteed by design and are not production tested.
Note 3: ICCS specified with VCC = 5.0V and SDA, SCL = 5.0V.
Note 4: After this period, the first clock pulse is generated.
Note 5: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIH(MIN) of the SCL
signal) to bridge the undefined region of the falling edge of SCL.
Note 6: The maximum tHD:DAT only has to be met if the device does not stretch the LOW period (tLOW) of the SCL signal.
Note 7: CB—total capacitance of one bus line in pF.
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TIMING DIAGRAM
SDA
tBUF
tHD:STA
tLOW
tR tF
SCL
tHD:STA tSU:STA
tHIGH
tSU:STO
STOP START SU:DAT

REPEATED
START
tHD:DAT
Figure 1. Block Diagram
1Hz/4.096kHz/
X1
32,768Hz DIVIDER 8.192kHz/32.768kHz SQW /OUT
CHAIN
OSCILLATOR M UX/BUFFER
X2
v cc
CONTROL
V BAT POW ER LOGIC
CONTROL 1Hz
CLOCK AND
GND CALENDAR
REGISTERS
DS1307
SCL SERIAL BUS RAM

INTERFACE
AND ADDRESS USER BUFFER
REGISTER (7 BYTES)
SDA
DECODE
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TYPICAL OPERATING CHARACTERISTICS

(VCC = 5.0V, TA = +25°C, unless otherwise noted.)
ICCS vs. VCC V BAT=3.0V IBAT vs. VBAT V CC = 0V
120 400
SQW=32kHz
110
100 350
90
SUPPLY CURRENT (nA)

SUPPLY CURRENT (uA)
80 300
70
60 250
50 SQW off
40 200
30
20 150
10
0 100
1.0 2.0 3.0 4.0 5.0 2.0 2.5 3.0 3.5
VCC (V) V BACKUP (V)
V CC=0V, V BAT=3.0
IBAT vs. Temperature SQW/OUT vs. Supply Voltage
32769
325.0
SQW=32kHz 32768.9
32768.8
SUPPLY CURRENT (nA)
32768.7
FREQUENCY (Hz)
275.0 32768.6
32768.5
32768.4
225.0
32768.3
32768.2
SQW off
32768.1
175.0
-40 -20 0 20 40 60 80 32768
TEMPERATURE (°C) 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Supply (V)
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PIN DESCRIPTION
PIN NAME FUNCTION
Connections for Standard 32.768kHz Quartz Crystal. The internal oscillator circuitry is
1 X1 designed for operation with a crystal having a specified load capacitance (CL) of 12.5pF. X1
is the input to the oscillator and can optionally be connected to an external 32.768kHz
oscillator. The output of the internal oscillator, X2, is floated if an external oscillator is
connected to X1.
2 X2 Note: For more information on crystal selection and crystal layout considerations, refer to
Application Note 58: Crystal Considerations with Dallas Real-Time Clocks.
Backup Supply Input for Any Standard 3V Lithium Cell or Other Energy Source. Battery
voltage must be held between the minimum and maximum limits for proper operation.
Diodes in series between the battery and the VBAT pin may prevent proper operation. If a
backup supply is not required, VBAT may be grounded. The nominal power-fail trip point
3 VBAT (VPF) voltage at which access to the RTC and user RAM is denied is set by the internal
circuitry as 1.25 x VBAT nominal. A lithium battery with 48mAhr or greater will back up the
DS1307 for more than 10 years in the absence of power at +25°C.
UL recognized to ensure against reverse charging current when used with a lithium battery.
4 GND Ground.
Serial Data Input/Output. SDA is the data input/output for the I2C serial interface. The SDA
5 SDA
pin is open drain and requires an external pullup resistor.
Serial Clock Input. SCL is the clock input for the I2C interface and is used to synchronize
6 SCL
data movement on the serial interface.
Square Wave/Output Driver. When enabled, the SQWE bit set to 1, the SQW/OUT pin
outputs one of four square-wave frequencies (1Hz, 4kHz, 8kHz, 32kHz). The SQW/OUT
7 SWQ/OUT
pin is open drain and requires an external pullup resistor. SQW/OUT operates with either
VCC or VBAT applied.
Primary Power Supply. When voltage is applied within normal limits, the device is fully
accessible and data can be written and read. When a backup supply is connected to the
8 VCC
device and VCC is below VTP, read and writes are inhibited. However, the timekeeping
function continues unaffected by the lower input voltage.
DETAILED DESCRIPTION
The DS1307 is a low-power clock/calendar with 56 bytes of battery-backed SRAM. The clock/calendar
provides seconds, minutes, hours, day, date, month, and year information. The date at the end of the
month is automatically adjusted for months with fewer than 31 days, including corrections for leap year.
The DS1307 operates as a slave device on the I2C bus. Access is obtained by implementing a START
condition and providing a device identification code followed by a register address. Subsequent registers
can be accessed sequentially until a STOP condition is executed. When VCC falls below 1.25 x VBAT, the
device terminates an access in progress and resets the device address counter. Inputs to the device will not
be recognized at this time to prevent erroneous data from being written to the device from an out-of-
tolerance system. When VCC falls below VBAT, the device switches into a low-current battery-backup
mode. Upon power-up, the device switches from battery to VCC when VCC is greater than VBAT +0.2V and
recognizes inputs when VCC is greater than 1.25 x VBAT. The block diagram in Figure 1 shows the main
elements of the serial RTC.
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OSCILLATOR CIRCUIT
The DS1307 uses an external 32.768kHz crystal. The oscillator circuit does not require any external
resistors or capacitors to operate. Table 1 specifies several crystal parameters for the external crystal.
Figure 3 shows a functional schematic of the oscillator circuit. If using a crystal with the specified
characteristics, the startup time is usually less than one second.
CLOCK ACCURACY
The accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the match
between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was
trimmed. Additional error will be added by crystal frequency drift caused by temperature shifts. External
circuit noise coupled into the oscillator circuit may result in the clock running fast. Refer to Application
Note 58: Crystal Considerations with Dallas Real-Time Clocks for detailed information.
Table 1. Crystal Specifications*

PARAMETER SYMBOL MIN TYP MAX UNITS
Nominal Frequency fO 32.768 kHz
Series Resistance ESR 45 kW
Load Capacitance CL 12.5 pF
*The crystal, traces, and crystal input pins should be isolated from RF generating signals. Refer to
Application Note 58: Crystal Considerations for Dallas Real-Time Clocks for additional specifications.
Figure 2. Recommended Layout for Crystal
LOCAL GROUND PLANE (LAYER 2)
X1
CRYSTAL
X2
GND
NOTE: AVOID ROUTING SIGNAL LINES IN THE CROSSHATCHED

AREA (UPPER LEFT QUADRANT) OF THE PACKAGE UNLESS
THERE IS A GROUND PLANE BETWEEN THE SIGNAL LINE AND THE
DEVICE PACKAGE.
7 of 15
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Figure 3. Oscillator Circuit Showing Internal Bias Network
COUNTDOWN
CHAIN
DS1307 RTC
CL1
CL2 RTC
REGISTERS
X1 X2
CRYSTAL
RTC AND RAM ADDRESS MAP

Table 2 shows the address map for the DS1307 RTC and RAM registers. The RTC registers are located in
address locations 00h to 07h. The RAM registers are located in address locations 08h to 3Fh. During a
multibyte access, when the address pointer reaches 3Fh, the end of RAM space, it wraps around to
location 00h, the beginning of the clock space.
CLOCK AND CALENDAR

The time and calendar information is obtained by reading the appropriate register bytes. Table 2 shows
the RTC registers. The time and calendar are set or initialized by writing the appropriate register bytes.
The contents of the time and calendar registers are in the BCD format. The day-of-week register
increments at midnight. Values that correspond to the day of week are user-defined but must be
sequential (i.e., if 1 equals Sunday, then 2 equals Monday, and so on.) Illogical time and date entries
result in undefined operation. Bit 7 of Register 0 is the clock halt (CH) bit. When this bit is set to 1, the
oscillator is disabled. When cleared to 0, the oscillator is enabled.
Please note that the initial power-on state of all registers is not defined. Therefore, it is important to
enable the oscillator (CH bit = 0) during initial configuration.
The DS1307 can be run in either 12-hour or 24-hour mode. Bit 6 of the hours register is defined as the
12-hour or 24-hour mode-select bit. When high, the 12-hour mode is selected. In the 12-hour mode, bit 5
is the AM/PM bit with logic high being PM. In the 24-hour mode, bit 5 is the second 10-hour bit (20 to
23 hours). The hours value must be re-entered whenever the 12/24-hour mode bit is changed.
When reading or writing the time and date registers, secondary (user) buffers are used to prevent errors
when the internal registers update. When reading the time and date registers, the user buffers are
synchronized to the internal registers on any I2C START. The time information is read from these
secondary registers while the clock continues to run. This eliminates the need to re-read the registers in
case the internal registers update during a read. The divider chain is reset whenever the seconds register is
written. Write transfers occur on the I2C acknowledge from the DS1307. Once the divider chain is reset,
to avoid rollover issues, the remaining time and date registers must be written within one second.
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Table 2. Timekeeper Registers

ADDRESS Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 FUNCTION RANGE
00H CH 10 Seconds Seconds Seconds 00–59
01H 0 10 Minutes Minutes Minutes 00–59
12 10 Hour 1–12
02H 0 10 Hour Hours Hours +AM/PM
24 PM/AM 00–23
03H 0 0 0 0 0 DAY Day 01–07
04H 0 0 10 Date Date Date 01–31
10
05H 0 0 0 Month Month 01–12
Month
06H 10 Year Year Year 00–99
07H OUT 0 0 SQWE 0 0 RS1 RS0 Control —
08H-3FH RAM 56 x 8 00H–FFH
0 = Always reads back as 0.
CONTROL REGISTER
The DS1307 control register is used to control the operation of the SQW/OUT pin.
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

OUT 0 0 SQWE 0 0 RS1 RS0
Bit 7: Output Control (OUT). This bit controls the output level of the SQW/OUT pin when the square-
wave output is disabled. If SQWE = 0, the logic level on the SQW/OUT pin is 1 if OUT = 1 and is 0 if
OUT = 0.
Bit 4: Square-Wave Enable (SQWE). This bit, when set to logic 1, enables the oscillator output. The
frequency of the square-wave output depends upon the value of the RS0 and RS1 bits. With the square-
wave output set to 1Hz, the clock registers update on the falling edge of the square wave.
Bits 1, 0: Rate Select (RS1, RS0). These bits control the frequency of the square-wave output when the
square-wave output has been enabled. The following table lists the square-wave frequencies that can be
selected with the RS bits.
SQUARE-WAVE
RS1 RS0
OUTPUT FREQUENCY
0 0 1Hz
0 1 4.096kHz
1 0 8.192kHz
1 1 32.768kHz
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I2C DATA BUS

The DS1307 supports the I2C protocol. A device that sends data onto the bus is defined as a transmitter
and a device receiving data as a receiver. The device that controls the message is called a master. The
devices that are controlled by the master are referred to as slaves. The bus must be controlled by a master
device that generates the serial clock (SCL), controls the bus access, and generates the START and STOP
conditions. The DS1307 operates as a slave on the I2C bus.
Figures 4, 5, and 6 detail how data is transferred on the I2C bus.
§ Data transfer may be initiated only when the bus is not busy.
§ During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in
the data line while the clock line is high will be interpreted as control signals.
Accordingly, the following bus conditions have been defined:
Bus not busy: Both data and clock lines remain HIGH.
Start data transfer: A change in the state of the data line, from HIGH to LOW, while the clock is
HIGH, defines a START condition.
Stop data transfer: A change in the state of the data line, from LOW to HIGH, while the clock line
is HIGH, defines the STOP condition.
Data valid: The state of the data line represents valid data when, after a START condition, the data
line is stable for the duration of the HIGH period of the clock signal. The data on the line must be
changed during the LOW period of the clock signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a START condition and terminated with a STOP condition. The
number of data bytes transferred between START and STOP conditions is not limited, and is
determined by the master device. The information is transferred byte-wise and each receiver
acknowledges with a ninth bit. Within the 2-wire bus specifications a standard mode (100kHz clock
rate) and a fast mode (400kHz clock rate) are defined. The DS1307 operates in the standard mode
(100kHz) only.
Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after
the reception of each byte. The master device must generate an extra clock pulse which is associated
with this acknowledge bit.
A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in
such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related
clock pulse. Of course, setup and hold times must be taken into account. A master must signal an
end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked
out of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate
the STOP condition.
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Figure 4. Data Transfer on I2C Serial Bus
SDA
MSB
R/W
DIRECTION ACKNOWLEDGEMENT
BIT SIGNAL FROM RECEIVER
ACKNOWLEDGEMENT
SIGNAL FROM RECEIVER
SCL
1 2 6 7 8 9 1 2 3-7 8 9
ACK ACK
START STOP
CONDITION CONDITION
REPEATED IF MORE BYTES OR
ARE TRANSFERED REPEATED
START
CONDITION
Depending upon the state of the R/W bit, two types of data transfer are possible:
1. Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the
master is the slave address. Next follows a number of data bytes. The slave returns an acknowledge
bit after each received byte. Data is transferred with the most significant bit (MSB) first.
2. Data transfer from a slave transmitter to a master receiver. The first byte (the slave address) is
transmitted by the master. The slave then returns an acknowledge bit. This is followed by the slave
transmitting a number of data bytes. The master returns an acknowledge bit after all received bytes
other than the last byte. At the end of the last received byte, a “not acknowledge” is returned.
The master device generates all the serial clock pulses and the START and STOP conditions. A
transfer is ended with a STOP condition or with a repeated START condition. Since a repeated
START condition is also the beginning of the next serial transfer, the bus will not be released. Data is
transferred with the most significant bit (MSB) first.
The DS1307 may operate in the following two modes:
1. Slave Receiver Mode (Write Mode): Serial data and clock are received through SDA and SCL.
After each byte is received an acknowledge bit is transmitted. START and STOP conditions are
recognized as the beginning and end of a serial transfer. Hardware performs address recognition after
reception of the slave address and direction bit (see Figure 5). The slave address byte is the first byte
received after the master generates the START condition. The slave address byte contains the 7-bit
DS1307 address, which is 1101000, followed by the direction bit (R/W), which for a write is 0. After
receiving and decoding the slave address byte, the DS1307 outputs an acknowledge on SDA. After
the DS1307 acknowledges the slave address + write bit, the master transmits a word address to the
DS1307. This sets the register pointer on the DS1307, with the DS1307 acknowledging the transfer.
The master can then transmit zero or more bytes of data with the DS1307 acknowledging each byte
received. The register pointer automatically increments after each data byte are written. The master
will generate a STOP condition to terminate the data write.
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Figure 5. Data Write—Slave Receiver Mode
<RW>
<Slave Address> <Word Address (n)> <Data (n) <Data (n+1)> <Data (n+X)>
S 1101000 0 A XXXXXXXX A XXXXXXXX A XXXXXXXX A XXXXXXXX A P
S — START DATA TRANSFERRED

A — ACKNOWLEDGE (X+1 BYTES + ACKNOWLEDGE)
P — STOP
R/W — READ/WRITE OR DIRECTION BIT ADDRESS = D0H
2. Slave Transmitter Mode (Read Mode): The first byte is received and handled as in the slave
receiver mode. However, in this mode, the direction bit will indicate that the transfer direction is
reversed. The DS1307 transmits serial data on SDA while the serial clock is input on SCL. START
and STOP conditions are recognized as the beginning and end of a serial transfer (see Figure 6). The
slave address byte is the first byte received after the START condition is generated by the master. The
slave address byte contains the 7-bit DS1307 address, which is 1101000, followed by the direction bit
(R/W), which is 1 for a read. After receiving and decoding the slave address the DS1307 outputs an
acknowledge on SDA. The DS1307 then begins to transmit data starting with the register address
pointed to by the register pointer. If the register pointer is not written to before the initiation of a read
mode the first address that is read is the last one stored in the register pointer. The register pointer
automatically increments after each byte are read. The DS1307 must receive a Not Acknowledge to
end a read.
Figure 6. Data Read—Slave Transmitter Mode

<RW>
<Slave Address> <Data (n)> <Data (n+1) <Data (n+2)> <Data (n+X)>
S 1101000 1 A XXXXXXXX A XXXXXXXX A XXXXXXXX A XXXXXXXX A P
DATA TRANSFERRED
S — START (X+1 BYTES + ACKNOWLEDGE); NOTE: LAST DATA BYTE IS
FOLLOWED BY A NOT ACKNOWLEDGE (A) SIGNAL)
A — ACKNOWLEDGE
P — STOP
A — NOT ACKNOWLEDGE
R/W — READ/WRITE OR DIRECTION BIT ADDRESS = D1H
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TYPICAL OPERATING CIRCUIT

VCC
VCC
CRYSTAL
VCC RPU RPU
1 2 8
X1 X2 VCC
6 7
SCL FT/OUT
CPU
DS1307
5 3
SDA VBAT
GND
RPU = tr / Cb 4
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PACKAGE INFORMATION
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package
outline information, go to www.maxim-ic.com/DallasPackInfo.)
14 of 15
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PACKAGE INFORMATION (continued)

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package
outline information, go to www.maxim-ic.com/DallasPackInfo.)
15 of 15
Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product.
No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2004 Maxim Integrated Products · Printed USA
MAXIM is a registered trademark of Maxim Integrated Products, Inc. DALLAS is a registered trademark of Dallas Semiconductor Corporation.
MC68HC908QY4
MC68HC908QT4
MC68HC908QY2
MC68HC908QT2
MC68HC908QY1
MC68HC908QT1
Data Sheet
M68HC08
Microcontrollers
MC68HC908QY4/D
Rev 1.0
8/2003
MOTOROLA.COM/SEMICONDUCTORS
MC68HC908QY4
MC68HC908QT4
MC68HC908QY2
MC68HC908QT2
MC68HC908QY1
MC68HC908QT1
Data Sheet
To provide the most up-to-date information, the revision of our documents on the
World Wide Web will be the most current. Your printed copy may be an earlier
revision. To verify you have the latest information available, refer to:
http://motorola.com/semiconductors/
The following revision history table summarizes changes contained in this

document. For your convenience, the page number designators have been linked
to the appropriate location.
Motorola and the Stylized M Logo are registered trademarks of Motorola, Inc.
DigitalDNA is a trademark of Motorola, Inc.
This product incorporates SuperFlash® technology licensed from SST. © Motorola, Inc., 2003
MC68HC908QY/QT Family — Rev. 1 Data Sheet
MOTOROLA 3
Revision History
Revision History
Revision Page
Date Description
Level Number(s)
September,
N/A Initial release N/A
2002
1.2 Features — Added 8-pin dual flat no lead (DFN) packages to features list. 19
Figure 1-2. MCU Pin Assignments — Figure updated to include DFN
21
packages.
Figure 2-1. Memory Map — Clarified illegal address and unimplemented
28
memory.
Figure 2-2. Control, Status, and Data Registers — Corrected bit definitions
28
for Port A Data Register (PTA) and Data Direction Register A (DDRA).
Table 13-3. Interrupt Sources — Corrected vector addresses for keyboard
124
interrupt and ADC conversion complete interrupt.
Section 13. System Integration Module (SIM) — Removed reference to break
113
status register as it is duplicated in break module.
11.3.1 Internal Oscillator and 11.3.1.1 Internal Oscillator Trimming —
Clarified oscillator trim option ordering information and what to expect with 97
untrimmed device.
December,
0.1 Figure 11-5. Oscillator Trim Register (OSCTRIM) — Bit 1 designation
2002 104
corrected.
Figure 15-13. Monitor Mode Circuit (Internal Clock, No High Voltage) —
160
Diagram updated for clarity.
Figure 12-1. I/O Port Register Summary — Corrected bit definitions for PTA7,
105
DDRA7, and DDRA6.
Figure 12-2. Port A Data Register (PTA) — Corrected bit definition for PTA7. 106
Figure 12-3. Data Direction Register A (DDRA) — Corrected bit definitions for
107
DDRA7 and DDRA6.
Figure 12-6. Port B Data Register (PTB) — Corrected bit definition for PTB1 109
Section 9. Keyboard Interrupt Module (KBI) — Section reworked after
83
deletion of auto wakeup for clarity.
Section 4. Auto Wakeup Module (AWU) — New section added for clarity. 49
Figure 10-1. LVI Module Block Diagram — Corrected LVI stop representation. 91
Section 16. Electrical Specifications — Extensive changes made to electrical
169
specifications.
December, 17.5 8-Pin Dual Flat No Lead (DFN) Package (Case #1452) — Added case
0.1 187
2002 outline drawing for DFN package.
Section 17. Ordering Information and Mechanical Specifications — Added
185
ordering information for DFN package.
January,
0.2 4.2 Features — Corrected third bulleted item. 49
2003
Data Sheet MC68HC908QY/QT Family — Rev. 1
4 Revision History MOTOROLA

Revision History
Revision History (Continued)

Revision Page
Date Description
Level Number(s)
Reformatted to meet latest M68HC08 documentation standards N/A
Figure 1-1. Block Diagram — Diagram redrawn to include keyboard interrupt
20
module and TCLK pin designator.
Figure 1-2. MCU Pin Assignments — Added TCLK pin designator. 21
Table 1-2. Pin Functions — Added TCLK pin description. 22
Table 1-3. Function Priority in Shared Pins — Revised table for clarity and to
23
add TCLK.
Figure 2-1. Memory Map — Corrected names for the IRQ status and control
26
register (INTSCR) bits 3–0.
August,
1.0
2003 3.7.3 ADC Input Clock Register — Clarified bit description for the ADC clock
48
prescaler bits.
4.3 Functional Description — Updated periodic wakeup request values. 51
Figure 6-1. COP Block Diagram — Reworked for clarity 59
Section 8. External Interrupt (IRQ) — Corrected bit names for MODE, IRQF,
77–81
ACK, and IMASK
Section 14. Timer Interface Module (TIM) — Added TCLK function. 131–147
15.3 Monitor Module (MON) — Updated with additional data. 156
Section 16. Electrical Specifications — Updated with additional data. 169–183
MOTOROLA Revision History 5

Revision History
6 Revision History MOTOROLA

Data Sheet — MC68HC908QY/QT Family
List of Sections
Section 1. General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Section 2. Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Section 3. Analog-to-Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . 41
Section 4. Auto Wakeup Module (AWU) . . . . . . . . . . . . . . . . . . . . . . . . 49
Section 5. Configuration Register (CONFIG) . . . . . . . . . . . . . . . . . . . . 55
Section 6. Computer Operating Properly (COP) . . . . . . . . . . . . . . . . . 59
Section 7. Central Processor Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . 63
Section 8. External Interrupt (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Section 9. Keyboard Interrupt Module (KBI) . . . . . . . . . . . . . . . . . . . . 83
Section 10. Low-Voltage Inhibit (LVI) . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Section 11. Oscillator Module (OSC). . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Section 12. Input/Output Ports (PORTS) . . . . . . . . . . . . . . . . . . . . . . 105
Section 13. System Integration Module (SIM) . . . . . . . . . . . . . . . . . . 113
Section 14. Timer Interface Module (TIM) . . . . . . . . . . . . . . . . . . . . . . 131
Section 15. Development Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Section 16. Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . 169
Section 17. Ordering Information and Mechanical

Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
MOTOROLA List of Sections 7

List of Sections
8 List of Sections MOTOROLA

Table of Contents
Section 1. General Description

1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.3 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.4 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.5 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.6 Pin Function Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Section 2. Memory
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.2 Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.3 Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.4 Input/Output (I/O) Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.5 Random-Access Memory (RAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.6 FLASH Memory (FLASH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.6.1 FLASH Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.6.2 FLASH Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.6.3 FLASH Mass Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.6.4 FLASH Program Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.6.5 FLASH Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.6.6 FLASH Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.6.7 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2.6.8 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Section 3. Analog-to-Digital Converter (ADC)

3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.3.1 ADC Port I/O Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.3.2 Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.3.3 Conversion Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.3.4 Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.3.5 Accuracy and Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
MOTOROLA Table of Contents 9

Table of Contents
3.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.5.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.6 Input/Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.7 Input/Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.7.1 ADC Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.7.2 ADC Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.7.3 ADC Input Clock Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Section 4. Auto Wakeup Module (AWU)

4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.4 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.5 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.6.1 Port A I/O Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4.6.2 Keyboard Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . 52
4.6.3 Keyboard Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . 53
Section 5. Configuration Register (CONFIG)

5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Section 6. Computer Operating Properly (COP)

6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6.3 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
6.3.1 BUSCLKX4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
6.3.2 COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
6.3.3 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
6.3.4 Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
6.3.5 Reset Vector Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
6.3.6 COPD (COP Disable) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6.3.7 COPRS (COP Rate Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6.4 COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6.6 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6.7.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
6.8 COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
10 Table of Contents MOTOROLA

Table of Contents
Section 7. Central Processor Unit (CPU)

7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
7.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
7.3 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
7.3.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
7.3.2 Index Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
7.3.3 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
7.3.4 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
7.3.5 Condition Code Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
7.4 Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
7.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
7.5.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
7.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
7.6 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
7.7 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
7.8 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Section 8. External Interrupt (IRQ)

8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
8.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
8.4 IRQ Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
8.5 IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
8.6 IRQ Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Section 9. Keyboard Interrupt Module (KBI)

9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
9.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
9.3.1 Keyboard Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
9.3.2 Keyboard Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
9.4 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
9.5 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
9.6 Keyboard Module During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . 87
9.7.1 Keyboard Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . 88
9.7.2 Keyboard Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . 89

Table of Contents
Section 10. Low-Voltage Inhibit (LVI)

10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
10.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
10.3.1 Polled LVI Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
10.3.2 Forced Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
10.3.3 Voltage Hysteresis Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
10.3.4 LVI Trip Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
10.4 LVI Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
10.5 LVI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
10.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
10.6.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
10.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Section 11. Oscillator Module (OSC)

11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
11.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
11.3.1 Internal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
11.3.1.1 Internal Oscillator Trimming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
11.3.1.2 Internal to External Clock Switching . . . . . . . . . . . . . . . . . . . . . . . 97
11.3.2 External Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
11.3.3 XTAL Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
11.3.4 RC Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
11.4 Oscillator Module Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
11.4.1 Crystal Amplifier Input Pin (OSC1) . . . . . . . . . . . . . . . . . . . . . . . . . 100
11.4.2 Crystal Amplifier Output Pin (OSC2/PTA4/BUSCLKX4). . . . . . . . . 100
11.4.3 Oscillator Enable Signal (SIMOSCEN) . . . . . . . . . . . . . . . . . . . . . . 101
11.4.4 XTAL Oscillator Clock (XTALCLK) . . . . . . . . . . . . . . . . . . . . . . . . . 101
11.4.5 RC Oscillator Clock (RCCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
11.4.6 Internal Oscillator Clock (INTCLK) . . . . . . . . . . . . . . . . . . . . . . . . . 101
11.4.7 Oscillator Out 2 (BUSCLKX4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
11.4.8 Oscillator Out (BUSCLKX2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
11.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
11.5.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
11.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
11.6 Oscillator During Break Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
11.7 CONFIG2 Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
11.8 Input/Output (I/O) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
11.8.1 Oscillator Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
11.8.2 Oscillator Trim Register (OSCTRIM) . . . . . . . . . . . . . . . . . . . . . . . 104

Table of Contents
Section 12. Input/Output Ports (PORTS)

12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
12.2 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
12.2.1 Port A Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
12.2.2 Data Direction Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
12.2.3 Port A Input Pullup Enable Register . . . . . . . . . . . . . . . . . . . . . . . . 108
12.3 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
12.3.1 Port B Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
12.3.2 Data Direction Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
12.3.3 Port B Input Pullup Enable Register . . . . . . . . . . . . . . . . . . . . . . . . 111
Section 13. System Integration Module (SIM)

13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
13.2 RST and IRQ Pins Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
13.3 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . . . . . . . . 116
13.3.1 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
13.3.2 Clock Start-Up from POR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
13.3.3 Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . . . . . . . . 116
13.4 Reset and System Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
13.4.1 External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
13.4.2 Active Resets from Internal Sources . . . . . . . . . . . . . . . . . . . . . . . 117
13.4.2.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
13.4.2.2 Computer Operating Properly (COP) Reset . . . . . . . . . . . . . . . . 119
13.4.2.3 Illegal Opcode Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
13.4.2.4 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
13.4.2.5 Low-Voltage Inhibit (LVI) Reset . . . . . . . . . . . . . . . . . . . . . . . . . 120
13.5 SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
13.5.1 SIM Counter During Power-On Reset . . . . . . . . . . . . . . . . . . . . . . 120
13.5.2 SIM Counter During Stop Mode Recovery . . . . . . . . . . . . . . . . . . . 121
13.5.3 SIM Counter and Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
13.6 Exception Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
13.6.1 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
13.6.1.1 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
13.6.1.2 SWI Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
13.6.2 Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
13.6.2.1 Interrupt Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
13.6.3 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
13.6.4 Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
13.6.5 Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . . . . . . . 126
13.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
13.7.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
13.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Table of Contents
13.8 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

13.8.1 SIM Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
13.8.2 Break Flag Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Section 14. Timer Interface Module (TIM)

14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
14.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
14.3 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
14.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
14.4.1 TIM Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
14.4.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
14.4.3 Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
14.4.3.1 Unbuffered Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
14.4.3.2 Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
14.4.4 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
14.4.4.1 Unbuffered PWM Signal Generation. . . . . . . . . . . . . . . . . . . . . . 137
14.4.4.2 Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . 138
14.4.4.3 PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
14.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
14.6 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
14.7 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
14.8 Input/Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
14.8.1 TIM Clock Pin (PTA2/TCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
14.8.2 TIM Channel I/O Pins (PTA0/TCH0 and PTA1/TCH1) . . . . . . . . . . 140
14.9 Input/Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
14.9.1 TIM Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . 141
14.9.2 TIM Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
14.9.3 TIM Counter Modulo Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
14.9.4 TIM Channel Status and Control Registers . . . . . . . . . . . . . . . . . . 144
14.9.5 TIM Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Section 15. Development Support

15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
15.2 Break Module (BRK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
15.2.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
15.2.1.1 Flag Protection During Break Interrupts . . . . . . . . . . . . . . . . . . . 152
15.2.1.2 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
15.2.1.3 COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
15.2.2 Break Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
15.2.2.1 Break Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . 153
15.2.2.2 Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
15.2.2.3 Break Auxiliary Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
15.2.2.4 Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
15.2.2.5 Break Flag Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

Table of Contents
15.2.3 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

15.3 Monitor Module (MON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
15.3.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
15.3.1.1 Normal Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
15.3.1.2 Forced Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
15.3.1.3 Monitor Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
15.3.1.4 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
15.3.1.5 Break Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
15.3.1.6 Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
15.3.1.7 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
15.3.2 Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Section 16. Electrical Specifications

16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
16.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
16.3 Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
16.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
16.5 5-V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
16.6 Typical 5-V Output Drive Characteristics . . . . . . . . . . . . . . . . . . . . . . . 172
16.7 5-V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
16.8 5-V Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
16.9 3-V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
16.10 Typical 3.0-V Output Drive Characteristics. . . . . . . . . . . . . . . . . . . . . . 176
16.11 3-V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
16.12 3-V Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
16.13 Supply Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
16.14 Analog-to-Digital Converter Characteristics . . . . . . . . . . . . . . . . . . . . . 181
16.15 Timer Interface Module Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 182
16.16 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Section 17. Ordering Information

and Mechanical Specifications
17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
17.2 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
17.3 8-Pin Plastic Dual In-Line Package (Case #626) . . . . . . . . . . . . . . . . . 186
17.4 8-Pin Small Outline Integrated Circuit Package (Case #968). . . . . . . . 186
17.5 8-Pin Dual Flat No Lead (DFN) Package (Case #1452). . . . . . . . . . . . 187
17.6 16-Pin Plastic Dual In-Line Package (Case #648D) . . . . . . . . . . . . . . . 188
17.7 16-Pin Small Outline Integrated Circuit Package
(Case #751G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
17.8 16-Pin Thin Shrink Small Outline Package (Case #948F) . . . . . . . . . . 189

Table of Contents

Section 1. General Description
1.1 Introduction
The MC68HC908QY4 is a member of the low-cost, high-performance M68HC08
Family of 8-bit microcontroller units (MCUs). The M68HC08 Family is a Complex
Instruction Set Computer (CISC) with a Von Neumann architecture. All MCUs in
the family use the enhanced M68HC08 central processor unit (CPU08) and are
available with a variety of modules, memory sizes and types, and package types.
0.4
Table 1-1. Summary of Device Variations
FLASH Analog-to-Digital Pin
Device
Memory Size Converter Count
MC68HC908QT1 1536 bytes — 8 pins
MC68HC908QT2 1536 bytes 4 ch, 8 bit 8 pins
MC68HC908QT4 4096 bytes 4 ch, 8 bit 8 pins
MC68HC908QY1 1536 bytes — 16 pins
MC68HC908QY2 1536 bytes 4 ch, 8 bit 16 pins
MC68HC908QY4 4096 bytes 4 ch, 8 bit 16 pins
1.2 Features
Features include:
• High-performance M68HC08 CPU core
• Fully upward-compatible object code with M68HC05 Family
• 5-V and 3-V operating voltages (VDD)
• 8-MHz internal bus operation at 5 V, 4-MHz at 3 V
• Trimmable internal oscillator
– 3.2 MHz internal bus operation
– 8-bit trim capability allows 0.4% accuracy(1)
– ± 25% untrimmed
• Auto wakeup from STOP capability
• Configuration (CONFIG) register for MCU configuration options, including:
– Low-voltage inhibit (LVI) trip point
1. The oscillator frequency is guaranteed to ±5% over temperature and voltage range after trimming.
MOTOROLA General Description 17

General Description
• In-system FLASH programming

• FLASH security(1)
• On-chip in-application programmable FLASH memory (with internal
program/erase voltage generation)
– MC68HC908QY4 and MC68HC908QT4 — 4096 bytes
– MC68HC908QY2, MC68HC908QY1, MC68HC908QT2, and
MC68HC908QT1 — 1536 bytes
• 128 bytes of on-chip random-access memory (RAM)
• 2-channel, 16-bit timer interface module (TIM)
• 4-channel, 8-bit analog-to-digital converter (ADC) on MC68HC908QY2,
MC68HC908QY4, MC68HC908QT2, and MC68HC908QT4
• 5 or 13 bidirectional input/output (I/O) lines and one input only:
– Six shared with keyboard interrupt function and ADC
– Two shared with timer channels
– One shared with external interrupt (IRQ)
– Eight extra I/O lines on 16-pin package only
– High current sink/source capability on all port pins
– Selectable pullups on all ports, selectable on an individual bit basis
– Three-state ability on all port pins
• 6-bit keyboard interrupt with wakeup feature (KBI)
• Low-voltage inhibit (LVI) module features:
– Software selectable trip point in CONFIG register
• System protection features:
– Computer operating properly (COP) watchdog
– Low-voltage detection with reset
– Illegal opcode detection with reset
– Illegal address detection with reset
• External asynchronous interrupt pin with internal pullup (IRQ) shared with
general-purpose input pin
• Master asynchronous reset pin (RST) shared with general-purpose
input/output (I/O) pin
• Power-on reset
• Internal pullups on IRQ and RST to reduce external components
• Memory mapped I/O registers
• Power saving stop and wait modes
1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or

copying the FLASH difficult for unauthorized users.
18 General Description MOTOROLA

General Description
MCU Block Diagram
• MC68HC908QY4, MC68HC908QY2, and MC68HC908QY1 are available in

these packages:
– 16-pin plastic dual in-line package (PDIP)
– 16-pin small outline integrated circuit (SOIC) package
– 16-pin thin shrink small outline package (TSSOP)
• MC68HC908QT4, MC68HC908QT2, and MC68HC908QT1 are available in
these packages:
– 8-pin PDIP
– 8-pin SOIC
– 8-pin dual flat no lead (DFN) package
Features of the CPU08 include the following:

• Enhanced HC05 programming model
• Extensive loop control functions
• 16 addressing modes (eight more than the HC05)
• 16-bit index register and stack pointer
• Memory-to-memory data transfers
• Fast 8 × 8 multiply instruction
• Fast 16/8 divide instruction
• Binary-coded decimal (BCD) instructions
• Optimization for controller applications
• Efficient C language support
1.3 MCU Block Diagram

Figure 1-1 shows the structure of the MC68HC908QY4.
1.4 Pin Assignments

The MC68HC908QT4, MC68HC908QT2, and MC68HC908QT1 are available in
8-pin packages and the MC68HC908QY4, MC68HC908QY2, and
MC68HC908QY1 in 16-pin packages. Figure 1-2 shows the pin assignment for
these packages.

General Description
PTA0/AD0/TCH0/KBI0
CLOCK
PTA1/AD1/TCH1/KBI1 GENERATOR
PTA2/IRQ/KBI2/TCLK (OSCILLATOR)
DDRA
PTA
PTA3/RST/KBI3
PTA4/OSC2/AD2/KBI4 SYSTEM INTEGRATION
MODULE
PTA5/OSC1/AD3/KBI5
M68HC08 CPU
SINGLE INTERRUPT
PTB0 MODULE
PTB1
PTB2
BREAK
DDRB
PTB3
PTB
PTB4 MODULE
PTB5
PTB6 POWER-ON RESET
PTB7 MODULE
MC68HC908QY4 AND MC68HC908QT4 KEYBOARD INTERRUPT

8-BIT ADC 4096 BYTES MODULE
MC68HC908QY2, MC68HC908QY1,
MC68HC908QT2, AND MC68HC908QT1:
1536 BYTES 16-BIT TIMER
USER FLASH MODULE
128 BYTES RAM
COP
MODULE
VDD
POWER SUPPLY MONITOR ROM
VSS
RST, IRQ: Pins have internal (about 30K Ohms) pull up

PTA[0:5]: High current sink and source capability
PTA[0:5]: Pins have programmable keyboard interrupt and pull up
PTB[0:7]: Not available on 8-pin devices – MC68HC908QT1, MC68HC908QT2, and MC68HC908QT4
ADC: Not available on the MC68HC908QY1 and MC68HC908QT1
Figure 1-1. Block Diagram

General Description
Pin Assignments
VDD 1 8 VSS VDD 1 8 VSS
PTA5/OSC1/KBI5 2 7 PTA0/TCH0/KBI0 PTA5/OSC1/AD3/KBI5 2 7 PTA0/AD0/TCH0/KBI0

PTA3/RST/KBI3 4 5 PTA2/IRQ/KBI2/TCLK PTA3/RST/KBI3 4 5 PTA2/IRQ/KBI2/TCLK
8-PIN ASSIGNMENT 8-PIN ASSIGNMENT

MC68HC908QT1 PDIP/SOIC MC68HC908QT2 AND MC68HC908QT4 PDIP/SOIC
VDD 1 16 VSS VDD 1 16 VSS

PTB7 2 15 PTB0 PTB7 2 15 PTB0


PTA3/RST/KBI3 8 9 PTA2/IRQ/KBI2/TCLK PTA3/RST/KBI3 8 9 PTA2/IRQ/KBI2/TCLK

MC68HC908QY1 PDIP/SOIC MC68HC908QY2 AND MC68HC908QY4 PDIP/SOIC
PTA0/TCH0/KBI0 1 16 PTA1/TCH1/KBI1 PTA0/AD0/TCH0/KBI0 1 16 PTA1/AD1/TCH1/KBI1

VSS 4 13 PTA2/IRQ/KBI2/TCLK VSS 4 13 PTA2/IRQ/KBI2/TCLK
VDD 5 12 PTA3/RST/KBI3 VDD 5 12 PTA3/RST/KBI3
PTA5/OSC1/KBI5 8 9 PTA4/OSC2/KBI4 PTA5/OSC1/AD3/KBI5 8 9 PTA4/OSC2/AD2/KBI4
MC68HC908QY1 TSSOP MC68HC908QY2 AND MC68HC908QY4 TSSOP
PTA0/TCH0/KBI0 1 8 PTA1/TCH1/KBI1 PTA0/AD0/TCH0/KBI0 1 8 PTA1/AD1/TCH1/KBI1
VSS 2 7 PTA2/IRQ/KBI2/TCLK VSS 2 7 PTA2/IRQ/KBI2/TCLK

VDD 3 6 PTA3/RST/KBI3 VDD 3 6 PTA3/RST/KBI3
PTA5/OSC1/KB15 4 5 PTA4/OSC2/KBI4 PTA5//OSC1/AD3/KB15 4 5 PTA4/OSC2/AD2/KBI4

MC68HC908QT1 DFN MC68HC908QT2 AND MC68HC908QT4 DFN
Figure 1-2. MCU Pin Assignments

General Description
1.5 Pin Functions

Table 1-2 provides a description of the pin functions.
Table 1-2. Pin Functions

Pin
Description Input/Output
Name
VDD Power supply Power
VSS Power supply ground Power
PTA0 — General purpose I/O port Input/Output
AD0 — A/D channel 0 input Input
PTA0
TCH0 — Timer Channel 0 I/O Input/Output
KBI0 — Keyboard interrupt input 0 Input
PTA1
TCH1 — Timer Channel 1 I/O Input/Output
PTA2 — General purpose input-only port Input
IRQ — External interrupt with programmable pullup and Schmitt trigger input Input
PTA2
TCLK — Timer clock input Input
PTA3 RST — Reset input, active low with internal pullup and Schmitt trigger Input
OSC2 — XTAL oscillator output (XTAL option only) Output
PTA4 RC or internal oscillator output (OSC2EN = 1 in PTAPUE register) Output
OSC1 — XTAL, RC, or external oscillator input Input
PTA5
PTB[0:7](1) 8 general-purpose I/O ports Input/Output
1. The PTB pins are not available on the 8-pin packages.

General Description
Pin Function Priority
1.6 Pin Function Priority

Table 1-3 is meant to resolve the priority if multiple functions are enabled on a
single pin.
NOTE: Upon reset all pins come up as input ports regardless of the priority table.
Table 1-3. Function Priority in Shared Pins

Pin Name Highest-to-Lowest Priority Sequence
PTA0 AD0 → TCH0 → KBI0 → PTA0
PTA1 AD1 →TCH1 → KBI1 → PTA1
PTA2 IRQ → KBI2 → TCLK → PTA2
PTA3 RST → KBI3 → PTA3
PTA4 OSC2 → AD2 → KBI4 → PTA4
PTA5 OSC1 → AD3 → KBI5 → PTA5

General Description

Section 2. Memory
2.1 Introduction
The central processor unit (CPU08) can address 64 Kbytes of memory space. The
memory map, shown in Figure 2-1, includes:
• 4096 bytes of user FLASH for MC68HC908QT4 and MC68HC908QY4
• 1536 bytes of user FLASH for MC68HC908QT2, MC68HC908QT1,
MC68HC908QY2, and MC68HC908QY1
• 128 bytes of random access memory (RAM)
• 48 bytes of user-defined vectors, located in FLASH
• 416 bytes of monitor read-only memory (ROM)
• 1536 bytes of FLASH program and erase routines, located in ROM
2.2 Unimplemented Memory Locations

Accessing an unimplemented location can have unpredictable effects on MCU
operation. In Figure 2-1 and in register figures in this document, unimplemented
locations are shaded.
2.3 Reserved Memory Locations

Accessing a reserved location can have unpredictable effects on MCU operation.
In Figure 2-1 and in register figures in this document, reserved locations are
marked with the word Reserved or with the letter R.
MOTOROLA Memory 25
Memory
$0000
I/O REGISTERS
↓
64 BYTES
$003F
$0040
RESERVED(1)
↓
64 BYTES Note 1.
$007F
Attempts to execute code from addresses in this
$0080
RAM range will generate an illegal address reset.
↓
128 BYTES
$00FF
$0100
UNIMPLEMENTED(1)
↓
9984 BYTES
$27FF
$2800
AUXILIARY ROM
↓
1536 BYTES
$2DFF
$2E00 $2E00
UNIMPLEMENTED(1)
↓ UNIMPLEMENTED
$EDFF
49152 BYTES ↓
51712 BYTES
$F7FF
$EE00 FLASH MEMORY
$F800
↓ MC68HC908QT4 AND MC68HC908QY4 FLASH MEMORY
$FDFF 4096 BYTES ↓
1536 BYTES
$FDFF
$FE00 BREAK STATUS REGISTER (BSR) MC68HC908QT1, MC68HC908QT2,
$FE01 RESET STATUS REGISTER (SRSR) MC68HC908QY1, and MC68HC908QY2
$FE02 BREAK AUXILIARY REGISTER (BRKAR) Memory Map
$FE03 BREAK FLAG CONTROL REGISTER (BFCR)
$FE04 INTERRUPT STATUS REGISTER 1 (INT1)
$FE07 RESERVED FOR FLASH TEST CONTROL REGISTER (FLTCR)
$FE08 FLASH CONTROL REGISTER (FLCR)
$FE09 BREAK ADDRESS HIGH REGISTER (BRKH)
$FE0A BREAK ADDRESS LOW REGISTER (BRKL)
$FE0B BREAK STATUS AND CONTROL REGISTER (BRKSCR)
$FE0C LVISR
$FE0D
RESERVED FOR FLASH TEST
↓
3 BYTES
$FE0F
$FE10
↓ MONITOR ROM 416 BYTES
$FFAF
$FFB0
FLASH
↓
14 BYTES
$FFBD
$FFBE FLASH BLOCK PROTECT REGISTER (FLBPR)
$FFBF RESERVED FLASH
$FFC0 INTERNAL OSCILLATOR TRIM VALUE
$FFC1 RESERVED FLASH
$FFC2
FLASH
↓
14 BYTES
$FFCF
$FFD0
USER VECTORS
↓
48 BYTES
$FFFF
Figure 2-1. Memory Map
26 Memory MOTOROLA
Memory
Input/Output (I/O) Section
2.4 Input/Output (I/O) Section

Addresses $0000–$003F, shown in Figure 2-2, contain most of the control, status,
and data registers. Additional I/O registers have these addresses:
• $FE00 — Break status register, BSR
• $FE01 — Reset status register, SRSR
• $FE02 — Break auxiliary register, BRKAR
• $FE03 — Break flag control register, BFCR
• $FE04 — Interrupt status register 1, INT1
• $FE07 — Reserved
• $FE08 — FLASH control register, FLCR
• $FE09 — Break address register high, BRKH
• $FE0A — Break address register low, BRKL
• $FE0B — Break status and control register, BRKSCR
• $FE0C — LVI status register, LVISR
• $FE0D — Reserved
• $FFBE — FLASH block protect register, FLBPR
• $FFC0 — Internal OSC trim value — Optional
• $FFFF — COP control register, COPCTL
MOTOROLA Memory 27
Memory
Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0
Port A Data Register Read: R

AWUL
PTA5 PTA4 PTA3
PTA2
PTA1 PTA0
$0000 (PTA) Write:
See page 106. Reset: Unaffected by reset
Port B Data Register Read: PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0
$0001 (PTB) Write:
$0002 Unimplemented
$0003 Unimplemented
Data Direction Register A Read: R R DDRA5 DDRA4 DDRA3

0
DDRA1 DDRA0
$0004 (DDRA) Write:
See page 107. Reset: 0 0 0 0 0 0 0 0
Data Direction Register B Read:

DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0
$0005 (DDRB) Write:
See page 109. Reset: 0 0 0 0 0 0 0 0
$0006 Unimplemented
↓
$000A Unimplemented
Port A Input Pullup Enable Read: OSC2EN

0
PTAPUE5 PTAPUE4 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0
$000B Register (PTAPUE) Write:
See page 108. Reset: 0 0 0 0 0 0 0 0
Port B Input Pullup Enable Read: PTBPUE7 PTBPUE6 PTBPUE5 PTBPUE4 PTBPUE3 PTBPUE2 PTBPUE1 PTBPUE0
$000C Register (PTBPUE) Write:
See page 111. Reset: 0 0 0 0 0 0 0 0
$000D
↓ Unimplemented
$0019
Keyboard Status and Read: 0 0 0 0 KEYF 0

IMASKK MODEK
$001A Control Register (KBSCR) Write: ACKK
See page 88. Reset: 0 0 0 0 0 0 0 0
Keyboard Interrupt Read: 0

AWUIE KBIE5 KBIE4 KBIE3 KBIE2 KBIE1 KBIE0
$001B Enable Register (KBIER) Write:
See page 89. Reset: 0 0 0 0 0 0 0 0
= Unimplemented R = Reserved U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 5)
28 Memory MOTOROLA
Memory

$001C Unimplemented
IRQ Status and Control Read: 0 0 0 0 IRQF 0

IMASK MODE
$001D Register (INTSCR) Write: ACK
See page 81. Reset: 0 0 0 0 0 0 0 0
Configuration Register 2 Read: IRQPUD IRQEN R OSCOPT1 OSCOPT0 R R RSTEN

$001E (CONFIG2)(1) Write:
See page 56. Reset: 0 0 0 0 0 0 0 0(2)
1. One-time writable register after each reset.
2. RSTEN reset to 0 by a power-on reset (POR) only.
Configuration Register 1 Read: COPRS LVISTOP LVIRSTD LVIPWRD LVI5OR3 SSREC STOP COPD
$001F (CONFIG1)(1) Write:
See page 56. Reset: 0 0 0 0 0(2) 0 0 0
1. One-time writable register after each reset.
2. LVI5OR3 reset to 0 by a power-on reset (POR) only.
TIM Status and Control Read: TOF

TOIE TSTOP
0 0
PS2 PS1 PS0
$0020 Register (TSC) Write: 0 TRST
See page 141. Reset: 0 0 1 0 0 0 0 0
TIM Counter Register High Read: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
$0021 (TCNTH) Write:
See page 143. Reset: 0 0 0 0 0 0 0 0
TIM Counter Register Low Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$0022 (TCNTL) Write:
See page 143. Reset: 0 0 0 0 0 0 0 0
TIM Counter Modulo Read: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
$0023 Register High (TMODH) Write:
See page 143. Reset: 1 1 1 1 1 1 1 1
TIM Counter Modulo Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$0024 Register Low (TMODL) Write:
See page 143. Reset: 1 1 1 1 1 1 1 1
TIM Channel 0 Status and Read: CH0F

CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX
$0025 Control Register (TSC0) Write: 0
See page 144. Reset: 0 0 0 0 0 0 0 0
TIM Channel 0 Read:

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
$0026 Register High (TCH0H) Write:
See page 147. Reset: Indeterminate after reset
MOTOROLA Memory 29
Memory
TIM Channel 0 Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$0027 Register Low (TCH0L) Write:
TIM Channel 1 Status and Read: CH1F

CH1IE
0
MS1A ELS1B ELS1A TOV1 CH1MAX
See page 144. Reset: 0 0 0 0 0 0 0 0
$0029 Register High (TCH1H) Write:
$002A Register Low (TCH1L) Write:
$002B
↓ Unimplemented
$0035
Oscillator Status Register Read: R R R R R R ECGON

ECGST
$0036 (OSCSTAT) Write:
See page 103. Reset: 0 0 0 0 0 0 0 0
$0037 Unimplemented Read:
Oscillator Trim Register Read:

(OSCTRIM) TRIM7 TRIM6 TRIM5 TRIM4 TRIM3 TRIM2 TRIM1 TRIM0
$0038 Write:
See page 104.
Reset: 1 0 0 0 0 0 0 0
$0039
↓ Unimplemented
$003B
ADC Status and Control Read: COCO

AIEN ADCO CH4 CH3 CH2 CH1 CH0
$003C Register (ADSCR) Write:
See page 46. Reset: 0 0 0 1 1 1 1 1
$003D Unimplemented
ADC Data Register Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$003E (ADR) Write:
30 Memory MOTOROLA
Memory
ADC Input Clock Register Read: ADIV2 ADIV1 ADIV0

0 0 0 0 0
$003F (ADICLK) Write:
See page 48. Reset: 0 0 0 0 0 0 0 0
Break Status Register Read: R R R R R R

SBSW
R
$FE00 (BSR) Write: See note 1
See page 155. Reset: 0
1. Writing a 0 clears SBSW.
SIM Reset Status Register Read: POR PIN COP ILOP ILAD MODRST LVI 0
$FE01 (SRSR) Write:
See page 129. POR: 1 0 0 0 0 0 0 0
Break Auxiliary Read: 0 0 0 0 0 0 0

BDCOP
$FE02 Register (BRKAR) Write:
See page 154. Reset: 0 0 0 0 0 0 0 0
Break Flag Control Read: BCFE R R R R R R R

$FE03 Register (BFCR) Write:
See page 155. Reset: 0
Interrupt Status Register 1 Read: 0 IF5 IF4 IF3 0 IF1 0 0

$FE04 (INT1) Write: R R R R R R R R
See page 81. Reset: 0 0 0 0 0 0 0 0
Interrupt Status Register 2 Read: IF14 0 0 0 0 0 0 0

See page 81. Reset: 0 0 0 0 0 0 0 0
Interrupt Status Register 3 Read: 0 0 0 0 0 0 0 IF15

See page 81. Reset: 0 0 0 0 0 0 0 0
$FE07 Reserved R R R R R R R R
FLASH Control Register Read: 0 0 0 0

HVEN MASS ERASE PGM
$FE08 (FLCR) Write:
See page 34. Reset: 0 0 0 0 0 0 0 0
Break Address High Read:

$FE09 Register (BRKH) Write:
See page 154. Reset: 0 0 0 0 0 0 0 0
Break Address low Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$FE0A Register (BRKL) Write:
See page 154. Reset: 0 0 0 0 0 0 0 0
MOTOROLA Memory 31
Memory
Break Status and Control Read: BRKE BRKA

0 0 0 0 0 0
$FE0B Register (BRKSCR) Write:
See page 153. Reset: 0 0 0 0 0 0 0 0
LVI Status Register Read: LVIOUT 0 0 0 0 0 0 R

$FE0C (LVISR) Write:
See page 93. Reset: 0 0 0 0 0 0 0 0
$FE0D
↓ Reserved for FLASH Test R R R R R R R R
$FE0F
$FFB0
↓ Unimplemented
$FFBD
FLASH Block Protect Read: BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0
$FFBE Register (FLBPR) Write:
See page 39. Reset: 0 0 0 0 0 0 0 0
$FFBF Unimplemented
Read:
Internal Oscillator Trim TRIM7 TRIM6 TRIM5 TRIM4 TRIM3 TRIM2 TRIM1 TRIM0
$FFC0 Write:
Value (Optional)
Reset: 1 0 0 0 0 0 0 0
$FFC1 Reserved R R R R R R R R
$FFC2
↓ Unimplemented
$FFCF
COP Control Register Read: LOW BYTE OF RESET VECTOR

$FFFF (COPCTL) Write: WRITING CLEARS COP COUNTER (ANY VALUE)
32 Memory MOTOROLA
Memory
Random-Access Memory (RAM)
Table 2-1. Vector Addresses

Vector Priority Vector Address Vector
Lowest $FFDE ADC conversion complete vector (high)
IF15
$FFDF ADC conversion complete vector (low)
$FFE0 Keyboard vector (high)
IF14
$FFE1 Keyboard vector (low)
IF13
↓ — Not used
IF6
$FFF2 TIM overflow vector (high)
IF5
$FFF3 TIM overflow vector (low)
$FFF4 TIM Channel 1 vector (high)
IF4
$FFF5 TIM Channel 1 vector (low)
$FFF6 TIM Channel 0 vector (high)
IF3
$FFF7 TIM Channel 0 vector (low)
IF2 — Not used
$FFFA IRQ vector (high)
IF1
$FFFB IRQ vector (low)
$FFFC SWI vector (high)
—
$FFFD SWI vector (low)
$FFFE Reset vector (high)
—
Highest $FFFF Reset vector (low)
2.5 Random-Access Memory (RAM)

Addresses $0080–$00FF are RAM locations. The location of the stack RAM is
programmable. The 16-bit stack pointer allows the stack to be anywhere in the
64-Kbyte memory space.
NOTE: For correct operation, the stack pointer must point only to RAM locations.
Before processing an interrupt, the central processor unit (CPU) uses five bytes of
the stack to save the contents of the CPU registers.
NOTE: For M6805, M146805, and M68HC05 compatibility, the H register is not stacked.
During a subroutine call, the CPU uses two bytes of the stack to store the return
address. The stack pointer decrements during pushes and increments during pulls.
NOTE: Be careful when using nested subroutines. The CPU may overwrite data in the
RAM during a subroutine or during the interrupt stacking operation.
MOTOROLA Memory 33
Memory
2.6 FLASH Memory (FLASH)

This subsection describes the operation of the embedded FLASH memory. The
FLASH memory can be read, programmed, and erased from a single external
supply. The program and erase operations are enabled through the use of an
internal charge pump.
The FLASH memory consists of an array of 4096 or 1536 bytes with an additional
48 bytes for user vectors. The minimum size of FLASH memory that can be erased
is 64 bytes; and the maximum size of FLASH memory that can be programmed in
a program cycle is 32 bytes (a row). Program and erase operations are facilitated
through control bits in the FLASH control register (FLCR). Details for these
operations appear later in this section. The address ranges for the user memory
and vectors are:
• $EE00 – $FDFF; user memory, 4096 bytes: MC68HC908QY4 and
MC68HC908QT4
• $F800 – $FDFF; user memory, 1536 bytes: MC68HC908QY2,
MC68HC908QT2, MC68HC908QY1 and MC68HC908QT1
• $FFD0 – $FFFF; user interrupt vectors, 48 bytes.
NOTE: An erased bit reads as a 1 and a programmed bit reads as a 0. A security feature
prevents viewing of the FLASH contents.(1)
2.6.1 FLASH Control Register
The FLASH control register (FLCR) controls FLASH program and erase
operations.
Address: $FE08
Bit 7 6 5 4 3 2 1 Bit 0
Read: 0 0 0 0
HVEN MASS ERASE PGM
Write:
Reset: 0 0 0 0 0 0 0 0
Figure 2-3. FLASH Control Register (FLCR)
HVEN — High Voltage Enable Bit

This read/write bit enables high voltage from the charge pump to the memory
for either program or erase operation. It can only be set if either PGM =1 or
ERASE =1 and the proper sequence for program or erase is followed.
1 = High voltage enabled to array and charge pump on
0 = High voltage disabled to array and charge pump off

34 Memory MOTOROLA
Memory
FLASH Memory (FLASH)
MASS — Mass Erase Control Bit

This read/write bit configures the memory for mass erase operation.
1 = Mass erase operation selected
0 = Mass erase operation unselected
ERASE — Erase Control Bit
This read/write bit configures the memory for erase operation. ERASE is
interlocked with the PGM bit such that both bits cannot be equal to 1 or set to 1
at the same time.
1 = Erase operation selected
0 = Erase operation unselected
PGM — Program Control Bit
This read/write bit configures the memory for program operation. PGM is
interlocked with the ERASE bit such that both bits cannot be equal to 1 or set
to 1 at the same time.
1 = Program operation selected
0 = Program operation unselected
2.6.2 FLASH Page Erase Operation

Use the following procedure to erase a page of FLASH memory. A page consists
of 64 consecutive bytes starting from addresses $XX00, $XX40, $XX80, or $XXC0.
The 48-byte user interrupt vectors area also forms a page. Any FLASH memory
page can be erased alone.
1. Set the ERASE bit and clear the MASS bit in the FLASH control register.
2. Read the FLASH block protect register.
3. Write any data to any FLASH location within the address range of the block
to be erased.
4. Wait for a time, tNVS (minimum 10 µs).
5. Set the HVEN bit.
6. Wait for a time, tErase (minimum 1 ms or 4 ms).
7. Clear the ERASE bit.
8. Wait for a time, tNVH (minimum 5 µs).
9. Clear the HVEN bit.
10. After time, tRCV (typical 1 µs), the memory can be accessed in read mode
again.
NOTE: Programming and erasing of FLASH locations cannot be performed by code being
executed from the FLASH memory. While these operations must be performed in
the order as shown, but other unrelated operations may occur between the steps.
CAUTION: A page erase of the vector page will erase the internal oscillator trim value at
$FFC0.
MOTOROLA Memory 35
Memory
In applications that require more than 1000 program/erase cycles, use the 4 ms
page erase specification to get improved long-term reliability. Any application can
use this 4 ms page erase specification. However, in applications where a FLASH
location will be erased and reprogrammed less than 1000 times, and speed is
important, use the 1 ms page erase specification to get a shorter cycle time.
2.6.3 FLASH Mass Erase Operation
Use the following procedure to erase the entire FLASH memory to read as a 1:
1. Set both the ERASE bit and the MASS bit in the FLASH control register.
3. Write any data to any FLASH address(1) within the FLASH memory address
range.
6. Wait for a time, tMErase (minimum 4 ms).
7. Clear the ERASE and MASS bits.
NOTE: Mass erase is disabled whenever any block is protected (FLBPR does not equal
$FF).
8. Wait for a time, tNVHL (minimum 100 µs).

again.
the order as shown, but other unrelated operations may occur between the steps.
CAUTION: A mass erase will erase the internal oscillator trim value at $FFC0.
2.6.4 FLASH Program Operation
Programming of the FLASH memory is done on a row basis. A row consists of 32

consecutive bytes starting from addresses $XX00, $XX20, $XX40, $XX60, $XX80,
$XXA0, $XXC0, or $XXE0. Use the following step-by-step procedure to program a
row of FLASH memory
Figure 2-4 shows a flowchart of the programming algorithm.

NOTE: Only bytes which are currently $FF may be programmed.
1. When in monitor mode, with security sequence failed (see 15.3.2 Security), write to the FLASH
block protect register instead of any FLASH address.
36 Memory MOTOROLA
Memory
1. Set the PGM bit. This configures the memory for program operation and
enables the latching of address and data for programming.
3. Write any data to any FLASH location within the address range desired.
6. Wait for a time, tPGS (minimum 5 µs).
7. Write data to the FLASH address being programmed(1).
8. Wait for time, tPROG (minimum 30 µs).
9. Repeat step 7 and 8 until all desired bytes within the row are programmed.
10. Clear the PGM bit(1).
11. Wait for time, tNVH (minimum 5 µs).
again.
NOTE: The COP register at location $FFFF should not be written between steps 5-12,
when the HVEN bit is set. Since this register is located at a valid FLASH address,
unpredictable behavior may occur if this location is written while HVEN is set.
This program sequence is repeated throughout the memory until all data is
programmed.
the order shown, other unrelated operations may occur between the steps. Do not
exceed tPROG maximum, see 16.16 Memory Characteristics.
2.6.5 FLASH Protection
Due to the ability of the on-board charge pump to erase and program the FLASH
memory in the target application, provision is made to protect blocks of memory
from unintentional erase or program operations due to system malfunction. This
protection is done by use of a FLASH block protect register (FLBPR). The FLBPR
determines the range of the FLASH memory which is to be protected. The range
of the protected area starts from a location defined by FLBPR and ends to the
bottom of the FLASH memory ($FFFF). When the memory is protected, the HVEN
bit cannot be set in either ERASE or PROGRAM operations.
NOTE: In performing a program or erase operation, the FLASH block protect register must
be read after setting the PGM or ERASE bit and before asserting the HVEN bit.
1. The time between each FLASH address change, or the time between the last FLASH address
programmed to clearing PGM bit, must not exceed the maximum programming time, tPROG
maximum.
MOTOROLA Memory 37
Memory
Algorithm for Programming 1

SET PGM BIT
a Row (32 Bytes) of FLASH Memory
2 READ THE FLASH BLOCK PROTECT REGISTER
3 WRITE ANY DATA TO ANY FLASH ADDRESS

WITHIN THE ROW ADDRESS RANGE DESIRED
4
WAIT FOR A TIME, tNVS
5
SET HVEN BIT
6
WAIT FOR A TIME, tPGS
7
WRITE DATA TO THE FLASH ADDRESS
TO BE PROGRAMMED
8
WAIT FOR A TIME, tPROG
COMPLETED
Y
9 PROGRAMMING
THIS ROW?
10 CLEAR PGM BIT
11
WAIT FOR A TIME, tNVH
NOTES: 12
CLEAR HVEN BIT
The time between each FLASH address change (step 7 to step 7),
or the time between the last FLASH address programmed
13
to clearing PGM bit (step 7 to step 10) WAIT FOR A TIME, tRCV
must not exceed the maximum programming
time, tPROG max.
This row program algorithm assumes the row/s END OF PROGRAMMING

to be programmed are initially erased.
Figure 2-4. FLASH Programming Flowchart
38 Memory MOTOROLA
Memory
When the FLBPR is programmed with all 0 s, the entire memory is protected from
being programmed and erased. When all the bits are erased (all 1’s), the entire
memory is accessible for program and erase.
When bits within the FLBPR are programmed, they lock a block of memory. The
address ranges are shown in 2.6.6 FLASH Block Protect Register. Once the
FLBPR is programmed with a value other than $FF, any erase or program of the
FLBPR or the protected block of FLASH memory is prohibited. Mass erase is
disabled whenever any block is protected (FLBPR does not equal $FF). The
FLBPR itself can be erased or programmed only with an external voltage, VTST,
present on the IRQ pin. This voltage also allows entry from reset into the monitor
mode.
2.6.6 FLASH Block Protect Register
The FLASH block protect register is implemented as a byte within the FLASH
memory, and therefore can only be written during a programming sequence of the
FLASH memory. The value in this register determines the starting address of the
protected range within the FLASH memory.
Address: $FFBE
Bit 7 6 5 4 3 2 1 Bit 0
Read:
BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0
Write:
Reset: U U U U U U U U
U = Unaffected by reset. Initial value from factory is 1.
Write to this register is by a programming sequence to the FLASH memory.
Figure 2-5. FLASH Block Protect Register (FLBPR)
BPR[7:0] — FLASH Protection Register Bits [7:0]

These eight bits in FLBPR represent bits [13:6] of a 16-bit memory address. Bits
[15:14] are 1s and bits [5:0] are 0s.
The resultant 16-bit address is used for specifying the start address of the
FLASH memory for block protection. The FLASH is protected from this start
address to the end of FLASH memory, at $FFFF. With this mechanism, the
protect start address can be XX00, XX40, XX80, or XXC0 within the FLASH
memory. See Figure 2-6 and Table 2-2.
16-BIT MEMORY ADDRESS
START ADDRESS OF 1 1 FLBPR VALUE 0 0 0 0 0 0

FLASH BLOCK PROTECT
Figure 2-6. FLASH Block Protect Start Address
MOTOROLA Memory 39
Memory
Table 2-2. Examples of Protect Start Address

BPR[7:0] Start of Address of Protect Range
$00–$B8 The entire FLASH memory is protected.
$B9 (1011 1001) $EE40 (1110 1110 0100 0000)
$BA (1011 1010) $EE80 (1110 1110 1000 0000)
$BB (1011 1011) $EEC0 (1110 1110 1100 0000)
$BC (1011 1100) $EF00 (1110 1111 0000 0000)
and so on...
$DE (1101 1110) $F780 (1111 0111 1000 0000)
$DF (1101 1111) $F7C0 (1111 0111 1100 0000)
$FF80 (1111 1111 1000 0000)
$FE (1111 1110)
FLBPR, OSCTRIM, and vectors are protected
$FF The entire FLASH memory is not protected.
2.6.7 Wait Mode
Putting the MCU into wait mode while the FLASH is in read mode does not affect
the operation of the FLASH memory directly, but there will not be any memory
activity since the CPU is inactive.
The WAIT instruction should not be executed while performing a program or erase
operation on the FLASH, or the operation will discontinue and the FLASH will be
on standby mode.
2.6.8 Stop Mode
Putting the MCU into stop mode while the FLASH is in read mode does not affect
the operation of the FLASH memory directly, but there will not be any memory
activity since the CPU is inactive.
The STOP instruction should not be executed while performing a program or erase
operation on the FLASH, or the operation will discontinue and the FLASH will be
on standby mode
NOTE: Standby mode is the power-saving mode of the FLASH module in which all internal
control signals to the FLASH are inactive and the current consumption of the
FLASH is at a minimum.
40 Memory MOTOROLA
Section 3. Analog-to-Digital Converter (ADC)
3.1 Introduction
This section describes the analog-to-digital converter (ADC). The ADC is an 8-bit,
4-channel analog-to-digital converter. The ADC module is only available on the
MC68HC908QY2, MC68HC908QT2, MC68HC908QY4, and MC68HC908QT4.
3.2 Features
Features of the ADC module include:
• 4 channels with multiplexed input
• Linear successive approximation with monotonicity
• 8-bit resolution
• Single or continuous conversion
• Conversion complete flag or conversion complete interrupt
• Selectable ADC clock frequency
Figure 3-1 provides a summary of the input/output (I/O) registers.
ADC Status and Control Read: COCO

$003C Register (ADSCR) Write:
See page 46. Reset: 0 0 0 1 1 1 1 1
$003D Unimplemented
ADC Data Register Read: AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
$003E (ADR) Write:
ADC Input Clock Register Read: 0 0 0 0 0

ADIV2 ADIV1 ADIV0
$003F (ADICLK) Write:
See page 48. Reset: 0 0 0 0 0 0 0 0
= Unimplemented
Figure 3-1. ADC I/O Register Summary
MOTOROLA Analog-to-Digital Converter (ADC) 41

Analog-to-Digital Converter (ADC)
PTA0/AD0/TCH0/KBI0
CLOCK
DDRA
PTA
PTA3/RST/KBI3
MODULE
PTA5/OSC1/AD3/KBI5
M68HC08 CPU
SINGLE INTERRUPT
PTB0 MODULE
PTB1
PTB2
BREAK
DDRB
PTB3
PTB
PTB4 MODULE
PTB5
PTB6 POWER-ON RESET
PTB7 MODULE

USER FLASH MODULE
128 BYTES RAM
COP
MODULE
VDD
VSS

Figure 3-2. Block Diagram Highlighting ADC Block and Pins
42 Analog-to-Digital Converter (ADC) MOTOROLA

Functional Description
3.3 Functional Description

Four ADC channels are available for sampling external sources at pins PTA0,
PTA1, PTA4, and PTA5. An analog multiplexer allows the single ADC converter to
select one of the four ADC channels as an ADC voltage input (ADCVIN). ADCVIN
is converted by the successive approximation register-based counters. The ADC
resolution is eight bits. When the conversion is completed, ADC puts the result in
the ADC data register and sets a flag or generates an interrupt.
Figure 3-3 shows a block diagram of the ADC.
INTERNAL
DATA BUS
READ DDRA
WRITE DDRA DISABLE
DDRAx
RESET
WRITE PTA
PTAx ADCx
READ PTA
DISABLE
ADC CHANNEL x
ADC DATA REGISTER
CONVERSION ADC VOLTAGE IN

INTERRUPT COMPLETE ADCVIN CHANNEL
ADC SELECT CH[4:0]
LOGIC
(1 OF 4 CHANNELS)
AIEN COCO ADC CLOCK
CLOCK
BUS CLOCK GENERATOR
ADIV[2:0]
Figure 3-3. ADC Block Diagram

3.3.1 ADC Port I/O Pins
PTA0, PTA1, PTA4, and PTA5 are general-purpose I/O pins that are shared with
the ADC channels. The channel select bits (ADC status and control register
(ADSCR), $003C), define which ADC channel/port pin will be used as the input
signal. The ADC overrides the port I/O logic by forcing that pin as input to the ADC.
The remaining ADC channels/port pins are controlled by the port I/O logic and can
be used as general-purpose I/O. Writes to the port register or data direction register
(DDR) will not have any affect on the port pin that is selected by the ADC. Read of
a port pin which is in use by the ADC will return a 0 if the corresponding DDR bit is
at 0. If the DDR bit is at 1, the value in the port data latch is read.
3.3.2 Voltage Conversion
When the input voltage to the ADC equals VDD, the ADC converts the signal to $FF
(full scale). If the input voltage equals VSS, the ADC converts it to $00. Input
voltages between VDD and VSS are a straight-line linear conversion. All other input
voltages will result in $FF if greater than VDD and $00 if less than VSS.
NOTE: Input voltage should not exceed the analog supply voltages.
3.3.3 Conversion Time
Sixteen ADC internal clocks are required to perform one conversion. The ADC
starts a conversion on the first rising edge of the ADC internal clock immediately
following a write to the ADSCR. If the ADC internal clock is selected to run at
1 MHz, then one conversion will take 16 µs to complete. With a 1-MHz ADC
internal clock the maximum sample rate is 62.5 kHz.
16 ADC Clock Cycles
Conversion Time =
ADC Clock Frequency
Number of Bus Cycles = Conversion Time × Bus Frequency
3.3.4 Continuous Conversion
In the continuous conversion mode (ADCO = 1), the ADC continuously converts
the selected channel filling the ADC data register (ADR) with new data after each
conversion. Data from the previous conversion will be overwritten whether that
data has been read or not. Conversions will continue until the ADCO bit is cleared.
The COCO bit (ADSCR, $003C) is set after each conversion and will stay set until
the next read of the ADC data register.
When a conversion is in process and the ADSCR is written, the current conversion
data should be discarded to prevent an incorrect reading.
3.3.5 Accuracy and Precision
The conversion process is monotonic and has no missing codes.

Interrupts
3.4 Interrupts
When the AIEN bit is set, the ADC module is capable of generating a central
processor unit (CPU) interrupt after each ADC conversion. A CPU interrupt is
generated if the COCO bit is at 0. The COCO bit is not used as a conversion
complete flag when interrupts are enabled.
3.5 Low-Power Modes

The following subsections describe the ADC in low-power modes.
3.5.1 Wait Mode
The ADC continues normal operation during wait mode. Any enabled CPU interrupt
request from the ADC can bring the microcontroller unit (MCU) out of wait mode. If
the ADC is not required to bring the MCU out of wait mode, power down the ADC
by setting the CH[4:0] bits in ADSCR to 1s before executing the WAIT instruction.
3.5.2 Stop Mode
The ADC module is inactive after the execution of a STOP instruction. Any pending
conversion is aborted. ADC conversions resume when the MCU exits stop mode.
Allow one conversion cycle to stabilize the analog circuitry before using ADC data
after exiting stop mode.
3.6 Input/Output Signals

The ADC module has four channels that are shared with I/O port A.
ADC voltage in (ADCVIN) is the input voltage signal from one of the four ADC
channels to the ADC module.
3.7 Input/Output Registers

These I/O registers control and monitor ADC operation:
• ADC status and control register (ADSCR)
• ADC data register (ADR)
• ADC clock register (ADICLK)

3.7.1 ADC Status and Control Register
The following paragraphs describe the function of the ADC status and control
register (ADSCR). When a conversion is in process and the ADSCR is written, the
current conversion data should be discarded to prevent an incorrect reading.
Address: $003C
Bit 7 6 5 4 3 2 1 Bit 0
Read: COCO
Write:
Reset: 0 0 0 1 1 1 1 1
= Unimplemented
Figure 3-4. ADC Status and Control Register (ADSCR)
COCO — Conversions Complete Bit

In non-interrupt mode (AIEN = 0), COCO is a read-only bit that is set at the end
of each conversion. COCO will stay set until cleared by a read of the ADC data
register. Reset clears this bit.
In interrupt mode (AIEN = 1), COCO is a read-only bit that is not set at the end
of a conversion. It always reads as a 0.
1 = Conversion completed (AIEN = 0)
0 = Conversion not completed (AIEN = 0) or CPU interrupt enabled
(AIEN = 1)
NOTE: The write function of the COCO bit is reserved. When writing to the ADSCR
register, always have a 0 in the COCO bit position.
AIEN — ADC Interrupt Enable Bit

When this bit is set, an interrupt is generated at the end of an ADC conversion.
The interrupt signal is cleared when ADR is read or ADSCR is written. Reset
clears the AIEN bit.
1 = ADC interrupt enabled
0 = ADC interrupt disabled
ADCO — ADC Continuous Conversion Bit
When set, the ADC will convert samples continuously and update ADR at the
end of each conversion. Only one conversion is allowed when this bit is cleared.
Reset clears the ADCO bit.
1 = Continuous ADC conversion
0 = One ADC conversion
CH[4:0] — ADC Channel Select Bits
CH4, CH3, CH2, CH1, and CH0 form a 5-bit field which is used to select one of
the four ADC channels. The five select bits are detailed in Table 3-1. Care
should be taken when using a port pin as both an analog and a digital input
simultaneously to prevent switching noise from corrupting the analog signal.

Input/Output Registers
The ADC subsystem is turned off when the channel select bits are all set to 1.
This feature allows for reduced power consumption for the MCU when the ADC
is not used. Reset sets all of these bits to 1.
NOTE: Recovery from the disabled state requires one conversion cycle to stabilize.
Table 3-1. MUX Channel Select

ADC
CH4 CH3 CH2 CH1 CH0 Input Select
Channel
0 0 0 0 0 ADC0 PTA0
0 0 0 0 1 ADC1 PTA1
0 0 0 1 0 ADC2 PTA4
0 0 0 1 1 ADC3 PTA5
0 0 1 0 0 —
↓ ↓ ↓ ↓ ↓ — Unused(1)
1 1 0 1 0 —
1 1 0 1 1 — Reserved
1 1 1 0 0 — Unused
1 1 1 0 1 — VDDA(2)
1 1 1 1 0 — VSSA(2)
1 1 1 1 1 — ADC power off
1. If any unused channels are selected, the resulting ADC conversion will be
unknown.
2. The voltage levels supplied from internal reference nodes, as specified in the
table, are used to verify the operation of the ADC converter both in produc-
tion test and for user applications.
3.7.2 ADC Data Register
One 8-bit result register is provided. This register is updated each time an ADC
conversion completes.
Address: $003E
Bit 7 6 5 4 3 2 1 Bit 0
Read: AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
Write:
Reset: Indeterminate after reset
= Unimplemented
Figure 3-5. ADC Data Register (ADR)

3.7.3 ADC Input Clock Register
This register selects the clock frequency for the ADC.
Address: $003F
Bit 7 6 5 4 3 2 1 Bit 0
Read: 0 0 0 0 0
ADIV2 ADIV1 ADIV0
Write:
Reset: 0 0 0 0 0 0 0 0
= Unimplemented
Figure 3-6. ADC Input Clock Register (ADICLK)
ADIV2–ADIV0 — ADC Clock Prescaler Bits

ADIV2, ADIV1, and ADIV0 form a 3-bit field which selects the divide ratio used
by the ADC to generate the internal ADC clock. Table 3-2 shows the available
clock configurations. The ADC clock frequency should be set between fADIC(MIN)
and fADIC(MAX). The analog input level should remain stable for the entire
conversion time (maximum = 17 ADC clock cycles).
Table 3-2. ADC Clock Divide Ratio

ADIV2 ADIV1 ADIV0 ADC Clock Rate
0 0 0 Bus clock ÷ 1
1 X X Bus clock ÷ 16
X = don’t care

Section 4. Auto Wakeup Module (AWU)
4.1 Introduction
This section describes the auto wakeup module (AWU). The AWU generates a
periodic interrupt during stop mode to wake the part up without requiring an
external signal. Figure 4-2 is a block diagram of the AWU.
4.2 Features
Features of the auto wakeup module include:
• One internal interrupt with separate interrupt enable bit, sharing the same
keyboard interrupt vector and keyboard interrupt mask bit
• Exit from low-power stop mode without external signals
• Selectable timeout periods
• Dedicated low-power internal oscillator separate from the main system clock
sources
Figure 4-1 provides a summary of the input/output (I/O) registers used in

conjuction with the AWU.
Port A Data Register Read: 0 AWUL

PTA5 PTA4 PTA3
PTA2
PTA1 PTA0
$0000 (PTA) Write:
Keyboard Status Read: 0 0 0 0 KEYF 0
and Control Register Write: IMASKK MODEK
$001A ACKK
(KBSCR)
See page 52. Reset: 0 0 0 0 0 0 0 0
Keyboard Interrupt Enable Read: 0

$001B Register (KBIER) Write:
See page 53. Reset: 0 0 0 0 0 0 0 0
= Unimplemented
Figure 4-1. AWU Register Summary
MOTOROLA Auto Wakeup Module (AWU) 49

Auto Wakeup Module (AWU)

The function of the auto wakeup logic is to generate periodic wakeup requests to
bring the microcontroller unit (MCU) out of stop mode. The wakeup requests are
treated as regular keyboard interrupt requests, with the difference that instead of a
pin, the interrupt signal is generated by an internal logic.
Writing the AWUIE bit in the keyboard interrupt enable register enables or disables
the auto wakeup interrupt input (see Figure 4-2). A logic 1 applied to the
AWUIREQ input with auto wakeup interrupt request enabled, latches an auto
wakeup interrupt request.
Auto wakeup latch, AWUL, can be read directly from the bit 6 position of port A data
register (PTA). This is a read-only bit which is occupying an empty bit position on
PTA. No PTA associated registers, such as PTA6 data direction or PTA6 pullup
exist for this bit.
Entering stop mode will enable the auto wakeup generation logic. An internal RC
oscillator (exclusive for the auto wakeup feature) drives the wakeup request
generator. Once the overflow count is reached in the generator counter, a wakeup
request, AWUIREQ, is latched and sent to the KBI logic. See Figure 4-1.
Wakeup interrupt requests will only be serviced if the associated interrupt enable
bit, AWUIE, in KBIER is set. The AWU shares the keyboard interrupt vector.
COPRS (FROM CONFIG1)

VDD
AUTOWUGEN TO PTA READ, BIT 6
1 = DIV 29 D Q AWUL
SHORT 0 = DIV 214
INT RC OSC OVERFLOW

E AWUIREQ
R
EN 32 kHz CLK
RST TO KBI INTERRUPT LOGIC (SEE
Figure 9-3. Keyboard Interrupt
Block Diagram)
CLRLOGIC
RESET
CLEAR
ACKK
(CGMXCLK)
CLK
BUSCLKX4 RST
RESET
ISTOP
RESET
AWUIE
Figure 4-2. Auto Wakeup Interrupt Request Generation Logic
50 Auto Wakeup Module (AWU) MOTOROLA

Wait Mode
The overflow count can be selected from two options defined by the COPRS bit in
CONFIG1. This bit was “borrowed” from the computer operating properly (COP)
using the fact that the COP feature is idle (no MCU clock available) in stop mode.
The typical values of the periodic wakeup request are (at room temperature):
• COPRS = 0: 650 ms @ 5 V, 875 ms @ 3 V
• COPRS = 1: 16 ms @ 5 V, 22 ms @ 3 V
The auto wakeup RC oscillator is highly dependent on operating voltage and

temperature. This feature is not recommended for use as a time-keeping function.
The wakeup request is latched to allow the interrupt source identification. The
latched value, AWUL, can be read directly from the bit 6 position of PTA data
register. This is a read-only bit which is occupying an empty bit position on PTA.
No PTA associated registers, such as PTA6 data, PTA6 direction, and PTA6 pullup
exist for this bit. The latch can be cleared by writing to the ACKK bit in the KBSCR
register. Reset also clears the latch. AWUIE bit in KBI interrupt enable register (see
Figure 4-2) has no effect on AWUL reading.
The AWU oscillator and counters are inactive in normal operating mode and
become active only upon entering stop mode.
4.4 Wait Mode

The AWU module remains inactive in wait mode.
4.5 Stop Mode

When the AWU module is enabled (AWUIE = 1 in the keyboard interrupt enable
register) it is activated automatically upon entering stop mode. Clearing the
IMASKK bit in the keyboard status and control register enables keyboard interrupt
requests to bring the MCU out of stop mode. The AWU counters start from ‘0’ each
time stop mode is entered.

The AWU shares registers with the keyboard interrupt (KBI) module and the port A
I/O module. The following I/O registers control and monitor operation of the AWU:
• Port A data register (PTA)
• Keyboard interrupt status and control register (KBSCR)
• Keyboard interrupt enable register (KBIER)

4.6.1 Port A I/O Register
The port A data register (PTA) contains a data latch for the state of the AWU
interrupt request, in addition to the data latches for port A.
Address: $0000
Bit 7 6 5 4 3 2 1 Bit 0
Read: 0 AWUL PTA2
PTA5 PTA4 PTA3 PTA1 PTA0
Write:
Reset: 0 0 Unaffected by reset
= Unimplemented
Figure 4-3. Port A Data Register (PTA)
AWUL — Auto Wakeup Latch

This is a read-only bit which has the value of the auto wakeup interrupt request
latch. The wakeup request signal is generated internally. There is no PTA6 port
or any of the associated bits such as PTA6 data direction or pullup bits.
1 = Auto wakeup interrupt request is pending
0 = Auto wakeup interrupt request is not pending
NOTE: PTA5–PTA0 bits are not used in conjuction with the auto wakeup feature. To see
a description of these bits, see 12.2.1 Port A Data Register.
4.6.2 Keyboard Status and Control Register

The keyboard status and control register (KBSCR):
• Flags keyboard/auto wakeup interrupt requests
• Acknowledges keyboard/auto wakeup interrupt requests
• Masks keyboard/auto wakeup interrupt requests
Address: $001A
Bit 7 6 5 4 3 2 1 Bit 0
Read: 0 0 0 0 KEYF 0
IMASKK MODEK
Write: ACKK
Reset: 0 0 0 0 0 0 0 0
= Unimplemented
Figure 4-4. Keyboard Status and Control Register (KBSCR)
Bits 7–4 — Not used

These read-only bits always read as 0s.
KEYF — Keyboard Flag Bit
This read-only bit is set when a keyboard interrupt is pending on port A or auto
wakeup. Reset clears the KEYF bit.
1 = Keyboard/auto wakeup interrupt pending
0 = No keyboard/auto wakeup interrupt pending

ACKK — Keyboard Acknowledge Bit

Writing a 1 to this write-only bit clears the keyboard/auto wakeup interrupt
request on port A and auto wakeup logic. ACKK always reads as 0. Reset clears
ACKK.
IMASKK— Keyboard Interrupt Mask Bit
Writing a 1 to this read/write bit prevents the output of the keyboard interrupt
mask from generating interrupt requests on port A or auto wakeup. Reset clears
the IMASKK bit.
1 = Keyboard/auto wakeup interrupt requests masked
0 = Keyboard/auto wakeup interrupt requests not masked
NOTE: MODEK is not used in conjuction with the auto wakeup feature. To see a
description of this bit, see 9.7.1 Keyboard Status and Control Register.
4.6.3 Keyboard Interrupt Enable Register

The keyboard interrupt enable register (KBIER) enables or disables the auto
wakeup to operate as a keyboard/auto wakeup interrupt input.
Address: $001B
Bit 7 6 5 4 3 2 1 Bit 0
Read: 0
Write:
Reset: 0 0 0 0 0 0 0 0
= Unimplemented
Figure 4-5. Keyboard Interrupt Enable Register (KBIER)
AWUIE — Auto Wakeup Interrupt Enable Bit

This read/write bit enables the auto wakeup interrupt input to latch interrupt
requests. Reset clears AWUIE.
1 = Auto wakeup enabled as interrupt input
0 = Auto wakeup not enabled as interrupt input
NOTE: KBIE5–KBIE0 bits are not used in conjuction with the auto wakeup feature. To see
a description of these bits, see 9.7.2 Keyboard Interrupt Enable Register.


Section 5. Configuration Register (CONFIG)
5.1 Introduction
This section describes the configuration registers (CONFIG1 and CONFIG2). The
configuration registers enable or disable the following options:
• Stop mode recovery time (32 × BUSCLKX4 cycles or
4096 × BUSCLKX4 cycles)
• STOP instruction
• Computer operating properly module (COP)
• COP reset period (COPRS): (213 –24) × BUSCLKX4 or
(218 –24) × BUSCLKX4
• Low-voltage inhibit (LVI) enable and trip voltage selection
• OSC option selection
• IRQ pin
• RST pin
• Auto wakeup timeout period

The configuration registers are used in the initialization of various options. The
configuration registers can be written once after each reset. Most of the
configuration register bits are cleared during reset. Since the various options affect
the operation of the microcontroller unit (MCU) it is recommended that this register
be written immediately after reset. The configuration registers are located at $001E
and $001F, and may be read at anytime.
NOTE: The CONFIG registers are one-time writable by the user after each reset. Upon
a reset, the CONFIG registers default to predetermined settings as shown in
Figure 5-1 and Figure 5-2.
MOTOROLA Configuration Register (CONFIG) 55

Configuration Register (CONFIG)
Address: $001E
Bit 7 6 5 4 3 2 1 Bit 0
Read:
IRQPUD IRQEN R OSCOPT1 OSCOPT0 R R RSTEN
Write:
Reset: 0 0 0 0 0 0 0 U
POR: 0 0 0 0 0 0 0 0
R = Reserved U = Unaffected
Figure 5-1. Configuration Register 2 (CONFIG2)
IRQPUD — IRQ Pin Pullup Control Bit

1 = Internal pullup is disconnected
0 = Internal pullup is connected between IRQ pin and VDD
IRQEN — IRQ Pin Function Selection Bit
1 = Interrupt request function active in pin
0 = Interrupt request function inactive in pin
OSCOPT1 and OSCOPT0 — Selection Bits for Oscillator Option
(0, 0) Internal oscillator
(0, 1) External oscillator
(1, 0) External RC oscillator
(1, 1) External XTAL oscillator
RSTEN — RST Pin Function Selection
1 = Reset function active in pin
0 = Reset function inactive in pin
NOTE: The RSTEN bit is cleared by a power-on reset (POR) only. Other resets will leave
this bit unaffected.
Address: $001F
Bit 7 6 5 4 3 2 1 Bit 0
Read:
COPRS LVISTOP LVIRSTD LVIPWRD LVI5OR3 SSREC STOP COPD
Write:
Reset: 0 0 0 0 U 0 0 0
POR: 0 0 0 0 0 0 0 0
R = Reserved U = Unaffected
Figure 5-2. Configuration Register 1 (CONFIG1)
COPRS (Out of STOP Mode) — COP Reset Period Selection Bit

1 = COP reset short cycle = (213 – 24) × BUSCLKX4
0 = COP reset long cycle = (218 – 24) × BUSCLKX4
COPRS (In STOP Mode) — Auto Wakeup Period Selection Bit
1 = Auto wakeup short cycle = (29) × INTRCOSC
0 = Auto wakeup long cycle = (214) × INTRCOSC
56 Configuration Register (CONFIG) MOTOROLA

LVISTOP — LVI Enable in Stop Mode Bit

When the LVIPWRD bit is clear, setting the LVISTOP bit enables the LVI to
operate during stop mode. Reset clears LVISTOP.
1 = LVI enabled during stop mode
0 = LVI disabled during stop mode
LVIRSTD — LVI Reset Disable Bit
LVIRSTD disables the reset signal from the LVI module.
1 = LVI module resets disabled
0 = LVI module resets enabled
LVIPWRD — LVI Power Disable Bit
LVIPWRD disables the LVI module.
1 = LVI module power disabled
0 = LVI module power enabled
LVI5OR3 — LVI 5-V or 3-V Operating Mode Bit
LVI5OR3 selects the voltage operating mode of the LVI module. The voltage
mode selected for the LVI should match the operating VDD for the LVI’s voltage
trip points for each of the modes.
1 = LVI operates in 5-V mode
0 = LVI operates in 3-V mode
NOTE: The LVI5OR3 bit is cleared by a power-on reset (POR) only. Other resets will leave
this bit unaffected.
SSREC — Short Stop Recovery Bit

SSREC enables the CPU to exit stop mode with a delay of 32 BUSCLKX4
cycles instead of a 4096 BUSCLKX4 cycle delay.
1 = Stop mode recovery after 32 BUSCLKX4 cycles
0 = Stop mode recovery after 4096 BUSCLKX4 cycles
NOTE: Exiting stop mode by an LVI reset will result in the long stop recovery.
When using the LVI during normal operation but disabling during stop mode, the
LVI will have an enable time of tEN. The system stabilization time for power-on
reset and long stop recovery (both 4096 BUSCLKX4 cycles) gives a delay
longer than the LVI enable time for these startup scenarios. There is no period
where the MCU is not protected from a low-power condition. However, when
using the short stop recovery configuration option, the 32 BUSCLKX4 delay
must be greater than the LVI’s turn on time to avoid a period in startup where
the LVI is not protecting the MCU.
STOP — STOP Instruction Enable Bit
STOP enables the STOP instruction.
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
COPD — COP Disable Bit
COPD disables the COP module.
1 = COP module disabled
0 = COP module enabled
MOTOROLA Configuration Register (CONFIG) 57

58 Configuration Register (CONFIG) MOTOROLA

Section 6. Computer Operating Properly (COP)
6.1 Introduction
The computer operating properly (COP) module contains a free-running counter
that generates a reset if allowed to overflow. The COP module helps software
recover from runaway code. Prevent a COP reset by clearing the COP counter
periodically. The COP module can be disabled through the COPD bit in the
configuration 1 (CONFIG1) register.
SIM MODULE
BUSCLKX4 12-BIT SIM COUNTER SIM RESET CIRCUIT
RESET STATUS REGISTER

CLEAR STAGES 5–12
CLEAR ALL STAGES
COP TIMEOUT
INTERNAL RESET SOURCES(1)
RESET VECTOR FETCH
COPCTL WRITE
COP CLOCK
COP MODULE
6-BIT COP COUNTER
COPEN (FROM SIM)
COPD (FROM CONFIG1)
CLEAR
RESET COP COUNTER
COPCTL WRITE
COP RATE SELECT

(COPRS FROM CONFIG1)
1. See Section 13. System Integration Module (SIM) for more details.
Figure 6-1. COP Block Diagram
MOTOROLA Computer Operating Properly (COP) 59

Computer Operating Properly (COP)
The COP counter is a free-running 6-bit counter preceded by the 12-bit system
integration module (SIM) counter. If not cleared by software, the COP counter
overflows and generates an asynchronous reset after 218 – 24 or 213 – 24
BUSCLKX4 cycles; depending on the state of the COP rate select bit, COPRS, in
configuration register 1. With a 218 – 24 BUSCLKX4 cycle overflow option, the
internal 12.8-MHz oscillator gives a COP timeout period of 20.48 ms. Writing any
value to location $FFFF before an overflow occurs prevents a COP reset by
clearing the COP counter and stages 12–5 of the SIM counter.
NOTE: Service the COP immediately after reset and before entering or after exiting stop
mode to guarantee the maximum time before the first COP counter overflow.
A COP reset pulls the RST pin low (if the RSTEN bit is set in the CONFIG1 register)
for 32 × BUSCLKX4 cycles and sets the COP bit in the reset status register (RSR).
See 13.8.1 SIM Reset Status Register.
NOTE: Place COP clearing instructions in the main program and not in an interrupt
subroutine. Such an interrupt subroutine could keep the COP from generating a
reset even while the main program is not working properly.
6.3 I/O Signals

The following paragraphs describe the signals shown in Figure 6-1.
6.3.1 BUSCLKX4
BUSCLKX4 is the oscillator output signal. BUSCLKX4 frequency is equal to the

crystal frequency or the RC-oscillator frequency.
6.3.2 COPCTL Write
Writing any value to the COP control register (COPCTL) (see 6.4 COP Control
Register) clears the COP counter and clears stages 12–5 of the SIM counter.
Reading the COP control register returns the low byte of the reset vector.
6.3.3 Power-On Reset
The power-on reset (POR) circuit in the SIM clears the SIM counter
4096 × BUSCLKX4 cycles after power up.
6.3.4 Internal Reset
An internal reset clears the SIM counter and the COP counter.
6.3.5 Reset Vector Fetch
A reset vector fetch occurs when the vector address appears on the data bus.
A reset vector fetch clears the SIM counter.
60 Computer Operating Properly (COP) MOTOROLA

COP Control Register
6.3.6 COPD (COP Disable)
The COPD signal reflects the state of the COP disable bit (COPD) in the
configuration register (CONFIG). See Section 5. Configuration Register
(CONFIG).
6.3.7 COPRS (COP Rate Select)
The COPRS signal reflects the state of the COP rate select bit (COPRS) in the
configuration register 1 (CONFIG1). See Section 5. Configuration Register
(CONFIG).
6.4 COP Control Register

The COP control register (COPCTL) is located at address $FFFF and overlaps the
reset vector. Writing any value to $FFFF clears the COP counter and starts a new
timeout period. Reading location $FFFF returns the low byte of the reset vector.
Address: $FFFF
Bit 7 6 5 4 3 2 1 Bit 0
Read: LOW BYTE OF RESET VECTOR
Write: CLEAR COP COUNTER
Reset: Unaffected by reset
Figure 6-2. COP Control Register (COPCTL)
6.5 Interrupts
The COP does not generate CPU interrupt requests.
6.6 Monitor Mode

The COP is disabled in monitor mode when VTST is present on the IRQ pin.
6.7 Low-Power Modes

The WAIT and STOP instructions put the MCU in low power-consumption standby
modes.
6.7.1 Wait Mode
The COP continues to operate during wait mode. To prevent a COP reset during
wait mode, periodically clear the COP counter.
MOTOROLA Computer Operating Properly (COP) 61

6.7.2 Stop Mode
Stop mode turns off the BUSCLKX4 input to the COP and clears the SIM counter.
Service the COP immediately before entering or after exiting stop mode to ensure
a full COP timeout period after entering or exiting stop mode.
6.8 COP Module During Break Mode

The COP is disabled during a break interrupt with monitor mode when BDCOP bit
is set in break auxiliary register (BRKAR).
62 Computer Operating Properly (COP) MOTOROLA

Section 7. Central Processor Unit (CPU)
7.1 Introduction
The M68HC08 CPU (central processor unit) is an enhanced and fully
object-code-compatible version of the M68HC05 CPU. The CPU08 Reference
Manual (Motorola document order number CPU08RM/AD) contains a description
of the CPU instruction set, addressing modes, and architecture.
7.2 Features
Features of the CPU include:
• Object code fully upward-compatible with M68HC05 Family
• 16-bit stack pointer with stack manipulation instructions
• 16-bit index register with x-register manipulation instructions
• 8-MHz CPU internal bus frequency
• 64-Kbyte program/data memory space
• 16 addressing modes
• Memory-to-memory data moves without using accumulator
• Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions
• Enhanced binary-coded decimal (BCD) data handling
• Modular architecture with expandable internal bus definition for extension
of addressing range beyond 64 Kbytes
• Low-power stop and wait modes
MOTOROLA Central Processor Unit (CPU) 63

Central Processor Unit (CPU)
7.3 CPU Registers

Figure 7-1 shows the five CPU registers. CPU registers are not part of the memory
map.
7 0
ACCUMULATOR (A)
15 0
H X INDEX REGISTER (H:X)
15 0
STACK POINTER (SP)
15 0
PROGRAM COUNTER (PC)
7 0
V 1 1 H I N Z C CONDITION CODE REGISTER (CCR)
CARRY/BORROW FLAG
ZERO FLAG
NEGATIVE FLAG
INTERRUPT MASK
HALF-CARRY FLAG
TWO’S COMPLEMENT OVERFLOW FLAG
Figure 7-1. CPU Registers
7.3.1 Accumulator
The accumulator is a general-purpose 8-bit register. The CPU uses the

accumulator to hold operands and the results of arithmetic/logic operations.
Bit 7 6 5 4 3 2 1 Bit 0
Read:
Write:
Figure 7-2. Accumulator (A)
64 Central Processor Unit (CPU) MOTOROLA

CPU Registers
7.3.2 Index Register
The 16-bit index register allows indexed addressing of a 64-Kbyte memory space.
H is the upper byte of the index register, and X is the lower byte. H:X is the
concatenated 16-bit index register.
In the indexed addressing modes, the CPU uses the contents of the index register
to determine the conditional address of the operand.
The index register can serve also as a temporary data storage location.
Bit Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read:
Write:
Reset: 0 0 0 0 0 0 0 0 X X X X X X X X
X = Indeterminate
Figure 7-3. Index Register (H:X)
7.3.3 Stack Pointer
The stack pointer is a 16-bit register that contains the address of the next location
on the stack. During a reset, the stack pointer is preset to $00FF. The reset stack
pointer (RSP) instruction sets the least significant byte to $FF and does not affect
the most significant byte. The stack pointer decrements as data is pushed onto the
stack and increments as data is pulled from the stack.
In the stack pointer 8-bit offset and 16-bit offset addressing modes, the stack
pointer can function as an index register to access data on the stack. The CPU
uses the contents of the stack pointer to determine the conditional address of the
operand.
Bit Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read:
Write:
Reset: 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Figure 7-4. Stack Pointer (SP)
NOTE: The location of the stack is arbitrary and may be relocated anywhere in
random-access memory (RAM). Moving the SP out of page 0 ($0000 to $00FF)
frees direct address (page 0) space. For correct operation, the stack pointer must
point only to RAM locations.

7.3.4 Program Counter
The program counter is a 16-bit register that contains the address of the next
instruction or operand to be fetched.
Normally, the program counter automatically increments to the next sequential

memory location every time an instruction or operand is fetched. Jump, branch,
and interrupt operations load the program counter with an address other than that
of the next sequential location.
During reset, the program counter is loaded with the reset vector address located
at $FFFE and $FFFF. The vector address is the address of the first instruction to
be executed after exiting the reset state.
Bit Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read:
Write:
Reset: Loaded with vector from $FFFE and $FFFF
Figure 7-5. Program Counter (PC)
7.3.5 Condition Code Register

The 8-bit condition code register contains the interrupt mask and five flags that
indicate the results of the instruction just executed. Bits 6 and 5 are set
permanently to 1. The following paragraphs describe the functions of the condition
code register.
Bit 7 6 5 4 3 2 1 Bit 0
Read:
V 1 1 H I N Z C
Write:
Reset: X 1 1 X 1 X X X
X = Indeterminate
Figure 7-6. Condition Code Register (CCR)
V — Overflow Flag
The CPU sets the overflow flag when a two's complement overflow occurs. The
signed branch instructions BGT, BGE, BLE, and BLT use the overflow flag.
1 = Overflow
0 = No overflow

CPU Registers
H — Half-Carry Flag
The CPU sets the half-carry flag when a carry occurs between accumulator bits
3 and 4 during an add-without-carry (ADD) or add-with-carry (ADC) operation.
The half-carry flag is required for binary-coded decimal (BCD) arithmetic
operations. The DAA instruction uses the states of the H and C flags to
determine the appropriate correction factor.
1 = Carry between bits 3 and 4
0 = No carry between bits 3 and 4
I — Interrupt Mask
When the interrupt mask is set, all maskable CPU interrupts are disabled. CPU
interrupts are enabled when the interrupt mask is cleared. When a CPU
interrupt occurs, the interrupt mask is set
automatically after the CPU registers are saved on the stack, but before the
interrupt vector is fetched.
1 = Interrupts disabled
0 = Interrupts enabled
NOTE: To maintain M6805 Family compatibility, the upper byte of the index register (H) is
not stacked automatically. If the interrupt service routine modifies H, then the user
must stack and unstack H using the PSHH and PULH instructions.
After the I bit is cleared, the highest-priority interrupt request is serviced first.
A return-from-interrupt (RTI) instruction pulls the CPU registers from the stack
and restores the interrupt mask from the stack. After any reset, the interrupt
mask is set and can be cleared only by the clear interrupt mask software
instruction (CLI).
N — Negative flag
The CPU sets the negative flag when an arithmetic operation, logic operation,
or data manipulation produces a negative result, setting bit 7 of the result.
1 = Negative result
0 = Non-negative result
Z — Zero flag
The CPU sets the zero flag when an arithmetic operation, logic operation, or
data manipulation produces a result of $00.
1 = Zero result
0 = Non-zero result
C — Carry/Borrow Flag
The CPU sets the carry/borrow flag when an addition operation produces a
carry out of bit 7 of the accumulator or when a subtraction operation requires a
borrow. Some instructions — such as bit test and branch, shift, and rotate —
also clear or set the carry/borrow flag.
1 = Carry out of bit 7
0 = No carry out of bit 7

7.4 Arithmetic/Logic Unit (ALU)

The ALU performs the arithmetic and logic operations defined by the instruction
set.
Refer to the CPU08 Reference Manual (Motorola document order number

CPU08RM/AD) for a description of the instructions and addressing modes and
more detail about the architecture of the CPU.
7.5 Low-Power Modes

The WAIT and STOP instructions put the MCU in low power-consumption standby
modes.
7.5.1 Wait Mode

The WAIT instruction:
• Clears the interrupt mask (I bit) in the condition code register, enabling
interrupts. After exit from wait mode by interrupt, the I bit remains clear. After
exit by reset, the I bit is set.
• Disables the CPU clock
7.5.2 Stop Mode

The STOP instruction:
• Clears the interrupt mask (I bit) in the condition code register, enabling
external interrupts. After exit from stop mode by external interrupt, the I bit
remains clear. After exit by reset, the I bit is set.
• Disables the CPU clock
After exiting stop mode, the CPU clock begins running after the oscillator
stabilization delay.
7.6 CPU During Break Interrupts

If a break module is present on the MCU, the CPU starts a break interrupt by:
• Loading the instruction register with the SWI instruction
• Loading the program counter with $FFFC:$FFFD or with $FEFC:$FEFD in
monitor mode
The break interrupt begins after completion of the CPU instruction in progress. If
the break address register match occurs on the last cycle of a CPU instruction, the
break interrupt begins immediately.
A return-from-interrupt instruction (RTI) in the break routine ends the break

interrupt and returns the MCU to normal operation if the break interrupt has been
deasserted.

Instruction Set Summary
7.7 Instruction Set Summary

Table 7-1 provides a summary of the M68HC08 instruction set.
Table 7-1. Instruction Set Summary (Sheet 1 of 7)
Operand
Address
Effect
Opcode
Cycles
Source on CCR
Mode
Operation Description
Form
V H I N Z C
ADC #opr IMM A9 ii 2
ADC opr DIR B9 dd 3
ADC opr EXT C9 hh ll 4
ADC opr,X IX2 D9 ee ff 4
ADC opr,X Add with Carry A ← (A) + (M) + (C) – IX1 E9 ff 3
ADC ,X IX F9 2
ADC opr,SP SP1 9EE9 ff 4
ADC opr,SP SP2 9ED9 ee ff 5
ADD #opr IMM AB ii 2

ADD opr DIR BB dd 3
ADD opr EXT CB hh ll 4
ADD opr,X IX2 DB ee ff 4
ADD opr,X Add without Carry A ← (A) + (M) – IX1 EB ff 3
ADD ,X IX FB 2
ADD opr,SP SP1 9EEB ff 4
ADD opr,SP SP2 9EDB ee ff 5
AIS #opr Add Immediate Value (Signed) to SP SP ← (SP) + (16 « M) – – – – – – IMM A7 ii 2
AIX #opr Add Immediate Value (Signed) to H:X H:X ← (H:X) + (16 « M) – – – – – – IMM AF ii 2
AND #opr IMM A4 ii 2

AND opr DIR B4 dd 3
AND opr EXT C4 hh ll 4
AND opr,X IX2 D4 ee ff 4
Logical AND A ← (A) & (M) 0 – – –
AND opr,X IX1 E4 ff 3
AND ,X IX F4 2
AND opr,SP SP1 9EE4 ff 4
AND opr,SP SP2 9ED4 ee ff 5
ASL opr DIR 38 dd 4
ASLA INH 48 1
ASLX Arithmetic Shift Left INH 58 1
ASL opr,X (Same as LSL)
C 0 – – IX1 68 ff 4
ASL ,X b7 b0 IX 78 3
ASL opr,SP SP1 9E68 ff 5
ASR opr DIR 37 dd 4

ASRA INH 47 1
ASRX INH 57 1
Arithmetic Shift Right C – –
ASR opr,X IX1 67 ff 4
ASR opr,X b7 b0 IX 77 3
ASR opr,SP SP1 9E67 ff 5
BCC rel Branch if Carry Bit Clear PC ← (PC) + 2 + rel ? (C) = 0 – – – – – – REL 24 rr 3
DIR (b0) 11 dd 4
DIR (b1) 13 dd 4
DIR (b2) 15 dd 4
BCLR n, opr Clear Bit n in M Mn ← 0 – – – – – – DIR (b3) 17 dd 4
DIR (b4) 19 dd 4
DIR (b5) 1B dd 4
DIR (b6) 1D dd 4
DIR (b7) 1F dd 4
BCS rel Branch if Carry Bit Set (Same as BLO) PC ← (PC) + 2 + rel ? (C) = 1 – – – – – – REL 25 rr 3
BEQ rel Branch if Equal PC ← (PC) + 2 + rel ? (Z) = 1 – – – – – – REL 27 rr 3

Operand
Address
Effect
Opcode
Cycles
Source on CCR
Mode
Form
V H I N Z C
Branch if Greater Than or Equal To
BGE opr (Signed Operands) PC ← (PC) + 2 + rel ? (N ⊕ V) = 0 – – – – – – REL 90 rr 3
Branch if Greater Than (Signed

BGT opr Operands) PC ← (PC) + 2 + rel ? (Z) | (N ⊕ V) = 0 – – – – – – REL 92 rr 3
BHCC rel Branch if Half Carry Bit Clear PC ← (PC) + 2 + rel ? (H) = 0 – – – – – – REL 28 rr 3
BHCS rel Branch if Half Carry Bit Set PC ← (PC) + 2 + rel ? (H) = 1 – – – – – – REL 29 rr 3
BHI rel Branch if Higher PC ← (PC) + 2 + rel ? (C) | (Z) = 0 – – – – – – REL 22 rr 3
Branch if Higher or Same

BHS rel (Same as BCC) PC ← (PC) + 2 + rel ? (C) = 0 – – – – – – REL 24 rr 3
BIH rel Branch if IRQ Pin High PC ← (PC) + 2 + rel ? IRQ = 1 – – – – – – REL 2F rr 3
BIL rel Branch if IRQ Pin Low PC ← (PC) + 2 + rel ? IRQ = 0 – – – – – – REL 2E rr 3
BIT #opr IMM A5 ii 2
BIT opr DIR B5 dd 3
BIT opr EXT C5 hh ll 4
BIT opr,X Bit Test (A) & (M) 0 – – – IX2 D5 ee ff 4
BIT opr,X IX1 E5 ff 3
BIT ,X IX F5 2
BIT opr,SP SP1 9EE5 ff 4
BIT opr,SP SP2 9ED5 ee ff 5
Branch if Less Than or Equal To

BLE opr
(Signed Operands) PC ← (PC) + 2 + rel ? (Z) | (N ⊕ V) = 1 – – – – – – REL 93 rr 3
BLO rel Branch if Lower (Same as BCS) PC ← (PC) + 2 + rel ? (C) = 1 – – – – – – REL 25 rr 3
BLS rel Branch if Lower or Same PC ← (PC) + 2 + rel ? (C) | (Z) = 1 – – – – – – REL 23 rr 3
BLT opr Branch if Less Than (Signed Operands) PC ← (PC) + 2 + rel ? (N ⊕ V) =1 – – – – – – REL 91 rr 3
BMC rel Branch if Interrupt Mask Clear PC ← (PC) + 2 + rel ? (I) = 0 – – – – – – REL 2C rr 3
BMI rel Branch if Minus PC ← (PC) + 2 + rel ? (N) = 1 – – – – – – REL 2B rr 3

BMS rel Branch if Interrupt Mask Set PC ← (PC) + 2 + rel ? (I) = 1 – – – – – – REL 2D rr 3
BNE rel Branch if Not Equal PC ← (PC) + 2 + rel ? (Z) = 0 – – – – – – REL 26 rr 3
BPL rel Branch if Plus PC ← (PC) + 2 + rel ? (N) = 0 – – – – – – REL 2A rr 3
BRA rel Branch Always PC ← (PC) + 2 + rel – – – – – – REL 20 rr 3
DIR (b0) 01 dd rr 5
DIR (b1) 03 dd rr 5
DIR (b2) 05 dd rr 5
DIR (b3) 07 dd rr 5
BRCLR n,opr,rel Branch if Bit n in M Clear PC ← (PC) + 3 + rel ? (Mn) = 0 – – – – – DIR (b4) 09 dd rr 5
DIR (b5) 0B dd rr 5
DIR (b6) 0D dd rr 5
DIR (b7) 0F dd rr 5
BRN rel Branch Never PC ← (PC) + 2 – – – – – – REL 21 rr 3

Operand
Address
Effect
Opcode
Cycles
Source on CCR
Mode
Form
V H I N Z C
DIR (b0) 00 dd rr 5
DIR (b1) 02 dd rr 5
DIR (b2) 04 dd rr 5
DIR (b3) 06 dd rr 5
BRSET n,opr,rel Branch if Bit n in M Set PC ← (PC) + 3 + rel ? (Mn) = 1 – – – – – DIR (b4) 08 dd rr 5
DIR (b5) 0A dd rr 5
DIR (b6) 0C dd rr 5
DIR (b7) 0E dd rr 5
DIR (b0) 10 dd 4
DIR (b1) 12 dd 4
DIR (b2) 14 dd 4
DIR (b3) 16 dd 4
BSET n,opr Set Bit n in M Mn ← 1 – – – – – – DIR (b4) 18 dd 4
DIR (b5) 1A dd 4
DIR (b6) 1C dd 4
DIR (b7) 1E dd 4
PC ← (PC) + 2; push (PCL)

SP ← (SP) – 1; push (PCH)
BSR rel Branch to Subroutine – – – – – – REL AD rr 4
SP ← (SP) – 1
PC ← (PC) + rel
CBEQ opr,rel PC ← (PC) + 3 + rel ? (A) – (M) = $00 DIR 31 dd rr 5

CBEQA #opr,rel PC ← (PC) + 3 + rel ? (A) – (M) = $00 IMM 41 ii rr 4
CBEQX #opr,rel Compare and Branch if Equal PC ← (PC) + 3 + rel ? (X) – (M) = $00 – – – – – – IMM 51 ii rr 4
CBEQ opr,X+,rel PC ← (PC) + 3 + rel ? (A) – (M) = $00 IX1+ 61 ff rr 5
CBEQ X+,rel PC ← (PC) + 2 + rel ? (A) – (M) = $00 IX+ 71 rr 4
CBEQ opr,SP,rel PC ← (PC) + 4 + rel ? (A) – (M) = $00 SP1 9E61 ff rr 6
CLC Clear Carry Bit C←0 – – – – – 0 INH 98 1
CLI Clear Interrupt Mask I←0 – – 0 – – – INH 9A 2
CLR opr M ← $00 DIR 3F dd 3

CLRA A ← $00 INH 4F 1
CLRX X ← $00 INH 5F 1
CLRH Clear H ← $00 0 – – 0 1 – INH 8C 1
CLR opr,X M ← $00 IX1 6F ff 3
CLR ,X M ← $00 IX 7F 2
CLR opr,SP M ← $00 SP1 9E6F ff 4
CMP #opr IMM A1 ii 2
CMP opr DIR B1 dd 3
CMP opr EXT C1 hh ll 4
CMP opr,X IX2 D1 ee ff 4
Compare A with M (A) – (M) – –
CMP opr,X IX1 E1 ff 3
CMP ,X IX F1 2
CMP opr,SP SP1 9EE1 ff 4
CMP opr,SP SP2 9ED1 ee ff 5
COM opr M ← (M) = $FF – (M) DIR 33 dd 4

COMA A ← (A) = $FF – (M) INH 43 1
COMX X ← (X) = $FF – (M) INH 53 1
COM opr,X Complement (One’s Complement) M ← (M) = $FF – (M) 0 – – 1 IX1 63 ff 4
COM ,X M ← (M) = $FF – (M) IX 73 3
COM opr,SP M ← (M) = $FF – (M) SP1 9E63 ff 5
CPHX #opr Compare H:X with M (H:X) – (M:M + 1) – – IMM 65 ii ii+1 3

CPHX opr DIR 75 dd 4

Operand
Address
Effect
Opcode
Cycles
Source on CCR
Mode
Form
V H I N Z C
CPX #opr IMM A3 ii 2
CPX opr DIR B3 dd 3
CPX opr EXT C3 hh ll 4
CPX ,X IX2 D3 ee ff 4
CPX opr,X Compare X with M (X) – (M) – – IX1 E3 ff 3
CPX opr,X IX F3 2
CPX opr,SP SP1 9EE3 ff 4
CPX opr,SP SP2 9ED3 ee ff 5
DAA Decimal Adjust A (A)10 U – – INH 72 2
A ← (A) – 1 or M ← (M) – 1 or X ← (X) – 1

5
DBNZ opr,rel PC ← (PC) + 3 + rel ? (result) ≠ 0 DIR 3B dd rr 3
DBNZA rel PC ← (PC) + 2 + rel ? (result) ≠ 0 INH 4B rr
DBNZX rel Decrement and Branch if Not Zero PC ← (PC) + 2 + rel ? (result) ≠ 0 – – – – – – INH 5B rr 3
5
DBNZ opr,X,rel PC ← (PC) + 3 + rel ? (result) ≠ 0 IX1 6B ff rr 4
DBNZ X,rel PC ← (PC) + 2 + rel ? (result) ≠ 0 IX 7B rr
DBNZ opr,SP,rel PC ← (PC) + 4 + rel ? (result) ≠ 0 SP1 9E6B ff rr 6
DEC opr M ← (M) – 1 DIR 3A dd 4

DECA A ← (A) – 1 INH 4A 1
DECX Decrement X ← (X) – 1 – – – INH 5A 1
DEC opr,X M ← (M) – 1 IX1 6A ff 4
DEC ,X M ← (M) – 1 IX 7A 3
DEC opr,SP M ← (M) – 1 SP1 9E6A ff 5
A ← (H:A)/(X)
DIV Divide – – – – INH 52 7
H ← Remainder
EOR #opr IMM A8 ii 2
EOR opr DIR B8 dd 3
EOR opr EXT C8 hh ll 4
EOR opr,X IX2 D8 ee ff 4
EOR opr,X
Exclusive OR M with A A ← (A ⊕ M) 0 – – –
IX1 E8 ff 3
EOR ,X IX F8 2
EOR opr,SP SP1 9EE8 ff 4
EOR opr,SP SP2 9ED8 ee ff 5
INC opr M ← (M) + 1 DIR 3C dd 4
INCA A ← (A) + 1 INH 4C 1
INCX X ← (X) + 1 INH 5C 1
INC opr,X Increment M ← (M) + 1 – – – IX1 6C ff 4
INC ,X M ← (M) + 1 IX 7C 3
INC opr,SP M ← (M) + 1 SP1 9E6C ff 5
JMP opr DIR BC dd 2

JMP opr EXT CC hh ll 3
JMP opr,X Jump PC ← Jump Address – – – – – – IX2 DC ee ff 4
JMP opr,X IX1 EC ff 3
JMP ,X IX FC 2
JSR opr PC ← (PC) + n (n = 1, 2, or 3) DIR BD dd 4

JSR opr EXT CD hh ll 5
JSR opr,X Jump to Subroutine Push (PCL); SP ← (SP) – 1 – – – – – – IX2 DD ee ff 6
Push (PCH); SP ← (SP) – 1
JSR opr,X PC ← Unconditional Address IX1 ED ff 5
JSR ,X IX FD 4
LDA #opr IMM A6 ii 2

LDA opr DIR B6 dd 3
LDA opr EXT C6 hh ll 4
LDA opr,X Load A from M A ← (M) 0 – – – IX2 D6 ee ff 4
LDA opr,X IX1 E6 ff 3
LDA ,X IX F6 2
LDA opr,SP SP1 9EE6 ff 4
LDA opr,SP SP2 9ED6 ee ff 5

Operand
Address
Effect
Opcode
Cycles
Source on CCR
Mode
Form
V H I N Z C
LDHX #opr IMM 45 ii jj 3
LDHX opr Load H:X from M H:X ← (M:M + 1) 0 – – – DIR 55 dd 4
LDX #opr IMM AE ii 2

LDX opr DIR BE dd 3
LDX opr EXT CE hh ll 4
LDX opr,X IX2 DE ee ff 4
LDX opr,X Load X from M X ← (M) 0 – – – IX1 EE ff 3
LDX ,X IX FE 2
LDX opr,SP SP1 9EEE ff 4
LDX opr,SP SP2 9EDE ee ff 5
LSL opr DIR 38 dd 4

LSLA INH 48 1
LSLX Logical Shift Left C 0 – – INH 58 1
LSL opr,X (Same as ASL) IX1 68 ff 4
LSL ,X b7 b0 IX 78 3
LSL opr,SP SP1 9E68 ff 5
LSR opr DIR 34 dd 4

LSRA INH 44 1
LSRX INH 54 1
Logical Shift Right 0 C – – 0
LSR opr,X IX1 64 ff 4
LSR ,X b7 b0 IX 74 3
LSR opr,SP SP1 9E64 ff 5
MOV opr,opr (M)Destination ← (M)Source DD 4E dd dd 5

MOV opr,X+ DIX+ 5E dd 4
Move 0 – – –
MOV #opr,opr IMD 6E ii dd 4
MOV X+,opr H:X ← (H:X) + 1 (IX+D, DIX+) IX+D 7E dd 4
MUL Unsigned multiply X:A ← (X) × (A) – 0 – – – 0 INH 42 5
NEG opr DIR 30 dd 4

M ← –(M) = $00 – (M)
NEGA A ← –(A) = $00 – (A) INH 40 1
NEGX INH 50 1
NEG opr,X Negate (Two’s Complement) X ← –(X) = $00 – (X) – – IX1 60 ff 4
M ← –(M) = $00 – (M)
NEG ,X M ← –(M) = $00 – (M) IX 70 3
NEG opr,SP SP1 9E60 ff 5
NOP No Operation None – – – – – – INH 9D 1
NSA Nibble Swap A A ← (A[3:0]:A[7:4]) – – – – – – INH 62 3
ORA #opr IMM AA ii 2

ORA opr DIR BA dd 3
ORA opr EXT CA hh ll 4
ORA opr,X IX2 DA ee ff 4
ORA opr,X Inclusive OR A and M A ← (A) | (M) 0 – – – IX1 EA ff 3
ORA ,X IX FA 2
ORA opr,SP SP1 9EEA ff 4
ORA opr,SP SP2 9EDA ee ff 5
PSHA Push A onto Stack Push (A); SP ← (SP) – 1 – – – – – – INH 87 2
PSHH Push H onto Stack Push (H); SP ← (SP) – 1 – – – – – – INH 8B 2
PSHX Push X onto Stack Push (X); SP ← (SP) – 1 – – – – – – INH 89 2
PULA Pull A from Stack SP ← (SP + 1); Pull (A) – – – – – – INH 86 2
PULH Pull H from Stack SP ← (SP + 1); Pull (H) – – – – – – INH 8A 2

PULX Pull X from Stack SP ← (SP + 1); Pull (X) – – – – – – INH 88 2

Operand
Address
Effect
Opcode
Cycles
Source on CCR
Mode
Form
V H I N Z C
ROL opr DIR 39 dd 4
ROLA INH 49 1
ROLX Rotate Left through Carry C – – INH 59 1
ROL opr,X IX1 69 ff 4
ROL ,X b7 b0 IX 79 3
ROL opr,SP SP1 9E69 ff 5
ROR opr DIR 36 dd 4

RORA INH 46 1
RORX INH 56 1
ROR opr,X Rotate Right through Carry C – – IX1 66 ff 4
ROR ,X b7 b0 IX 76 3
ROR opr,SP SP1 9E66 ff 5
RSP Reset Stack Pointer SP ← $FF – – – – – – INH 9C 1
SP ← (SP) + 1; Pull (CCR)

SP ← (SP) + 1; Pull (A)
RTI Return from Interrupt SP ← (SP) + 1; Pull (X) INH 80 7
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
RTS Return from Subroutine SP ← SP + 1; Pull (PCH) – – – – – – INH 81 4

SP ← SP + 1; Pull (PCL)
SBC #opr IMM A2 ii 2

SBC opr DIR B2 dd 3
SBC opr EXT C2 hh ll 4
SBC opr,X Subtract with Carry A ← (A) – (M) – (C) – – IX2 D2 ee ff 4
SBC opr,X IX1 E2 ff 3
SBC ,X IX F2 2
SBC opr,SP SP1 9EE2 ff 4
SBC opr,SP SP2 9ED2 ee ff 5
SEC Set Carry Bit C←1 – – – – – 1 INH 99 1

SEI Set Interrupt Mask I←1 – – 1 – – – INH 9B 2
STA opr DIR B7 dd 3

STA opr EXT C7 hh ll 4
STA opr,X IX2 D7 ee ff 4
STA opr,X Store A in M M ← (A) 0 – – – IX1 E7 ff 3
STA ,X IX F7 2
STA opr,SP SP1 9EE7 ff 4
STA opr,SP SP2 9ED7 ee ff 5
STHX opr Store H:X in M (M:M + 1) ← (H:X) 0 – – – DIR 35 dd 4
STOP Enable IRQ Pin; Stop Oscillator I ← 0; Stop Oscillator – – 0 – – – INH 8E 1
STX opr DIR BF dd 3

STX opr EXT CF hh ll 4
STX opr,X IX2 DF ee ff 4
STX opr,X Store X in M M ← (X) 0 – – – IX1 EF ff 3
STX ,X IX FF 2
STX opr,SP SP1 9EEF ff 4
STX opr,SP SP2 9EDF ee ff 5
SUB #opr IMM A0 ii 2

SUB opr DIR B0 dd 3
SUB opr EXT C0 hh ll 4
SUB opr,X Subtract A ← (A) – (M) – – IX2 D0 ee ff 4
SUB opr,X IX1 E0 ff 3
SUB ,X IX F0 2
SUB opr,SP SP1 9EE0 ff 4
SUB opr,SP SP2 9ED0 ee ff 5

Opcode Map
Operand
Address
Effect
Opcode
Cycles
Source on CCR
Mode
Form
V H I N Z C
PC ← (PC) + 1; Push (PCL)
SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
SWI Software Interrupt SP ← (SP) – 1; Push (CCR) – – 1 – – – INH 83 9
SP ← (SP) – 1; I ← 1
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
TAP Transfer A to CCR CCR ← (A) INH 84 2
TAX Transfer A to X X ← (A) – – – – – – INH 97 1
TPA Transfer CCR to A A ← (CCR) – – – – – – INH 85 1
TST opr DIR 3D dd 3

TSTA INH 4D 1
TSTX Test for Negative or Zero (A) – $00 or (X) – $00 or (M) – $00 0 – – – INH 5D 1
TST opr,X IX1 6D ff 3
TST ,X IX 7D 2
TST opr,SP SP1 9E6D ff 4
TSX Transfer SP to H:X H:X ← (SP) + 1 – – – – – – INH 95 2
TXA Transfer X to A A ← (X) – – – – – – INH 9F 1
TXS Transfer H:X to SP (SP) ← (H:X) – 1 – – – – – – INH 94 2
A Accumulator n Any bit

C Carry/borrow bit opr Operand (one or two bytes)
CCR Condition code register PC Program counter
dd Direct address of operand PCH Program counter high byte
dd rr Direct address of operand and relative offset of branch instruction PCL Program counter low byte
DD Direct to direct addressing mode REL Relative addressing mode
DIR Direct addressing mode rel Relative program counter offset byte
DIX+ Direct to indexed with post increment addressing mode rr Relative program counter offset byte
ee ff High and low bytes of offset in indexed, 16-bit offset addressing SP1 Stack pointer, 8-bit offset addressing mode
EXT Extended addressing mode SP2 Stack pointer 16-bit offset addressing mode
ff Offset byte in indexed, 8-bit offset addressing SP Stack pointer
H Half-carry bit U Undefined
H Index register high byte V Overflow bit
hh ll High and low bytes of operand address in extended addressing X Index register low byte
I Interrupt mask Z Zero bit
ii Immediate operand byte & Logical AND
IMD Immediate source to direct destination addressing mode | Logical OR
IMM Immediate addressing mode ⊕ Logical EXCLUSIVE OR
INH Inherent addressing mode () Contents of
IX Indexed, no offset addressing mode –( ) Negation (two’s complement)
IX+ Indexed, no offset, post increment addressing mode # Immediate value
IX+D Indexed with post increment to direct addressing mode « Sign extend
IX1 Indexed, 8-bit offset addressing mode ← Loaded with
IX1+ Indexed, 8-bit offset, post increment addressing mode ? If
IX2 Indexed, 16-bit offset addressing mode : Concatenated with
M Memory location Set or cleared
N Negative bit — Not affected
7.8 Opcode Map

See Table 7-2.

76
Data Sheet
Table 7-2. Opcode Map
Bit Manipulation Branch Read-Modify-Write Control Register/Memory
DIR DIR REL DIR INH INH IX1 SP1 IX INH INH IMM DIR EXT IX2 SP2 IX1 SP1 IX
MSB
0 1 2 3 4 5 6 9E6 7 8 9 A B C D 9ED E 9EE F
LSB
5 4 3 4 1 1 4 5 3 7 3 2 3 4 4 5 3 4 2
0 BRSET0 BSET0 BRA NEG NEGA NEGX NEG NEG NEG RTI BGE SUB SUB SUB SUB SUB SUB SUB SUB
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 3 SP1 1 IX 1 INH 2 REL 2 IMM 2 DIR 3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX
5 4 3 5 4 4 5 6 4 4 3 2 3 4 4 5 3 4 2
1 BRCLR0 BCLR0 BRN CBEQ CBEQA CBEQX CBEQ CBEQ CBEQ RTS BLT CMP CMP CMP CMP CMP CMP CMP CMP
3 DIR 2 DIR 2 REL 3 DIR 3 IMM 3 IMM 3 IX1+ 4 SP1 2 IX+ 1 INH 2 REL 2 IMM 2 DIR 3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX
5 4 3 5 7 3 2 3 2 3 4 4 5 3 4 2
2 BRSET1 BSET1 BHI MUL DIV NSA DAA BGT SBC SBC SBC SBC SBC SBC SBC SBC
3 DIR 2 DIR 2 REL 1 INH 1 INH 1 INH 1 INH 2 REL 2 IMM 2 DIR 3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX
5 4 3 4 1 1 4 5 3 9 3 2 3 4 4 5 3 4 2
3 BRCLR1 BCLR1 BLS COM COMA COMX COM COM COM SWI BLE CPX CPX CPX CPX CPX CPX CPX CPX
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 3 SP1 1 IX 1 INH 2 REL 2 IMM 2 DIR 3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX
5 4 3 4 1 1 4 5 3 2 2 2 3 4 4 5 3 4 2
4 BRSET2 BSET2 BCC LSR LSRA LSRX LSR LSR LSR TAP TXS AND AND AND AND AND AND AND AND
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 3 SP1 1 IX 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX
5 4 3 4 3 4 3 4 1 2 2 3 4 4 5 3 4 2
5 BRCLR2 BCLR2 BCS STHX LDHX LDHX CPHX CPHX TPA TSX BIT BIT BIT BIT BIT BIT BIT BIT
3 DIR 2 DIR 2 REL 2 DIR 3 IMM 2 DIR 3 IMM 2 DIR 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX
5 4 3 4 1 1 4 5 3 2 2 3 4 4 5 3 4 2
6 BRSET3 BSET3 BNE ROR RORA RORX ROR ROR ROR PULA LDA LDA LDA LDA LDA LDA LDA LDA
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 3 SP1 1 IX 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX
5 4 3 4 1 1 4 5 3 2 1 2 3 4 4 5 3 4 2
7 BRCLR3 BCLR3 BEQ ASR ASRA ASRX ASR ASR ASR PSHA TAX AIS STA STA STA STA STA STA STA
5 4 3 4 1 1 4 5 3 2 1 2 3 4 4 5 3 4 2
8 BRSET4 BSET4 BHCC LSL LSLA LSLX LSL LSL LSL PULX CLC EOR EOR EOR EOR EOR EOR EOR EOR
5 4 3 4 1 1 4 5 3 2 1 2 3 4 4 5 3 4 2
9 BRCLR4 BCLR4 BHCS ROL ROLA ROLX ROL ROL ROL PSHX SEC ADC ADC ADC ADC ADC ADC ADC ADC
5 4 3 4 1 1 4 5 3 2 2 2 3 4 4 5 3 4 2
A BRSET5 BSET5 BPL DEC DECA DECX DEC DEC DEC PULH CLI ORA ORA ORA ORA ORA ORA ORA ORA
5 4 3 5 3 3 5 6 4 2 2 2 3 4 4 5 3 4 2
B BRCLR5 BCLR5 BMI DBNZ DBNZA DBNZX DBNZ DBNZ DBNZ PSHH SEI ADD ADD ADD ADD ADD ADD ADD ADD
5 4 3 4 1 1 4 5 3 1 1 2 3 4 3 2
C BRSET6 BSET6 BMC INC INCA INCX INC INC INC CLRH RSP JMP JMP JMP JMP JMP
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 3 SP1 1 IX 1 INH 1 INH 2 DIR 3 EXT 3 IX2 2 IX1 1 IX
MC68HC908QY/QT Family — Rev. 1
5 4 3 3 1 1 3 4 2 1 4 4 5 6 5 4
D BRCLR6 BCLR6 BMS TST TSTA TSTX TST TST TST NOP BSR JSR JSR JSR JSR JSR
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 3 SP1 1 IX 1 INH 2 REL 2 DIR 3 EXT 3 IX2 2 IX1 1 IX
5 4 3 5 4 4 4 1 2 3 4 4 5 3 4 2
E BRSET7 BSET7 BIL MOV MOV MOV MOV STOP LDX LDX LDX LDX LDX LDX LDX LDX
3 DIR 2 DIR 2 REL 3 DD 2 DIX+ 3 IMD 2 IX+D 1 INH * 2 IMM 2 DIR 3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX
5 4 3 3 1 1 3 4 2 1 1 2 3 4 4 5 3 4 2
F BRCLR7 BCLR7 BIH CLR CLRA CLRX CLR CLR CLR WAIT TXA AIX STX STX STX STX STX STX STX
INH Inherent REL Relative SP1 Stack Pointer, 8-Bit Offset MSB
IMM Immediate IX Indexed, No Offset SP2 Stack Pointer, 16-Bit Offset 0 High Byte of Opcode in Hexadecimal
MOTOROLA
DIR Direct IX1 Indexed, 8-Bit Offset IX+ Indexed, No Offset with LSB
EXT Extended IX2 Indexed, 16-Bit Offset Post Increment 5 Cycles
DD Direct-Direct IMD Immediate-Direct IX1+ Indexed, 1-Byte Offset with Low Byte of Opcode in Hexadecimal 0 BRSET0 Opcode Mnemonic
IX+D Indexed-Direct DIX+ Direct-Indexed Post Increment 3 DIR Number of Bytes / Addressing Mode
*Pre-byte for stack pointer indexed instructions
Section 8. External Interrupt (IRQ)
8.1 Introduction
The IRQ pin (external interrupt), shared with PTA2 (general purpose input) and
keyboard interrupt (KBI), provides a maskable interrupt input.
8.2 Features
Features of the IRQ module include the following:
• External interrupt pin, IRQ
• IRQ interrupt control bits
• Hysteresis buffer
• Programmable edge-only or edge and level interrupt sensitivity
• Automatic interrupt acknowledge
• Selectable internal pullup resistor

IRQ pin functionality is enabled by setting configuration register 2 (CONFIG2)
IRQEN bit accordingly. A zero disables the IRQ function and IRQ will assume the
other shared functionalities. A one enables the IRQ function.
A falling edge on the external interrupt pin can latch a central processor unit (CPU)
interrupt request. Figure 8-2 shows the structure of the IRQ module.
Interrupt signals on the IRQ pin are latched into the IRQ latch. An interrupt latch
remains set until one of the following actions occurs:
• Vector fetch — A vector fetch automatically generates an interrupt
acknowledge signal that clears the IRQ latch.
• Software clear — Software can clear the interrupt latch by writing to the
acknowledge bit in the interrupt status and control register (INTSCR).
Writing a 1 to the ACK bit clears the IRQ latch.
• Reset — A reset automatically clears the interrupt latch.
The external interrupt pin is falling-edge-triggered out of reset and is software-

configurable to be either falling-edge or falling-edge and low-level triggered. The
MODE bit in the INTSCR controls the triggering sensitivity of the IRQ pin.
When the interrupt pin is edge-triggered only (MODE = 0), the CPU interrupt
request remains set until a vector fetch, software clear, or reset occurs.
MOTOROLA External Interrupt (IRQ) 77

External Interrupt (IRQ)
PTA0/AD0/TCH0/KBI0
CLOCK
DDRA
PTA
PTA3/RST/KBI3
MODULE
PTA5/OSC1/AD3/KBI5
M68HC08 CPU
SINGLE INTERRUPT
PTB0 MODULE
PTB1
PTB2
BREAK
DDRB
PTB3
PTB
PTB4 MODULE
PTB5
PTB6 POWER-ON RESET
PTB7 MODULE

USER FLASH MODULE
128 BYTES RAM
COP
MODULE
VDD
VSS

Figure 8-1. Block Diagram Highlighting IRQ Block and Pins
78 External Interrupt (IRQ) MOTOROLA

ACK
RESET
INTERNAL ADDRESS BUS
VECTOR TO CPU FOR

FETCH BIL/BIH
DECODER INSTRUCTIONS
VDD
IRQPUD INTERNAL VDD

PULLUP IRQF
DEVICE
CLR
D Q SYNCHRO- IRQ
NIZER INTERRUPT
IRQ CK
REQUEST
IRQ
FF
IMASK
MODE
HIGH TO MODE
VOLTAGE SELECT
DETECT LOGIC
Figure 8-2. IRQ Module Block Diagram
When the interrupt pin is both falling-edge and low-level triggered (MODE = 1), the
CPU interrupt request remains set until both of the following occur:
• Vector fetch or software clear
• Return of the interrupt pin to logic 1
The vector fetch or software clear may occur before or after the interrupt pin returns
to logic 1. As long as the pin is low, the interrupt request remains pending. A reset
will clear the latch and the MODE control bit, thereby clearing the interrupt even if
the pin stays low.
When set, the IMASK bit in the INTSCR mask all external interrupt requests. A
latched interrupt request is not presented to the interrupt priority logic unless the
IMASK bit is clear.
NOTE: The interrupt mask (I) in the condition code register (CCR) masks all interrupt
requests, including external interrupt requests. See 13.6 Exception Control.
Figure 8-3 provides a summary of the IRQ I/O register.
IRQ Status and Control Read: 0 0 0 0 IRQF 0

IMASK MODE
$001D Register (INTSCR) Write: ACK
See page 81. Reset: 0 0 0 0 0 0 0 0
= Unimplemented
Figure 8-3. IRQ I/O Register Summary

8.4 IRQ Pin

A falling edge on the IRQ pin can latch an interrupt request into the IRQ latch. A
vector fetch, software clear, or reset clears the IRQ latch.
If the MODE bit is set, the IRQ pin is both falling-edge sensitive and low-level
sensitive. With MODE set, both of the following actions must occur to clear IRQ:
• Vector fetch or software clear — A vector fetch generates an interrupt
acknowledge signal to clear the latch. Software may generate the interrupt
acknowledge signal by writing a 1 to the ACK bit in the interrupt status and
control register (INTSCR). The ACK bit is useful in applications that poll the
IRQ pin and require software to clear the IRQ latch. Writing to the ACK bit
prior to leaving an interrupt service routine can also prevent spurious
interrupts due to noise. Setting ACK does not affect subsequent transitions
on the IRQ pin. A falling edge that occurs after writing to the ACK bit latches
another interrupt request. If the IRQ mask bit, IMASK, is clear, the CPU
loads the program counter with the vector address at locations $FFFA and
$FFFB.
• Return of the IRQ pin to logic 1 — As long as the IRQ pin is at logic 0, IRQ
remains active.
The vector fetch or software clear and the return of the IRQ pin to logic 1 may occur
in any order. The interrupt request remains pending as long as the IRQ pin is at
logic 0. A reset will clear the latch and the MODE control bit, thereby clearing the
interrupt even if the pin stays low.
If the MODE bit is clear, the IRQ pin is falling-edge sensitive only. With MODE
clear, a vector fetch or software clear immediately clears the IRQ latch.
The IRQF bit in the INTSCR register can be used to check for pending interrupts.
The IRQF bit is not affected by the IMASK bit, which makes it useful in applications
where polling is preferred.
NOTE: When the IRQ function is enabled in the CONFIG2 register, the BIH and BIL
instructions can be used to read the logic level on the IRQ pin. If the IRQ function
is disabled, these instructions will behave as if the IRQ pin is a logic 1, regardless
of the actual level on the pin. Conversely, when the IRQ function is enabled, bit 2
of the port A data register will always read a 0.
NOTE: When using the level-sensitive interrupt trigger, avoid false interrupts by masking
interrupt requests in the interrupt routine. An internal pullup resistor to VDD is
connected to the IRQ pin; this can be disabled by setting the IRQPUD bit in the
CONFIG2 register ($001E).
8.5 IRQ Module During Break Interrupts

The system integration module (SIM) controls whether the IRQ latch can be
cleared during the break state. The BCFE bit in the break flag control register
(BFCR) enables software to clear the latches during the break state. See
Section 13. System Integration Module (SIM).

IRQ Status and Control Register
To allow software to clear the IRQ latch during a break interrupt, write a 1 to the
BCFE bit. If a latch is cleared during the break state, it remains cleared when the
MCU exits the break state.
To protect the latches during the break state, write a 0 to the BCFE bit. With BCFE
at 0 (its default state), writing to the ACK bit in the IRQ status and control register
during the break state has no effect on the IRQ latch.
8.6 IRQ Status and Control Register

The IRQ status and control register (ISCR) controls and monitors operation of the
IRQ module, see Section 5. Configuration Register (CONFIG).
The ISCR has the following functions:

• Shows the state of the IRQ flag
• Clears the IRQ latch
• Masks IRQ and interrupt request
• Controls triggering sensitivity of the IRQ interrupt pin
Address: $001D
Bit 7 6 5 4 3 2 1 Bit 0
Read: 0 0 0 0 IRQF 0
IMASK MODE
Write: ACK
Reset: 0 0 0 0 0 0 0 0
= Unimplemented
Figure 8-4. IRQ Status and Control Register (INTSCR)
IRQF — IRQ Flag

This read-only status bit is high when the IRQ interrupt is pending.
1 = IRQ interrupt pending
0 = IRQ interrupt not pending
ACK — IRQ Interrupt Request Acknowledge Bit
Writing a 1 to this write-only bit clears the IRQ latch. ACK always reads as 0.
Reset clears ACK.
IMASK — IRQ Interrupt Mask Bit
Writing a 1 to this read/write bit disables IRQ interrupt requests. Reset clears
IMASK.
1 = IRQ interrupt requests disabled
0 = IRQ interrupt requests enabled
MODE — IRQ Edge/Level Select Bit
This read/write bit controls the triggering sensitivity of the IRQ pin. Reset clears
MODE.
1 = IRQ interrupt requests on falling edges and low levels
0 = IRQ interrupt requests on falling edges only


Section 9. Keyboard Interrupt Module (KBI)
9.1 Introduction
The keyboard interrupt module (KBI) provides six independently maskable external
interrupts, which are accessible via the PTA0–PTA5 pins.
9.2 Features
Features of the keyboard interrupt module include:
• Six keyboard interrupt pins with separate keyboard interrupt enable bits and
one keyboard interrupt mask
• Software configurable pullup device if input pin is configured as input port bit
• Programmable edge-only or edge and level interrupt sensitivity
• Exit from low-power modes
Figure 9-1 provides a summary of the input/output (I/O) registers

Keyboard Status and Control IMASKK MODEK
$001A Register (KBSCR) Write: ACKK
See page 88.
Reset: 0 0 0 0 0 0 0 0
Read: 0
Keyboard Interrupt Enable AWUIE KBIE5 KBIE4 KBIE3 KBIE2 KBIE1 KBIE0
$001B Register (KBIER) Write:
See page 89.
Reset: 0 0 0 0 0 0 0 0
= Unimplemented
Figure 9-1. KBI I/O Register Summary
MOTOROLA Keyboard Interrupt Module (KBI) 83

Keyboard Interrupt Module (KBI)
PTA0/AD0/TCH0/KBI0
CLOCK
DDRA
PTA
PTA3/RST/KBI3
MODULE
PTA5/OSC1/AD3/KBI5
M68HC08 CPU
SINGLE INTERRUPT
PTB0 MODULE
PTB1
PTB2
BREAK
DDRB
PTB3
PTB
PTB4 MODULE
PTB5
PTB6 POWER-ON RESET
PTB7 MODULE

USER FLASH MODULE
128 BYTES RAM
COP
MODULE
VDD
VSS

PTB[0:7]: Not available on 8-pin devices – MC68HLC908QT1, MC68HLC908QT2, and MC68HLC908QT4
Figure 9-2. Block Diagram Highlighting KBI Block and Pins
84 Keyboard Interrupt Module (KBI) MOTOROLA


The keyboard interrupt module controls the enabling/disabling of interrupt
functions on the six port A pins. These six pins can be enabled/disabled
independently of each other.
INTERNAL BUS
VECTOR FETCH
DECODER
ACKK
KBI0
VDD RESET
KEYF
. D
CLR
Q
KBIE0 SYNCHRONIZER
. CK
TO PULLUP ENABLE
. KEYBOARD
INTERRUPT
IMASKK REQUEST
KBI5 KEYBOARD
INTERRUPT FF
MODEK
KBIE5
TO PULLUP ENABLE
AWUIREQ(1) 1. For AWUGEN logic refer to Figure 4-2. Auto Wakeup Interrupt Request Generation Logic.
Figure 9-3. Keyboard Interrupt Block Diagram
9.3.1 Keyboard Operation
Writing to the KBIE0–KBIE5 bits in the keyboard interrupt enable register (KBIER)
independently enables or disables each port A pin as a keyboard interrupt pin.
Enabling a keyboard interrupt pin in port A also enables its internal pullup device
irrespective of PTAPUEx bits in the port A input pullup enable register (see 12.2.3
Port A Input Pullup Enable Register). A logic 0 applied to an enabled keyboard
interrupt pin latches a keyboard interrupt request.
A keyboard interrupt is latched when one or more keyboard interrupt inputs goes
low after all were high. The MODEK bit in the keyboard status and control register
controls the triggering mode of the keyboard interrupt.
• If the keyboard interrupt is edge-sensitive only, a falling edge on a keyboard
interrupt input does not latch an interrupt request if another keyboard pin is
already low. To prevent losing an interrupt request on one input because
another input is still low, software can disable the latter input while it is low.
• If the keyboard interrupt is falling edge and low-level sensitive, an interrupt
request is present as long as any keyboard interrupt input is low.

If the MODEK bit is set, the keyboard interrupt inputs are both falling edge and
low-level sensitive, and both of the following actions must occur to clear a keyboard
interrupt request:
• Vector fetch or software clear — A vector fetch generates an interrupt
acknowledge signal to clear the interrupt request. Software may generate
the interrupt acknowledge signal by writing a 1 to the ACKK bit in the
keyboard status and control register (KBSCR). The ACKK bit is useful in
applications that poll the keyboard interrupt inputs and require software to
clear the keyboard interrupt request. Writing to the ACKK bit prior to leaving
an interrupt service routine can also prevent spurious interrupts due to
noise. Setting ACKK does not affect subsequent transitions on the keyboard
interrupt inputs. A falling edge that occurs after writing to the ACKK bit
latches another interrupt request. If the keyboard interrupt mask bit,
IMASKK, is clear, the central processor unit (CPU) loads the program
counter with the vector address at locations $FFE0 and $FFE1.
• Return of all enabled keyboard interrupt inputs to logic 1 — As long as any
enabled keyboard interrupt pin is at logic 0, the keyboard interrupt remains
set. The auto wakeup interrupt input, AWUIREQ, will be cleared only by
writing to ACKK bit in KBSCR or reset.
The vector fetch or software clear and the return of all enabled keyboard interrupt
pins to logic 1 may occur in any order.
If the MODEK bit is clear, the keyboard interrupt pin is falling-edge sensitive only.
With MODEK clear, a vector fetch or software clear immediately clears the
keyboard interrupt request.
Reset clears the keyboard interrupt request and the MODEK bit, clearing the
interrupt request even if a keyboard interrupt input stays at logic 0.
The keyboard flag bit (KEYF) in the keyboard status and control register can be
used to see if a pending interrupt exists. The KEYF bit is not affected by the
keyboard interrupt mask bit (IMASKK) which makes it useful in applications where
polling is preferred.
To determine the logic level on a keyboard interrupt pin, use the data direction
register to configure the pin as an input and then read the data register.
NOTE: Setting a keyboard interrupt enable bit (KBIEx) forces the corresponding keyboard
interrupt pin to be an input, overriding the data direction register. However, the data
direction register bit must be a 0 for software to read the pin.

Wait Mode
9.3.2 Keyboard Initialization
When a keyboard interrupt pin is enabled, it takes time for the internal pullup to
reach a logic 1. Therefore a false interrupt can occur as soon as the pin is enabled.
To prevent a false interrupt on keyboard initialization:

1. Mask keyboard interrupts by setting the IMASKK bit in the keyboard status
and control register.
2. Enable the KBI pins by setting the appropriate KBIEx bits in the keyboard
interrupt enable register.
3. Write to the ACKK bit in the keyboard status and control register to clear any
false interrupts.
4. Clear the IMASKK bit.
An interrupt signal on an edge-triggered pin can be acknowledged immediately
after enabling the pin. An interrupt signal on an edge- and level-triggered interrupt
pin must be acknowledged after a delay that depends on the external load.
Another way to avoid a false interrupt:

1. Configure the keyboard pins as outputs by setting the appropriate DDRA
bits in the data direction register A.
2. Write 1s to the appropriate port A data register bits.
3. Enable the KBI pins by setting the appropriate KBIEx bits in the keyboard
interrupt enable register.
9.4 Wait Mode

The keyboard module remains active in wait mode. Clearing the IMASKK bit in the
keyboard status and control register enables keyboard interrupt requests to bring
the MCU out of wait mode.
9.5 Stop Mode

The keyboard module remains active in stop mode. Clearing the IMASKK bit in the
keyboard status and control register enables keyboard interrupt requests to bring
the MCU out of stop mode.
9.6 Keyboard Module During Break Interrupts

The system integration module (SIM) controls whether the keyboard interrupt latch
can be cleared during the break state. The BCFE bit in the break flag control
register (BFCR) enables software to clear status bits during the break state.
To allow software to clear the keyboard interrupt latch during a break interrupt,
write a 1 to the BCFE bit. If a latch is cleared during the break state, it remains
cleared when the MCU exits the break state.

To protect the latch during the break state, write a 0 to the BCFE bit. With BCFE
at 0 (its default state), writing to the keyboard acknowledge bit (ACKK) in the
keyboard status and control register during the break state has no effect.

The following I/O registers control and monitor operation of the keyboard interrupt
module:
• Keyboard interrupt status and control register (KBSCR)
• Keyboard interrupt enable register (KBIER)
9.7.1 Keyboard Status and Control Register
The keyboard status and control register (KBSCR):

• Flags keyboard interrupt requests
• Acknowledges keyboard interrupt requests
• Masks keyboard interrupt requests
• Controls keyboard interrupt triggering sensitivity
Address: $001A
Bit 7 6 5 4 3 2 1 Bit 0
IMASKK MODEK
Write: ACKK
Reset: 0 0 0 0 0 0 0 0
= Unimplemented
Figure 9-4. Keyboard Status and Control Register (KBSCR)

Bits 7–4 — Not used
These read-only bits always read as 0s.
KEYF — Keyboard Flag Bit
This read-only bit is set when a keyboard interrupt is pending on port A or auto
wakeup. Reset clears the KEYF bit.
1 = Keyboard interrupt pending
0 = No keyboard interrupt pending
ACKK — Keyboard Acknowledge Bit
Writing a 1 to this write-only bit clears the keyboard interrupt request on port A
and auto wakeup logic. ACKK always reads as 0. Reset clears ACKK.
IMASKK— Keyboard Interrupt Mask Bit
Writing a 1 to this read/write bit prevents the output of the keyboard interrupt
mask from generating interrupt requests on port A or auto wakeup. Reset clears
the IMASKK bit.
1 = Keyboard interrupt requests masked
0 = Keyboard interrupt requests not masked

MODEK — Keyboard Triggering Sensitivity Bit

This read/write bit controls the triggering sensitivity of the keyboard interrupt
pins on port A and auto wakeup. Reset clears MODEK.
1 = Keyboard interrupt requests on falling edges and low levels
0 = Keyboard interrupt requests on falling edges only
9.7.2 Keyboard Interrupt Enable Register
The port A keyboard interrupt enable register (KBIER) enables or disables each
port A pin or auto wakeup to operate as a keyboard interrupt input.
Address: $001B
Bit 7 6 5 4 3 2 1 Bit 0
Read: 0
Write:
Reset: 0 0 0 0 0 0 0 0
= Unimplemented
Figure 9-5. Keyboard Interrupt Enable Register (KBIER)
KBIE5–KBIE0 — Port A Keyboard Interrupt Enable Bits

Each of these read/write bits enables the corresponding keyboard interrupt pin
on port A to latch interrupt requests. Reset clears the keyboard interrupt enable
register.
1 = KBIx pin enabled as keyboard interrupt pin
0 = KBIx pin not enabled as keyboard interrupt pin
NOTE: AWUIE bit is not used in conjunction with the keyboard interrupt feature. To see a
description of this bit, see Section 4. Auto Wakeup Module (AWU).


Section 10. Low-Voltage Inhibit (LVI)
10.1 Introduction
This section describes the low-voltage inhibit (LVI) module, which monitors the
voltage on the VDD pin and can force a reset when the VDD voltage falls below the
LVI trip falling voltage, VTRIPF.
10.2 Features
Features of the LVI module include:
• Programmable LVI reset
• Programmable power consumption
• Selectable LVI trip voltage
• Programmable stop mode operation

Figure 10-1 shows the structure of the LVI module. LVISTOP, LVIPWRD,
LVI5OR3, and LVIRSTD are user selectable options found in the configuration
register (CONFIG1). See Section 5. Configuration Register (CONFIG).
VDD
STOP INSTRUCTION
LVISTOP
FROM CONFIG
FROM CONFIG
LVIRSTD
LVIPWRD
FROM CONFIG
LOW VDD VDD > LVITRIP = 0 LVI RESET

DETECTOR VDD ≤ LVITRIP = 1
LVIOUT
LVI5OR3
FROM CONFIG
Figure 10-1. LVI Module Block Diagram
MOTOROLA Low-Voltage Inhibit (LVI) 91

Low-Voltage Inhibit (LVI)
The LVI is enabled out of reset. The LVI module contains a bandgap reference
circuit and comparator. Clearing the LVI power disable bit, LVIPWRD, enables the
LVI to monitor VDD voltage. Clearing the LVI reset disable bit, LVIRSTD, enables
the LVI module to generate a reset when VDD falls below a voltage, VTRIPF. Setting
the LVI enable in stop mode bit, LVISTOP, enables the LVI to operate in stop
mode. Setting the LVI 5-V or 3-V trip point bit, LVI5OR3, enables the trip point
voltage, VTRIPF, to be configured for 5-V operation. Clearing the LVI5OR3 bit
enables the trip point voltage, VTRIPF, to be configured for 3-V operation. The
actual trip thresholds are specified in 16.5 5-V DC Electrical Characteristics and
16.9 3-V DC Electrical Characteristics.
NOTE: After a power-on reset, the LVI’s default mode of operation is 3 volts. If a 5-V
system is used, the user must set the LVI5OR3 bit to raise the trip point to 5-V
operation.
If the user requires 5-V mode and sets the LVI5OR3 bit after power-on reset while
the VDD supply is not above the VTRIPR for 5-V mode, the microcontroller unit
(MCU) will immediately go into reset. The next time the LVI releases the reset, the
supply will be above the VTRIPR for 5-V mode.
Once an LVI reset occurs, the MCU remains in reset until VDD rises above a
voltage, VTRIPR, which causes the MCU to exit reset. See Section 13. System
Integration Module (SIM) for the reset recovery sequence.
The output of the comparator controls the state of the LVIOUT flag in the LVI status
register (LVISR) and can be used for polling LVI operation when the LVI reset is
disabled.
10.3.1 Polled LVI Operation
In applications that can operate at VDD levels below the VTRIPF level, software can
monitor VDD by polling the LVIOUT bit. In the configuration register, the LVIPWRD
bit must be cleared to enable the LVI module, and the LVIRSTD bit must be at set
to disable LVI resets.
10.3.2 Forced Reset Operation
In applications that require VDD to remain above the VTRIPF level, enabling LVI
resets allows the LVI module to reset the MCU when VDD falls below the VTRIPF
level. In the configuration register, the LVIPWRD and LVIRSTD bits must be
cleared to enable the LVI module and to enable LVI resets.
10.3.3 Voltage Hysteresis Protection
Once the LVI has triggered (by having VDD fall below VTRIPF), the LVI will maintain
a reset condition until VDD rises above the rising trip point voltage, VTRIPR. This
prevents a condition in which the MCU is continually entering and exiting reset if
VDD is approximately equal to VTRIPF. VTRIPR is greater than VTRIPF by the
hysteresis voltage, VHYS.
92 Low-Voltage Inhibit (LVI) MOTOROLA

LVI Status Register
10.3.4 LVI Trip Selection
The LVI5OR3 bit in the configuration register selects whether the LVI is configured
for 5-V or 3-V protection.
NOTE: The microcontroller is guaranteed to operate at a minimum supply voltage. The trip
point (VTRIPF [5 V] or VTRIPF [3 V]) may be lower than this. See 16.5 5-V DC
Electrical Characteristics and 16.9 3-V DC Electrical Characteristics for the
actual trip point voltages.
10.4 LVI Status Register

The LVI status register (LVISR) indicates if the VDD voltage was detected below
the VTRIPF level while LVI resets have been disabled.
Address: $FE0C
Bit 7 6 5 4 3 2 1 Bit 0
Read: LVIOUT 0 0 0 0 0 0 R
Write:
Reset: 0 0 0 0 0 0 0 0
= Unimplemented R = Reserved
Figure 10-2. LVI Status Register (LVISR)
LVIOUT — LVI Output Bit

This read-only flag becomes set when the VDD voltage falls below the VTRIPF
trip voltage and is cleared when VDD voltage rises above VTRIPR. The difference
in these threshold levels results in a hysteresis that prevents oscillation into and
out of reset (see Table 10-1). Reset clears the LVIOUT bit.
Table 10-1. LVIOUT Bit Indication

VDD LVIOUT
VDD > VTRIPR 0
VDD < VTRIPF 1
VTRIPF < VDD < VTRIPR Previous value
10.5 LVI Interrupts

The LVI module does not generate interrupt requests.
MOTOROLA Low-Voltage Inhibit (LVI) 93

10.6 Low-Power Modes

The STOP and WAIT instructions put the MCU in low power-consumption standby
modes.
10.6.1 Wait Mode
If enabled, the LVI module remains active in wait mode. If enabled to generate
resets, the LVI module can generate a reset and bring the MCU out of wait mode.
10.6.2 Stop Mode
When the LVIPWRD bit in the configuration register is cleared and the LVISTOP
bit in the configuration register is set, the LVI module remains active in stop mode.
If enabled to generate resets, the LVI module can generate a reset and bring the
MCU out of stop mode.
94 Low-Voltage Inhibit (LVI) MOTOROLA

Section 11. Oscillator Module (OSC)
11.1 Introduction
The oscillator module is used to provide a stable clock source for the
microcontroller system and bus. The oscillator module generates two output
clocks, BUSCLKX2 and BUSCLKX4. The BUSCLKX4 clock is used by the system
integration module (SIM) and the computer operating properly module (COP). The
BUSCLKX2 clock is divided by two in the SIM to be used as the bus clock for the
microcontroller. Therefore the bus frequency will be one forth of the BUSCLKX4
frequency.
11.2 Features
The oscillator has these four clock source options available:
1. Internal oscillator: An internally generated, fixed frequency clock, trimmable
to ±5%. This is the default option out of reset.
2. External oscillator: An external clock that can be driven directly into OSC1.
3. External RC: A built-in oscillator module (RC oscillator) that requires an
external R connection only. The capacitor is internal to the chip.
4. External crystal: A built-in oscillator module (XTAL oscillator) that requires
an external crystal or ceramic-resonator.

The oscillator contains these major subsystems:
• Internal oscillator circuit
• Internal or external clock switch control
• External clock circuit
• External crystal circuit
• External RC clock circuit
MOTOROLA Oscillator Module (OSC) 95

Oscillator Module (OSC)
PTA0/AD0/TCH0/KBI0
CLOCK
DDRA
PTA
PTA3/RST/KBI3
MODULE
PTA5/OSC1/AD3/KBI5
M68HC08 CPU
SINGLE INTERRUPT
PTB0 MODULE
PTB1
PTB2
BREAK
DDRB
PTB3
PTB
PTB4 MODULE
PTB5
PTB6 POWER-ON RESET
PTB7 MODULE

USER FLASH MODULE
128 BYTES RAM
COP
MODULE
VDD
VSS

Figure 11-1. Block Diagram Highlighting OSC Block and Pins
96 Oscillator Module (OSC) MOTOROLA

11.3.1 Internal Oscillator
The internal oscillator circuit is designed for use with no external components to
provide a clock source with tolerance less than ±25% untrimmed. An 8-bit trimming
register allows adjustment to a tolerance of less than ±5%.
The internal oscillator will generate a clock of 12.8 MHz typical (INTCLK) resulting
in a bus speed (internal clock ÷ 4) of 3.2 MHz. 3.2 MHz came from the maximum
bus speed guaranteed at 3 V which is 4 MHz. Since the internal oscillator will have
a ±25% tolerance (pre-trim), then the +25% case should not allow a frequency
higher than 4 MHz:
3.2 MHz + 25% = 4 MHz
Figure 11-3 shows how BUSCLKX4 is derived from INTCLK and, like the RC
oscillator, OSC2 can output BUSCLKX4 by setting OSC2EN in PTAPUE register.
See Section 12. Input/Output Ports (PORTS).
11.3.1.1 Internal Oscillator Trimming
The 8-bit trimming register, OSCTRIM, allows a clock period adjust of +127 and
–128 steps. Increasing OSCTRIM value increases the clock period. Trimming
allows the internal clock frequency to be set to 12.8 MHz ± 5%.
All devices are programmed with a trim value in a reserved FLASH location,
$FFC0. This value can be copied from the FLASH to the OSCTRIM register
($0038) during reset initialization.
Reset loads OSCTRIM with a default value of $80.
WARNING: Bulk FLASH erasure will set location $FFC0 to $FF and the factory
programmed value will be lost.
11.3.1.2 Internal to External Clock Switching
When external clock source (external OSC, RC, or XTAL) is desired, the user must
perform the following steps:
1. For external crystal circuits only, OSCOPT[1:0] = 1:1: To help precharge an
external crystal oscillator, set PTA4 (OSC2) as an output and drive high for
several cycles. This may help the crystal circuit start more robustly.
2. Set CONFIG2 bits OSCOPT[1:0] according to Table 11-2. The oscillator
module control logic will then set OSC1 as an external clock input and, if the
external crystal option is selected, OSC2 will also be set as the clock output.
3. Create a software delay to wait the stabilization time needed for the selected
clock source (crystal, resonator, RC) as recommended by the component
manufacturer. A good rule of thumb for crystal oscillators is to wait 4096
cycles of the crystal frequency, i.e., for a 4-MHz crystal, wait approximately
1 msec.

4. After the manufacturer’s recommended delay has elapsed, the ECGON bit
in the OSC status register (OSCSTAT) needs to be set by the user software.
5. After ECGON set is detected, the OSC module checks for oscillator activity
by waiting two external clock rising edges.
6. The OSC module then switches to the external clock. Logic provides a glitch
free transition.
7. The OSC module first sets the ECGST bit in the OSCSTAT register and then
stops the internal oscillator.
NOTE: Once transition to the external clock is done, the internal oscillator will only be
reactivated with reset. No post-switch clock monitor feature is implemented (clock
does not switch back to internal if external clock dies).
11.3.2 External Oscillator

The external clock option is designed for use when a clock signal is available in the
application to provide a clock source to the microcontroller. The OSC1 pin is
enabled as an input by the oscillator module. The clock signal is used directly to
create BUSCLKX4 and also divided by two to create BUSCLKX2.
In this configuration, the OSC2 pin cannot output BUSCLKX4. So the OSC2EN bit
in the port A pullup enable register will be clear to enable PTA4 I/O functions on
the pin.
11.3.3 XTAL Oscillator
The XTAL oscillator circuit is designed for use with an external crystal or ceramic
resonator to provide an accurate clock source. In this configuration, the OSC2 pin
is dedicated to the external crystal circuit. The OSC2EN bit in the port A pullup
enable register has no effect when this clock mode is selected.
In its typical configuration, the XTAL oscillator is connected in a Pierce oscillator
configuration, as shown in Figure 11-2. This figure shows only the logical
representation of the internal components and may not represent actual circuitry.
The oscillator configuration uses five components:
• Crystal, X1
• Fixed capacitor, C1
• Tuning capacitor, C2 (can also be a fixed capacitor)
• Feedback resistor, RB
• Series resistor, RS (optional)
NOTE: The series resistor (RS) is included in the diagram to follow strict Pierce oscillator
guidelines and may not be required for all ranges of operation, especially with high
frequency crystals. Refer to the crystal manufacturer’s data for more information.

FROM SIM TO SIM TO SIM
BUSCLKX4 BUSCLKX2
XTALCLK
÷2
SIMOSCEN
MCU
OSC1 OSC2
RS(1)
RB
X1
C1 C2
Note 1.
RS can be zero (shorted) when used with higher-frequency crystals. Refer to manufacturer’s
data. See Section 16. Electrical Specifications for component value recommendations.
Figure 11-2. XTAL Oscillator External Connections
11.3.4 RC Oscillator
The RC oscillator circuit is designed for use with external R to provide a clock
source with tolerance less than 25%.
In its typical configuration, the RC oscillator requires two external components, one
R and one C. In the MC68HC908QY4, the capacitor is internal to the chip. The R
value should have a tolerance of 1% or less, to obtain a clock source with less than
25% tolerance. The oscillator configuration uses one component, REXT.
In this configuration, the OSC2 pin can be left in the reset state as PTA4. Or, the
OSC2EN bit in the port A pullup enable register can be set to enable the OSC2
output function on the pin. Enabling the OSC2 output slightly increases the external
RC oscillator frequency, fRCCLK.
See Figure 11-3.

OSCRCOPT
FROM SIM TO SIM TO SIM

INTCLK 0
BUSCLKX4 BUSCLKX2
1
SIMOSCEN EXTERNAL RC RCCLK
EN ÷2
OSCILLATOR
PTA4
0 PTA4
I/O
MCU OSC2EN
OSC1 PTA4/BUSCLKX4 (OSC2)
VDD
REXT
See Section 16. Electrical Specifications for component value requirements.
Figure 11-3. RC Oscillator External Connections
11.4 Oscillator Module Signals

The following paragraphs describe the signals that are inputs to and outputs from
the oscillator module.
11.4.1 Crystal Amplifier Input Pin (OSC1)
The OSC1 pin is either an input to the crystal oscillator amplifier, an input to the RC
oscillator circuit, or an external clock source.
For the internal oscillator configuration, the OSC1 pin can assume other functions
according to Table 1-3. Function Priority in Shared Pins.
11.4.2 Crystal Amplifier Output Pin (OSC2/PTA4/BUSCLKX4)
For the XTAL oscillator device, the OSC2 pin is the crystal oscillator inverting
amplifier output.
For the external clock option, the OSC2 pin is dedicated to the PTA4 I/O function.
The OSC2EN bit has no effect.
For the internal oscillator or RC oscillator options, the OSC2 pin can assume other
functions according to Table 1-3. Function Priority in Shared Pins, or the output
of the oscillator clock (BUSCLKX4).

Oscillator Module Signals
Table 11-1. OSC2 Pin Function

Option OSC2 Pin Function
XTAL oscillator Inverting OSC1
External clock PTA4 I/O
Internal oscillator Controlled by OSC2EN bit in PTAPUE register
or OSC2EN = 0: PTA4 I/O
RC oscillator OSC2EN = 1: BUSCLKX4 output
11.4.3 Oscillator Enable Signal (SIMOSCEN)
The SIMOSCEN signal comes from the system integration module (SIM) and
enables/disables either the XTAL oscillator circuit, the RC oscillator, or the internal
oscillator.
11.4.4 XTAL Oscillator Clock (XTALCLK)
XTALCLK is the XTAL oscillator output signal. It runs at the full speed of the crystal
(fXCLK) and comes directly from the crystal oscillator circuit. Figure 11-2 shows
only the logical relation of XTALCLK to OSC1 and OSC2 and may not represent
the actual circuitry. The duty cycle of XTALCLK is unknown and may depend on
the crystal and other external factors. Also, the frequency and amplitude of
XTALCLK can be unstable at start up.
11.4.5 RC Oscillator Clock (RCCLK)

RCCLK is the RC oscillator output signal. Its frequency is directly proportional to
the time constant of external R and internal C. Figure 11-3 shows only the logical
relation of RCCLK to OSC1 and may not represent the actual circuitry.
11.4.6 Internal Oscillator Clock (INTCLK)
INTCLK is the internal oscillator output signal. Its nominal frequency is fixed to
12.8 MHz, but it can be also trimmed using the oscillator trimming feature of the
OSCTRIM register (see 11.3.1.1 Internal Oscillator Trimming).
11.4.7 Oscillator Out 2 (BUSCLKX4)
BUSCLKX4 is the same as the input clock (XTALCLK, RCCLK, or INTCLK). This
signal is driven to the SIM module and is used to determine the COP cycles.
11.4.8 Oscillator Out (BUSCLKX2)
The frequency of this signal is equal to half of the BUSCLKX4, this signal is driven
to the SIM for generation of the bus clocks used by the CPU and other modules on
the MCU. BUSCLKX2 will be divided again in the SIM and results in the internal

bus frequency being one fourth of either the XTALCLK, RCCLK, or INTCLK
frequency.
11.5 Low Power Modes

The WAIT and STOP instructions put the MCU in low-power consumption standby
modes.
11.5.1 Wait Mode
The WAIT instruction has no effect on the oscillator logic. BUSCLKX2 and
BUSCLKX4 continue to drive to the SIM module.
11.5.2 Stop Mode
The STOP instruction disables either the XTALCLK, the RCCLK, or INTCLK
output, hence BUSCLKX2 and BUSCLKX4.
11.6 Oscillator During Break Mode

The oscillator continues to drive BUSCLKX2 and BUSCLKX4 when the device
enters the break state.
11.7 CONFIG2 Options

Two CONFIG2 register options affect the operation of the oscillator module:
OSCOPT1 and OSCOPT0. All CONFIG2 register bits will have a default
configuration. Refer to Section 5. Configuration Register (CONFIG) for more
information on how the CONFIG2 register is used.
Table 11-2 shows how the OSCOPT bits are used to select the oscillator clock
source.
Table 11-2. Oscillator Modes
OSCOPT1 OSCOPT0 Oscillator Modes

0 0 Internal oscillator
0 1 External oscillator
1 0 External RC
1 1 External crystal

Input/Output (I/O) Registers
11.8 Input/Output (I/O) Registers

The oscillator module contains these two registers:
1. Oscillator status register (OSCSTAT)
2. Oscillator trim register (OSCTRIM)
11.8.1 Oscillator Status Register
The oscillator status register (OSCSTAT) contains the bits for switching from
internal to external clock sources.
Address: $0036
Bit 7 6 5 4 3 2 1 Bit 0
Read: ECGST
R R R R R R ECGON
Write:
Reset: 0 0 0 0 0 0 0 0
R = Reserved = Unimplemented
Figure 11-4. Oscillator Status Register (OSCSTAT)
ECGON — External Clock Generator On Bit

This read/write bit enables external clock generator, so that the switching
process can be initiated. This bit is forced low during reset. This bit is ignored in
monitor mode with the internal oscillator bypassed, PTM or CTM mode.
1 = External clock generator enabled
0 = External clock generator disabled
ECGST — External Clock Status Bit
This read-only bit indicates whether or not an external clock source is engaged
to drive the system clock.
1 = An external clock source engaged
0 = An external clock source disengaged

11.8.2 Oscillator Trim Register (OSCTRIM)
Address: $0038
Bit 7 6 5 4 3 2 1 Bit 0
Read:
TRIM7 TRIM6 TRIM5 TRIM4 TRIM3 TRIM2 TRIM1 TRIM0
Write:
Reset: 1 0 0 0 0 0 0 0
Figure 11-5. Oscillator Trim Register (OSCTRIM)
TRIM7–TRIM0 — Internal Oscillator Trim Factor Bits

These read/write bits change the size of the internal capacitor used by the
internal oscillator. By measuring the period of the internal clock and adjusting
this factor accordingly, the frequency of the internal clock can be fine tuned.
Increasing (decreasing) this factor by one increases (decreases) the period by
approximately 0.2% of the untrimmed period (the period for TRIM = $80). The
trimmed frequency is guaranteed not to vary by more than ±5% over the full
specified range of temperature and voltage. The reset value is $80, which sets
the frequency to 12.8 MHz (3.2 MHz bus speed) ±25%.

Section 12. Input/Output Ports (PORTS)
12.1 Introduction
The MC68HC908QT1, MC68HC908QT2, and MC68HC908QT4 have five
bidirectional input-output (I/O) pins and one input only pin. The MC68HC908QY1,
MC68HC908QY2, and MC68HC908QY4 have thirteen bidirectional pins and one
input only pin. All I/O pins are programmable as inputs or outputs.
NOTE: Connect any unused I/O pins to an appropriate logic level, either VDD or VSS.
Although the I/O ports do not require termination for proper operation, termination
reduces excess current consumption and the possibility of electrostatic damage.
Figure 12-1 provides a summary of the I/O registers.
Port A Data Register Read: AWUL PTA2

R PTA5 PTA4 PTA3 PTA1 PTA0
$0000 (PTA) Write:
Port B Data Register Read:

PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0
$0001 (PTB) Write:
Data Direction Register A Read: 0

R R DDRA5 DDRA4 DDRA3 DDRA1 DDRA0
$0004 (DDRA) Write:
See page 107. Reset: 0 0 0 0 0 0 0 0
Data Direction Register B Read:

$0005 (DDRB) Write:
See page 109. Reset: 0 0 0 0 0 0 0 0
Port A Input Pullup Enable Read:

OSC2EN PTAPUE5 PTAPUE4 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0
$000B Register (PTAPUE) Write:
See page 108. Reset: 0 0 0 0 0 0 0 0
Port B Input Pullup Enable Read:

PTBPUE7 PTBPUE6 PTBPUE5 PTBPUE4 PTBPUE3 PTBPUE2 PTBPUE1 PTBPUE0
$000C Register (PTBPUE) Write:
See page 111. Reset: 0 0 0 0 0 0 0 0
Figure 12-1. I/O Port Register Summary
MOTOROLA Input/Output Ports (PORTS) 105

Input/Output Ports (PORTS)
12.2 Port A
Port A is a 6-bit special function port that shares all six of its pins with the keyboard
interrupt (KBI) module (see Section 9. Keyboard Interrupt Module (KBI)). Each
port A pin also has a software configurable pullup device if the corresponding port
pin is configured as an input port.
NOTE: PTA2 is input only.
When the IRQ function is enabled in the configuration register 2 (CONFIG2), bit 2
of the port A data register (PTA) will always read a 0. In this case, the BIH and BIL
instructions can be used to read the logic level on the PTA2 pin. When the IRQ
function is disabled, these instructions will behave as if the PTA2 pin is a logic 1.
However, reading bit 2 of PTA will read the actual logic level on the pin.
12.2.1 Port A Data Register
The port A data register (PTA) contains a data latch for each of the six port A pins.
Address: $0000
Bit 7 6 5 4 3 2 1 Bit 0
Read: AWUL PTA2
R PTA5 PTA4 PTA3 PTA1 PTA0
Write:
Additional Functions: KBI5 KBI4 KBI3 KBI2 KBI1 KBI0
Figure 12-2. Port A Data Register (PTA)
PTA[5:0] — Port A Data Bits

These read/write bits are software programmable. Data direction of each port A
pin is under the control of the corresponding bit in data direction register A.
Reset has no effect on port A data.
AWUL — Auto Wakeup Latch Data Bit
This is a read-only bit which has the value of the auto wakeup interrupt request
latch. The wakeup request signal is generated internally (see Section 4. Auto
Wakeup Module (AWU)). There is no PTA6 port nor any of the associated bits
such as PTA6 data register, pullup enable or direction.
KBI[5:0] — Port A Keyboard Interrupts
The keyboard interrupt enable bits, KBIE5–KBIE0, in the keyboard interrupt
control enable register (KBIER) enable the port A pins as external interrupt pins
(see Section 9. Keyboard Interrupt Module (KBI)).
106 Input/Output Ports (PORTS) MOTOROLA

Port A
12.2.2 Data Direction Register A
Data direction register A (DDRA) determines whether each port A pin is an input or
an output. Writing a 1 to a DDRA bit enables the output buffer for the corresponding
port A pin; a 0 disables the output buffer.
Address: $0004
Bit 7 6 5 4 3 2 1 Bit 0
Read: 0
R R DDRA5 DDRA4 DDRA3 DDRA1 DDRA0
Write:
Reset: 0 0 0 0 0 0 0 0
Figure 12-3. Data Direction Register A (DDRA)
DDRA[5:0] — Data Direction Register A Bits

These read/write bits control port A data direction. Reset clears DDRA[5:0],
configuring all port A pins as inputs.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
NOTE: Avoid glitches on port A pins by writing to the port A data register before changing
data direction register A bits from 0 to 1.
Figure 12-4 shows the port A I/O logic.
READ DDRA ($0004)
PTAPUEx
WRITE DDRA ($0004)
DDRAx
INTERNAL DATA BUS
RESET 30 k
WRITE PTA ($0000)

PTAx PTAx
READ PTA ($0000)
TO KEYBOARD INTERRUPT CIRCUIT
Figure 12-4. Port A I/O Circuit
NOTE: Figure 12-4 does not apply to PTA2
When DDRAx is a 1, reading address $0000 reads the PTAx data latch. When
DDRAx is a 0, reading address $0000 reads the voltage level on the pin. The data
latch can always be written, regardless of the state of its data direction bit.

12.2.3 Port A Input Pullup Enable Register
The port A input pullup enable register (PTAPUE) contains a software configurable
pullup device for each if the six port A pins. Each bit is individually configurable and
requires the corresponding data direction register, DDRAx, to be configured as
input. Each pullup device is automatically and dynamically disabled when its
corresponding DDRAx bit is configured as output.
Address: $000B
Bit 7 6 5 4 3 2 1 Bit 0
Read:
OSC2EN PTAPUE5 PTAPUE4 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0
Write:
Reset: 0 0 0 0 0 0 0 0
= Unimplemented
Figure 12-5. Port A Input Pullup Enable Register (PTAPUE)
OSC2EN — Enable PTA4 on OSC2 Pin

This read/write bit configures the OSC2 pin function when internal oscillator or
RC oscillator option is selected. This bit has no effect for the XTAL or external
oscillator options.
1 = OSC2 pin outputs the internal or RC oscillator clock (BUSCLKX4)
0 = OSC2 pin configured for PTA4 I/O, having all the interrupt and pullup
functions
PTAPUE[5:0] — Port A Input Pullup Enable Bits
These read/write bits are software programmable to enable pullup devices on
port A pins.
1 = Corresponding port A pin configured to have internal pull if its DDRA bit
is set to 0
0 = Pullup device is disconnected on the corresponding port A pin regardless
of the state of its DDRA bit
Table 12-1 summarizes the operation of the port A pins.
Table 12-1. Port A Pin Functions

PTAPUE DDRA PTA I/O Pin Accesses to DDRA Accesses to PTA
Bit Bit Bit Mode Read/Write Read Write
1 0 X(1) Input, VDD(2) DDRA5–DDRA0 Pin PTA5–PTA0(3)
0 0 X Input, Hi-Z(4) DDRA5–DDRA0 Pin PTA5–PTA0(3)
X 1 X Output DDRA5–DDRA0 PTA5–PTA0 PTA5–PTA0(5)
1. X = don’t care
2. I/O pin pulled to VDD by internal pullup.
3. Writing affects data register, but does not affect input.
4. Hi-Z = high impedance
5. Output does not apply to PTA2

Port B
12.3 Port B
Port B is an 8-bit general purpose I/O port. Port B is only available on the
MC68HC908QY1, MC68HC908QY2, and MC68HC908QY4.
12.3.1 Port B Data Register
The port B data register (PTB) contains a data latch for each of the eight port B
pins.
Address: $0001
Bit 7 6 5 4 3 2 1 Bit 0
Read:
PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0
Write:
Figure 12-6. Port B Data Register (PTB)
PTB[7:0] — Port B Data Bits

These read/write bits are software programmable. Data direction of each port B
pin is under the control of the corresponding bit in data direction register B.
Reset has no effect on port B data.
12.3.2 Data Direction Register B
Data direction register B (DDRB) determines whether each port B pin is an input or
an output. Writing a 1 to a DDRB bit enables the output buffer for the corresponding
port B pin; a 0 disables the output buffer.
Address: $0005
Bit 7 6 5 4 3 2 1 Bit 0
Read:
Write:
Reset: 0 0 0 0 0 0 0 0
Figure 12-7. Data Direction Register B (DDRB)
DDRB[7:0] — Data Direction Register B Bits

These read/write bits control port B data direction. Reset clears DDRB[7:0],
configuring all port B pins as inputs.
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
NOTE: Avoid glitches on port B pins by writing to the port B data register before changing
data direction register B bits from 0 to 1. Figure 12-8 shows the port B I/O logic.

READ DDRB ($0005)
PTBPUEx
WRITE DDRB ($0005)
DDRBx
INTERNAL DATA BUS

RESET 30 k
WRITE PTB ($0001)

PTBx PTBx
READ PTB ($0001)
Figure 12-8. Port B I/O Circuit
When DDRBx is a 1, reading address $0001 reads the PTBx data latch. When
DDRBx is a 0, reading address $0001 reads the voltage level on the pin. The
data latch can always be written, regardless of the state of its data direction bit.
Table 12-2 summarizes the operation of the port B pins.
Table 12-2. Port B Pin Functions
DDRB PTB I/O Pin Accesses to DDRB Accesses to PTB

Bit Bit Mode Read/Write Read Write
0 X(1) Input, Hi-Z(2) DDRB7–DDRB0 Pin PTB7–PTB0(3)

1 X Output DDRB7–DDRB0 Pin PTB7–PTB0
1. X = don’t care
3. Writing affects data register, but does not affect the input.

Port B
12.3.3 Port B Input Pullup Enable Register
The port B input pullup enable register (PTBPUE) contains a software configurable
pullup device for each of the eight port B pins. Each bit is individually configurable
and requires the corresponding data direction register, DDRBx, be configured as
input. Each pullup device is automatically and dynamically disabled when its
corresponding DDRBx bit is configured as output.
Address: $000C
Bit 7 6 5 4 3 2 1 Bit 0
Read:
PTBPUE7 PTBPUE6 PTBPUE5 PTBPUE4 PTBPUE3 PTBPUE2 PTBPUE2 PTBPUE0
Write:
Reset: 0 0 0 0 0 0 0 0
Figure 12-9. Port B Input Pullup Enable Register (PTBPUE)
PTBPUE[7:0] — Port B Input Pullup Enable Bits

These read/write bits are software programmable to enable pullup devices on
port B pins
1 = Corresponding port B pin configured to have internal pull if its DDRB bit
is set to 0
0 = Pullup device is disconnected on the corresponding port B pin regardless
of the state of its DDRB bit.
Table 12-3 summarizes the operation of the port B pins.
Table 12-3. Port B Pin Functions
PTBPUE DDRB PTB I/O Pin Accesses to DDRB Accesses to PTB

Bit Bit Bit Mode Read/Write Read Write
1 0 X(1) Input, VDD(2) DDRB7–DDRB0 Pin PTB7–PTB0(3)
0 0 X Input, Hi-Z(4) DDRB7–DDRB0 Pin PTB7–PTB0(3)

X 1 X Output DDRB7–DDRB0 PTB7–PTB0 PTB7–PTB0
1. X = don’t care
2. I/O pin pulled to VDD by internal pullup.
3. Writing affects data register, but does not affect input.


Section 13. System Integration Module (SIM)
13.1 Introduction
This section describes the system integration module (SIM), which supports up to
24 external and/or internal interrupts. Together with the central processor unit
(CPU), the SIM controls all microcontroller unit (MCU) activities. A block diagram
of the SIM is shown in Figure 13-1. Figure 13-2 is a summary of the SIM I/O
registers. The SIM is a system state controller that coordinates CPU and exception
timing.
The SIM is responsible for:
• Bus clock generation and control for CPU and peripherals
– Stop/wait/reset/break entry and recovery
– Internal clock control
• Master reset control, including power-on reset (POR) and computer
operating properly (COP) timeout
• Interrupt control:
– Acknowledge timing
– Arbitration control timing
– Vector address generation
• CPU enable/disable timing
Table 13-1. Signal Name Conventions

Signal Name Description
BUSCLKX4 Buffered clock from the internal, RC or XTAL oscillator circuit.
The BUSCLKX4 frequency divided by two. This signal is again divided by two in the SIM to
BUSCLKX2
generate the internal bus clocks (bus clock = BUSCLKX4 ÷ 4).
Address bus Internal address bus
Data bus Internal data bus
PORRST Signal from the power-on reset module to the SIM
IRST Internal reset signal
R/W Read/write signal
MOTOROLA System Integration Module (SIM) 113

System Integration Module (SIM)
MODULE STOP
MODULE WAIT
STOP/WAIT CPU STOP (FROM CPU)
CONTROL CPU WAIT (FROM CPU)
SIMOSCEN (TO OSCILLATOR)
SIM COP CLOCK

COUNTER
BUSCLKX4 (FROM OSCILLATOR)

BUSCLKX2 (FROM OSCILLATOR)
÷2
VDD
CLOCK
CONTROL CLOCK GENERATORS INTERNAL CLOCKS
INTERNAL
PULL-UP
ILLEGAL OPCODE (FROM CPU)

RESET POR CONTROL ILLEGAL ADDRESS (FROM ADDRESS
PIN LOGIC MASTER MAP DECODERS)
RESET PIN CONTROL RESET COP TIMEOUT (FROM COP MODULE)
CONTROL
SIM RESET STATUS REGISTER LVI RESET (FROM LVI MODULE)
FORCED MON MODE ENTRY (FROM MENRST MODULE)
RESET
INTERRUPT CONTROL INTERRUPT SOURCES

AND PRIORITY DECODE
CPU INTERFACE
Figure 13-1. SIM Block Diagram
114 System Integration Module (SIM) MOTOROLA

Introduction

Read: SBSW
Break Status Register R R R R R R R
$FE00 (BSR) Write: Note 1
See page 155.
Reset: 0 0 0 0 0 0 0 0
1. Writing a 0 clears SBSW.
Read: POR PIN COP ILOP ILAD MODRST LVI 0

SIM Reset Status
$FE01 Register (SRSR) Write:
See page 129.
POR: 1 0 0 0 0 0 0 0
$FE02 Reserved R R R R R R R R
Read:
Break Flag Control BCFE R R R R R R R
See page 130.
Reset: 0
Read: 0 IF5 IF4 IF3 0 IF1 0 0
Interrupt Status
$FE04 Register 1 (INT1) Write: R R R R R R R R
See page 125.
Reset: 0 0 0 0 0 0 0 0
Read: IF14 0 0 0 0 0 0 0
Interrupt Status
See page 125.
Reset: 0 0 0 0 0 0 0 0
Read: 0 0 0 0 0 0 0 IF15
Interrupt Status
See page 126.
Reset: 0 0 0 0 0 0 0 0
= Unimplemented R = Reserved
Figure 13-2. SIM I/O Register Summary

13.2 RST and IRQ Pins Initialization

RST and IRQ pins come out of reset as PTA3 and PTA2 respectively. RST and IRQ
functions can be activated by programing CONFIG2 accordingly. Refer to
Section 5. Configuration Register (CONFIG).
13.3 SIM Bus Clock Control and Generation

The bus clock generator provides system clock signals for the CPU and peripherals
on the MCU. The system clocks are generated from an incoming clock,
BUSCLKX2, as shown in Figure 13-3.
FROM BUSCLKX4
OSCILLATOR SIM COUNTER
BUSCLKX2
FROM ÷2 BUS CLOCK
GENERATORS
OSCILLATOR
SIM
Figure 13-3. SIM Clock Signals
13.3.1 Bus Timing
In user mode, the internal bus frequency is the oscillator frequency (BUSCLKX4)
divided by four.
13.3.2 Clock Start-Up from POR
When the power-on reset module generates a reset, the clocks to the CPU and
peripherals are inactive and held in an inactive phase until after the 4096
BUSCLKX4 cycle POR time out has completed. The IBUS clocks start upon
completion of the time out.
13.3.3 Clocks in Stop Mode and Wait Mode
Upon exit from stop mode by an interrupt or reset, the SIM allows BUSCLKX4 to
clock the SIM counter. The CPU and peripheral clocks do not become active until
after the stop delay time out. This time out is selectable as 4096 or 32 BUSCLKX4
cycles. See 13.7.2 Stop Mode.
In wait mode, the CPU clocks are inactive. The SIM also produces two sets of
clocks for other modules. Refer to the wait mode subsection of each module to see
if the module is active or inactive in wait mode. Some modules can be programmed
to be active in wait mode.

Reset and System Initialization
13.4 Reset and System Initialization

The MCU has these reset sources:
• Power-on reset module (POR)
• External reset pin (RST)
• Computer operating properly module (COP)
• Low-voltage inhibit module (LVI)
• Illegal opcode
• Illegal address
All of these resets produce the vector $FFFE–FFFF ($FEFE–FEFF in monitor

mode) and assert the internal reset signal (IRST). IRST causes all registers to be
returned to their default values and all modules to be returned to their reset states.
An internal reset clears the SIM counter (see 13.5 SIM Counter), but an external
reset does not. Each of the resets sets a corresponding bit in the SIM reset status
register (SRSR). See 13.8 SIM Registers.
13.4.1 External Pin Reset
The RST pin circuits include an internal pullup device. Pulling the asynchronous
RST pin low halts all processing. The PIN bit of the SIM reset status register
(SRSR) is set as long as RST is held low for at least the minimum tRL time.
Figure 13-4 shows the relative timing. The RST pin function is only available if the
RSTEN bit is set in the CONFIG1 register.
BUSCLKX2
RST
ADDRESS BUS PC VECT H VECT L
Figure 13-4. External Reset Timing
13.4.2 Active Resets from Internal Sources
The RST pin is initially setup as a general-purpose input after a POR. Setting the
RSTEN bit in the CONFIG1 register enables the pin for the reset function. This
section assumes the RSTEN bit is set when describing activity on the RST pin.
NOTE: For POR and LVI resets, the SIM cycles through 4096 BUSCLKX4 cycles. The
internal reset signal then follows the sequence from the falling edge of RST shown
in Figure 13-5.
The COP reset is asynchronous to the bus clock.

The active reset feature allows the part to issue a reset to peripherals and other
chips within a system built around the MCU.
All internal reset sources actively pull the RST pin low for 32 BUSCLKX4 cycles to
allow resetting of external peripherals. The internal reset signal IRST continues to
be asserted for an additional 32 cycles (see Figure 13-5). An internal reset can be
caused by an illegal address, illegal opcode, COP time out, LVI, or POR (see
Figure 13-6).
IRST
RST RST PULLED LOW BY MCU
32 CYCLES 32 CYCLES
BUSCLKX4
ADDRESS
BUS VECTOR HIGH
Figure 13-5. Internal Reset Timing
ILLEGAL ADDRESS RST

ILLEGAL OPCODE RST
COPRST INTERNAL RESET
POR
LVI
Figure 13-6. Sources of Internal Reset
Table 13-2. PIN Bit Set Timing

Reset Type Number of Cycles Required to Set PIN
POR 4163 (4096 + 64 + 3)
All others 67 (64 + 3)
13.4.2.1 Power-On Reset
When power is first applied to the MCU, the power-on reset module (POR)
generates a pulse to indicate that power on has occurred. The SIM counter counts
out 4096 BUSCLKX4 cycles. Sixty-four BUSCLKX4 cycles later, the CPU and
memories are released from reset to allow the reset vector sequence to occur.

Reset and System Initialization
At power on, the following events occur:

• A POR pulse is generated.
• The internal reset signal is asserted.
• The SIM enables the oscillator to drive BUSCLKX4.
• Internal clocks to the CPU and modules are held inactive for
4096 BUSCLKX4 cycles to allow stabilization of the oscillator.
• The POR bit of the SIM reset status register (SRSR) is set
See Figure 13-7.
OSC1
PORRST
4096 32 32
CYCLES CYCLES CYCLES
BUSCLKX4
BUSCLKX2
RST
ADDRESS BUS $FFFE $FFFF
Figure 13-7. POR Recovery
13.4.2.2 Computer Operating Properly (COP) Reset
An input to the SIM is reserved for the COP reset signal. The overflow of the COP
counter causes an internal reset and sets the COP bit in the SIM reset status
register (SRSR). The SIM actively pulls down the RST pin for all internal reset
sources.
To prevent a COP module time out, write any value to location $FFFF. Writing to
location $FFFF clears the COP counter and stages 12–5 of the SIM counter. The
SIM counter output, which occurs at least every (212 – 24) BUSCLKX4 cycles,
drives the COP counter. The COP should be serviced as soon as possible out of
reset to guarantee the maximum amount of time before the first time out.
The COP module is disabled during a break interrupt with monitor mode when
BDCOP bit is set in break auxiliary register (BRKAR).

13.4.2.3 Illegal Opcode Reset
The SIM decodes signals from the CPU to detect illegal instructions. An illegal
instruction sets the ILOP bit in the SIM reset status register (SRSR) and causes a
reset.
If the stop enable bit, STOP, in the mask option register is 0, the SIM treats the
STOP instruction as an illegal opcode and causes an illegal opcode reset. The SIM
actively pulls down the RST pin for all internal reset sources.
13.4.2.4 Illegal Address Reset
An opcode fetch from an unmapped address generates an illegal address reset.

The SIM verifies that the CPU is fetching an opcode prior to asserting the ILAD bit
in the SIM reset status register (SRSR) and resetting the MCU. A data fetch from
an unmapped address does not generate a reset. The SIM actively pulls down the
RST pin for all internal reset sources. See Figure 2-1. Memory Map for memory
ranges.
13.4.2.5 Low-Voltage Inhibit (LVI) Reset
The LVI asserts its output to the SIM when the VDD voltage falls to the LVI trip
voltage VTRIPF. The LVI bit in the SIM reset status register (SRSR) is set, and the
external reset pin (RST) is held low while the SIM counter counts out 4096
BUSCLKX4 cycles after VDD rises above VTRIPR. Sixty-four BUSCLKX4 cycles
later, the CPU and memories are released from reset to allow the reset vector
sequence to occur. The SIM actively pulls down the (RST) pin for all internal reset
sources.
13.5 SIM Counter

The SIM counter is used by the power-on reset module (POR) and in stop mode
recovery to allow the oscillator time to stabilize before enabling the internal bus
(IBUS) clocks. The SIM counter also serves as a prescaler for the computer
operating properly module (COP). The SIM counter uses 12 stages for counting,
followed by a 13th stage that triggers a reset of SIM counters and supplies the clock
for the COP module. The SIM counter is clocked by the falling edge of BUSCLKX4.
13.5.1 SIM Counter During Power-On Reset

The power-on reset module (POR) detects power applied to the MCU. At
power-on, the POR circuit asserts the signal PORRST. Once the SIM is initialized,
it enables the oscillator to drive the bus clock state machine.

Exception Control
13.5.2 SIM Counter During Stop Mode Recovery
The SIM counter also is used for stop mode recovery. The STOP instruction clears
the SIM counter. After an interrupt, break, or reset, the SIM senses the state of the
short stop recovery bit, SSREC, in the configuration register 1 (CONFIG1). If the
SSREC bit is a 1, then the stop recovery is reduced from the normal delay of 4096
BUSCLKX4 cycles down to 32 BUSCLKX4 cycles. This is ideal for applications
using canned oscillators that do not require long start-up times from stop mode.
External crystal applications should use the full stop recovery time, that is, with
SSREC cleared in the configuration register 1 (CONFIG1).
13.5.3 SIM Counter and Reset States
External reset has no effect on the SIM counter (see 13.7.2 Stop Mode for details.)
The SIM counter is free-running after all reset states. See 13.4.2 Active Resets
from Internal Sources for counter control and internal reset recovery sequences.
13.6 Exception Control

Normal sequential program execution can be changed in three different ways:
1. Interrupts
a. Maskable hardware CPU interrupts
b. Non-maskable software interrupt instruction (SWI)
2. Reset
3. Break interrupts
13.6.1 Interrupts
An interrupt temporarily changes the sequence of program execution to respond to

a particular event. Figure 13-8 flow charts the handling of system interrupts.
Interrupts are latched, and arbitration is performed in the SIM at the start of
interrupt processing. The arbitration result is a constant that the CPU uses to
determine which vector to fetch. Once an interrupt is latched by the SIM, no other
interrupt can take precedence, regardless of priority, until the latched interrupt is
serviced (or the I bit is cleared).
At the beginning of an interrupt, the CPU saves the CPU register contents on the
stack and sets the interrupt mask (I bit) to prevent additional interrupts. At the end
of an interrupt, the RTI instruction recovers the CPU register contents from the
stack so that normal processing can resume. Figure 13-9 shows interrupt entry
timing. Figure 13-10 shows interrupt recovery timing.

FROM RESET
YES
BREAK INTERRUPT?
I BIT SET?
NO
YES
I BIT SET?
NO
IRQ YES
INTERRUPT?
NO
TIMER YES
INTERRUPT?
NO STACK CPU REGISTERS

SET I BIT
LOAD PC WITH INTERRUPT VECTOR
(AS MANY INTERRUPTS AS EXIST ON CHIP)
FETCH NEXT
INSTRUCTION
SWI YES
INSTRUCTION?
NO
RTI YES
INSTRUCTION? UNSTACK CPU REGISTERS
NO
EXECUTE INSTRUCTION
Figure 13-8. Interrupt Processing

Exception Control
MODULE
INTERRUPT
I BIT
ADDRESS BUS DUMMY SP SP – 1 SP – 2 SP – 3 SP – 4 VECT H VECT L START ADDR
DATA BUS DUMMY PC – 1[7:0] PC – 1[15:8] X A CCR V DATA H V DATA L OPCODE
R/W
Figure 13-9. Interrupt Entry

MODULE
INTERRUPT
I BIT
ADDRESS BUS SP – 4 SP – 3 SP – 2 SP – 1 SP PC PC + 1
DATA BUS CCR A X PC – 1[7:0] PC – 1[15:8] OPCODE OPERAND
R/W
Figure 13-10. Interrupt Recovery
13.6.1.1 Hardware Interrupts
A hardware interrupt does not stop the current instruction. Processing of a

hardware interrupt begins after completion of the current instruction. When the
current instruction is complete, the SIM checks all pending hardware interrupts.
If interrupts are not masked (I bit clear in the condition code register), and if the
corresponding interrupt enable bit is set, the SIM proceeds with interrupt
processing; otherwise, the next instruction is fetched and executed.
If more than one interrupt is pending at the end of an instruction execution, the
highest priority interrupt is serviced first. Figure 13-11 demonstrates what happens
when two interrupts are pending. If an interrupt is pending upon exit from the
original interrupt service routine, the pending interrupt is serviced before the LDA
instruction is executed.
The LDA opcode is prefetched by both the INT1 and INT2 return-from-interrupt
(RTI) instructions. However, in the case of the INT1 RTI prefetch, this is a
redundant operation.
NOTE: To maintain compatibility with the M6805 Family, the H register is not pushed on
the stack during interrupt entry. If the interrupt service routine modifies the H
register or uses the indexed addressing mode, software should save the H register
and then restore it prior to exiting the routine.

CLI
LDA #$FF BACKGROUND ROUTINE
INT1 PSHH
INT1 INTERRUPT SERVICE ROUTINE

PULH
RTI
INT2 PSHH
INT2 INTERRUPT SERVICE ROUTINE

PULH
RTI
Figure 13-11. Interrupt Recognition Example
13.6.1.2 SWI Instruction

The SWI instruction is a non-maskable instruction that causes an interrupt
regardless of the state of the interrupt mask (I bit) in the condition code register.
NOTE: A software interrupt pushes PC onto the stack. A software interrupt does not push
PC – 1, as a hardware interrupt does.
13.6.2 Interrupt Status Registers

The flags in the interrupt status registers identify maskable interrupt sources.
Table 13-3 summarizes the interrupt sources and the interrupt status register flags
that they set. The interrupt status registers can be useful for debugging.
Table 13-3. Interrupt Sources
INT
Vector
Priority Source Flag Mask(1) Register
Address
Flag
Highest Reset — — — $FFFE–$FFFF
SWI instruction — — — $FFFC–$FFFD
IRQ pin IRQF IMASK IF1 $FFFA–$FFFB
Timer channel 0 interrupt CH0F CH0IE IF3 $FFF6–$FFF7
Timer channel 1 interrupt CH1F CH1IE IF4 $FFF4–$FFF5
Timer overflow interrupt TOF TOIE IF5 $FFF2–$FFF3
Keyboard interrupt KEYF IMASKK IF14 $FFE0–$FFE1
Lowest ADC conversion complete interrupt COCO AIEN IF15 $FFDE–$FFDF
1. The I bit in the condition code register is a global mask for all interrupt sources except the SWI
instruction.

Exception Control
13.6.2.1 Interrupt Status Register 1
Address: $FE04
Bit 7 6 5 4 3 2 1 Bit 0
Read: 0 IF5 IF4 IF3 0 IF1 0 0
Write: R R R R R R R R
Reset: 0 0 0 0 0 0 0 0
R = Reserved
Figure 13-12. Interrupt Status Register 1 (INT1)
IF1 and IF3–IF5 — Interrupt Flags

These flags indicate the presence of interrupt requests from the sources shown
in Table 13-3.
1 = Interrupt request present
0 = No interrupt request present
Bit 0, 1, 3, and 7 — Always read 0
Address: $FE05
Bit 7 6 5 4 3 2 1 Bit 0
Read: IF14 0 0 0 0 0 0 0
Reset: 0 0 0 0 0 0 0 0
R = Reserved
IF14 — Interrupt Flags

This flag indicates the presence of interrupt requests from the sources shown in
Table 13-3.
Bit 0–6 — Always read 0

Address: $FE06
Bit 7 6 5 4 3 2 1 Bit 0
Read: 0 0 0 0 0 0 0 IF15
Reset: 0 0 0 0 0 0 0 0
R = Reserved
IF15 — Interrupt Flags

These flags indicate the presence of interrupt requests from the sources shown
in Table 13-3.
Bit 1–7 — Always read 0
13.6.3 Reset
All reset sources always have equal and highest priority and cannot be arbitrated.
13.6.4 Break Interrupts
The break module can stop normal program flow at a software programmable
break point by asserting its break interrupt output. (See Section 15. Development
Support.) The SIM puts the CPU into the break state by forcing it to the SWI vector
location. Refer to the break interrupt subsection of each module to see how each
module is affected by the break state.
13.6.5 Status Flag Protection in Break Mode
The SIM controls whether status flags contained in other modules can be cleared
during break mode. The user can select whether flags are protected from being
cleared by properly initializing the break clear flag enable bit (BCFE) in the break
flag control register (BFCR).
Protecting flags in break mode ensures that set flags will not be cleared while in
break mode. This protection allows registers to be freely read and written during
break mode without losing status flag information.
Setting the BCFE bit enables the clearing mechanisms. Once cleared in break
mode, a flag remains cleared even when break mode is exited. Status flags with a
two-step clearing mechanism — for example, a read of one register followed by the
read or write of another — are protected, even when the first step is accomplished
prior to entering break mode. Upon leaving break mode, execution of the second
step will clear the flag as normal.

Low-Power Modes
13.7 Low-Power Modes

Executing the WAIT or STOP instruction puts the MCU in a low power-
consumption mode for standby situations. The SIM holds the CPU in a non-clocked
state. The operation of each of these modes is described below. Both STOP and
WAIT clear the interrupt mask (I) in the condition code register, allowing interrupts
to occur.
13.7.1 Wait Mode
In wait mode, the CPU clocks are inactive while the peripheral clocks continue to
run. Figure 13-15 shows the timing for wait mode entry.
ADDRESS BUS WAIT ADDR WAIT ADDR + 1 SAME SAME
DATA BUS PREVIOUS DATA NEXT OPCODE SAME SAME
R/W
NOTE: Previous data can be operand data or the WAIT opcode, depending on the last instruction.
Figure 13-15. Wait Mode Entry Timing
A module that is active during wait mode can wake up the CPU with an interrupt if
the interrupt is enabled. Stacking for the interrupt begins one cycle after the WAIT
instruction during which the interrupt occurred. In wait mode, the CPU clocks are
inactive. Refer to the wait mode subsection of each module to see if the module is
active or inactive in wait mode. Some modules can be programmed to be active in
wait mode.
Wait mode can also be exited by a reset (or break in emulation mode). A break
interrupt during wait mode sets the SIM break stop/wait bit, SBSW, in the break
status register (BSR). If the COP disable bit, COPD, in the configuration register
is 0, then the computer operating properly module (COP) is enabled and remains
active in wait mode.
Figure 13-16 and Figure 13-17 show the timing for wait recovery.
ADDRESS BUS $6E0B $6E0C $00FF $00FE $00FD $00FC
DATA BUS $A6 $A6 $A6 $01 $0B $6E
EXITSTOPWAIT
NOTE: EXITSTOPWAIT = RST pin OR CPU interrupt OR break interrupt
Figure 13-16. Wait Recovery from Interrupt

32 32
CYCLES CYCLES
ADDRESS BUS $6E0B RSTVCT H RSTVCT L
DATA BUS $A6 $A6 $A6
RST
BUSCLKX4
Figure 13-17. Wait Recovery from Internal Reset
13.7.2 Stop Mode
In stop mode, the SIM counter is reset and the system clocks are disabled. An
interrupt request from a module can cause an exit from stop mode. Stacking for
interrupts begins after the selected stop recovery time has elapsed. Reset or break
also causes an exit from stop mode.
The SIM disables the oscillator signals (BUSCLKX2 and BUSCLKX4) in stop
mode, stopping the CPU and peripherals. Stop recovery time is selectable using
the SSREC bit in the configuration register 1 (CONFIG1). If SSREC is set, stop
recovery is reduced from the normal delay of 4096 BUSCLKX4 cycles down to 32.
This is ideal for the internal oscillator, RC oscillator, and external oscillator options
which do not require long start-up times from stop mode.
NOTE: External crystal applications should use the full stop recovery time by clearing the
SSREC bit.
The SIM counter is held in reset from the execution of the STOP instruction until
the beginning of stop recovery. It is then used to time the recovery period.
Figure 13-18 shows stop mode entry timing and Figure 13-19 shows the stop
mode recovery time from interrupt or break.
NOTE: To minimize stop current, all pins configured as inputs should be driven to a logic 1
or logic 0.
CPUSTOP
ADDRESS BUS STOP ADDR STOP ADDR + 1 SAME SAME
DATA BUS PREVIOUS DATA NEXT OPCODE SAME SAME
R/W
NOTE: Previous data can be operand data or the STOP opcode, depending on the last instruction.
Figure 13-18. Stop Mode Entry Timing

SIM Registers
STOP RECOVERY PERIOD
BUSCLKX4
INTERRUPT
ADDRESS BUS STOP +1 STOP + 2 STOP + 2 SP SP – 1 SP – 2 SP – 3
Figure 13-19. Stop Mode Recovery from Interrupt
13.8 SIM Registers

The SIM has three memory mapped registers. Table 13-4 shows the mapping of
these registers.
Table 13-4. SIM Registers

Address Register Access Mode
$FE00 BSR User
$FE01 SRSR User
$FE03 BFCR User
13.8.1 SIM Reset Status Register
This register contains seven flags that show the source of the last reset. Clear the
SIM reset status register by reading it. A power-on reset sets the POR bit.
Address: $FE01
Bit 7 6 5 4 3 2 1 Bit 0
Read: POR PIN COP ILOP ILAD MODRST LVI 0
Write:
POR: 1 0 0 0 0 0 0 0
= Unimplemented
Figure 13-20. SIM Reset Status Register (SRSR)
POR — Power-On Reset Bit

1 = Last reset caused by POR circuit
0 = Read of SRSR
PIN — External Reset Bit
1 = Last reset caused by external reset pin (RST)
0 = POR or read of SRSR

COP — Computer Operating Properly Reset Bit

1 = Last reset caused by COP counter
ILOP — Illegal Opcode Reset Bit
1 = Last reset caused by an illegal opcode
ILAD — Illegal Address Reset Bit (illegal attempt to fetch an opcode from an
unimplemented address)
1 = Last reset caused by an opcode fetch from an illegal address
MODRST — Monitor Mode Entry Module Reset bit
1 = Last reset caused by monitor mode entry when vector locations $FFFE
and $FFFF are $FF after POR while IRQ = VDD
LVI — Low Voltage Inhibit Reset bit
1 = Last reset caused by LVI circuit
13.8.2 Break Flag Control Register
The break control register (BFCR) contains a bit that enables software to clear
status bits while the MCU is in a break state.
Address: $FE03
Bit 7 6 5 4 3 2 1 Bit 0
Read:
BCFE R R R R R R R
Write:
Reset: 0
R = Reserved
Figure 13-21. Break Flag Control Register (BFCR)
BCFE — Break Clear Flag Enable Bit

This read/write bit enables software to clear status bits by accessing status
registers while the MCU is in a break state. To clear status bits during the break
state, the BCFE bit must be set.
1 = Status bits clearable during break
0 = Status bits not clearable during break

Section 14. Timer Interface Module (TIM)
14.1 Introduction
This section describes the timer interface module (TIM). The TIM is a two-channel
timer that provides a timing reference with input capture, output compare, and
pulse-width-modulation functions. Figure 14-2 is a block diagram of the TIM.
14.2 Features
Features of the TIM include the following:
• Two input capture/output compare channels
– Rising-edge, falling-edge, or any-edge input capture trigger
– Set, clear, or toggle output compare action
• Buffered and unbuffered pulse width modulation (PWM) signal generation
• Programmable TIM clock input
– 7-frequency internal bus clock prescaler selection
– External TIM clock input
• Free-running or modulo up-count operation
• Toggle any channel pin on overflow
• TIM counter stop and reset bits
14.3 Pin Name Conventions

The TIM shares two input/output (I/O) pins with two port A I/O pins. The full names
of the TIM I/O pins are listed in Table 14-1. The generic pin name appear in the
text that follows.
Table 14-1. Pin Name Conventions

TIM Generic Pin Names: TCH0 TCH1
Full TIM Pin Names: PTA0/TCH0 PTA1/TCH1
MOTOROLA Timer Interface Module (TIM) 131

Timer Interface Module (TIM)
PTA0/AD0/TCH0/KBI0
CLOCK
DDRA
PTA
PTA3/RST/KBI3
MODULE
PTA5/OSC1/AD3/KBI5
M68HC08 CPU
SINGLE INTERRUPT
PTB0 MODULE
PTB1
PTB2
BREAK
DDRB
PTB3
PTB
PTB4 MODULE
PTB5
PTB6 POWER-ON RESET
PTB7 MODULE

USER FLASH MODULE
128 BYTES RAM
COP
MODULE
VDD
VSS

Figure 14-1. Block Diagram Highlighting TIM Block and Pins
132 Timer Interface Module (TIM) MOTOROLA


Figure 14-2 shows the structure of the TIM. The central component of the TIM is
the 16-bit TIM counter that can operate as a free-running counter or a modulo
up-counter. The TIM counter provides the timing reference for the input capture
and output compare functions. The TIM counter modulo registers,
TMODH:TMODL, control the modulo value of the TIM counter. Software can read
the TIM counter value at any time without affecting the counting sequence.
The two TIM channels are programmable independently as input capture or output
compare channels.
PRESCALER SELECT
INTERNAL
BUS CLOCK PRESCALER
TSTOP
PS2 PS1 PS0
TRST
16-BIT COUNTER TOF INTERRUPT

LOGIC
TOIE
16-BIT COMPARATOR
TMODH:TMODL
TOV0
CHANNEL 0 ELS0B ELS0A CH0MAX PORT
TCH0
LOGIC
16-BIT COMPARATOR
TCH0H:TCH0L CH0F
16-BIT LATCH INTERRUPT
LOGIC
MS0A CH0IE
MS0B
TOV1
CHANNEL 1 ELS1B ELS1A CH1MAX PORT
TCH1
INTERNAL BUS
LOGIC
16-BIT COMPARATOR
TCH1H:TCH1L CH1F
16-BIT LATCH INTERRUPT
CH1IE LOGIC
MS1A
Figure 14-2. TIM Block Diagram


Read: TOF 0 0
TIM Status and Control Register TOIE TSTOP PS2 PS1 PS0
$0020 (TSC) Write: 0 TRST
See page 141.
Reset: 0 0 1 0 0 0 0 0
Read: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
TIM Counter Register High
$0021 (TCNTH) Write:
See page 143.
Reset: 0 0 0 0 0 0 0 0
TIM Counter Register Low
$0022 (TCNTL) Write:
See page 143.
Reset: 0 0 0 0 0 0 0 0
Read:
TIM Counter Modulo Register Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
$0023 High (TMODH) Write:
See page 143.
Reset: 1 1 1 1 1 1 1 1
Read:
TIM Counter Modulo Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$0024 Low (TMODL) Write:
See page 143.
Reset: 1 1 1 1 1 1 1 1
Read: CH0F
TIM Channel 0 Status and CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX
See page 144.
Reset: 0 0 0 0 0 0 0 0
Read:
TIM Channel 0 Register High Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
$0026 (TCH0H) Write:
See page 147.
Read:
TIM Channel 0 Register Low Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$0027 (TCH0L) Write:
See page 147.
Read: CH1F 0
TIM Channel 1 Status and CH1IE MS1A ELS1B ELS1A TOV1 CH1MAX
See page 144.
Reset: 0 0 0 0 0 0 0 0
Read:
TIM Channel 1 Register High Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
$0029 (TCH1H) Write:
See page 147.
Read:
TIM Channel 1 Register Low Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$002A (TCH1L) Write:
See page 147.
= Unimplemented
Figure 14-3. TIM I/O Register Summary

14.4.1 TIM Counter Prescaler
The TIM clock source is one of the seven prescaler outputs or the TIM clock pin,
TCLK. The prescaler generates seven clock rates from the internal bus clock. The
prescaler select bits, PS[2:0], in the TIM status and control register (TSC) select
the TIM clock source.
14.4.2 Input Capture
With the input capture function, the TIM can capture the time at which an external
event occurs. When an active edge occurs on the pin of an input capture channel,
the TIM latches the contents of the TIM counter into the TIM channel registers,
TCHxH:TCHxL. The polarity of the active edge is programmable. Input captures
can generate TIM central processor unit (CPU) interrupt requests.
14.4.3 Output Compare
With the output compare function, the TIM can generate a periodic pulse with a
programmable polarity, duration, and frequency. When the counter reaches the
value in the registers of an output compare channel, the TIM can set, clear, or
toggle the channel pin. Output compares can generate TIM CPU interrupt
requests.
14.4.3.1 Unbuffered Output Compare
Any output compare channel can generate unbuffered output compare pulses as
described in 14.4.3 Output Compare. The pulses are unbuffered because
changing the output compare value requires writing the new value over the old
value currently in the TIM channel registers.
An unsynchronized write to the TIM channel registers to change an output compare

value could cause incorrect operation for up to two counter overflow periods. For
example, writing a new value before the counter reaches the old value but after the
counter reaches the new value prevents any compare during that counter overflow
period. Also, using a TIM overflow interrupt routine to write a new, smaller output
compare value may cause the compare to be missed. The TIM may pass the new
value before it is written.
Use the following methods to synchronize unbuffered changes in the output

compare value on channel x:
• When changing to a smaller value, enable channel x output compare
interrupts and write the new value in the output compare interrupt routine.
The output compare interrupt occurs at the end of the current output
compare pulse. The interrupt routine has until the end of the counter
overflow period to write the new value.

• When changing to a larger output compare value, enable TIM overflow

interrupts and write the new value in the TIM overflow interrupt routine. The
TIM overflow interrupt occurs at the end of the current counter overflow
period. Writing a larger value in an output compare interrupt routine (at the
end of the current pulse) could cause two output compares to occur in the
same counter overflow period.
14.4.3.2 Buffered Output Compare
Channels 0 and 1 can be linked to form a buffered output compare channel whose
output appears on the TCH0 pin. The TIM channel registers of the linked pair
alternately control the output.
Setting the MS0B bit in TIM channel 0 status and control register (TSC0) links
channel 0 and channel 1. The output compare value in the TIM channel 0 registers
initially controls the output on the TCH0 pin. Writing to the TIM channel 1 registers
enables the TIM channel 1 registers to synchronously control the output after the
TIM overflows. At each subsequent overflow, the TIM channel registers (0 or 1) that
control the output are the ones written to last. TSC0 controls and monitors the
buffered output compare function, and TIM channel 1 status and control register
(TSC1) is unused. While the MS0B bit is set, the channel 1 pin, TCH1, is available
as a general-purpose I/O pin.
NOTE: In buffered output compare operation, do not write new output compare values to
the currently active channel registers. User software should track the currently
active channel to prevent writing a new value to the active channel. Writing to the
active channel registers is the same as generating unbuffered output compares.
14.4.4 Pulse Width Modulation (PWM)
By using the toggle-on-overflow feature with an output compare channel, the TIM
can generate a PWM signal. The value in the TIM counter modulo registers
determines the period of the PWM signal. The channel pin toggles when the
counter reaches the value in the TIM counter modulo registers. The time between
overflows is the period of the PWM signal
As Figure 14-4 shows, the output compare value in the TIM channel registers
determines the pulse width of the PWM signal. The time between overflow and
output compare is the pulse width. Program the TIM to clear the channel pin on
output compare if the state of the PWM pulse is logic 1 (ELSxA = 0). Program the
TIM to set the pin if the state of the PWM pulse is logic 0 (ELSxA = 1).
The value in the TIM counter modulo registers and the selected prescaler output
determines the frequency of the PWM output. The frequency of an 8-bit PWM
signal is variable in 256 increments. Writing $00FF (255) to the TIM counter
modulo registers produces a PWM period of 256 times the internal bus clock period
if the prescaler select value is 000. See 14.9.1 TIM Status and Control Register.

The value in the TIM channel registers determines the pulse width of the PWM
output. The pulse width of an 8-bit PWM signal is variable in 256 increments.
Writing $0080 (128) to the TIM channel registers produces a duty cycle of 128/256
or 50%.
OVERFLOW OVERFLOW OVERFLOW
PERIOD
PULSE
WIDTH
TCHx
OUTPUT OUTPUT OUTPUT

COMPARE COMPARE COMPARE
Figure 14-4. PWM Period and Pulse Width
14.4.4.1 Unbuffered PWM Signal Generation
Any output compare channel can generate unbuffered PWM pulses as described
in 14.4.4 Pulse Width Modulation (PWM). The pulses are unbuffered because
changing the pulse width requires writing the new pulse width value over the old
value currently in the TIM channel registers.
An unsynchronized write to the TIM channel registers to change a pulse width

value could cause incorrect operation for up to two PWM periods. For example,
writing a new value before the counter reaches the old value but after the counter
reaches the new value prevents any compare during that PWM period. Also, using
a TIM overflow interrupt routine to write a new, smaller pulse width value may
cause the compare to be missed. The TIM may pass the new value before it is
written.
Use the following methods to synchronize unbuffered changes in the PWM pulse
width on channel x:
• When changing to a shorter pulse width, enable channel x output compare
interrupts and write the new value in the output compare interrupt routine.
The output compare interrupt occurs at the end of the current pulse. The
interrupt routine has until the end of the PWM period to write the new value.
• When changing to a longer pulse width, enable TIM overflow interrupts and
write the new value in the TIM overflow interrupt routine. The TIM overflow
interrupt occurs at the end of the current PWM period. Writing a larger value
in an output compare interrupt routine (at the end of the current pulse) could
cause two output compares to occur in the same PWM period.
NOTE: In PWM signal generation, do not program the PWM channel to toggle on output
compare. Toggling on output compare prevents reliable 0% duty cycle generation

and removes the ability of the channel to self-correct in the event of software error
or noise. Toggling on output compare also can cause incorrect PWM signal
generation when changing the PWM pulse width to a new, much larger value.
14.4.4.2 Buffered PWM Signal Generation
Channels 0 and 1 can be linked to form a buffered PWM channel whose output
appears on the TCH0 pin. The TIM channel registers of the linked pair alternately
control the pulse width of the output.
Setting the MS0B bit in TIM channel 0 status and control register (TSC0) links
channel 0 and channel 1. The TIM channel 0 registers initially control the pulse
width on the TCH0 pin. Writing to the TIM channel 1 registers enables the TIM
channel 1 registers to synchronously control the pulse width at the beginning of the
next PWM period. At each subsequent overflow, the TIM channel registers (0 or 1)
that control the pulse width are the ones written to last. TSC0 controls and monitors
the buffered PWM function, and TIM channel 1 status and control register (TSC1)
is unused. While the MS0B bit is set, the channel 1 pin, TCH1, is available as a
general-purpose I/O pin.
NOTE: In buffered PWM signal generation, do not write new pulse width values to the
currently active channel registers. User software should track the currently active
channel to prevent writing a new value to the active channel. Writing to the active
channel registers is the same as generating unbuffered PWM signals.
14.4.4.3 PWM Initialization
To ensure correct operation when generating unbuffered or buffered PWM signals,

use the following initialization procedure:
1. In the TIM status and control register (TSC):
a. Stop the TIM counter by setting the TIM stop bit, TSTOP.
b. Reset the TIM counter and prescaler by setting the TIM reset bit,
TRST.
2. In the TIM counter modulo registers (TMODH:TMODL), write the value for
the required PWM period
3. In the TIM channel x registers (TCHxH:TCHxL), write the value for the
required pulse width.
4. In TIM channel x status and control register (TSCx):
a. Write 0:1 (polarity 1 — to clear output on compare) or 1:0 (polarity 0 —
to set output on compare) to the mode select bits, MSxB:MSxA. See
Table 14-3.
b. Write 1 to the toggle-on-overflow bit, TOVx.

Interrupts
c. Write 1:0 (to clear output on compare) or 1:1 (to set output on compare)
to the edge/level select bits, ELSxB:ELSxA. The output action on
compare must force the output to the complement of the pulse width
level. See Table 14-3.
NOTE: In PWM signal generation, do not program the PWM channel to toggle on output
compare. Toggling on output compare prevents reliable 0% duty cycle generation
and removes the ability of the channel to self-correct in the event of software error
or noise. Toggling on output compare can also cause incorrect PWM signal
generation when changing the PWM pulse width to a new, much larger value.
5. In the TIM status control register (TSC), clear the TIM stop bit, TSTOP.
Setting MS0B links channels 0 and 1 and configures them for buffered PWM
operation. The TIM channel 0 registers (TCH0H:TCH0L) initially control the
buffered PWM output. TIM status control register 0 (TSCR0) controls and monitors
the PWM signal from the linked channels. MS0B takes priority over MS0A.
Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIM overflows.
Subsequent output compares try to force the output to a state it is already in and
have no effect. The result is a 0% duty cycle output.
Setting the channel x maximum duty cycle bit (CHxMAX) and setting the TOVx bit
generates a 100% duty cycle output. See 14.9.4 TIM Channel Status and Control
Registers.
14.5 Interrupts
The following TIM sources can generate interrupt requests:
• TIM overflow flag (TOF) — The TOF bit is set when the TIM counter reaches
the modulo value programmed in the TIM counter modulo registers. The TIM
overflow interrupt enable bit, TOIE, enables TIM overflow CPU interrupt
requests. TOF and TOIE are in the TIM status and control register.
• TIM channel flags (CH1F:CH0F) — The CHxF bit is set when an input
capture or output compare occurs on channel x. Channel x TIM CPU
interrupt requests are controlled by the channel x interrupt enable bit,
CHxIE. Channel x TIM CPU interrupt requests are enabled when CHxIE =1.
CHxF and CHxIE are in the TIM channel x status and control register.
14.6 Wait Mode

The WAIT instruction puts the MCU in low power-consumption standby mode.
The TIM remains active after the execution of a WAIT instruction. In wait mode the
TIM registers are not accessible by the CPU. Any enabled CPU interrupt request
from the TIM can bring the MCU out of wait mode.

If TIM functions are not required during wait mode, reduce power consumption by
stopping the TIM before executing the WAIT instruction.
14.7 TIM During Break Interrupts

A break interrupt stops the TIM counter.
The system integration module (SIM) controls whether status bits in other modules
register (BFCR) enables software to clear status bits during the break state. See
13.8.2 Break Flag Control Register.
To allow software to clear status bits during a break interrupt, write a 1 to the BCFE
bit. If a status bit is cleared during the break state, it remains cleared when the MCU
exits the break state.
To protect status bits during the break state, write a 0 to the BCFE bit. With BCFE
at 0 (its default state), software can read and write I/O registers during the break
state without affecting status bits. Some status bits have a two-step read/write
clearing procedure. If software does the first step on such a bit before the break,
the bit cannot change during the break state as long as BCFE is at 0. After the
break, doing the second step clears the status bit.
14.8 Input/Output Signals

Port A shares three of its pins with the TIM. Two TIM channel I/O pins are
PTA0/TCH0 and PTA1/TCH1 and an alternate clock source is PTA2/TCLK.
14.8.1 TIM Clock Pin (PTA2/TCLK)
PTA2/TCLK is an external clock input that can be the clock source for the TIM
counter instead of the prescaled internal bus clock. Select the PTA2/TCLK input
by writing 1s to the three prescaler select bits, PS[2–0]. (See 14.9.1 TIM Status
and Control Register.) When the PTA2/TCLK pin is the TIM clock input, it is an
input regardless of port pin initialization.
14.8.2 TIM Channel I/O Pins (PTA0/TCH0 and PTA1/TCH1)
Each channel I/O pin is programmable independently as an input capture pin or an

output compare pin. PTA0/TCH0 can be configured as a buffered output compare
or buffered PWM pin.


The following I/O registers control and monitor operation of the TIM:
• TIM status and control register (TSC)
• TIM control registers (TCNTH:TCNTL)
• TIM counter modulo registers (TMODH:TMODL)
• TIM channel status and control registers (TSC0 and TSC1)
• TIM channel registers (TCH0H:TCH0L and TCH1H:TCH1L)
14.9.1 TIM Status and Control Register
The TIM status and control register (TSC) does the following:
• Enables TIM overflow interrupts
• Flags TIM overflows
• Stops the TIM counter
• Resets the TIM counter
• Prescales the TIM counter clock
Address: $0020
Bit 7 6 5 4 3 2 1 Bit 0
Read: TOF 0 0
TOIE TSTOP PS2 PS1 PS0
Write: 0 TRST
Reset: 0 0 1 0 0 0 0 0
= Unimplemented
Figure 14-5. TIM Status and Control Register (TSC)

TOF — TIM Overflow Flag Bit
This read/write flag is set when the TIM counter reaches the modulo value
programmed in the TIM counter modulo registers. Clear TOF by reading the TIM
status and control register when TOF is set and then writing a 0 to TOF. If
another TIM overflow occurs before the clearing sequence is complete, then
writing 0 to TOF has no effect. Therefore, a TOF interrupt request cannot be lost
due to inadvertent clearing of TOF. Reset clears the TOF bit. Writing a 1 to TOF
has no effect.
1 = TIM counter has reached modulo value
0 = TIM counter has not reached modulo value
TOIE — TIM Overflow Interrupt Enable Bit
This read/write bit enables TIM overflow interrupts when the TOF bit becomes
set. Reset clears the TOIE bit.
1 = TIM overflow interrupts enabled
0 = TIM overflow interrupts disabled

TSTOP — TIM Stop Bit

This read/write bit stops the TIM counter. Counting resumes when TSTOP is
cleared. Reset sets the TSTOP bit, stopping the TIM counter until software
clears the TSTOP bit.
1 = TIM counter stopped
0 = TIM counter active
NOTE: Do not set the TSTOP bit before entering wait mode if the TIM is required to exit
wait mode.
TRST — TIM Reset Bit

Setting this write-only bit resets the TIM counter and the TIM prescaler. Setting
TRST has no effect on any other registers. Counting resumes from $0000.
TRST is cleared automatically after the TIM counter is reset and always reads
as 0. Reset clears the TRST bit.
1 = Prescaler and TIM counter cleared
0 = No effect
NOTE: Setting the TSTOP and TRST bits simultaneously stops the TIM counter at a value
of $0000.
PS[2:0] — Prescaler Select Bits
These read/write bits select either the PTA2/TCLK pin or one of the seven
prescaler outputs as the input to the TIM counter as Table 14-2 shows. Reset
clears the PS[2:0] bits.
Table 14-2. Prescaler Selection

PS2 PS1 PS0 TIM Clock Source
0 0 0 Internal bus clock ÷ 1
1 1 1 PTA2/TCLK

14.9.2 TIM Counter Registers

The two read-only TIM counter registers contain the high and low bytes of the value
in the TIM counter. Reading the high byte (TCNTH) latches the contents of the low
byte (TCNTL) into a buffer. Subsequent reads of TCNTH do not affect the latched
TCNTL value until TCNTL is read. Reset clears the TIM counter registers. Setting
the TIM reset bit (TRST) also clears the TIM counter registers.
NOTE: If you read TCNTH during a break interrupt, be sure to unlatch TCNTL by reading
TCNTL before exiting the break interrupt. Otherwise, TCNTL retains the value
latched during the break.
Address: $0021 TCNTH
Bit 7 6 5 4 3 2 1 Bit 0
Write:
Reset: 0 0 0 0 0 0 0 0
Address: $0022 TCNTL
Bit 7 6 5 4 3 2 1 Bit 0
Write:
Reset: 0 0 0 0 0 0 0 0
= Unimplemented
Figure 14-6. TIM Counter Registers (TCNTH:TCNTL)
14.9.3 TIM Counter Modulo Registers

The read/write TIM modulo registers contain the modulo value for the TIM counter.
When the TIM counter reaches the modulo value, the overflow flag (TOF) becomes
set, and the TIM counter resumes counting from $0000 at the next timer clock.
Writing to the high byte (TMODH) inhibits the TOF bit and overflow interrupts until
the low byte (TMODL) is written. Reset sets the TIM counter modulo registers.
Address: $0023 TMODH
Bit 7 6 5 4 3 2 1 Bit 0
Read:
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8
Write:
Reset: 1 1 1 1 1 1 1 1
Address: $0024 TMODL
Bit 7 6 5 4 3 2 1 Bit 0
Read:
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Write:
Reset: 1 1 1 1 1 1 1 1
Figure 14-7. TIM Counter Modulo Registers (TMODH:TMODL)

NOTE: Reset the TIM counter before writing to the TIM counter modulo registers.

14.9.4 TIM Channel Status and Control Registers
Each of the TIM channel status and control registers does the following:
• Flags input captures and output compares
• Enables input capture and output compare interrupts
• Selects input capture, output compare, or PWM operation
• Selects high, low, or toggling output on output compare
• Selects rising edge, falling edge, or any edge as the active input capture
trigger
• Selects output toggling on TIM overflow
• Selects 0% and 100% PWM duty cycle
• Selects buffered or unbuffered output compare/PWM operation
Address: $0025 TSC0

Bit 7 6 5 4 3 2 1 Bit 0
Read: CH0F
CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX
Write: 0
Reset: 0 0 0 0 0 0 0 0
Address: $0028 TSC1

Bit 7 6 5 4 3 2 1 Bit 0
Read: CH1F 0
CH1IE MS1A ELS1B ELS1A TOV1 CH1MAX
Write: 0
Reset: 0 0 0 0 0 0 0 0
= Unimplemented
Figure 14-8. TIM Channel Status and Control

Registers (TSC0:TSC1)
CHxF — Channel x Flag Bit

When channel x is an input capture channel, this read/write bit is set when an
active edge occurs on the channel x pin. When channel x is an output compare
channel, CHxF is set when the value in the TIM counter registers matches the
value in the TIM channel x registers.
Clear CHxF by reading the TIM channel x status and control register with CHxF
set and then writing a 0 to CHxF. If another interrupt request occurs before the
clearing sequence is complete, then writing 0 to CHxF has no effect. Therefore,
an interrupt request cannot be lost due to inadvertent clearing of CHxF.
Reset clears the CHxF bit. Writing a 1 to CHxF has no effect.
1 = Input capture or output compare on channel x
0 = No input capture or output compare on channel x

CHxIE — Channel x Interrupt Enable Bit

This read/write bit enables TIM CPU interrupt service requests on channel x.
Reset clears the CHxIE bit.
1 = Channel x CPU interrupt requests enabled
0 = Channel x CPU interrupt requests disabled
MSxB — Mode Select Bit B
This read/write bit selects buffered output compare/PWM operation. MSxB
exists only in the TIM channel 0 status and control register.
Setting MS0B disables the channel 1 status and control register and reverts
TCH1 to general-purpose I/O.
Reset clears the MSxB bit.
1 = Buffered output compare/PWM operation enabled
0 = Buffered output compare/PWM operation disabled
MSxA — Mode Select Bit A
When ELSxB:A ≠ 00, this read/write bit selects either input capture operation or
unbuffered output compare/PWM operation. See Table 14-3.
1 = Unbuffered output compare/PWM operation
0 = Input capture operation
When ELSxB:A = 00, this read/write bit selects the initial output level of the
TCHx pin (see Table 14-3). Reset clears the MSxA bit.
1 = Initial output level low
0 = Initial output level high
NOTE: Before changing a channel function by writing to the MSxB or MSxA bit, set the
TSTOP and TRST bits in the TIM status and control register (TSC).
Table 14-3. Mode, Edge, and Level Selection

MSxB MSxA ELSxB ELSxA Mode Configuration
Pin under port control; initial
X 0 0 0
output level high
Output preset
Pin under port control; initial
X 1 0 0
output level low
0 0 0 1 Capture on rising edge only
0 0 1 0 Input capture Capture on falling edge only
0 0 1 1 Capture on rising or falling edge
0 1 0 1 Toggle output on compare
Output compare
0 1 1 0 Clear output on compare
or PWM
0 1 1 1 Set output on compare
1 X 0 1 Toggle output on compare
Buffered output
1 X 1 0 compare or Clear output on compare
buffered PWM
1 X 1 1 Set output on compare

ELSxB and ELSxA — Edge/Level Select Bits

When channel x is an input capture channel, these read/write bits control the
active edge-sensing logic on channel x.
When channel x is an output compare channel, ELSxB and ELSxA control the
channel x output behavior when an output compare occurs.
When ELSxB and ELSxA are both clear, channel x is not connected to an I/O
port, and pin TCHx is available as a general-purpose I/O pin. Table 14-3 shows
how ELSxB and ELSxA work. Reset clears the ELSxB and ELSxA bits.
NOTE: After initially enabling a TIM channel register for input capture operation and
selecting the edge sensitivity, clear CHxF to ignore any erroneous edge detection
flags.
TOVx — Toggle-On-Overflow Bit

When channel x is an output compare channel, this read/write bit controls the
behavior of the channel x output when the TIM counter overflows. When
channel x is an input capture channel, TOVx has no effect. Reset clears the
TOVx bit.
1 = Channel x pin toggles on TIM counter overflow.
0 = Channel x pin does not toggle on TIM counter overflow.
NOTE: When TOVx is set, a TIM counter overflow takes precedence over a channel x
output compare if both occur at the same time.
CHxMAX — Channel x Maximum Duty Cycle Bit

When the TOVx bit is at a 1, setting the CHxMAX bit forces the duty cycle of
buffered and unbuffered PWM signals to 100%. As Figure 14-9 shows, the
CHxMAX bit takes effect in the cycle after it is set or cleared. The output stays
at the 100% duty cycle level until the cycle after CHxMAX is cleared.
OVERFLOW OVERFLOW OVERFLOW OVERFLOW OVERFLOW
PERIOD
TCHx
OUTPUT OUTPUT OUTPUT OUTPUT

COMPARE COMPARE COMPARE COMPARE
CHxMAX
Figure 14-9. CHxMAX Latency

14.9.5 TIM Channel Registers
These read/write registers contain the captured TIM counter value of the input
capture function or the output compare value of the output compare function. The
state of the TIM channel registers after reset is unknown.
In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the TIM
channel x registers (TCHxH) inhibits input captures until the low byte (TCHxL) is
read.
In output compare mode (MSxB:MSxA ≠ 0:0), writing to the high byte of the TIM
channel x registers (TCHxH) inhibits output compares until the low byte (TCHxL) is
written.
Address: $0026 TCH0H

Bit 7 6 5 4 3 2 1 Bit 0
Read:
Write:
Address: $0027 TCH0L
Bit 7 6 5 4 3 2 1 Bit 0
Read:
Write:
Address: $0029 TCH1H
Bit 7 6 5 4 3 2 1 Bit 0
Read:
Write:
Address: $002A TCH1L
Bit 7 6 5 4 3 2 1 Bit 0
Read:
Write:
Figure 14-10. TIM Channel Registers (TCH0H/L:TCH1H/L)


Section 15. Development Support
15.1 Introduction
This section describes the break module, the monitor read-only memory (MON),
and the monitor mode entry methods.
15.2 Break Module (BRK)

The break module can generate a break interrupt that stops normal program flow
at a defined address to enter a background program.
Features include:
• Accessible input/output (I/O) registers during the break Interrupt
• Central processor unit (CPU) generated break interrupts
• Software-generated break interrupts
• Computer operating properly (COP) disabling during break interrupts
15.2.1 Functional Description
When the internal address bus matches the value written in the break address
registers, the break module issues a breakpoint signal (BKPT) to the system
integration module (SIM). The SIM then causes the CPU to load the instruction
register with a software interrupt instruction (SWI). The program counter vectors to
$FFFC and $FFFD ($FEFC and $FEFD in monitor mode).
The following events can cause a break interrupt to occur:

• A CPU generated address (the address in the program counter) matches
the contents of the break address registers.
• Software writes a 1 to the BRKA bit in the break status and control register.
When a CPU generated address matches the contents of the break address
registers, the break interrupt is generated. A return-from-interrupt instruction (RTI)
in the break routine ends the break interrupt and returns the microcontroller unit
(MCU) to normal operation.
Figure 15-2 shows the structure of the break module.
Figure 15-3 provides a summary of the I/O registers.
MOTOROLA Development Support 149

Development Support
PTA0/AD0/TCH0/KBI0
CLOCK
DDRA
PTA
PTA3/RST/KBI3
MODULE
PTA5/OSC1/AD3/KBI5
M68HC08 CPU
SINGLE INTERRUPT
PTB0 MODULE
PTB1
PTB2
BREAK
DDRB
PTB3
PTB
PTB4 MODULE
PTB5
PTB6 POWER-ON RESET
PTB7 MODULE

USER FLASH MODULE
128 BYTES RAM
COP
MODULE
VDD
VSS

Figure 15-1. Block Diagram Highlighting BRK and MON Blocks
150 Development Support MOTOROLA

Development Support
Break Module (BRK)
ADDRESS BUS[15:8]
BREAK ADDRESS REGISTER HIGH
8-BIT COMPARATOR
ADDRESS BUS[15:0]
CONTROL BKPT
(TO SIM)
8-BIT COMPARATOR
BREAK ADDRESS REGISTER LOW
ADDRESS BUS[7:0]
Figure 15-2. Break Module Block Diagram

Read: SBSW
Break Status Register R R R R R R R
$FE00 (BSR) Write: Note(1)
See page 155.
Reset: 0
Read:
Break Auxiliary Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$FE02 (BRKAR) Write:
See page 154.
Reset: 0 0 0 0 0 0 0 0
Read:
Break Flag Control BCFE R R R R R R R
See page 155.
Reset: 0
Read:
Break Address High Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8
$FE09 Register (BRKH) Write:
See page 154.
Reset: 0 0 0 0 0 0 0 0
Read:
Break Address Low Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$FE0A Register (BRKL) Write:
See page 154.
Reset: 0 0 0 0 0 0 0 0
Read: 0 0 0 0 0 0
Break Status and Control BRKE BRKA
$FE0B Register (BRKSCR) Write:
See page 153.
Reset: 0 0 0 0 0 0 0 0
1. Writing a 0 clears SBSW. = Unimplemented R = Reserved
Figure 15-3. Break I/O Register Summary

Development Support
When the internal address bus matches the value written in the break address
registers or when software writes a 1 to the BRKA bit in the break status and control
register, the CPU starts a break interrupt by:
• Loading the instruction register with the SWI instruction
• Loading the program counter with $FFFC and $FFFD ($FEFC and $FEFD
in monitor mode)
The break interrupt timing is:

• When a break address is placed at the address of the instruction opcode,
the instruction is not executed until after completion of the break interrupt
routine.
• When a break address is placed at an address of an instruction operand, the
instruction is executed before the break interrupt.
• When software writes a 1 to the BRKA bit, the break interrupt occurs just
before the next instruction is executed.
By updating a break address and clearing the BRKA bit in a break interrupt routine,
a break interrupt can be generated continuously.
CAUTION: A break address should be placed at the address of the instruction opcode. When
software does not change the break address and clears the BRKA bit in the first
break interrupt routine, the next break interrupt will not be generated after exiting
the interrupt routine even when the internal address bus matches the value written
in the break address registers.
15.2.1.1 Flag Protection During Break Interrupts
The system integration module (SIM) controls whether or not module status bits
register (BFCR) enables software to clear status bits during the break state. See
13.8.2 Break Flag Control Register and the Break Interrupts subsection for
each module.
15.2.1.2 TIM During Break Interrupts
A break interrupt stops the timer counter.
15.2.1.3 COP During Break Interrupts
The COP is disabled during a break interrupt with monitor mode when BDCOP bit
is set in break auxiliary register (BRKAR).

Development Support
Break Module (BRK)
15.2.2 Break Module Registers
These registers control and monitor operation of the break module:

• Break status and control register (BRKSCR)
• Break address register high (BRKH)
• Break address register low (BRKL)
• Break status register (BSR)
• Break flag control register (BFCR)
15.2.2.1 Break Status and Control Register
The break status and control register (BRKSCR) contains break module enable
and status bits.
Address: $FE0B
Bit 7 6 5 4 3 2 1 Bit 0
Read: 0 0 0 0 0 0
BRKE BRKA
Write:
Reset: 0 0 0 0 0 0 0 0
= Unimplemented
Figure 15-4. Break Status and Control Register (BRKSCR)
BRKE — Break Enable Bit

This read/write bit enables breaks on break address register matches. Clear
BRKE by writing a 0 to bit 7. Reset clears the BRKE bit.
1 = Breaks enabled on 16-bit address match
0 = Breaks disabled
BRKA — Break Active Bit
This read/write status and control bit is set when a break address match occurs.
Writing a 1 to BRKA generates a break interrupt. Clear BRKA by writing a 0 to
it before exiting the break routine. Reset clears the BRKA bit.
1 = Break address match
0 = No break address match

Development Support
15.2.2.2 Break Address Registers
The break address registers (BRKH and BRKL) contain the high and low bytes of
the desired breakpoint address. Reset clears the break address registers.
Address: $FE09
Bit 7 6 5 4 3 2 1 Bit 0
Read:
Write:
Reset: 0 0 0 0 0 0 0 0
Figure 15-5. Break Address Register High (BRKH)
Address: $FE0A
Bit 7 6 5 4 3 2 1 Bit 0
Read:
Write:
Reset: 0 0 0 0 0 0 0 0
Figure 15-6. Break Address Register Low (BRKL)
15.2.2.3 Break Auxiliary Register
The break auxiliary register (BRKAR) contains a bit that enables software to
disable the COP while the MCU is in a state of break interrupt with monitor mode.
Address: $FE02
Bit 7 6 5 4 3 2 1 Bit 0
Read: 0 0 0 0 0 0 0
BDCOP
Write:
Reset: 0 0 0 0 0 0 0 0
= Unimplemented
Figure 15-7. Break Auxiliary Register (BRKAR)
BDCOP — Break Disable COP Bit

This read/write bit disables the COP during a break interrupt. Reset clears the
BDCOP bit.
1 = COP disabled during break interrupt
0 = COP enabled during break interrupt

Development Support
Break Module (BRK)
15.2.2.4 Break Status Register
The break status register (BSR) contains a flag to indicate that a break caused an
exit from wait mode. This register is only used in emulation mode.
Address: $FE00
Bit 7 6 5 4 3 2 1 Bit 0
Read: SBSW
R R R R R R R
Write: Note(1)
Reset: 0
R = Reserved 1. Writing a 0 clears SBSW.
Figure 15-8. Break Status Register (BSR)
SBSW — SIM Break Stop/Wait

SBSW can be read within the break state SWI routine. The user can modify the
return address on the stack by subtracting one from it.
1 = Wait mode was exited by break interrupt
0 = Wait mode was not exited by break interrupt
15.2.2.5 Break Flag Control Register
The break control register (BFCR) contains a bit that enables software to clear
status bits while the MCU is in a break state.
Address: $FE03
Bit 7 6 5 4 3 2 1 Bit 0
Read:
BCFE R R R R R R R
Write:
Reset: 0
R = Reserved
Figure 15-9. Break Flag Control Register (BFCR)
BCFE — Break Clear Flag Enable Bit

This read/write bit enables software to clear status bits by accessing status
registers while the MCU is in a break state. To clear status bits during the break
state, the BCFE bit must be set.
1 = Status bits clearable during break
0 = Status bits not clearable during break

Development Support
15.2.3 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power- consumption standby
modes. If enabled, the break module will remain enabled in wait and stop modes.
However, since the internal address bus does not increment in these modes, a
break interrupt will never be triggered.
15.3 Monitor Module (MON)

This subsection describes the monitor module (MON) and the monitor mode entry
methods. The monitor allows debugging and programming of the microcontroller
unit (MCU) through a single-wire interface with a host computer. Monitor mode
entry can be achieved without use of the higher test voltage, VTST, as long as
vector addresses $FFFE and $FFFF are blank, thus reducing the hardware
requirements for in-circuit programming.
Features include:
• Normal user-mode pin functionality on most pins
• One pin dedicated to serial communication between MCU and host
computer
• Standard non-return-to-zero (NRZ) communication with host computer
• Execution of code in random-access memory (RAM) or FLASH
• FLASH memory security feature(1)
• FLASH memory programming interface
• Use of external 9.8304 MHz crystal or clock to generate internal frequency
of 2.4576 MHz
• Simple internal oscillator mode of operation (no external clock or high
voltage)
• Monitor mode entry without high voltage, VTST, if reset vector is blank
($FFFE and $FFFF contain $FF)
• Standard monitor mode entry if high voltage is applied to IRQ
15.3.1 Functional Description
Figure 15-10 shows a simplified diagram of monitor mode entry.
The monitor module receives and executes commands from a host computer.
Figure 15-11, Figure 15-12, and Figure 15-13 show example circuits used to
enter monitor mode and communicate with a host computer via a standard RS-232
interface.


Development Support
Monitor Module (MON)
POR RESET
NO YES
IRQ = VTST?
CONDITIONS
PTA0 = 1, NO PTA0 = 1, NO
FROM Table 15-1
RESET VECTOR PTA1 = 1, AND
BLANK? PTA4 = 0?
YES YES
FORCED NORMAL NORMAL INVALID

MONITOR MODE USER MODE MONITOR MODE USER MODE
HOST SENDS
8 SECURITY BYTES
IS RESET YES
POR?
NO
ARE ALL
YES NO
SECURITY BYTES
CORRECT?
ENABLE FLASH DISABLE FLASH
MONITOR MODE ENTRY
DEBUGGING
AND FLASH EXECUTE
PROGRAMMING MONITOR CODE
(IF FLASH
IS ENABLED)
YES DOES RESET NO

OCCUR?
Figure 15-10. Simplified Monitor Mode Entry Flowchart

Development Support
Simple monitor commands can access any memory address. In monitor mode, the
MCU can execute code downloaded into RAM by a host computer while most MCU
pins retain normal operating mode functions. All communication between the host
computer and the MCU is through the PTA0 pin. A level-shifting and multiplexing
interface is required between PTA0 and the host computer. PTA0 is used in a
wired-OR configuration and requires a pullup resistor.
The monitor code has been updated from previous versions of the monitor code to
allow enabling the internal oscillator to generate the internal clock. This addition,
which is enabled when IRQ is held low out of reset, is intended to support serial
communication/programming at 9600 baud in monitor mode by using the internal
oscillator, and the internal oscillator user trim value OSCTRIM (FLASH location
$FFC0, if programmed) to generate the desired internal frequency (3.2 MHz).
Since this feature is enabled only when IRQ is held low out of reset, it cannot be
used when the reset vector is programmed (i.e., the value is not $FFFF) because
entry into monitor mode in this case requires VTST on IRQ. The IRQ pin must
remain low during this monitor session in order to maintain communication.
Table 15-1 shows the pin conditions for entering monitor mode. As specified in the
table, monitor mode may be entered after a power-on reset (POR) and will allow
communication at 9600 baud provided one of the following sets of conditions is
met:
• If $FFFE and $FFFF do not contain $FF (programmed state):
– The external clock is 9.8304 MHz
– IRQ = VTST
• If $FFFE and $FFFF contain $FF (erased state):
– The external clock is 9.8304 MHz
– IRQ = VDD (this can be implemented through the internal IRQ pullup)
• If $FFFE and $FFFF contain $FF (erased state):
– IRQ = VSS (internal oscillator is selected, no external clock required)
The rising edge of the internal RST signal latches the monitor mode. Once monitor
mode is latched, the values on PTA1 and PTA4 pins can be changed.
Once out of reset, the MCU waits for the host to send eight security bytes
(see 15.3.2 Security). After the security bytes, the MCU sends a break signal
(10 consecutive logic 0s) to the host, indicating that it is ready to receive a
command.

Development Support
VDD VDD
10 kΩ* VDD
RST (PTA3) 0.1 µF

MAX232 9.8304 MHz CLOCK
VDD OSC1 (PTA5)
1 16
C1+
+ VTST
+ VDD
1 µF 1 µF
3 15 1 µF
C1–
+ 1 kΩ 10 kΩ*
4 PTA1
C2+ V+ 2 IRQ (PTA2)
+ VDD
1 µF
V– 6
5 C2– 9.1 V
1 µF
+ 10 kΩ 10 kΩ*
DB9 74HC125 PTA4
2 7 10 6 5
PTA0
74HC125
3 8 9 2 3 4
VSS
1
5
* Value not critical
Figure 15-11. Monitor Mode Circuit (External Clock, with High Voltage)
VDD
N.C. RST (PTA3) VDD
0.1 µF
MAX232 VDD
1 16 9.8304 MHz CLOCK

C1+
+ + OSC1 (PTA5)
1 µF 1 µF
3 15 1 µF
C1–
+
10 kΩ* PTA1 N.C.
4
C2+ V+ 2
+ VDD IRQ (PTA2)
1 µF
V– 6 PTA4 N.C.
5 C2–
1 µF
+ 10 kΩ
DB9 74HC125
2 7 10 6 5
74HC125 PTA0
3 8 9 2 3 4 VSS
1
5
Figure 15-12. Monitor Mode Circuit (External Clock, No High Voltage)

Development Support
VDD
N.C. RST (PTA3)

VDD
0.1 µF
MAX232 VDD N.C. OSC1 (PTA5)

1 16
C1+
+ +
1 µF 1 µF
3 IRQ (PTA2) PTA1 N.C.
C1– 15 1 µF
+
10 kΩ*
4
C2+ V+ 2 PTA4 N.C.
+ VDD
1 µF
V– 6
5 C2–
1 µF
+ 10 kΩ
DB9 74HC125
2 7 10 6 5
PTA0 VSS
74HC125
3 8 9 2 3 4
5 1
Figure 15-13. Monitor Mode Circuit (Internal Clock, No High Voltage)
15.3.1.1 Normal Monitor Mode

RST and OSC1 functions will be active on the PTA3 and PTA5 pins respectively
as long as VTST is applied to the IRQ pin. If the IRQ pin is lowered (no longer VTST)
then the chip will still be operating in monitor mode, but the pin functions will be
determined by the settings in the configuration registers (see Section 5.
Configuration Register (CONFIG)) when VTST was lowered. With VTST lowered,
the BIH and BIL instructions will read the IRQ pin state only if IRQEN is set in the
CONFIG2 register.
If monitor mode was entered with VTST on IRQ, then the COP is disabled as long
as VTST is applied to IRQ.

MOTOROLA
MC68HC908QY/QT Family — Rev. 1
Table 15-1. Monitor Mode Signal Requirements and Options

Serial Mode Communication
IRQ RST Reset Communication Selection Speed
Mode COP Comments
(PTA2) (PTA3) Vector External Bus Baud
PTA0 PTA1 PTA4
Clock Frequency Rate
Normal 9.8304 2.4576
VTST VDD X 1 1 0 Disabled 9600 Provide external clock at OSC1.
Monitor MHz MHz
$FFFF 9.8304 2.4576
VDD X 1 X X Disabled 9600 Provide external clock at OSC1.
Forced (blank) MHz MHz
Monitor $FFFF 3.2 MHz
VSS X 1 X X Disabled X 9600 Internal clock is active.
(blank) (Trimmed)
Not
User X X X X X Enabled X X X
$FFFF
Development Support
MON08
VTST RST COM MOD0 MOD1 OSC1
Function — — — —
[6] [4] [8] [12] [10] [13]
[Pin No.]
1. PTA0 must have a pullup resistor to VDD in monitor mode.
2. Communication speed in the table is an example to obtain a baud rate of 9600. Baud rate using external oscillator is bus frequency / 256 and baud
rate using internal oscillator is bus frequency / 335.
3. External clock is a 9.8304 MHz oscillator on OSC1.
4. X = don’t care
5. MON08 pin refers to P&E Microcomputer Systems’ MON08-Cyclone 2 by 8-pin connector.
NC 1 2 GND
NC 3 4 RST
NC 5 6 IRQ
NC 7 8 PTA0

NC 9 10 PTA4
Development Support
NC 11 12 PTA1
OSC1 13 14 NC
VDD 15 16 NC
Data Sheet
161
Development Support
15.3.1.2 Forced Monitor Mode
If entering monitor mode without high voltage on IRQ, then startup port pin
requirements and conditions, (PTA1/PTA4) are not in effect. This is to reduce
circuit requirements when performing in-circuit programming.
NOTE: If the reset vector is blank and monitor mode is entered, the chip will see an
additional reset cycle after the initial power-on reset (POR). Once the reset vector
has been programmed, the traditional method of applying a voltage, VTST, to IRQ
must be used to enter monitor mode.
If monitor mode was entered as a result of the reset vector being blank, the COP
is always disabled regardless of the state of IRQ.
If the voltage applied to the IRQ is less than VTST, the MCU will come out of reset
in user mode. Internal circuitry monitors the reset vector fetches and will assert an
internal reset if it detects that the reset vectors are erased ($FF). When the MCU
comes out of reset, it is forced into monitor mode without requiring high voltage on
the IRQ pin. Once out of reset, the monitor code is initially executing with the
internal clock at its default frequency.
If IRQ is held high, all pins will default to regular input port functions except for
PTA0 and PTA5 which will operate as a serial communication port and OSC1 input
respectively (refer to Figure 15-11). That will allow the clock to be driven from an
external source through OSC1 pin.
If IRQ is held low, all pins will default to regular input port function except for PTA0
which will operate as serial communication port. Refer to Figure 15-12.
Regardless of the state of the IRQ pin, it will not function as a port input pin in
monitor mode. Bit 2 of the Port A data register will always read 0. The BIH and BIL
instructions will behave as if the IRQ pin is enabled, regardless of the settings in
the configuration register. See Section 5. Configuration Register (CONFIG).
The COP module is disabled in forced monitor mode. Any reset other than a
power-on reset (POR) will automatically force the MCU to come back to the forced
monitor mode.
15.3.1.3 Monitor Vectors
In monitor mode, the MCU uses different vectors for reset, SWI (software interrupt),
and break interrupt than those for user mode. The alternate vectors are in the $FE
page instead of the $FF page and allow code execution from the internal monitor
firmware instead of user code.
NOTE: Exiting monitor mode after it has been initiated by having a blank reset vector
requires a power-on reset (POR). Pulling RST (when RST pin available) low will
not exit monitor mode in this situation.

Development Support
Table 15-2 summarizes the differences between user mode and monitor mode
regarding vectors.
Table 15-2. Mode Difference

Functions
Modes Reset Reset Break Break SWI SWI
Vector High Vector Low Vector High Vector Low Vector High Vector Low
User $FFFE $FFFF $FFFC $FFFD $FFFC $FFFD
Monitor $FEFE $FEFF $FEFC $FEFD $FEFC $FEFD
15.3.1.4 Data Format
Communication with the monitor ROM is in standard non-return-to-zero (NRZ)

mark/space data format. Transmit and receive baud rates must be identical.
NEXT
START START
BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 STOP BIT
BIT
Figure 15-14. Monitor Data Format
15.3.1.5 Break Signal
A start bit (logic 0) followed by nine logic 0 bits is a break signal. When the monitor
receives a break signal, it drives the PTA0 pin high for the duration of two bits and
then echoes back the break signal.
MISSING STOP BIT

2-STOP BIT DELAY BEFORE ZERO ECHO
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
Figure 15-15. Break Transaction
15.3.1.6 Baud Rate
The monitor communication baud rate is controlled by the frequency of the external
or internal oscillator and the state of the appropriate pins as shown in Table 15-1.
Table 15-1 also lists the bus frequencies to achieve standard baud rates. The
effective baud rate is the bus frequency divided by 256 when using an external
oscillator. When using the internal oscillator in forced monitor mode, the effective
baud rate is the bus frequency divided by 335.

Development Support
15.3.1.7 Commands
The monitor ROM firmware uses these commands:

• READ (read memory)
• WRITE (write memory)
• IREAD (indexed read)
• IWRITE (indexed write)
• READSP (read stack pointer)
• RUN (run user program)
The monitor ROM firmware echoes each received byte back to the PTA0 pin for
error checking. An 11-bit delay at the end of each command allows the host to send
a break character to cancel the command. A delay of two bit times occurs before
each echo and before READ, IREAD, or READSP data is returned. The data
returned by a read command appears after the echo of the last byte of the
command.
NOTE: Wait one bit time after each echo before sending the next byte.
FROM
HOST
ADDRESS ADDRESS ADDRESS ADDRESS

READ READ HIGH HIGH LOW LOW DATA
4 1 4 1 4 1 3, 2 4
ECHO RETURN
Notes:
1 = Echo delay, 2 bit times 3 = Cancel command delay, 11 bit times
2 = Data return delay, 2 bit times 4 = Wait 1 bit time before sending next byte.
Figure 15-16. Read Transaction
FROM
HOST

WRITE WRITE DATA DATA
HIGH HIGH LOW LOW
3 1 3 1 3 1 3 1 2, 3
ECHO
Notes:
1 = Echo delay, 2 bit times
2 = Cancel command delay, 11 bit times
3 = Wait 1 bit time before sending next byte.
Figure 15-17. Write Transaction
A brief description of each monitor mode command is given in Table 15-3 through
Table 15-8.

Development Support
Table 15-3. READ (Read Memory) Command

Description Read byte from memory
Operand 2-byte address in high-byte:low-byte order
Data Returned Returns contents of specified address
Opcode $4A
Command Sequence
SENT TO MONITOR

READ READ HIGH HIGH LOW LOW DATA
ECHO RETURN
Table 15-4. WRITE (Write Memory) Command

Description Write byte to memory
2-byte address in high-byte:low-byte order; low byte followed by data
Operand
byte
Data Returned None
Opcode $49
Command Sequence
FROM HOST
ADDRESS ADDRESS ADDRESS ADDRESS DATA DATA

WRITE WRITE HIGH HIGH LOW LOW
ECHO
Table 15-5. IREAD (Indexed Read) Command

Description Read next 2 bytes in memory from last address accessed
Operand 2-byte address in high byte:low byte order
Data Returned Returns contents of next two addresses
Opcode $1A
Command Sequence
FROM HOST
IREAD IREAD DATA DATA
ECHO RETURN

Development Support
Table 15-6. IWRITE (Indexed Write) Command

Description Write to last address accessed + 1
Operand Single data byte
Data Returned None
Opcode $19
Command Sequence
FROM HOST
IWRITE IWRITE DATA DATA
ECHO
A sequence of IREAD or IWRITE commands can access a block of memory

sequentially over the full 64-Kbyte memory map.
Table 15-7. READSP (Read Stack Pointer) Command

Description Reads stack pointer
Operand None
Returns incremented stack pointer value (SP + 1) in
Data Returned
high-byte:low-byte order
Opcode $0C
Command Sequence
FROM HOST
SP SP
READSP READSP HIGH LOW
ECHO RETURN
Table 15-8. RUN (Run User Program) Command

Description Executes PULH and RTI instructions
Operand None
Data Returned None
Opcode $28
Command Sequence
FROM HOST
RUN RUN
ECHO

Development Support
The MCU executes the SWI and PSHH instructions when it enters monitor mode.
The RUN command tells the MCU to execute the PULH and RTI instructions.
Before sending the RUN command, the host can modify the stacked CPU registers
to prepare to run the host program. The READSP command returns the
incremented stack pointer value, SP + 1. The high and low bytes of the program
counter are at addresses SP + 5 and SP + 6.
SP
HIGH BYTE OF INDEX REGISTER SP + 1
CONDITION CODE REGISTER SP + 2
ACCUMULATOR SP + 3
LOW BYTE OF INDEX REGISTER SP + 4
HIGH BYTE OF PROGRAM COUNTER SP + 5
LOW BYTE OF PROGRAM COUNTER SP + 6
SP + 7
Figure 15-18. Stack Pointer at Monitor Mode Entry
15.3.2 Security
A security feature discourages unauthorized reading of FLASH locations while in

monitor mode. The host can bypass the security feature at monitor mode entry by
sending eight security bytes that match the bytes at locations $FFF6–$FFFD.
Locations $FFF6–$FFFD contain user-defined data.
NOTE: Do not leave locations $FFF6–$FFFD blank. For security reasons, program
locations $FFF6–$FFFD even if they are not used for vectors.
During monitor mode entry, the MCU waits after the power-on reset for the host to
send the eight security bytes on pin PTA0. If the received bytes match those at
locations $FFF6–$FFFD, the host bypasses the security feature and can read all
FLASH locations and execute code from FLASH. Security remains bypassed until
a power-on reset occurs. If the reset was not a power-on reset, security remains
bypassed and security code entry is not required. See Figure 15-19.
Upon power-on reset, if the received bytes of the security code do not match the
data at locations $FFF6–$FFFD, the host fails to bypass the security feature. The
MCU remains in monitor mode, but reading a FLASH location returns an invalid
value and trying to execute code from FLASH causes an illegal address reset. After
receiving the eight security bytes from the host, the MCU transmits a break
character, signifying that it is ready to receive a command.
NOTE: The MCU does not transmit a break character until after the host sends the eight
security bytes.

Development Support
VDD
4096 + 32 CGMXCLK CYCLES
RST
COMMAND
BYTE 1
BYTE 2
BYTE 8
FROM HOST
PA0
256 BUS CYCLES 1

1 4 1 2 4 1
(MINIMUM)
FROM MCU
BYTE 1 ECHO
BYTE 2 ECHO
BYTE 8 ECHO
BREAK
COMMAND ECHO
Notes:
1 = Echo delay, 2 bit times
2 = Data return delay, 2 bit times
4 = Wait 1 bit time before sending next byte.
Figure 15-19. Monitor Mode Entry Timing
To determine whether the security code entered is correct, check to see if bit 6 of
RAM address $80 is set. If it is, then the correct security code has been entered
and FLASH can be accessed.
If the security sequence fails, the device should be reset by a power-on reset and
brought up in monitor mode to attempt another entry. After failing the security
sequence, the FLASH module can also be mass erased by executing an erase
routine that was downloaded into internal RAM. The mass erase operation clears
the security code locations so that all eight security bytes become $FF (blank).

Section 16. Electrical Specifications
16.1 Introduction
This section contains electrical and timing specifications.
16.2 Absolute Maximum Ratings

Maximum ratings are the extreme limits to which the microcontroller unit (MCU)
can be exposed without permanently damaging it.
NOTE: This device is not guaranteed to operate properly at the maximum ratings. Refer to
16.5 5-V DC Electrical Characteristics and 16.9 3-V DC Electrical
Characteristics for guaranteed operating conditions.
Characteristic(1) Symbol Value Unit
Supply voltage VDD –0.3 to +6.0 V
Input voltage VIN VSS –0.3 to VDD +0.3 V
Mode entry voltage, IRQ pin VTST VSS –0.3 to +9.1 V

Maximum current per pin excluding
I ±15 mA
PTA0–PTA5, VDD, and VSS
Maximum current for pins PTA0–PTA5 IPTA0—IPTA5 ±25 mA
Storage temperature TSTG –55 to +150 °C

Maximum current out of VSS IMVSS 100 mA
Maximum current into VDD IMVDD 100 mA
1. Voltages references to VSS.
NOTE: This device contains circuitry to protect the inputs against damage due to high
static voltages or electric fields; however, it is advised that normal precautions be
taken to avoid application of any voltage higher than maximum-rated voltages to
this high-impedance circuit. For proper operation, it is recommended that VIN and
VOUT be constrained to the range VSS ≤ (VIN or VOUT) ≤ VDD. Reliability of
operation is enhanced if unused inputs are connected to an appropriate logic
voltage level (for example, either VSS or VDD.)
MOTOROLA Electrical Specifications 169

Electrical Specifications
16.3 Functional Operating Range
Temp.
Characteristic Symbol Value Unit
Code
– 40 to +125 M
Operating temperature range TA – 40 to +105 °C V
– 40 to +85 C
Operating voltage range VDD 2.7 to 5.5 V —
16.4 Thermal Characteristics
Characteristic Symbol Value Unit

Thermal resistance
8-pin PDIP 105
8-pin SOIC 142
8-pin DFN θJA 173 °C/W
16-pin PDIP 76
16-pin SOIC 90
16-pin TSSOP 133
I/O pin power dissipation PI/O User determined W
PD = (IDD x VDD)
Power dissipation(1) PD
+ PI/O = K/(TJ + 273°C)
W
PD x (TA + 273°C)
Constant(2) K W/°C
+ PD2 x θJA
Average junction temperature TJ TA + (PD x θJA) °C
Maximum junction temperature TJM 150 °C
1. Power dissipation is a function of temperature.

2. K constant unique to the device. K can be determined for a known TA and measured PD. With
this value of K, PD and TJ can be determined for any value of TA.
170 Electrical Specifications MOTOROLA

5-V DC Electrical Characteristics
16.5 5-V DC Electrical Characteristics
Characteristic(1) Symbol Min Typ(2) Max Unit

Output high voltage
ILoad = –2.0 mA, all I/O pins VDD –0.4 — —
VOH V
ILoad = –15.0 mA, PTA0, PTA1, PTA3–PTA5 only VDD –0.8 — —
Maximum combined IOH (all I/O pins) IOHT — — 50 mA

Output low voltage
ILoad = 1.6 mA, all I/O pins — — 0.4
VOL V
ILoad = 15.0 mA, PTA0, PTA1, PTA3–PTA5 only — — 0.8
Maximum combined IOL (all I/O pins) IOLT — — 50 mA

Input high voltage
VIH 0.7 x VDD — VDD V
PTA0–PTA5, PTB0–PTB7
Input low voltage
VIL VSS — 0.3 x VDD V
Input hysteresis VHYS 0.06 x VDD — — V
DC injection current, all ports IINJ –2 — +2 mA
Total dc current injection (sum of all I/O) IINJTOT –25 — +25 mA
Ports Hi-Z leakage current IIL –1 ±0.1 +1 µA
Capacitance
Ports (as input) CIN — — 12
pF
Ports (as input) COUT — — 8
POR rearm voltage(3) VPOR 0 — 100 mV
POR rise time ramp rate(4) RPOR 0.035 — — V/ms
Monitor mode entry voltage VTST VDD + 2.5 — 9.1 V
Pullup resistors(5) RPU 16 26 36 kΩ

Low-voltage inhibit reset, trip falling voltage VTRIPF 3.90 4.20 4.50 V
Low-voltage inhibit reset, trip rising voltage VTRIPR 4.00 4.30 4.60 V
Low-voltage inhibit reset/recover hysteresis VHYS — 100 — mV
1. VDD = 4.5 to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted.
2. Typical values reflect average measurements at midpoint of voltage range, 25°C only.
3. Maximum is highest voltage that POR is guaranteed.
4. If minimum VDD is not reached before the internal POR reset is released, the LVI will hold the part in reset until minimum
VDD is reached.
5. RPU is measured at VDD = 5.0 V.

16.6 Typical 5-V Output Drive Characteristics
2.0
1.5
VDD-VOH (V)
5V PTA
1.0
5V PTB
0.5
0.0
0 -5 -10 -15 -20 -25 -30 -35
IOH (mA)
Figure 16-1. Typical 5-Volt Output High Voltage

versus Output High Current (25°C)
2.0
1.5
VOL (V)
5V PTA
1.0
5V PTB
0.5
0.0
0 5 10 15 20 25 30 35
IOL (mA)
Figure 16-2. Typical 5-Volt Output Low Voltage

versus Output Low Current (25°C)

5-V Control Timing
16.7 5-V Control Timing
Characteristic(1) Symbol Min Max Unit

Internal operating frequency fOP (fBus) — 8 MHz
Internal clock period (1/fOP) tcyc 125 — ns
RST input pulse width low tRL 100 — ns
IRQ interrupt pulse width low (edge-triggered) tILIH 100 — ns
IRQ interrupt pulse period tILIL (2) — tcyc
Note
1. VDD = 4.5 to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH; timing shown with respect to 20% VDD and 70% VSS, unless otherwise
noted.
2. The minimum period is the number of cycles it takes to execute the interrupt service routine plus 1 tcyc.
tRL
RST
tILIL
tILIH
IRQ
Figure 16-3. RST and IRQ Timing

16.8 5-V Oscillator Characteristics

Characteristic Symbol Min Typ Max Unit
Internal oscillator frequency(1) fINTCLK — 12.8 — MHz
Crystal frequency, XTALCLK(1) fOSCXCLK 1 — 24 MHz
External RC oscillator frequency, RCCLK(1) fRCCLK 2 — 12 MHz

(1) (2) fOSCXCLK dc — 32 MHz
External clock reference frequency
Crystal load capacitance(3) CL — 20 — pF
Crystal fixed capacitance(3) C1 — 2 x CL — —

(3) C2 — 2 x CL — —
Crystal tuning capacitance
Feedback bias resistor RB 1 10 — MΩ
RC oscillator external resistor REXT See Figure 16-4 —
Crystal series damping resistor
fOSCXCLK = 1 MHz — 20 —
RS kΩ
fOSCXCLK = > 8 MHz — 0 —
1. Bus frequency, fOP, is oscillator frequency divided by 4.

2. No more than 10% duty cycle deviation from 50%.
3. Consult crystal vendor data sheet.
14
5 V 25°C
12
10
RC FREQUENCY, f RCCLK (MHz)
0
0 10 20 30 40 50 60
R EXT (k Ω)
Figure 16-4. RC versus Frequency (5 Volts @ 25°C)

3-V DC Electrical Characteristics
16.9 3-V DC Electrical Characteristics
Characteristic(1) Symbol Min Typ(2) Max Unit

Output high voltage
VOH V
ILoad = –10.0 mA, PTA0, PTA1, PTA3–PTA5 only VDD –0.8 — —
Maximum combined IOH (all I/O pins) IOHT — — 50 mA

Output low voltage
VOL V
ILoad = 10.0 mA, PTA0, PTA1, PTA3–PTA5 only — — 0.8
Maximum combined IOL (all I/O pins) IOLT — — 50 mA

Input high voltage
VIH 0.7 x VDD — VDD V
Input low voltage
VIL VSS — 0.3 x VDD V
Input hysteresis VHYS 0.06 x VDD — — V
DC injection current, all ports IINJ –2 — +2 mA
Total dc current injection (sum of all I/O) IINJTOT –25 — +25 mA
Ports Hi-Z leakage current IIL –1 ±0.1 +1 µA
Capacitance
Ports (as input) CIN — — 12
pF
Ports (as input) COUT — — 8
POR rearm voltage(3) VPOR 0 — 100 mV
POR rise time ramp rate(4) RPOR 0.035 — — V/ms
Monitor mode entry voltage VTST VDD + 2.5 — VDD + 4.0 V
Pullup resistors(5) RPU 16 26 36 kΩ

Low-voltage inhibit reset, trip falling voltage VTRIPF 2.40 2.55 2.70 V
Low-voltage inhibit reset, trip rising voltage VTRIPR 2.50 2.65 2.80 V
Low-voltage inhibit reset/recover hysteresis VHYS — 60 — mV
1. VDD = 2.7 to 3.3 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted.
2. Typical values reflect average measurements at midpoint of voltage range, 25°C only.
3. Maximum is highest voltage that POR is guaranteed.
4. If minimum VDD is not reached before the internal POR reset is released, the LVI will hold the part in reset until minimum
VDD is reached.
5. RPU is measured at VDD = 3.0 V

16.10 Typical 3.0-V Output Drive Characteristics
1.5
1.0
VDD-VOH (V)
3V PTA
3V PTB
0.5
0.0
0 -5 -10 -15 -20
IOH (mA)
Figure 16-5. Typical 3-Volt Output High Voltage

versus Output High Current (25°C)
1.5
1.0
VOL (V)
3V PTA
3V PTB
0.5
0.0
0 5 10 15 20
IOL (mA)
Figure 16-6. Typical 3-Volt Output Low Voltage

versus Output Low Current (25°C)

3-V Control Timing
16.11 3-V Control Timing

Characteristic(1) Symbol Min Max Unit
Internal operating frequency fOP (fBus) — 4 MHz
Internal clock period (1/fOP) tcyc 250 — ns
RST input pulse width low tRL 200 — ns
IRQ interrupt pulse width low (edge-triggered) tILIH 200 — ns
IRQ interrupt pulse period tILIL (2) — tcyc
Note
1. VDD = 2.7 to 3.3 Vdc, VSS = 0 Vdc, TA = TL to TH; timing shown with respect to 20% VDD and 70% VDD, unless otherwise
noted.
tRL
RST
tILIL
tILIH
IRQ
Figure 16-7. RST and IRQ Timing

16.12 3-V Oscillator Characteristics

Internal oscillator frequency(1) fINTCLK — 12.8 — MHz
Crystal frequency, XTALCLK(1) fOSCXCLK 1 — 16 MHz
External RC oscillator frequency, RCCLK (1) fRCCLK 2 — 12 MHz

(1) (2) fOSCXCLK dc — 16 MHz
External clock reference frequency
Crystal load capacitance(3) CL — 20 — pF
Crystal fixed capacitance(3) C1 — 2 x CL — —

(3) C2 — 2 x CL — —
Crystal tuning capacitance
Feedback bias resistor RB 1 10 — MΩ
RC oscillator external resistor REXT See Figure 16-8 —
Crystal series damping resistor
RS kΩ
fOSCXCLK = > 8 MHz — 0 —
1. Bus frequency, fOP, is oscillator frequency divided by 4.

2. No more than 10% duty cycle deviation from 50%
3. Consult crystal vendor data sheet
12
3 V 25°C
10
RCCLK (MHz)
8
RC FREQUENCY, f
0
0 10 20 30 40 50 60
R EXT (k Ω)
Figure 16-8. RC versus Frequency (3 Volts @ 25°C)

Supply Current Characteristics
16.13 Supply Current Characteristics
Bus
Characteristic(1) Voltage Frequency Symbol Typ(2) Max Unit
(MHz)
5.0 3.2 6.0 7.0
Run Mode VDD supply current(3) RIDD mA
3.0 3.2 2.5 3.2
5.0 3.2 1.0 1.5 mA
Wait Mode VDD supply current(4) WIDD
3.0 3.2 0.67 1.0 mA
Stop Mode VDD supply current(5)

–40 to 85°C 0.04 1.0
–40 to 105°C — 2.0
5.0 SIDD µA
–40 to 125°C — 5.0
25°C with auto wakeup enabled 7 —
Incremental current with LVI enabled at 25°C 125 —
Stop Mode VDD supply current(5)

–40 to 85°C 0.02 0.5
–40 to 105°C — 1.0
3.0 SIDD µA
–40 to 125°C — 4.0
25°C with auto wakeup enabled 5 —
Incremental current with LVI enabled at 25°C 100 —
1. VSS = 0 Vdc, TA = TL to TH, unless otherwise noted.

2. Typical values reflect average measurements at 25°C only.
3. Run (operating) IDD measured using trimmed internal oscillator, ADC off, all other modules enabled. All pins configured as
inputs and tied to 0.2 V from rail.
4. Wait IDD measured using trimmed internal oscillator, ADC off, all other modules enabled. All pins configured as inputs and
tied to 0.2 V from rail.
5. Stop IDD measured with all pins tied to 0.2 V or less from rail. No dc loads. On the 8-pin versions, port B is configured as
inputs with pullups enabled.

14
12
10
Crystal w/o ADC

8
IDD (mA)
Crystal w/ ADC
6
Internal Osc w/o
4 ADC
Internal Osc w/
2 ADC
0
0 1 2 3 4 5 6 7
Bus Frequency (MHz)
Figure 16-9. Typical 5-Volt Run Current

versus Bus Frequency (25°C)
Crystal w/o ADC

IDD (mA)
2 Crystal w/ ADC
Internal Osc w/o

ADC
1
Internal Osc w/
ADC
0
0 1 2 3 4 5
Bus Frequency (MHz)
Figure 16-10. Typical 3-Volt Run Current

versus Bus Frequency (25°C)

Analog-to-Digital Converter Characteristics
16.14 Analog-to-Digital Converter Characteristics

Characteristic Symbol Min Max Unit Comments
2.7 5.5
Supply voltage VDDAD V —
(VDD min) (VDD max)
Input voltages VADIN VSS VDD V —

Resolution
RES 10.5 21.5 mV —
(1 LSB)
Absolute accuracy
ETUE — ± 1.5 LSB Includes quantization
(Total unadjusted error)
tADIC = 1/fADIC,
ADC internal clock fADIC 0.5 1.048 MHz
tested only at 1 MHz
Conversion range VAIN VSS VDD V —
Power-up time tADPU 16 — tADIC cycles tADIC = 1/fADIC
Conversion time tADC 16 17 tADIC cycles tADIC = 1/fADIC
Sample time(1) tADS 5 — tADIC cycles tADIC = 1/fADIC
Zero input reading(2) ZADI 00 01 Hex VIN = VSS
Full-scale reading(3) FADI FE FF Hex VIN = VDD
Input capacitance CADI — 8 pF Not tested
Input leakage(3) IIL — ±1 µA —
ADC supply current

VDD = 3 V IADAD Typical = 0.45 mA Enabled
VDD = 5 V Typical = 0.65 mA Enabled
1. Source impedances greater than 10 kΩ adversely affect internal RC charging time during input sampling.
2. Zero-input/full-scale reading requires sufficient decoupling measures for accurate conversions.
3. The external system error caused by input leakage current is approximately equal to the product of R source and input
current.

16.15 Timer Interface Module Characteristics

Characteristic Symbol Min Max Unit
Timer input capture pulse width tTH, tTL 2 — tcyc
Timer input capture period tTLTL Note(1) — tcyc
Timer input clock pulse width tTCL, tTCH tcyc + 5 — ns
tTLTL
tTH
INPUT CAPTURE
RISING EDGE
tTLTL
tTL
INPUT CAPTURE
FALLING EDGE
tTLTL
tTH tTL
INPUT CAPTURE
BOTH EDGES
tTCH
TCLK
tTCL
Figure 16-11. Timer Input Timing

Memory Characteristics
16.16 Memory Characteristics

RAM data retention voltage VRDR 1.3 — — V
FLASH program bus clock frequency — 1 — — MHz
FLASH read bus clock frequency fRead(1) 0 — 8M Hz
FLASH page erase time

<1 k cycles tErase 0.9 1 1.1 ms
>1 k cycles 3.6 4 5.5
FLASH mass erase time tMErase 4 — — ms
FLASH PGM/ERASE to HVEN setup time tNVS 10 — — µs
FLASH high-voltage hold time tNVH 5 — — µs
FLASH high-voltage hold time (mass erase) tNVHL 100 — — µs
FLASH program hold time tPGS 5 — — µs
FLASH program time tPROG 30 — 40 µs
FLASH return to read time tRCV(2) 1 — — µs
FLASH cumulative program hv period tHV(3) — — 4 ms
FLASH endurance(4) — 10 k 100 k — Cycles
FLASH data retention time(5) — 15 100 — Years
1. fRead is defined as the frequency range for which the FLASH memory can be read.
2. tRCV is defined as the time it needs before the FLASH can be read after turning off the high voltage charge pump, by
clearing HVEN to 0.
3. tHV is defined as the cumulative high voltage programming time to the same row before next erase.
tHV must satisfy this condition: tNVS + tNVH + tPGS + (tPROG x 32) ≤ tHV maximum.
4. Typical endurance was evaluated for this product family. For additional information on how Motorola defines Typical
Endurance, please refer to Engineering Bulletin EB619.
5. Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated
to 25°C using the Arrhenius equation. For additional information on how Motorola defines Typical Data Retention, please
refer to Engineering Bulletin EB618.


Section 17. Ordering Information and Mechanical Specifications
17.1 Introduction
This section contains order numbers for the MC68HC908QY1, MC68HC908QY2,
MC68HC908QY4, MC68HC908QT1, MC68HC908QT2, and MC69HC908QT4.
Dimensions are given for:
• 8-pin plastic dual in-line package (PDIP)
• 8-pin small outline integrated circuit (SOIC) package
• 8-pin dual flat no lead (DFN) package
• 16-pin PDIP
• 16-pin SOIC
• 16-pin thin shrink small outline package (TSSOP)
17.2 MC Order Numbers
Table 17-1. MC Order Numbers

MC Order Number ADC FLASH Memory Package
MC68HC908QY1 — 1536 bytes 16-pins
MC68HC908QY2 Yes 1536 bytes PDIP, SOIC,
MC68HC908QY4 Yes 4096 bytes and TSSOP
MC68HC908QT1 — 1536 bytes 8-pins

MC68HC908QT2 Yes 1536 bytes PDIP, SOIC,
MC68HC908QT4 Yes 4096 bytes and DFN
Temperature and package designators:

C = –40°C to +85°C
V = –40°C to +105°C (available for VDD = 5 V only)
M = –40°C to +125°C (available for VDD = 5 V only)
P = Plastic dual in-line package (PDIP)
DW = Small outline integrated circuit package (SOIC)
DT = Thin shrink small outline package (TSSOP)
FQ = Dual flat no lead (DFN)
MC68HC908QY1XXX
FAMILY PACKAGE DESIGNATOR
TEMPERATURE RANGE
Figure 17-1. Device Numbering System
MOTOROLA Ordering Information and Mechanical Specifications 185

Ordering Information and Mechanical Specifications
17.3 8-Pin Plastic Dual In-Line Package (Case #626)
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
8 5 SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER
-B- ANSI Y14.5M, 1982.
1 4 MILLIMETERS INCHES
DIM MIN MAX MIN MAX
A 9.40 10.16 0.370 0.400
B 6.10 6.60 0.240 0.260
F C 3.94 4.45 0.155 0.175
D 0.38 0.51 0.015 0.020
NOTE 2 -A- F 1.02 1.78 0.040 0.070
L G 2.54 BSC 0.100 BSC
H 0.76 1.27 0.030 0.050
J 0.20 0.30 0.008 0.012
K 2.92 3.43 0.115 0.135
C L 7.62 BSC 0.300 BSC
M --- 10 ° --- 10 °
J N 0.76 1.01 0.030 0.040
-T-
SEATING N STYLE 1:
PLANE
M 1. AC IN
D K 2. DC + IN
3. DC - IN
H G 4. AC IN
0.13 (0.005) M T A M B M 5. GROUND
6. OUTPUT
7. AUXILIARY
8. VCC
17.4 8-Pin Small Outline Integrated Circuit Package (Case #968)
NOTES:
8 5 LE 1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER
Q1 3. DIMENSION D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE
E HE MEASURED AT THE PARTING LINE. MOLD
FLASH OR PROTRUSIONS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
M× 4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
1 4 5. THE LEAD WIDTH DIMENSION (b) DOES NOT
L
INCLUDE DAMBAR PROTUSION. ALLOWABLE
Z DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
DETAIL P TOTAL IN EXCESS OF THE LEAD WIDTH
D DIMENSION AT MAXIMUM MATERIAL
CONDITION. DAMBAR CANNOT BE LOCATED
ON THE LOWER RADIUS OR THE FOOT
MINIMUM SPACE BETWEEN PROTRUSIONS
e
AND ADJACENT LEAD TO BE 0.46 (0.018).
P
MILLIMETERS INCHES
A
DIM MIN MAX MIN MAX

A --- 2.05 --- 0.081
A1 0.05 0.20 0.002 0.008
A1
b b 0.35 0.50 0.014 0.020

c c 0.18 0.27 0.007 0.011
0.13 (0.005) M D 5.10 5.50 0.201 0.217
0.10 (0.004) E 5.10 5.45 0.201 0.215
e 1.27 BSC 0.050 BSC
HE 7.40 8.20 0.291 0.323
L 0.50 0.85 0.020 0.033
LE 1.10 1.50 0.043 0.059
M 0° 10° 0° 10°
Q1 0.70 0.90 0.028 0.035
Z --- 0.94 --- 0.037
186 Ordering Information and Mechanical Specifications MOTOROLA

8-Pin Dual Flat No Lead (DFN) Package (Case #1452)
17.5 8-Pin Dual Flat No Lead (DFN) Package (Case #1452)
0.1 C
A 4 2X
0.1 C
0.1 C 8 5
1.0 1.00 0.05 C 4
2X 0.8 0.75
(0.35)
0.05
4 0.00 (0.8) C SEATING PLANE
DETAIL G
VIEW ROTATED 90 o CLOCKWISE
1 4
PIN 1 0.3
B INDEX AREA 0.2
G 0.3
0.2
M M
DETAIL M
BACKSIDE PIN 1 INDEX
0.1 C A B
3.5
DETAIL M 3.4
PIN 1 INDEX 1 4 EXPOSED DIE
ATTACH PAD
3.05 2.55
2.95 2.45
0.1 C A B 0.1 C A B 0.4 6X 0.8 0.065
8X
0.015
DETAIL N
N
NOTES:
0.5 8 5 1. ALL DIMENSIONS ARE IN MILLIMETERS.
8X 2. INTERPRET DIMENSIONS AND TOLERANCES PER
0.4 0.35
8X ASME Y14.5M, 1994.
0.25 3. THE COMPLETE JEDEC DESIGNATOR FOR THIS
0.1 M C A B PACKAGE IS: HP-VFDFP-N.
4. COPLANARITY APPLIES TO LEADS AND DIE ATTACH
VIEW M-M 0.05 M C PAD.

17.6 16-Pin Plastic Dual In-Line Package (Case #648D)
NOTES:
-A- ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
16 9
4. DIMENSIONS A AND B DO NOT INCLUDE
-B- MOLD PROTRUSION.
5. MOLD FLASH OR PROTRUSIONS SHALL NOT
1 8 EXCEED 0.25 (0.010).
6. ROUNDED CORNERS OPTIONAL.
F C L INCHES MILLIMETERS
DIM MIN MAX MIN MAX
S A 0.740 0.760 18.80 19.30
SEATING B 0.245 0.260 6.23 6.60
-T- PLANE C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
F 0.050 0.070 1.27 1.77
K J M G 0.100 BSC 2.54 BSC
H H 0.050 BSC 1.27 BSC
J 0.008 0.015 0.21 0.38
G K 0.120 0.140 3.05 3.55
D 16 PL L 0.295 0.305 7.50 7.74
0.25 (0.010) M T B S A S M 0° 10° 0° 10°
S 0.015 0.035 0.39 0.88
17.7 16-Pin Small Outline Integrated Circuit Package (Case #751G)
D A NOTES:
q 1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND
16 9 TOLERANCES PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INLCUDE
M
MOLD PROTRUSION.
B
4. MAXIMUM MOLD PROTRUSION 0.15 PER

SIDE.
H
h X 45 °
M
5. DIMENSION B DOES NOT INCLUDE DAMBAR

8X
0.25
PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.13 TOTAL IN
EXCESS OF THE B DIMENSION AT MAXIMUM
MATERIAL CONDITION.
1 8
MILLIMETERS
16X B B DIM MIN MAX
A 2.35 2.65
0.25 M T A S B S A1 0.10 0.25
B 0.35 0.49
C 0.23 0.32
D 10.15 10.45
E 7.40 7.60
A
e 1.27 BSC
H 10.05 10.55
h 0.25 0.75
L
SEATING
L 0.40 1.00
14X e PLANE
0° 7°
A1
q
T C

16-Pin Thin Shrink Small Outline Package (Case #948F)
17.8 16-Pin Thin Shrink Small Outline Package (Case #948F)
16X K REF
0.10 (0.004) M T U S V S
NOTES:
0.15 (0.006) T U S
K ANSI Y14.5M, 1982.
5. CONTROLLING DIMENSION: MILLIMETER.
K1 6. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
16 9 MOLD FLASH OR GATE BURRS SHALL NOT
2X L/2 J1 EXCEED 0.15 (0.006) PER SIDE.
7. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
B SECTION N-N INTERLEAD FLASH OR PROTRUSION SHALL
L -U- NOT EXCEED
J 0.25 (0.010) PER SIDE.
PIN 1 8. DIMENSION K DOES NOT INCLUDE DAMBAR
IDENT. PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
1 8 IN EXCESS OF THE K DIMENSION AT
N MAXIMUM MATERIAL CONDITION.
0.25 (0.010) 9. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
0.15 (0.006) T U S 10. DIMENSION A AND B ARE TO BE
A M DETERMINED AT DATUM PLANE -W-.
-V-
N
F MILLIMETERS INCHES
DIM MIN MAX MIN MAX
DETAIL E A 4.90 5.10 0.193 0.200
B 4.30 4.50 0.169 0.177
C --- 1.20 --- 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
C -W- G 0.65 BSC 0.026 BSC
H 0.18 0.28 0.007 0.011
J 0.09 0.20 0.004 0.008
0.10 (0.004) J1 0.09 0.16 0.004 0.006
-T- SEATING H DETAIL E K 0.19 0.30 0.007 0.012
PLANE D G K1 0.19 0.25 0.007 0.010
L 6.40 BSC 0.252 BSC
M 0° 8° 0° 8°


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Information in this document is provided solely to enable system and software implementers to use Motorola products.
There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or
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names are the property of their respective owners. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
© Motorola Inc. 2003
MC68HC908QY4/D
Rev. 1.0
8/2003
L3
LAMPIRAN GAMBAR RANGKAIAN

RANGKAIAN KONEKSI RTC DAN LCD DENGAN MIKROKONTROLER
XTAL VCC
32.768 KHZ
DS1307
1 8
2 X1 VDD 7
3 X2 SQW/OUT 6 VCC
4 Vbat SCL 5
GND SDA
Vcc
K
DS1307 GND LCD 16 X 2
3V
VEE A
RS
VCC
0 0 0 E R/W D0 D1 D2 D3 D4 D5 D6 D7
U12
10k 10k 10k
15
PTB0 14
VCC PTB1 13
PTA0/AD0/TCH0/KBI0 12
PTA1/AD1/TCH1/KBI1 11
PTB2 10
1 PTB3 9 13 15
VDD PTA2/IRQ/KBI2/TCLK OE Q0
16 8 1
VSS PTA3/RST/KBI3 7 12 Q1
2 PTB4 6 STcp 2
PTB7 PTB5 5 Q2
PTA4/OSC2/AD2/KBI4 4 10 3
PTA5/OSC1/AD3/KBI5 3 MR Q3
PTB6 4
11 Q4
MC68HC908QY 4 SHcp 5
Q5
14 6
DS Q6
7
Q7
74HC595
9
10K 10K Q7'
DETEKTOR BEBAN 2
DETEKTOR BEBAN 1
SW1
MODE
SW2
Title
HOUR METER
PILIH
Size Document Number Rev
A I WAY AN SANTRA / 005114006 <Rev Code>
0
Date: Monday , January 22, 2007 Sheet 1 of 1
RANGKAIAN KONEKSI DETEKTOR BEBAN DENGAN MIKROKONTROLER
D1 D4
1N5408 1N5408
T1
600V 4 A
T2
D2 D3 RGT1
1
1N5408 1N5408 280 1 T1 5
7805
4 - + 2 1 3
4 8 VIN VOUT
500 mA
GND
BEBAN 1 330
3
220 Vac 47uF 47uF
2
LED
0 0 MC68HC908QY4
PTA3
D5 D8
1N5408 1N5408 PTA4
T1
600V 4 A
T2
D6 D7 RGT2 10K 10K
1
1N5408 1N5408 280 1 T1 5
7805
4 - + 2 1 3
4 8 VIN VOUT 0 0
500 mA
GND
BEBAN 2 330
3
47uF 47uF
2
LED
0 0
Title
KONEKSI DETEKTOR BEBAN
Size Document Number Rev

A I WAY AN SANTRA / 005114006 / HM <Rev Code>
Date: Monday , January 22, 2007 Sheet 1 of 1

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PENGUKUR LAMA WAKTU KERJA ALAT

Diajukan Untuk Memenuhi Salah Satu Syarat

PROGRAM STUDI TEKNIK ELEKTRO

Diajukan Untuk Memenuhi Salah Satu Syarat

PROGRAM STUDI TEKNIK ELEKTRO

Electrical Engineering Study Program

KEGAGALAN ADALAH PROSES

Dengan rasa syukur kepada Tuhan, sekripsi ini

Dalam penelitian ini hour meter dikendalikan dengan sebuah

Kata kunci : Hour meter, MC68HC908QY4.

In this research is hour meter controlled with a microcontroller

Keyword : hour meter, MC68HC908QY4.

Penulis menyadari bahwa skripsi ini masih banyak kekurangan, karena

Yogyakarta, Januari 2007

HALAMAN JUDUL (INDONESIA) .............................................................. i

BAB II DASAR TEORI................................................................................. 6

BAB III RANCANGAN PENELITIAN....................................................... 31

BAB IV HASIL DAN PEMBAHASAN ....................................................... 59

BAB V KESIMPULAN DAN SARAN ......................................................... 80

DAFTAR PUSTAKA ..................................................................................... 82

Gambar 2.1 Sistem Bus I2C ............................................................................. 6

Gambar 2.2 Transfer Data dalam Bus Serial I2C ............................................ 8

Gambar 2.3 Diagram Blok Antarmuka Mikrokontroler dengan DS1307........ 9

Gambar 2.4 Diagram Blok Antarmuka Mikrokontroler dengan LCD............. 10

Gambar 2.5 Konfigurasi Pin DS1307 .............................................................. 12

Gambar 2.6 Diagram Blok MC68HC908QY4 ................................................ 16

Gambar 2.7 Penempatan Pin MC68HC908QY4 ............................................. 17

Gambar 2.8 Port A Data Register .................................................................... 18

Gambar 2.9 Data Direction Register A (DDRA) ............................................ 19

Gambar 2.10 Port A Input Pullup Enable Register (PTAPUE)....................... 20

Gambar 2.11 Port B Data Register (PTB) ...................................................... 21

Gambar 2.12 Data Direction Register B (DDRB) ........................................... 22

Gambar 2.14 IRQ Status dan Control Register (INTSCR) ............................. 24

Gambar 2.15 Penempatan pin 74HC595.......................................................... 25

Gambar 2.16 Konfigurasi Kaki M1632 Hitachi............................................... 28

Gambar 2.17 Rangkaian Detektor Beban ........................................................ 29

Gambar 2.18 Rangkaian Pengubah AC ke DC ................................................ 30

Gambar 3.1 Layout Hour Meter Tampak Depan ............................................ 32

Gambar 3.2 Layout Hour Meter Tampak Belakang......................................... 33

Gambar 3.5 Rangkaian Mikrokontroler dengan Tombol Push Button ........... 38

Gambar 3.6 Koneksi Mikrokontroler dengan LCD ......................................... 39

Gambar 3.10 Diagram Blok Sistem Program .................................................. 44

Gambar 3.17 Diagram Alir Program Utama .................................................... 48

Gambar 3.18 Diagram Alir Pengambilan Data RTC ....................................... 50

Gambar 3.19 Diagram alir Subrutin Kirim Data ke RTC ................................ 51

Gambar 3. 20 Diagram Alir Start dan Stop Serial ........................................... 52

Gambar 4.1 Tampilan Alat Sebelum Digunakan untuk Pengukuran............... 59

1.1 Latar Belakang

Perkembangan teknologi sekarang sangat memegang peranan penting dalam

peradaban manusia. Seiring dengan perkembangan teknologi yang semakin modern,

banyak dijumpai beranekaragam peralatan elektronika yang tersedia di pasaran,

sehingga banyak pekerjaan dapat dilakukan dengan memanfaatkan teknologi

terutama teknologi elektronika. Sekarang penggunaan mesin atau peralatan

elektronika sudah menjadi kebutuhan hampir setiap sudut kehidupan manusia.

Tentunya pemakaian suatu peralatan memerlukan perawatan, karena komponen

pemakaian yang tanpa memperhatikan lama waktu penggunaan secara langsung

umur dari peralatan tersebut.

peralatan yang memakai tenaga listrik sebagai catu daya.

1.2 Perumusan Masalah

Karena masih terbatasnya mesin atau peralatan yang menggunakan tenaga

dari penelitian ini adalah bagaimana merancang dan menimplementasikan

mikrokontroler motorola MC68HC908QY4 sebagai pengendali utama dengan

dua detektor beban, dan dua buah tombol push button.