Percobaan V

Synthesizable MIPS32®Microprocessor
Bagian III : Top Level Design dan Testbench

Pangeran Letarare Sitompul (14S17009)

Tanggal Percobaan : 4 Desember 2019
[NWS3103] [Praktikum Arsitektur]
Lab Dasar Teknik Elektro – Teknik Elektro
Institut Teknologi Del

➢ Praktikan dapat membuat testbench untuk menguji

Abstrak— SYNTHESIZABLE MIPS32®
MICROPROCESSOR BAGIAN III: TOP LEVEL DESIGN
DAN TESTBENCH Arsitektur mikroprosesor MIPS32®
beserta datapath eksekusinya,instruction set dan dapat
membuat program sederhana dalam bahasa assembly
memahami Praktikan dapat menggabungkan komponen-
komponen desain yang telah dibuat dari praktikum
sebelumnya dalam kode VHDL untuk membuat top level
design dari mikroprosesor Single-Cycle MIPS32® yang
synthesizable dan dapat disimulasikan dengan Altera®
Quartus® II v9.1sp2,dalam praktikum membuat testbenkch
untuk menguji desain mikroprosesor single cyccle dalam
kode VHDL dan dapat disimulasikan dengan Altera®
Quartus® II v9.1sp2. dan simulasi melakukan eksekusi
dengan IPS32® pada program simulasi SPIM dan
memahami cara setiap instruksi dieksekusi
Key word : instruction set, datapath dan pengujian
menggunakan testBench
desain mikriprosesor Single-Cycle MIPS32® dalam
kode VHDL dan dapat disimulasikan dengan Altera®
Quartus® II v9.1sp2.
BAB II. LANDASAN TEORETIS
A. Datapath dan Control
Dalam desain mikroprosesor Single-Cycle MIPS32®,
rangkaian digital dapat dikelompokkan menjadi dua macam, yaitu
datapath (jalur data) dan control (kontrol). Datapath merupakan
komponen dari mikroprosesor yang melakukan operasi aritmetik
serta melakukan penyimpanan data. Dalam datapath pula kelima
tahap pemrosesan instruksi meliputi instruction fetch, instruction
decode, execute, memory access, dan write back dilaksanakan.
Sedangkan control merupakan komponen dari mikroprosesor
yang mengatur datapath berdasarkan instruksi yang sedang
dieksekusi

BAB 1 PENDAHULUAN Bagian kontrol telah direpresentasikan oleh control unit

yang telah kita desain pada praktikum sebelumnya. Untuk bagian
Pada praktikum ini merupakan synthesizable MIPS32 dengna datapath, kita perlu menggabungkan komponen-komponen yang
menggunakan top level design dan testbench dengan telah kita buat meliputi multiplexer, ALU, register, data memory,
melakukan perancangan instruction memory , data memory dan instruction memory, dan sebagainya untuk membentuk sebuah
register. Dengan menggunakan bahasa VHDL dikarenakan jalur yang dapat dilewati oleh data. Dengan demikian, control dan
pembuatan kode prpogram lebih behavioral maupun structural. datapath tidak dapat dipisahkan dalam desain sebuah
Adapaun tujuan yang harus dicapai dalam praktikan ini adalah mikroprosesor. Datapath dan control akan membentuk sebuah
sebagai berikut: desain mikroprosesor Single-Cycle MIPS32® yang disebut sebuah
➢ Praktikan memahami arsitektur mikroprosesor top-level design (desain paling atas). Top-level design pada
MIPS32® beserta datapath eksekusinya. umumnya hanya berisi port mapping dari satu komponen ke
➢ Praktikan memahami instruction set dari MIPS32®dan komponen lain.
dapat membuat program sederhana dalam Bahasa
assembly yang dapat dieksekusi pada MIPS32.
➢ Praktikan dapat melakukan simulasi eksekusi program
MIPS32® pada program simulasi SPIM dan memahami
cara setiap instruksi dieksekusi
➢ Praktikan dapat menggabungkan komponen-komponen
desain yang telah dibuat dari praktikan sebelumnya
dalam kode VHDL untuk membuat top level design dari
mikroprosesor Single-Cycle MIPS32® yang
synthesizable dan dapat disimulasikan dengan Altera®
Quartus® II v9.1sp2.
 5. sgnMemReadout => SigMemRead
6. sgnMemWriteout => SIGMemWrite
7. sgnMemToRegOut => SIGMemtoReg

1. Fungsi Simulasi ketika data 0 – 120 ns

B. Testbench
Dalam melakukan simulasi sebuah rangkaian digital, biasanya kita
memberikan sinyal input secara manual melalui sebuah waveform Pada tampilan diatas kta melihat bahwa adanya
editor. Cara ini boleh dibilang sederhana namun akan sangat tidak perbedaan tiap data yang kita peroleh dengan setiap
efektif apabila kita melakukan simulasi secara berulang-ulang. percobaan yang telah kita lakukan sebelumnya.
Cara lain untuk melakukan simulasi suatu rangkaian digital tanpa
memberikan input satu per satu menggunakan waveform editor
adalah menggunakan testbech 2. Simulasi Timing

Pada dasarnya, testbench terdiri atas kode VHDL atau Verilog HDL,
tergantung pada implementasi. Testbench sendiri dapat berisi sebuah
desain yang menyimpan nilai-nilai sinyal input yang harus diberikan
Sample dari 4 clock : 0ns-40ns
kepada desain yang sedang diuji (design under test). Kemudian, testbench
ini akan mengeluarkan masing- masing input yang harus diberikan kepada
desain yang sedang diuji berdasarkan suatu trigger, misalnya clock.

III. HASIL DAN ANALISIS

A. Tugas 1 : Implementasi Top-Level Design MIPS32

Adapun sinyal kontrol adalah sebagai berikut :

1. sgnregdestout => SIGRegDest
2. sgnregwriteout => SIGRegWrite
3. sgnALUSrcout => SIGALUSrc
4. sgnBranchResult => branch_result
Melaui data yang diambil dari scale diperoleh bahwa pada waktu
0-10.0ns ketika 0ns bernilai 0000000 bernilai nol atau delay
sebesar1 scale dan kembali bekerja ketika melewati 1 scale
tersebut , pada output outmux1,pcntest,pcoutTest,pcplus4out
akan menghasilkan nilai (signed decimal) dengan memiliki IV.
perbedaan angka sebesar 4 dari 1 clock ke scale yang lain. KESIMPULAN
Pada instrout memiliki nilai berbentuk hexadecimal ketika
melewati masa delay tersebut ketika pada signaddr juga memiliki 1. Pengujian Single-Cycle MIPS32 dapat
nilai dalam bentuk (signed decimal) dan untuk signALU akan dilakukan dengan memberikan instruksi-instruksi
bekerja ketika melewati 2 clock. dalam Bahasa MIPS yang dapat dieksekusi oleh
mikroprosesor. Instruksi-instruksi tersebut diubah
Sample dari 4 clock : 50ns-90ns ke dalam format instruksi MIPS32 bit(opcode,
func, rt, rs, rd) yang kemudian diubah menjadi
suatu bilangan hexadecimal8 bit, yang
disimpan pada instruction memory sebelum
akhirnya dieksekusi.

2. Single-Cycle MIPS32 dapat dibuat

dengan cara menggabungkan komponen-
komponen seperti ALU, multiplexer, register file,
instruction memory, data memory, dan komponen
lainnya ke dalam suatu top level design. Deklarasi
komponen, definisi sinyal penghubung antar
komponen, serta port mapping yang sesuai maka
akan dapat menghasilkan suatu Single-Cycle
MIPS32 yang utuh.

V. REFERENSI

1. BRYANT, RANDAL, DAN DAVID O’HALLARON.

COMPUER
2. SYSTEMS : A PROGRAMMER’S PERSPECTIVE 2ND
EDITION. 2011
3. MASSACHUSETTS : PERSON EDUCATION INC. PA
Melaui data yang diambil dari scale diperoleh bahwa pada
waktu 50ns-90.0ns ketika 50ns bernilai bernilai nol atau delay
sebesar1 scale dan kembali bekerja ketika melewati 1 scale
tersebut , pada output outmux1,pcntest,pcoutTest,pcplus4out
akan menghasilkan nilai (signed decimal) dengan memiliki
perbedaan angka sebesar 4 dari 1 clock ke scale yang lain.
Pada instrout memiliki nilai berbentuk hexadecimal ketika
melewati masa delay tersebut ketika pada signaddr juga
memiliki nilai dalam bentuk (signed decimal) dan untuk
signALU akan bekerja ketika melewati 2 clock.

B. Tugas 2 : Pengujian Menggunakan TestBench

Pada percobaan ini tidak dapat dikerjakakn (gagal)
 Lampiran

Percobaan 1

Program Counter (PC)

-- Praktikum EL3111 Arsitektur Sistem Komputer

-- Modul : 5
-- Percobaan : 1
-- Tanggal : 4 Desember 2019
-- Nama : Pangeran Sitompul (14S17009)
-- Nama File : program_counter.vhd

library ieee;
use ieee.std_logic_1164.all;

entity program_counter

is port(
clk : IN
std_logic;
PC_in : IN std_logic_vector (31 downto 0);
PC_out: OUT std_logic_vector (31 downto 0)
);

end program_counter;

architecture behavioral of program_counter

is begin
process (clk)
begin
if clk' event and clk='1' then
PC_out <= PC_in;
end if;
end process;
end behavioral;
Left Shift

-- Praktikum EL3111 Arsitektur Sistem Komputer

-- Modul : 5
-- Percobaan : 2- 32 bit
-- Tanggal : 4 Desember 2019
-- Nama : Pangeran Sitompul (14S17009)
-- Nama File : lshift_32_32.vhd

library ieee;
use ieee.std_logic_1164.all;

entity lshift_32_32
is port (

D_IN : IN std logic vector (31 downto 0);

D_OUT : OUT std logic vector (31 downto 0);

);
end lshift_32_32;

architecture behavioral of lshift_32_32

is begin
D_OUT (31 downto 2) <= D_IN (29 downto 0);
D_OUT (1 downto 0) <= (others => '0');
end behavioral;
Left Shift 28 BIT
-- Praktikum EL3111 Arsitektur Sistem Komputer
-- Modul : 5
-- Percobaan : 2- 28 bit
-- Tanggal : 4 Desember 2019
-- Nama : Pangeran Sitompul (14S17009)
File : lshift_26_28.vhd

library ieee;
use ieee.std_logic_1164.all;

entity lshift_26_28
is port (
D_IN : IN std_logic_vector (25 downto 0);
D_OUT : OUT std_logic_vector (27 downto 0)
);
end lshift_26_28;

architecture behavioral of lshift_26_28

is begin
D_OUT (27 downto 2) <= D_IN (25 downto 0);
D_OUT (1 downto 0) <= (others => '0');
end behavioral;

Cla_32

-- Praktikum EL3111 Arsitektur Sistem Komputer

-- Modul : 5
-- Percobaan : 3
-- Tanggal : 4 Desember 2019
-- Nama : Pangeran Sitompul (14S17009)
-- Nama File : cla_32.vhd

library ieee;
use ieee.std_logic_1164.all;

entity cla_32 is
port (
OPRND_1 : IN std_logic_vector (31 downto 0);
 OPRND_2 : IN std_logic_vector (31 downto 0);
C_IN : IN std_logic;
RESULT : OUT std_logic_vector (31 downto 0);
C_OUT : OUT std_logic
);
end cla_32;

architecture behavioral of cla_32 is

signal sum : std_logic_vector (31 downto 0);
signal carry_a : std_logic_vector (31 downto 0);
signal carry_b : std_logic_vector (31 downto 0);
signal carry_in: std_logic_vector (31 downto 1);
begin
sum <= OPRND_1 XOR OPRND_2;
carry_a <= OPRND_1 AND OPRND_2;
carry_b <= OPRND_1 OR OPRND_2;
process (carry_a, carry_b, carry_in)
begin
carry_in(1) <= carry_a (0) OR (carry_b(0) AND C_IN);
carry : for i in 1 to 30 loop
carry_in(i+1) <= carry_a(i) OR (carry_b(i) AND carry_in (i));
end loop;
C_OUT <= carry_a(31) OR (carry_b(31) AND carry_in (31));
end process;
RESULT(0) <= sum(0) XOR C_IN;
RESULT (31 downto 1) <= sum (31 downto 1) XOR carry_in (31 downto 1);

end behavioral;

Sign Extender

-- Praktikum EL3111 Arsitektur Sistem Komputer

-- Modul : 5
-- Percobaan : 4
-- Tanggal : 4 Desember 2019
-- Nama : Pangeran Sitompul (14S17009)
-- Nama File : sign_extender.vhd
library ieee;
use ieee.std_logic_1164.all;

entity sign_extender is
port (
D_In : IN std_logic_vector (15 downto 0);
D_Out : OUT std_logic_vector (31 downto 0)
);
end sign_extender;

architecture behavioral of sign_extender is

begin
process (D_In(15))
begin
if D_In (15) = '1' then
D_Out(31 downto 16) <= (others => '1');
else
D_Out(31 downto 16) <= (others => '0');
 end if;
end process;
D_Out(15 downto 0) <= D_In(15 downto 0);
end behavioral;

ALU

-- Praktikum EL3111 Arsitektur Sistem Komputer

-- Modul : 5
-- Percobaan : 5
-- Tanggal : 4 Desember 2019
-- Nama : Pangeran Sitompul (14S17009)
-- Nama File : ALU.vhd
library ieee;
use ieee.std_logic_1164.all;

entity ALU is
port(
OPERAND_1 : IN std_logic_vector (31 downto 0);
OPERAND_2 : IN std_logic_vector (31 downto 0);
OP_SEL : IN std_logic_vector (1 downto 0);
OUTPUT : OUT std_logic_vector (31 downto 0)
);
end ALU;
architecture behavioral of ALU is
signal op_a : std_logic_vector (31 downto 0);
signal op_b : std_logic_vector (31 downto 0);
signal c_in : std_logic;
signal c_out: std_logic;
signal hasil: std_logic_vector (31 downto 0);

component cla_32
port (
OPRND_1 : IN std_logic_vector (31 downto 0);
OPRND_2 : IN std_logic_vector (31 downto 0);
C_In : IN std_logic;
RESULT : OUT std_logic_vector (31 downto 0);
C_Out : OUT std_logic
);
end component;
begin
componentcarry: cla_32
port map (
OPRND_1 => op_a,
OPRND_2 => op_b,
C_In => c_in,
C_Out => c_out,
RESULT => hasil
);
process (OP_SEL)
begin
if OP_SEL = "00" then
op_a <= OPERAND_1;
op_b <= OPERAND_2;
c_in <= OP_SEL (0);
OUTPUT <= hasil;
elsif OP_SEL = "01" then
op_a <= OPERAND_1 ;
 op_b <= (not OPERAND_2);
c_in <= OP_SEL(0);
OUTPUT <= hasil;
end if;
end process;
end behavioral;

CU
-- Praktikum EL3111 Arsitektur Sistem Komputer
-- Modul : 5
-- Percobaan : 6
-- Tanggal : 4 Desember 2019
-- Nama : Pangeran Sitompul (14S17009)
-- Nama File : cu.vhd
library ieee;
use ieee.std_logic_1164.all;

entity cu is
port (
OP_In : IN std_logic_vector (5 downto 0);
FUNCT_In : IN std_logic_vector (5 downto 0);
Sig_Jmp : OUT std_logic_vector (1 downto 0);
Sig_Bne : OUT std_logic;
Sig_Branch : OUT std_logic;
Sig_MemtoReg: OUT std_logic;
Sig_MemRead : OUT std_logic;
Sig_MemWrite: OUT std_logic;
Sig_RegDest : OUT std_logic_vector (1 downto 0);
Sig_RegWrite: OUT std_logic;
Sig_ALUSrc : OUT std_logic_vector (1 downto 0);
Sig_ALUCtrl : OUT std_logic_vector (1 downto 0)
);
end cu;

architecture behavioral of cu is
begin
process (OP_In, FUNCT_In)
begin
--Sig_Jmp
if OP_In = "000010" then
Sig_Jmp <= "01";
else
Sig_Jmp <= "00";
end if;
--Sig_Bne
if OP_In = "000101" then
Sig_Bne <= '1';
else
Sig_Bne <= '0';
end if;
--Sig_Branch
if OP_In = "000100" then
Sig_Branch <= '1';
else
Sig_Branch <= '0';
end if;
--Sig_MemtoReg and Sig_MemRead
if OP_In = "100011" then
 Sig_MemtoReg <= '1';
Sig_MemRead <= '1';
else
Sig_MemtoReg <= '0';
Sig_MemRead <= '0';
end if;
--Sig_MemWrite
if OP_In = "101011" then
Sig_MemWrite <= '1';
else
Sig_MemWrite <= '0';
end if;
--Sig_RegDest
if (OP_In = "000000" AND (FUNCT_In = "100000" OR FUNCT_In = "100010")) then
Sig_RegDest <= "01";
else
Sig_RegDest <= "00";
end if;
--Sig_RegWrite
if (OP_In = "000000" AND (FUNCT_In = "100000" OR FUNCT_In = "100010")) OR OP_In =
"001000" OR OP_In = "100011" then
Sig_RegWrite <= '1';
else
Sig_RegWrite <= '0';
end if;
--Sig_ALUSrc
if OP_In = "001000" OR OP_In = "100011" OR OP_In = "101011" then
Sig_ALUSrc <= "01";
else
Sig_ALUSrc <= "00";
end if;
--Sig_ALUCtrl
if (OP_In = "000000" AND FUNCT_In = "100010") then
Sig_ALUCtrl <= "01";
else
Sig_ALUCtrl <= "00";
end if;
end process;
end behavioral;

instrucMEM

-- Praktikum EL3111 Arsitektur Sistem Komputer

-- Modul : 5
-- Percobaan : 1
-- Tanggal : 4 Desember 2019
-- Nama : Pangeran Sitompul (14S17009)
-- Nama File : instrucMEM.vhd

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.ALL;

entity instrucMEM is
 port (
ADDR : in std_logic_vector (31 downto 0);
clock : in std_logic;
INSTR : out std_logic_vector (31 downto 0)
);
end entity;
architecture behavior of instrucMEM is
type ramtype is array (255 downto 0) of std_logic_vector (31 downto 0);
signal mem: ramtype;
begin
process (clock,ADDR)
begin
if clock'event and clock='1' then
INSTR <= mem(conv_integer (ADDR));
end if;
end process;
-- Isi instruction memory
mem(0) <= X"00000000"; -- initializing
mem(4) <= X"20080000"; -- add $t0, $0, $0
mem(8) <= X"20090000"; -- add $t1,$0,$0
mem(12) <= X"212afff6"; -- addi $t2, $t1, -10
mem(16) <= X"15400001"; -- bne $t2,$0, loop
mem(20) <= X"00000000"; -- nop -- if not bne, j done -- loop :
mem(28) <= X"21080001"; -- addi $t0, $t0, 1
mem(32) <= X"21290001"; -- addi $t1, $t1, 1
mem(36) <= X"212afff6"; -- addi $t2, $t1, -10
mem(40) <= X"1540fffc"; -- bne $t2, $0, loop
mem(44) <= X"00000000"; -- nop -- done :
mem(48) <= X"03e08021"; -- addu $s0, $ra, $0
mem(52) <= X"0010f821"; -- addu $ra, $0, $s0
end behavior;

top_level_design

-- Praktikum EL3111 Arsitektur Sistem Komputer

-- Modul : 5
-- Percobaan : 1
-- Tanggal : 4 Desember 2019
-- Nama : Pangeran Sitompul (14S17009)
-- Nama File : top_level_design.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

entity top_level_design is
PORT (
clk, rst : IN STD_LOGIC;
ALU_result, PCinTest, PCoutTest : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
rd1out,rd2out, instrout ,sgnsignimmout : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
outmux1out, PCplus4out,sgnRead_Mem1out : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
sgnwritedataout:OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
instr_15_11_out : OUT STD_LOGIC_VECTOR (4 downto 0);
instr_20_16_out : OUT STD_LOGIC_VECTOR (4 downto 0);
instr_25_21_out : OUT STD_LOGIC_VECTOR (4 downto 0);
sgnaddress_regout : OUT STD_LOGIC_VECTOR (4 downto 0);
sgnMemReadout, sgnMemWriteout : OUT STD_LOGIC;
sgnMemToRegOut : OUT STD_LOGIC;
 sgnregdestout,sgnALUSrcout : OUT STD_LOGIC_VECTOR (1 downto 0);
sgnregwriteout,sgnBranchResult :OUT STD_LOGIC;
signoutshift2out:OUT STD_LOGIC_VECTOR (31 DOWNTO 0) );
end top_level_design;

architecture structural of top_level_design is

-- cu
component cu
PORT (
OP_In : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
FUNCT_In : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
Sig_Jmp : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
Sig_Bne : OUT STD_LOGIC;
Sig_Branch : OUT STD_LOGIC;
Sig_MemtoReg : OUT STD_LOGIC;
Sig_MemRead : OUT STD_LOGIC;
Sig_MemWrite : OUT STD_LOGIC;
Sig_RegDest : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
Sig_RegWrite : OUT STD_LOGIC;
Sig_ALUSrc : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
Sig_ALUCtrl : OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END COMPONENT;
-- PC
component program_counter
PORT (
clk : IN STD_LOGIC;
PC_in : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
PC_out : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;

-- cla
component cla_32
PORT (
OPRND_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- Operand 1
OPRND_2 : IN STD_LOGIC_VECTOR (31 DOWNTO 0); -- Operand 2
C_IN : IN STD_LOGIC; -- Carry In
RESULT : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); -- Result
C_OUT : OUT STD_LOGIC -- Overflow
);
END COMPONENT;
--ALU
COMPONENT ALU
PORT(
OPERAND_1 : IN std_logic_vector (31 DOWNTO 0); -- Data Input 1
OPERAND_2 : IN std_logic_vector (31 DOWNTO 0); -- Data Input 2
OP_SEL : IN std_logic_vector (1 DOWNTO 0); -- Operation Select
OUTPUT : OUT std_logic_vector (31 DOWNTO 0)
);
END COMPONENT;
-- bus_merger
COMPONENT bus_merger
PORT (
DATA_IN1 : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
DATA_IN2 : IN STD_LOGIC_VECTOR (27 DOWNTO 0);
DATA_OUT : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
-- data memori
COMPONENT data_memory
PORT(
ADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
WR_EN, RD_EN, clock : IN STD_LOGIC;
RD_Data : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
WR_Data : IN STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;

--instrucmem
COMPONENT instrucMEM port (
ADDR : in std_logic_vector (31 downto 0);
clock : in std_logic;
INSTR : out std_logic_vector (31 downto 0)
);
END COMPONENT;
-- komparator
COMPONENT comparator
PORT (
D_1 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
D_2 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
EQ : OUT STD_LOGIC -- Hasil Perbandingan EQ
);
END COMPONENT;
--mux 2 to 1
COMPONENT mux_2to1_32bit
PORT (
D1 : IN std_logic_vector (31 DOWNTO 0); -- Data Input 1
D2 : IN std_logic_vector (31 DOWNTO 0); -- Data Input 2
Y : OUT std_logic_vector (31 DOWNTO 0); -- Selected Data
S : IN std_logic -- Selector
);
END COMPONENT;
--mux 4 to 1 5 bit
COMPONENT mux_4to1_5bit
PORT (
D1 : IN std_logic_vector (4 DOWNTO 0); -- Data Input 1
D2 : IN std_logic_vector (4 DOWNTO 0); -- Data Input 2
D3 : IN std_logic_vector (4 DOWNTO 0); -- Data Input 3
D4 : IN std_logic_vector (4 DOWNTO 0); -- Data Input 4
Y : OUT std_logic_vector (4 DOWNTO 0); -- Selected Data
S : IN std_logic_vector (1 DOWNTO 0) -- Selector
);
END COMPONENT;
--mux 4 to 1 32 bit
COMPONENT mux_4to1_32bit
PORT (
D1 : IN std_logic_vector (31 DOWNTO 0); -- Data Input 1
D2 : IN std_logic_vector (31 DOWNTO 0); -- Data Input 2
D3 : IN std_logic_vector (31 DOWNTO 0); -- Data Input 3
D4 : IN std_logic_vector (31 DOWNTO 0); -- Data Input 4
Y : OUT std_logic_vector (31 DOWNTO 0); -- Selected Data
S : IN std_logic_vector (1 DOWNTO 0) -- Selector
);
END COMPONENT;
-- register
COMPONENT Reg_File
PORT(
 clock,WR_EN : IN STD_LOGIC;
ADDR_1,ADDR_2,ADDR_3 : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
WR_DATA_3: IN STD_LOGIC_VECTOR(31 DOWNTO 0);
RD_DATA_1,RD_DATA_2: OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
-- sign_extender
COMPONENT sign_extender
PORT(
D_In : IN std_logic_vector (15 DOWNTO 0); -- Data Input 1
D_Out : OUT std_logic_vector (31 DOWNTO 0) -- Data Input 2
);
END COMPONENT;
COMPONENT lshift_32_32 -- lshift 32_32
PORT (
D_IN : IN STD_LOGIC_VECTOR (31 DOWNTO 0); -- Input 32-bit
D_OUT : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) -- Output 32-bit
);
END COMPONENT;
COMPONENT lshift_26_28 -- lshift 26_28
PORT (
D_IN : IN STD_LOGIC_VECTOR (25 DOWNTO 0); -- Input 32-bit
D_OUT : OUT STD_LOGIC_VECTOR (27 DOWNTO 0) -- Output 32-bit
);
END COMPONENT;

-- deklarasi sinyal-sinyal
SIGNAL pcin, pcout : STD_LOGIC_VECTOR (31 downto 0); -- PC
SIGNAL instruction : STD_LOGIC_VECTOR (31 downto 0); -- Instruction memory
SIGNAL cout1, cout2 : STD_LOGIC; -- adder
SIGNAL result1, result2 : STD_LOGIC_VECTOR (31 DOWNTO 0);-- adder1adder2
SIGNAL branch_result, outEQ : STD_LOGIC; -- gerbang and
SIGNAL Add1res : STD_LOGIC_VECTOR (31 downto 0); --
SIGNAL outmux1, outbus, outmux2, outmux5 : STD_LOGIC_VECTOR (31 downto 0);
SIGNAL outshift1 : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL outshift2 : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL outmux4 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL WD3, RD1, RD2 : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL inshift,inshift2 : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL srcB : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL ALUresult : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL Read_mem : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL SIGBne : STD_LOGIC;
SIGNAL SIGBranch : STD_LOGIC;
SIGNAL SIGMemtoReg : STD_LOGIC;
SIGNAL SIGMemWrite : STD_LOGIC;
SIGNAL SigMemRead : STD_LOGIC;
SIGNAL SIGRegDest : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL SIGRegWrite : STD_LOGIC;
SIGNAL SIGJump : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL SIGALUSrc : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL SIGALUControl : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL Readmem: STD_LOGIC_VECTOR (31 DOWNTO 0);

BEGIN --Instruction Fetch

Blok_PC : program_counter
PORT MAP (clk, pcin, pcout);

Blok_cla1 : cla_32
PORT MAP (pcout, x"00000004", '0', result1, cout1);

Blok_mux1 : mux_2to1_32bit
PORT MAP (result1, result2, outmux1,branch_result);

Blok_mux2 :mux_4to1_32bit
PORT MAP (outmux1, outbus, x"00000000",x"00000000" ,outmux2,SIGJump);

Blok_mux3 :mux_2to1_32bit
PORT MAP (outmux2, x"00000000",pcin,rst);

Blok_busmerging : bus_merger
PORT MAP (result1(31 downto 28), outshift1, outbus);

Blok_instructMem : instrucMEM
PORT MAP (pcout, clk, instruction);

--Instruction Decode
control_unit : cu
PORT MAP (instruction(31 downto 26), instruction(5 downto 0), SIGJump, SIGBne,
SIGBranch, SIGMemtoReg,SigMemRead, SIGMemWrite, SIGRegDest, SIGRegWrite, SIGALUSrc,
SIGALUControl);

Blok_SL2 : lshift_26_28
PORT MAP (instruction(25 downto 0), outshift1);

Blok_reg_file : reg_File
PORT MAP (clk, SIGRegWrite, instruction(25 DOWNTO 21), instruction(20 downto 16),
outmux4, WD3, RD1, RD2);

Blok_mux4 : mux_4to1_5bit
PORT MAP (instruction(20 downto 16), instruction(15 downto
11),"00000","00000",outmux4, SIGRegDest);

Blok_Sign_ext : sign_extender
PORT MAP (instruction(15 downto 0), inshift2);
--Execution Stage
Blok_komparator : comparator
PORT MAP (RD1, RD2, outEQ); branch_result <= ((SIGBranch and outEQ) or (SIGBne and
(not outEQ)));

Blok_SL1 : lshift_32_32
PORT MAP (inshift2, outshift2);

Blok_cla2 : cla_32
PORT MAP (outshift2, pcout, '0', result2, cout2);

Blok_mux5 : mux_4to1_32bit
PORT MAP (RD2, inshift2, x"00000000", x"00000000",outmux5, SIGALUSrc);

Blok_ALU : ALU
PORT MAP (RD1, outmux5, SIGALUControl, ALUresult);
--Data Memory
Blok_data_mem : data_memory
PORT MAP (ALUresult(7 Downto 0), SIGMemWrite, SigMemRead, clk, Read_mem, RD2(7 downto
0));
Readmem(31 downto 8) <= (others => Read_mem(7));
Readmem(7 downto 0)<= Read_mem;
--Write Back
 Blok_mux6 : mux_2to1_32bit
PORT MAP (ALUresult, Readmem,WD3, SIGMemtoReg );
--Sinyal yang akan ditampilkan pada waveform
PCinTest <= pcin;
PCoutTest <= Pcout;
ALU_result <= ALUresult;
instrout <= instruction;
PCplus4out <= result1;
outmux1out <= outmux1;
rd1out <= RD1;
rd2out <= RD2;
instr_15_11_out<= instruction(15 downto 11);
instr_20_16_out<= instruction(20 downto 16);
instr_25_21_out<= instruction(25 downto 21);
sgnaddress_regout<= outmux4; sgnwritedataout<=WD3;
sgnregdestout <= SIGRegDest; sgnregwriteout<= SIGRegWrite;
sgnsignimmout<= inshift2;
sgnALUSrcout<= SIGALUSrc;
sgnBranchResult<= branch_result;
signoutshift2out<= outshift2;
sgnMemReadout<= SigMemRead;
sgnMemWriteout<=SIGMemWrite;
sgnRead_Mem1out<=Readmem;
sgnMemToRegOut<= SIGMemtoReg;

END structural;

MUX 4 to 1 32 bit

-- Praktikum EL3111 Arsitektur Sistem Komputer

-- Modul : 5
-- Percobaan : 1
-- Tanggal : 4 Desember 2019
-- Nama : Pangeran Sitompul (14S17009)
-- Nama File : mux_4to1_32bit.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY mux_4to1_32bit IS
PORT (
D1 : IN std_logic_vector (31 DOWNTO 0); -- Data Input 1
D2 : IN std_logic_vector (31 DOWNTO 0); -- Data Input 2
D3 : IN std_logic_vector (31 DOWNTO 0); -- Data Input 3
D4 : IN std_logic_vector (31 DOWNTO 0); -- Data Input 4
Y : OUT std_logic_vector (31 DOWNTO 0); -- Selected Data
S : IN std_logic_vector (1 DOWNTO 0) -- Selector
);
END mux_4to1_32bit;

ARCHITECTURE behavior OF mux_4to1_32bit IS

BEGIN
with S select
Y <= D1 when "00",
D2 when "01",
D3 when "10",
D4 when "11";
 END behavior;

MUX 4 to 1 5bit

-- Praktikum EL3111 Arsitektur Sistem Komputer

-- Modul : 5
-- Percobaan : 1
-- Tanggal : 4 Desember 2019
-- Nama : Pangeran Sitompul (14S17009)
-- Nama File : mux_4to1_5bit.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY mux_4to1_5bit IS
PORT (
D1 : IN std_logic_vector (4 DOWNTO 0); -- Data Input 1
D2 : IN std_logic_vector (4 DOWNTO 0); -- Data Input 2
D3 : IN std_logic_vector (4 DOWNTO 0); -- Data Input 3
D4 : IN std_logic_vector (4 DOWNTO 0); -- Data Input 4
Y : OUT std_logic_vector (4 DOWNTO 0); -- Selected Data
S : IN std_logic_vector (1 DOWNTO 0) -- Selector
);
END mux_4to1_5bit;

ARCHITECTURE behavior OF mux_4to1_5bit IS

BEGIN
with S select
Y <= D1 when "00",
D2 when "01",
D3 when "10",
D4 when "11";
END behavior;

MUX 2 to 1 32 bit

-- Praktikum EL3111 Arsitektur Sistem Komputer

-- Modul : 5
-- Percobaan : 1
-- Tanggal : 4 Desember 2019
-- Nama : Pangeran Sitompul (14S17009)
-- Nama File : mux_2to1_32bit.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY altera_mf; USE altera_mf.altera_mf_components.ALL;

ENTITY mux_2to1_32bit IS
PORT (
D1 : IN std_logic_vector (31 DOWNTO 0); -- Data Input 1
D2 : IN std_logic_vector (31 DOWNTO 0); -- Data Input 2
Y : OUT std_logic_vector (31 DOWNTO 0); -- Selected Data
S : IN std_logic
);
END mux_2to1_32bit;
 ARCHITECTURE behavior OF mux_2to1_32bit IS
BEGIN
PROCESS (S, D1, D2)
BEGIN
IF (S = '1') THEN
Y <= D2;
ELSE Y <= D1;
END IF;
END PROCESS;
END behavior;

Comparator

-- Praktikum EL3111 Arsitektur Sistem Komputer

-- Modul : 5
-- Percobaan : 1
-- Tanggal : 4 Desember 2019
-- Nama : Pangeran Sitompul (14S17009)
-- Nama File : comparator.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY comparator IS
PORT (
D_1 : IN std_logic_vector (31 DOWNTO 0); -- Data Input 1
D_2 : IN std_logic_vector (31 DOWNTO 0); -- Data Input 2
EQ : OUT std_logic -- Output
);
END comparator;

ARCHITECTURE behavior OF comparator IS

BEGIN
EQ <= '1' WHEN D_1 = D_2 ELSE '0';
END behavior;

Bus_Merger

-- Praktikum EL3111 Arsitektur Sistem Komputer

-- Modul : 5
-- Percobaan : 1
-- Tanggal : 4 Desember 2019
-- Nama : Pangeran Sitompul (14S17009)
-- Nama File : bus_merger.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY bus_merger IS
PORT (
DATA_IN1 : IN std_logic_vector (3 DOWNTO 0); -- Data Input 1
DATA_IN2 : IN std_logic_vector (27 DOWNTO 0); -- Data Input 2
 DATA_OUT : OUT std_logic_vector (31 DOWNTO 0) -- Output
);
END bus_merger;

ARCHITECTURE behavior OF bus_merger IS

BEGIN
DATA_OUT <= DATA_IN1 & DATA_IN2;

END behavior;

Reg_file

-- Praktikum EL3111 Arsitektur Sistem Komputer

-- Modul : 5
-- Percobaan : 1
-- Tanggal : 4 Desember 2019
-- Nama : Pangeran Sitompul (14S17009)
-- Nama File : instruction_memory.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.STD_LOGIC_ARITH.ALL;
USE ieee.std_logic_unsigned.all;
LIBRARY altera_mf;
USE altera_mf.all;

ENTITY reg_file IS
PORT (
clock : IN STD_LOGIC;
WR_EN : IN STD_LOGIC;
ADDR_1 : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
ADDR_2 : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
ADDR_3 : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
WR_DATA_3 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
RD_DATA_1 : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
RD_DATA_2 : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END ENTITY;

ARCHITECTURE behavior OF reg_file IS

TYPE ramtype IS ARRAY (31 DOWNTO 0) OF STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL mem : ramtype;

BEGIN
process (clock, WR_EN, ADDR_1, ADDR_2, ADDR_3, mem)
begin
if (clock'EVENT and clock = '0')
then
RD_DATA_1 <= mem(conv_integer (ADDR_1));
RD_DATA_2 <= mem(conv_integer (ADDR_2));
elsif (clock'EVENT and clock ='1' and WR_EN ='1')
then
mem(conv_integer(ADDR_3)) <= WR_DATA_3;
end if;
end process;

END behavior
Data_memory

-- Praktikum EL3111 Arsitektur Sistem Komputer

-- Modul : 5
-- Percobaan : 1
-- Tanggal : 4 Desember 2019
-- Nama : Pangeran Sitompul (14S17009)
-- Nama File : data_memory.vhd
-- Deskripsi : Desain data memory dengan menggunakan template desain
Altera MegaFunction ALTSYNCRAM

LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;

ENTITY data_memory IS
PORT (
ADDR : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
WR_EN, clock : IN STD_LOGIC;
RD_EN : IN STD_LOGIC;
RD_Data : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
WR_DATA : IN STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END data_memory;

ARCHITECTURE structural OF data_memory IS

COMPONENT altsyncram
GENERIC (
init_file : STRING;
operation_mode : STRING;
widthad_a : NATURAL;
width_a : NATURAL
);
PORT (
wren_a : IN STD_LOGIC;
clock0 : IN STD_LOGIC;
address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;

BEGIN

altsyncram_component : altsyncram
GENERIC MAP (
init_file => "dmemory.mif",
operation_mode => "SINGLE_PORT",
widthad_a => 8,
width_a => 8
)
PORT MAP (
wren_a => WR_EN AND NOT RD_EN,
 data_a => WR_DATA,
clock0 => clock,
address_a => ADDR,
q_a => RD_Data
);
END structural;