FPGA based Space Vector PWM Control IC for

Three Phase Induction Motor Drive

R.K.PongiannanI N.Yadaiah , Member IEEE
Department of Electrical and Electronics Engineering Department of Electrical and Electronics Engineering
Kumaraguru College of Technology, Coimbatore,TN,India JNTU College of Engineering,, Anantapur, AP, India
E- mail: pongiannan_rk@yahoo.co.in E - mail: yadaiahn@hotmail.com

Abstract - In conventional Digital motor controllers, the

PWM gating signal generation, current control loop for stator
current regulation, dead time generation and other
computational tasks requires high sampling rate to achieve
wide bandwidth performance. To relieve the controller from
FPEa
the time consuming computational task of PWM signal
generation, a novel method of Space Vector PWM signal
generation is implemented in FPGA using Hardware
Description Language VHDL. The designed Space Vector
PWM control IC has been simulated using a single FPGA from
Xilinx, inc. The output fundamental frequency can be varied Fig. 1. FPGA -DSP Based Control of digital ac drives
from 1.46 Hz to 1.5 kHz and the PWM switching frequency
can be set from 195 Hz to 49.92 kHz. The delay time of PWM
output is programmable and the SVPWM control IC is generation and the execution of current control loop algorithms
reprogrammable. [3]-[5][8]. Only a limited time is left to control other functions of
the drive. Even though another such DSP can be employed to
Key wods Sae ecoPMCVDLadPG.implement the special functions, the design procedure will be
complicated and requires long time to develop hardware and
I. INTRODUCTION control software and also the system is not compact. Therefore, in
recent years, motor control and power conversion ICs employing
The nprdictd dvelomen in ndutria drves ASICIFPGA technology are receiving more attention [6]-[10] and
over the past two decades [1] [2] is resulted from the process AnCFPGA-aedhPWM cro scemenfor acrestis shown in
developments demanded by the automation industry. This is Fan FPGA-based
PWM control scheme for ac drives is shown in
f moern Fig. Fig.2. Dynamic and ever progressing developments in
furter agmened wth icreaed seed
land
furtheroaugmente
microprocessors, pmcro withoionrolleasedit
conroollers, digit sp signall profPrcsorn the rapid prototyping ofradically
m
o
VLSI Technology affected the
have digital systems. design
FPGA is aprocess and
new PLD
(DP) cope prganal logi deie (CPD) developed by Xilinx, Inc. with a maximum number of
application specific integrated circuit (ASIC) technology configurablebyinput/output blocks of 1200 and a speed of 550 MHz
deeoe Xiix n.wt aiu ubro
app felcaio andspecificmainegrated
ielproramablegat aray (AC)basd
circut(PGA tsedchntroloy
cntrlin virtex-5 family devices. The FPGA comprises of thousands of
techniques used in reduced insulated gate bipolar transistor
(IGBT) drive package size coupled with ac motors leads to logic gates,
the main blocks are configurable logic block (CLB)
achievement of multiple machine configuration with and inputFPGA output blocks (JOB).
minimal processdowntime. In the conventionaldrives,The based SVPWM based control of three phase
mnionimaliprocuessdontim veolloop con n tioWMgenealtdriv the induction motor drive shown in Fig. 2 has current loop control,
imlikem uentedwithan
functions control.lo and hMkind
geneiontare and voltage and speed regulation is based on the switching patterns
hasti animplementged
has
wt
advantage of good aoodnalog icntreol.nise
dynamic ouffctrobby pae"FG bsdSacVctrPM
response but suffers the target induction machine parameters are considered. This
onolIfrthe
the~~~ ~ drwak liecmlxt,lmte .ucin n h paper "FPGA based Space Vector PWM control IC for three
thedrawbacksy
difcut inys
ike compeictyim u phase Induction motor Drive"
cirui moediicantion in driveshasbecome scheme for the Space Vector PWM control IC employing a single
is a novel digital circuit realization
ac

theinownsearday DP bseahduntrolthe insfintensive

acdrieshasime FPGA from Xilinx, Inc. The designed SVPWM control IC can be
araoeerhdeused either for ac motor drives or three-phase ac voltage
circuitry, software .'
control and flexibility to adapt various
. ~~~~~~~~~~~~reg_ulationsystems. The pa-per rest of the paper is org_anized as
applications Hoevr . PW geeainadcurn
.oto follows: Section II describes space vector PWM concepts. Section
loo reuirshghampingrat toachevewid badwith III describes the design of FPGA based SVPWM IC, Architecture
performance. Thrfr,ms.opttoa eore and its components. Section IV gives the simulation results and
of the controller must be utilized for PWM gating signal scinVi h ocuin

1-4244-0726-5/06/$20.OO '2006 IEEE 2061

 U n~ ,UDCexL3
=U eXP j(n -1)Xt for n= 1,2,....6 (7)
1 | 5;1 39 ^
S5 9 // Xwhere,
UDC is the DC link voltage
UDC U1 to U6 are active vectors and
S 1 | 54 s SS S2 ;UO = U7= 0 are null vectors.

FPGiA halsed SVPWM coi itlol iliterfa ce( wil Wl|

Mlicroprocessor 1 DSP
U0(l 1 1) Ul(l 0 0) U2(1 1 0) U3(0 1 0)
Fig. 2. FPGA based SVPWM control

II. PRINCIPLE OF SPACE VECTOR PWM

The major purpose of the PWM inverter is to supply a
variable-voltage variable-frequency three-phase voltage to
the ac motor so that the resulting rotating magneto motive
force has minimum harmonic distortion [8].The Space
Vector Pulse Width Modulation (SVPWM) [8],[11]-[13]
method is an advanced, computation intensive PWM
method and is probably the best among all the PWM
techniques in the aspects of harmonic distortion and dc bus
utilization.
The operating principle of the space vector PWM is
explained by representing the space vectors. The motor
stator voltage vector can be expressed as a combination of
the inverter output phase voltages Ua ,Ub and Uc, which can
be expressed in vector form as:
U4(0 1 1) U5(0 0 1 U6(1 01 17( 0 0)
Fig. 3. The switching configuration of a three phase PWM Inverter
The stator voltage vector can be decomposed into two
orthogonal components in a two-axis coordinate or as a
combination of two basic vectors as in Fig 4. The SVPWM
strategy aims to minimize harmonic distortion by selecting the
appropriate switching vectors and determining their
corresponding dwelling widths. If the reference vector is located
in sector I, then it is composed of voltage vector U1, U2 and zero
voltage vectors as illustrated in Fig.5. Since voltage vectors Ul,
U2 are the basic vectors and U0, U7 are zero vectors, this gives
Uref = U1 (T1 / T3 ) + U2 (T2/ T3) (8)

U s= Ua + Y2Ub + yUC (1) where Tland T2 are the dwelling time for Uland U2 respectively.
where, This voltage space vector can be described in rectangular
. 2x coordinates as follows:
7y exp j
- (2)
(

(p 2 (3) UDC+T UDCcos+T2jV 4 UDC sinO

Ua Um sin (wt) (4) = j) ji)UDC-asO

Ub =Um sin (wot - 120) (5)
Uc Um sin(wot+ 120) (6)
Um is the amplitude of the fundamental component. The U3 U2
space vector Us rotates in a circular orbit at an angular II
velocity Cl and the direction of rotation depends on the \I
phase sequence of the voltages. U4 v_
A. Reference Vector and Converter switching states I VI U,

A three- phase bridge inverter has 8 permissible V /

switching states as Fig.3 depicts and their corresponding
voltage vectors are expressed as U5 U6
Fig. 4. Voltage vectors

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 U2 III. FPGA BASED SVPWM CONTROL IC
In practical ac drive applications, the current control, voltage
regulation and speed regulation are based on the SVPWM
switching patterns and, therefore, the PWM control circuit should
be compatible with a conventional microprocessors and needs a
Uref computer interface. The current control loop, voltage regulation
and motor parameters and its variation are to be implemented in
(T2/Ts)U2 the microcroprocessor, which has the flexibility implementing the
floating-point function. This paper describes only the design of
(T11T5)U1 U1 Space Vector PWM control IC for three phase induction motor
drives using Very high speed integrated circuit Hardware
Fig.5. Decomposition of voltage vectors in sector 1 Description Language (VHDL) and FPGA.
r
1IR rv v A. FPGA based SVPWM Control ICArchitecture
The programmable FPGA-based SVPWM control IC
architecture is shown in Fig.7. This IC consists of the command
registers for setting the frequency, amplitude, phase of the stator
voltage vector, the switching frequency and the delay time for the
power device [8],[14]. The internal structure of the designed
SVPWM IC consists of a sin-table address decoder, duty-ratio
calculator, 2 to 3- axis converters, PWM waveform generator,
- > Time programmable delay-time controller and a sector detector.
Fig. 6. Space Vector PWM pattern in 6 sectors The basic requirements for realizing the SVPWM scheme is to
first compute the orthogonal components of the voltage vector.
Second, these 2-axis orthogonal components are converted to 3-
where, UDC1S dc link voltage, axis components, and then these three-phase PWM waveforms are
arom "(9),"
From (9 converted to centralized encased PWM waveforms with minimal
switching. Finally, the PWM gating signals to the power switches

T7 =2= (Ts
(T 12).a.(sin(60-)I(sin ( 10) of the sametophase legtheof the inverter inserted with adjustable
areshort-circuiting.
/2) .a.( 0 ( 60)s
0 (1) time delay protect phase legs from
T7 =To = (Tg I2) - T2 - T (1 2) medlytprtcthpaslgsfosot-rutn.
B. Orthogonal Voltage Vectors
TABLE I The SVPWM IC receives a rotating voltage vector with
VOLTAGE VECTORS,SWITCHING VECTORS AND THE INVERTER amplitude and frequency. An internal sin/cos generator is used to
OUTPUT VOLTAGES produce PWM duty ratio. The command voltage vector is
Vol Switch ing Line to neutral decomposed into two orthogonal vectors U,(k) and Up(k) in the
-tage vectors voltage Line to line voltage stationary -axis, and then they are converted to corresponding
vectors b l- U Uab U 1caUc duty ratios d,(k) and dp(k).This duty ratio function is transformed
to 3 axes by 2 to 3-axis transformation using the relations[8], [14]
U0 a b c U U UIn0 U 0
U1 1 0 0 2/3 -1/3 -1/3 1 0 -1
d()d,()(3
U2 1/3 1/3 -2/3 0 1 -1 da(k)=d(k) (13)
U3 0 1 0 -1/3 2/3 -1/3 -1 I 0 db(k) = - 1/2 d (k) - 13 /2 d, (k) (14)
U4 0 1 1 -2/3 1/3 1/3 -1 0 1
U5 0 0 1 -1/3 -1/3 2/3 0 -1 1 dc(k) = - 1/2 dp (k) +13 /2 d, (k) (15)
U6 1 0 1 1/3 -2/3 1/3 1 -1 0
U7 1 T I 0 0 0 0 0 0 Digital implementation of "(14),"and "(15)," requires floating-
The equivalent PWM waveforms which produce the point arithmetic, which complicates the design procedure. This is
required average flux consist of various combinations of the implemented using integer approximations using basic adder,
basic vectors. Fig. 6. illustrates the PWM gating signals of subtractor and divider modules without affecting the resolution.
the SVPWM scheme in each operating section. Table-I
gives details of voltage vectors, switching vectors and the
corresponding output voltages.

2063
 PWM _ Freq_data Dead time

Phase data |l l
Generator | tDP, Pi
Pt-
l da ,
Delaytime
. Pl-~d
P2
Freqdata |Orthogonal p

duty converter db DGenerator

U - mag-data
generator
Xq p
dc ,
Generator
P_
tP2
l P3+
Tj P3~~~~~~~~~~~~~~3
Rattio T2 >.*P
Calculator *

Fig. 7. FPGA based SVPWM control IC Architecture

C. Two Axis - 3 Phase Voltage Converter maximum turn-off time. The output signals ta, tb, t, and td decide
The duty ratio function is transformed to 3 axes da(k), the switching pattern for positive, negative legs respectively. The
db(k) and dc(k) by 2- 3 axis transformation. An integer relationships of the gating signal are as follows:
approximation is implemented [8] for the value +13 /2 in
"(14),"and "(15),". For analysis, a 20 kHz PWM switching T
signal with switching period of 50pts is considered. An 8-bit
resolution of the PWM signal indicates a control clock
period of around 0.2 hts. This period is usually much shorter
than the turn-off time of the PWM switches for motor drives T * ta A
and is acceptable in most applications. T 1 tb
D. Duty Ratio Controller and PWM Generator T
Ts Ts _
The duty ratios, T1 and T2 decide turn-on and turn-off_
time of the power device and for every switching cycle they
are updated continuously based on the feedback. L
The three-phase duty ratios da(k), db(k) and dc(k) are ' tc
routed to the optimal PWM generator. This SVPWM Ton
generator produces PWM waveforms with minimum ,AT td AT
switching and the same duty-ratio equivalence. There are
two zero vectors U0 and U7 in the basic switching vectors. Fig 8. PWM waveforms with delay time
However, only one of them with the longer dwelling time Ts-Ton
should be used during one switching period. Determining ta = (16)
the proper zero vector depends on the duration of its 2
dwelling time. The one with the longer dwelling time is t Ts+Ton (17)
selected. 2
E. Programmable Delay Time Generator Ts-(Ton + AT)
The phase legs of the inverter have to be protected from tc = 2(18)2
short circuit. Therefore, a programmable delay-time
controller is introduced in the designed SVPWM IC as Fig.8 td T + (Ton + AT) (19)
depicts. The turn-off time of power devices is usually longer 2
than its turn-on time, and, therefore, an appropriate delay where, AT is the specified programmable delay time.
time must be inserted between these two gating signals. The The delay-time controller generates the gating signals with the
length of this delay time is usually about 1.5 to 2 times the specified time delay.

2064
F. Macro source code B. Simulation Results
The SVPWM control IC has internal modules of 2 axis to
3 phase converter, sin/cos generator, orthogonal duty ratio
generator, sector detection, PWM generator and OsIIIiII4ldIldilt [1 ihII4IIIIIS I
programmable delay time generator. The source code for "2 J_
-axis to 3-phase voltage" converter module is given B SANGIE6(h& 32
8 EADTfI E7 (hf1JU4
appendix - I. B r7~ (bex46 23
BVP7(chX)*8
h 23
IV. RESULTS IS _SUPIDT 22C
8 DAY7 (hfe)48 15
The control scheme is simple in architecture and thus B flX7 *8
facilitates the realization of the developed SVPWM B IY7. (hx) #8 DC
B VAH23U
B V4TESA,3 (he
(e O4g7
A
controller using FPGA based circuit design approach. The
designed SVPWM control IC has been realized using a P 7......
single FPGA (SPARTON).The implementation report is FU52
HUMEr
shown in Table-Il and the internal chip view is shown in P SE -
Fig. 9. Space Vector PWM switching pattern has been ---E
achieved for different switching frequencies varying
between 222 Hz and 40 kHz with a fundamental frequency
of 50 Hz. Results for fs = 222 Hz, fs = 20 kHz and fs = 40
kHz with a fundamental frequency of 50 Hz are shown Fig. Fig. 10. a. SVPWM IC output waveforms for fs = 222 Hz and f= 50z
10a, l0b and l0c respectively. Such a wide frequency
control with very high frequency-switching is only possible 1 11iL11 m.III IIIIIIIId
by utilizing the state-of-art VLSI digital circuit design _
approach. From the result the switching pattern generated BAN GLE 6
P DEADTIXE
xhk(ho 04
1
will reduce the harmonic content and switching losses. BS7 (h) 2L _2_ _
A. Implementation report AX I JS <1T 28ME
Target Device family,Device SPARTAN ,XS20TQ14 EBEl DAY7 (i8ex 2U06
DER7, (hix)tg
TABLE II ( )00 DiC
IMPLEMENTATION REPORT
1B V3ETA 23 11XD61DÆ
Parts Size |NISEI.
6
Number of CLBs 296/ 400, 74% a PUISE2 fi:771
Number of bonded IOBs 39 /113, 34%
CLB 4 input LUTs 523 PUI4.
CLB 3 input LUTs 50 777
Target Speed 3
Total equivalent gate count for design 3699
Maximum net delay 15.316 ns
Maximum combinational path delay 152.271 ns Fig. 10. b. SVPWM IC output waveforms for fs = 20kHz and f= 50 Hz

i. iCL~~~U
C-. C4

E
B ALE6
b 2
B DEADTIE 7(he0

1TS7~ (h 13 4

CLB- Configurable logic block I/O pad'

Fig . 9. SVPWM IC Internal Chip view Fig. 10.c. SVPWM output waveforms for fs = 40 kHz and f = 50 Hz

2065
 V. CONCLUSION APPENDIX - I
The designed Space Vector PWM control IC for A. The source code for "2 - axis to 3-phase voltage"
induction motor drive has been simulated using a single converter module:
FPGA. The output fundamental frequency can be varied
from 1.46 Hz to 1.5 kHz and the PWM switching frequency libraryieee;
can be set from 195 Hz to 49.92 kHz. The delay time of useieee.stdjogicj 164.all;
PWM output is programmable. The designed SVPWM use ieee.stdjlogic-unsigned.all;
control IC is reprogrammable. The switching pattern use ieee.stdjlogic_arith.all;
generated will reduce the harmonic content, provides entity axis2_vc3phase is
efficient as well flexible control and reduces the total size of port (cosk,mak,sink: in std_logic_vector(7 downto 0);
the system. This SVPWM IC can be used for high dbk_in,dak_in in stdjlogic_vector(15 downto 0);
performance ac drives and power conditioning equipment as dak_out,dbk_out,dck_out: out stdjlogic-vector(7 downto 0));
a modulator. end axis2_vc3phase;
AcKNOWLEDGEMENT
architecture ax_arch of axis2_vc3phase is
The authors would like to thank the Management of component mul8 is
Kumaraguru College of Technology, Coimbatore, Tamil port(A: in std_logic_vector(7 downto 0);
Nadu and Jawaharlal Nehru Technological and University B: in std_logic-vector(7 downto 0);
(JNTU), Hyderabad, Andra Pradesh, India for providing all mulout: out stdjlogic-vector(15 downto 0));
infrastructural facilities during this work. end component;
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component divide2_4_8 is
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