. (a).Design and simulate the Verilog code for 1-bit adder and subtractor usingModelsim.(b).

Implement full adder in

FPGA kit and obtain the synthesis report and RTLschematic.
 
2. Design and simulate the Verilog code for 1-bit adder using Modelsim.Usestructural modeling to simulate Verilog code
for 4 bit ripple carry adder.Obtain the RTL schematic respectively.
 
3. (a).Design and simulate 8 input to single output Multiplexer using Modelsim.(b).Implement 4X1 Multiplexer in FPGA
kit.
 
4. (a).Design and simulate Verilog code for binary to Gray code Converter usingModelsim.Create RTL schematic for the
same.(b).Implement half adder in FPGA kit.
 
5.(a) Design and simulate Verilog code for octal to binary encoder usingModelsim.Create RTL schematic for the same.
(b).Implement half Subtractor in FPGA kit.
 
6. (a)Design and implement the verilog code for eight input priority encoder usingSimulation and synthesis tool.(b)
Simulate the verilog code for JK and D Flip flops.
 
7.(a) Design and implement the verilog code for odd parity generator usingSimulation and synthesis tool.(b) Simulate
the verilog code for SR and T Flip flops.
 
8.(a) Design and implement the verilog code for even parity generator usingSimulation and synthesis tool.(b) Simulate
the verilog code for T and D Flip flops.9.(a). Design and simulate 8 input to single output Multiplexer using Modelsim.
(b). Implement Half subtractor in FPGA kit
 
10.(a).Simulate and synthesize the verilog code for 4 bit binary up down counterusing behavioral modeling and create
RTL Schematic for the same.(b).Implement half subtractor in FPGA kit.
 
11.(a). Simulate and synthesize the verilog code for 4 bit binary up down counterusing behavioral modeling and create
RTL Schematic for the same.(b).Implement 4X1 Multiplexer in FPGA kit.
 
12.(a).Design and simulate the verilog code for pipelined serial adder to add eight 12bit signed numbers.Create RTL
schematic for the same.(b). Implement half adder in FPGA kit.
 
13.(a) Design and simulate the verilog code for pipelined parallel adder to add eight12 bit signed numbers.Create RTL
schematic for the same.(b)Implement half adder in FPGA kit.
 
14. Design and simulate the verilog code for multiplying two signed binary numbersusing Modelsim and create RTL
Schematic for the same.
 
15. Design and simulate the verilog code to obtain the behavioral simulation of thetraffic light controller for the road
conditions specified:Allow Traffic in Road A, B,C for 25 seconds with a delay of 5 seconds in each roadConditions
respectively and Create RTL schematic for the same.
 
16.(a).Design and simulate the verilog code for eight input priority encoder usingSimulation tool.(b).Implement full
adder in FPGA kit.
 
17.(a). Design and simulate the verilog code for SR, JK, D & T Flip-flop usingSimulation tool.(b).Implement half adder in
FPGA kit.