FIFO
ADC PROCESSING
P15 TO P0
NTSC/PAL/SECAM autodetection AIN1 AA
BLOCK
FILTER
MUX BLOCK
AIN2 2D COMB
8-bit ITU-R BT.656 YCrCb 4:2:2 output and HS, VS, and FIELD 1
OUTPUT BLOCK
VS
AIN3 AA SHA A/D HS
FILTER
1.0 V analog input signal range AIN41 VBI SLICER
FIELD3
AIN51 AA
Full-featured VBI data slicer with teletext support (WST) AIN61
FILTER COLOR
DEMOD
GPO5
SFL
Power-down mode and ultralow sleep mode current
INTRQ
2-wire serial MPU interface (I2C compatible) REFERENCE I2C/CONTROL
1.8 V analog, 1.8 V PLL, 1.8 V digital, 1.8 to 3.3 V I/O supply SCLK SDATA ALSB RESET PWRDWN4
05700-001
1 ONLY AVAILABLE ON 64-LEAD PACKAGE.
−10°C to +70°C commercial temperature grade 2 16-BIT ONLY AVAILABLE ON 64-LEAD PACKAGE.
3 40-LEAD AND 32-LEAD PACKAGE USES ONE LEAD FOR VS/FIELD.
−40°C to +85°C industrial temperature grade 4 NOT AVAILABLE ON 32-LEAD PACKAGE.
5 ONLY AVAILABLE ON 64-LEAD PACKAGE.
−40°C to +125°C temperature grade for automotive qualified
(AEC-Q100 test methods), 64-lead and 40-lead devices Figure 1.
3 package types
1
The 40-lead and 32-lead LFCSP use one pin to output VS or FIELD.
64-lead, 10 mm × 10 mm, RoHS-compliant LQFP
40-lead, 6 mm × 6 mm, RoHS-compliant LFCSP
32-lead, 5 mm × 5 mm, RoHS-compliant LFCSP
GENERAL DESCRIPTION
The ADV7180 automatically detects and converts standard wide range of consumer video sources. AGC and clamp-restore
analog baseband television signals compatible with worldwide circuitry allow an input video signal peak-to-peak range to 1.0 V.
NTSC, PAL, and SECAM standards into 4:2:2 component video Alternatively, these can be bypassed for manual settings.
data compatible with the 8-bit ITU-R BT.656 interface standard. The line-locked clock output allows the output data rate, timing
The simple digital output interface connects gluelessly to a wide signals, and output clock signals to be synchronous, asynchronous,
range of MPEG encoders, codecs, mobile video processors, and or line locked even with ±5% line length variation. Output control
Analog Devices, Inc., digital video encoders, such as the ADV7179. signals allow glueless interface connections in many applications.
External HS, VS, and FIELD signals provide timing references The ADV7180 is programmed via a 2-wire, serial bidirectional
for LCD controllers and other video ASICs, if required. Accurate port (I2C® compatible) and is fabricated in a 1.8 V CMOS process.
10-bit analog-to-digital conversion provides professional quality Its monolithic CMOS construction ensures greater functionality
video performance for consumer applications with true 8-bit with lower power dissipation. LFCSP package options make the
data resolution. Three analog video input channels accept standard decoder ideal for space-constrained portable applications. The
composite, S-Video, or component video signals, supporting a LQFP package is pin compatible with the ADV7181C.
Rev.E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com
Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2006-2010 Analog Devices, Inc. All rights reserved.
ADV7180
TABLE OF CONTENTS
Features .............................................................................................. 1 SD Chroma Path ......................................................................... 22
Applications ....................................................................................... 1 Sync Processing .......................................................................... 23
Functional Block Diagram .............................................................. 1 VBI Data Recovery..................................................................... 23
General Description ......................................................................... 1 General Setup .............................................................................. 23
Revision History ............................................................................... 3 Color Controls ............................................................................ 25
Introduction ...................................................................................... 4 Clamp Operation........................................................................ 27
Analog Front End ......................................................................... 4 Luma Filter .................................................................................. 28
Standard Definition Processor ................................................... 4 Chroma Filter.............................................................................. 31
Functional Block Diagrams ............................................................. 5 Gain Operation ........................................................................... 32
Specifications..................................................................................... 6 Chroma Transient Improvement (CTI) .................................. 36
Electrical Characteristics ............................................................. 6 Digital Noise Reduction (DNR) and Luma Peaking Filter ... 37
Video Specifications ..................................................................... 7 Comb Filters ................................................................................ 38
Timing Specifications .................................................................. 8 IF Filter Compensation ............................................................. 40
Analog Specifications ................................................................... 8 AV Code Insertion and Controls ............................................. 41
Thermal Specifications ................................................................ 9 Synchronization Output Signals............................................... 43
Timing Diagrams.......................................................................... 9 Sync Processing .......................................................................... 49
Absolute Maximum Ratings.......................................................... 10 VBI Data Decode ....................................................................... 50
ESD Caution ................................................................................ 10 I2C Readback Registers .............................................................. 59
Pin Configurations and Function Descriptions ......................... 11 Pixel Port Configuration ............................................................... 72
40-Lead LFCSP ........................................................................... 11 GPO Control ................................................................................... 73
64-Lead LQFP ............................................................................. 12 MPU Port Description ................................................................... 74
32-Lead LFCSP ........................................................................... 14 Register Access............................................................................ 75
Analog Front End ........................................................................... 15 Register Programming............................................................... 75
Input Configuration ................................................................... 16 I2C Sequencer .............................................................................. 75
Power-On RESET ...................................................................... 17 I2C Register Maps ........................................................................... 76
Analog Input Muxing ................................................................ 17 I2C Programming Examples........................................................ 103
Antialiasing Filters ..................................................................... 18 64-Lead LQFP ........................................................................... 103
Global Control Registers ............................................................... 19 40-Lead and 32-Lead LFCSP .................................................. 104
Power-Saving Modes .................................................................. 19 PCB Layout Recommendations.................................................. 105
Reset Control .............................................................................. 19 Analog Interface Inputs ........................................................... 105
Global Pin Control ..................................................................... 19 Power Supply Decoupling ....................................................... 105
Global Status Register .................................................................... 21 PLL ............................................................................................. 105
Identification ............................................................................... 21 VREFN and VREFP ................................................................. 105
Status 1 ......................................................................................... 21 Digital Outputs (Both Data and Clocks) .............................. 105
Autodetection Result.................................................................. 21 Digital Inputs ............................................................................ 105
Status 2 ......................................................................................... 21 Typical Circuit Connection ......................................................... 106
Status 3 ......................................................................................... 21 Outline Dimensions ..................................................................... 109
Video Processor .............................................................................. 22 Ordering Guide ........................................................................ 110
SD Luma Path ............................................................................. 22
INTRODUCTION
The ADV7180 is a versatile one-chip multiformat video decoder is performed downstream by digital fine clamping within the
that automatically detects and converts PAL, NTSC, and ADV7180.
SECAM standards in the form of composite, S-Video, and Table 2 shows the three ADC clocking rates that are determined by
component video into a digital ITU-R BT.656 format. the video input format to be processed—that is, INSEL[3:0].
The simple digital output interface connects gluelessly to a wide These clock rates ensure 4× oversampling per channel for CVBS
range of MPEG encoders, codecs, mobile video processors, and mode and 2× oversampling per channel for Y/C and YPrPb modes.
Analog Devices digital video encoders, such as the ADV7179.
External HS, VS, and FIELD signals provide timing references Table 2. ADC Clock Rates
for LCD controllers and other video ASICs that do not support Oversampling
the ITU-R BT.656 interface standard. Below is a table intro- Input Format ADC Clock Rate (MHz)1 Rate per Channel
ducing the many different package options available for the CVBS 57.27 4×
ADV7180. Y/C (S-Video)2 86 2×
YPrPb 86 2×
1
Table 1. ADV7180 Selection Guide 2
Based on a 28.6363 MHz crystal between the XTAL and XTAL1 pins.
See INSEL[3:0] in Table 106 for the mandatory write for Y/C (S-Video) mode.
Package Analog Digital Temp
Part Number Type Inputs Outputs Grade STANDARD DEFINITION PROCESSOR
ADV7180KCP32Z 32-lead 3 8-bit −10°C The ADV7180 is capable of decoding a large selection of
LFCSP to baseband video signals in composite, S-Video, and component
+70°C
formats. The video standards supported by the video processor
ADV7180WBCP32Z 32-lead 3 8-bit −40°C
include PAL B/D/I/G/H, PAL 60, PAL M, PAL N, PAL Nc, NTSC
(Automotive)1 LFCSP to
+85°C M/J, NTSC 4.43, and SECAM B/D/G/K/L. The ADV7180 can
ADV7180BCPZ 40-lead 3 8-bit −40°C automatically detect the video standard and process it accordingly.
LFCSP to The ADV7180 has a five-line, superadaptive, 2D comb filter
+85°C
that gives superior chrominance and luminance separation
ADV7180WBCPZ 40-lead 3 8-bit −40°C
when decoding a composite video signal. This highly adaptive filter
(Automotive)2 LFCSP to
+125°C automatically adjusts its processing mode according to the video
ADV7180BSTZ 64-lead 6 8-/16-bit −40°C standard and signal quality without requiring user intervention.
LQFP to Video user controls such as brightness, contrast, saturation, and
+85°C hue are also available with the ADV7180.
ADV7180WBSTZ 64-lead 6 8-/16-bit −40°C The ADV7180 implements a patented ADLLT™ algorithm to
(Automotive)2 LQFP to
+125°C track varying video line lengths from sources such as a VCR.
1
Automotive qualification (AEC-Q100 test methods) will be completed to
ADLLT enables the ADV7180 to track and decode poor quality
temperature range −40°C to +85°C. video sources such as VCRs and noisy sources from tuner outputs,
2
Automotive qualification (AEC-Q100 test methods) completed to VCD players, and camcorders. The ADV7180 contains a chroma
temperature range −40°C to +125°C.
transient improvement (CTI) processor that sharpens the edge
ANALOG FRONT END rate of chroma transitions, resulting in sharper vertical transitions.
The ADV7180 analog front end comprises a single high speed, The video processor can process a variety of VBI data services,
10-bit, analog-to-digital converter (ADC) that digitizes the such as closed captioning (CCAP), wide screen signaling (WSS),
analog video signal before applying it to the standard definition copy generation management system (CGMS), EDTV, Gemstar®
processor. The analog front end employs differential channels to 1×/2×, and extended data service (XDS). Teletext data slicing
the ADC to ensure high performance in mixed-signal applications. for world standard teletext (WST), along with program delivery
The front end also includes a 3-channel input mux that enables control (PDC) and video programming service (VPS), are
multiple composite video signals to be applied to the ADV7180. provided. Data is transmitted via the 8-bit video output port as
Current clamps are positioned in front of the ADC to ensure ancillary data packets (ANC). The ADV7180 is fully Macrovision®
that the video signal remains within the range of the converter. certified; detection circuitry enables Type I, Type II, and Type III
A resistor divider network is required before each analog input protection levels to be identified and reported to the user. The
channel to ensure that the input signal is kept within the range decoder is also fully robust to all Macrovision signal inputs.
of the ADC (see Figure 25). Fine clamping of the video signal
16-BIT
DIGITAL PIXEL DATA
10-BIT, 86MHz
FIFO
ADC PROCESSING
BLOCK P15 TO P0
AIN1 AA
FILTER
MUX BLOCK
AIN2 2D COMB
OUTPUT BLOCK
ANALOG HS
AIN3 AA
VIDEO SHA A/D VS
INPUTS AIN4 FILTER VBI SLICER
FIELD
AIN5 AA
FILTER COLOR GPO0 TO GPO3
AIN6 DEMOD
SFL
INTRQ
REFERENCE I2C/CONTROL
05700-003
SCLK SDATA ALSB RESET PWRDWN
8-BIT
DIGITAL PIXEL DATA
10-BIT, 86MHz
FIFO
ADC PROCESSING
BLOCK P7 TO P0
AA
FILTER
MUX BLOCK
AIN1
2D COMB
ANALOG
AA OUTPUT BLOCK HS
VIDEO AIN2 SHA A/D
INPUTS FILTER VBI SLICER
VS/FIELD
AIN3 AA
FILTER COLOR
DEMOD
SFL
INTRQ
REFERENCE I2C/CONTROL
05700-004
8-BIT
DIGITAL PIXEL DATA
10-BIT, 86MHz
FIFO
ADC PROCESSING
BLOCK P7 TO P0
AA
FILTER
MUX BLOCK
AIN1
2D COMB
OUTPUT BLOCK
ANALOG HS
VIDEO AA
AIN2 SHA A/D
INPUTS FILTER VBI SLICER
VS/FIELD
AIN3 AA
FILTER COLOR
DEMOD
SFL
INTRQ
REFERENCE I2C/CONTROL
05700-055
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
AVDD = 1.71 V to 1.89 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 1.62 V to 3.6 V, PVDD = 1.65 V to 2.0 V, specified at operating temperature range,
unless otherwise noted.
Table 3.
Parameter Symbol Test Conditions Min Typ Max Unit
STATIC PERFORMANCE
Resolution (Each ADC) N 10 Bits
Integral Nonlinearity INL BSL in CVBS mode 2 LSB
Differential Nonlinearity DNL CVBS mode −0.6/+0.6 LSB
DIGITAL INPUTS
Input High Voltage (DVDDIO =3.3 V) VIH 2 V
Input High Voltage (DVDDIO =1.8 V) VIH 1.2 V
Input Low Voltage (DVDDIO =3.3 V) VIL 0.8 V
Input Low Voltage (DVDDIO =1.8 V) VIL 0.4 V
Crystal Inputs VIH 1.2 V
VIL 0.4 V
Input Current IIN –10 +10 μA
Input Capacitance CIN 10 pF
DIGITAL OUTPUTS
Output High Voltage (DVDDIO = 3.3 V) VOH ISOURCE = 0.4 mA 2.4 V
Output High Voltage (DVDDIO = 1.8 V) VOH ISOURCE = 0.4 mA 1.4 V
Output Low Voltage (DVDDIO =3.3 V) VOL ISINK = 3.2 mA 0.4 V
Output Low Voltage (DVDDIO =1.8 V) VOL ISINK = 1.6 mA 0.2 V
High Impedance Leakage Current ILEAK 10 μA
Output Capacitance COUT 20 pF
POWER REQUIREMENTS 1, 2, 3
Digital Power Supply DVDD 1.65 1.8 2 V
Digital I/O Power Supply DVDDIO 1.62 3.3 3.6 V
PLL Power Supply PVDD 1.65 1.8 2.0 V
Analog Power Supply AVDD 1.71 1.8 1.89 V
Digital Supply Current IDVDD 77 85 mA
Digital I/O Supply Current 4 IDVDDIO 3 5 mA
PLL Supply Current IPVDD 12 15 mA
Analog Supply Current IAVDD CVBS input 33 43 mA
Y/C input 59 75 mA
YPrPb input 77 94 mA
Power-Down Current IDVDD 6 10 μA
IDVDDIO 0.1 1 μA
IPVDD 1 5 μA
IAVDD 1 5 μA
Total Power Dissipation in Power-Down Mode 5 15 44 μW
Power-Up Time tPWRUP 20 ms
1
Guaranteed by characterization.
2
Typical current consumption values are recorded with nominal voltage supply levels and a SMPTEBAR pattern.
3
Maximum current consumption values are recorded with maximum rated voltage supply levels and a multiburst pattern.
4
Typical (Typ) number is measured with DVDDIO = 3.3 V; maximum (Max) number is measured with DVDDIO = 3.6 V.
5
ADV7180 clocked.
Table 4.
Parameter Symbol Test Conditions Min Typ Max Unit
NONLINEAR SPECIFICATIONS
Differential Phase DP CVBS input, modulate five-step [NTSC] 0.6 Degrees
Differential Gain DG CVBS input, modulate five-step [NTSC] 0.5 %
Luma Nonlinearity LNL CVBS input, five-step [NTSC] 2.0 %
NOISE SPECIFICATIONS
SNR Unweighted Luma ramp 57.1 dB
Luma flat field 58 dB
Analog Front-End Crosstalk 60 dB
LOCK TIME SPECIFICATIONS
Horizontal Lock Range –5 +5 %
Vertical Lock Range 40 70 Hz
fSC Subcarrier Lock Range ±1.3 kHz
Color Lock-In Time 60 Lines
Sync Depth Range 20 200 %
Color Burst Range 5 200 %
Vertical Lock Time 2 Fields
Autodetection Switch Speed 100 Lines
Chroma Luma Gain Delay CVBS 2.9 ns
Y/C 5.6 ns
YPrPb −3.0 ns
LUMA SPECIFICATIONS
Luma Brightness Accuracy CVBS, 1 V input 1 %
Luma Contrast Accuracy CVBS, 1 V input 1 %
Table 5.
Parameter Symbol Test Conditions Min Typ Max Unit
SYSTEM CLOCK AND CRYSTAL
Nominal Frequency 28.6363 MHz
Frequency Stability ±50 ppm
I2C PORT
SCLK Frequency 400 kHz
SCLK Minimum Pulse Width High t1 0.6 μs
SCLK Minimum Pulse Width Low t2 1.3 μs
Hold Time (Start Condition) t3 0.6 μs
Setup Time (Start Condition) t4 0.6 μs
SDA Setup Time t5 100 ns
SCLK and SDA Rise Times t6 300 ns
SCLK and SDA Fall Times t7 300 ns
Setup Time for Stop Condition t8 0.6 μs
RESET FEATURE
Reset Pulse Width 5 ms
CLOCK OUTPUTS
LLC Mark Space Ratio t9:t10 45:55 55:45 % duty cycle
DATA AND CONTROL OUTPUTS
Data Output Transitional Time t11 Negative clock edge to start of valid data 3.6 ns
(tACCESS = t10 − t11)
Data Output Transitional Time t12 End of valid data to negative clock edge 2.4 ns
(tHOLD = t9 + t12)
ANALOG SPECIFICATIONS
Guaranteed by characterization. AVDD = 1.71 V to 1.89 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 1.62 V to 3.6 V, PVDD = 1.65 V to 2.0 V, specified
at operating temperature range, unless otherwise noted.
Table 6.
Parameter Test Conditions Min Typ Max Unit
CLAMP CIRCUITRY
External Clamp Capacitor 0.1 μF
Input Impedance Clamps switched off 10 MΩ
Large-Clamp Source Current 0.4 mA
Large-Clamp Sink Current 0.4 mA
Fine Clamp Source Current 10 μA
Fine Clamp Sink Current 10 μA
THERMAL SPECIFICATIONS
Table 7.
Parameter Symbol Test Conditions Min Typ Max Unit
THERMAL CHARACTERISTICS
Junction-to-Ambient Thermal θJA 4-layer PCB with solid ground plane, 32-lead LFCSP 32.5 °C/W
Resistance (Still Air)
Junction-to-Case Thermal Resistance θJC 4-layer PCB with solid ground plane, 32-lead LFCSP 2.3 °C/W
Junction-to-Ambient Thermal θJA 4-layer PCB with solid ground plane, 40-lead LFCSP 30 °C/W
Resistance (Still Air)
Junction-to-Case Thermal Resistance θJC 4-layer PCB with solid ground plane, 40-lead LFCSP 3 °C/W
Junction-to-Ambient Thermal θJA 4-layer PCB with solid ground plane, 64-lead LQFP 47 °C/W
Resistance (Still Air)
Junction-to-Case Thermal Resistance θJC 4-layer PCB with solid ground plane, 64-lead LQFP 11.1 °C/W
TIMING DIAGRAMS
t3 t5 t3
SDATA
t6 t1
SCLK
05700-005
t2 t7 t4 t8
2
Figure 5. I C Timing
t9 t10
OUTPUT LLC
t11
t12
OUTPUTS P0 TO P15, VS,
HS, FIELD, 05700-006
SFL
VS/FIELD
RESET
SDATA
INTRQ
DGND
DGND
DVDD
SCLK
ALSB
HS
32
31
40
39
38
37
36
35
34
33
DVDDIO 1 PIN 1 30 AIN3
SFL 2 INDICATOR 29 AIN2
DGND 3 28 AGND
DVDDIO 4 ADV7180 27 AVDD
P7 5 26 VREFN
P6 6 LFCSP 25 VREFP
TOP VIEW
P5 7 (Not to Scale) 24 AGND
P4 8 23 AIN1
P3 9 22 TEST_0
P2 10 21 AGND
11
12
13
14
15
16
17
18
19
20
LLC
XTAL
ELPF
XTAL1
P1
P0
PWRDWN
DGND
PVDD
DVDD
05700-007
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED TO GND.
RESET
SDATA
FIELD
DGND
DVDD
GPO2
GPO3
SCLK
ALSB
AIN6
P12
P13
P14
P15
NC
VS
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
INTRQ 1 48 AIN5
PIN 1
HS 2 47 AIN4
DGND 3 46 AIN3
DVDDIO 4 45 NC
P11 5 44 NC
P10 6 43 AGND
ADV7180
P9 7
LQFP
42 NC
P8 8 TOP VIEW 41 NC
(Not to Scale)
SFL 9 40 AVDD
DGND 10 39 VREFN
DVDDIO 11 38 VREFP
GPO1 12 37 AGND
GPO0 13 36 AIN2
P7 14 35 AIN1
P6 15 34 TEST_0
P5 16 33 NC
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
LLC
XTAL
ELPF
P4
P3
P2
XTAL1
P1
P0
PWRDWN
DGND
NC
NC
PVDD
AGND
DVDD
05700-008
NC = NO CONNECT
VS/FIELD
SDATA
RESET
INTRQ
DGND
DVDD
SCLK
ALSB
32
31
30
29
28
27
26
25
PIN1
HS 1 INDICATOR
24 AIN3
DGND 2 23 AIN2
DVDDIO 3 22 AVDD
SFL 4 ADV7180
21 VREFN
P7 5 LFCSP
TOP VIEW 20 VREFP
P6 6 (Not to Scale) 19 AIN1
P5 7 18 PVDD
P4 8 17 ELPF
9
10
11
12
13
14
15
16
LLC
XTAL1
P3
P2
P1
P0
XTAL
DVDD
05700-057
NOTES
1. THE EXPOSEDPAD MUST BE CONNECTEDTO GND.
AIN2
AIN1
AIN4
AIN3
AIN6
AIN5
AIN2
AIN1 MUX_0[2:0]
AIN4
AIN3
AIN6
AIN5
AIN4
AIN3
AIN6 MUX_1[2:0]
AIN5
ADC
AIN6
AIN5 MUX_2[2:0]
05700-009
Figure 10. 64-Lead LQFP Internal Pin Connections
MAN_MUX_EN
AIN1
AIN2
AIN3
AIN1 MUX_0[2:0]
AIN2
AIN3
AIN2
AIN3
MUX_1[2:0]
ADC
AIN3 MUX_2[2:0]
05700-010
1
Not available in 32-pin part
Table 14. Manual Mux Settings for the ADC (MAN_MUX_EN Must be Set to 1)
ADC Connected To ADC Connected To ADC Connected To
MUX0[2:0] LQFP-64 LFCSP-40 MUX1[2:0] LQFP-64 LFCSP-40 MUX2[2:0] LQFP-64 LFCSP-40
LFCSP-32 LFCSP-32 LFCSP-32
000 No connect No connect 000 No connect No connect 000 No connect No connect
001 AIN1 AIN1 001 No connect No connect 001 No connect No connect
010 AIN2 No connect 010 No connect No connect 010 AIN2 No connect
011 AIN3 No connect 011 AIN3 No connect 011 No connect No connect
100 AIN4 AIN2 100 AIN4 AIN2 100 No connect No connect
101 AIN5 AIN3 101 AIN5 AIN3 101 AIN5 AIN3
110 AIN6 No connect 110 AIN6 No connect 110 AIN6 No connect
111 No connect No connect 111 No connect No connect 111 No connect No connect
–12
MAGNITUDE (dB)
10-BIT, 86MHz
ADC
AIN1 –16
AA
FILTER 1 –20
AIN2
MUX BLOCK
AIN3 –24
AA
FILTER 2 SHA A/D
AIN41 –28
05700-013
AIN51 –32
AA
FILTER 3
–36
AIN61 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
05700-012
05700-014
and is routed directly to the ADC. –140
–150
AA_FILT_EN, Address 0xF3[0] 1k 10k 100k 1M 10M 100M
When PDBP is 0 (default), the digital supply power is controlled by When the reset bit is 1, the reset sequence starts.
the PWRDWN pin2 (the PWRDWN bit, 0x0F[5], is disregarded). GLOBAL PIN CONTROL
When PDBP is 1, the PWRDWN bit has priority (the pin is Three-State Output Drivers
disregarded). TOD, Address 0x03[6]
PWRDWN, Address 0x0F[5] This bit allows the user to three-state the output drivers of the
When PDBP is set to 1, setting the PWRDWN bit switches the ADV7180.
ADV7180 to a chip-wide power-down mode. The power-down Upon setting the TOD bit, the P15 to P0 (P7 to P0 for the 40-lead
stops the clock from entering the digital section of the chip, and 32-lead devices), HS, VS, FIELD (VS/FIELD pin for the
thereby freezing its operation. No I2C bits are lost during power- 40-lead and 32-lead LFCSP), and SFL pins are three-stated.
down. The PWRDWN bit also affects the analog blocks and
The timing pins (HS, VS, FIELD) can be forced active via the
switches them into low current modes. The I2C interface is
TIM_OE bit. For more information on three-state control, see
unaffected and remains operational in power-down mode.
the Three-State LLC Driver and the Timing Signals Output
The ADV7180 leaves the power-down state if the PWRDWN bit is Enable sections.
set to 0 (via I2C) or if the ADV7180 is reset using the RESET pin.
Individual drive strength controls are provided via the
PDBP must be set to 1 for the PWRDWN bit to power down DR_STR_X bits.
the ADV7180. When TOD is 0 (default), the output drivers are enabled.
When PWRDWN is 0 (default), the chip is operational. When TOD is 1, the output drivers are three-stated.
When PWRDWN is 1, the ADV7180 is in a chip-wide power-
down mode. Three-State LLC Driver
TRI_LLC, Address 0x1D[7]
RESET CONTROL
This bit allows the output drivers for the LLC pin of the
Reset, Chip Reset, Address 0x0F[7]
ADV7180 to be three-stated. For more information on three-
Setting this bit, which is equivalent to controlling the RESET state control, refer to the Three-State Output Drivers and the
pin on the ADV7180, issues a full chip reset. All I2C registers Timing Signals Output Enable sections.
are reset to their default/power-up values. Note that some
Individual drive strength controls are provided via the
register bits do not have a reset value specified. They keep their
DR_STR_X bits.
last written value. Those bits are marked as having a reset value
of x in the register tables (see Table 106 and Table 107). After When TRI_LLC is 0 (default), the LLC pin drivers work
the reset sequence, the part immediately starts to acquire the according to the DR_STR_C[1:0] setting (pin enabled).
incoming video signal. When TRI_LLC is 1, the LLC pin drivers are three-stated.
1
For 32-lead, I2C is the only PWRDWN option.
2
For 64-lead and 40-lead only.
VIDEO PROCESSOR
STANDARD DEFINITION PROCESSOR
DIGITIZED CVBS
DIGITIZED Y (YC) LUMA LUMA
DIGITAL LUMA LUMA LUMA
FILTER GAIN RESAMPLE 2D COMB
FINE CONTROL
CLAMP
LINE AV
SYNC LENGTH RESAMPLE CODE VIDEO DATA
EXTRACT PREDICTOR CONTROL INSERTION OUTPUT
DIGITIZED CVBS
DIGITIZED C (YC) CHROMA
DIGITAL CHROMA CHROMA CHROMA CHROMA CHROMA MEASUREMENT
FINE DEMOD FILTER GAIN RESAMPLE 2D COMB BLOCK (≥ I2C)
CLAMP CONTROL
VIDEO DATA
PROCESSING
BLOCK
fSC
RECOVERY
05700-015
Figure 16. Block Diagram of the Video Processor
Figure 16 shows a block diagram of the ADV7180 video processor. SD CHROMA PATH
The ADV7180 can handle standard definition video in CVBS, The input signal is processed by the following blocks:
Y/C, and YPrPb formats. It can be divided into a luminance and
chrominance path. If the input video is of a composite type • Chroma digital fine clamp. This block uses a high precision
(CVBS), both processing paths are fed with the CVBS input. algorithm to clamp the video signal.
• Chroma demodulation. This block employs a color
SD LUMA PATH subcarrier (fSC) recovery unit to regenerate the color
The input signal is processed by the following blocks: subcarrier for any modulated chroma scheme. The
• Luma digital fine clamp. This block uses a high precision demodulation block then performs an AM demodulation
algorithm to clamp the video signal. for PAL and NTSC,and an FM demodulation for SECAM.
• Luma filter. This block contains a luma decimation filter • Chroma filter. This block contains a chroma decimation
(YAA) with a fixed response and some shaping filters filter (CAA) with a fixed response and some shaping filters
(YSH) that have selectable responses. (CSH) that have selectable responses.
• Luma gain control. The automatic gain control (AGC) can • Chroma gain control. AGC can operate on several different
operate on a variety of different modes, including gain modes, including gain based on the color subcarrier
based on the depth of the horizontal sync pulse, peak white amplitude, gain based on the depth of the horizontal sync
mode, and fixed manual gain. pulse on the luma channel, or fixed manual gain.
• Luma resample. To correct for line length errors as well as • Chroma resample. The chroma data is digitally resampled
dynamic line length changes, the data is digitally resampled. to keep it perfectly aligned with the luma data. The
• Luma 2D comb. The 2D comb filter provides Y/C separation. resampling is done to correct for static and dynamic line
length errors of the incoming video signal.
• AV code insertion. At this point, the decoded luma (Y)
signal is merged with the retrieved chroma values. AV • Chroma 2D comb. The 2D, five-line, superadaptive comb
codes can be inserted (as per ITU-R BT.656). filter provides high quality Y/C separation in case the input
signal is CVBS.
• AV code insertion. At this point, the demodulated chroma
(Cr and Cb) signal is merged with the retrieved luma
values. AV codes can be inserted (as per ITU-R BT.656).
TIME_WIN 1
0
FREE_RUN 0 COUNTER INTO LOCK STATUS 1[0]
COUNTER OUT OF LOCK
1
fSC LOCK MEMORY STATUS 1[1]
05700-016
SRLS, Select Raw Lock Signal, Address 0x51[6] COL[2:0], Count Out of Lock, Address 0x51[5:3]
Using the SRLS bit, the user can choose between two sources for COL[2:0] determines the number of consecutive lines for which
determining the lock status (per Bits[1:0] in the Status 1 register). the out-of-lock condition must be true before the system switches
See Figure 17. into the unlocked state and reports this via Status 1[1:0]. It counts
the value in lines of video.
• The TIME_WIN signal is based on a line-to-line evaluation
of the horizontal synchronization pulse of the incoming Table 25. COL Function
video. It reacts quite quickly. COL[2:0] Number of Video Lines
• The FREE_RUN signal evaluates the properties of the 000 1
incoming video over several fields, taking vertical 001 2
synchronization information into account. 010 5
Setting SRLS to 0 (default) selects the FREE_RUN signal. 011 10
100 (default) 100
Setting SRLS to 1 selects the TIME_WIN signal.
101 500
FSCLE, fSC Lock Enable, Address 0x51[7] 110 1000
The FSCLE bit allows the user to choose whether the status of 111 100,000
the color subcarrier loop is taken into account when the overall
COLOR CONTROLS
lock status is determined and presented via Bits[1:0] in the
Status 1 register. This bit must be set to 0 when operating the These registers allow the user to control picture appearance,
ADV7180 in YPrPb component mode to generate a reliable including control of the active data in the event of video being
HLOCK status bit. lost. These controls are independent of any other controls. For
instance, brightness control is independent of picture clamping,
When FSCLE is set to 0 (default), only the overall lock status is although both controls affect the dc level of the signal.
dependent on horizontal sync lock.
CON[7:0], Contrast Adjust, Address 0x08[7:0]
When FSCLE is set to 1, the overall lock status is dependent on
horizontal sync lock and FSC lock. This register allows the user to control contrast adjustment of
the picture.
CIL[2:0], Count Into Lock, Address 0x51[2:0]
CIL[2:0] determines the number of consecutive lines for which Table 26. CON Function
the into lock condition must be true before the system switches CON[7:0] Description
into the locked state and reports this via Status 1[1:0]. The bit 0x80 (default) Gain on luma channel = 1
counts the value in lines of video. 0x00 Gain on luma channel = 0
0xFF Gain on luma channel = 2
Table 24. CIL Function
CIL[2:0] Number of Video Lines SD_SAT_Cb[7:0], SD Saturation Cb Channel,
000 1 Address 0xE3[7:0]
001 2 This register allows the user to control the gain of the Cb channel
010 5 only, which in turn adjusts the saturation of the picture.
011 10
100 (default) 100 Table 27. SD_SAT_Cb Function
101 500 SD_SAT_Cb[7:0] Description
110 1000 0x80 (default) Gain on Cb channel = 0 dB
111 100,000 0x00 Gain on Cb channel = −42 dB
0xFF Gain on Cb channel = +6 dB
ANALOG DATA
VIDEO PROCESSOR
VIDEO PRE-
ADC WITH DIGITAL
INPUT PROCESSOR
FINE CLAMP
(DPP)
05700-017
CLAMP CONTROL
The decisions of the control logic are shown in Figure 19. When WYSFMOVR is 0, the shaping filter for good quality
video signals is selected automatically.
Setting WYSFMOVR to 1 (default) enables manual override via
WYSFM[4:0].
SET YSFM
VIDEO
QUALITY
BAD GOOD
USE YSFM SELECTED
FILTER REGARDLESS OF
VIDEO QUALITY
AUTO SELECT LUMA
SHAPING FILTER TO
COMPLEMENT COMB WYSFMOVR
1 0
SELECT WIDEBAND
05700-018
SELECT AUTOMATIC
FILTER AS PER WIDEBAND FILTER
WYSFM[4:0]
–40
WYSFM[4:0], Wideband Y Shaping Filter Mode,
Address 0x18[4:0] –50
The WYSFM[4:0] bits allow the user to manually select a shaping –60
05700-019
filter for good quality video signals, for example, CVBS with
stable time base, luma component of YPrPb, and luma component –70
0 2 4 6 8 10 12
of Y/C. The WYSFM bits are active only if the WYSFMOVR bit FREQUENCY (MHz)
is set to 1. See the general discussion of the shaping filter settings in Figure 20. Y SVHS Combined Responses
the Y Shaping Filter section.
COMBINED Y ANTIALIAS, CCIR MODE SHAPING FILTER, COMBINED Y ANTIALIAS, NTSC NOTCH FILTERS,
Y RESAMPLE Y RESAMPLE
0
0
–20 –10
–20
AMPLITUDE (dB)
AMPLITUDE (dB)
–40
–30
–60
–40
–80
–50
–100
–60
05700-022
05700-020
–120 –70
0 2 4 6 8 10 12 0 2 4 6 8 10 12
FREQUENCY (MHz) FREQUENCY (MHz)
Figure 21. Combined Y Antialias, CCIR Mode Shaping Filter Figure 23. Combined Y Antialias Filter, NTSC Notch Filters
–10 –10
ATTENUATION (dB)
–20 –20
AMPLITUDE (dB)
–30
–30
–40
–40
–50
–50
–60
05700-023
05700-021
–70 –60
0 2 4 6 8 10 12 0 1 2 3 4 5 6
FREQUENCY (MHz) FREQUENCY (MHz)
Figure 22. Combined Y Antialias, PAL Notch Filters Figure 24. Chroma Shaping Filter Responses
05700-024
39Ω
Table 36. CSFM Function
CSFM[2:0] Description Figure 25. Input Voltage Divider Network
000 (default) Autoselection 1.5 MHz bandwidth
The minimum supported amplitude of the input video is
001 Autoselection 2.17 MHz bandwidth
determined by the ability of the ADV7180 to retrieve horizontal
010 SH1
and vertical timing and to lock to the color burst, if present.
011 SH2
100 SH3 There are separate gain control units for luma and chroma data.
101 SH4 Both can operate independently of each other. The chroma unit,
110 SH5 however, can also take its gain value from the luma path.
111 Wideband mode The possible AGC modes are shown in Table 37.
Figure 24 shows the responses of SH1 (narrowest) to SH5 Table 37. AGC Modes
(widest) in addition to the wideband mode (shown in red). Input
GAIN OPERATION Video Type Luma Gain Chroma Gain
Any Manual gain luma Manual gain chroma
The gain control within the ADV7180 is done on a purely
CVBS Dependent on Dependent on color-burst
digital basis. The input ADC supports a 10-bit range mapped horizontal sync depth amplitude taken from
into a 1.0 V analog voltage range. Gain correction takes place luma path
after the digitization in the form of a digital multiplier. Peak white Dependent on color-burst
Advantages of this architecture over the commonly used amplitude taken from
luma path
programmable gain amplifier (PGA) before the ADC include
Y/C Dependent on Dependent on color-burst
the fact that the gain is now completely independent of supply, horizontal sync depth amplitude taken from
temperature, and process variations. luma path
As shown in Figure 26, the ADV7180 can decode a video signal Peak white Dependent on color-burst
as long as it fits into the ADC window. The components for this amplitude
are the amplitude of the input signal and the dc level it resides on. YPrPb Dependent on Taken from luma path
horizontal sync depth
The dc level is set by the clamping circuitry (see the Clamp
Operation section). It is possible to freeze the automatic gain control loops. This
If the amplitude of the analog video signal is too high, clipping causes the loops to stop updating and the AGC determined gain
may occur, resulting in visual artifacts. The analog input range at the time of the freeze to stay active until the loop is either
of the ADC, together with the clamp level, determines the unfrozen or the gain mode of operation is changed.
maximum supported amplitude of the video signal. The currently active gain from any of the modes can be read
back. Refer to the description of the dual-function manual gain
registers, LG[11:0] luma gain and CG[11:0] chroma gain, in the
Luma Gain and Chroma Gain sections.
ANALOG VOLTAGE
RANGE SUPPORTED BY ADC (1V RANGE FOR ADV7180)
MAXIMUM
VOLTAGE
VIDEO PROCESSOR
(GAIN SELECTION ONLY)
DATA PRE-
ADC PROCESSOR
(DPP)
GAIN
CONTROL
05700-025
MINIMUM CLAMP
VOLTAGE LEVEL
SHARPENED CHROMA
TRANSITION AT THE enabled via the CTI_EN bit, and the alpha blender must be
OUTPUT OF CTI
switched on via CTI_AB_EN.
Figure 27. CTI Luma/Chroma Transition
Sharp blending maximizes the effect of CTI on the picture but
The chroma transient improvement block examines the input video may also increase the visual impact of small amplitude, high
data. It detects transitions of chroma and can be programmed to frequency chroma noise.
create steeper chroma edges in an attempt to artificially restore
lost color bandwidth. The CTI block, however, operates only on Table 47. CTI_AB Function
edges above a certain threshold to ensure that noise is not CTI_AB[1:0] Description
emphasized. Care has also been taken to ensure that edge 00 Sharpest mixing between sharpened and
ringing and undesirable saturation or hue distortion are avoided. original chroma signal
01 Sharp mixing
Chroma transient improvements are needed primarily for
10 Smooth mixing
signals that have severe chroma bandwidth limitations. For
11 (default) Smoothest alpha blend function
those types of signals, it is strongly recommended to enable
the CTI block via CTI_EN.
CTI_C_TH[7:0], CTI Chroma Threshold, Address 0x4E[7:0]
CTI_EN, Chroma Transient Improvement Enable,
The CTI_C_TH[7:0] value is an unsigned, 8-bit number specifying
Address 0x4D[0]
how big the amplitude step in a chroma transition must be to be
Setting CTI_EN to 0 disables the CTI block. steepened by the CTI block. Programming a small value into this
Setting CTI_EN to 1 (default) enables the CTI block. register causes even smaller edges to be steepened by the CTI
block. Making CTI_C_TH[7:0] a large value causes the block to
improve large transitions only.
The default value for CTI_C_TH[7:0] is 0x08, indicating the
threshold for the chroma edges prior to CTI.
LUMA
DNR1 LUMA PEAKING DNR2 LUMA Table 50. PEAKING_GAIN[7:0] Function
SIGNAL FILTER OUTPUT
Setting Description
0x40 (Default) 0 dB response
05700-051
PEAKING GAIN USING BP FILTER
Figure 28. DNR and Peaking Block Diagram 15
05700-052
The DNR1 block is positioned before the luma peaking block.
–20
The DNR_TH[7:0] value is an unsigned, 8-bit number used to 0 1 2 3 4 5 6 7
determine the maximum edge that is interpreted as noise and, FREQUENCY (MHz)
therefore, blanked from the luma data. Programming a large Figure 29. Peaking Filter Responses
value into DNR_TH[7:0] causes the DNR block to interpret DNR_TH2[7:0], DNR Noise Threshold 2,
even large transients as noise and remove them. As a result, the Address 0xFC[7:0]
effect on the video data is more visible. Programming a small
value causes only small transients to be seen as noise and to be The DNR2 block is positioned after the luma peaking block
removed. and, therefore, affects the gained luma signal. It operates in the
same way as the DNR1 block, but there is an independent
Table 49. DNR_TH[7:0] Function threshold control, DNR_TH2[7:0], for this block. This value is
Setting Description an unsigned, 8-bit number used to determine the maximum
0x08 (Default) Threshold for maximum luma edges to be edge that is interpreted as noise and, therefore, blanked from
interpreted as noise the luma data. Programming a large value into DNR_TH2[7:0]
causes the DNR block to interpret even large transients as noise
and remove them. As a result, the effect on the video data is
more visible. Programming a small value causes only small
transients to be seen as noise and to be removed.
AMPLITUDE (dB)
observed on tuner outputs. Figure 30 and Figure 31 show IF
–2
filter compensation for NTSC and PAL, respectively.
–4
The options for this feature are as follows:
• Bypass mode –6
05700-053
–10
AMPLITUDE (dB)
0
–2
–4
–6
05700-054
–8
3.0 3.5 4.0 4.5 5.0 5.5 6.0
FREQUENCY (MHz)
SD_DUP_AV = 1 SD_DUP_AV = 0
LLC
PIXEL Cr Y FF 00 00 XY 80 10 80 10 80 10 FF 00 00 XY Cb Y Cr Y Cb Y Cr
BUS
ACTIVE
EAV H BLANK SAV ACTIVE VIDEO
VIDEO
HS
HSE[10:0] HSB[10:0]
4 LLC C D
D
E E
05700-028
VS/FIELD, Address 0x58[0] VSBHE, VS Begin Horizontal Position Even, Address 0x32[6]
This feature is used for the 40-lead LFCSP and 32-Lead LFCSP The VSBHO and VSBHE bits select the position within a line at
only. The polarity of this bit determines what signal appears on which the VS pin (not the bit in the AV code) becomes active.
the VS/FIELD pin. Some follow-on chips require the VS pin to only change state
when HS is high or low.
When this bit is set to 0 (default), the FIELD signal is output.
When VSBHE is 0 (default), the VS pin goes high in the middle
When this bit is set to 1, the VSYNC signal is output.
of a line of video (even field).
The 64-lead LQFP has dedicated FIELD and VSYNC pins.
When VSBHE is 1, the VS pin changes state at the start of a line
ADV encoder-compatible signals via the NEWAVMODE (even field).
register follow:
VSEHO, VS End Horizontal Position Odd, Address 0x33[7]
• PVS, PF
The VSEHO and VSEHE bits select the position within a line at
• HVSTIM which the VS pin (not the bit in the AV code) becomes active.
• VSBHO, VSBHE Some follow-on chips require the VS pin to change state only
• VSEHO, VSEHE when HS is high or low.
For NTSC control, When VSEHO is 0 (default), the VS pin goes low (inactive) in
• NVBEGDELO, NVBEGDELE, NVBEGSIGN, NVBEG[4:0] the middle of a line of video (odd field).
• NVENDDELO, NVENDDELE, NVENDSIGN, NVEND[4:0] When VSEHO is 1, the VS pin changes state at the start of a line
• NFTOGDELO, NFTOGDELE, NFTOGSIGN, NFTOG[4:0] (odd field).
For PAL control, VSEHE, VS End Horizontal Position Even, Address 0x33[6]
• PVBEGDELO, PVBEGDELE, PVBEGSIGN, PVBEG[4:0] The VSEHO and VSEHE bits select the position within a line at
which the VS pin (not the bit in the AV code) becomes active.
• PVENDDELO, PVENDDELE, PVENDSIGN, PVEND[4:0]
Some follow-on chips require the VS pin to only change state
• PFTOGDELO, PFTOGDELE, PFTOGSIGN, PFTOG[4:0]
when HS is high or low.
NEWAVMODE, New AV Mode, Address 0x31[4] When VSEHE is 0 (default), the VS pin goes low (inactive) in
When NEWAVMODE is 0, EAV/SAV codes are generated to the middle of a line of video (even field).
suit Analog Devices encoders. No adjustments are possible. When VSEHE is 1, the VS pin changes state at the start of a line
Setting NEWAVMODE to 1 (default) enables the manual position (even field).
of the VSYNC, FIELD, and AV codes using Register 0x32 to PVS, Polarity VS, Address 0x37[5]
Register 0x33 and Register 0xE5 to Register 0xEA. Default register
settings are CCIR656 compliant; see Figure 34 for NTSC and The polarity of the VS pin can be inverted using the PVS bit.
Figure 39 for PAL. For recommended manual user settings, see When PVS is 0 (default), VS is active high.
Table 64 and Figure 35 for NTSC and Table 65 and Figure 40 for When PVS is 1, VS is active low.
PAL.
Rev. E | Page 44 of 112
ADV7180
PF, Polarity FIELD, Address 0x37[3] Table 64. User Settings for NTSC (See Figure 35)
The polarity of the FIELD pin for the 64-lead LQFP part can be Register Register Name Write
inverted using the PF bit. 0x31 VS/FIELD Control 1 0x1A
The FIELD pin can be inverted using the PF bit. 0x32 VS/FIELD Control 2 0x81
0x33 VS/FIELD Control 3 0x84
When PF is 0 (default), FIELD is active high.
0x34 HS Position Control 1 0x00
When PF is 1, FIELD is active low. 0x35 HS Position Control 2 0x00
0x36 HS Position Control 3 0x7D
0x37 Polarity 0xA1
0xE5 NTSV V bit begin 0x41
0xE6 NTSC V bit end 0x84
0xE7 NTSC F bit toggle 0x06
FIELD 1
525 1 2 3 4 5 6 7 8 9 10 11 12 13 19 20 21 22
OUTPUT
VIDEO
F
NFTOG[4:0] = 0x03
FIELD 2
262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 283 284 285
OUTPUT
VIDEO
V
NVBEG[4:0] = 0x05 NVEND[4:0] = 0x04 1BT.656-4
REG 0x04, BIT 7 = 1
F
NFTOG[4:0] = 0x03
05700-029
1APPLIES IF NEWAVMODE = 0:
MUST BE MANUALLY SHIFTED IF NEWAVMODE = 1.
Figure 34. NTSC Default, ITU-R BT.656 (the Polarity of H, V, and F is Embedded in the Data)
FIELD 1
525 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 21 22
OUTPUT
VIDEO
HS
OUTPUT
VS
OUTPUT
FIELD 2
262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 284 285
OUTPUT
VIDEO
HS
OUTPUT
VS
OUTPUT
NVBEG[4:0] = 0x01 NVEND[4:0] = 0x04
05700-030
FIELD
OUTPUT
NFTOG[4:0] = 0x06
Figure 35. NTSC Typical VSYNC/FIELD Positions Using the Register Writes in Table 64
Rev. E | Page 45 of 112
ADV7180
For all NTSC/PAL VSYNC timing controls, both the V bit in
1 NVBEGSIGN 0 the AV code and the VSYNC signal on the VS pin are modified.
ODD FIELD?
YES NO NOT VALID FOR USER
PROGRAMMING
ODD FIELD?
YES NO
NVBEGDELO NVBEGDELE
1 0 0 1
NVENDDELO NVENDDELE
ADDITIONAL ADDITIONAL
DELAY BY DELAY BY 1 0 0 1
1 LINE 1 LINE
ADDITIONAL ADDITIONAL
DELAY BY DELAY BY
1 LINE 1 LINE
VSBHO VSBHE
1 0 0 1
VSEHO VSEHE
ADVANCE BY ADVANCE BY
0.5 LINE 0.5 LINE 1 0 0 1
ADVANCE BY ADVANCE BY
0.5 LINE 0.5 LINE
05700-031
VSYNC BEGIN
05700-032
VSYNC END
NVBEGDELO, NTSC VSYNC Begin Delay on Odd Field,
Address 0xE5[7] Figure 37. NTSC VSYNC End
When NVBEGDELO is 0 (default), there is no delay. NVENDDELO, NTSC VSYNC End Delay on Odd Field,
Setting NVBEGDELO to 1 delays VSYNC going high on an odd Address 0xE6[7]
field by a line relative to NVBEG. When NVENDDELO is 0 (default), there is no delay.
NVBEGDELE, NTSC VSYNC Begin Delay on Even Field, Setting NVENDDELO to 1 delays VSYNC from going low on
Address 0xE5[6] an odd field by a line relative to NVEND.
When NVBEGDELE is 0 (default), there is no delay. NVENDDELE, NTSC VSYNC End Delay on Even Field,
Setting NVBEGDELE to 1 delays VSYNC going high on an Address 0xE6[6]
even field by a line relative to NVBEG. When NVENDDELE is set to 0 (default), there is no delay.
NVBEGSIGN, NTSC VSYNC Begin Sign, Address 0xE5[5] Setting NVENDDELE to 1 delays VSYNC from going low on an
Setting NVBEGSIGN to 0 delays the start of VSYNC. Set for even field by a line relative to NVEND.
user manual programming. NVENDSIGN, NTSC VSYNC End Sign, Address 0xE6[5]
Setting NVBEGSIGN to 1 (default) advances the start of Setting NVENDSIGN to 0 (default) delays the end of VSYNC.
VSYNC (not recommended for user programming). Set for user manual programming.
NVBEG[4:0], NTSC VSYNC Begin, Address 0xE5[4:0] Setting NVENDSIGN to 1 advances the end of VSYNC (not
The default value of NVBEG is 00101, indicating the NTSC recommended for user programming).
VSYNC begin position.
05700-033
FIELD
TOGGLE
FIELD 1
V
PVBEG[4:0] = 0x05 PVEND[4:0] = 0x04
F
PFTOG[4:0] = 0x03
FIELD 2
310 311 312 313 314 315 316 317 318 319 320 321 322 335 336 337
OUTPUT
VIDEO
V
PVBEG[4:0] = 0x05 PVEND[4:0] = 0x04
05700-034
F
PFTOG[4:0] = 0x03
Figure 39. PAL Default, ITU-R BT.656 (the Polarity of H, V, and F Is Embedded in the Data)
HS
OUTPUT
VS
OUTPUT
310 311 312 313 314 315 316 317 318 319 320 321 322 323 336 337
OUTPUT
VIDEO
HS
OUTPUT
VS
OUTPUT
PVBEG[4:0] = 0x01 PVEND[4:0] = 0x04
FIELD
05700-035
OUTPUT
PFTOG[4:0] = 0x06
Figure 40. PAL Typical VS/FIELD Positions Using the Register Writes Shown in Table 65
Table 65. User Settings for PAL PVBEG[4:0], PAL VSYNC Begin, Address 0xE8[4:0]
Register Register Name Write The default value of PVBEG is 00101, indicating the PAL VSYNC
0x31 VS/FIELD Control 1 0x1A begin position. For all NTSC/PAL VSYNC timing controls, the
0x32 VS/FIELD Control 2 0x81 V bit in the AV code and the VSYNC signal on the VS pin are
0x33 VS/FIELD Control 3 0x84 modified.
0x34 HS Position Control 1 0x00
1 PVBEGSIGN 0
0x35 HS Position Control 2 0x00
0x36 HS Position Control 3 0x7D
ADVANCE BEGIN OF DELAY BEGIN OF
0x37 Polarity 0xA1 VSYNC BY PVBEG[4:0] VSYNC BY PVBEG[4:0]
0xE8 PAL V bit begin 0x41
0xE9 PAL V bit end 0x84 NOT VALID FOR USER
PROGRAMMING
0xEA PAL F bit toggle 0x06
ODD FIELD?
YES NO
1 PFTOGSIGN 0
05700-037
VSYNC END
ADVANCE TOGGLE OF DELAY TOGGLE OF
Figure 42. PAL VSYNC End FIELD BY PFTOG[4:0] FIELD BY PFTOG[4:0]
FIELD
(set for user manual programming). TOGGLE
Setting PVENDSIGN to 1 advances the end of VSYNC (not Figure 43. PAL F Toggle
recommended for user programming). SYNC PROCESSING
PVEND[4:0], PAL VSYNC End, Address 0xE9[4:0] The ADV7180 has two additional sync processing blocks that
The default value of PVEND is 10100, indicating the PAL postprocess the raw synchronization information extracted
VSYNC end position. from the digitized input video. If desired, the blocks can be
disabled via the following two I2C bits: ENHSPLL and
For all NTSC/PAL VSYNC timing controls, both the V bit in
ENVSPROC.
the AV code and the VSYNC signal on the VS pin are modified.
1
This mode does not fully comply with ITU-R BT.1364.
Table 76 shows the framing code and its valid length for VBI
Structure of VBI Words in the Ancillary Data Stream
data standards supported by VDP.
Each VBI data standard has been split into a clock-run-in
(CRI), a framing code (FC), and a number of data bytes (n).
Example
The data packet in the ancillary stream includes only the FC For teletext (B-WST), the framing code byte is 11100100 (0xE4),
and data bytes. Table 75 shows the format of VBI_WORD_x in with bits shown in the order of transmission. VBI_WORD_1 =
the ancillary data stream. 0x27, VBI_WORD_2 = 0x00, and VBI_WORD_3 = 0x00
translated into UDWs in the ancillary data stream for nibble
Table 75. Structure of VBI Data-Words in the Ancillary mode are as follows:
Stream
UDW5[5:2] = 0010
Ancillary Data
Byte Number Byte Type Description UDW6[5:2] = 0111
VBI_WORD_1 FC0 Framing Code[23:16] UDW7[5:2] = 0000 (undefined bits set to 0)
VBI_WORD_2 FC1 Framing Code[15:8]
VBI_WORD_3 FC2 Framing Code[7:0] UDW8[5:2] = 0000 (undefined bits set to 0)
VBI_WORD_4 DB1 First data byte UDW9[5:2] = 0000 (undefined bits set to 0)
… … … UDW10[5:2] = 0000 (undefined bits set to 0)
VBI_WORD_N + 3 DBn Last (nth) data byte
For byte mode,
VDP Framing Code UDW5[9:2] = 0010_0111
The length of the actual framing code depends on the VBI data
UDW6[9:2] = 0000_0000 (undefined bits set to 0)
standard. For uniformity, the length of the framing code reported
in the ancillary data stream is always 24 bits. For standards with UDW7[9:2] = 0000_0000 (undefined bits set to 0)
a smaller framing code length, the extra LSB bits are set to 0.
The valid length of the framing code can be decoded from the
VBI_DATA_STD bits available in ID0 (UDW 1). The framing
code is always reported in the inverse-transmission order.
VDP_VITC_MSK, Address 0x50[6], User Sub Map Setting VDP_VITC_CLR to 1 clears the VDP_VITC_Q bit.
VDP_CGMS_WSS_
VDP_CGMS_WSS_DATA_2 DATA_1[5:0]
0 1 2 3 4 5 6 7 0 1 2 3 4 5
RUN-IN START ACTIVE
SEQUENCE CODE VIDEO
11.0µs
38.4µs
05700-039
42.5µs
+100 IRE
VDP_CGMS_WSS_
REF VDP_CGMS_WSS_DATA_2 VDP_CGMS_WSS_DATA_1 DATA_0[3:0]
+70 IRE
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3
0 IRE
49.1µs ± 0.5µs
–40 IRE 11.2µs
05700-040
CRC SEQUENCE
2.235µs ± 20ns
7 CYCLES
OF 0.5035MHz
(CLOCK RUN-IN)
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
S
T P P
50 IRE A A A
R R R
T I I
T T
Y Y
05700-041
27.382µs 33.764µs
TO
05700-042
BIT 0, BIT 1 BIT 88, BIT 89
VITC WAVEFORM
To identify the data that should be made available in the I2C AUTO_DETECT_GS_TYPE, Address 0x61[4], User Sub Map
registers, the user must program I2C_GS_VPS_PDC_UTC[1:0] Setting AUTO_DETECT_GS_TYPE to 0 (default) disables the
(Register Address 0x9C, user sub map). autodetection of the Gemstar type.
I2C_GS_VPS_PDC_UTC[1:0] (VDP), Address 0x9C[7:6], Setting AUTO_DETECT_GS_TYPE to 1 enables the
User Sub Map autodetection of the Gemstar type.
Specifies which standard result is available for I2C readback. GS_DATA_TYPE, Address 0x78[5], User Sub Map, Read Only
GS_PDC_VPS_UTC_CLEAR, GS/PDC/VPS/UTC Clear, Identifies the decoded Gemstar data type.
Address 0x78[4], User Sub Map, Write Only, Self-Clearing When GS_DATA_TYPE is 0, Gemstar 1× mode is detected.
Setting GS_PDC_VPS_UTC_CLEAR to 1 reinitializes the Read two data bytes from 0x84.
GS/PDC/VPS/UTC data readback registers. When GS_DATA_TYPE is 1, Gemstar 2× mode is detected.
GS_PDC_VPS_UTC_AVL, GS/PDC/VPS/UTC Available, Read four data bytes from 0x84.
Address 0x78[4], User Sub Map, Read Only The Gemstar data that is available in the I2C register can be
When GS_PDC_VPS_UTC_AVL is 0, no GS, PDC, VPS, or from any line of the input video on which Gemstar was decoded.
UTC data was detected. To read the Gemstar data on a particular video line, the user
should use the manual configuration described in Table 69 and
When GS_PDC_VPS_UTC_AVL is 1, one GS, PDC, VPS, or
Table 70 and enable Gemstar decoding only on the required line.
UTC data was detected.
PDC/UTC
VDP_GS_VPS_PDC_UTC, Readback Registers,
Address 0x84 to Address 0x90 PDC and UTC are data transmitted through Teletext Packet 8/30
Format 2 (Magazine 8, Row 30, Design Code 2 or Design Code 3)
See Table 84 for information on the readback registers.
and Packet 8/30 Format 1 (Magazine 8, Row 30, Design Code 0
VPS or Design Code 1). Therefore, if PDC or UTC data is to be read
The VPS data bits are biphase decoded by the VDP. The through I2C, the corresponding teletext standard (WST or PAL
decoded data is available in both the ancillary stream and in the System B) should be decoded by VDP. The whole teletext
I2C readback registers. VPS decoded data is available in the decoded packet is output on the ancillary data stream. The user
VDP_GS_VPS_PDC_UTC_0 to VDP_VPS_PDC_UTC_12 can look for the magazine number, row number, and design
registers (Address 0x84 to Address 0x90, User Sub Map). The code and qualify the data as PDC, UTC, or neither of these.
GS_PDC_VPS_UTC_AVL bit is set if the user programmed If PDC/UTC packets are identified, Byte 0 to Byte 12 are updated
I2C_GS_VPS_PDC_UTC to 01, as explained in Table 83. to the VDP_GS_VPS_PDC_UTC_0 to VDP_VPS_PDC_UTC_12
Gemstar registers, and the GS_PDC_VPS_UTC_AVL bit is set. The full
packet data is also available in the ancillary data format.
The Gemstar-decoded data is made available in the ancillary
stream, and any one line of Gemstar is also available in the I2C Note that the data available in the I2C register depends on the
registers for evaluation purposes. To read Gemstar results status of the WST_PKT_DECODE_DISABLE bit (Bit 3,
through the I2C registers, the user must program Subaddress 0x60, user sub map).
I2C_GS_VPS_PDC_UTC to 00, as explained in Table 83.
05700-043
DATA OPTIONAL PADDING CHECK
00 FF FF DID SDID USER DATA
COUNT BYTES SUM
NTSC CCAP Data See the GDECEL[15:0], Gemstar Decoding Even Lines,
Half-byte output mode is selected by setting GDECAD to 0, and Address 0x48[7:0], Address 0x49[7:0] section and the
the full-byte mode is enabled by setting GDECAD to 1. See the GDECOL[15:0], Gemstar Decoding Odd Lines,
GDECAD, Gemstar Decode Ancillary Data Format, Address Address 0x4A[7:0], Address 0x4B[7:0] section.
0x4C[0] section. The data packet formats are shown in Table 91 GDECEL[15:0], Gemstar Decoding Even Lines,
and Table 92. Only closed caption data can be embedded in the Address 0x48[7:0], Address 0x49[7:0]
output data stream. The 16 bits of GDECEL[15:0] are interpreted as a collection of
NTSC closed caption data is sliced on Line 21 of even and odd 16 individual line decode enable signals. Each bit refers to a line
fields. The corresponding enable bit must be set high. See the of video in an even field. Setting the bit enables the decoder block
GDECAD, Gemstar Decode Ancillary Data Format, Address trying to find Gemstar or closed caption-compatible data on
0x4C[0] section and the GDECOL[15:0], Gemstar Decoding that particular line. Setting the bit to 0 prevents the decoder
Odd Lines, Address 0x4A[7:0], Address 0x4B[7:0] section. from trying to retrieve data. See Table 95 and Table 96.
PAL CCAP Data To retrieve closed caption data services on NTSC (Line 284),
Half-byte output mode is selected by setting GDECAD to 0, and GDECEL[11] must be set.
full-byte output mode is selected by setting GDECAD to 1. See To retrieve closed caption data services on PAL (Line 335),
the GDECAD, Gemstar Decode Ancillary Data Format, GDECEL[14] must be set.
Address 0x4C[0] section. Table 93 and Table 94 list the bytes of The default value of GDECEL[15:0] is 0x0000. This setting
the data packet. instructs the decoder not to attempt to decode Gemstar or
Only closed caption data can be embedded in the output data CCAP data from any line in the even field. The user should
stream. PAL closed caption data is sliced from Line 22 and only enable Gemstar slicing on lines where VBI data is expected.
Line 335. The corresponding enable bits must be set.
Rev. E | Page 69 of 112
ADV7180
Table 95. NTSC Line Enable Bits and Corresponding GDECAD, Gemstar Decode Ancillary Data Format,
Line Numbering Address 0x4C[0]
Line Number The decoded data from Gemstar-compatible transmissions or
Line[3:0] (ITU-R BT.470) Enable Bit Comment
closed caption-compatible transmissions is inserted into the
0 10 GDECOL[0] Gemstar
horizontal blanking period of the respective line of video. A
1 11 GDECOL[1] Gemstar
potential problem can arise if the retrieved data bytes have a
2 12 GDECOL[2] Gemstar
3 13 GDECOL[3] Gemstar value of 0x00 or 0xFF. In an ITU-R BT.656-compatible data
4 14 GDECOL[4] Gemstar stream, these values are reserved and used only to form a fixed
5 15 GDECOL[5] Gemstar preamble. The GDECAD bit allows the data to be inserted into
6 16 GDECOL[6] Gemstar the horizontal blanking period in two ways:
7 17 GDECOL[7] Gemstar
• Insert all data straight into the data stream, even the
8 18 GDECOL[8] Gemstar
reserved values of 0x00 and 0xFF, if they occur. This may
9 19 GDECOL[9] Gemstar
violate output data format specification ITU-R BT.1364.
10 20 GDECOL[10] Gemstar
11 21 GDECOL[11] Gemstar or • Split all data into nibbles and insert the half-bytes over
closed caption double the number of cycles in a 4-bit format.
12 22 GDECOL[12] Gemstar
When GDECAD is 0 (default), the data is split into half-bytes
13 23 GDECOL[13] Gemstar
14 24 GDECOL[14] Gemstar and inserted.
15 25 GDECOL[15] Gemstar When GDECAD is 1, the data is output straight into the data
0 273 (10) GDECEL[0] Gemstar stream in 8-bit format.
1 274 (11) GDECEL[1] Gemstar
2 275 (12) GDECEL[2] Gemstar Table 96. PAL Line Enable Bits and Line Numbering
3 276 (13) GDECEL[3] Gemstar Line Number
4 277 (14) GDECEL[4] Gemstar Line[3:0] (ITU-R BT.470) Enable Bit Comment
5 278 (15) GDECEL[5] Gemstar 12 8 GDECOL[0] Not valid
6 279 (16) GDECEL[6] Gemstar 13 9 GDECOL[1] Not valid
7 280 (17) GDECEL[7] Gemstar 14 10 GDECOL[2] Not valid
8 281 (18) GDECEL[8] Gemstar 15 11 GDECOL[3] Not valid
9 282 (19) GDECEL[9] Gemstar 0 12 GDECOL[4] Not valid
10 283 (20) GDECEL[10] Gemstar 1 13 GDECOL[5] Not valid
11 284 (21) GDECEL[11] Gemstar or 2 14 GDECOL[6] Not valid
closed caption 3 15 GDECOL[7] Not valid
12 285 (22) GDECEL[12] Gemstar 4 16 GDECOL[8] Not valid
13 286 (23) GDECEL[13] Gemstar 5 17 GDECOL[9] Not valid
14 287 (24) GDECEL[14] Gemstar 6 18 GDECOL[10] Not valid
15 288 (25) GDECEL[15] Gemstar 7 19 GDECOL[11] Not valid
8 20 GDECOL[12] Not valid
GDECOL[15:0], Gemstar Decoding Odd Lines,
9 21 GDECOL[13] Not valid
Address 0x4A[7:0], Address 0x4B[7:0] 10 22 GDECOL[14] Closed caption
The 16 bits of GDECOL[15:0] form a collection of 16 individual 11 23 GDECOL[15] Not valid
line decode enable signals. See Table 95 and Table 96. 12 321 (8) GDECEL[0] Not valid
13 322 (9) GDECEL[1] Not valid
To retrieve closed caption data services on NTSC (Line 21), 14 323 (10) GDECEL[2] Not valid
GDECOL[11] must be set. 15 324 (11) GDECEL[3] Not valid
To retrieve closed caption data services on PAL (Line 22), 0 325 (12) GDECEL[4] Not valid
GDECOL[14] must be set. 1 326 (13) GDECEL[5] Not valid
2 327 (14) GDECEL[6] Not valid
The default value of GDECOL[15:0] is 0x0000. This setting 3 328 (15) GDECEL[7] Not valid
instructs the decoder not to attempt to decode Gemstar or CCAP 4 329 (16) GDECEL[8] Not valid
data from any line in the odd field. The user should only enable 5 330 (17) GDECEL[9] Not valid
Gemstar slicing on lines where VBI data is expected. 6 331 (18) GDECEL[10] Not valid
7 332 (19) GDECEL[11] Not valid
8 333 (20) GDECEL[12] Not valid
9 334 (21) GDECEL[13] Not valid
10 335 (22) GDECEL[14] Closed caption
11 336 (23) GDECEL[15] Not valid
The ordering of components, for example, Cr vs. Cb for LLC_PAD_SEL[2:0] LLC Output Selection, Address
Channel A, Channel B, and Channel C can be changed. See 0x8F[6:4]
the SWPC, Swap Pixel Cr/Cb, Address 0x27[7] section. Table 99 The following I2C write allows the user to select between LLC
indicates the default positions for the Cr/Cb components. (nominally at 27 MHz) and LLC (nominally at 13.5 MHz).
OF_SEL[3:0], Output Format Selection, Address 0x03[5:2] The LLC signal is useful for LLC-compatible wide bus (16-bit)
The modes in which the ADV7180 pixel port can be configured output modes. See the OF_SEL[3:0], Output Format Selection,
are under the control of OF_SEL[3:0]. See Table 101 for details. Address 0x03[5:2] section for additional information. The LLC
signal and data on the data bus are synchronized. By default, the
The default LLC frequency output on the LLC pin is approxi-
rising edge of LLC/LLC is aligned with the Y data; the falling
mately 27 MHz. For modes that operate with a nominal data rate
edge occurs when the data bus holds C data. The polarity of the
of 13.5 MHz (0001, 0010), the clock frequency on the LLC pin
clock, and therefore the Y/C assignments to the clock edges, can
stays at the higher rate of 27 MHz. For information on outputting
be altered by using the polarity LLC pin.
the nominal 13.5 MHz clock on the LLC pin, see the
LLC_PAD_SEL[2:0] LLC Output Selection, Address 0x8F[6:4] When LLC_PAD_SEL is 000, the output is nominally 27 MHz
section. LLC on the LLC pin (default).
When LLC_PAD_SEL is 101, the output is nominally 13.5 MHz
LLC on the LLC pin.
GPO CONTROL
The 64-lead LQFP has four general-purpose outputs (GPO). Table 102. General-Purpose Output Truth Table
These outputs allow the user to control other devices in a
GPO_ENABLE GPO[3:0] GPO3 GPO2 GPO1 GPO0
system via the I2C port of the device.
0 XXXX1 Z Z Z Z
The 40-lead and 32-lead LFCSP do not have GPO pins. 1 0000 0 0 0 0
GPO_Enable, General-Purpose Output Enable, 1 0001 0 0 0 1
Address 0x59[4] 1 0010 0 0 1 0
1 0011 0 0 1 1
When GPO_Enable is set to 0, all GPO pins are three-stated. 1 0100 0 1 0 0
When GPO_Enable is set to 1, all GPO pins are in a driven 1 0101 0 1 0 1
state. The polarity output from each GPO is controlled by 1 0110 0 1 1 0
GPO[3:0] for the 64-lead LQFP. 1 0111 0 1 1 1
GPO[3:0], General-Purpose Outputs, Address 0x59[3:0] 1 1000 1 0 0 0
1 1001 1 0 0 1
Individual control of the four GPO ports is achieved using 1 1010 1 0 1 0
GPO[3:0]. 1 1011 1 0 1 1
GPO_Enable must be set to 1 for the GPO pins to become active. 1 1100 1 1 0 0
GPO[0] 1 1101 1 1 0 1
1 1110 1 1 1 0
When GPO[0] is set to 0, a Logic Level 0 is output from the 1 1111 1 1 1 1
GPO0 pin. 1
X indicates any value.
When GPO[0] is set to 1, a Logic Level 1 is output from the
GPO0 pin.
GPO[1]
When GPO[1] is set to 0, a Logic Level 0 is output from the
GPO1 pin.
When GPO[1] is set to 1, a Logic Level 1 is output from the
GPO1 pin.
GPO[2]
When GPO[2] is set to 0, a Logic Level 0 is output from the
GPO2 pin.
When GPO[2] is set to 1, a Logic Level 1 is output from the
GPO2 pin.
GPO[3]
When GPO[3] is set to 0, a Logic Level 0 is output from the
GPO3 pin.
When GPO[3] is set to 1, a Logic Level 1 is output from the
GPO3 pin.
SDATA
SCLK
05700-044
WRITE
SEQUENCE S SLAVE ADDR A(S) SUB ADDR A(S) DATA A(S) DATA A(S) P
LSB = 0 LSB = 1
READ
SEQUENCE S SLAVE ADDR A(S) SUB ADDR A(S) S SLAVE ADDR A(S) DATA A(M) DATA A(M) P
05700-045
1
This feature applies to the 40-lead and 32-lead LFCSP only because VS or FIELD is shared on a single pin.
2
This feature applies to the 64-lead LQFP only.
1
To access the registers listed in Table 105, SUB_USR_EN in Register Address 0x0E must be programmed to 1.
2
x in a reset value indicates do not care.
1
Shading indicates default values.
2
x indicates a bit that keeps the last written value.
1
x indicates a bit that keeps the last written value.
2
Shading indicates default values.
Figure 52. Recommended Power Supply Decoupling Adding a 30 Ω to 50 Ω series resistor can suppress reflections,
reduce EMI, and reduce the current spikes inside the ADV7180.
It is particularly important to maintain low noise and good
If series resistors are used, place them as close as possible to the
stability of PVDD. Careful attention must be paid to regulation,
ADV7180 pins. However, try not to add vias or extra length to
filtering, and decoupling. It is highly desirable to provide separate
the output trace to place the resistors closer.
regulated supplies for each of the analog circuitry groups (AVDD,
DVDD, DVDDIO, and PVDD). If possible, limit the capacitance that each of the digital outputs
drives to less than 15 pF. This can easily be accomplished by
Some graphic controllers use substantially different levels of
keeping traces short and by connecting the outputs to only one
power when active (during active picture time) and when idle
device. Loading the outputs with excessive capacitance increases
(during horizontal and vertical sync periods). This can result in
the current transients inside the ADV7180, creating more digital
a measurable change in the voltage supplied to the analog supply
noise on its power supplies.
regulator, which can in turn produce changes in the regulated
analog supply voltage. This can be mitigated by regulating the The 40-lead and 32-leadLFCSP have an exposed metal paddle
analog supply, or at least PVDD, from a different, cleaner power on the bottom of the package. This paddle must be soldered to
source, for example, from a 12 V supply. PCB ground for proper heat dissipation and for noise and
mechanical strength benefits.
Using a single ground plane for the entire board is also recom-
mended. This ground plane should have a space between the DIGITAL INPUTS
analog and digital sections of the PCB (see Figure 53). The digital inputs on the ADV7180 are designed to work with
ADV7180 1.8 V to 3.3 V signals and are not tolerant of 5 V signals. Extra
ANALOG DIGITAL components are needed if 5 V logic signals are required to be
SECTION SECTION
applied to the decoder.
05700-047
ANALOG_INPUT_2 0.1µF
AIN2
PVDD_1.8V
36Ω DVDDIO _3.3V
39Ω
DVDD_1.8V
0.1µF
AVDD_1.8V 10nF
ANALOG_INPUT_3 0.1µF
36
14
27
20
AIN3
1
4
P[0:7]
36Ω
39Ω
PVDD
DVDD
DVDD
AVDD
DVDDIO
DVDDIO
23
AIN1 AIN1
29
AIN2 AIN2 17 P0
P0
30 16 P1
AIN3 AIN3 P1
10 P2 YCrCb
P2 8-BIT
9 P3
P3 656 DATA
31 8 P4
RESET RESET P4
7 P5
P5
6 P6
KEEP VREFN AND VREFP CAPACITORS AS CLOSE AS P6
POSSIBLE TO THE ADV7180 AND ON THE SAME SIDE
ADV7180BCPZ P7
5 P7
OF THE PCB AS THE ADV7180. LFCSP–40
26
VREFN
0.1µF
25
VREFP
0.1µF
11
LLC LLC
38
LOCATE CLOSE TO, AND ON THE INTRQ INTRQ
SAME SIDE AS, THE ADV7180.
2
SFL SFL
13
XTAL 37
47pF VS/FIELD VS/FIELD
28.63636MHz 1MΩ 39
HS HS
12
XTAL1
47pF
DVDDIO
4kΩ
32
ALSB PVDD_1.8V
ALSB TIED HI ≥ I2C ADDRESS = 42h EXTERNAL
ALSB TIED LOW ≥ I2C ADDRESS = 40h LOOP FILTER
19 10nF
ELPF
18
POWER_DOWN PWRDWN
82nF
34
SCLK SCLK 1.69kΩ
TEST_0
DGND
DGND
DGND
DGND
AGND
AGND
AGND
33
SDA SDATA
KEEP CLOSE TO THE ADV7180 AND ON
THE SAME SIDE OF PCB AS THE ADV7180.
3
40
15
35
28
21
24
22
05700-048
11
23
58
40
31
4
ANALOG_INPUT_5
AVDD
PVDD
DVDD
DVDD
DVDDIO
DVDDIO
Cb 0.1µF 8-BIT 16-BIT
AIN5 35
AIN1 AIN1 26 P0 DATA BUS OUTPUT MODE OUTPUT MODE
36Ω P0
39Ω 36 25 P1 P[0:7] N/A CbCr
AIN2 AIN2 P1
19 P2 P[8:15] 656/601 YCbCr Y
P2
ANALOG_INPUT_6 46 18 P3
AIN3 AIN3 P3
YC_C 17 P4
0.1µF P4 P[8:15]
47 16 P5
AIN6 AIN4 AIN4 P5
15 P6
36Ω P6
39Ω 48 14 P7
AIN5 AIN5 P7
ADV7180BSTZ
49 LQFP–64 8 P8
AIN6 AIN6 P8
7 P9
P9
6 P10
P10
KEEP VREFN AND VREFP CAPACITORS AS CLOSE AS 5 P11
POSSIBLE TO THE ADV7180 AND ON THE SAME P11
62 P12
SIDE OF THE PCB AS THE ADV7180. P12
61 P13
P13
39 60 P14
VREFN P14
0.1µF 59 P15
P15
1
INTRQ INT
38
VREFP 55
GPO3 GPO3
0.1µF 56
GPO2 GPO2
12
GPO1 GPO1
13
22 GPO0 GPO0
XTAL
47pF 63
FIELD FIELD
28.63636MHz 1MΩ 64
VS VSYNC
21 2
XTAL1 HS HS
47pF
9
SFL SFL PVDD_1.8V
51 27, 28, 33, EXTERNAL
RESET RESET NC 41, 42, 44,
45, 50 LOOP FILTER
29
POWER_DOWN PWRDWN 10nF
30
ELPF
DVDDIO _3.3V
82nF
4kΩ
52 1.69kΩ
ALSB
TIE HI: I2C ADDRESS = 42 KEEP CLOSE TO THE ADV7180 AND ON
TIE LOW: I2C ADDRESS = 40 THE SAME SIDE OF PCB AS THE ADV7180.
20
33Ω LLC LLC
54
SCLK SCLK
TEST_0
DGND
DGND
DGND
DGND
AGND
AGND
AGND
53
SDA SDATA
33Ω
3
10
24
57
32
37
43
34
05700-049
NC = NO CONNECT
ANALOG_INPUT_2 0.1µF
AIN2
PVDD _1.8V
36Ω DVDDIO _3.3V
39Ω
DVDD _1.8V
0.1µF
AVDD_1.8V 10nF
ANALOG_INPUT_3 0.1µF
14
30
22
18
AIN3
3
P[0:7]
36Ω
39Ω
PVDD
DVDD
DVDD
AVDD
DVDDIO
19
AIN1 AIN1
23
AIN2 AIN2 16 P0
P0
24 15 P1
AIN3 AIN3 P1
10 P2 YCrCb
P2 8-BIT
9 P3
P3 656 DATA
25 8 P4
RESET RESET P4
7 P5
P5
6 P6
KEEP VREFN AND VREFP CAPACITORS AS CLOSE AS P6
POSSIBLE TO THE ADV7180 AND ON THE SAME SIDE
ADV7180KCP32Z P7
5 P7
OF THE PCB AS THE ADV7180. LFCSP–32
21
VREFN
0.1µF
20
VREFP
0.1µF
11
LLC LLC
32
LOCATE CLOSE TO, AND ON THE INTRQ INTRQ
SAME SIDE AS, THE ADV7180.
4
SFL SFL
13
XTAL 31
47pF VS/FIELD VS/FIELD
28.63636MHz 1MΩ 1
HS HS
12
XTAL1
47pF
DVDDIO
4kΩ
26
ALSB PVDD_1.8V
ALSB TIED HI ≥ I2C ADDRESS = 42h EXTERNAL
ALSB TIED LOW ≥ I2C ADDRESS = 40h LOOP FILTER
17 10nF
ELPF
82nF
28
SCLK SCLK 1.69kΩ
DGND
DGND
27
SDA SDATA
KEEP CLOSE TO THE ADV7180 AND ON
THE SAME SIDE OF PCB AS THE ADV7180.
2
29
05700-056
OUTLINE DIMENSIONS
6.00 0.60 MAX
BSC SQ
0.60 MAX PIN 1
INDICATOR
31 40
30 1
PIN 1 0.50
INDICATOR TOP 4.25
5.75 BSC EXPOSED
VIEW 4.10 SQ
BSC SQ PAD
(BOT TOM VIEW) 3.95
0.50
0.40 21 10
20 11
0.30
0.25 MIN
4.50
12° MAX 0.80 MAX REF
0.65 TYP
0.05 MAX FOR PROPER CONNECTION OF
0.02 NOM THE EXPOSED PAD, REFER TO
1.00 THE PIN CONFIGURATION AND
0.85 0.30 FUNCTION DESCRIPTIONS
0.80 0.23 0.20 REF COPLANARITY SECTION OF THIS DATA SHEET.
SEATING 0.08
PLANE 0.18
072108-A
COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2
12.20
0.75 12.00 SQ
0.60 1.60 11.80
0.45 MAX
64 49
1 48
PIN 1
10.20
TOP VIEW 10.00 SQ
(PINS DOWN)
9.80
1.45
0.20
1.40
0.09
1.35
7°
3.5°
0.15 16 33
0°
0.05 SEATING 17 32
PLANE 0.08
COPLANARITY VIEW A 0.27
0.50
BSC 0.22
VIEW A LEAD PITCH 0.17
ROTATED 90° CCW
051706-A
0.50
BSC *3.75
EXPOSED
PAD
3.60 SQ
3.55
17 8
16 9
0.50 0.25 MIN
TOP VIEW 0.40 BOTTOM VIEW
0.30 FOR PROPER CONNECTION OF
0.80 THE EXPOSED PAD, REFER TO
0.75 THE PIN CONFIGURATION AND
0.05 MAX FUNCTION DESCRIPTIONS
0.70 SECTION OF THIS DATA SHEET.
0.02 NOM
COPLANARITY
0.08
SEATING 0.20 REF
PLANE
02-05-2009-B
*COMPLIANT TO JEDEC STANDARDS MO-220-WHHD-5
WITH EXCEPTION TO EXPOSED PAD DIMENSION.
ORDERING GUIDE
Model 1 Temperature Range Package Description Package Option
ADV7180KCP32Z −10°C to +70°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-12
ADV7180KCP32Z-RL −10°C to +70°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-12
ADV7180BCPZ −40°C to +85°C 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-40-1
ADV7180BCPZ-REEL −40°C to +85°C 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-40-1
ADV7180BSTZ −40°C to +85°C 64-Lead Low Profile Quad Flat Package [LQFP] ST-64-2
ADV7180BSTZ-REEL −40°C to +85°C 64-Lead Low Profile Quad Flat Package [LQFP] ST-64-2
ADV7180WBCP32Z −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 2 CP-32-12
ADV7180WBCP32Z-RL −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]2 CP-32-12
ADV7180WBCPZ −40°C to +125°C 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 3 CP-40-1
ADV7180WBCPZ-REEL −40°C to +125°C 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]3 CP-40-1
ADV7180WBSTZ −40°C to +125°C 64-Lead Low Profile Quad Flat Package [LQFP]3 ST-64-2
ADV7180WBSTZ-REEL −40°C to +125°C 64-Lead Low Profile Quad Flat Package [LQFP]3 ST-64-2
EVAL-ADV7180LQEBZ Evaluation Board for the 64-Lead LQFP
EVAL-ADV7180LFEBZ Evaluation Board for the 40-Lead LFCSP
EVAL-ADV7180-32EBZ Evaluation Board for the 32-Lead LFCSP
1
Z = RoHS Compliant Part.
2
Automotive device, automotive qualification (AEC-Q100 test methods) planned but not completed to temperature range −40°C to +85°C.
3
Automotive device, automotive qualification (AEC-Q100 test methods) qualified.
The ADV7180W models are available with controlled manufacturing to support the quality and reliability requirements of automotive
applications. Note that these automotive models may have specifications that differ from the commercial models, and designers should
review the product Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in
automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to
obtain the specific automotive reliability reports for these models.
Note that the ADV7180 is a Pb-free, environmentally friendly product. It is manufactured using the most up-to-date materials and
processes. The coating on the leads of each device is 100% pure Sn electroplate. The device is suitable for Pb-free applications and can
withstand surface-mount soldering at up to 255°C (±5°C).
In addition, it is backward-compatible with conventional SnPb soldering processes. This means that the electroplated Sn coating can be
soldered with Sn/Pb solder pastes at conventional reflow temperatures of 220°C to 235°C.
NOTES
NOTES
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).