Part B Entrepreneurship
Unit 5 Entrepreneur 6 Hours
Meaning of Entrepreneur; Evolution of the Concept, Functions of an
Entrepreneur, Types of Entrepreneur, Intrapreneur .- an emerging Class,
Concept of Entrepreneurship – Evolution of Entrepreneurship, Development
of Entrepreneurship, Stages in entrepreneurial process, Role of entrepreneurs
in Economic Development, Entrepreneurship in India; Enterpreneurship – its
Barriers
6
DIGITAL SIGNAL PROCESSING
Unit 6 Small Scale Industry 7 Hours
Definition, Charatersitics: Need and rationale, Objective; Scope; role of SSI Sub Code : 06EC-52 IA Marks :25
in Economic Development. Advantages of SSI, Steps to staert an SSI – Hours /Week :04 Exam Hours :3
Government policy towards SSI; Different Policies of SSI; Government Total Hours :52 Exam Marks :100
support for SSI, during 5 year plans. Impact of Liberalization, Privatisation, PART A
Globalization on SSI. Effects of WTO/GATT supporting agencies of Unit 1 7 Hours
Government for SSI, Meaning and Nature of support, Objectives; Functions; Discrete Fourier Transforms (DFT): Frequency domain sampling and
Types of help, Ancillary Industry and Tiny Industry (Definition only). reconstruction of discrete time signals. DFT as a linear transformation, its
relationship with other transforms.
Unit 7 Institutional support 6 Hours
Different Schemes, TECKSOK, KIADB; KSSIDC; DIC Single Window Unit 2 6 Hours
agency; SISI, NSIC, SIDBI, KSFC. Properties of DFT, multiplication of two DFTs- the circular convolution,
additional DFT properties, use of DFT in linear filtering, overlap-save and
Unit 8 Preparation of Project 6 Hours overlap-add method.
Meaning of Project; Project Identification, Project Selection, Project Report,
Need and Significance of Report, Contents, formulation, Guidelines by Unit 3 8 Hours
Planning Commission for Project report, Network Analysis, Errors of Project Fast-Fourier-Transform(FFT) algorithms: Direct computation of DFT, need
Report, Project appraisal, Identification of Business Opportunities: Market for efficient computation of the DFT ( FFT algorithms).
feasibility study, Technical feasibility study, Financial feasibility study and
Social feasibility study. Unit 4 6 Hours
Radix-2 FFT algorithm for the computation of DFT and IDFT–decimation-
TEXT BOOKS: in-time and decimation-in-frequency algorithms. Goertzel algorithm, and
1. P. C. Tripathi, P.N. Reddy; Principles of Management, Tata chirp-z transform
McGraw Hill,
2. Vasant Desai, Dynamics of Entrepreneurial Development &
Management, Himalaya Pub. House, - ( PART B
3. Poornima M Charantimath, Entrepreneurship Development – Small Unit 5 6 Hours
Business Enterprises, Pearsion education – 2006 IIR filter design: Characteristics of commonly used analog filters –
Butterworth and Chebysheve filters., analog to analog frequency
REFERENCE BOOKS: transformations
1. Robert Lusier, Management Fundamentals – Concepts,
Applications, Skill Development, Thompson, Unit 6 6 Hours
2. S S Khanka, Entre[reneurship Development, S Chand & Co., FIR filter design: Introduction to FIR filters, design of FIR filters using -
3. Stephen Robbins, Management, Peasrson Eduncation/PHI, 17th Ed, Rectangular, Hamming, Bartlet and Kaiser windows, FIR filter design using
2003 frequency sampling technique
Unit 7 7 Hours
Design of IIR filters from analog filters (Butterworth and Chebyshev) -
impulse invariance method. Mapping of transfer functions: Approximation of
derivative (backward difference and bilinear transformation) method,
Matched z transforms, Verification for stability and linearity during mapping
7 8
Unit 8 6 Hours Unit 3: 6 Hours
.Implementation of discrete-time systems: Structures for IIR and FIR Single Side-Band Modulation (SSB): Quadrature carrier multiplexing,
systems-direct form I and direct form II systems, cascade, lattice and parallel Hilbert transform, properties of Hilbert transform, Pre-envelope, Canonical
realization. representation of band pass signals, Single side-band modulation, Frequency-
Domain description of SSB wave, Time-Domain description. Phase
TEXT BOOK: discrimination method for generating an SSB modulated wave, Time-Domain
1. Proakis & Monalakis, Digital signal processing – Principles description. Phase discrimination method for generating an SSB modulated
Algorithms & Applications, Pearson education, 4th Edition, New wave. Demodulation of SSB waves.
Delhi, 2007.
Unit 4: 6 Hours
Vestigial Side-Band Modulation ( VSB): Frequency – Domain description,
REFERENCE BOOKS:
Generation of VSB modulated wave, Time - Domain description, Envelop
1. Oppenheim & Schaffer, Discrete Time Signal Processing, PHI,
detection of VSB wave plus carrier, Comparison of amplitude modulation
2003.
techniques, Frequency translation, Frequency division multiplexing,
2. S. K. Mitra, Digital Signal Processing, Tata Mc-Graw Hill, 2nd
Application: Radio broadcasting, AM radio.
Edition, 2004.
3. Lee Tan: Digital signal processing, Elsivier publications, 2007
---------------------------------------------------------------------
PART B
Unit 5: 6 Hours
ANALOG COMMUNICATION
Angle Modulation (FM): Basic definitions, FM, narrow band FM, wide
band FM, transmission bandwidth of FM waves, generation of FM waves:
Sub Code : 06EC-53 IA Marks : 25
indirect FM and direct FM.
Hours /Week :04 Exam Hours :3
Total Hour : 52 Exam Marks :100 Unit 6: 6 Hours
Angle Modulation (FM): Demodulation of FM waves, FM stereo
PART A multiplexing, Phase-locked loop, Nonlinear model of the phase – locked
loop, Linear model of the phase – locked loop, Nonlinear effects in FM
Unit 1: 7 Hours systems
Random process: Random variables: Several random variables. Statistical
averages: Function of Random variables, moments, , Mean, Correlation and Unit 7: 6 Hours
Covariance function: Principles of autocorrelation function, cross – Noise: Introduction, shot noise, thermal noise, white noise, Noise equivalent
correlation functions. Central limit theorem, Properties of Gaussian process. bandwidth, Narrow bandwidth, Noise Figure, Equivalent noise temperature,
cascade connection of two-port networks.
11 12
Unit 2: 4 Hours system, Firmware-software coupling, Switching system maintainability
Evolution of Switching Systems: Introduction, Message switching, Circuit metrics, Upgrade process success rate, Number of patches applied per year,
switching, Functions of switching systems, Distribution systems, Basics of Diagnostic resolution rate, Reported critical and major faults corrected, A
crossbar systems, Electronic switching, Digital switching systems strategy improving software quality, Program for software process
improvement, Software processes improvement, Software processes, Metrics,
Digital Switching Systems: Fundamentals : Purpose of analysis, Basic Defect analysis, Defect analysis.
central office linkages, Outside plant venous inside plant, Switching system
hierarchy, Evolution of digital switching systems, Stored program control Unit 8: 6 Hours
switching systems, Digital switching system fundamentals, Building blocks A Generic Digital Switching System Model: Introduction, Scope, Hardware
of a digital switching system, Basic call processing. architecture, Software architecture, Recovery strategy, Simple call through a
4 Hours digital system, Common characteristics of digital switching systems.
Analysis report. Reliability analysis.
Unit 3: 6 Hours
Telecommunications Traffic: Introduction, Unit of traffic, Congestion,
Traffic measurement, Mathematical model, Lost call systems, Queuing
systems. TEXT BOOKS:
1. J E Flood: Telecommunication and Switching, Traffic and
Networks. Pearson Education, 2002
Unit 4: 6 Hours 2. Syed R. Ali, Digital Switching Systems, TMH Ed 2002.
Switching Systems: Introduction, Single stage networks, Gradings, Link
Systems, GOS of Linked systems REFERENCE BOOK:
1. John C Bellamy: Digital Telephony Wiley India 3rd Ed, 2000
PART-B
Unit 5: 4 Hours
Time Division Switching : Introduction, space and time switching, Time FUNDAMENTALS OF CMOS VLSI
switching networks, Synchronisation.
Text 1: Chapter 6 Sub Code : 06EC-56 IA Marks : 25
Unit 6: 6 Hours
Switching System Software: Introduction, Scope, Basic software architecture, Hours /Week :4 Exam Hours :3
Operating systems, Database Management, Concept of generic program, Total Hour : 52 Exam Marks :100
Software architecture for level 1 control, Software architecture for level 2 PART A
control, Software architecture for level 3 control, Digital switching system Unit 1: 4Hours
software classification, Call models, Connect sequence, Software linkages Basic MOS technology: Integrated circuit’s era. Enhancement and depletion
during call, Call features, Feature flow diagram, Feature interaction. mode MOS transistors. nMOS fabrication. CMOS fabrication. Thermal
Text 2: Chapter 5 aspects of processing. BiCMOS technology. Production of E-beam masks.
Unit 7: 8 Hours 4Hours
MOS Transistor Theory: Introduction, MOS Device Design Equations, The
Maintenance of Digital Switching System: Introduction, Scope, Software
Complementary CMOS Inverter – DC Characteristics, Static Load MOS
maintenance, Interface of a typical digital switching system central office,
Inverters, The Differential Inverter, The Transmission Gate, Tristate Inverter
System outage and its impact on digital switching system reliability, Impact
of software patches on digital switching system maintainability, Embedded
patcher concept, Growth of digital switching system central office, Generic
program upgrade, A methodology for proper maintenance of digital Unit 2: 4Hours
switching system, Effect of firmware deployment on digital switching
13 14
Circuit design processes: MOS layers. Stick diagrams. Design rules and 1. M. K. Achuthan and K. N. Bhat, “Fundamentals of Semiconductor
layout – lambda-based design and other rules. Examples. Layout diagrams. Devices”, Tata McGraw-Hill Publishing Company Limited, New
Symbolic diagrams. Tutorial exercises. Delhi, 2007.
Basic Physical Design of Simple logic gates 2. Sung-Mo Kang & Yusuf Leblebici, “CMOS Digital Integrated
3Hours Circuits: Analysis and Design”, 3rd Edition, Tata McGraw-Hill
Publishing Company Ltd., New Delhi, 2007.
Unit 3 6 Hours 3. D.A Hodges, H.G Jackson and R.A Saleh. “Analysis and Design of
CMOS logic structures : CMOS Complementary Logic, Bi CMOS Logic, Digital Integrated Circuits”- 3rd Edition, Tata McGraw-Hill
Pseudo-nMOS Logic, Dynamic CMOS Logic, Clocked CMOS Logic, Pass Publishing Company Limited, New Delhi, 2007.
Transistor Logic, CMOS Domino Logic Cascaded Voltage Switch Logic ---------------------------------------------
(CVSL).
DIGITAL SIGNAL PROCESSING LABORATORY
Unit 4: 4 Hours
Basic circuit concepts: Sheet resistance. Area capacitances. Capacitance Sub Code : 06ECL-57 IA Marks : 25
calculations. The delay unit. Inverter delays. Driving capacitive loads. Hours /Week :3 Exam Hours :3
Propagation delays. Wiring capacitances. Tutorial exercises. Total Hour : 42 Exam Marks :50
Scaling of MOS circuits: Scaling models and factors. Limits on scaling.
Limits due to current density and noise. 3Hours A LIST OF EXPERIMENTS USING
MATLAB/SCILAB/OCTAVE/WAB
Unit 5: 4 Hours
CMOS subsystem design: Architectural issues. Switch logic. Gate logic. 1. Verification of Sampling theorem.
Design examples – combinational logic. Clocked circuits. Other system 2. Impulse response of a given system
considerations. 3. Linear convolution of two given sequences.
Clocking Strategies 4 Hours 4. Circular convolution of two given sequences
5. Autocorrelation of a given sequence and verification of its properties.
Unit 6: 6 Hours 6. Cross correlation of given sequences and verification of its properties.
CMOS subsystem design processes: General considerations. Process 7. Solving a given difference equation.
illustration. ALU subsystem. Adders. Multipliers. 8. Computation of N point DFT of a given sequence and to plot magnitude
and phase spectrum.
Unit 7: 5 Hours 9. Linear convolution of two sequences using DFT and IDFT.
Memory, registers, and clock: Timing considerations. Memory elements. 10. Circular convolution of two given sequences using DFT and IDFT
Memory cell arrays. 11. Design and implementation of FIR filter to meet given specifications.
12. Design and implementation of IIR filter to meet given specifications.
Unit 8: 5 Hours
Testability: Performance parameters. Layout issues. I/O pads. Real estate. B. LIST OF EXPERIMENTS USING DSP PROCESSOR
System delays. Ground rules for design. Test and testability. (Note: Experiments no: 1, 2, 3 & 7 may be performed on CCS)
TEXT BOOKS: 1. Linear convolution of two given sequences.
1. Douglas A. Pucknell & Kamran Eshraghian, “Basic VLSI Design” 2. Circular convolution of two given sequences.
PHI 3rd Edition (original Edition – 1994), 2005. 3. Computation of N- Point DFT of a given sequence
2. Neil H. E. Weste and K. Eshragian,” Principles of CMOS VLSI 4. Realization of an FIR filter (any type) to meet given specifications .The
Design: A Systems Perspective,” 2nd edition, Pearson Education input can be a signal from function generator / speech signal .
(Asia) Pvt. Ltd., 2000. 5. Audio applications such as to plot time and frequency (Spectrum)
display of Microphone output plus a cosine using DSP. Read a wav file
REFERENCE BOOKS:
15 16
and match with their respective spectrograms
6. Noise: Add noise above 3kHz and then remove; Interference suppression VI SEMESTER
using 400 Hz tone. DIGITAL COMMUNICATION
7. Impulse response of first order and second order system
REFERENCE BOOKS: Sub Code : 06EC-61 IA Marks : 25
1. Sanjeet Mitra, Digital signal processing using MATLAB, TMH, Hours /Week :04 Exam Hours :3
2001 Total Hour : 52 Exam Marks :100
2. J.G.Proakis & Ingale, Digital signal processing using PART A
MATLAB,.MGH, 2000 Unit 1: 07 Hours
3. B.Venkataramani and Bhaskar, Digital signal processors,
TMH,2002 Basic signal processing operations in digital communication. Sampling
Principles: Sampling Theorem, Quadrature sampling of Band pass signal,
ANALOG COMMUNICATION LAB + LIC LAB Practical aspects of sampling and signal recovery.
Unit2: 07 Hours
Sub Code : 06ECL-58 IA Marks :25
PAM, TDM. Waveform Coding Techniques, PCM, Quantization noise and
Hours /Week :3 Exam Hours :3
SNR, robust quantization.
Total Hour : 42 Exam Marks :50
Unit3: 06 Hours
EXPERIMENTS
1. Second order active LPF and HPF DPCM, DM, applications. Base-Band Shaping for Data Transmission,
2. Second order active BPF and BE Discrete PAM signals, power spectra of discrete PAM signals.
3. Schmitt Trigger Design and test a Schmitt trigger circuit for the Unit4: 06 Hours
given values of UTP and LTP
4. Frequency synthesis using PLL. ISI, Nyquist’s criterion for distortion less base-band binary transmission,
5. Design and test R-2R DAC using op-amp correlative coding , eye pattern, base-band M-ary PAM systems, adaptive
6. Design and test the following circuits using IC 555 equalization for data transmission.
a. Astable multivibrator for given frequency and duty cycle PART B
b. Monostable multivibrator for given pulse width W Unit 5 07 Hours
7. Class C Single tuned amplifier Digital Modulation Techniques: Digital Modulation formats, Coherent binary
8. Amplitude modulation using transistor/FET (Generation and modulation techniques, Coherent quadrature modulation techniques. Non-
detection) coherent binary modulation techniques.
9. Pulse amplitude modulation and detection
10. PWM and PPM Unit 6: 06 Hours
11. Frequency modulation using 8038/2206 Detection and estimation, Model of DCS, , Gram-Schmidt Orthogonalization
12. Precision rectifiers – both Full Wave and Half Wave. procedure, geometric interpretation of signals, response of bank of correlators
to noisy input.
Unit 7: 06 Hours
Detection of known signals in noise, , correlation receiver, matched filter
receiver, detection of signals with unknown phase in noise,
Unit 8 07 Hours
Spread Spectrum Modulation: Pseudo noise sequences, notion of spread
spectrum, direct sequence spread spectrum, coherent binary PSK, , frequency
17 18
hop spread spectrum, applications. PART B
Unit 5 06 Hours
TEXT BOOK:
8086 Interfacing: Interfacing microprocessor to keyboard (keyboard types,
1. Simon Haykin, Digital communications, JohnWiley,2003. keyboard circuit connections and interfacing, software keyboard interfacing,
REFERENCE BOOKS: keyboard interfacing with hardware), Interfacing to alphanumeric displays
(interfacing LED displays to microcomputer), Interfacing a microcomputer to
1. K.Sam Shanmugam, Digital and analog communication systems, a stepper motor
John Wiley, 1996. 2.Simon Haykin, An introduction to Analog and
Digital Communication, John Wiley, 2003 Unit 6 06 Hours
2. Bernard Sklar: Digital communications Pearson education 2007
8086/8088 based Multiprocessing Systems: Coprocessor configurations, The
8087 numeric data processor: data types, processor architecture, instruction
set and examples
MICROPROCESSOR
Unit 7 07 Hours
Sub Code : 06EC-62 IA Marks : 25 System Bus Structure: Basic 8086/8088 configurations: minimum mode,
Hours /Week :04 Exam Hours :3 maximum mode, Bus Interface: peripheral component interconnect (PCI)
Total Hour : 52 Exam Marks :100 bus, the parallel printer interface (LTP), The universal serial bus (USB)
19 20
ANALOG AND MIXED MODE VLSI DESIGN ANTENNAS AND PROPAGATION
21 22
Unit 6 06 Hours Unit 2 : 06 Hours
Antenna Types: Helical Antenna, Yagi-Uda array, corner reflectors, Source Coding: Encoding of the source output, Shannon’s encoding
parabolic reflectors, log periodic antenna, lens antenna, antenna for special algorithm. Communication Channels, Discrete communication channels,
applications – sleeve antenna, turnstile antenna, omni directional antennas, Continuous channels.
antennas for satellite antennas for ground penetrating radars, embedded
antennas, ultra wide band antennas, plasma antenna. Unit 3 : 06 Hours
Fundamental Limits on Performance: Source coding theorem,,
Unit 7 and 8 12 Hours Huffman coding, Discrete memory less Channels, Mutual information,
Radio Wave Propagation: Introduction, Ground wave propagation, free Channel Capacity.
space propagation, ground reflection, surface wave, diffraction.
Troposphere Wave Propagation: troposcopic scatter, Ionosphere
,
Unit 4 : 06 Hours
propagation, electrical properties of the ionosphere, effects of earth’s Channel coding theorem , Differential entropy and mutual information for
magnetic field. continuous ensembles, Channel capacity Theorem .
TEXT BOOK: PART-B
1. John D.Krauss, Antennas, III (SEI) edition, McGraw-Hill International Unit 5 : 07 Hours
edition, 2006 Introduction to Error Control Coding: Introduction, Types of errors,
2. Harish and Sachidananda: Antennas and Wave Propagation Oxford Press examples, Types of codes Linear Block Codes: Matrix description, Error
2007 detection and correction, Standard arrays and table look up for decoding.
,
23 24
ADVANCED COMMUNICATION LAB v] Bit wise and nibble wise palindrome
4)Branch/Loop instructions like:
Sub Code : 06EC-67 IA Marks : 25 i] Arrays: addition/subtraction of N nos.
Hours /Week :3 Exam Hours :3 Finding largest and smallest nos.
Total Hour : 42 Exam Marks :50 Ascending and descending order
ii] Near and Far Conditional and Unconditional jumps, Calls and Returns
LIST OF EXPERIMENTS 5) Programs on String manipulation like string transfer, string reversing,
1. TDM of two band limited signals. searching
2. ASK and FSK generation and detection for a string, etc.
3. PSK generation and detection 6) Programs involving Software interrupts
4. DPSK generation and detection Programs to use DOS interrupt INT 21h Function calls for Reading a
5. QPSK generation and detection Character
6. PCM generation and detection using a CODEC Chip from keyboard, Buffered Keyboard input, Display of character/ String on
7. Measurement of losses in a given optical fiber ( propagation loss, bending console
loss) and numerical aperture II) Experiments on interfacing 8086 with the following interfacing modules
8. Analog and Digital (with TDM) communication link using optical fiber. through
9. Measurement of frequency, guide wavelength , power, VSWR and DIO (Digital Input/Output-PCI bus compatible) card
attenuation in a microwave test bench a) Matrix keyboard interfacing
10. Measurement of directivity and gain of antennas: Standard dipole (or b) Seven segment display interface
printed dipole), microstrip patch antenna and Yagi antenna(printed). c) Logical controller interface
11. Determination of coupling and isolation characteristics of a stripline (or d) Stepper motor interface
microstrip) directional coupler III) Other Interfacing Programs
12. (a) Measurement of resonance characteristics of a microstrip ring a) Interfacing a printer to an X86 microcomputer
resonator and determination of dielectric constant of the substrate. b) PC to PC Communication
(b) Measurement of power division and isolation characteristics of a -------------------------------------------------------------------------------------
microstrip 3 dB power divider.
ELECTIVE GROUP-A
06ECL-68: Microprocessor Lab
I) Programs involving PROGRAMMING IN C++
1) Data transfer instructions like:
i] Byte and word data transfer in different addressing modes. Sub Code : 06EC-661 IA Marks : 25
ii] Block move (with and without overlap)
Hours /Week :4 Exam Hours :3
iii] Block interchange
Total Hour : 52 Exam Marks :100
2) Arithmetic & logical operations like:
PART A
i] Addition and Subtraction of multi precision nos.
Unit 1 06 Hours
ii] Multiplication and Division of signed and unsigned Hexadecimal
C++, An Overview: Getting started, the C++ program, Preprocessor
nos.
Directives,
iii] ASCII adjustment instructions
The Built-In Array Data Type, Dynamic Memory Allocation and Pointers,
iv] Code conversions
An
v] Arithmetic programs to find square cube, LCM, GCD, factorial
Object – based Design, An Object-Oriented Design, An Exception – based
3)Bit manipulation instructions like checking:
Design, An array.
i] Whether given data is positive or negative
ii] Whether given data is odd or even
iii]Logical 1’s and 0’s in a given data
iv] 2 out 5 code
25 26
SATELLITE COMMUNICATION
Unit 2 06 Hours
The basic language: Literal Constant, Variables, Pointer Type, String Types, Sub Code : 06EC-662 IA Marks : 25
const
Hours /Week :4 Exam Hours :3
Qualifier, Reference Types, the bool type, Enumeration types, Array types.
Total Hour : 52 Exam Marks :100
The vector container type. Text 1: Chap 3: 3.1 to 3.10
PART A
Unit 3 10 Hours
Unit 1 03 Hours
Operators: Arithmetic Operators, Equality, Relational and Logical operators,
Over view of Satellite Systems: Introduction, frequency allocation, INTEL
Assignment operators, Increment and Decrement operator, The conditional
Sat.
Operator, Bitwise operator, bitset operations. Statements: if, switch, for
Loop, while, break, goto, continue statements.
Unit 2 10 Hours
Orbits: Introduction, Kepler laws, definitions, orbital element, apogee and
Unit 4 04 Hours
perigee heights, orbit perturbations, inclined orbits, calendars, universal time,
Functions: Prototype, Argument passing, Recursion and linear function.
sidereal time, orbital plane, local mean time and sun synchronous orbits,
Geostationary orbit: Introduction, antenna, look angles, polar mix antenna,
PART B
limits of visibility, earth eclipse of satellite, sun transit outage, leandiag
Unit 5 06 Hours
orbits.
Exception Handling: Throwing an Exception, Catching an exception,
Execption Specification and Execptions and Design Issues.
,,
Unit 3 08 Hours
Unit 6 07 Hours Propagation impairments and space link: Introduction, atmospheric loss,
Classes : Definition, Class Objects, Class Initailization, Class constructior, ionospheric effects, rain attenuation, other impairments.
The class destructor, Class Object Arrays and Vectors. Space link: Introduction, EIRP, transmission losses, link power budget,
system noise, CNR, uplink, down link, effects of rain, combined CNR.
Unit 7 07 Hours
Overload Operators, Operators ++ and --, Operators new and delete. Unit 4 06 Hours
Unit 8 06 Hours Space Segment: Introduction, power supply units, altitude control, station
Multiple Inheritance, public, private & protected inheritance, Class scope keeping, thermal control, TT&C, transponders, antenna subsystem.
under
Inheritance. Unit 5 and 6 03 Hours
,
Earth Segemnt: Introduction, receive only home TV system, out door unit,
TEXT BOOKS:
indoor unit, MATV, CATV, Tx – Rx earth station.
1. S. B. Lippman & J. Lajoie, C++ Primer, 3rd Edition, Addison Wesley,
2000.
Interference and Satellite access: Introduction, interference between satellite
REFERENCE BOOKS: circuits, satellite access, single access, pre-assigned FDMA, SCPC (spade
1. C++ Program Design: An Introduction to Programming and Object- system), TDMA, pre-assigned TDMA, demand assigned TDMA, down link
Oriented Design. Cohoon and Davidson, 3rd Edn. TMH publication. 2004. analysis, comparison of uplink power requirements for TDMA & FDMA, on
2. R. Lafore, Object Oriented Programming using C++, Galgotia board signal processing satellite switched TDMA. 08 Hours
Publications, 2004.
Unit 7 and 8 1 0 Hours
27 28
digital TV, satellite mobile services, USAT, RadarSat, GPS, orb PART B
communication and iridium. Unit 5: 07 Hours
Pairs of Random variables, Joint CDF, joint PDF, Joint probability mass
TEXT BOOK: functions, Conditional Distribution, density and mass functions, EV
1. Dennis Roddy, Satellite Communications, 4th Edition, McGraw-Hill involving pairs of Random variables, Independent Random variables,
International edition, 2006 Complex Random variables, Engg Application
29 30
loop adaptation, Example of an adaptive system. adaptive interface canceller as a high-pass filter, Effects of finite length and
causality, multiple-reference noise canceling.
Unit 2 06 Hours
The Adaptive Linear Combiner: General description, Input signal and weight TEXT BOOK:
vectors, Desired response and error, the performance function, gradient and 1. Bernard Widrow and Samuel D. Stearns, Adaptive Signal Processing,
minimum mean-square error, Example of a performance surface, Alternative Pearson Education Asia, 2001.
expression of the gradient, Decorrelation of error and input components.
REFERENCE BOOKS:
Unit 3 08 Hours 1. Simon Haykin, Adaptive filter Theory , 4e, Pearson Education Asia, 2002
Properties Of The Quadratic Performance Surface: Normal of the input 2. Jophn R. Treichler C. Richard Johnson, Jr. and Michael G. Larimore,
correlation matrix, Eigen values and Eigen vectors of the input correlation Theory and Design of Adaptive Filters, Pearson education/,PHI 2002.
matrix, an example with two weights, geometrical significance of *************************************
eigenvectors and Eigen values, a second example.
LOW POWER VLSI DESIGN
Unit 4 07 Hours
Searching The Performance Surface: Methods of searching the performance Sub Code : 06EC-665 IA Marks : 25
surface, Basic ideal of gradient search methods, a simple gradient search Hours /Week :04 Exam Hours :3
algorithm and its solution, Stability and rate of convergence, The learning Total Hour : 52 Exam Marks :100
curve, Gradient search by Newton’s method in multidimensional space, PART A
Gradient search by the method of steepest descent, Comparison of learning Unit 1: 06 Hours
curves. Introduction, Sources of power dissipation, designing for low power.
PART-B Physics of power dissipation in MOSFET devices – MIS Structure, Long
Unit 5 08 Hours channel and sub-micron MOSFET, Gate induced Drain leakage.
Gradient Estimation And Its Effects On Adaptation: Gradient component
estimation by derivate measurement, the performance penalty, Derivative Unit 2: 08 Hours
measurement and performance penalties with multiple weights, variance of Power dissipation in CMOS – Short circuit dissipation, dynamic dissipation,
the gradient estimate, effects on the weight-over solution, excess mean- Load capacitance. Low power design limits - Principles of low power
square error and time constants, mis adjustment, comparative performance of design, Hierarchy of limits, fundamental limits, Material, device, circuit
Newton’s and steepest-descent methods, Total mis adjustment and other and system limits.
practical considerations.
Unit 3: 12 Hours
Unit 6 05 Hours Synthesis for Low power: Behavioral, Logic and Circuit level approaches,
The LMS Algorithm: Derivation of the LMS algorithm, convergence of the Algorithm level transforms, Power-constrained Least squares optimization
weight vector, an example of convergence, learning curve, noise in the for adaptive and non-adaptive filters, Circuit activity driven architectural
weight-vector solution, misadjustment, performance. transformations, voltage scaling, operation reduction and substitution, pre-
computation, FSM and Combinational logic, Transistor sizing.
Unit 7 05 Hours PART B
Adaptive Modeling And System Identification: General description, Adaptive Unit 4: 12 Hours
modeling of multipath communication channel, adaptive modeling in Design and Test of Low-Voltage CMOS Circuits: Introduction, Design style,
geophysical exploration, Adaptive modeling in FIR digital filter synthesis. Leakage current in Deep sub-micron transistors, device design issues,
minimizing short channel effect, Low voltage design techniques using
Unit 8 07 Hours reverse Vgs, steep sub
Adaptive Interfacing Canceling: The concept of adaptive noise canceling, threshold swing and multiple threshold voltages, Testing with elevated
stationary noise-canceling solutions, effects of signal components in the intrinsic leakage, multiple supply voltages.
reference input, The adaptive interference canceller as a notch filter, The
31 32
Unit 5: 8 Hours Time State Equations, Solution of Linear Time- Invariant continuous-Time
Low energy computing: Energy dissipation in transistor channel, Energy State Equations, Solution of Linear Discrete-Time
recovery circuit design, designs with reversible and partially reversible logic, State Equations, State Equations of Sampled –Data Systems.
energy recovery in adiabatic logic and SRAM core, Design of peripheral PART-B
circuits – address decoder, level shifter and I/O Buffer, supply clock Unit 5: 07 Hours
generation. Controllability and Observability: Introduction, General Concept of
Unit 6: 4 Hours Controllability, General Concept of Observability, Controllability Tests for
Software design for low power: Introduction, sources of power dissipation, Continuous-Time Systems, Observability Tests for Continuous- Time
power estimation and optimization. Systems, Controllability and Observability of Discrete-Time Systems,
Controllability and Observability of State Model in Jordan Canonical Form,
TEXT BOOK: Loss of Controllability and Observability due to Sampling, Controllability
1. Kaushik Roy and Sharat C Prasad, Low-Power CMOS VLSI Circuit and Observability, Canonical Forms of State Model.
,
33 34
DIGITAL SYSTEMS DESIGN USING VHDL Additional Topics In VHDL: Attributes, Transport and Inertial delays,
Operator overloading, Multi-valued logic and signal resolution, IEEE-1164
Sub Code : 06EC-667 IA Marks : 25 standard logic, Generics, Generate statements, Synthesis of VHDL code,
Hours /Week :4 Exam Hours :3 Synthesis examples, Files and Text IO.
Total Hour : 52 Exam Marks :100 Unit 8 07 Hours
PART-A VHDL Models For Memories And Buses: Static RAM, A simplified 486 bus
Unit 1 07 Hours model, Interfacing memory to a microprocessor bus.
Introduction: VHDL description of combinational networks, Modeling flip-
TEXT BOOKS:
flops using VHDL, VHDL models for a multiplexer, Compilation and
1. Charles H. Roth. Jr:, Digital Systems Design using VHDL, Thomson
simulation of VHDL code, Modeling a sequential machine, Variables,
Learning, Inc, 9th reprint, 2006.
Signals and constants, Arrays, VHDL operators, VHDL functions, VHDL
procedures, Packages and libraries, VHDL model for a counter.
REFERENCE BOOKS:
1. Stephen Brwon & Zvonko Vranesic, Fundamentals of Digital Logic
Unit 2 06 Hours
Design with VHDL, Tata McGrw-Hill, New Delhi, 2nd Ed., 2007
Designing With Programmable Logic Devices: Read-only memories,
2. Mark Zwolinski, Digital System Design with VHDL, 2 Ed, Pearson
Programmable logic arrays (PLAs), Programmable array logic (PLAs), Other
Education., 2004
sequential programmable logic devices (PLDs), Design of a keypad scanner.
3. Volnei A Pedroni, Digital electronics and Design with VHDL. Elsivier
Science, 2009
Unit 3 06 Hours
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Design Of Networks For Arithmetic Operations: Design of a serial adder
with accumulator, State graphs for control networks, Design of a binary
multiplier, Multiplication of signed binary numbers, Design of a binary
divider.
Unit 4 07 Hours
Digital Design with SM Charts: State machine charts, Derivation of SM
charts, Realization of SM charts. Implementation of the dice game,
Alternative realization for SM charts using microprogramming, Linked state
machines.
PART-B
Unit 5 06 Hours
Unit 7 07 Hours
35 36