INTRODUCTION TO DUAL-DAMASCENE INTERCONNECT PROCESSES

by Stanley Wolf, Ph.D.

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The text and graphics remain the same as in Vol. 4, pp.674-679.
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In a dual-damascene (DD) structure, only a single metal deposition step is used to simultaneously form
the main metal lines and the metal in the vias. That is, both trenches and vias are formed in a single
dielectric layer. The vias and trenches are defined by using two lithography steps (Fig. 15-3). Trenches
are typically etched to a depth of 4000-5000-Å, and the vias are typically 5000-7000Å-deep. After the via
and trench recesses are etched, the via is filled in the same metal-deposition step that fills the trench.
After filling, the excess metal that is deposited outside the trench is removed by a CMP process, and a
planar structure with metal inlays is achieved. As in the single-damascene process, once a planarized
surface is achieved, it is no longer necessary to perform CMP on the dielectric layers. Thus, one of the
CMP steps needed for each metal level in the subtractive interconnect process is also eliminated.

Fig. 15-3 Dual-Damascene process: (a) IMD is deposited by CVD and planarized by CMP. Trench is defined by PR #1 and then etched; (b)
SEM of the etched trench after PR #1 has been stripped; (c) Vias are defined by PR #2 and then etched, using PR #2 to protect other regions
of the IMD from etching; (d) Metal is deposited to simultaneously fill trenches and vias. CMP is used to remove excess metal. The sequence is
repeated for the next level of metal.

It should also be mentioned that in early dual-damascene processes, the trench dimension was somewhat
wider than that of the vias. This made the alignment of the via to the trench somewhat easier. However,
with time, the via and trench widths have been made equal. (At the 0.18-µm node, the via and trench
widths are 0.22-0.24-µm wide, while at the 0.13-µm node they will probably be ~0.18-µm wide.) Thus,
modern dual-damascene processes are more sensitive to misalignment between the trench and via.
However, this overlay sensitivity problem is mitigated to some degree by the nature of the damascene
process, making it possible to maintain high interconnect packing density.

That is, the alignment of the trenches to the vias in the dual-damascene sequences is an easier task than
in the subtractive interconnect process. In the latter, aligning metal lines to the underlying contact holes
(or vias) must be done after the opaque, shiny, blanket-metal film has been deposited. In damascene
approaches, aligning the trenches to the vias is done through the transparent dielectric film, which allows
tighter design-rule tolerances to be used when performing this alignment.

When comparing the single-damascene process to the simple dual-damascene process described above,
one observes one metal-deposition step and one CMP step are eliminated in the latter (as well as one
dielectric-deposition step). The reduction in the number of processing steps is another of the benefits that
have driven the development of dual-damascene processes. Note that in single-damascene structures,
plugs are typically filled with W, but in the dual-damascene-interconnects the metal that fills the holes is
Al or Cu. The technology of filling of vias and trenches with Cu is described in Chap. 16. A dual-damascene
process using Al was described by workers at IBM in 1998.

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 15.5 THE THREE DUAL-DAMASCENE PROCESS SEQUENCES

Three different fabrication sequences have been developed to produce dual-damascene structures:

1. Trench-First Dual-Damascene
2. Via-First Dual-Damascene
3. Self-Aligned (or Buried-Via) Dual-Damascene

It should be noted that the via-first and the trench-first sequences are the processes currently being used
in mainstream production. The trench-first sequence was probably the first one to be adopted, but the
via-first sequence is currently the approach that has gained the greatest acceptance (and will likely
remain so going forward). As a result, we will focus on these two sequences, and will point out the
advantages and drawbacks of each one. While the third approach (the self-aligned process), has not been
implemented in production (for reasons we will also explain), we will provide a brief description of it as
well. However, whichever sequence is used, the final damascene structure is the same (see Fig. 15-4).

Before outlining the three dual-damascene processes, it should be mentioned that the dielectric layer in
which the trenches and vias are etched actually consists of at least three layers of dielectric (see Fig. 15-
8b). That is, SiO2 (or a low-k dielectric is deposited to a depth of 5000-7000Å (and this will be the layer in
which the vias will be etched). Next, a thin silicon nitride layer - or other material (which will serve as an
embedded etch-stop layer), is deposited (about 30-nm thick). Finally, another SiO2 layer (or a low-k
dielectric layer) is deposited (~4000-5000-Å thick). This will serve as the layer in which the trenches will
be etched.

Fig. 15-4 A suggested dual-damascene-based Cu metallization flow and resulting cross-sectional structure. Reprinted with permission of
Solid State Technology. Published by PennWell.

In the trench-first sequence (Fig. 15-5), the trench patterns are defined in the ILD first. That is, after
spinning on the resist, the trench-pattern-mask is used to expose the resist. The trench is then produced
by etching the dielectric down to the embedded etch-stop layer. After the trench-etching process, the first
resist layer is stripped. A second resist layer is then spun on, and the via-pattern-mask is used to create
openings in this resist layer - aligned to the trench that was etched previously. The resist protects the
other parts of the wafer surface (including the etched regions of the trenches) so that the vias can be
etched without further etching the dielectric in the trenches.

Fig. 15-5 In the trench-first approach, the vias are patterned & etched after trenches are etched.

The chief disadvantage of the trench-first sequence involves the fact that the vias must be patterned after

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the trench etch. That is, since resist is applied as a liquid onto the wafer surface, it fills recessed regions
as water fills a lake. Hence, the top surface of the resist is planar. This means that the regions of resist
over the damascene trenches is quite thick. Resolving fine features in thick resist is harder than in thinner
resists. For features smaller than 0.25-µm the process latitude becomes too small for this to be a practical
manufacturing process. Thus, while the trench-first sequence could be used for early dual-damascene
processes (0.35-µm and some 0.25-µm processes), it is difficult to extend it to smaller technology nodes
(i.e., in order to able to use it at such small dimensions, it may be necessary to implement a thin imaging-
resist-layer process, as discussed later).

In the via-first approach the vias are defined first in the ILD, followed by patterning the trenches. As
noted above, this is currently the most common method of fabricating dual-damascene interconnects (and
is schematically shown in Fig. 15-6). The sequence of forming the damascene recesses in this approach
begins by exposing the via patterns with the first mask. After etching the vias completely through the
entire dielectric stack (except not through the barrier layer at the bottom of the dielectric stack) and
stripping the resist, a second mask is used to pattern the trenches.

The trenches are then created by etching the dielectric down to the embedded etch-stop layer. The barrier
layer at the bottom of the vias is protected from further etching during the trench-etch either by resist or
a BARC layer (applied for the trench-etch step) that floods the vias, or by using an etch process that is
highly selective to the bottom etch-stop material (i.e., so that the etch-stop layer at the bottom of the via
is not removed during the trench-etch step). After the resist is stripped and the etch-stop layer at the
bottom of the via is removed by dry-etching, the metal that fills both the vias and the trenches can be
deposited. After deposition, it is polished back to create the dual-damascene structure.

Fig. 15-6 In the via-first approach, the trench is patterned and etched after the via is formed.

In the self-aligned dual-damascene process (Fig. 15-7), the via pattern is created in the embedded etch-
stop layer with a lithography-and-etch sequence that is performed before the top dielectric layer of the
stack is deposited. A special etch process is required for this step. After the via pattern is thus etched, the
top dielectric layer is deposited. Finally, the trench mask is aligned to the via openings in the embedded
nitride layer, and both the trench and via are opened with a single etch step. This sequence requires
nearly perfect trench-to-via alignment, otherwise the via may no longer be round (but instead only half-
moon shaped), resulting in high via resistance. In addition, an etch-process with high nitride-to-oxide
selectivity is required. For these reasons this scheme has not found use in production.

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New barrier layers can help Cu/low-k
integration

Overview
The importance of copper and low-k thin film materials in next-
generation interconnect structures is well established and the
process of integrating these materials into manufacturing is
progressing rapidly, particularly with copper film technology.
However, a consistent industry-wide focus to minimize the k
values of new dielectric materials and then force-fit them into
back-end-of-line interconnect manufacturing flow with traditional Click here to enlarge
plasma oxide (SiOx) integration schemes has slowed overall image
integration progress. A bridge is needed to assist in the industry
transition from the traditional "dense" dielectrics to low-k
dielectrics. Amorphous hydrogenated silicon carbide (a-SiC:H)
films may provide that bridge.

Interconnect back-end-of-line (BEOL) processing of silicon ICs has evolved from

subtractive aluminum, where the interlayer dielectric (ILD) consists of oxides applied
over existing patterned metallization, to copper dual damascene processes where metal is
inlaid into patterned dielectric layers and undergoes chemical mechanical polish (CMP)
to complete conductor isolation. Dual damascene processes were developed to facilitate
patterning of the copper conductors and to meet the geometry demands for shorter circuit
delays and smaller transistor dimensions. These growing requirements have now dictated
that low-k dielectric films be integrated into the damascene process to optimize
interconnect performance. More than with subtractive interconnect technology,
damascene processes place large demands on dielectric material integrity, such as
requiring greater control of CMP erosion, withstanding more aggressive cleaning
approaches, and minimizing metal diffusion.

Figure 1. Applications of the barrier/hard mask/etch stop dielectric in Cu dual

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 damascene interconnection technology.
Click here to enlarge image

Damascene process evolution has resulted in the use of several dielectric layers to
address the integration and capacitance requirements associated with the structure. The
first is the primary isolation ILD. A second layer, known as the barrier/hard mask/etch
stop film, is stacked on the ILD to provide a block for copper migration and act as a dry
etch mask, CMP polish stop, or embedded dry etch stop, depending on the structure (Fig.
1). Plasma silicon nitrides (SixNyHz) were originally used as the barrier layer with SiOx as
the primary dielectric, but the relative permittivity of these nitride dielectrics is high
(6<kGlt;8) and limits the ability to reduce electrical delay within the interconnect. To
reduce interline capacitance, the ILD layer can be switched from SiOx to low-k dielectric
materials, but even in this case, the silicon nitride layer limits capacitance reduction and
opens other integration difficulties in the damascene patterning process. Clearly, a
different material is needed for the barrier, one that can meet the diffusion barrier
requirements, improve selectivity in patterning processes, maintain electrical integrity
through low leakage and good breakdown strength, and at the same time provide a
relative permittivity that is lower than nitride. Amorphous SiC:H is filling these
requirements because of its more desirable mechanical, chemical and electrical properties
compared to oxide and nitride films.

Low-k integration requirements

The basic unwritten rule for low-k materials is that, for a given application, they should
integrate no differently than SiOx films. The key integration points are as follows:

• Chemical integrity. The material must not degrade chemically in order to

maintain its permittivity, resistivity, and film thickness during patterning and
cleaning processes; and
• Mechanical integrity. The material must have controllable polish properties,
show good adhesion to contacting films, and enough mechanical strength to
ensure film integrity in subsequent processes all the way through packaging of the
final product.

Low-k materials are relatively porous and/or soft, and commonly contain methyl and
hydrogen bonds, making them vulnerable to chemical breakdown in subsequent process
steps. They provide the capacitance reduction for shrinking dimensions used in metal
conductors but are often poor barriers against Cu+ drift. These ILD films need to be
protected to maintain their beneficial electrical properties.

One method to overcome some of these problems is the selection of a robust barrier
dielectric material that can provide the mechanical integrity to the interconnect structure
while at the same time protecting the underlying ILD material from degradation in
subsequent process steps.

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Barrier/etch stop requirements
To provide the mandatory electrical performance in the interconnect structure, any
barrier/hardmask material must be insulating and enable the fabrication of interconnects
with low capacitance and low power dissipation in order to achieve optimum signal
performance in next-generation high-speed circuits. To achieve adequate reliability, the
films should also exhibit sufficient dielectric strength and impede Cu+ diffusion at
electric fields of approximately 1MV/cm. Low-k spin-on dielectric (SOD) and PECVD
films have significantly lower mechanical strength than SiOx. To integrate these low-k
films successfully in interconnect structures previously designed around more
mechanically capable films, it is helpful to sandwich them between other "capping
layers," which have higher modulus and hardness. This will improve the performance of
the structure in subsequent CMP processes, and later, in final packaging.

As with any dielectric, the cap material must be stable, both to thermal cycles and
chemical-based cleaning. Most low-k films are hydrophilic. If the ILD material contains
or picks up moisture, and/or is susceptible to mobile ion contamination, the cap should
act as a barrier to impede the movement of these charged entities. For this reason,
capping of low-k films is often performed directly after ILD deposition or after a short
ILD anneal step.

The barrier material must be thermally stable, remaining unchanged at normal Cu

damascene processing temperatures of 300-425°C. Outgassing of the barrier or ILD layer
during metal barrier (Ta or TaN) or Cu seed deposition will ruin the metals' conductivity.
The barrier dielectric material must exhibit good adhesion to the metals in order to
withstand the stresses generated as a result of the coefficient of expansion mismatch
between the conductors and insulators. Stress changes in the barrier film resulting from
thermal cycling can lead to adhesion failures and cracking.

The process chemistry used to deposit barrier films must minimize particle and pinhole
formation. Such problems can lead to such failures as dielectric undercut, bowing, and
void formation during subsequent CMP and cleaning steps.

In the realm of photolithography, the hard mask must be compatible with photoresist
deposition and strip processes. Photoresist is typically consumed during the etch process
or removed afterward with plasma processing. If the resist is consumed during etch, the
barrier layer will then be subjected to harsh etch chemistries. Therefore, good selectivity
with respect to the ILD is required. Throughout this process, the barrier film must not
change chemically in a way that adversely affects electrical performance.

Since available low-k films have k values <3, the relative permittivity of the barrier
should be <5 in order to maintain optimal electrical delay characteristics [1]. Hence,
interconnect capacitance levels with effective dielectric constants <3.8 can be easily
achieved.

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Amorphous-SiC:H has low relative permittivity, tunable between 4 and 6 depending on
deposition parameters, and good standard thin film characteristics such as adhesion,
chemical and moisture resistance, and mechanical strength [2-4].

Lithography
With the size of the lithography targets shrinking, DUV photoresist is mandatory. Since
substrate reflection increases as the wavelength decreases, and most low-k dielectric films
are transparent at DUV wavelengths, it is necessary to add an anti-reflective coating
(ARC) either underneath or on top of the photoresist to minimize reflection [5]. The
addition of a spin-on ARC layer can complicate the etch process, however [6]. If the
barrier/hardmask material used in the dual damascene structure exhibits sufficient ARC
properties, though, the ARC layer can be eliminated. This is the case with a-SiC:H.
Studies indicate that a-SiC:H is an effective inorganic ARC as well as a hardmask/barrier
protective layer. Unlike SiO2, which is transparent at DUV wavelengths, reflectivity
modeling yields a reflectivity less than 3%, with very good uniformity for a-SiC:H layers
as thin as tens of nanometers (Fig. 2).

Figure 2. DUV substrate reflectivity model for an a-SiC:H/low-k ILD damscene stack.
Click here to enlarge image

Etching
Maximizing the selectivity of the resist to the barrier/hard mask layers and between the
barrier and low-k ILD is essential to creating a process flow that yields straight sidewalls
and controllable dimensions. Amorphous-SiC:H films are attractive for dual damascene
processes because they exhibit slower etch rates than silicon nitride, SiOx, and low-k
films. These relative etch rates translate into high selectivity between barrier and ILD
materials. The slow erosion rate of the barrier also allows for more control of the etch
profile of the ILD, as the masking property of the barrier will not deteriorate before the
etching of the ILD is complete. If a-SiC:H is used as an embedded or bottom etch stop in
dual damascene, it can provide a wider process margin, enabling better control to prevent
the unintentional exposure of the metal contact at the bottom of the via during dielectric
etch (punch through).

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However, a-SiC:H is so chemically inert that it may be difficult to dry etch. If the
appropriate resist process is not established, based on material, thickness, and post-
exposure bake selection, a condition of low selectivity toward the photoresist can occur.
If resist consumption during etch is intended, this is not really a problem, but if the
process calls for resist to be intact after the hardmask is patterned, a dual hardmask
approach can be utilized.

Figure 3. DUV substrate reflectivity model for dual SiO2/SiC:H HM (structure shown right).
Click here to enlarge image

In the dual hardmask approach, a thick layer of SiOx can be placed on top of a much
thinner layer of a-SiC:H (Fig. 3). The resist and SiOx layer help to create a better etch
profile in the barrier/ILD layers and the necessary ARC performance is provided.
Additionally, the SiOx can provide two other important functions. First, since the
chemical interaction between oxide and DUV resists is well understood, it acts as a
controllable chemical interface for application of the DUV resist. Second, since the polish
rates of oxide films are established, the oxide layer can act as a sacrificial CMP layer,
allowing good control of the CMP removal process. The successful implementation of
this dual hardmask approach ensures that a continuous a-SiC:H layer will remain on the
low-k material after CMP, thus protecting the underlying ILD material properties.

Dry etch studies have been investigated for the single and dual hardmask/ILD etch.
Several combinations of Ar, N2, O2, CHF3 and CF4 etch gases were tested to produce a
process with minimized resist/hard mask erosion and maximized uniformity across the
wafer, with good critical dimensional (CD) control. The single a-SiC:H hard mask
approach with an Ar/CF4/CHF3/O2 etch chemistry showed adequate selectivity to oxide
(3.5:1), resist (5.5:1), and a-SiCO:H (6:1) films. The process of opening a thick a-SiC:H
hardmask (~200nm) was slow and consumed too much resist, however. By modifying the
etch chemistry to Ar/CF4/N2/O2, an improved etch rate through the hardmask was
achieved. Next, by combining the dual hardmask and etch approaches, using an
Ar/CF4/N2/O2 etch to break through the mask layers then switching to an Ar/CF4/CHF3/O2
chemistry for the ILD, adequate selectivity was maintained throughout the etch of the
entire stack, resulting in the production of vertical sidewalls with minimum deterioration
of the profile at the top of the via/trench opening.

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 Figure 4. Dry etch and strip results on dense 0.2 trenches (strip times are normalized fro removal
of 200mm resist).
Click here to enlarge image

Once an etch process is established, a resist strip/clean process compatible with the stack
dielectrics must be identified. This is one of the most difficult steps in the integration of
low-k materials. In one set of experiments, five separate strips were performed on 0.2μm
dense and isolated structures (Fig. 4). Most of the strip processes yielded poor results for
the underlying low-k ILD material (a-SiCOH), though none damaged the a-SiC:H
hardmask. The best result for the low-k ILD strip process was obtained using a N2/O2
chemistry at a low temperature and pressure.

Copper polishing
For copper CMP, important issues include high polish rates, good across-wafer
uniformity, and high selectivity to the CMP stop layer. An ideal stop layer has excellent
adhesion to the underlying low-k layer, is erosion resistant, protects the ILD layer by
providing a moisture barrier during subsequent cleaning processes, and blocks Cu+
migration.

Chemically inert a-SiC:H materials appear to provide a good CMP stop. Chemical
mechanical polishing of a-SiC:H was performed on blanket wafers using Cu and Ta
slurries. After a 120-sec polish, film loss was on the order of only 2-3nm. Amorphous-
SiC:H films exhibited better adhesion than oxide and nitrides to some low-k ILD films.
For example, adhesion of a-SiC:H to SiCOH ILD layers was evaluated with visual
inspection following CMP.

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 Figure 5. Normalized adhesion strengths by m-ELT.
Click here to enlarge image

Figure 5 shows the test structure and adhesion results normal to oxide, where the cap and
liner material sandwiching the SiCO:H ILD layer were changed among samples. Plasma
oxide, nitride, oxynitride, and a-SiC:H were tested. Following CMP, no delamination was
noted on a-SiC:H films; all others showed signs of delamination. This result was further
quantified using modified edge liftoff testing (m-ELT). Here the dielectric stack samples
were cryogenically cooled to induce large stresses at the film interfaces due to coefficient
of expansion mismatch variations between the films. When the stress exceeds the
adhesion strength, delamination occurs. The a-SiC:H film provided up to 4¥ more
adhesion strength compared to oxide, nitride and oxynitride (Fig. 5).

Figure 6. Moisture barrier properties SiO2 vs. a-SiC:H (on k ~2.0 SOG).
Click here to enlarge image

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As stated earlier, protecting the underlying low-k ILD materials by blocking moisture
during subsequent processes is an important requirement of a barrier film for successful
integration of porous low-k materials. Moisture barrier properties of a-SiC:H and SiOx
capping layers were compared by measuring capacitance changes in damascene
structures fabricated using a low-k SOD (k ~2.0) as the ILD. Electrical tests showed that
over time, the oxide cap allowed the capacitance of the structure to increase due to the
diffusion of moisture into the underlying porous oxide material. This is noted as a 30%
relative increase in the permittivity of the test sample in Figure 6. Moisture absorption
through the PECVD oxide was confirmed as the mechanism for capacitance change using
FTIR analysis. In contrast, no measurable change in capacitance was noted when an a-
SiC:H barrier covered the ILD. The presence of the a-SiC:H barrier enables the complete
fabrication of damascene structures with porous oxides while maintaining the
performance enhancements associated with ILD materials with k <2.5. The use of the a-
SiC:H film as a substitute for nitride in structures fabricated with SiOx, FSG, and SiCO:H
ILD materials (4>k>2.6) reduced capacitance on the order of 10-25% [1, 8].

Figure 7. Single a) and dual b) damascene structures made with a-

SiC:H and low-k ILD stacks. Single damascene picture uses SiCOH
ILD, and dual damascene picture uses SiOF ILD [7, 8].
Click here to enlarge image

Conclusion
There is growing interest in thin film a-SiC:H for easing some copper/low-k integration
issues. Damascene structures were fabricated using a-SiC:H barrier and low-k ILD,
demonstrating significant capacitance reduction when compared with similar structures
fabricated using oxide and nitride layers [7, 8]. Whether one uses a CVD or SOD low-k
ILD in the damascene approach, a-SiC:H films may enable faster integration of current
low-k material and improve the possibilities for success with future porous dielectrics.
Improvements in a-SiC:H materials are under way to reduce further their contribution to
the interconnect capacitance and improve the performance of next-generation logic
devices.

Acknowledgements
The authors gratefully acknowledge the advance of this technology through integration
work performed at IMEC, as part of the Industrial Affiliates Program, Samsung
Electronics, and Applied Materials.

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