Chapter 3:
Sequential Logic Design -- Controllers
Digital Design
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Frank Vahid
3.1
Introduction
• Sequential circuit 1
a 1
– Output depends not just on present inputs (as in 0 Combinational F
combinational circuit), but on past sequence of inputs b digital circuit
i
s
n
a
z
past inputs to
machine know output
– Convert a finite state machine to a controller – a
sequential circuit having a register and combinational
logic
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3.2
button
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First attempt at Bit Storage
• We need some sort of feedback S Q
– Does circuit on the right do what we want? t
• No: Once Q becomes 1 (when S=1), Q stays 1
forever – no value of S can bring Q back to 0
S 0 S 1 S 1 S 0
0Q S 1 0Q 1Q 1Q 1Q a
0 0 0 1 1
t t t t t
1
S
0
1
t
0
1
Q
0
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Bit Storage Using an SR Latch
S (set) SR latch
• Does the circuit to the right, with cross-coupled
NOR gates, do what we want?
– Yes! How did someone come up with that circuit?
Maybe just trial and error, a bit of insight... Q
R (reset)
S=0 S=0 S=1 S=0
t t t t Recall…
1 1 0 0 0
0 0 1 1 1
0
l
ca
.e
1
1 1 0 0 R
0
0 Q 0 Q 1 1 X
Q Q
1
S
0
R1
0 a
t 1
0
1
Q
0
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Example Using SR Latch for Bit Storage
• SR latch can serve as bit Call Blue light
storage in previous example button Bit
Storage
Cancel
of flight-attendant call button button
– Call=1 : sets Q to 1
• Q stays 1 even after Call=0 Call S
– Cancel=1 : resets Q to 0 but t on
Blue light
• But, there’s a problem... Q
Cancel
but t on
R
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Problem with SR Latch
• Problem
– If S=1 and R=1 simultaneously, we don’t know what value Q will take
1
S=1 S=0 S=0 S
t t t 0
0 1 0 1
0 0 1 R
0
1
0 0 1 t
0 Q 1 Q 0 Q 0
1
R=1 R=0 R=0 Q
0
1
Q may oscillate. Then, because one path will be t
0
slightly longer than the other, Q will eventually 1
settle to 1 or 0 – but we don’t know which. Q
0
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Problem with SR Latch
• Problem not just one of a user pressing two buttons at
same time
• Can also occur even if SR inputs come from a circuit that
supposedly never sets S=1 and R=1 at same time
– But does, due to different delays of different paths
1
Arbitrary
circuit SR latch
X
S
X 0
1
Y
Q 0
Y R
1
S
The longer path from X to R than to S causes SR=11 for 0
short time – could be long enough to cause oscillation SR= 11
1
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R
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Frank Vahid
Solution: Level-Sensitive SR Latch
• Add enable input “C” as shown Level-sensitive SR latch
S
– Only let S and R change when C=0 S1
• Enure circuit in front of SR never sets
SR=11, except briefly due to path delays C
– Change C to 1 only after sufficient time for S
and R to be stable Q
– When C becomes 1, the stable S and R R
R1
value passes through the two AND gates to
the SR latch’s S1 R1 inputs. S
Q’
Level-sensitive SR latch Though SR=11 briefly... C
1 Q
S S R
X S1 0
1 Level-sensitive
R0
SR latch symbol
C 1 a
Clk C
0
Q 1
S1
R 0
R1
Y 1
R1 0
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...S1R1 never = 11
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Clock Signals for a Latch
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Level-Sensitive D Latch
• SR latch requires careful design to D latch
D
ensure SR=11 never occurs S
C1 C2 C3 C4
Clk
Clk_A Clk_B
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D Flip-Flop
• Flip-flop: Bit storage that stores on clock edge, not level rising edges
• One design -- master-servant Clk
Clk Qs
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D Flip-Flop
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D Flip-Flop
• Solves problem of not knowing through how many latches a signal
travels when C=1
– In figure below, signal travels through exactly one flip-flop, for Clk_A or
Clk_B
– Why? Because on rising edge of Clk, all four flip-flops are loaded
simultaneously -- then all four no longer pay attention to their input, until the
next rising edge. Doesn’t matter how long Clk is 1.
n
d
si
ch
a
e
Y D1 Q1 D2 Q2 D3 Q3 D4 Q4 ifl
p
l
o
o
-fl
p
s
e
ch
each flip-flop
Clk
Clk_A Clk_B
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D Latch vs. D Flip-Flop
• Latch is level-sensitive: Stores D when C=1
• Flip-flop is edge triggered: Stores D when C changes from
0 to 1
– Saying “level-sensitive latch,” or “edge-triggered flip-flop,” is
redundant
– Two types of flip-flops -- rising or falling edge triggered.
• Comparing behavior of latch and flip-flop:
Clk 1 2
D3 4 5 6
Q (D latch) 7 8
Q (D flip-flop) 9 10
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Flight-Attendant Call Button Using D Flip-Flop
• D flip-flop will store bit Call
Flight Blue
button light
• Inputs are Call, Cancel, and present value attendant
call-button
Cancel
of D flip-flop, Q button system
Feature: S=1 sets Feature: S and R only Feature: SR can’t be 11 if Feature: Only loads D value
Q to 1, R=1 resets have effect when C=1. D is stable before and present at rising clock edge, so
Q to 0. Problem: We can design outside while C=1, and will be 11 values can’t propagate to other
SR=11 yield circuit so SR=11 never for only a brief glitch even flip-flops during same clock
undefined Q. happens when C=1. if D changes while C=1. cycle. Tradeoff: uses more
Problem: avoiding SR=11 Problem: C=1 too long gates internally than D latch,
can be a burden. propagates new values and requires more external
through too many latches: gates than SR – but gate count
too short may not enable a is less of an issue today.
store.
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Basic Register
• Typically, we store multi-bit items
– e.g., storing a 4-bit binary number
• Register: multiple flip-flops sharing clock signal
– From this point, we’ll use registers for bit storage
• No need to think of latches or flip-flops
• But now you know what’s inside a register
I3 I2 I1 I0
4-bit register
D D D D I3 I2 I1 I0
Q Q Q Q reg(4)
clk Q3 Q2 Q1 Q0
Q3 Q2 Q1 Q0
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Example Using Registers: Temperature Display
• Temperature history display
– Sensor outputs temperature as 5-bit binary number
– Timer pulses C every hour
– Record temperature on each pulse, display last three recorded values
e
x4 a4 a3 a2 a1 a0 b4 b3 b2 b1 b0 c4 c3 c2 c1 c0
r
tu
x3
a
x2
TemperatureHistoryStorage
r
o
n
se
x1
p
m
e
x0
timer
C
(In practice, we would actually avoid connecting the timer output
C to a clock input, instead only connecting an oscillator output to a clock input.)
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Example Using Registers: Temperature Display
• Use three 5-bit registers
a4 a3 a2 a1 a0 b4 b3 b2 b1 b0 c4 c3 c2 c1 c0
I4 Q4 I4 Q4 I4 Q4
x4
I3 Q3 I3 Q3 I3 Q3
x3
I2 Q2 I2 Q2 I2 Q2
x2
I1 Q1 I1 Q1 I1 Q1
x1
I0 Q0 I0 Q0 I0 Q0
x0
Ra Rb Rc
C
TemperatureHistoryStorage
x4...x0 15 18 20 21 21 22 24 24 24 25 25 26 26 26 27 27 27 27
Ra 0 18 21 24 25 26 27
Rb 0 0 18 21 24 25 26
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3.3
clk
• Example: Laser timer
patient
– Push button: x=1 for 3 clock cycles
– How? Let’s try three flip-flops
• b=1 gets stored in first D flip-flop
• Then 2nd flip-flop on next cycle,
then 3rd flip-flop on next
• OR the three flip-flop outputs, so x b
D Q D Q D Q
should be 1 for three cycles
clk
x
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Need a Better Way to Design Sequential Circuits
• Trial and error is not a good design method
– Will we be able to “guess” a circuit that works for other desired
behavior?
• How about counting up from 1 to 9? Pulsing an output for 1 cycle
every 10 cycles? Detecting the sequence 1 3 5 in binary on a 3-bit
input?
– And, a circuit built by guessing may have undesired behavior
• Laser timer: What if press button again while x=1? x then stays one
another 3 cycles. Is that what we want?
• Combinational circuit design process had two important
things
1. A formal way to describe desired circuit behavior
• Boolean equation, or truth table
2. A well-defined process to convert that behavior to a circuit
• We need those things for sequence circuit design
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Describing Behavior of Sequential Circuit: FSM
• Finite-State Machine (FSM) Outputs: x
x=0 clk^ x=1
– A way to describe desired
behavior of sequential circuit
Off On
• Akin to Boolean equations for
combinational behavior
clk^
– List states, and transitions
among states
Off On Off On Off On Off On
• Example: Make x change
toggle (0 to 1, or 1 to 0) every
clock cycle cycle 1 cycle 2 cycle 3 cycle 4
clk
• Two states: “Off” (x=0), and
“On” (x=1) state Off On Off On
• Transition from Off to On, or
Outputs:
On to Off, on rising clock edge
• Arrow with no starting state x
points to initial state (when
circuit first starts)
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FSM Example: 0,1,1,1,repeat
• Want 0, 1, 1, 1, 0, 1, 1, 1, ... Outputs: x
– Each value for one clock cycle x=0 clk^ x=1 clk^ x=1 clk^ x=1
– Four states
clk^
– Transition on rising clock
edge to next state
clk
State Off On1On2On3 Off On1On2 On3 Off
Outputs:
x
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Extend FSM to Three-Cycles High Laser Timer
Inputs: b; Outputs: x
• Four states x=0
clk^
• Wait in “Off” state while b is Off b’*clk^
0 (b’)
b*clk^
• When b is 1 (and rising x=1 clk^ x=1 clk^ x=1
On1
– Sets x=1 clk
– On next two clock edges, Inputs:
transition to On2, then On3, b
which also set x=1
State Off Off Off Off Off On1 On2 On3 Off
• So x=1 for three cycles after
Outputs:
button pressed
x
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FSM Simplification: Rising Clock Edges Implicit
Inputs: b; Outputs: x
• Showing rising clock on every x=0
clk^
transition: cluttered Off b’ *clk^
– Make implicit -- assume every
edge has rising clock, even if not b*clk ^
x=1 clk^ x=1 clk^ x=1
shown
On1 On2 On3
– What if we wanted a transition
without a rising edge
• We don’t consider such Inputs: x; Outputs: b
asynchronous FSMs -- less x=0
common, and advanced topic
Off b’
• Only consider synchronous
a
FSMs -- rising edge on every b
transition x=1 x=1 x=1
On1 On2 On3
Note: Transition with no associated condition thus
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FSM Definition
• FSM consists of Inputs: x; Outputs: b
– Set of states x=0
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FSM Example: Secure Car Key
• Many new car keys include
tiny computer chip
– When car starts, car’s
computer (under engine hood)
requests identifier from key
Inputs: a; Outputs: r
– Key transmits identifier
• If not, computer shuts off car Wait
r=0
• FSM a a’
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FSM Example: Secure Car Key (cont.)
Inputs: a; Outputs: r
• Nice feature of FSM
Wait
– Can evaluate output behavior r=0 a’
a
for different input sequence
K1 K2 K3 K4
– Timing diagrams show states
r=1 r=1 r=0 r=1
and output values for different
input waveforms
Q: Determine states and r value for
given input waveform:
clk clk
Inputs Inputs
a
a
State Wait Wait K1 K2 K3 K4 Wait Wait State Wait Wait K1 K2 K3 K4 Wait K1
Outputs Output a
r r
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FSM Example: Code Detector
• Unlock door (u=1) only when s
Start
u
buttons pressed in sequence: r Door
Red Code
– start, then red, blue, green, red a Green
g detector lock
• Input from each button: s, r, g, b Blue b
a
– Also, output a indicates that
some colored button pressed
Inputs: s,r,g,b,a;
• FSM Outputs: u
– Wait for start (s=1) in “Wait” Wait
u=0 s s’
– Once started (“Start”) ar’ ab’ ag’ ar’
a
• If see red, go to “Red1” Start a’
• Then, if see blue, go to “Blue”
u=0
• Then, if see green, go to ar
“Green” ab ag ar
Red1 Blue Green Red2
• Then, if see red, go to “Red2” a’ a’ a’
u=0 u=0 u=0 u=1
– In that state, open the door
(u=1) Q: Can you trick this FSM to open the door,
• Wrong button at any step, return without knowing the code?
to “Wait”, without opening door a
A: Yes, hold all buttons simultaneously
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Improve FSM for Code Detector
Inputs: s,r,g,b,a;
Outputs: u
Wait
u=0 s s’ ar’ ab’ ag’ ar’ a
Start
a’
u=0
ar
ab ag ar
Red1 Blue Green Red2
a’ a’ a’
u=0 u=0 u=0 u=1 Note: small problem still
remains; we’ll discuss later
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Standard Controller Architecture
• How implement FSM as sequential Inputs: x; Outputs: b
circuit? x=0
– Use standard architecture Off b’
• State register -- to store the present
state b
• Combinational logic -- to compute x=1 x=1 x=1
outputs, and next state On1 On2 On3
• For laser timer FSM
– 2-bit state register, can represent four
states s
tp
u
o
inputs
outputs
M
S
F
FSM
– Input b, output x b x
FSM
– Known as controller Combinational n1
logic
inputs
outputs
FSM
I O FSM n0
Combinational
logic s1 s0
S clk State register
a m
m-bit m
clk
state register
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3.4
Controller Design
• Five step controller design process
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Controller Design: Laser Timer Example
• Step 1: Capture the FSM Inputs: b; Outputs: x
x=0
– Already done 00
Off b’
• Step 2: Create architecture a
b
– 2-bit state register (for 4 states) x=1 x=1 x=1
01 On1 10 On2 11 On3
– Input b, output x
– Next state signals n1, n0 s
tp
u
o
inputs
outputs
M
S
F
FSM
b x
FSM
Combinational n1
– Any encoding with each state logic
unique will work n0
a
s1 s0
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Controller Design: Laser Timer Example (cont)
• Step 4: Create state table Inputs: b; Outputs: x
x=0
00
Off b’
a
b
x=1 x=1 x=1
01 On1 10 On2 11 On3
outputs
inputs
FSM
FSM
b x
Combinational n1
logic
n0
s1 s0
clk State register
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Controller Design: Laser Timer Example (cont)
• Step 5: Implement
outputs
inputs
FSM
FSM
b x
combinational logic Combinational n1
logic
n0
a
s1 s0
clk State register
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Controller Design: Laser Timer Example (cont)
s
tp
u
o
M
S
F
Combinational Logic
• Step 5: Implement b x
outputs
inputs
combinational logic (cont)
FSM
FSM
n
i
M
S
F
ts
u
p
b x
Combinational n1
logic n1 a
n0
s1 s0
clk State register
n0
s1 s0
x = s1 + s0
n1 = s1’s0 + s1s0’
n0 = s1’s0’b + s1s0’
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Understanding the Controller’s Behavior
x=0 x=0 x=0
00 b’ 00 b’ 00 b’
Off Off Off
b b b
x=1 x=1 x=1 x=1 x=1 x=1 x=1 x=1 x=1
01 On1 10 On2 11 On3 01 On1 10 On2 11 On3 01 On1 10 On2 11 On3
b x b x b x
0 0 0
0 0 1 0 1 1
0 0 1
0 0 1
n1 n1 n1
0 0 1
0 0 0 a
0 1 0
n0 n0 n0
0 1 0
0 0 0
s1 s0 s1 s0 s1 s0
clk clk clk
0 0 0 0 0 1
0 0 0 1 1 0
Inputs:
b
Outputs:
x
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Controller Example:
Button Press Synchronizer
cycle1 cycle2 cycle3 cycle4
clk
Inputs:
bi
Button press
bi synchronizer
bo
Outputs:
controller
bo
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Controller Example:
Button Press Synchronizer (cont)
outputs
inputs
FSM
bi bo
FSM
FSM inputs: bi; FSM outputs: bo Step 2: Create architecture
Combinational
bi’ logic n1
bi
bi’ n0
A bi B bi C bi’ s1 s0 n1 = s1’s0bi + s1s0bi a
n0 = s1’s0’bi
bo=0 bo=1 bo=0 State register bo = s1’s0bi’ + s1’s0bi = s1s0
clk
Combinational logic s
tp
u
o
Step 1: FSM bo
M
S
F
Combinational logic bi
Inputs Outputs
s1 s0 bi n1 n0 bo n1
FSM inputs: bi; FSM outputs: bo 0 0 0 0 0 0
A
0 0 1 0 1 0
bi’ 0 1 0 0 0 1 n0
bi B
bi’ 0 1 1 1 0 1
00 bi 01 bi 10 bi’ 1 0 0 0 0 0 s1 s0
C
bo=0 bo=1 bo=0 1 0 1 1 0 0
State register
1 1 0 0 0 0 clk
Step 3: Encode states unused
1 1 1 0 0 0
w = s1 x
x = s1s0’ y
y = s1’s0
z
z = s1’
a
n1 = s1 xor s0
n0 = s0’
n0 n1
s1 s0
clk State register
Digital Design Step 4: Create state table
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Controller Example: Secure Car Key
Inputs: a; Outputs: r
• (from earlier example)
Wait
r=0 a a’
Step 1
a
K1 K2 K3 K4
r=1 r=1 r=0 r=1 s
tp
u
o
a r M
S
F
M
S
F
Combinational
Step 2
n
i
ts
u
p
logic n2
n1
n0
s2 s1 s0
clk State register
Inputs: a; Outputs: r
000
r=0 a’
a
Step 3
D C
x y
n0=(s1’*s0’)x
n
i
M
S
F
ts
u
p
z Outputs:y, z
A B states
n1 yz=10 yz=10
with
D C outputs
n0 yz=00 yz=01
s1 s0
Inputs: x; Outputs:y, z
State register
clk x
x’ A B yz=10
yz=10 x’ x
Work backwards D x’ C yz=01
yz=00
Pick any state names you want x
states with
outputs and
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Common Pitfalls Regarding Transition Properties
a
a’b
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Verifying Correct Transition Properties
• Can verify using Boolean algebra Answer:
a * a’b
– Only one condition true: AND of each condition pair (for = (a * a’) * b
transitions leaving a state) should equal 0 Æ proves pair =0*b
can never simultaneously be true =0 a
OK!
– One condition true: OR of all conditions of transitions
leaving a state) should equal 1 Æ proves at least one a + a’b
= a*(1+b) + a’b
condition must be true = a + ab + a’b
– Example = a + (a+a’)b
a =a+b
Fails! Might not
be 1 (i.e., a=0,
a’b b=0)
c=0 c=1
– Assume unassigned output clk a
implicitly assigned 0
• Sequential circuits
– Assume unconnected clock b=1 c=1
inputs connected to same
external clock
a
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3.5
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Non-Ideal Flip-Flop Behavior
• Can’t change flip-flop input too close to clock clk
edge
– Setup time: time that D must be stable before edge D
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Metastability clk
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Metastability
• One flip-flop doesn’t completely solve problem
• How about adding more synchronizer flip-flops?
– Helps, but just decreases probability of metastability
• So how solve completely?
– Can’t! May be unsettling to new designers. But we just can’t guarantee a
design that won’t ever be metastable. We can just minimize the mean time
between failure (MTBF) -- a number often given along with a circuit
synchronizers
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Flip-Flop Set and Reset Inputs
• Some flip-flops have D Q’ D Q’ D
AR
Q’
additional inputs Q
Q Q AS
– Synchronous reset: clears Q to 0 R AR
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Initial State of a Controller
• All our FSMs had initial state Inputs: x; Outputs: b
x=0
– But our sequential circuit designs
Off b’
did not
b
– Can accomplish using flip-flops x=1 x=1 x=1
with reset/set inputs On1 On2 On3
• Shown circuit initializes flip-flops to
01 b x
Combinational
– Designer must ensure reset input n1
logic
is 1 during power up of circuit n0
s1 s0
• By electronic circuit design State register
clk
D Q’ D Q’
Q Q
R S
reset
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Glitching
• Glitch: Temporary values on outputs that appear soon after
input changes, before stable new output values
• Designer must determine whether glitching outputs may
pose a problem
– If so, may consider adding flip-flops to outputs
• Delays output by one clock cycle, but may be OK
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Active Low Inputs
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Chapter Summary
• Sequential circuits
– Have state
• Created robust bit-storage device: D flip-flop
– Put several together to build register, which we used to hold state
• Defined FSM formal model to describe sequential behavior
– Using solid mathematical models -- Boolean equations for
combinational circuit, and FSMs for sequential circuits -- is very
important.
• Defined 5-step process to convert FSM to sequential circuit
– Controller
• So now we know how to build the class of sequential
circuits known as controllers
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