Manual T50

Eclipse Ser ies
RF Technology
rfinfo@rftechnology.com.au
August, 2003
Revision 2
T50 Tr ansmitter
Operation and Maintenance Manual
This manual is produced by RF Technology Pty Ltd

10/8 Leighton Place, Hornsby NSW 2077 Australia
Copyright © 2001 RF Technology
1
Contents
1 Operating Instructions 5
1.1 Front Panel Controls and Indicators 5
1.1.1 PTT 5
1.1.2 Line 5
1.1.3 POWER LED 6
1.1.4 TX LED 6
1.1.5 ALARM LED 6
2 Transmitter Internal J umper Options 6
2.1 Serial I/O Parameters 6
2.2 Line Terminations 7
2.3 Exciter Low Battery Level 7
2.4 External PA Parameters 7
2.5 Generate Loop 7
2.6 External Tone Input 7
2.7 External Tone, High Pass Filter Bypass 7
2.8 Transmit Time 7
2.9 Channel Select Override 7
2.10 CWID Start Delay 7
2.11 CWID Period 8
2.11 CWID Message 8
2.9 Channel Selectable Parameters 8
3 Transmitter I/O Connections 8
3.1 25 Pin Connector 8
3.2 9 Pin Front Panel Connector 9
4 Channel and Tone Frequency Programming 9
5 Circuit Description 10
5.1 T50 Master Schematic (Sheet 1) 10
5.2 Microprocessor (Sheet 2) 10
5.3 Audio Processing Section (Sheet 3) 13
5.4 Line Input Processing Section (Sheet 4) 14
5.5 Tone Generation Section (Sheet 5) 15
5.6 Frequency Synthesiser (Sheet 6) 16
5.7 Voltage Controlled Oscillators (Sheet 7) 18
5.8 1W Broadband HF Power Amplifier (Sheet 8) 20
5.9 Power Generation Section (Sheet 9) 20
6 Field Alignment Procedure 21
6.1 Standard Test Equipment 21
6.2 Invoking the Calibration Procedure Manually 21
6.2.1 The “Miscellaneous” Calibration Procedure 22
6.2.2 The “Reference” Calibration Procedure 22
6.2.3 The “Deviation” Calibration Procedure 24
6.2.4 The “Tone Deviation” Calibration Procedure 25
6.2.5 The “Line” Calibration Procedure 25
6.2.6 The “Power” Calibration Procedure 26
7 Specifications 28
2
7.1 Overall Descr iption 28
7.1.1 Channel Capacity 28
7.1.2 CTCSS 28
7.1.3 Channel Programming 28
7.1.4 Channel Selection 29
7.1.5 Microprocessor 29
7.2 Physical Configuration 29
7.3 Front Panel Controls, Indicators and Test Points 29

7.3.1 Controls 29
7.3.2 Indicators 29
7.3.3 Test Points 29
7.4 Electrical Specifications 29
7.4.1 Power Requirements 29
7.4.2 Frequency Range and Channel Spacing 29
7.4.3 Frequency Synthesizer Step Size 30
7.4.4 Frequency Stability 30
7.4.5 Number of Channels 30
7.4.6 Output Power 30
7.4.7 Transmit Duty Cycle 30
7.4.8 Spurious and Harmonics 30
7.4.9 Carrier and Modulation Attack Time 30
7.4.10 Modulation 30
7.4.11 Distortion 30
7.4.12 Residual Modulation and Noise 30
7.4.13 600Ω Line Input Sensitivity 30
7.4.14 Test Microphone Input 30
7.4.15 External Tone Input 30
7.4.16 T/R Relay Driver 31
7.4.17 Channel Select Input / Output 31
7.4.18 DC Remote Keying 31
7.4.19 PTT in 31
7.4.20 Programmable No-Tone Period 31
7.4.21 Firmware Timers 31
7.4.22 CTCSS 32
7.4.23 DCS Codes 32
7.4.24 CWID 32
7.5 Connectors 32
7.5.1 RF Output Connector 32
7.5.2 Power and I/O Connector 32
7.5.3 External Reference Connector (optional) 32
A Engineering Diagrams 33
A.1 Block Diagram 33
A.2 Circuit Diagrams 33
A.3 Component Overlay Diagrams 33
B T50 Parts List (Rev. 4) 34

C T50 Parts List (Rev. 3) 46
D EIA CTCSS Tones 48
3
WARNING
Changes or modifications not expressly approved by RF
Technology could void your authority to operate this
equipment. Specifications may vary from those given in this
document in accordance with requirements of local authorities.
RF Technology equipment is subject to continual improvement
and RF Technology reserves the right to change performance
and specification without further notice.
1 Oper ating Instr uctions
1.1 Fr ont Panel Contr ols and Indicator s

1.1.1 PTT
A front-panel push-to-talk (PTT) button is provided to facilitate bench and field tests
and adjustments. The button is a momentary action type. When keyed, audio from the
line input is disabled so that a carrier with subtone is transmitted. The front-panel
microphone input is not enabled in this mode, but it is enabled when the PTT line on
that socket is pulled to ground.
The PTT button has another function when transmission is keyed up, and the TX LED
light is showing. If there is a “forward power low” alarm (the ALARM LED flashes
three times, then pauses), pressing this will cause the ALARM LED to flash 6, 7, 8, or 9
times before the pause (see Table 2). This will indicate what has caused the low power
alarm.
1.1.2 Line
The LINE trimpot is accessible by means of a small screwdriver from the front panel of
the module. It is used to set the correct sensitivity of either line input or the direct
audio input. It is factory preset to give 60% of rated deviation with an input of 0dBm
(1mW on 600Ω, equivalent to 775mV RMS or about 2.2V peak-to-peak) at 1kHz. By
this means an input sensitivity from approximately -12dBm to +12dBm may be
established.
An internal, software selectable, option, provides an extra gain step of 20dB. This,
effectively changes the input sensitivity to –32 to –8dBm.
LED Flash Cadence Fault Condition
9 flashes, pause External PA failure – reason unknown
8 flashes, pause Low dc supply on External PA
7 flashes, pause External PA Over Current Condition
6 flashes, pause External PA Over Temperature
5 flashes, pause One or both synthesizers could not lock.
4
4 flashes, pause Either PLL is near its operational limit
3 flashes, pause Unable to communicate with the External PA.
2 flashes, pause The current channel is not programmed or the channel
frequency is out of range.
1 flash, pause Low dc supply voltage
LED ON continuously Transmitter timed out
Table 1: Interpretations of LED flash cadence (TX LED Off)
LED Flash Cadence Fault Condition
9 flashes, pause External PA failure (if PTT is pressed)
8 flashes, pause Low dc supply on External PA (if PTT is pressed)
7 flashes, pause External PA Over Current Condition(if PTT is pressed)
6 flashes, pause External PA Over Temperature(if PTT is pressed)
3 flashes, pause Forward Power Out of Range(if PTT is not pressed)
2 flashes, pause Reverse Power ratio exceeded.
1 flash, pause Low dc supply voltage
LED ON continuously Transmitter timed out
Table 2: Interpretations of LED flash cadence (TX LED On)
1.1.3 POWER LED
The PWR LED shows that the dc supply is connected to the receiver and that the
microprocessor is not being held in a RESET state.
1.1.4 TX LED
The TX LED illuminates when the transmitter is keyed. It will not illuminate (and an
ALARM cadence will be shown) if the synthesizer becomes unlocked, or the output
amplifier supply is interrupted by the microprocessor.
1.1.5 ALARM LED
The Alarm LED can indicate several fault conditions if they are detected by the self test
program. The alarm indicator shows the highest priority fault present. See Tables 1
and 2.
2 Tr ansmitter Options
There are NO internal jumpers in the T50.
There are many software selectable options. Some options are selected on a per channel
basis, and some are defined globally (i.e. the parameter is fixed irrespective of which
channel is selected). Below is a description of these global parameters
2.1 Ser ial I/O Par ameter s

There are two serial ports. There is the main serial port which is brought out to the front
panel connector. This is referred to as PORT0. There is another serial port which is for
factory use only. It is referred to as PORT1.
The baud rate, can be defined for PORT0. PORT0 is set by default to 57.6Kbps, with
No parity.
5
2.2 LINE Ter minations
There are two main audio inputs, plus a direct audio (TONE) input. The direct audio
input is a High Impedance Balanced DC input, but the two audio inputs are AC coupled
(> 10Hz) inputs which can be High Impedance(HiZ), or 600 ohm inputs. Each input
can be software selected to be HiZ, or 600 ohms.
2.3 Exciter Low Batter y Level

This is factory set to 24.0V, and defines the level of the DC supply that will cause an
Exciter dc supply low alarm.
2.4 Exter nal PA Par ameter s

There are several user definable parameters associated with the external PA provided
with each exciter.
These are the PA low battery alarm level (default is 26V), the PA Set Forward Power
Level (defaults to 100W), the Forward Power Low Alarm Level (defaults to 90%), and
the Reverse Power Alarm Level (defaults to 25% - corresponding to a VSWR of 3:1).
2.5 Gener ate LOOP

Normally the transmitter will key up if dc current is sensed flowing in either direction
between Line1+ and Line1- (>=1mA). If the LOOP_VOLTS option is set to its non-
default setting, then a 12Vdc supply is applied to the pair through 660 ohms of source
impedance. (It would be expected, normally, that if this option is selected, then the
option to remove the 600 terminator from Line1, would also be selected). If dc current
flows from having applied this potential, then the transmitter will key up.
2.6 Exter nal TONE Input

Normally any signal applied to the TONE+/TONE- pair is ignored. If this option is
selected, then a Direct Audio input will be mixed with any audio received on either of
the other two lines, and with any CTCSS tones, or DCS codes being generated.
2.7 Exter nal Tone High Pass Filter Bypass

Normally the Direct Audio, and the CTCSS/DCS outputs are passed through a 250Hz,
low pass filter. This filter can be bypassed by selecting this option.
2.8 Tr ansmit Time

This parameter defines a maximum time limit for continuous transmission. It is
expressed in seconds and can be arbitrarily large (months in fact). If it is set to zero
seconds, then the transmitter can stay keyed up permanently.
2.9 Channel Select Over r ide

This parameter allows the user to override the channel number that is read in via
connector P3. Normally it is InActive, but if it is set to a value from 0 to 255, then the
exciter will behave as though that channel was hard-wired at the rear.
2.10 CWID Star t Delay

If CWID (Continuous Wave Identification) is enabled, then this value indicates the time
in tenths of a second, from keying up an exciter to when the first station identication
6
message is sent. If this timer value is negative, then CWID transmission is disabled.
This feature is only available on models from Rev. 4.
2.11 CWID Per iod

If CWID (Continuous Wave Identification) is enabled, then this value indicates the time
in tenths of a second from one transmission to the next. If the value is zero, then the
CWID message is transmitted only once. This feature is only available on models from
Rev. 4.
2.12 CWID Message

This parameter allows the user to specify the message string to be transmitted as the
station ID. This feature is only available on models from Rev. 4.
2.13 Channel Selectable Par ameter s

Each channel defines two complete set of parameters. One set of parameters is used
when a transmitter keys up from the PTT-in input, and the other set is used when the
transmitter keys up from the LOOP-in, the PTT switch, or the microphone PTT input.
Each set defines what frequency to use, what CTCSS sub-tone (if any) to use, what
maximum line deviation to use, what tone deviation to use, what transmit delay (a delay
applied from PTT-in or LOOP-in to transmission), what transmit tail (delay from PTT-
in, or LOOP-in, to transmission being stopped, and No-TONE period (a period of extra
transmission in which No Tone is applied after PTT-in or LOOP-in has been released.
As well as these parameters, which Line (or Lines) can be selected, and whether the
lines should have flat frequency response or have pre-emphasis applied. Also, it can
enable or disable, the extra 20dB gain pad.
Note that both Line1 and Line 2 can be selected (each with or without pre-emphasis),
and if so, then the two signals will be mixed, and the Line potentiometer will adjust the
level of them both.
3 Tr ansmitter I/O Connections
3.1 25 Pin Connector

The female D-shell, 25 pin, connector is the main interface to the transmitter. The pin
connections are described in table 3.
Function Signal Pins Specification
dc power +28Vdc(in) 13, 25 +24 to 32 Vdc
0 Vdc 1, 14 Common Voltage
+5Vdc(out) 17 Output for external Logic(100mA)
+12Vdc(out) 15 Output for an external relay(120mA)
Vref 4 Reference voltage for Tests
Serial SCLK 12 Serial Clock
Communications MOSI 6 Bi-directional Data Pin
CH_EN 18 Enables Channel Select Shift Register
PA_CS 24 Enables PA A/D chip
7
SPARE_SEL 5 Spare Select (for future use)
600Ω/HiZ Line Line1+ 8 Transformer Isolated Balanced 0dBm
Input
Line1- 19
600Ω/HiZ Line Line2+ 10 Transformer Isolated Balanced 0dBm
Input
Line2- 22
Direct PTT input 11 Ground to key PTT
T/R Relay driver 23 Open collector, 250mA /12V
output
Sub-Audible Tone Tone+ 9 >10kΩ, dc coupled
Input Tone- 21
Table 3: Pin connections and explanations for the main 25-pin, D connector.
3.2 9 Pin Fr ont Panel Connector

The female D-shell, 9 pin, front panel connector is an RS232 interface for serial
communications to a terminal, a terminal emulator, or to a computer. The pin
connections are described in table 4.
Function Pins Specification Pin name on IBM PC

TXD 2 Transmit Data (Output) RxD
RXD 3 Receive Data (Input) TxD
RTS 8 Request To Send (Output) CTS
CTS 7 Clear To Send (Input) RTS
DTR 6 Data Terminal Ready(Output) DSR
DSR 1 Data Set Ready (Input) DCD
GND 5 GND GND
Table 4: Pin connections for the front panel 9 pin D connector.

The pinout for the connector has been chosen so that a straight-through BD9 male to
DB9 female cable can connect the transmitter to any male DB9 serial port on an IBM
PC compatible computer.
Note that for connection to a modem, a cross-over cable will be required.
4 Channel Pr ogr amming and Option Selection

Channel and tone frequency programming is most easily accomplished with RF
Technology WinTekHelp software. This software can be run on an IBM compatible PC
and can be used to calibrate a T50, R50, and PA50 as well as program channel
information. See the WinTekHelp manual for further information.
8
5 Cir cuit Descr iption
The following descriptions should be read as an aid to understanding the block and
schematic diagrams given in the appendix of this manual.
There are 9 sheets in the schematic in all.
5.1 T50 Master Schematic (Sheet 1)

Sheet 1, referred to as the “T50 Master Schematic”, is a top level sheet, showing five
circuit blocks, and their interconnection with each other, as well as the interconnection
with all connectors and external switches.
JP12 is the connector, on the printed circuit board, for the microphone input.
P3 represents the rear female DB25 connector.
J1 is the nominal 1W RF output (BNC) connector, which is used to connect to the
External Power Amplifier.
J4 is an optional BNC connector for an external reference clock. If an external
reference clock, with power level from +5 to +26dBm is attached here, the firmware
will automatically track the channel VCO to the reference.
Note that the external reference frequency is limited to:
500kHz, or any multiple
any multiple of 128KHz greater than or equal to 512kHz
and cannot be greater than 10MHz in Rev 4 or older versions. In Rev 5, the external
frequency can be as high as 20MHz.
P1 is the front panel DB9 RS-232 connector for attachment to a terminal, a terminal
emulator, or to an IBM PC running the WinTekHelp software.
JP2 is for the attachment of an LCD display module. This has been included for later
development. This connector, is not normally fitted
JP3, and JP4 are specialised connectors for test and factory configuration use only.
RV100 represents the front panel LINE potentiometer.
SW1 represents the PTT test pin.
D102, D103, and D104 represent the three front panel LEDs.
5.2 Micr opr ocessor (Sheet 2)

Sheet 2 describes the basic microprocessor circuitry.
The core CPU is the Motorola XC68HC12A0. It is configured in 8 bit data width
mode.
The CPU is clocked by a 14.7456MHz crystal oscillator circuit (top left) comprising the
JFET Q202, and two switching transistors Q203 and Q204.
The CPU contains an 8 channel A/D converter whose inputs are identified as AN0,
AN1, …, AN7.
AN7 and AN6 are used as LOCK detect inputs from the two Phase Locked Loop (PLL)
circuits (see 5.6)
AN5 is used to sense whether or not the dc supply is within spec or not.
9
AN4 is multiplexed between the LINE control potentiometer and the Channel reference
crystal’s temperature sense. Which analogue input drives this analogue input, is defined
by the state of TEMP_LEVEL_IN which is a CPU output signal.
AN3 and AN1 are inputs from the PLL circuits that sense the bias voltage on the VCO
control varactor for each VCO.
AN2 is used to sense the average peak voltage of the audio input.
AN0 is used to sense the average peak voltage of the RF output.
FRDY is an output from the flash. It goes low when the Flash starts to write a byte of
data, or erase a block, or erase the whole chip, and it returns to its default high state
when the action requested has completed.
FPSW1 is the switch input from the PTT Test pin.
FPSW2, and FPSW3 are two pins that have been reserved for future use as switch
inputs.
LOOP/VOLTS_SEL is a CPU output that when high applies 12V of dc feed to the
audio output.
TONE_DEV_U/D and TONE_DEV_INC are CPU outputs that are used to control the
digital potentiometer that sets the TONE deviation level. (see 5.5)
EXT_TONE_SEL is a CPU output that when low enables differential analogue input
from the TONE+/TONE- pair. (see 5.5)
LINEINP_ADSEL is a serial bus select pin. It selects the quad Digital to Analogue
converter (DAC) that sets the levels for the two Line input Voltage Controlled
Amplifiers, the output RF power amplifier bias voltage, and the LCD bias circuit. (see
5.4)
LINEINP_DSEL is also a serial bus select pin. It is used to select the shift register that
is used to control most of the analogue switches in the audio Line input circuitry, as
well as the digital POT used to set the maximum deviation level. (See 5.4)
PWR_CNTRL_HIGH is a CPU output that can be low, tri-state, or high. This adjusts,
slightly, the range of the power amplifier bias circuitry allowing finer control of the
output power level. (see 5.4 and 5.8)
CTCSS_SEL is a serial bus select pin. It is used to select the FX805 chip(U500), which
is used to generate CTCSS tones. (see 5.5)
CHAN_PLL_SEL is a serial bus select pin. It is used to select the PLL chip in the
Channel PLL circuit (U604). (See 5.6)
SIGGEN_ADSEL is a serial bus select pin. It is used to select the quad DAC in the RF
area. This DAC controls the reference oscillator bias voltages, and the BALANCE
voltage controlled amplifier. (See 5.6)
CHAN_VCO_EN is a CPU output that enables (when high) the Channel VCO. (See 5.6
and 5.7)
EXT_REF_DIV is a CPU timer input. It is the output of the external reference clock
divided by 3200. The software can measure what the reference frequency is, and then
use this input to calculate the frequency error of the channel PLL reference oscillator. It
can then adjust the channel reference oscillator to reduce this error to less than 0.3ppm.
(See 5.6)
SPARE_SEL is a serial bus select. It has been reserved for future use, and has been
brought out to the rear DB25 connector. (see 5.1)
10
CH_EN is a serial bus select. It is brought out to the rear panel and is used to interface
to the channel encoder on the rear daughter-board. (See 5.1)
Any GPS pulses are isolated from the on-board electronics by the opto-isolator U212.
The output of that opto-isolator is then connected to the GPS timer input of the CPU.
This has been included for future use to be able to auto-adjust the reference oscillator
frequencies to low, or high frequency clock pulses from an external clock reference of a
GPS receiver.
TERM_EN2 and TERM_EN1 are used to enable (when low) 600 ohm termination of
Line2, and Line1 respectively. (See 5.3)
The Fo outputs from the Modulation PLL and the Channel PLL are divided by two, and
these are called FO_MOD_2 and FO_CHAN_2 respectively. They should be 200Hz
square waves, except for brief periods when frequencies are being changed. (See 5.6)
ECLK is a pin that at start-up only, should have the CPU system clock of 7.3728MHz
on it.
TX_LED, ALARM_LED, are CPU outputs that drive (when low) the TX LED, and the
ALARM LED on.
T/R_RELAY_H, when high, drives the T/R RELAY output low, and also enables the
RF power amplifier. The T/R RELAY output can activate at least one conventional
12V relay. (See 5.1)
SCLK, and MOSI are used as the core of a serial bus. SCLK is a clock pin, and MOSI
is a bi-directional data pin.
PA_CS is a serial select pin. It is passed, via the rear DB25 connector to the External
Power Amplifier (PA). (See 5.1)
DBGTX_TTL, DBGRX_TTL are RS232 transmit and receive (TTL) data pins which
are connected to the debug port after conversion to/from RS232 compatible voltage
levels by U202 and U201.
TXD_TTL, RXD_TTL, RTS_TTL, CTS_TTL, DTR_TTL, DSR_TTL, are RS232 data
pins which are connected to the main front panel serial port after conversion to/from
RS232 compatible voltage levels by U202 and U201.
PTT_uPHONE is a CPU input and it reflects the state of the PTT pin on the microphone
handset.
TONE_INT is a CPU input that comes from the FX805 (U500). This pin is used to
indicate when a Tone has been decoded, or there is some other need to service the
FX805. As yet, this pin is not used in the T50. (See 5.5)
LOOP_DET is a CPU pin that is asserted low if there is dc loop current detected
through the centre tap input of Line2. (See 5.3)
FILTER_OFF is a CPU output that is used to by-pass, when low, the low pass filter in
the Tone Input Circuitry. (See 5.5)
PTT-in is an input from the rear DB25 connector that causes the INT pin of the CPU to
be asserted (low) when 1mA of current is drawn via that pin. If PTT-in is pulled to
ground, through a resistance of at most 3.9kohms, it will cause INT to be asserted. If it
is pulled low via a 2K2 resistor, and as many as three diodes in series, it will still cause
the INT pin to be asserted. This latter example shows that quite complex diode logic
can be used on this pin.
BKGD is a bi-directional I/O pin used to communicate with the core of the CPU. It is
connected to the debug port and is utilised by specialised hardware to control the CPU
externally, even without any firmware being present in the Flash.
11
MORSE is a CPU output that can be used to generate a CWID (Continuous Wave
Identification) code. This is a 1028Hz tone which is keyed on and off in a Morse code
as a staion identifier. (See 5.4)
The RESET pin is both a low active input and a low active output to the CPU. If
generated externally to the CPU, it forces the CPU into reset, and if the CPU executes a
RESET instruction, this pin will be driven low by the CPU.
Whenever there is insufficient volts (< 4.65V) on pin 2 of the MC33064D (U203), it
will keep its RES output low. After the voltage has met the right level it will assert its
output low for another 200 milliseconds. Thus the CPU will be held in reset until VCC
is at the correct level. Thus the PWR_OK LED will only light when VCC is within
specification, and RESET has been released.
S200 is a momentary push-button switch that, when pressed, will cause the CPU to be
reset.
MOD_PLL_SEL is a serial bus select pin. It is used to select the Modulation PLL chip
(U602). (See 5.6)
LCD_DB7, LCD_RS, LCD_R/W, and LCD_E are reserved for interfacing to an LCD
display module. Note that this feature has not been implemented.
U205 is used to select whether the Flash or RAM is to be read or written.
U207 is a single supply, 5V, TSOP40 Flash chip of size 8, 16, or 32 Megabits, and is
used to store the firmware.
U208 is a 1, or 4, Megabit Static RAM in an SOP-32 package, and is used for both code
and data. The code in the RAM is copied from the Flash, at start-up.
5.3 Audio Pr ocessing Section (Sheet 3)

Sheet 3 is a schematic, which itself refers to two other sheets.
Sheet 3 shows how the two Line inputs go to audio transformers T300 and T301, are
then optionally terminated by analogue switches U301B, and U301C, before being
passed to the audio input stages described by Sheet 4.
It also shows how the Direct Audio (TONE) signal is passed to the Tone circuitry (sheet
5).
It also shows how dc current in Line1 will cause the opto-isolator (U300) to generate
the CPU input LOOP_DET.
Relay RL300 is used to drive current back through an externally generated dc loop,
when the CPU output LOOP/VOLTS_SEL is high.
The output of the Tone circuitry and the Audio circuitry are mixed (summed) and
amplified by U302. It is then passed through a high order low pass filter (3.1kHz),
before being attenuated by digital POT U303.
U403D adds an extra 1.8% gain of the summed modulation signal. It effectively adds
another bit of control to the maximum deviation level.
The Digital POT (U303), in conjunction with U403D, set the Maximum deviation.
U302C then adds 6dB of gain before sending the audio to the modulator.
R317, D307, and C304, act as an average peak detector. This enables the CPU to
determine the size of signals being handled by the audio section.
12
Note that the Line inputs, and the TONE input, are protected by transils and fuses
against accidental connection to damaging voltages. The fuses (F300, F301, and F302)
are not user replaceable. They are surface mount devices and must be replaced by
authorised service personnel.
5.4 Line Input Pr ocessing Section (Sheet 4)

The two audio inputs are passed, after transformer coupling, to sheet 4.
In Sheet 4, the two Line Inputs are input to a transconductance amplifier (U402A, and
U402B). A transconductance amplifier is a current controlled, current amplifier, i.e. it
amplifies input current, but its level of amplification is controlled by the level of current
that is injected into pin1 (or pin16). By converting a DAC output into a current, and
converting the input voltage into an input current, U402A and U402B are converted into
Voltage Controlled, Amplifiers(VCAs).
Two of the DAC outputs are converted to currents by U400B, U400C, Q401, and Q400,
and these currents are used to control the gain of the transconductance amplifiers.
The input voltages are converted to current by the input load resistors R402, and R403.
The output currents are converted to voltages by resistors R420 and R424.
The outputs of the transconductance amplifiers are buffered by the darlington buffers
provided with the amplifiers (U402C, and U402D).
The output of each VCA is then amplified by U405B and U405C respectively.
The level of amplification of each VCA is adjusted in software in accordance with any
adjustments made to the LINE POT. The software converts the linear range of the
LINE POT into a logarithmic scale, such that if the LINE POT is wound down to zero,
the amplification of each VCA is reduced by 12db relative to its centre position.
Similarly if the POT is wound to its maximum position, both amplifiers increase their
gain by 12dB.
The outputs of these amplification stages are then attenuated. Analogue switches
U404A and U404Bare used to select which attenuation circuit is used for Line 2, and
U404D and U404C are used to select which attenuation circuit is used for Line 1.
If the resistive divider formed by R425, R426, and R439 is selected then the Line 2
audio signal frequency response is unaffected (it is Flat). If the reactive divider defined
by C402, R431, and R439 is selected, then higher frequencies of the Line 2 audio signal
are attenuated less than lower frequencies, i.e. Pre-emphasis is applied to the audio
signal.
Line 1 has an identical circuit.
The outputs of these pre-emphasis/flat frequency response attenuators are then buffered
by U405A, and U405D respectively.
The microphone input is amplified by U400D, after being limited by D400. It is passed
through a pre-emphasis network (defined by C404, R433, and R436), and is enabled, or
disabled by switch U403A.
The outputs of the Line 1 conditioning circuit, the Line 2 conditioning circuit, and the
microphone input amplifier, are then mixed (summed) and amplified by U407A. Its
output is, in turn, amplified by U407B, but the gain of U407B is either 2.7 or 27
depending on the state of analogue switch U403B.
The CPU is capable of injecting a signal into the audio path. This can be achieved via
the MORSE output. This is partially filtered by R446 and C421. C420 provides DC
13
isolation, and R446, and R448 set the level to be approximately 30% of maximum
deviation.
The output of U407B is passed (signal LINE_INP) to the Line Level Sense circuitry
(sheet 3) so that the CPU can determine the input line level.
U407B’s output is also passed to the limiter defined by D402, and D401. Resistors
R442, and R444 are used to “soften” the clipping, i.e. to “round off” the edges as the
voltage hits the clipping levels. This reduces the level of the lower order harmonics
produced.
U407C then buffers the output for mixing with the tone output circuitry.
The PWR_CNTRL_RAW DAC output is used to control the bias to the on-board RF
amplifier (see Sheet 8). The CPU output pin PWR_CNTRL_HIGH is effectively
summed with the DAC output to define three control ranges:
State of PWR_CNTRL_HIGH PWRCNTRL Voltage Range
TriState 2.98 – 5.86
Low (0V) 0.6 – 3.0
High (5V) 3.55 - 5.96
Table 9: Power Control Ranges.

Note that in practice only the first two power ranges are used.
U401 is an octal shift register and octal latch combined. When there is a rising edge on
LINEINP_DEN, the 8 shift register outputs are latched into the octal latch. The outputs
of the octal latch are the outputs Q0 to Q7. Thus the last 8 data bits clocked onto MOSI,
by SCLK, before LINEINP_DEN is clocked high, will appear on Q0 to Q7.
U406 is a quad 8 bit DAC. The CPU communicates with the DAC via SCLK, MOSI,
and the select signal LINEINP_ADSEL, which is low when the DAC is selected.
U302B is used to convert the DAC output into a bias level for the LCD. Note that, at
this stage, the LCD display option is not developed.
5.5 Tone Gener ation Section (Sheet 5)

U500 is a CTCSS tone encoder and decoder. The integrated circuit is also capable of
generating DCS signals.
The CPU accesses U500 via the serial bus using MOSI, SCLK, and the low active
Select signal CTCSS_SEL.
The output of the tone generator is mixed (summed) with any signals that are allowed
through analogue switch U301D.
U502 is set up as a balanced differential amplifier. The resistors R530, R531, R508,
R509, R510, R532, R533, and R511, are precision resistors to improve the CMRR of
the differential amplifier.
U502A amplifies, as well as mixes, the two audio inputs, and its output is either passed
through a low pass filter (at 250Hz), or not, depending on the state of analogue switch
U301A.
The output of U502C is then attenuated by a digital POT, before being buffered by
U502D.
14
The digital POT performs two functions. It is used to help set the maximum CTCSS
tone deviation. It does this in conjunction with U500, as it is also possible for the
CTCSS tones that are launched by U500 to be adjusted using software.
The second function of the digital POTs is enabled when U301D is enabled. The level
of attenuation by the digital POT is adjusted as part of the calibration procedure to set
the tone deviation caused when a signal is applied to the tone input.
R526, D502, and D503, form a limiter, that prevents any signal arriving from the TONE
pair from ever exceeding 3kHz deviation.
5.6 Fr equency Synthesiser (Sheet 6)

This circuit also includes Sheet 7 as a block diagram. Sheet 7 contains the schematic
for the two Voltage Controlled Oscillators.
There are two complete Phase Locked Loops. One is called the Modulation PLL, and
the other is referred to as the Channel PLL.
The Modulation PLL does change frequencies slightly, but by less than +/- 240kHz.
The Channel PLL is the principal PLL that changes frequencies when the exciter
changes frequency.
As its name suggests, modulation is performed on the Modulation PLL.
The modulation is a conventional 2 point FM modulation. Modulation by signals,
whose frequency components are well below the PLL loop frequency, is effected by
modulating the reference oscillator of the Modulation PLL. Frequencies well above the
PLL loop frequency are effected by modulating the Modulation VCO directly, and
frequencies in the cross-over region are a combination of the two.
The heart of this schematic are the two PLL chips U602, and U604.
Each is, in fact, a dual PLL chip, but only one PLL, in each, is used. All that is used of
the second PLL chip is its dividers. The outputs of these dividers can be switched to the
FoLD output pin, which is then converted to a square wave by a further division of 2 by
U606A and U606B.
By using the second PLL’s dividers it is possible to divide the reference oscillator, and
the VCO output down to frequencies that can be handled by the Timer inputs of the
CPU, without causing excessive interrupt load to the CPU.
5.6.1 The Modulation PLL
U602 and the Modulation VCO (see Sheet 7) form the modulation PLL. U602 acts as
its own crystal oscillator for its reference oscillator. X600 is a 5ppm, 12MHz, crystal.
Its resonant point is adjusted by the bias applied to varactor D600.
The bias applied to varactor D600 is a combination of the potentials at two DAC
outputs (MOD_ADJ and MOD_ADJ_FINE), plus the modulating signal arriving at
MOD_IN (which is the same signal as MOD_OUT in Sheet 3).
The summing of these three voltages is performed by U607.
The Phase detector output of the PLL chip is then passed through the loop filter network
defined by C612, R618, C625, R617, C613, and C718 (see Sheet 7). L713 is used to
filter out any residual noise (outside of the audio bandwidth), including the phase
detector frequency, and/or any switch-mode noise from the dc voltage rails.
The loop filter signal is then fed as a control voltage to the Modulation VCO
(MOD_PLL_IN).
15
The output of the Modulation VCO is connected back to the PLL for phase detection via
signal path MOD_VCO_OUT.
The phase detector output is also buffered and attenuated for the analogue input of the
CPU. This is the function of U600, R622, and R625. In this way the CPU can monitor
the VCO bias to ensure that it is within specification (>0.5V, and < 4.5V).
The FoLD pin, of U602, can be used for many purposes. It can be connected to the
output of any of the 4 internal dividers, or be used as a LOCK-DETECT monitor, or as
a user programmable output pin. In this circuit it is used as a LOCK-DETECT output
when the frequency is being changed, but otherwise it is connected internally to the
unused reference divider of U602, to deliver a 400Hz pulse train to FoLD.
U602 is set up with a phase detector frequency of 20kHz.
5.6.2 The Channel PLL
U604 and the Channel VCO (see Sheet 7) form the Channel PLL. U604 acts as its own
crystal oscillator for its reference oscillator. X601 is a 5ppm, 12MHz, crystal. Its
resonant point is adjusted by the bias applied to varactor D601.
The bias applied to varactor D601 is adjusted by the CHAN_ADJ DAC output.
The Phase detector output of U604 is then passed through the loop filter network
defined by C622, R620, C626, R619, C623, and C725 (see Sheet 7). L718 is used to
filter out any residual noise (outside of the audio bandwidth), including the phase
detector frequency, and/or any switch-mode noise from the dc voltage rails.
The loop filter signal is then fed as a control voltage to the Channel VCO
(CHAN_PLL_IN).
The output of the Channel VCO is connected back to the PLL for phase detection via
signal path CHAN_VCO_OUT.
The phase detector output is also buffered and attenuated for the analogue input of the
CPU. This is the function of U608, R623, and R624. In this way the CPU can monitor
the VCO bias to ensure that it is within specification (>0.5V, and < 4.5V).
The FoLD pin, of U604, can be used for many purposes. It can be connected to the
output of any of the 4 internal dividers, or be used as a LOCK-DETECT monitor, or as
a user programmable output pin. In this circuit it is used as a LOCK-DETECT output
when the frequency is being changed, but otherwise it is connected internally to the
unused reference divider of U604, to deliver a 400Hz pulse train to FoLD.
U604 is set up with a phase detector frequency of 31.25kHz.
The signal CHAN_VCO_EN is an output from the CPU that is used to turn on (when
High) or turn off (when low) the Channel VCO.
5.6.3 The External Reference Divider
The external Reference Input (EXT_REF_IN) is buffered by an attenuator network
formed by R628,R633, and R630 in parallel with R635. This also forms a 50 ohm
termination network for the reference input.
R628 is a 1 watt resistor, and so, in theory levels as high as +30dBm can be accepted.
To be safe, though, the largest signal that is approved to be accepted is +26dBm.
Q600 is set up as a switching transistor, and with a sufficiently high input signal level (>
+5dBm), it will clock U605.
U605 is set up as a divide by 128 circuit, and its output is then divided by U606 by 25.
16
The two unused, divide by two, stages of U606 are then used to convert the 400Hz
FoLD pulse trains into 200Hz square waves for the Timer inputs of the CPU.
5.6.4 The DAC
U601 is a quad DAC. It is programmed by the CPU via the serial bus (SCLK and
MOSI). It is selected by the low active signal SIGGEN_ADSEL.
Three of its outputs are used to adjust the reference oscillators.
In the presence of an external reference oscillator, the software will automatically track
the channel VCO to the external clock.
The modulation reference oscillator is always tracked as closely as possible to the
Channel reference oscillator. Because of this need for very close tracking, two DAC
outputs are summed. In this way, the CPU is given coarse, as well as fine control.
The CPU can sense a phase difference of 136ns in 4 seconds, i.e. as little as 0.034ppm
between the two PLL reference oscillators. Each step of the MOD_ADJ_FINE DAC
output will move the frequency about 2% of this amount.
The other DAC output (BALANCE) is used to adjust the BALANCE VCA (see sheet
7).
The user programmable digital output of the DAC (MOD_VCO_EN) is used to enable
the modulation VCO (when High)
5.6.5 The VCOs and the RF Output
These are more closely described in 5.7, but it is worth noting that there are three
primary outputs of the VCOs. There is each VCO output itself, but also the signal
VCO_OUT. This is the difference frequency between them.
Generally the modulation VCO is set to oscillate at 320MHz. To get an output of
40MHz, the Channel VCO is set to 280MHz.
But if you wanted an output frequency of, for example, 40.00125MHz, then the
modulation VCO would change to 319.78125 MHz (i.e. it drops by 218.75kHz), and the
Channel VCO would become 279.78MHz (i.e. dropping by 220kHz).
By such small changes in the modulation VCO (maximum delta is +/- 240kHz), each
multiple of 1250Hz can be accommodated, without any need to ever change the two
phase detector frequencies.
5.7 Voltage Contr olled Oscillator s (Sheet 7)

JFETS Q704, and Q705 are the heart of two Colpitts oscillators.
The capacitor feedback divider for Q704 (modulation VCO) is defined by C732 and
C733, and this shapes the negative impedance looking into the drain of Q704.
In the Channel VCO, C740 is effectively in series with Cgs of Q705. These, then define
the negative impedance looking into the drain of Q705.
L716, in parallel with L726 forms the tank coil for the modulation oscillator, and the
resonant capacitance is defined by the series combination of C750 and the capacitance
across D701. L712 has +ve reactance and it acts to reduce the minimum effective
capacitance seen back through C750, thereby increasing the tuning range slightly.
Similarly, L719 is the tank coil for the channel oscillator, and the resonant capacitance
is defined by the series combination of C751 and the capacitance across D704. L717
has +ve reactance and it acts to reduce the minimum effective capacitance seen back
through C751, thereby increasing the tuning range slightly.
17
The VCO frequencies are controlled by the bias applied to D701 and D704 respectively,
which is set by signals MOD_PLL_IN and CHAN_PLL_IN. These signals are the
phase detector outputs from the Modulation PLL and the Channel VCO respectively
(see Sheet 6).
Diodes D700 and D703 are used to provide some AGC for the JFETs. These Schottky
diodes will increase the –ve bias on the gate of the JFETs (thereby decreasing the drain
current) if the oscillation level should increase, and similarly the gate bias will reduce if
the –ve peaks of the oscillation should reduce.
The Modulation bias is also adjusted by the modulation input (MOD_IN). This signal is
amplified by a VCA. The BALANCE DAC output is converted to a current by U707
and Q700, and that then is used to set the gain of the VCA. The output of the VCA is
then attenuated by R725/R729, and this bias is then applied to varactor D701. Note that
the modulation bias is in anti-phase to the PLL bias.
Each VCO has its own gyrator feed circuit (Q707 and Q702). This is done to remove
any possible noise on the voltage rails from modulating either VCO.
The drain current of each VCO can be switched off or on by MOSFETs Q701 and
Q703. Q701 is switched on when MOD_VCO_EN is high. MOD_VCO_EN is the user
programmable digital output from DAC U601 (see Sheet 6). Q703 is switched on when
the CPU output CHAN_VCO_EN (see Sheet 2) is high.
The output of each VCO is “sniffed”, by a high impedance attenuator. In the
modulation VCO, R737 in series with the 50 ohm input impedance of U702 forms this
attenuator. In the Channel VCO, R745, R736, and the input impedance of U706 form
one such attenuator, and R741 in series with the input impedance of U703 forms the
other. Note that there is a low pass filter in the front of U702, and U706 to reduce the
level of spurious signals generated by intermod in these two amplifiers,
U702 amplifies the modulation VCO signal, which is then amplified again by U701,
then filtered to reduce harmonics, before arriving at the LO input of MX700 at a level of
around +5 - +7dBm. The output of U702 also has a low pass filter to reduce the level of
harmonics arriving at the mixer.
The output of the MOD VCO is also attenuated by R733, and then re-amplified before
becoming MOD_VCO_OUT. MOD_VCO_OUT is then passed to the Modulation PLL
(U602, see Sheet 6).
U705’s primary role is to ensure that noise that becomes coupled by the PLL chip, back
onto its VCO input, does not couple back into the path to the mixer. If this isn’t done,
then the mixer’s LO input contains many harmonics of the reference oscillator.
U703 performs both an amplification role, and an isolation role similar to U703’s. Its
output (CHAN_VCO__OUT) is fed back to the Channel PLL (U604, see Sheet 6).
The output of U706 is attenuated by the network R714, R742, and R724, and it is
filtered to reduce harmonics as much as possible. This filtered VCO output is then
brought to the RF pin of the mixer at a level of about –19dBm.
The output of the mixer is then run through a low pass filter to remove frequencies other
than (Fmod - Fvco). U700 then amplifies this signal to a level of about –6 to –8dBm.
The external output signal of T/R_RELAY, which is asserted low whenever the exciter
is keyed up, is used to switch MOSFET Q706 off. When Q706 is off, amplifier U700 is
enabled. When T/R_RELAY is high, then U700 is deprived of bias current and
VCO_OUT is then completely disabled.
18
5.8 1W Br oadband HF/VHF Power Amplifier (Sheet 8)
The RF output of Sheet 7 (VCO_OUT) becomes the primary input to this circuit
(RF_IN).
This RF input is first amplified to a level of about +2 to +4dBm by U800, then it is
amplified by Q801 to about +20dBm (with full bias), and then it is amplified by Q804
and Q805 to +30dBm. The output stage gain is less above about 42MHz, so that the
peak output power falls to about +26dBm at 50MHz.
The effective gain of Q801 is controlled by adjusting the bias level (PWRCNTRL).
This can vary from 0.6V to nearly 6V, and is adjusted by a DAC output and a CPU
digital output, in Sheet 4.
The software monitors the forward power sense in the External Power Amplifier(PA) as
well as the Reverse Power, temperatures, drain currents etc. It does this via the serial
bus (formed by SCLK and MOSI) and the select pin for the ADC converter on the
External PA (PA_CS).
The software then automatically adjusts the PWRCNTRL bias to:
1) Keep the forward power at the level defined by parameter PA_SET_FWD_PWR
(see 4.1), unless,
2) If the reverse power is > PA_SET_FWD_PWR*REV_PWR_ALARM/100.0
then the forward power is reduced until the reverse power stops exceeding this
limit, or,
3) The temperature of the PA output stage FETs exceeds 120C, in which case
forward power is reduced until this stops occurring.
5.9 Power Generation Section (Sheet 9)

There are three switch mode dc-dc converters in the board. These use monolithic
converters based on the National LM2595. Two of the converters are 12V converters
and one is a 5V converter.
The power in to the whole exciter is the voltage rail 28V.
U907 converts this down to 12V.
U908 is set up as an inverter, and uses the 12V rail to create –12V.
U909 converts the +12V rail to +5V for all the digital circuitry.
The +12V rail is used to power the on-board relay, as well as up to one extra off-board
relay. It is also dropped, via a linear regulator (U910) to produce the +10V rail, which
in turn is dropped by another linear regulator U911 to produce +5Q, which, in turn, is
dropped by a further linear regulator (U912) to produce +2.5V.
Similarly U913, U914, and U915 are linear regulators that produce –10V, -5V, and –
2.5V from the –12V output of U908.
+10, +5Q, and +2.5V, -10V, -5V, and –2.5V rails are used in the audio and RF sections.
D911 is a 4.096V (3%) reference diode. Its output is buffered by U906 which then
produces a reference voltage rail Vref, which is used by the CPU’s A/D converter, and
the DACs, and also in the voltage to current converters of the VCAs (see Sheet 4, and
Sheet 7).
19
6 FIELD ALIGNMENT PROCEDURE
6.1 Standar d Test Equipment

Some, or all of the following equipment will be required:
• AF signal generator, 75 - 3000Hz frequency range, with output level set to 387mV
RMS and, if the microphone input is to be tested, 10mV rms output.
• Power supply set to 28Vdc, with current >10A.
• RF 50Ω load(s), 250W rated, return loss <-20dB, and total attenuation of 50dB
• Reference Clock. At least +6dBm output.
The external reference frequency is limited to:
500kHz, or any multiple,
any multiple of 128KHz greater than or equal to 512kHz,
In Rev 4 or earlier revision systems, the external reference clock is limited to 10MHz.
In Rev 5 or later systems, the external reference clock can be as high as 24 MHz, and
can have an output level as low as 0dBm. The accuracy should be at least 0.5ppm,
preferably 0.1ppm
• RF Peak Deviation Meter
• True RMS AC voltmeter, and a DC voltmeter.
• RF Power Meter (accurate to 2%, i.e. 0.17dB)
• Some means of measuring Reverse Power, and a known 3:1 mismatched load.
6.2 Invoking the Calibration Pr ocedur e Manually

From Version 4 of the firmware, and version 1.4 of WinTekHelp, the calibration
procedure can be performed through a Windows front end program. This is
documented in the WinTekHelp manual.
As well as the Windows based calibration procedure, the firmware still supports the
older command prompt method, which is described in this section.
The T50 has in-built firmware to perform calibration. This firmware requests the user
for information as to meter readings, and/or to attach or adjust an AF signal generator.
The firmware based calibration program can be accessed from a terminal, a terminal
emulator, or the WinTekHelp terminal emulator.
If the user selects the “Go to the Prompt Window” option from the main menu, they can
manually type commands to invoke the calibration procedure. When the exciter is
ready to accept commands it echoes the following prompt:
T50>
Via a terminal, or a terminal emulator, a user can type various commands in. The basic
command to start the calibration procedure is:
T50> cal calibration_type
Where “calibration_type” is one of:
a) misc: Miscellaneous parameters are defined and calibrated
20
b) dev: Maximum deviations are set (automatically forces a “cal line” and a “cal
tone”)
c) line: Line1, Line 2, Dir Aud (Tone), and microphone inputs are tested and
calibrated.
d) pwr: The External PA attached to this unit is calibrated.
e) ref: The reference oscillators are adjusted and calibrated
f) tone: The maximum tone deviations are calibrated
6.2.1 The “ Miscellaneous” Calibration Procedure
T50> cal misc
This procedure should not normally be invoked as part of any field maintenance.
The program will print out the Model Name and Serial Number of the exciter. If these
parameters haven’t already been defined (e.g. at an initial calibration, at the factory, the
service personnel will be prompted to enter these values).
Then it will ask the operator to enter the value of Vref (as measured at TP913, see 5.9).
Measure the voltage, at TP913 (Vref)
and type it on the command line...
Unless the reference diode D911 has been replaced, this should not be done. The user
should simply hit the Enter key to bypass this operation. If, though, D911 has been
replaced for some reason, then, the reference voltage can be measured either on TP913
or pin 4 of P3.
Then the exciter low battery alarm level will be asked for. If the current value is
acceptable, the User need only hit the Enter key on the keyboard. If another value is
preferred, then that value can be typed in.
For example:
The Exciter's Low Battery Alarm is 24V
If this is correct enter < RET> ,
else enter the new value: 26
In this example, the low Battery Alarm level is changed to 26V.
Then the user will be prompted for serial port baud rates, parities etc. At present only
No parity and No flow control are supported. The WinTekHelp software will expect
57600 BPS, and No Parity, and No Flow Control. Note well, that if you do change any
of these, the change will not take effect until you power down the exciter and then
power it up again. (As an alternative to power cycling the exciter, and if the cover is off
the exciter, you may simply press the momentary push-button switch S200 (see 5.2).
The next thing the calibration program tests is the state of the LINE pot. The program
will ask the user to adjust this pot. If the Potentiometer is below centre, it will ask the
user to adjust it up (i.e. adjust it clockwise). If it is above centre, it will ask the user to
adjust it down (i.e. adjust it counter clockwise). When the POT has been centred, or,
the User hits the Enter key, the program will terminate.
This last step is normally only done as part of a factory install, and it is done to ensure
that the POT is centred before being shipped to customers. For field maintenance
purposes, the step should be skipped in order to leave the LINE POT at the setting
formerly desired.
6.2.2 The “ Reference” Calibration Procedure
T50> cal ref
21
To compensate for crystal ageing and other component parameters that drift over time,
the following procedure should be performed approximately once per year.
If your exciter is fitted with the external reference option (an extra BNC connector on
the rear panel), the user can connect an external reference directly to the rear BNC
connector. If the exciter does not have this option, then the top cover of the exciter
should be removed and an external reference oscillator should be connected via a 50
ohm probe to J4 (just to the right of the DC voltage regulators and converters).
The external reference clock, should have a power level from +6 to +26dBm and any
frequency that meets the following criteria:
500kHz, or any multiple, or,
any multiple of 128KHz, greater than or equal to 512kHz, or,
any multiple of 160KHz, greater than or equal to 480kHz.
The frequency should be 10MHz or less in Rev 4 or older versions. In Rev 5, and later
versions the frequency can be as high as 24MHz, and at power levels as low as 0dBm.
No User input is required, except to hit the Enter key when the external reference is
connected. The firmware will automatically adjust both reference oscillators, and save
the new DAC adjustments in FLASH (as parameters) to be used to centre the oscillators
each time the unit powers up.
The user should see the following output. (Note that the temperatures, frequencies,
error values, serial number, etc, indicated are examples only)
Connect an external reference input or the clock output

from a GPS receiver to the GPS input.
Enter < RET> when this has been done.
External Reference is 10.0MHz
Ensure that the displayed reference frequency (10.0MHz in the above example) is the
same as the frequency of your oscillator.
Waiting for a GPS clock.
......
The system waits here for a GPS reference to be seen. At this stage, this method of
calibrating the clocks has not been validated by RFT Engineering, so do not attempt to
use this option.
Then the firmware continues.
Have not observed a GPS clock
System Frequency relative to external clock is 7372654.32
The crystal temperature is 32C.
Waiting up to 1 minute for clocks to stabilise.
......
The crystal temperature is 32 C
The channel ref error = 1 cnts or, 1.63 Hz
The mod ref error = 1 cnts or, 1.63Hz
The user may see the following error message.
The Model Name is T50_REV4
and the Serial Number is RT11500
Please take note of the Model, DAC values, serial number and
crystal temperature, and report this problem to RFT Engineering.
22
If a message, similar to this is seen, it indicates a potential fault condition. If the final
text indicates that the channel and mod reference errors are within specification (the last
text output), then the unit is able to be used, but nonetheless, it is advisable that an e-
mail be sent to RF Technology indicating the problem. Such a problem may be caused
by a crystal having aged to such an extent, that it is getting close to the region where it
may soon, no longer be adjusted, or that, with further degradation, the low frequency
performance may be compromised.
As no other calibration procedure requires the top cover to be removed, you should
replace the cover, should you have had to remove it for this procedure.
6.2.3 The “ Deviation” Calibration Procedure
T50> cal dev
This procedure should not normally be invoked as part of any field maintenance. The
only conceivable time that it might ever be used, would be if a non standard maximum
deviation was required.
Note that the nominal output power of the exciter’s output is 1W. Whilst the power
level is not set to the maximum level, the deviation meter should either have an input
power rating of at least +30dBm, or suitable attenuation is required between the exciter
and the deviation meter. Note that for this test the nominal RF output frequency is
37.5MHz.
The first stage begins with the following message:
This procedure sets the Balance and Max Deviation Levels
Connect an audio signal generator to the External Tone input
Set the output to be a sine wave, 3.87 V rms and 120Hz
Disconnect the RF connection to the PA
and connect a deviation meter to the exciter's BNC output,
and use a CRO to monitor the Audio output from the deviation meter.
The Channel VCO Bias is 2.5V
The Modulation VCO Bias is 2.3V.
Enter + or – to increase or decrease the Balance, until the
CRO signal is as symmetric as possible.
?
Here the user can hit the +, p, or P, keys to increase the Balance, or -, m, or M keys to
decrease it. In response, the firmware, which has opened up the maximum deviation
digital POT (U303) to maximum gain, will adjusted the Balance VCA accordingly.
This test applies a very high level to the External Tone Input which becomes “saturated”
by the limiter for the Tone input. The result is a square wave with a slight ring on the
edges. The ringing is caused by the elliptical filter used as a 3kHz low pass filter.
If the modulation balance is not working properly, the top edges of the resulting
modulated signal will be slewed.
Then the firmware will make the following request.
change the signal input to Line 1, and adjust the frequency till the
deviation peaks
When this has been done, the User needs to hit the Enter key, and the following will
appear again.
Enter + or - to increase or decrease the deviation,
and < RET> when the deviation is 5kHz
23
?
In response to the +, or – keys (or m, p, M, or P), the firmware adjusts the deviation
digital POT. The user should do this until the deviation is about 200Hz below the value
shown.
The firmware will now repeat this for the following standard deviations, 5.0kHz,
4.5kHz, 4.0kHz, 3.5kHz, 3.0kHz, 2.5kHz, 2.0kHz, and 1.5kHz.
6.2.4 The “ Tone Deviation” Calibration Procedure
T50> cal tone
This procedure should not normally be invoked as part of any field maintenance.
Note that if the deviations are calibrated, then this procedure will be automatically
invoked.
This procedure is similar to the maximum deviation procedure (See 6.5). The Line 1
and Line 2 audio paths are turned off for this procedure, as is the Direct Audio (TONE)
input. The only signal sent to the modulator is a tone of 107.2Hz.
The program starts off, with the following message:
This procedure sets the maximum tone deviations for a
Max Deviation of 5kHz. Note that the actual maximum
tone deviations automatically scale with the Max Deviation.
eg a 500Hz tone deviation would be a 250Hz tone deviation
when a 2.5kHz Max Deviation was chosen.
Disconnect the RF connection to the PA,
and connect a deviation meter to the exciter's BNC output.
The audio is being switched off, and 107.2Hz tone generated
Thence a procedure that is almost identical to that used for setting maximum deviations
is used to set these tone deviations. There is one significant difference, though, and that
is, as well as using + (or p, or P), and – (or m, or M) keys to step the deviation up or
down, one can also use the < key, or the > key. These last two keys will step down, or
up, the level of signal transmitted by U500, whereas the other keys will modify the
setting of the digital POT U503 (see 5.5).
This procedure is used to set tone deviations of 750Hz, 700Hz, 650Hz, 600Hz, 550Hz,
500Hz, etc down to 150Hz.
6.2.5 The “ Line” Calibration Procedure
T50> cal line
This procedure should not be used as part of any usual field maintenance, unless any
component has been replaced that might affect the gain of any of the audio inputs.
Note that if the deviations are calibrated, then this procedure will be automatically
invoked.
The program begins:
Calibrating Line 1 and Line 2 audio levels
Attach an audio signal generator to Line 1
Set the output to be a sine wave, 388mV rms and 1kHz
Disconnect the RF connection to the PA
and connect a deviation meter to the exciter's BNC output.
and < RET> when the deviation is 3kHz.
?
24
This is the same mechanism that is used in 6.5 and 6.6. The user enters +, p, or P to
increase the Line 1 gain, to increase the deviation, or, -, m, or M to decrease the gain.
The user hits the Enter key when the desired deviation is set.
Now attach the audio signal generator to Line 2
?
Again the user enters +, p, or P to increase the Line 2 gain, or, -, m, or M to decrease the
gain. The user hits the Enter key when the desired deviation is set.
The firmware goes on to open the microphone audio path (note that the microphone
PTT switch does not need to be depressed for this). Note also that the application of a
10mV test input is a factory only test. An adequate test in field testing, would be to
speak into the microphone and see that the deviation meter responded accordingly.
Testing the microphone input.
Attach an audio signal generator to the microphone input.
Set the output to be a sine wave, 10mV rms and 1kHz.
Ensure that the deviation is between 2.7 and 3.3kHz
Enter < RET> when measurement complete.
Alert Engineering if there is a failure.
Then the Direct Audio input (with the low pass filter off) is tested.
Testing the Tone input.
Attach an audio signal generator to the Tone input.
Set the output to be a sine wave, 129mV rms, and 1kHz.
?
And then user then follows the same procedure as defined for setting the Line 1 and
Line 2 gains.
6.2.6 The “ Power” Calibration Procedure
T50> cal pwr
All Power Amplifiers are calibrated ex-factory. All the important parameters, such as
the forward and reverse power sense adjustment, and drain bias settings are not
dependent on the exciter, and thus any factory calibrated PA50 power amplifier can be
connected to, and work correctly with any T50 exciter. The frequency range of the
amplifier is defined by three jumper settings on the external PA, which the CPU can
detect. Thus the CPU knows (on power up) what frequencies are, or are not, possible to
be used with the PA.
The exciter may store some PA specific parameters, such as the Serial Number of the
PA, and also some offset values for the pre-amp drain current, and the output stage
drain current. These latter offsets improve the accuracy of the over current alarm
testing, (but are not strictly necessary). In order to set these parameters, it is advised
that this procedure be performed every time an exciter is used with a new External
Power Amplifier. Note that many of the stages can be skipped if they have been
performed before.
The program begins:
25
This procedure is used to calibrate an External Power Amplifier.
The existing PA's SERIAL NO is: 002356
Enter the new PA serial no:
Simply hit the Enter key here if the Serial Number is correct.
Take the lid off a PA, and set all three
bias Pots (R238,R239, and R240) fully clockwise.
Enter < RET> when done.
Now we will set the Bias currents in the PA.
Attach power to the PA.
Each mV read across TP100(+ ve lead), and TP101(-ve lead),
corresponds to 1mA of 1st stage Bias current.
For power control in the range 50 - 150W,
set the 1st stage bias to 35 - 40mA.
For power control in the range 20 - 60W, use a bias of 15 - 20mA.
Attach the millivoltmeter, and
adjust R238 for the bias required.
Unless one of the RF power transistors has been replaced, the user should simply skip
these last four stages by hitting the Enter key four times.
Attach the Power Amplifier to the Exciter,

and ensure the PA is powered up.
Attach the PA output to a reflectometer, the reflectometer to a 50dB
(nominal) attenuator, and the attenuator to a calibrated power
meter
Enter < RET> when this has been done
Adjust C209 in the Power Amplifier
until there is a minimum in the dc voltage measured at TP204
Adjust the Forward Power Sense POT (R228) unti
tthe measured output power (adjusted for the attenuator and
reflectometer losses) is equal to the Preset Forward Power.
Unless something has been modified in the power sense circuits, these last three stages
should be skipped by simply hitting the Enter key three times.
This next step allows the firmware to compute an offset in the output stage drain
current, so that the exciter’s ability to measure the output stage drain current is
significantly more accurate.
Measure the voltage across TP102(+ ve lead)
and TP103(-ve lead), and enter the value measured
This next step allows the firmware to compute an offset in the pre-amp stage drain
current, so that the exciter’s ability to measure the pre-amp stage drain current is
significantly more accurate.
Measure the voltage across TP100(+ ve lead)
and TP101(-ve lead), and enter the value measured
The next two stages can be skipped by simply hitting the Enter key twice.
Attach the reflectometer to an open circuit
Enter < RET> when this has been done
Adjust the Reverse Power Sense POT (R227) until
26
the displayed reverse power equals 50W.
Enter < RET> when this has been done.
This then completes all the calibration procedures.
7 SPECIFICATIONS
7.1 Over all Descr iption

The transmitter is a frequency synthesized, narrow band, HF/VHF, FM unit, used to
drive an external 120 watt amplifier. All necessary control and 600 Ω line interface
circuitry is included.
7.1.1 Channel Capacity
Although most applications are single channel, the T50 can be programmed for up to
256 channels, numbered 0-255. This allows a network administrator to program every
exciter, in every site, the same way. By setting each site up to select which of the 256
channels is appropriate, any exciter can be plugged into any position, in any site,
without the need to perform on-site re-programming. This can be convenient in
maintenance situations.
Channel information consists of two independent and complete sets of information,
which may differ or be the same. One set defines the parameters to be used, if the unit
is keyed up from PTT-in being “grounded”, and the other set defines the parameters to
be used if the unit is keyed up for any reason other than PTT-in being “grounded”.
The parameters that can be defined on a per channel basis are:
a) The frequency
b) The CTCSS tone (if any) to be generated, or, the DCS code (if any) to be
generated.
c) The delay from the initiation of the exciter to RF output being generated
(Is specified in hundredths of a second, 0 – 999)
d) The transmit tail; the length of time after the exciter is released before
transmission stops. (Is specified in seconds 0 – 999).
e) The No Tone period; a length of time after the expiry of (d) in which
transmission continues, but with no tone being generated. (Is specified in
tenths of a second, 0 –999)
f) Whether audio from Line 1, or Line 2, or both, (or neither!) is enabled,
and whether or not Pre-emphasis is required, or not, on each line, and
whether or not an extra gain pad (of 20dB) is required.
g) What Nominal Tone Deviation, and Maximum Deviation should be used
(See Tables 7 and 8)
7.1.2 CTCSS
Full EIA subtone Capability is built into the modules. The CTCSS tone can be
programmed for each channel. This means that each channel number can represent a
unique RF and tone frequency combination.
7.1.3 DCS
From Rev. 4 hardware and Rev. 4 firmware, support for DCS codes is supported. DCS
code generation can be enabled on a per channel basis. If enabled, the 23 bit Golay
27
code containing the selected DCS code word will be generated continuously after the
exciter is keyed up.
7.1.4 Channel Programming
The channel information is stored in non-volatile memory and can be programmed via
the front panel connector using a PC, and/or RF Technology software.
7.1.5 Channel Selection
Channel selection is by eight channel select lines connected to the rear panel that
mounts on the rear DB25 female connector.
A BCD active high code applied to the lines selects the required channel. This can be
supplied by pre-wiring the rack connector so that each rack position is dedicated to a
fixed channel. Alternatively, thumb-wheel switch panels are available.
By redefining “illegal” BCD codes, users can also encode channels from 100 – 255.
7.1.6 Microprocessor
A microprocessor is used to control the synthesizer, tone squelch, PTT functions,
external reference monitoring, calibration, fault monitoring and reporting, output power
level control, volume adjustment, line selection, option setting, and facilitate channel
frequency programming.
7.2 Physical Configur ation

The transmitter is designed to fit in a 19 inch rack mounted sub-frame. The installed
height is 4 RU (178 mm) and the depth is 350 mm. The transmitter is 63.5 mm or two
Eclipse modules wide.
7.3 Fr ont Panel Contr ols, Indicator s, and Test Points

7.3.1 Controls
Transmitter Key - Momentary Contact Push Button
Line Input Level - screwdriver adjust multi-turn pot
7.3.2 Indicators
Power ON - Green LED
Tx Indicator - Yellow LED
Fault Indicator - Flashing Red LED
7.3.3 Test Points
There are no front panel test points. All important test points are monitored by the
firmware.
7.4 Electr ical Specifications

7.4.1 Power Requirements
Operating Voltage - 16 to 32 Vdc
Current Drain – 0.33A Maximum, typically 0.32A Standby
Polarity - Negative Ground
28
7.4.2 Frequency Range and Channel Spacing
The T50, as a single model, covers the full band, and all channel spacing.
Frequency 25 kHz 20kHz 15kHz 12.5 kHz 10 kHz 7.5 kHz 6.25 kHz
25 - 50 MHz T50 T50 T50 T50 T50 T50 T50
7.4.3 Frequency Synthesizer Step Size

The specified frequency can be any multiple of 1250Hz.
7.4.4 Frequency Stability
±5 ppm over 0 to +60 C, standard
±12 ppm over -30 to +60 C.
7.4.5 Number of Channels
256, numbered 00 - 255
7.4.6 Output power
The T50 needs an external PA50 power amplifier.
The output power is factory set to 100W by default, the reverse power level is set to
fold back the output power when the PA50 sees a load with VSWR of 3:1 or higher (i.e.
when the reverse power is 25% or more of the forward power).
7.4.7 Transmit Duty Cycle
100%
7.4.8 Spurious and Harmonics
Less than 0.25µW, when connected to a PA50 operating at an output power level of
100W.
7.4.9 Carrier and Modulation Attack Time
Less than 36ms (Rev 3 and Rev 4).
Less than 20ms (Rev 5 or higher).
7.4.10 Modulation
Type - Two point direct FM with optional pre-emphasis
Frequency Response - ±1 dB of the selected characteristic from 300-3000Hz
Maximum Deviation - Maximum deviation set on a per channel basis to 1.5, 2.0, 2.5,
3.0, 3.5, 4.0, 4.5, or 5.0 kHz.
7.4.11 Distortion
Modulation distortion is less than 3% at 1 kHz and 60% of rated system deviation.
7.4.12 Residual Modulation and Noise
The residual modulation and noise in the range 300 - 3000 Hz is typically less than -
50dB with 5kHz maximum deviation (i.e. a test level of 3kHz).
7.4.13 600Ω Line Input Sensitivity
Adjustable from -32 to +12 dBm for rated deviation on two symmetric, independent,
transformer coupled Line inputs.
29
7.4.14 Test Microphone Input
200Ω dynamic, with PTT
7.4.15 External Tone Input
Compatible with all RF Technology receivers. Each unit is factory configured to give
20% of maximum deviation for an external tone input of 129mV.
7.4.16 T/R Relay Driver
An open drain MOSFET output is provided to operate an antenna change over relay or
solid state switch. The transistor can sink up to 250mA. A 1W flywheel diode connects
to the 12V rail to prevent damage to the FET from inductive kick from a relay coil.
7.4.17 Channel Select Input/Output
Coding - 8 lines, BCD coded 00 – 99; illegal BCD codes used to encode channels
100 – 255.
If the MSN (Most Significant Nibble) is greater than 9, then the channel number is
defined by the formula:
16*MSN + LSN;
where the LSN is the Least Significant Nibble.
If the MSN is less than 9, but the LSN is greater than 9, then the channel number is
defined by the formula:
10*LSN+MSN;
Logic Input Levels - High for <1.5V, Low for >3.5V
Internal pull up resistors select channel 00 when all inputs are O/C.
7.4.18 DC Remote Keying
An opto-coupler input is provided to enable dc loop keying over balanced lines or local
connections. The circuit can be connected to operate through the 600Ω line.
7.4.19 PTT in
An external input that when “grounded” with at least 1mA of current, will cause the
exciter to key up. The current is drawn from the PTT in input which attempts to “pull
up” anything that “grounds” it. It can be “grounded” with a short to 0V, or any
resistance up to 3.9k ohm. If the resistance of the “ground connection” is less than 2.2k
ohms, then up to three diodes in series can be part of the grounding path. This allows
systems installers to use quite complex diode logic to enable or disable exciters.
It would normally be “grounded” by the COS output of a receiver.
7.4.20 Programmable No-Tone Period
A No-Tone period can be appended to the end of each transmission to aid in eliminating
squelch tail noise which may be heard in mobiles with slow turn off decoders. The No-
Tone period can be set from 0-99.9 seconds in 0.1 second increments.
7.4.21 Firmware Timers
The controller firmware includes some programmable timer functions.
Repeater Hang Time(Transmit Tail) - A short delay or ``Hang Time'' can be
programmed to be added to the end of transmissions. This is usually used in talk
through repeater applications to prevent the repeater from dropping out between mobile
30
transmissions. The Hang Time can be individually set on each channel for 0 - 999
seconds.
Time Out Timer - A time-out or transmission time limit can be programmed to
automatically turn the transmitter off. The time limit can be set from 0-10million
seconds. The timer is automatically reset when the PTT input is released. Zero seconds
disables the timer, and allows continuous transmission.
7.4.22 CTCSS
CTCSS tones can be provided by an internal encoder or by an external source connected
to the external tone input. The internal CTCSS encoding provides programmable
encoding of any tone, accurate to 0.1Hz, including all EIA tones, from 67.0Hz to
257Hz.
7.4.23 DCS codes
DCS codes can be generated. The 9 bit DCS codes can be specified as a 3 digit octal
number and individual codes can be assigned to each channel. The exciter computes the
23 bit golay code for each DCS code, which is then continuously transmitted as NRZ
data at a bit rate of 134.4 bits per second when the exciter has keyed up. This feature is
only available from Rev. 4 units or later revisions.
7.4.24 CWID
CWID messages are transmitted as Morse Code streams. The transmit rate is a nominal
20 words per minute. Each “dot” is a burst of 1028Hz tone at a deviation level of
1.5kHz for 60ms. Each “dash” is the same tone, at the same level for 180ms.
7.5 Connector s
7.5.1 RF Output Connector
BNC connector on the module rear panel.
7.5.2 Power & I/O Connector
25-pin “D” Female Mounted at the top of the rear panel
7.5.3 External Reference Connector (optional)
BNC connector mounted in the middle of the rear panel connector.
31
A Engineering Diagrams
There is only one printed circuit board covering all models of the T50. There is only
one option for this product, which is the external reference clock option. That option
adds a rear connector, and a small length of coaxial cable and a fixed coaxial cable
mount to the parts list.
Unlike other products in the Eclipse range, CTCSS is no longer an option. All units
have the ability to transmit CTCSS tones, and from Rev. 4, DCS codes.
A.1 Block Diagr am
Figure 1 shows the block signal flow diagram.
A.2 Cir cuit Diagr ams
Figure 2 shows the detailed circuit diagram with component numbers and values for the
main (exciter) PCB. Figure 3 shows the detailed circuit diagram with component
numbers and values for the higher-power PA variation. Figure 4 shows the detailed
circuit diagram with component numbers and values for the lower-power PA variation.
A.3 Component Over lay Diagr ams
Figure 5 shows the PCB overlay guide with component positions for the main (exciter)
PCB. Figure 6 shows the detailed circuit diagram with component numbers and values
for the higher-power PA variation. Figure 7 shows the detailed circuit diagram with
component numbers and values for the lower power PA variation.
32
B T50 Parts List (Rev 4)
Ref Descr iption Par t #

C100 Four EMI filters in a 1206 package, 100pF 34/NFA3/1100
C201 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100N
C209 10nF Cer. Cap, X7R, 0603, 10% 46/63X1/010N
C219 3u3F SMD, Electrolytic cap, A body, 10% 42/STA1/03U3
C300 22uF Electrolytic Capacitor, 35V, Bipolar 41/BP01/022U
C301 22uF Electrolytic Capacitor, 35V, Bipolar 41/BP01/022U
C302 2n2F Cer. Cap, NPO, 1206, 5% 46/26N1/02N2
C305 10nF Cer. Cap, NPO, 1206, 5% 46/26N1/010N
C306 120pF Cer. Cap, NPO, 0603, 5% 46/63N1/120P
C312 Ceramic Capacitor, 16V, 1uF, X7R, 1206 45/X7R1/1U16
C400 15uF SMD, low ESR Electrolytic cap, C body 41/SELC/015U
C401 10nF Cer. Cap, X7R, 0603, 10% 46/63X1/010N
C402 3n3F Cer. Cap, NPO, 1206, 5% 46/26N1/03N3
C403 3n3F Cer. Cap, NPO, 1206, 5% 46/26N1/03N3
C404 3n3F Cer. Cap, NPO, 1206, 5% 46/26N1/03N3
C421 1nF, 25V, X7R, 0603 46/63X1/001N
33
C500 22pF Cer. Cap, NPO, 0603, 5% 46/63N1/022P
C501 22pF Cer. Cap, NPO, 0603, 5% 46/63N1/022P
C502 Ceramic Capacitor, 16V, 1uF, X7R 45/X7R1/1U16
C506 100pF Cer. Cap, NPO, 0603, 5% 46/63N1/100P
C507 100pF Cer. Cap, NPO, 0603, 5% 46/63N1/100P
C514 Ceramic Capacitor, 16V, 22nF, X7R,10% 45/X7R1/022N
C515 100nF, 50V, NPO, TH, 5mm 47/2007/100N
C516 1n2F Cer. Cap, NPO, 1206, 5% 46/26N1/01N2
C600 10nF Cer. Cap, X7R, 0603, 10% 46/63X1/010N
C602 10nF Cer. Cap, X7R, 0603, 10% 46/63X1/010N
C603 10nF Cer. Cap, X7R, 0603, 10% 46/63X1/010N
C605 10nF Cer. Cap, X7R, 0603, 10% 46/63X1/010N
C609 10nF Cer. Cap, X7R, 0603, 10% 46/63X1/010N
C610 470pF Cer. Cap, NPO, 0603, 5% 46/63N1/470P
C611 1nF Cer. Cap, X7R, 0603, 10% 46/63X1/001N
C613 Ceramic Capacitor, 16V, 220nF, X7R, 10% 45/X7R1/220N
C614 15pF Cer. Cap, NPO, 0603, 5% 46/63N1/015P
C615 3p3F Cer. Cap, NPO, 0603, 5% 46/63N1/03P3
C616 10nF Cer. Cap, X7R, 0603, 10% 46/63X1/010N
C620 33pF Cer. Cap, NPO, 0603, 5% 46/63N1/033P
C623 Ceramic Capacitor, 16V, 220nF, X7R, 10% 45/X7R1/220N
C631 10nF Cer. Cap, X7R, 0603, 10% 46/63X1/010N
C634 10nF Cer. Cap, X7R, 0603, 10% 46/63X1/010N
C635 8p2F Cer. Cap, NPO, 0603, 5% 46/63N1/08P2
C636 10nF Cer. Cap, X7R, 0603, 10% 46/63X1/010N
C637 56pF Cer. Cap, NPO, 0603, 5% 46/63N1/056P
C638 10nF Cer. Cap, X7R, 0603, 10% 46/63X1/010N
C640 8p2F Cer. Cap, NPO, 0603, 5% 46/63N1/08P2
C642 100pF Cer. Cap, NPO, 0603, 5% 46/63N1/100P
C649 10pF Cer. Cap, NPO, 0603, 5% 46/63N1/010P
C650 10pF Cer. Cap, NPO, 0603, 5% 46/63N1/010P
34
C652 10nF Cer. Cap, X7R, 0603, 10% 46/63X1/010N
C701 10nF Cer. Cap, X7R, 0603, 10% 46/63X1/010N
C702 10nF Cer. Cap, X7R, 0603, 10% 46/63X1/010N
C704 220pF Cer. Cap, NPO, 0603, 5% 46/63N1/220P
C705 220pF Cer. Cap, NPO, 0603, 5% 46/63N1/220P
C707 220pF Cer. Cap, NPO, 0603, 5% 46/63N1/220P
C708 220pF Cer. Cap, NPO, 0603, 5% 46/63N1/220P
C709 220pF Cer. Cap, NPO, 0603, 5% 46/63N1/220P
C711 10nF Cer. Cap, X7R, 0603, 10% 46/63X1/010N
C714 10nF Cer. Cap, X7R, 0603, 10% 46/63X1/010N
C716 220pF Cer. Cap, NPO, 0603, 5% 46/63N1/220P
C720 10nF Cer. Cap, X7R, 0603, 10% 46/63X1/010N
C724 10nF Cer. Cap, X7R, 0603, 10% 46/63X1/010N
C726 12pF Cer. Cap, NPO, 0603, 5% 46/63N1/012P
C727 12pF Cer. Cap, NPO, 0603, 5% 46/63N1/012P
C728 12pF Cer. Cap, NPO, 0603, 5% 46/63N1/012P
C729 15pF Cer. Cap, NPO, 0603, 5% 46/63N1/015P
C730 10nF Cer. Cap, X7R, 0603, 10% 46/63X1/010N
C731 15pF Cer. Cap, NPO, 0603, 5% 46/63N1/015P
C732 5p6F Cer. Cap, NPO, 0603, 5% 46/63N1/05P6
C733 3p3F Cer. Cap, NPO, 0603, 5% 46/63N1/03P3
C734 12pF Cer. Cap, NPO, 0603, 5% 46/63N1/012P
C735 12pF Cer. Cap, NPO, 0603, 5% 46/63N1/012P
C737 10nF Cer. Cap, X7R, 0603, 10% 46/63X1/010N
C738 10nF Cer. Cap, X7R, 0603, 10% 46/63X1/010N
C739 10nF Cer. Cap, X7R, 0603, 10% 46/63X1/010N
C740 4p7F Cer. Cap, NPO, 0603, 5% 46/63N1/04P7
C742 10nF Cer. Cap, X7R, 0603, 10% 46/63X1/010N
C743 10nF Cer. Cap, X7R, 0603, 10% 46/63X1/010N
C744 12pF Cer. Cap, NPO, 0603, 5% 46/63N1/012P
C746 10nF Cer. Cap, X7R, 0603, 10% 46/63X1/010N
C747 10nF Cer. Cap, X7R, 0603, 10% 46/63X1/010N
C748 10nF Cer. Cap, X7R, 0603, 10% 46/63X1/010N
C749 10nF Cer. Cap, X7R, 0603, 10% 46/63X1/010N
C750 15pF Cer. Cap, NPO, 0603, 5% 46/63N1/015P
C751 33pF Cer. Cap, NPO, 0603, 5% 46/63N1/033P
C752 12pF Cer. Cap, NPO, 0603, 5% 46/63N1/012P
C755 22pF Cer. Cap, NPO, 0603, 5% 46/63N1/022P
C756 12pF Cer. Cap, NPO, 0603, 5% 46/63N1/012P
C757 47pF Cer. Cap, NPO, 0603, 5% 46/63N1/047P
C758 47pF Cer. Cap, NPO, 0603, 5% 46/63N1/047P
C759 22pF Cer. Cap, NPO, 0603, 5% 46/63N1/022P
C761 22pF Cer. Cap, NPO, 0603, 5% 46/63N1/022P
C762 10nF Cer. Cap, X7R, 0603, 10% 46/63X1/010N
C763 10nF Cer. Cap, X7R, 0603, 10% 46/63X1/010N
C764 6p8F Cer. Cap, NPO, 0603, 5% 46/63N1/06P8
C765 68pF Cer. Cap, NPO, 0603, 5% 46/63N1/068P
C766 10pF Cer. Cap, NPO, 0603, 5% 46/63N1/010P
35
C767 12pF Cer. Cap, NPO, 0603, 5% 46/63N1/012P
C768 15pF Cer. Cap, NPO, 0603, 5% 46/63N1/015P
C769 68pF Cer. Cap, NPO, 0603, 5% 46/63N1/068P
C773 Ceramic Capacitor, 16V, 1uF, Y5V 45/Y5X7/1U16
C801 100nF Cer. Cap, X7R, 1206, 10% 46/3310/100N
C802 1n2F Cer. Cap, X7R, 0603, 10% 46/63X1/01N2
C803 1nF Cer. Cap, NPO, 0603, 5% 46/63N1/01N0
C804 68pF Cer. Cap, NPO, 0603, 5% 46/63N1/068P
C805 470pF Cer. Cap, X7R, 0603, 10% 46/63X1/470P
C806 10nF Cer. Cap, X7R, 0603, 10% 46/63X1/010N
C807 10nF Cer. Cap, X7R, 0603, 10% 46/63X1/010N
C810 100nF Cer. Cap, X7R, 1206, 10% 46/3310/100N
C811 100uF Electrolytic Capacitor, 35V 41/2001/100U
C820 470pF Cer. Cap, NPO, 0603, 5% 46/63N1/470P
C822 10nF Cer. Cap, X7R, 0603, 10% 46/63X1/010N
C825 220pF Cer. Cap, NPO, 0603, 5% 46/63N1/220P
C827 10 uF Electrolytic capacitor 41/2001/010U
C828 150pF Cer. Cap, NPO, 0603, 5% 46/63N1/150P
C830 68pF Cer. Cap, NPO, 0603, 5% 46/63N1/068P
C901 100uF SMD, low ESR Electrolytic cap, D body 41/SELD/100U
C902 470uF Electrolytic Capacitor, Low ESR, 35V 41/200L/470U
C935 470uF Electrolytic Capacitor, Low ESR, 35V 41/200L/470U
D102 Radially mounted LED 21/1010/LEDR
D103 Radially mounted LED 21/1010/LEDY
D104 Radially mounted LED 21/1010/LEDG
D200 Dual Series Diode 21/3010/AV99
D202 Gen. Purpose 1N4004 diode in SMD pkg 24/SMA1/4004
D203 Zener Diode 21/1040/C3V3
D300 Bi-directional Transil 24/TRSL/012V
D301 Bidirectional Transil 24/TRSL/012V
D302 Bidirectional Transil 24/TRSL/012V
36
D307 Dual Schottky, Comm. Cathode, Diode 24/3BAT/54C1
D600 Varactor 21/3060/V109
D601 Varactor 21/3060/V109
D700 Schottky diode 21/3030/0017
D701 Varactor 21/3060/V109
D703 Schottky diode 21/3030/0017
D704 Varactor 21/3060/V109
D800 Dual Schottky, Comm. Cathode, Diode 24/3BAT/54C1
D906 Power Fast Schottky diode 24/BRM1/40T3
D911 4.096V Reference Diode 29/VREF/0001
F300 SMD (1206 pkg), 125mA fuse 39/1206/A125
F301 SMD (1206 pkg), 125mA fuse 39/1206/A125
F302 SMD (1206 pkg), 125mA fuse 39/1206/A125
J1 BNC Connector 35/5BNC/RA01
JP12 4 Pin SIL Header 35/2501/0004
JP2 14 Pin SIL Header 35/2501/0014
JP3 10 pin DIL Header 35/7026/0010
JP4 10 pin DIL Header 35/7026/0010
L100 Ferrite, 1206 pkg, 120 ohm, 3A 37/P034/0001
L101 Ferrite, 1206 pkg, 600 ohm, 200mA 37/P033/0001
L200 220uH Choke 37/3320/P103
L700 27nH Inductor 37/8551/027N
L701 33nH Inductor 37/8551/033N
L702 27nH Inductor 37/8551/027N
L703 27nH Inductor 37/8551/027N
L704 47nH Inductor 37/8551/047N
L705 27nH Inductor 37/8551/027N
L706 330nH Inductor 37/3320/330N
L708 330nH Inductor 37/3320/330N
L709 330nH Inductor 37/3320/330N
L710 330nH Inductor 37/3320/330N
L711 330nH Inductor 37/3320/330N
L712 220nH Inductor 37/8551/220N
L713 1206 47R resistor 51/3380/047R
L714 330nH Inductor 37/3320/330N
L715 330nH Inductor 37/3320/330N
L716 Inductor - Air Core, 12.5nH 37/AC51/12N5
L717 100nH Inductor 37/8551/100N
L719 Inductor - Air Core, 18.5nH 37/AC51/18N5
L720 24nH Inductor 37/6351/024N
L721 24nH Inductor 37/6351/024N
L722 24nH Inductor 37/6351/024N
L723 330nH Inductor 37/3320/330N
37
L724 330nH Inductor 37/3320/330N
L725 3u3H Choke 37/3320/P101
L726 33nH Inductor 37/8551/082N
L803 Inductor - Air Core, 538nH 37/AC52/558N
L804 Inductor - Air Core, 538nH 37/AC52/558N
L807 220uH Choke 37/3320/P103
L808 3u3H Choke 37/3320/P101
L809 180nH Inductor 37/8551/180N
L810 1uH Choke 37/3320/P200
L811 3u3H Choke 37/3320/P101
L812 150nH Inductor 37/3320/150N
L813 150nH Inductor 37/3320/150N
L902 SMD High Current, Shielded, 330uH Choke 37/MSP1/330U
LC700 70MHz SMD Filter, 0805 pkg 37/85LC/0135
M1 Tinned BeCu, used as RF screen. 94/BECU/24XH
M1C RF Screen Cover (Small) 80/9209/0001
M2 Conductive Foam Inserts 83/0001/0000
MX700 +7dBm0 Mixer, Surface Mount 37/MIXR/P028
P1 DB9 Female with filtered pins 35/5012/009F
P3 DB25 Female with filtered pins 35/5012/025F
Q200 Gen. Purpose NPN transistor in SOT-23 27/3020/3904
Q201 N channel, Enhancement Mode MOSFET 27/30B5/5138
Q202 N Channel Junction FET(low Freq) 27/3020/5484
Q203 NPN Switching transistor in SOT-23 27/3020/2369
Q204 NPN Switching transistor in SOT-23 27/3020/2369
Q205 Gen. Purpose PNP transistor in SOT-23 27/3010/3906
Q704 N Channel Junction FET(UHF) 27/3030/J309
Q705 N Channel Junction FET(UHF) 27/3030/J309
Q801 SOD-89A RF Transistor(1W) 27/300B/FQ17
R100 0805, 1%, 4K7 resistor 51/8511/04K7
R101 0805, 1%, 4K7 resistor 51/8511/04K7
R102 0805, 1%, 4K7 resistor 51/8511/04K7
R103 1206 180R resistor 51/3380/0180
R104 1206 270R resistor 51/3380/0270
R105 0805, 1%, 4K7 resistor 51/8511/04K7
R201 0805, 1%, 10K resistor 51/8511/010K
R202 0805, 1%, 10K resistor 51/8511/010K
R203 0805, 1%, 10K resistor 51/8511/010K
38
R204 0805, 1%, 10K resistor 51/8511/010K
R205 0805, 1%, 2K2 resistor 51/8511/02K2
R206 0805, 1%, 2K2 resistor 51/8511/02K2
R207 0805, 1%, 68K resistor 51/8511/068K
R208 0805, 1%, 22K resistor 51/8511/022K
R209 0805, 1%, 330R resistor 51/8511/330R
R210 0805, 1%, 10K resistor 51/8511/010K
R211 0805, 1%, 220R resistor 51/8511/220R
R212 0805, 1%, 220R resistor 51/8511/220R
R213 0805, 1%, 1M resistor 51/8511/01M0
R214 1206 180R resistor 51/3380/0180
R215 0805, 1%, 120R resistor 51/8511/120R
R216 0805, 1%, 1K resistor 51/8511/01K0
R217 0805, 1%, 10K resistor 51/8511/010K
R218 0805, 1%, 10K resistor 51/8511/010K
R219 0805, 1%, 10K resistor 51/8511/010K
R220 0805, 1%, 10K resistor 51/8511/010K
R221 0805, 1%, 560R resistor 51/8511/560R
R222 0805, 1%, 1K resistor 51/8511/01K0
R223 0805, 1%, 10K resistor 51/8511/010K
R224 0805, 1%, 10K resistor 51/8511/010K
R225 0805, 1%, 10K resistor 51/8511/010K
R226 1206 180R resistor 51/3380/0180
R227 0805, 1%, 56R resistor 51/8511/056R
R228 0805, 1%, 10K resistor 51/8511/010K
R229 0805, 1%, 10K resistor 51/8511/010K
R230 0805, 1%, 120R resistor 51/8511/120R
R231 0805, 1%, 120R resistor 51/8511/120R
R232 0805, 1%, 560R resistor 51/8511/560R
R233 0805, 1%, 22K resistor 51/8511/022K
R234 0805, 1%, 1K resistor 51/8511/01K0
R235 0805, 1%, 4K7 resistor 51/8511/04K7
R236 0805, 1%, 22K resistor 51/8511/022K
R237 0805, 1%, 47K resistor 51/8511/047K
R238 0805, 1%, 1K resistor 51/8511/01K0
R239 0805, 1%, 1K resistor 51/8511/01K0
R240 0805, 1%, 10K resistor 51/8511/010K
R241 0805, 1%, 47R resistor 51/8511/047R
R242 0805, 1%, 47K resistor 51/8511/047K
R243 0805, 1%, 220R resistor 51/8511/220R
R244 0805, 1%, 10R resistor 51/8511/010R
R245 0805, 1%, 10K resistor 51/8511/010K
R300 0805, 1%, 27R resistor 51/8511/027R
R301 0805, 1%, 27R resistor 51/8511/027R
R302 0805, 1%, 27R resistor 51/8511/027R
R303 0805, 1%, 27R resistor 51/8511/027R
R304 0805, 1%, 330R resistor 51/8511/330R
R305 0805, 1%, 330R resistor 51/8511/330R
R306 0805, 1%, 10R resistor 51/8511/010R
R307 0805, 1%, 4K7 resistor 51/8511/04K7
R308 0805, 1%, 2K2 resistor 51/8511/02K2
R309 0805, 1%, 560R resistor 51/8511/560R
R310 0805, 1%, 560R resistor 51/8511/560R
R311 0805, 1%, 22K resistor 51/8511/022K
R312 0805, 1%, 22K resistor 51/8511/022K
R313 0805, 1%, 22K resistor 51/8511/022K
R314 0805, 1%, 1K resistor 51/8511/010K
R315 0805, 1%, 22K resistor 51/8511/022K
R316 0805, 1%, 1K resistor 51/8511/010K
R317 0805, 1%, 1K resistor 51/8511/01K0
R318 0805, 1%, 120K resistor 51/8511/120K
R319 0805, 1%, 120K resistor 51/8511/120K
R320 0805, 1%, 120K resistor 51/8511/120K
R321 0805, 1%, 68K resistor 51/8511/068K
R322 0805, 1%, 68K resistor 51/8511/068K
R323 0805, 1%, 68K resistor 51/8511/068K
R324 0805, 1%, 1K resistor 51/8511/01K0
39
R325 0805, 1%, 47K resistor 51/8511/047K
R326 0805, 1%, 47K resistor 51/8511/047K
R327 0805, 1%, 47K resistor 51/8511/047K
R328 0805, 1%, 10K resistor 51/8511/010K
R329 0805, 1%, 10K resistor 51/8511/010K
R330 0805, 1%, 47K resistor 51/8511/047K
R331 0805, 1%, 47K resistor 51/8511/047K
R332 0805, 1%, 68K resistor 51/8511/068K
R333 0805, 1%, 1K resistor 51/8511/01K0
R335 0805, 1%, 22K resistor 51/8511/022K
R336 0805, 1%, 22K resistor 51/8511/022K
R337 0805, 1%, 1K8 resistor 51/8511/01K8
R400 0805, 1%, 330R resistor 51/8511/330R
R401 0805, 1%, 270R resistor 51/8511/270R
R402 0805, 1%, 22K resistor 51/8511/022K
R403 0805, 1%, 22K resistor 51/8511/022K
R404 0805, 1%, 12K resistor 51/8511/012K
R405 0805, 1%, 5K6 resistor 51/8511/05K6
R406 0805, 1%, 10K resistor 51/8511/010K
R407 0805, 1%, 10K resistor 51/8511/010K
R408 0805, 1%, 5K6 resistor 51/8511/05K6
R409 0805, 1%, 56K resistor 51/8511/056K
R410 0805, 1%, 47K resistor 51/8511/047K
R411 0805, 1%, 47K resistor 51/8511/047K
R412 0805, 1%, 10K resistor 51/8511/010K
R413 0805, 1%, 1K resistor 51/8511/01K0
R414 0805, 1%, 560R resistor 51/8511/560R
R415 0805, 1%, 560R resistor 51/8511/560R
R416 0805, 1%, 560R resistor 51/8511/560R
R417 0805, 1%, 560R resistor 51/8511/560R
R418 0805, 1%, 2K2 resistor 51/8511/02K2
R419 0805, 1%, 22K resistor 51/8511/022K
R420 0805, 1%, 120K resistor 51/8511/120K
R421 0805, 1%, 22K resistor 51/8511/022K
R422 0805, 1%, 120K resistor 51/8511/120K
R423 0805, 1%, 10K resistor 51/8511/010K
R424 0805, 1%, 10K resistor 51/8511/010K
R425 0805, 1%, 22K resistor 51/8511/022K
R426 0805, 1%, 22K resistor 51/8511/022K
R427 0805, 1%, 47K resistor 51/8511/047K
R428 0805, 1%, 22K resistor 51/8511/022K
R429 0805, 1%, 22K resistor 51/8511/022K
R430 0805, 1%, 47K resistor 51/8511/047K
R433 0805, 1%, 270K resistor 51/8511/270K
R434 0805, 1%, 4K7 resistor 51/8511/04K7
R435 0805, 1%, 1K resistor 51/8511/01K0
R436 0805, 1%, 4K7 resistor 51/8511/04K7
R437 0805, 1%, 47K resistor 51/8511/047K
R438 0805, 1%, 47K resistor 51/8511/047K
R439 0805, 1%, 4K7 resistor 51/8511/04K7
R440 0805, 1%, 4K7 resistor 51/8511/04K7
R442 0805, 1%, 4K7 resistor 51/8511/04K7
R443 0805, 1%, 4K7 resistor 51/8511/04K7
R444 0805, 1%, 4K7 resistor 51/8511/04K7
R445 0805, 1%, 47K resistor 51/8511/047K
R446 0805, 1%, 100K resistor 51/8511/100K
R447 0805, 1%, 47K resistor 51/8511/047K
R448 0805, 1%, 270K resistor 51/8511/270K
R449 0805, 1%, 220R resistor 51/8511/220R
R450 0805, 1%, 56K resistor 51/8511/56K
R451 0805, 1%, 47K resistor 51/8511/047K
R453 0805, 1%, 10K resistor 51/8511/010K
R454 0805, 1%, 10K resistor 51/8511/010K
R455 0805, 1%, 10K resistor 51/8511/010K
R456 0805, 1%, 47K resistor 51/8511/047K
R457 0805, 1%, 22K resistor 51/8511/022K
R458 0805, 1%, 4K7 resistor 51/8511/04K7
40
R459 0805, 1%, 4K7 resistor 51/8511/04K7
R460 0805, 1%, 4K7 resistor 51/8511/04K7
R461 0805, 1%, 56K resistor 51/8511/056K
R462 0805, 1%, 22K resistor 51/8511/022K
R463 0805, 1%, 56K resistor 51/8511/056K
R464 0805, 1%, 270K resistor 51/8511/270K
R465 0805, 1%, 22K resistor 51/8511/022K
R466 0805, 1%, 2K2 resistor 51/8511/02K2
R467 0805, 1%, 4K7 resistor 51/8511/04K7
R500 0805, 1%, 47K resistor 51/8511/047K
R501 0805, 1%, 47K resistor 51/8511/047K
R502 0805, 1%, 47K resistor 51/8511/047K
R503 0805, 1%, 22K resistor 51/8511/022K
R504 0805, 1%,1K resistor 51/8511/01K0
R505 0805, 1%, 10K resistor 51/8511/010K
R506 0805, 1%, 10K resistor 51/8511/010K
R507 0805, 1%, 1M resistor 51/8511/01M0
R508 0805, 0.5%, 50ppm,15K resistor 51/85P1/015K
R512 0805, 1%, 10K resistor 51/8511/010K
R513 0805, 1%, 10K resistor 51/8511/010K
R514 0805, 1%, 15K resistor 51/8511/015K
R515 0805, 1%, 330K resistor 51/8511/330K
R516 0805, 1%, 680R resistor 51/8511/680R
R517 0805, 1%, 47K resistor 51/8511/047K
R518 0805, 1%, 47K resistor 51/8511/047K
R519 0805, 1%, 47K resistor 51/8511/047K
R520 0805, 1%, 47K resistor 51/8511/047K
R521 0805, 1%, 47K resistor 51/8511/047K
R522 0805, 1%, 270K resistor 51/8511/270K
R523 0805, 1%, 1K resistor 51/8511/01K0
R525 0805, 1%, 10K resistor 51/8511/010K
R526 0805, 1%, 2K2 resistor 51/8511/02K2
R527 0805, 1%, 47K resistor 51/8511/047K
R528 0805, 1%, 47K resistor 51/8511/047K
R529 0805, 1%, 47K resistor 51/8511/047K
R534 0805, 1%, 5K6 resistor 51/8511/05K6
R535 0805, 1%, 100K resistor 51/8511/100K
R536 0805, 1%, 10K resistor 51/8511/10K
R537 0805, 1%, 100K resistor 51/8511/100K
R602 0805, 1%, 10K resistor 51/8511/010K
R603 0805, 1%, 10K resistor 51/8511/010K
R604 0805, 1%, 10K resistor 51/8511/010K
R605 0805, 1%, 15K resistor 51/8511/015K
R606 0805, 1%, 5K6 resistor 51/8511/05K6
R607 0805, 1%, 5K6 resistor 51/8511/05K6
R608 0805, 1%, 2K2 resistor 51/8511/02K2
R609 0805, 1%, 10K resistor 51/8511/010K
R610 0805, 1%, 10K resistor 51/8511/010K
R611 0805, 1%, 10K resistor 51/8511/010K
R612 0805, 1%, 10K resistor 51/8511/010K
R613 0805, 1%, 47R resistor 51/8511/047R
R614 0805, 1%, 47R resistor 51/8511/047R
R615 0805, 1%, 47R resistor 51/8511/047R
R616 0805, 1%, 47R resistor 51/8511/047R
R617 0805, 1%, 1K resistor 51/8511/01K0
R618 0805, 1%, 1K resistor 51/8511/01K0
R620 0805, 1%, 1K2 resistor 51/8511/1K2
R622 0805, 1%, 5K6 resistor 51/8511/05K6
R623 0805, 1%, 5K6 resistor 51/8511/05K6
R624 0805, 1%, 22K resistor 51/8511/022K
41
R625 0805, 1%, 22K resistor 51/8511/022K
R626 0805, 1%, 2K2 resistor 51/8511/02K2
R627 1218, 5%, 150R, 1W, SMD resistor 51/2851/0150
R628 1218, 5%, 150R, 1W, SMD resistor 51/2851/0150
R629 0805, 1%, 270K resistor 51/8511/270K
R630 1206, 1%, 120R resistor 51/3380/120R
R631 0805, 1%, 47R resistor 51/8511/047R
R632 0805, 1%, 47R resistor 51/8511/047R
R633 1218, 5%, 150R, 1W, SMD resistor 51/2851/0150
R634 1206, 1%, 120R resistor 51/3380/120R
R635 0805, 1%, 560R resistor 51/8511/560R
R636 0805, 1%, 220R resistor 51/8511/220R
R637 0805, 1%, 5K6 resistor 51/8511/05K6
R638 0805, 1%, 5K6 resistor 51/8511/05K6
R639 0805, 1%, 10K resistor 51/8511/010K
R640 1218, 5%, 150R, 1W, SMD resistor 51/2851/0150
R646 0805, 1%, 4K7 resistor 51/8511/04K7
R647 0805, 1%, 10K resistor 51/8511/010K
R648 0805, 1%, 4K7 resistor 51/8511/04K7
R649 0805, 1%, 10K resistor 51/8511/010K
R650 0805, 1%, 5K6 resistor 51/8511/05K6
R700 0805, 1%, 120R resistor 51/8511/120R
R701 0805, 1%, 100R resistor 51/8511/047R
R702 0805, 1%, 100R resistor 51/8511/120R
R703 0805, 1%, 100R resistor 51/8511/120R
R704 0805, 1%, 100R resistor 51/8511/120R
R705 0805, 1%, 100R resistor 51/8511/220R
R706 0805, 1%, 220R resistor 51/8511/220R
R707 0805, 1%, 100R resistor 51/8511/220R
R708 0805, 1%, 4K7 resistor 51/8511/04K7
R709 0805, 1%, 10K resistor 51/8511/010K
R710 0805, 1%, 2K2 resistor 51/8511/02K2
R711 0805, 1%, 10R resistor 51/8511/010R
R712 0805, 1%, 56R resistor 51/8511/056R
R713 0805, 1%, 10K resistor 51/8511/010K
R714 0805, 1%, 56R resistor 51/8511/056R
R715 0805, 1%, 10K resistor 51/8511/010K
R716 0805, 1%, 47R resistor 51/8511/047R
R717 0805, 1%, 10K resistor 51/8511/010K
R718 0805, 1%, 100R resistor 51/8511/120R
R719 0805, 1%, 10K resistor 51/8511/010K
R720 0805, 1%, 100K resistor 51/8511/100K
R721 0805, 1%, 330R resistor 51/8511/330R
R722 0805, 1%, 22K resistor 51/8511/022K
R723 0805, 1%, 10K resistor 51/8511/010K
R724 0805, 1%, 56R resistor 51/8511/056R
R725 0805, 1%, 5K6 resistor 51/8511/05K6
R726 0805, 1%, 47R resistor 51/8511/047R
R727 0805, 1%, 22K resistor 51/8511/022K
R729 0805, 1%, 10R resistor 51/8511/010R
R730 0805, 1%, 100R resistor 51/8511/100R
R731 0805, 1%, 560R resistor 51/8511/560R
R732 0805, 1%, 22K resistor 51/8511/022K
R733 0805, 1%, 1K resistor 51/8511/01K0
R734 0805, 1%, 4K7 resistor 51/8511/04K7
R735 0805, 1%, 22K resistor 51/8511/022K
R736 0805, 1%, 56R resistor 51/8511/056R
R737 0805, 1%, 330R resistor 51/8511/330R
R738 0805, 1%, 100R resistor 51/8511/100R
R739 0805, 1%, 10K resistor 51/8511/010K
R740 0805, 1%, 100R resistor 51/8511/100R
R741 0805, 1%, 1K resistor 51/8511/01K0
R742 0805, 1%, 220R resistor 51/8511/220R
R743 0805, 1%, 560R resistor 51/8511/560R
R745 0805, 1%, 330R resistor 51/8511/330R
R801 0805, 1%, 12K resistor 51/8511/012K
R802 0805, 1%, 100R resistor 51/8511/100R
42
R803 1218, 5%, 150R, 1W, SMD resistor 51/2851/0150
R804 1206 10R resistor 51/3380/0010
R805 1206 10R resistor 51/3380/0010
R806 1218, 5%, 150R, 1W, SMD resistor 51/2851/0150
R808 0805, 1%, 10R resistor 51/8511/010R
R809 0805, 1%, 27R resistor 51/8511/027R
R810 0805, 1%, 10R resistor 51/8511/010R
R811 0805, 1%, 27R resistor 51/8511/027R
R812 0805, 1%, 100R resistor 51/8511/100R
R813 1218, 5%, 150R, 1W, SMD resistor 51/2851/0150
R814 0805, 1%, 10R resistor 51/8511/010R
R815 0805, 1%, 1K resistor 51/8511/01K0
R816 0805, 1%, 10K resistor 51/8511/010K
R819 7W Axial 68R resistor 55/5W51/068R
R823 0805, 1%, 4K7 resistor 51/8511/04K7
R918 0805, 1%, 47K resistor 51/8511/047K
R919 0805, 1%, 47K resistor 51/8511/047K
R920 0805, 1%, 1K resistor 51/8511/01K0
R921 0805, 1%, 560R resistor 51/8511/560R
R922 0805, 1%, 220R resistor 51/8511/220R
R923 0805, 1%, 1K resistor 51/8511/01K0
R924 0805, 1%, 680R resistor 51/8511/680R
R925 0805, 1%, 220R resistor 51/8511/220R
R926 0805, 1%, 2K2 resistor 51/8511/02K2
R927 0805, 1%, 220R resistor 51/8511/220R
R928 0805, 1%, 220R resistor 51/8511/220R
R929 0805, 1%, 220R resistor 51/8511/220R
R930 0805, 1%, 220R resistor 51/8511/220R
R931 0805, 1%, 220R resistor 51/8511/220R
R932 0805, 1%, 220R resistor 51/8511/220R
R933 0805, 1%, 560R resistor 51/8511/560R
R934 0805, 1%, 560R resistor 51/8511/560R
R935 0805, 1%, 120R resistor 51/8511/120R
R936 0805, 1%, 120R resistor 51/8511/120R
RL300 12V Telecommunications DPDT Relay 96/2000/012V
RV100 100K, 11 turn, linear Pot. 53/THH1/100K
S200 4mm SMD PB switch 31/SMPB/0001
SW1 Omron-6x6-RA switch 31/0005/E121
T300 High Isolation Audio Transformer 37/2040/5065
T301 High Isolation Audio Transformer 37/2040/5065
U201 Quad CMOS RS232 Driver SMD (SO-14) 29/14C8/9A01
U202 Quad CMOS RS232 Driver SMD (SO-14) 29/14C8/8001
U203 Under-voltage sensor and Reset Generator 29/MC33/064D
U204 Motorola Embedded 8/16 bit microcontroller 29/68HC/12A0
U205 One of 8 Selector 29/2030/C138
U207 4 Megabyte TSOP (Std.) 5V (only) Flash 29/P006/0001
U208 1,2,4 Megabit RAM in SOP package 29/SRAM/P013
U212 Hi Speed, TTL compatible, opto-isolator 26/N137/0001
U300 Opto-isolator with Darlington Output 25/1010/4N33
U301 Quad SPST Analog Switch - low Rds On 29/00DG/411C
U302 Low Power Quad Operational Amplifier 29/000L/M224
U303 32 position digital pot. 29/MAX5/161L
U401 8-bit Shift reg. with output latch 29/2030/C595
U402 Transconductance Amplifier 29/0LM1/3700
U406 Voltage Output, Quad 8 bit DAC 29/00MA/X534
U500 CTCSS and DCS encoder/decoder 29/00FX/805L
U503 32 position digital pot. 29/MAX5/161L
U600 Gen. Purp. R2R Op. Amp. 29/1M55/P021
U601 Voltage Output, Quad 8 bit DAC 29/00MA/X534
U602 Dual PLL 29/LMX2/335L
U603 Temperature Sensor 29/0001/LM61
43
U604 Dual PLL 29/LMX2/335L
U605 Dual, Ripple Carry, 4 bit binary counter 29/2030/C393
U606 Dual 4 bit, ripple carry, decade counters 29/2030/C390
U700 MMIC Amplifier 24/3010/VAM6
U701 MMIC Amplifier 24/3010/211L
U704 Transconductance Amplifier 29/0LM1/3700
U907 Simple (Buck) Switcher, 5V, 1A output 29/REG1/0N12
U910 LDO Adjustable Positive Voltage Regulator 29/00LM/1117
U911 Positive Adjustable Voltage Reg. in SO8 package 29/000L/M317
U912 Positive Adjustable Voltage Reg. in SO8 package 29/000L/M317
U913 Negative Adjustable Voltage Reg. in SO8 29/000L/M337
X200 14.7456 MHz Crystal, 30ppm, SMD 33/14M7/0001
X500 4.0 MHz Crystal 32/2049/04M0
44
C T50 Parts List (Rev 3)
The following table highlights those components in Rev. 3 exciters, that differ from the
parts in Rev. 4. The values indicated are the values used in Rev.3
Ref Descr iption Par t #
C420 NF
C421 NF
C512 NF
C611 10nF Cer. Cap, X7R, 0603, 10% 46/63X1/010N
C726 3p9F Cer. Cap, NPO, 0603, 5% 46/63N1/03P9
C727 15pF Cer. Cap, NPO, 0603, 5% 46/63N1/015P
C728 15pF Cer. Cap, NPO, 0603, 5% 46/63N1/015P
C729 1p8F Cer. Cap, NPO, 0603, 5% 46/63N1/01P8
C731 NF
C734 3p9F Cer. Cap, NPO, 0603, 5% 46/63N1/03P9
C735 2p2F Cer. Cap, NPO, 0603, 5% 46/63N1/02P2
C744 NF
C752 NF
C755 47pF Cer. Cap, NPO, 0603, 5% 46/63N1/047P
C756 4p7F Cer. Cap, NPO, 0603, 5% 46/63N1/04P7
C757 120pF Cer. Cap, NPO, 0603, 5% 46/63N1/120P
C758 120pF Cer. Cap, NPO, 0603, 5% 46/63N1/120P
C759 47pF Cer. Cap, NPO, 0603, 5% 46/63N1/047P
C760 NF
C765 47pF Cer. Cap, NPO, 0603, 5% 46/63N1/047P
C766 NF
C767 NF
C768 NF
C769 NF
C804 18pF Cer. Cap, NPO, 0603, 5% 46/63N1/018P
C808 1p8F Cer. Cap, NPO, 0603, 5% 46/63N1/01P8
C809 NF
C812 1p8F Cer. Cap, NPO, 0603, 5% 46/63N1/01P8
C813 100pF Cer. Cap, NPO, 0603, 5% 46/63N1/100P
C815 56pF Cer. Cap, NPO, 0603, 5% 46/63N1/056P
C816 33pF Cer. Cap, NPO, 0603, 5% 46/63N1/033P
C818 10pF Cer. Cap, NPO, 0603, 5% 46/63N1/010P
C819 68pF Cer. Cap, NPO, 0603, 5% 46/63N1/01P8
C828 47pF Cer. Cap, NPO, 0603, 5% 46/63N1/047P
C830 NF
D503 NF
J4 NF
JP4 NF
L701 39nH Inductor 37/8551/039N
L703 NF
L704 NF
L705 NF
L713 220uH Choke 37/3320/P103
L720 220nH Inductor 37/3320/220N
L721 270nH Inductor 37/3320/270N
L722 220nH Inductor 37/3320/220N
L726 82nH Inductor 37/8551/082N
L805 120nH, air core 37/AC52/120N
L806 169nH, air core 37/MAXI/169N
L812 270nH Inductor 37/3320/270N
L813 NF
LC700 NF
45
LC701 NF
LC702 NF
R313 0805, 1%, 120K resistor 51/8511/120K
R314 0805, 1%, 22K resistor 51/8511/022K
R315 0805, 1%, 100K resistor 51/8511/100K
R316 0805, 1%, 22K resistor 51/8511/022K
R332 0805, 1%, 180K resistor 51/8511/180K
R333 0805, 1%, 1K resistor 51/8511/01K0
R337 NF
R404 0805, 1%, 10K resistor 51/8511/010K
R446 0805, 1%, 10K resistor 51/8511/010K
R448 0805, 1%,10K resistor 51/8511/010K
R451 0805, 1%, 47K resistor 51/8511/047K
R452 0805, 1%,10K resistor 51/8511/010K
R464 0805, 1%, 330K resistor 51/8511/330K
R514 0805, 1%, 22K resistor 51/8511/022K
R515 NF
R522 0805, 1%, 68K resistor 51/8511/068K
R534 NF
R535 NF
R536 NF
R537 NF
R600 0805, 1%, 4K7 resistor 51/8511/04K7
R602 0805, 1%, 27K resistor 51/8511/027K
R603 0805, 1%, 27K resistor 51/8511/027K
R604 0805, 1%, 100K resistor 51/8511/100K
R605 0805, 1%, 18K resistor 51/8511/018K
R609 0805, 1%, 22K resistor 51/8511/022K
R610 0805, 1%, 47K resistor 51/8511/047K
R612 0805, 1%, 100K resistor 51/8511/100K
R617 0805, 1%, 560R resistor 51/8511/560R
R619 0805, 1%, 680R resistor 51/8511/680R
R620 0805, 1%, 680R resistor 51/8511/680R
R621 0805, 1%, 4K7 resistor 51/8511/04K7
R626 0805, 1%, 4K7 resistor 51/8511/04K7
R627 NF
R628 1218, 5%, 68R, 1W, SMD resistor 51/2851/0068
R633 1206, 1%, 120R resistor 51/3380/120R
R634 1206, 1%, 120R resistor 51/8511/120R
R640 NF
R701 0805, 1%, 47R resistor 51/8511/047R
R702 0805, 1%, 120R resistor 51/8511/120R
R703 0805, 1%, 120R resistor 51/8511/120R
R705 0805, 1%, 220R resistor 51/8511/220R
R711 0805, 1%, 56R resistor 51/8511/056R
R712 NF
R713 0805, 1%, 100K resistor 51/8511/100K
R714 0805, 1%, 120R resistor 51/8511/120R
R721 NF
R725 0805, 1%, 22K resistor 51/8511/022K
R733 0805, 1%, 330R resistor 51/8511/330R
R736 0805, 1%, 220R resistor 51/8511/220R
R737 0805, 1%, 1K resistor 51/8511/01K0
R738 0805, 1%, 220R resistor 51/8511/220R
R740 0805, 1%, 120R resistor 51/8511/120R
R741 0805, 1%, 4K7 resistor 51/8511/04K7
R742 0805, 1%, 180R resistor 51/8511/180R
R745 0805, 1%, 220R resistor 51/8511/220R
R801 0805, 1%, 22K resistor 51/8511/022K
R803 1218, 5%, 100R, 1W, SMD resistor 51/2851/0100
R806 1218, 5%, 100R, 1W, SMD resistor 51/2851/0100
R807 1218, 5%, 100R, 1W, SMD resistor 51/2851/0100
R813 1218, 5%, 100R, 1W, SMD resistor 51/2851/0100
R814 NF
R815 NF
46
D EIA CTCSS TONES
Fr equency EIA Number
No Tone
67.0 A1
71.9 B1
74.4 C1
77.0 A2
79.7 C2
82.5 B2
85.4 C3
88.5 A3
91.5 C4
94.8 B3
100.0 A4
103.5 B4
107.2 A5
110.9 B5
114.8 A6
118.8 B6
123.0 A7
127.3 B7
131.8 A8
136.5 B8
141.3 A9
146.2 B9
151.4 A10
156.7 B10
162.2 A11
167.9 B11
173.8 A12
179.9 B12
186.2 A13
192.8 B13
203.5 A14
210.7 B14
218.1 A15
225.7 B15
233.6 A16
241.8 B16
250.3 A17
47
uP
uP
CTCSS
Summing
Generator
Amplifier
uP
Buffer
Tone+ Low Pass
Filter (250Hz)
Tone- Digital
Balanced Differential Line 2 Pre-emphasis Potentiometer
Amplifier Deviation uP Buffer Limiter
uP uP PLL: Phase Locked Loop
Control
VCA: Voltage Controlled Amplifier

T300 Maximum Tone Deviation Summing
Line2+ VCA VCO: Voltage Controlled Oscillator
uP Setting Amplifier
uP
and
Dir. Aud. (Tone IN) Deviation uP: Microprocessor Input or Output
Control
Line2- Buffer
Flat
uP Low Pass
Pre-emphasis Filter (3kHz)
uP
uP
Line 1
Summing
Deviation Vref
Amplifier
Control Digital
Amplifier
T301 Potentiometer
6dB gain
Line2+ VCA uP Line Level In
uP Peak
uP uP
Detector Maximum Deviation Line
Limiter Potentiometer
Line Level Sense Setting
Amplifier
uP
20dB gain
Line2-
Flat
Pre-emphasis
Modulation
uP
Balance
Loop/Volts Microphone input Centre Frequency Reference
uP VCA
Select Adjustment Oscillator uP
uP
Set Synthesiser
uP Modulation PLL uP
Dividers
Lock Detect and
+12V Reference Osc. Detect
RF
Amplifier Varactor
uP uP
Bias Low Pass
Loop Detect VCO
Filter (350MHz)
uP
RF uP RF
Amplifier Output
RF
Amplifier RF RF
External External Ref. Div.
Amplifier Amplifier
Reference Varactor Passive Low Pass Voltage Controlled Low Pass
3200 uP
Input Bias Mixer Filter (55MHz) RF Filter (55MHz)
uP
VCO Low Pass Amplifier
Filter (300MHz)
RF
Amplifier
High Speed Coupler Channel PLL

Set Synthesiser Title Block Flow Diagram of Audio and RF signals in 9154(T50)
GPS+ uP uP
GPS Dividers
Lock Detect and
uP
GPS- Reference Osc. Detect Size: A4 Number: 05/9 Revision: A
Centre Frequency
RF Technology Pty Ltd
uP Print Date: 8-Apr-2003 10:28:51 Sheet 1 of 1 Unit 10, 8 Leighton Place
Adjustment Temp.
uP Hornsby, NSW 2077
Reference Rev. Release Date: Originator: Australia
Temp. Sensor
Oscillator
File: D:\Protel Files\Copies from Crocodile\t50_4.ddb - Issue4\BLOCK_DIAGRAM.Sch
1 2 3 4 5 6 7 8
5V_PROT
D10 R20 PA_CS

D 180R D
BAV99
GND
5V_PROT
FD1
FIDUCIAL
D11
R21 SCLK FD2
180R FIDUCIAL
BAV99
GND
5V_PROT
D12
R22 MOSI
180R
C BAV99 C
+5V
J1 +28V GND
R19
22R
13 5V_PROT
25
LK1 JUMPER
12
D13 R3 R4 R5 R6 R7 R8 R9 R10
24 C1
16
11 PTT_IN R1 R2 100nF
74HC165
23 T/R_RELAY 100K 100K 100K 100K 100K 100K 100K 100K LK2
BZX84C5V6 JUMPER
10 LINE2+ 47K 47K
22 LINE2- 6 47K CH80
VCC
I7 R11 47K 2 1
9 TONE+ GND 5 CH40
I6 47K R12 3 LK3
21 TONE- 15 4 CH20 JUMPER
R23 C I5 R13 47K 4
8 LINE- 2 3 CH10
C I4 47K R14 5
20 GPS+ 180R 9 14 CH8
R24 Q I3 R15 47K 6
7 GPS- 7 13 CH4 LK4 JUMPER
Q I2 47K R16 7
19 LINE+ 180R 1 12 CH2
PL I1 R17 47K 8
6 11 CH1
Q1 I0 R18 9 10
18 CH_EN 10
BSS138 SI
5
GND
5X2 Header
17 +5V
4 Vref D9 U1
16
8
R25 BAW56
3 +12V GND
B 15 180R B
2
14
D1
D2
D3
D4
D5
D6
D7
D8
DB25
BAV99
BAV99
BAV99
BAV99
BAV99
BAV99
BAV99
BAV99
5V_PROT
D14
R26 CS2
180R
BAV99
GND
A A
Rev No. ECO No. Description of Change
Title Rear Panel Board for 9154 (T50) and 9155 (R50)
Size: A3 Number: 05/9160 R7 Revision: 1

Print Date: 16-Aug-2002 09:56:54 Sheet 1 of 1 Unit 10, 8 Leighton Place
Hornsby, NSW 2077
Rev. Release Date: Originator: Australia
File: F:\Obsoleted Files\Old Files Backup\916x.ddb - T50_R50_rear_panel.Sch
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
FILTER_OFF
FILTER_OFF
D C509 +5TONE L500 +5V D
18
24
BLM31A601
1uF U500
C508
100nF
C501 +5V
VCC
Vbias
1 GND
XTAL
R507 R512
22pF 1M
GND X500 10K
C500 4MHz
2 4
XTAL/CLK IRQ TONE_INT
22pF
CTCSS_SEL 7
CTCSS_SEL CS
3
ADDR
SCLK 5
SCLK SCLK
MOSI 6
MOSI Din
8 C513
Dout R514
9 CTCSS_OUT
C502 TONE_OUT
16
RX_SUB_IN 1uF 10K
17
RX_SUB_OUT
100nF TP500
14 TONE+CTCSS
RX_IN+
1
13
RX_IN-
15 U301A
RX_OUT R503
22 2 3
NO_TONE
20
COMP+ 22K
19 DG411
C COMP- C
21
COMP_OUT
C503
10 11 2 U502A
AUDIO_IN AUDIO_OUT R517 R518 R519
1 10 U502C
100nF 3 8
47K 47K 47K
WAKE
LM224 C516 9
GND
R527 C514 C515 LM224

R516 47K 22nF (X7R - 10%) 100nF 1n2F (NPO)
680R (NPO)
FX805 GND GND
23
12
-10V
GND GND
+10V R528 R522
+10V 47K 68K
U502D
4
R530, R531, R508, R509, R532, R533, R510, AND R511 C510 12
D500 R526
Should be 0.25%, 50ppm TC or better 14 TONE_OUT
100nF R523 TONE_OUT
BAV99 -10V +2.5V 13
V+
R530 R508 R510 1K 2K2 D502 D503
U502E LM224
TONEP-
GND
7K5 7K5 7K5 LM224
6
V-
R500 R532 U503 R525 BAV99
47K C506
100pF
VDD
7K5 10K R529
TP501 2
11
TONE_IN 47K BAV99
C507 R524 R534
GND R501 -10V D501 U502B 5 NF NF
47K 100pF U301D C511 INC
6 -10V +2.5V 4 GND GND
B BAV99 R504 U/D B
7 15 14 1
GND
R531 R509 MMBT3906
5 100nF -10V
TONEP+ 560R R505
7K5 7K5 LM224 DG411 Q500 GND
GND
R502 10K MAX5161L
16
+10V R533 R511
3
47K
7K5 7K5 +5V
R520
47K -2.5V
R513 -10V
GND 10K
-2.5V
EXT_TONE_SEL
+2.5V
TONE_DEV_INC
R506 Q501
TONE_DEV_U/D
10K
MMBT3906
R521
47K
-2.5V
A A
Title Tone Generation Section
Size: A3 Number: 9154 Revision: B

Print Date: 20-Feb-2002 23:41:52 Sheet 5 of 9 Unit 10, 8 Leighton Place
Hornsby, NSW 2077
File: C:\Program Files\Design Explorer 99 SE\rft\t50\t50.Ddb - tonetx.sch
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
+5Q +5Q
R631
+5Q
R605 R609 47R C630 C631
5
MOD_IN R616
MOD_IN
27K 10K 47R U600
1uF 10nF 4
R622
+5Q 1 MOD_BIAS
MOD_BIAS
+5Q GND GND 3
R613 5K6
5
+5Q C604 C609 TS971LT
R617 L713 C628 R625
R608 U607 47R C602 C613
4 C621 1uF 10nF 220uH 22K
1K
2
16
15
R602 R603
2
D 1 R618 * 100nF D
C601 2K2 1uF
3 10nF GND 1K 220nF -5V
27K C610 27K
TS971LT
VCC1
VCC2
Vp2
Vp1
100nF Vref C611 GND GND GND
R611
6 3 PDOUT_MOD
2
470pF Xin DO1 C625 C618
GND 2K2 X600 C612 +
MMBV109 10nF
-5V GND 14 +5V
R637 DO2 100nF
3u3F ** NF
5K6 D600 12M 7 12
C614 Xout Fin2
R621
C615 C620 11 5 GND
LE Fin1 4K7
C643 C624 C605 15pF SCLK 9
R607 R604 15pF 33pF CLK R648
MOSI 10 8 Fo_MOD MOD_PLL_SENSE
GND
GND
5K6 100nF 100K 10nF DATA FoLD MOD_PLL_SENSE
1uF 4K7
C634 +5Q C645
R649
U602 10K
GND -5V GND C649
13
4
LMX2335L 10nF 100nF
MOD_PLL_SEL R615
MOD_PLL_SEL
R632 47R 10pF
+5Q GND GND
GND +5Q
R614 47R
5
+5Q C608 C616
47R C619 C607
R612 C603 C600 U608
1uF 10nF 4
16
15
R623
2
10nF 1uF 1uF 10nF 1 CHAN_BIAS
100K CHAN_BIAS
-5V GND 3
MMBV109 C636 5K6
GND TS971LT
VCC1
VCC2
C629
Vp2
Vp1
C 10nF C627 R624 C
R619 22K
6 3 PDOUT_CHAN
2
1uF Xin DO1
D601 C640 C635 C637 X601 680R 100nF
14 -5V
C638 12M DO2
8p2F 8p2F 56pF
7 12 C622 R620 GND
Xout Fin2
GND 10nF GND C650 680R
CHAN_PLL_SEL 11 5 100nF
CHAN_PLL_SEL LE Fin1
SCLK 9 10pF
CLK C652 C647
MOSI 10 8
GND
GND
R629 R610 DATA FoLD C626 +
MOD_ADJ_FINE GND +5V
47K NF
270K 10nF 3u3F
**
R606 U604
MOD_ADJ GND
13
4
LMX2335L R600
C639 GND
5K6 R650 4K7
100nF R646
+5Q GND Fo_CHAN CHAN_PLL_SENSE
5K6 CHAN_PLL_SENSE
Vref VCO Section
4K7 C646 R647
GND vco.sch
C617 10K
13
C648 100nF
100nF U601 CHAN_VCO_OUT
MOD_IN
2PORT_MOD MOD_VCO_OUT
VCC
Vref
GND 5 100nF GND

PDE
2 CHAN_ADJ
OUTA
RESET 7 1 BALANCE
RESET CLR OUTB BALANCE L718
6 16
LDAC OUTC CHAN_PLL_IN
15 C623 220uH +5Q
B OUTD B
SIGGEN_ADSEL 9
SIGGEN_ADSEL CS
SCLK 10 8
SCLK SCLK Dout * * C613 AND C623 CAN BE X7R(10%)
DGND
AGND
1
MOSI 11 4 MOD_VCO_EN 220nF
MOSI Din UPO MOD_VCO_EN
** C625 and C626 should be 10% Tantalums U603 LM61 U400A
GND Case Size A 2
V+
CHAN_VCO_EN Placed near X601
1 TEMP
MAX534 TEMP
2 Vt 3
12
14
T/R_RELAY Vo
LM224
GND
+5V
MOD_PLL_IN C651
GND
CHAN_VCO_EN L600 100nF
3
BLM31A601 R638 R639
T/R_RELAY
5K6 10K
GND
C606 C644
14
16
VCO_OUT VCO_OUT
100nF 100nF
74HC393
74HC390
GndVcc
GndVcc
Divide by 128 GND GND

R635 R636
560R 220R U605A
C642
3
100pF QA U605C U606C
1 4
7
1A QB
Q600 2 5
R QC
C641 6
R633 R634 QD
A GND A
EXT_REF_IN
GND 74HC393 Fo_MOD_2 Rev No. ECO No. Description of Change
120R 120R Fo_MOD_2
100nF MMBT3904 U606A
Fo_MOD 1
1A QA
3 U606B Title Frequency Synthesiser
R628 R630 11 4 5 Fo_CHAN 15 13 Fo_CHAN_2
68R 120R QA 1B QB 1A QA Fo_CHAN_2
13 10 6 12 11
12
1A QB
9 2
QC
7
1B QB
10
R QC
8
R QD
14
QC
9
QD R QD EXT_REF_DIV Print Date: 20-Feb-2002 23:40:44 Sheet 6 of 9 Unit 10, 8 Leighton Place
GND 74HC390
Hornsby, NSW 2077
74HC393 Divide by 25 74HC390
U605B GND GND
File: C:\Program Files\Design Explorer 99 SE\rft\t50\t50.Ddb - siggen.sch
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
TP908
+5Q
12V +10V
12V +10V
D U907 Max output current is 1A D
+5Q
LM2595S-12 TP916
TP909 TP910
L909 +10V +2.5V
2 4 U910 U911 U912
28V Vin FB 12V
L902 LM1117DTX-ADJ +10V LM317LM +5Q LM317LM +2.5V
BLM31P121SG L901
5 1 3 4 1 2 1 2
GND
GND
EN Vout Vin Vo Vin Vout Vin Vout +2.5V
DS5022P-224 33uH 2 3 3
C902 + Vo Vout Vout
+ C938 + C903 C923 1 C926 7 7
D907 ADJ Vout Vout
+ C940 6 C942 C931 6 C944
Vout Vout
ADJ
ADJ
470uF 3 100uF 33uF 100nF R925 100nF 5 8 + 5 8 +
6
MBRM140T3 NC NC NC NC
220R 33uF R927 R929 33uF
100nF
GND 220R 220R
33uF
GND Tantalum, ESR <= 0.3 ohms GND
4
GND GND
GND
R933 C932 R930
R920
C924 560R 220R
1K
C930
100nF
100nF
100nF
R935 GND
R921
120R
560R
12V
GND GND
D906
U908
C MBRM140T3 LM2595S-12 C
-10V -5V
2 4
Vin FB TP911 -10V -5V
C915 L903 TP914
R918
5 1 -10V -5V
GND
GND
EN Vout
DS5022P-334
C935 + 47K R919 TP917
100nF + C937 D910 GND
Low Impedance Type 47K D908 SM4004 U913 U914 U915
35V, 10mm dia -2.5V
100uF -12V LM337LM -10V LM337LM LM337LM -2.5V
3
6
470uF MBRM140T3 L905 2 1 2 1 2 1

-Vin -Vout -Vin -Vout -Vin -Vout -2.5V
220uH 3 3 3
Tantalum, ESR <= 0.3 ohms -Vin -Vin -Vin
7 C941 7 7
-Vin -Vin -Vin
C920 6 6 C943 C933 6 C945
C901 -Vin -Vin -Vin
ADJ
ADJ
ADJ
+ C927
100uF 5 8 5 8 5 8
NC NC R922
+ NC NC R928
+ 100nF NC NC R931
+
100nF 33uF 33uF 33uF
220R 100nF 220R 220R
4
GND GND GND
GND GND
R923 R934 C934 R932
1K 560R 220R
100nF
C925 C928
100nF R924 100nF R936 GND

560R 120R
TP913
B B
Vref
GND GND
U909 Output Current is 750mA (max)

LM2595S-5 +5Q
TP912 TP915
12V
5
2 4
Vin FB +5V U906 GND
L904 +5V
5 1 +10V 4 Vref
GND
GND
EN Vout +5V GND

+ C936 DS5022P-224 1
R926 Vref
+ C939 3 GND
33uF D909 L906 +5D1 TS971LT
100uF 2K2 D911 C929 C904
3
6
MBRM140T3
BLM31P121SG +
2
100nF
Tantalum, ESR <= 0.3 ohms Tantalum, ESR <= 0.3 ohms ZRC400F01 3u3F
GND L907 +5D2
BLM31P121SG GND
L908 +5D3
BLM31P121SG
A A
Title Power Generation Section

Hornsby, NSW 2077
File: C:\Program Files\Design Explorer 99 SE\rft\t50\t50.Ddb - power.sch
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
D D
28V
R813 L800 L801 R819

C801 BLM31A601 BLM31A601
100R 68R
C827 + Murata Ferrite C810 C811 + C802 L803
100nF 10uF R806 SMD Choke 100uF 558nH
+10V 35V 100R C806 100nF 35V 1n2F
Coilcraft Maxi Spring Coils
C GND 10nF GND C
R802 L804
47R R807 GND 558nH
100R
C823
R812
100nF 220R L810
1uH L805 L806
GND C807 120nH 169nH
C824
L811 C808 C812
3u3H 100nF C822 Q804 Q805 1n2F 1p8F 1p8F
R808
GND RF_out
4
RF_out
GND C825 10R BFQ17 BFQ17
L809 R811 10nF C818
1 3 Q801 C816
RF_in D800
180nH BFQ17
27R C805 33pF 10pF BAT54C
MSA0311 U800 220pF R804 R805
2
C804 C820 C814 C813 C819 C809

10R 10R
470pF 470pF C815 C817
47pF NF 56pF 100pF NF 68pF NF
GND R803 C821 GND C803 R816

100R GND 10K
100nF 1nF
L807 R809 L808 R810 LOC_FWD_PWR

B PWRCNTRL B
220uH 3u3H R823
27R C829 10R 4K7
GND
C826 +
100nF
3u3F
GND
GND
A A
Title Broadband Power Amplifier

Hornsby, NSW 2077
File: C:\Program Files\Design Explorer 99 SE\rft\t50\t50.Ddb - pa.sch
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
+5D2 +5D2 +5D3 +5D1 +5LCD

R241 R244
C222
47R 10R R224 R225 R223
L200 R236 Vref
100nF 220uH 10K 10K 10K
22K
C214 C220 C225
R235 R240 C224
GND 100nF C226 C205 C204 C206 C207
LINE_LEVEL_IN 10K
100nF 100nF
4K7 R243 LCD_RS
100nF 100nF 100nF 100nF 100nF 100nF
Q203 220R
85
43
14
42
79
95
X200 LCD_R/W
2
MMBT2369 GND
14M7456 Q202 R242 LCD_E
DG411
D TEMP 10 11 28V MMBF5484 C221 U204 GND +5D3 +5D1 D
VCC
VCC
VCC
VCC
VCC
Vref
Vddpll
TEMP R239 47K
R213 46
EXTAL
1M 74 MOD_PLL_SEL
U403C R207 1K Q204 PF6 MOD_PLL_SEL R220 R219
100nF 71 LCD_RS
PF3
9
68K 70 LCD_R/W 10K 10K

R237 R238 PF2
47K 1K MMBT2369 47 69 LCD_E
XTAL PF1
GND +5D2 C212
44 CS0
R202 C203 XFC
GND R/W
20
12V
10K 100nF U209 100nF
CHAN_PLL_SENSE 94 L205 +5D1
CHAN_PLL_SENSE AN7
MOD_PLL_SENSE 93 11
VCC
D202 MOD_PLL_SENSE AN6 BLM31A601 C
R201 VIN_SENSE 92 1 GND
16
AN5 C208 E
SM4004 GND LINE_LEVEL_SENSE 91
10K LINE_LEVEL_SENSE AN4 U205 100nF
CHAN_BIAS 90 D7 3 2 LCD_DB7
CHAN_BIAS AN3 I7 O7 LCD_DB7
LINE_LEVEL_IN 89 7 D6 18 19 LCD_DB6
VCC
T/R_RELAY AN2 Y7 I6 O6 LCD_DB6
MOD_BIAS 88 6 9 GND D5 4 5 LCD_DB5
MOD_BIAS AN1 EN1 Y6 I5 O5 LCD_DB5
LOC_FWD_PWR 87 4 10 D4 17 16 LCD_DB4
Q201 LOC_FWD_PWR AN0 EN2A Y5 I4 O4 LCD_DB4
T/R_RELAY_H 5 11 D3 7 6 LCD_DB3
BSS138 EN2B Y4 I3 O3 LCD_DB3
FRDY 27 68 12 RAMRD D2 14 15 LCD_DB2
PD7 CSO Y3 I2 O2 LCD_DB2
R208 +5TONE FPSW1 26 72 3 13 RAMWT D1 8 9 LCD_DB1
GND
22K FPSW1 PD6 CSD S2 Y2 I1 O1 LCD_DB1
FPSW2 25 73 2 14 D0 13 12 LCD_DB0
GND
FPSW2 PD5 CSP0 S1 Y1 I0 O0 LCD_DB0
FPSW3 24 38 1 15
FPSW3 PD4 R/W S0 Y0
8
C227 LOOP/VOLTS_SEL 23
6N137 LOOP/VOLTS_SEL PD3 74HC374
TONE_DEV_U/D 22
10
100nF R216 TONE_DEV_U/D PD2 74HC138
GND 1 TONE_DEV_INC 21 +5D1
VCC
8
R214 NC 1K TONE_DEV_INC PD1
2 7 EXT_TONE_SEL 20 +5D1
GPS+ A Ve EXT_TONE_SEL PD0
GND -12V GND 12V
C 180R C
3 6 LINEINP_ADSEL 84 GND R218
GND
K Vo LINEINP_ADSEL PH7 10K L202

D203 4 LINEINP_DSEL 83 FWT
NC LINEINP_DSEL PH6 BLM31A601 L203 L204
BZX84C3V3 TEMP_LEVEL_IN 82 +5D1 FRD
R215 PH5 BLM31A601 BLM31A601
PWR_CNTRL_HIGH 81 CSD +5D2
PWR_CNTRL_HIGH PH4
120R U212 CTCSS_SEL 78
5
CTCSS_SEL PH3 R217

CHAN_PLL_SEL 77 C210 C217
10
31
R227 CHAN_PLL_SEL PH2 10K C211 C201 C215
SIGGEN_ADSEL 76
GPS- SIGGEN_ADSEL PH1 U207 100nF 100nF
GND CHAN_VCO_EN 75 100nF
14
56R CHAN_VCO_EN PH0
1
CSP0 9 100nF 100nF
VCC
VCC
U202D CE
12 EXT_REF_DIV 112 37 GND GND
32
EXT_REF_DIV PT7 OE
11 SPARE_SEL 111 38 GND GND
V-
V+
RTS SPARE_SEL PT6 WE U208
14C88 13 U202B CH_EN 110 RESET 12
CH_EN PT5 RESET
Gnd
4 GPS 109 36 FRDY 22
VCC
PT4 RY/BY CS
6 TERM_EN2 108 18 A21 A21 39 24
DBGTX 14C88 TERM_EN2 PT3 A21 A21 OE
5 TERM_EN1 107 17 A20 A20 40 29 14C88
TERM_EN1 PT2 A19 A20 WE U202E
U202C 9 Fo_MOD_2 106 16 A19 A19 1
7
14C88 Fo_MOD_2 PT1 A19 A19
8 Fo_CHAN_2 105 13 A18 A18 2 A18 1
TXDATA Fo_CHAN_2 PT0 A18 A18 A18
10 12 A17 A17 3 35 D7 A17 30
A17 A17 D7 A17
1 LCD_DB7 51 11 A16 A16 4 34 D6 A16 2 GND
DSR PE7 A16 A16 D6 A16
3 ECLK 48 67 A15 A15 5 33 D5 A15 31
14C89A PE4 A15 A15 D5 A15
2 TX_LED 39 66 A14 A14 6 32 D4 A14 3 21 D7 +5D3
C U201A TX_LED PE3 A14 A14 D4 A14 D7
65 A13 A13 7 28 D3 A13 28 20 D6
A13 A13 D3 A13 D6 C216
4 U201B T/R_RELAY_H 104 64 A12 A12 8 27 D2 A12 4 19 D5
14
CTS SS A12 A12 D2 A12 D5
6 SCLK R230 SCK 103 63 A11 A11 13 26 D1 A11 25 18 D4
SCLK 120R SCK A11 A11 D1 A11 D4 U201E
5 MOSI SD 102 62 A10 A10 14 25 D0 A10 23 17 D3 100nF
C 14C89A MOSI 120R MOSI A10 A10 D0 A10 D3
10 PA_CS R231 101 61 A9 A9 15 A9 26 15 D2
V+
DBGRX PA_CS MISO A9 A9 A9 D2
8 DBGTX_TTL 100 60 A8 A8 16 A8 27 14 D1 GND
TxD1 A8 A8 A8 D1
14C89A 9 DBGRX_TTL 99 59 A7 A7 17 A7 5 13 D0
B C RxD1 A7 A7 A7 D0 B
Gnd
U201C TXD_TTL 98 58 A6 A6 18 A6 6
TxD0 A6 A6 A6
13 U201D RXD_TTL 97 57 A5 A5 19 A5 7
RXDATA RxD0 A5 A5 A5
11 RTS_TTL 56 A4 A4 20 A4 8
A4 A4 A4 14C89A
12 DTR_TTL 10 55 A3 A3 21 A3 9
7
C PJ7 A3 A3 A3
14C89A DSR_TTL 9 54 A2 A2 22 A2 10
PJ6 A2 A2 A2
3 2 CTS_TTL 8 53 A1 A1 23 A1 11
GND
GND
GND
DTR PJ5 A1 A1 A1
+5D3 7 52 A0 A0 24 A0 12 GND
NC
14C88 U202A PJ4 A0 A0 A0
+5V +5D1 PTT_uPHONE 6
PTT_uPHONE PJ3
TONE_INT 5 35 D7 29F032
R234 TONE_INT PJ2 D7 K6T4008
LOOP_DET 4 34 D6
30
29
11
16
R232 R245 R204 R203 LOOP_DET PJ1 D6
1K FILTER_OFF 3 33 D5
R206 10K 10K FILTER_OFF PJ0 D5
32 D4
560R 2K2
Q205 10K 36
D4
31 D3 GND GND
R212 MMBT3906 XIRQ D3
INT 37 30 D2
PTT_IN IRQ D2
29 D1 A[0..21]
220R R229 DEV_H_L D1
28 D0
R211 R221 D0
220R BKGD_ISO 19 D[0..7]
D200 C209 10K BKGD BKGD
10K DEV_H_L 50
560R MODB
ALARM_LED 49
GNDref
GNDpll
R228 ALARM_LED MODA

10nF RESET 40
GND
GND
GND
GND
GND
Q206 RESET RESET

MMBT3904
BAV99
GND +5D3 R233
R209 22K MC68HC812A0
+5D3
86
45
15
41
80
96
1
C202 R226
C219 330R PWR_OK
2
+ R205
100nF 2K2 R222 180R
U203 GND
A 3u3F 3 GND 1K A
VCC
NC
5 Rev No. ECO No. Description of Change
NC R210 Q200
GND 6 1 RESET
NC RES
7 MMBT3904 Title Microprocessor
GND
NC 10K
8
NC
S200
7914G GND
MC33064D RF Technology Pty Ltd
4

Hornsby, NSW 2077
GND
File: C:\Program Files\Design Explorer 99 SE\rft\t50\t50.Ddb - micro.sch
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
JP12
uPHONE_IN
1
2
AUDIO PROCESSING SECTION PTT_uPHONE
3
audio.sch
4
MICROPROCESSOR CONTROL SECTION
LCD_BIAS micro.sch 4 HEADER
LCD_BIAS
GND
+5D3
FILTER_OFF FILTER_OFF
PTT_uPHONE
D D
TP102 LINE_LEVEL_SENSE LINE_LEVEL_SENSE R100 R101 R102 R103 R104
4K7 4K7 4K7 180R 270R
28V CTCSS_SEL CTCSS_SEL
28V SCLK
SCLK SCLK
MOSI
MOSI MOSI ALARM
L100 TONE_INT TONE_INT
D102 RED
BLM31P121SG C100
P3 NFA31CC102 EXT_TONE_SEL EXT_TONE_SEL ALARM_LED
SCLK
LOOP/VOLTS_SEL LOOP/VOLTS_SEL
PA_CS D103 AMBER
13 PTT_IN Tx Data
LINEINP_DSEL LINEINP_DSEL TX_LED
25
uPHONE_IN LINEINP_ADSEL LINEINP_ADSEL
12 D104 GREEN
24
TERM_EN2 TERM_EN2 PWR_OK
11
TERM_EN1 TERM_EN1 POWER OK
23 T/R_RELAY C101
2
10 HiZ+ NFA31CC102 L2+ RESET
L2+ RESET RESET FPSW1 SW1
22 HiZ- L2-
L2-
9 TONE+
3 2
TONE+ PWR_CNTRL_HIGH PWR_CNTRL_HIGH
21 TONE- C&K_PB
TONE- FPSW2
8 LINE_I/P4 C102
NFA31CC102 DEV_H_L DEV_H_L
20 L1+
L1+
7 GPS+ Vref
3
TONE_DEV_U/D TONE_DEV_U/D FPSW3
19 LINE_I/P1 GPS- GND
6 L1-
L1- TONE_DEV_INC TONE_DEV_INC
18
5 RV100
C103 LOOP_DET LOOP_DET R105 100K
17 MOSI PWRCNTRL
C PWRCNTRL LINE_LEVEL_IN C
4 CH_EN
MOD_OUT 4K7
16 SPARE_SEL +5D3
3 PTT_IN JP3
PTT_IN
15 NFA31CC102 BKGD
BKGD 1
2 Vref RF SIGNAL GENERATOR T/R_RELAY GND
T/R_RELAY 2
14 GND L101 +5V siggen.sch
3
1 PA_CS RESET Debug/Monitor Port
MOD_IN PA_CS 4
12V BLM31A601
5
GPS+
SCLK GPS+ 6
GPS-
DB25RA/F MOSI GPS- 7
GND CH_EN +5LCD L102 +5D1
CH_EN 8
SPARE_SEL DBGTX
RESET SPARE_SEL DBGTX 9
DBGRX BLM31A601
DBGRX 10
T/R_RELAY
T/R_RELAY JP2
POWER AMPLIFIER CON10
pa.sch SIGGEN_ADSEL GND
SIGGEN_ADSEL SIGGEN_ADSEL 1
L104 2
BNC Right Angle - Low Profile MOD_PLL_SEL LCD_BIAS
RF_in VCO_out MOD_PLL_SEL MOD_PLL_SEL 3
MOD_BIAS BLM31A601
J1 RF_out MOD_BIAS MOD_BIAS LCD_RS 4
MOD_PLL_SENSE
PWRCNTRL MOD_PLL_SENSE MOD_PLL_SENSE LCD_R/W 5
CHAN_PLL_SEL
LOC_FWD_PWR CHAN_PLL_SEL CHAN_PLL_SEL LCD_E 6
CHAN_BIAS
CHAN_BIAS CHAN_BIAS LCD_DB0 7
GND CHAN_PLL_SENSE HEADER 14
CHAN_PLL_SENSE CHAN_PLL_SENSE LCD_DB1 8
LCD_DB2 9
Fo_MOD_2
Fo_MOD_2 Fo_MOD_2 LCD_DB3 10
Fo_CHAN_2
J4 Fo_CHAN_2 Fo_CHAN_2 LCD_DB4 11
EXT_REF_DIV
EXT_REF_DIV EXT_REF_DIV LCD_DB5 12
B EXT_REF_IN LCD_DB6 13 B
LCD_DB7 14
BNC-2
TEMP TEMP
GND
5
CHAN_VCO_EN CHAN_VCO_EN SG
9
RI
4
DTR
RTS 8
RTS CTS
RXDATA 3
RXDATA TXD
CTS 7
CTS RTS
LOC_FWD_PWR TXDATA 2
LOC_FWD_PWR TXDATA RXD
DTR 6
DTR DSR
DSR 1
DSR DCD
P1 DB9
GND
POWER SECTION NB: connector signals reversed
power.sch 12V so that straight through cable can be used to PC
+10V
12V
+5V
+10V
28V +5Q
+5V
Vref
+5Q
28V
A +2.5V A
Vref
+2.5V
Title T50 Master Schematic
GND -2.5V
GND
-5V
-2.5V
-10V Hornsby, NSW 2077
-5V
-10V
File: C:\Program Files\Design Explorer 99 SE\rft\t50\t50.Ddb - Master.sch
71
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
+2.5V TEST_DEV
DEV_H_L
1
R446 Q402
+10V Io = Is(2Iabc/Id) : Io= Vo/Rl ; Is = Vs/Rs; Iabc = Vabc/Rabc; Id = Vd/Rd DEV_H_L MMBT3906 U403A
R448
=> Vo/Vs = 2*Rl*Rd*Vabc/(Rs*Rabc*Vd) = Vabc*0.11 2 3
10k
=> +10dBm peak voltage is transformed to 1.57V(max) to 6.15mV(min) (8 bit DAC, 4V reference)
C417 R406 10K LINE_INP
DG411 DG411
100nF 10K R425 R452
2 3
LINE2_GAIN 10k HIGH_GAIN
11
22K R428
GND U404A
1
R402 R450
8
LINE_IN2 3 VCC 22K
LINE_IN2 U403B
1
D U402A FLAT2 D
22K U402C 120K R449
2 A 5 7 -2.5V 7 6 +2.5V
C423 U405B
R420 R457 U405A 5k6
4 8 6 C402 (NPO) DG411 DG411
LM13700 120K LM224
7 7 6 3 R442
10K R434
1uF 5 3n3F 1
6
R414 R415 R423 4K7
C418 LM224 U404B 2
560R 560R 10K R431 4K7 R447
100nF R418
R439 R464
8
R461 5k6 D402
270K 4K7 R458 47K
120K
R410 270K BAV99
GND -10V GND -10V U407A
47K 4K7 R427
GND 2 C428 U407B
47K R465
GND 1 6 U407C
R443
3 7 10 LM224
100K
LM224 1uF 5 8 AUDIO_OUT
R435 4K7 AUDIO_OUT
+10V -10V 9
R407
PRE_EMPH2 -10V 1K R437 LM224 R438
LINE1_GAIN 47K 47K D401
10K R456
16
U402B 47K
R403 R463
LINE_IN1 14 VCC
LINE_IN1
DG411 GND BAV99 R445
22K 120K R426 47K
15 12 10 15 14 -10V -10V
B
C425 U405C 22K GND R444
R422 R462
13 LM13700 9 9 U404D 4K7
120K 8
U402D 10K
16
R416 1uF 10 R429 +5V +10V +10V -10V
R417 U405D
560R FLAT1 22K
560R LM224 LM224
R424 12 C405 -2.5V +5V +10V
R409
12
13
C R460 C
C403 (NPO)
4
GND 10K DG411 14 C409 C410
120K
10 11 13 100nF
12
13
4K7 100nF 100nF C411 C412
GND 3n3F
V+
V+
GND VL
R440 GND
+10dBm max input => |Vin| < 3.46V R432 R459
-10V GND U404C 4K7 GND GND U400E 100nF 100nF
V+
GND VL
For peak distortion of 0.3%
V-
V-
max input to transimpedance 270K 4K7 LM224
R430 U403E GND GND
amplifier is 100mV => need 25dB attenuation R411 47K DG411
V-
NB: Is max (3.46/18) is less than Id/2 (0.5ma) 47K GND U404E
11
5
4
DG411
+5V C415 C406
4
R404
PRE_EMPH1 -10V GND -10V
D400 -10V +5D1 -10V 100nF 100nF C416
BAV99 56K 100nF
GND
C400 (NPO) GND GND -10V
R400 R401 R467
13 U400D C407 C404 DG411
uPHONE_IN 3n3F R436 4K7
14 15 14 GND
+
330R 270R D403

33uF 12 100nF LM224
C401 R451 4K7 R453
LM224 U403D PWR_CNTRL_HIGH 12
47K R433 BAV99
EN_uPHONE 14
10K U407D PWRCNTRL
16
10nF 13
270K
GND +2.5V C426 +10V C413
GND
-10V
R413
4
GND 100nF 100nF GND
PWR_CNTRL_HIGH
PWR_CNTRL_HIGH R455 R408 1K
V+
V+
U405E U407E 5K6
B 10K B
LM224 LM224
Vref
V-
V-
C408 GND
R419 R421 C427 C414 LM224
11
11
100nF 22K 22K R405
5
7
5K6 U302B LCD_BIAS
+5V GND GND 100nF -10V 100nF GND 6
C419
R454 R466
6 Q401
100nF 7 PWR_CNTRL_RAW
U400B MMBT3906
+5V 5 R412 10K 2K2
16
GND LINE1_GAIN LCD_BIAS_RAW 10K

U401 C422 LM224
13 9
VCC
13
G Dout
3
LINEINP_DEN 12 7 PRE_EMPH2 100nF

LINEINP_DEN RCK Q7 U406
6 FLAT2 +5V
Q6
RESET 10 5 PRE_EMPH1 GND
VCC
Vref
RESET SRCLR Q5 LM224

SCLK 11 4 FLAT1 5 9
SCLK SRCK Q4 PDE Q400
3 TEST_DEV 2 8 MMBT3906
Q3 OUTA U400C
2 HIGH_GAIN 7 1 10
Q2 CLR OUTB
MOSI 14 1 AUDIO_DEV_U/D 6 16 LINE2_GAIN
GND
MOSI Din Q1 AUDIO_DEV_U/D LDAC OUTC

15 AUDIO_DEV_INC 15
Q0 AUDIO_DEV_INC OUTD
9
CS
10 8
74HC595A SCLK Dout
DGND
AGND
11 4
8
Din UPO
A A
GND
MAX534
MOSI Title Line Input Processing Section
12
14
SCLK
RESET EN_uPHONE
LINEINP_ADSEL
LINEINP_ADSEL
GND
Hornsby, NSW 2077
File: C:\Program Files\Design Explorer 99 SE\rft\t50\t50.Ddb - lineinp.sch
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
TERM_EN2
+5V
D307
TERM_EN1 BAT54C
R317
uPHONE_IN 1K R324
LINE_LEVEL_SENSE
AUDIO_XFRMR LINE_IN2 1k
Line Input Processing Section + C304 D305
R312
F300 R300 TP300
D T300 lineinp.sch 22K D
L2+ 3u3F BAV99
120mA 27R
U301B
D300 uPHONE_IN
1.5KE11CA 7 6
* GND
R301 C300 LINE_IN2
DG411 LINE_INP
L2- LINE_INP
27R 22uF LINE_IN1
8
GND TERM_EN2 R309 PWRCNTRL
PWRCNTRL PWRCNTRL
560R
LCD_BIAS
RESET LCD_BIAS LCD_BIAS
LINE_IN1
AUDIO_XFRMR GND
F301 R302 TP301 PWR_CNTRL_HIGH
T301
L1-
120mA 27R DEV_H_L
U301C AUDIO_DEV_INC
AUDIO_DEV_INC
10 11 AUDIO_DEV_U/D
AUDIO_DEV_U/D
R303 LINEINP_ADSEL
DG411
L1+ R310 LINEINP_DEN
27R SCLK
9
GND TERM_EN1 560R
MOSI AUDIO_OUT
1.5KE11CA C312
D301
12V TP302
* R306 1uF
C301 GND
2
3
5
22uF
10R
AUDIO_OUT
D306 R313
RL300 22K
C SM4004 R315 R318 R319 R320 C
MR62-12
1
22K 120K 120K 120K

R304 R305 Q300
GND BSS138 TP305
U302A
330R 330R 2 U302D MOD_OUT
R321 R322 R323 U302C
1 12
R332
3 14 10 LM224
R311 68K C302 68K C305 68K C306
GND LM224 13 68K 8 MOD_OUT
MOD_OUT
22K 9
R307 R325
LOOP/VOLTS_SEL R316 2n2F (NPO) 10nF (NPO) 120pF (NPO) LM224
LOOP/VOLTS_SEL 47K
10K
4K7 R336
GND +5D3 R314 GND GND
10K 22K
D303 -10V R327
U300 R335
BAV99 R308 GND R326 47K
22K
1 6 2K2 47K
A B
D304 2 5 LOOP_DET +2.5V
K C LOOP_DET
+2.5V -10V
3 4 MMBT3906 -10V
BAV99 NC E
TONE_OUT
6
R328
4N32 AUDIO_DEV_INC Q301 U303
GND
VDD
10K R333
TONE GENERATION SECTION 2
tonetx.sch TP303
RESET R330 1K R334
5
47K INC NF
4
PWR_CNTRL_HIGH U/D
TONE_OUT 1
GND
B B
DEV_H_L
-2.5V GND
LINEINP_ADSEL TONE_OUT MAX5161L
3
LINEINP_DSEL
+2.5V
FILTER_OFF FILTER_OFF MMBT3906
-2.5V
R329
AUDIO_DEV_U/D
CTCSS_SEL CTCSS_SEL Q302
SCLK SCLK 10K
MOSI MOSI
F302 R331
TONE+ TONEP+
TONE_INT TONE_INT 47K
120mA
1.5KE11CA D302
-2.5V
TONE- TONEP-
+10V +5V +10V
EXT_TONE_SEL EXT_TONE_SEL
12
13
TONE_DEV_U/D TONE_DEV_U/D C310
4
C307 C309
TONE_DEV_INC TONE_DEV_INC
100nF 100nF 100nF
V+
V+
GND VL
U302E GND GND GND

* C300, and C301 are Bipolar electrolytic capacitors LM224
V-
V-
A A
U301E
DG411
11
Title Audio Processing Section

-10V C308 GND
-10V C311 Size: A3 Number: 9154 Revision: B
100nF
100nF Hornsby, NSW 2077
GND
GND
File: C:\Program Files\Design Explorer 99 SE\rft\t50\t50.Ddb - audio.sch
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
+10V
Q707 +10V
R703 R716 MMBT3904
120R C748
47R
10nF C724 R717
+10V C736 L714
R718 R730 R738 10nF C754 10K
GND 330nH +
C722 220R 100nF C723
120R C721 220R 100nF 3u3F
100nF GND
L706
D 100nF C772 GND D
330nH
GND C750
L708 100nF C737 L712
GND
4
330nH MOD_PLL_IN
C702 U705 C708 Q704 220nH
R733 10nF
3 1 GND C732 22pF D701
MOD_VCO_OUT MMBFJ309 L716 D702 C718
4
10nF 330R 5p6F C739 12n5H MMBV109 NF
22pF +10V U702 C704
MSA0611 R701 R740 R737
2
3 1 D700 A04T 100nF
L726
BAT17 R709 Vref
47R 120R 1K 10nF 82nH
GND C770 C709 22pF 10K C762 GND
MSA0611 C733
2
C715
100nF GND 22pF 12pF 10nF
100nF R722
4
L709
GND GND 22K
L724
GND 330nH 3 1 GND GND
330nH
C705 U701
MSA0311 R744
2
+5Q
22pF C719
R711 10K
5
GND Q701 C760 C752
R734 100K
BSS138 100nF U707
MOD_VCO_EN
C743 1uF 1uF 4
4K7 C745
+10V GND Q700 1
R706 R700 10nF
Q706 GND 3 BALANCE
R735 R729 R725 BALANCE
BSS138 100nF -5V
220R 120R MMBT3906
22K 22K TS971LT
R710 10R
C700
2
T/R_RELAY C713 L700 L701 L702
2K2 100nF 27nH 39nH 27nH GND GND -5V
C L725 C
C749 100nF C734 GND +10V
3u3H C726 C727 C728
+10V VCC
10nF 3p9F 15pF 15pF R707 R704 100nF C776
3p9F
MX700 220R 120R 7
R723
GND GND MIXER C771 C703 100nF
4
C774
C714 U700 C763 6 GND 8
L722 L721 L720 LO 100nF 100nF 10K
3 1 2 GND
11
VCO_OUT IF U704C U704A
220nH 270nH 220nH 3
1
RF L710 R727
150pF 10nF GND R715 3
GND
GND
GND
330nH LM13700 2PORT_MOD

2
C765 MSA0611 10K
4
C755 C757 C758 C759 U706 22K
C707 C716 5 A 2
56pF L703 L704 L705 R742
3 1
47pF 120pF 120pF 47pF 27nH 47nH 27nH 4
5
4
1
820R 22pF R720

22pF -10V 100K
2
C717 C731 C729 C735 R724 R714 C756
6
GND 56R 56R MSA0611
R731 R743
3p9F 15pF 15pF 3p9F 10pF C775
560R 560R
100nF
GND GND R736 Q702 +10V
1K R726 MMBT3904 GND -10V GND
-10V
47R
+10V C730
R702 U704B C720 R719
16
LM13700 14 10nF L715

120R C706 10nF C753 10K
R705 R745 330nH +
12 15 GND 3u3F
220R B 220R
100nF 100nF C712
B B
13
C710 GND
C751
C738
100nF L711 L717
CHAN_PLL_IN
330nH GND Q705 100nH
GND GND C740 10nF 33pF D704 D705
MMBFJ309 L719
4
4p7F C747 L707 NF

C701 U703 C761 18n5H
R741 D703 R739 NF MMBV109
3 1
CHAN_VCO_OUT BAT17 10nF A05T C725
4K7 C741
10nF 22pF C711 C773
MSA0611 R713
C764 NF 10K
2
100K 100nF
1uF
10nF
6p8F GND GND
L723
330nH
GND -5V GND
GND
C742
Q703
R708 10nF
CHAN_VCO_EN BSS138
CHAN_VCO_EN
4K7 C746 GND
R732
10nF
22K
M1
A GND A
RFSCREEN1
Title Voltage Controlled Oscillators
GND
Hornsby, NSW 2077
File: C:\Program Files\Design Explorer 99 SE\rft\t50\t50.Ddb - vco.sch
1 2 3 4 5 6 7 8

Manual T50

Diunggah oleh

Informasi Dokumen

Deskripsi Asli:

Judul Asli

Hak Cipta

Format Tersedia

Bagikan dokumen Ini

Bagikan atau Tanam Dokumen

Opsi Berbagi

Apakah menurut Anda dokumen ini bermanfaat?

Apakah konten ini tidak pantas?

Hak Cipta:

Format Tersedia

Manual T50

Diunggah oleh

Hak Cipta:

Format Tersedia

Eclipse Ser ies

This manual is produced by RF Technology Pty Ltd

7.3 Front Panel Controls, Indicators and Test Points 29

B T50 Parts List (Rev. 4) 34

1 Oper ating Instr uctions

1.1 Fr ont Panel Contr ols and Indicator s

2.1 Ser ial I/O Par ameter s

2.3 Exciter Low Batter y Level

2.4 Exter nal PA Par ameter s

2.5 Gener ate LOOP

2.6 Exter nal TONE Input

2.7 Exter nal Tone High Pass Filter Bypass

2.8 Tr ansmit Time

2.9 Channel Select Over r ide

2.10 CWID Star t Delay

2.11 CWID Per iod

2.12 CWID Message

2.13 Channel Selectable Par ameter s

3 Tr ansmitter I/O Connections

3.1 25 Pin Connector

3.2 9 Pin Fr ont Panel Connector

Function Pins Specification Pin name on IBM PC

Table 4: Pin connections for the front panel 9 pin D connector.

4 Channel Pr ogr amming and Option Selection

5.1 T50 Master Schematic (Sheet 1)

5.2 Micr opr ocessor (Sheet 2)

5.3 Audio Pr ocessing Section (Sheet 3)

5.4 Line Input Pr ocessing Section (Sheet 4)

Table 9: Power Control Ranges.

5.5 Tone Gener ation Section (Sheet 5)

5.6 Fr equency Synthesiser (Sheet 6)

5.7 Voltage Contr olled Oscillator s (Sheet 7)

5.9 Power Generation Section (Sheet 9)

6.1 Standar d Test Equipment

6.2 Invoking the Calibration Pr ocedur e Manually

Connect an external reference input or the clock output

Attach the Power Amplifier to the Exciter,

7.1 Over all Descr iption

7.2 Physical Configur ation

7.3 Fr ont Panel Contr ols, Indicator s, and Test Points

7.4 Electr ical Specifications

7.4.3 Frequency Synthesizer Step Size

Ref Descr iption Par t #

VCA: Voltage Controlled Amplifier

High Speed Coupler Channel PLL

D10 R20 PA_CS

Size: A3 Number: 05/9160 R7 Revision: 1

D C509 +5TONE L500 +5V D

R527 C514 C515 LM224

+10V R533 R511

Title Tone Generation Section

Size: A3 Number: 9154 Revision: B

GND 5 100nF GND

Divide by 128 GND GND

470uF MBRM140T3 L905 2 1 2 1 2 1

100nF R924 100nF R936 GND

U909 Output Current is 750mA (max)

EN Vout +5V GND

Title Power Generation Section

Size: A3 Number: 9154 Revision: B

R813 L800 L801 R819

C804 C820 C814 C813 C819 C809