Service Guide
Disclaimer
Acer Incorporated makes no representations or warranties, either expressed or implied, with respect to the
contents hereof and specifically disclaims any warranties of merchantability or fitness for any particular
purpose. Any Acer Incorporated software described in this manual is sold or licensed "as is". Should the
programs prove defective following their purchase, the buyer (and not Acer Incorporated, its distributor, or
its dealer) assumes the entire cost of all necessary servicing, repair, and any incidental or consequential
damages resulting from any defect in the software. Further, Acer Incorporated reserves the right to revise
this publication and make changes from time to time in the contents hereof without obligation of Acer
Incorporated to notify any person of such revision or changes.
Other brands and product names are trademarks and/or registered trademarks of their respective holders.
ii
About this Manual
Purpose
This service guide contains reference information for the Extensa 610 notebook computer. It gives the
system and peripheral specifications, shows how to identify and solve system problems and explains the
procedure for removing and replacing system components. It also gives information for ordering spare
parts.
Manual Structure
This service guide consists of four chapters and seven appendices as follows:
Appendix D Schematics
This appendix contains the schematic diagrams of the notebook.
iii
Appendix E BIOS POST Checkpoints
This appendix lists all the BIOS POST checkpoints.
Appendix G Forms
This appendix contains standard forms that can help improve customer service.
iv
Conventions
The following are the conventions used in this manual:
NOTE
Gives bits and pieces of additional information related to the
current topic.
WARNING
Alerts you to any damage that might result from doing or not
doing specific actions.
CAUTION
Gives precautionary measures to avoid possible hardware or
software problems.
IMPORTANT
Reminds you to do specific actions relevant to the accomplishment
of procedures.
TIP
Tells how to accomplish a procedure with minimum steps through
little shortcuts.
v
vi
Table of Contents
vii
1.4.17 Keyboard........................................................................................................1-23
1.4.17.1 Windows 95 Keys ........................................................................1-23
1.4.18 FDD ...............................................................................................................1-24
1.4.19 HDD...............................................................................................................1-24
1.4.20 CD-ROM........................................................................................................1-25
1.4.21 Battery............................................................................................................1-25
1.4.22 Charger ..........................................................................................................1-26
1.4.23 DC-DC Converter...........................................................................................1-27
1.4.24 DC-AC Inverter..............................................................................................1-27
1.4.25 LCD ...............................................................................................................1-28
1.4.26 AC Adapter ....................................................................................................1-29
viii
2.4 ALI M7101 (Power Management Unit) .......................................................................... 2-24
2.4.1 Features ......................................................................................................... 2-24
2.4.2 Pin Diagram................................................................................................... 2-25
2.4.3 Pin Description .............................................................................................. 2-26
2.4.4 Different Pin definition setting ....................................................................... 2-34
2.4.5 Numerical Pin List ......................................................................................... 2-36
2.4.6 Alphabetical Pin List...................................................................................... 2-37
2.4.7 Function Description...................................................................................... 2-38
2.5 C&T 65550 High Performance Flat Panel/CRT VGA Controller.................................... 2-40
2.5.1 Features ......................................................................................................... 2-40
2.5.2 Block Diagram............................................................................................... 2-41
2.5.3 Pin Diagram................................................................................................... 2-42
2.5.4 Pin Descriptions............................................................................................. 2-43
ix
2.9.5 Pin Diagram ...................................................................................................2-94
2.9.6 Pin Description...............................................................................................2-95
2.9.7 Functions Description.....................................................................................2-96
2.9.7.1 Charge Function ..........................................................................2-96
2.9.7.2 Discharge Function......................................................................2-96
2.9.7.3 Safety Concerns...........................................................................2-97
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3.4 System Security................................................................................................................ 3-6
3.4.1 Floppy Disk Drive Control ............................................................................... 3-6
3.4.2 Hard Disk Drive Control .................................................................................. 3-6
3.4.3 System Boot Drive Control............................................................................... 3-7
3.4.4 CD-ROM Bootable........................................................................................... 3-7
3.4.5 Serial Port 1 Base Address ............................................................................... 3-8
3.4.6 Parallel Port Base Address ............................................................................... 3-8
3.4.7 Parallel Port Operation Mode ........................................................................... 3-8
3.4.8 Passwords ........................................................................................................ 3-9
3.4.9 CardBus Support............................................................................................ 3-10
xi
4.5 Disassembling the Inside Frame Assembly .....................................................................4-10
4.5.1 Removing the Heat Sink Assembly .................................................................4-10
4.5.2 Removing the Internal Drive ..........................................................................4-11
4.5.3 Replacing the CPU .........................................................................................4-12
4.5.4 Removing the Display ....................................................................................4-13
4.5.5 Detaching the Top Cover................................................................................4-14
4.5.6 Removing the Base Assembly .........................................................................4-16
4.5.7 Removing the Motherboard ............................................................................4-17
4.5.8 Disassembling the Motherboard......................................................................4-20
4.5.9 Removing the Touchpad.................................................................................4-21
Appendix D Schematics
Appendix G Forms
xii
List of Figures
1-1 Notebook.......................................................................................................................... 1-1
xiii
2-14 PCI-to-CardBus terminal assignments ............................................................................2-62
xiv
4-20 Removing the Battery Connector Board.......................................................................... 4-18
4-21 Unplugging the LCD Cover Switch and Speaker Cables................................................. 4-18
4-23 Detaching the Motherboard from the Inside Assembly Frame......................................... 4-19
4-33 Removing the DC-AC Inverter and LCD ID Inverter Boards.......................................... 4-25
xv
List of Tables
1-1 Port Descriptions .............................................................................................................1-3
xvi
1-28 CD-ROM Specifications................................................................................................. 1-25
xvii
2-14 NS87336VJG Pin Descriptions .......................................................................................2-79
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C h a p t e r 1
System Introduction
This chapter introduces the notebook, its features, components and specifications.
1.1 Overview
The notebook was designed with the user in mind. The figure below shows the notebook with the display
open.
• PCI local bus video with graphics acceleration and 1MB video RAM boost video performance
• Power management system with standby and hibernation power saving modes
Multimedia
• Full-sized keyboard
• PC card (formerly PCMCIA) slots (two type II/I or one type III) with ZV (Zoomed Video) port support
1 Some areas or regions may not offer models with a built-in CD-ROM drive.
CD-ROM model Internal 15mm, 5.25-inch high-speed External 3.5-inch, 1.44MB diskette drive
CD-ROM drive
One 3.5mm minijack line-in port Audio CD player or other line-in devices
CN11
CN6
CN12
CN13
CN14
CN15 CN17
CN16
SW3 CN18 S1
SW2 CN19
Switch ON OFF
1 Keyboard Type (Default OFF) - -
2 Keyboard Type 88-key (Japan keyboard) 84/85-key (U.S. keyboard)
3 Password Bypass Check
4 Generic boot-up screen show on screen in No Yes
POST
A PCMCIA card can use IRQ 3, 4, 5, 7, 9 and 11 as long as it does not conflict with the
interrupt address of any other device.
Item Description
GPIOA2 Smart inverter contrast counter control
GPIOA3 0: Normal operation of system
1: Shutdown system
GPIOA4 Serial data on X24C02
GPIOA5 Battery gauge communication control
GPIOA6 Battery data line
GPIOA7 Thermal sensor data line
GPIOC6 VGA thermal sensor data line
GPIOC7 0: VGA chip standby mode
1: Normal operation
Register E0h bit 8 Serial clock on X24C02
Register E0h bit 9 0: Disable 12V for flash ROM
1: Enable 12V for flash ROM
Register E0h bit 10 0: 3 mode FDD
1: Normal
Register E0h bit 11 Thermal sensor clock line
Register E0h bit 12 Thermal sensor reset
Register E0h bit 13 0: Enable battery LED
1: Disable battery LED
Register E0h bit 14 0: Disable audio amplifier
1: Enable audio amplifier
Register E1h bit 0 0: NiMH battery
1: Li-ion battery
Register E1h bit 1 CPU thermal high
1.4.6 Processor
Table 1-12 Processor Specifications
Item Specification
CPU type P54CSLM-120,P54CSLM-133, P54CSLM-150, P55CLM-133,
P55CLM - 150
CPU package SPGA
Switchable processor speed (Y/N) Yes
Minimum working speed 0MHz while hibernation mode
CPU voltage 3.1V/2.9V/2.45V
1.4.7 BIOS
Table 1-13 BIOS Specifications
• Expansion RAM module type:144-pin, 64-bit, small outline Dual Inline Memory Module (soDIMM)
• EDO and fast-page mode DIMMs may be used together in a memory configuration.
Item Specification
DRAM or VRAM DRAM(EDO type)
Fixed or upgradeable Fixed
Memory size/configuration 1MB (256K x 16 x 2pcs)
Memory speed 60ns
Memory voltage 3.3V
Memory package TSOP
1.4.11 Video
Table 1-16 Video Hardware Specification
Item Specification
Video chip C&T65550B
Working voltage C&T65550B: 3.3V
C&T65550XX: 3.3V/5V (“XX” represents codes other than “A” (i.e. “B1”))
Video Chip substitutability Yes
During power-on, system supplies 5V to video chip and read its register to determine
whether the video chip is 5V or 3.3V/5V type. If 5V video chip is detected, system
maintains video voltage at 5V; if 3.3V/5V video chip is detected, system switches
video voltage to 3.3V.
Resolution x Color on LCD Only TFT LCD (SVGA) STN LCD (SVGA)
640x480x16 Y Y
640x480x256 Y Y
640x480x65,536 Y Y
640x480x16,777,216 Y -
800x600x16 Y Y
800x600x256 Y Y
800x600x65,536 Y -
1024x768x16 Y Y
1024x768x256 Y Y
Using software, you can set the LCD to a higher resolution than its physical resolution, but
the image shown on the LCD will pan.
Item Specification
Number of parallel ports 1
ECP/EPP support Yes (set by BIOS setup)
Connector type 25-pin D-type
Location Rear side
Selectable parallel port (by BIOS Setup) • Parallel 1 (3BCh, IRQ7)
• Parallel 2 (378h, IRQ7)
• Parallel 3 (278h, IRQ5)
• Disable
Item Specification
Number of serial ports 1
16550 UART support Yes
Connector type 9-pin D-type
Location Rear side
Selectable serial port (by BIOS Setup) • Serial 1 (3F8h, IRQ4)
• Serial 2 (2F8h, IRQ3)
• Disable
Item Specification
Chipset YMF715
Audio onboard or optional Built-in
Mono or stereo Stereo
Resolution 16-bit
Compatibility SB-16 , Windows Sound System
Mixed sound sources Voice, Synthesizer, Line-in, Microphone, CD
Voice channel 8-/16-bit, mono/stereo
Sampling rate 44.1 kHz
Internal microphone No
Internal speaker / quantity Yes / 2 pcs.
Microphone jack Yes
Headphone jack Yes
1.4.15 PCMCIA
PCMCIA is an acronym for Personal Computer Memory Card International Association. The PCMCIA
committee set out to standardize a way to add credit-card size peripheral devices to a wide range of personal
computers with as little effort as possible.
There are two type II/I or one type III PC Card slots found on the left panel of the notebook. These slots
accept credit-card-sized cards that enhances the usability and expandability of the notebook.
ZV (Zoomed Video) port support allows your system to support hardware MPEG in the form of a ZV PC
card.
Table 1-22 PCMCIA Specifications
Item Specification
Chipset TI 1131
Supported card type Type-II / Type-III
Number of slots Two Type-II or one Type-III
Access location Left side
ZV (Zoomed Video) port support Yes (only in lower slot)
Item Specification
Vendor & model name Synaptics TM1002MPU
Power supply voltage (V) 5 ± 10%
Location Palm-rest center
Internal & external pointing device work simultaneously Yes
Support external pointing device hot plug Yes
X/Y position resolution (points/mm) 20
Interface PS/2 (compatible with Microsoft mouse driver)
1.4.17 Keyboard
Table 1-24 Keyboard Specifications
Item Specification
Vendor & model name SMK KAS1901-0161R (English)
Total number of keypads 84/85 keys
Windows 95 keys Yes, (Logo key / Application key):
Internal & external keyboard work simultaneously Yes
Key Description
Windows logo key Start button. Combinations with this key performs special functions. Below are a few
examples:
• Windows + Tab Activate next Taskbar button
• Windows + E Explore My Computer
• Windows + F Find Document
• Windows + M Minimize All
• Shift + Windows + M Undo Minimize All
• Windows + R Display Run dialog box
Application key Opens the application’s context menu (same as right-click).
Item Specification
Vendor & model name Mitsumi D353F2
Floppy Disk Specifications
Media recognition 2DD (720K) 2HD (1.2M, 3-mode) 2HD (1.44M)
Sectors / track 9 15 18
Tracks 80 80 80
Data transfer rate (Kbits/s) 250 300 500 500
Rotational speed (RPM) 300 360 360 300
Read/write heads 2
Encoding method MFM
Power Requirement
Input Voltage (V) +5 ± 10%
1.4.19 HDD
Table 1-27 HDD Specifications
Item Specification
Vendor & Model Name IBM DMCA21080 IBM DMCA21440 IBM DTNA22160 Toshiba
MK1002MAV
Drive Format
Capacity (MB) 1080 1440 2160 1085
Bytes per sector 512 512 512 512
Logical heads 16 16 16 16
Logical sectors 63 63 63 63
Logical cylinders 2100 2800 4200 2100
Physical read/write heads 3 4 6 6
Disks 2 2 3 3
Spindle speed (RPM) 4009 4009 4000 4635
Performance Specifications
Buffer size (KB) 128 96 96 128
Interface ATA-3 ATA-3 ATA-3 ATA-3
Data transfer rate 39.5 ~ 61.8 39.5 ~ 61.8 39.1~ 61.6 29.3 ~ 55.5
(disk-buffer, Mbytes/s)
1.4.20 CD-ROM
Table 1-28 CD-ROM Specifications
Item Specification
Vendor & Model Name Panasonic UJDCD8730
Performance Specification
Speed (KB/sec) 150 (normal speed)
1500 (10X speed)
Access time (ms) 170 (Typ.)
Buffer memory (KB) 128
Interface Enhanced IDE (ATAPI) compatible
Applicable disc format CD-DA, CD-ROM, CD-ROM XA (except ADPCM), CD-I,
Photo CD (Multisession), Video CD, CD+
Loading mechanism Drawer type, manual load/release
Power Requirement
Input Voltage (V) 5
1.4.21 Battery
Table 1-29 Battery Specifications
Item Specification
Battery gauge on screen Yes, by hotkey Yes, by hotkey Yes, by hotkey
Vendor & model name Sanyo BTP-W31 Sony BTP-T31 Toshiba BTP-X31
Battery type NiMH Li-Ion NiMH
Cell capacity (mAH) 3500 4050 3500
Cell voltage (V) 1.2 3.6 1.2
Number of battery cell 9-cell 9-Cell 9-Cell
Package configuration 9 serial 3 serial, 3 parallel 9 serial
Package voltage (V) 10.8 10.8 10.8
Package capacity (WAH) 37.8 40.5 37.8
• Rapid mode
The notebook uses rapid charging when power is turned off and a powered AC adapter is connected to
it. In rapid mode, a fully depleted battery gets fully charged in approximately two hours.
• Charge-in-use mode
When the notebook is in use with the AC adapter plugged in, the notebook also charges the battery
pack if installed. This mode will take longer to fully charge a battery than rapid mode. In charge-in-
use mode, a fully depleted battery gets fully charged in approximately six to eight hours.
• Trickle mode
When the battery is fully charged, the adapter changes to trickle mode to maintain the battery charge
level. This prevents the battery from draining while the notebook is in use.
Table 1-30 Charger Specifications
Item Specification
Vendor & model name Ambit T62.062.C.00
Input voltage (from adapter, V) 19 (min.)
20 (typ.),
20.5 (max.)
Battery Low Voltage
Battery Low 1 level (V) 10.7 (typ., for NiMH)
8.65 (typ., for LIB)
Battery Low 2 level (V) 10.35 (typ., for NiMH)
8.23 (typ., for LIB)
Battery Low 3 level (V) 9.22 (typ., for NiMH)
7.73 (typ., for LIB)
Charge Current
Fast charge (charge when system is still operative, A) 0.65 (typ.)
Quick charge (charge while system is not operative, A) 1.9 (typ.)
Charging Protection
Safety timer for Fast Charge mode while notebook is operating (minute) 576 (NiMH)
Safety timer for Quick Charge mode while notebook is not operating (minute) 192 (NiMH)
Maximum temperature protection (ºC) 60
Maximum voltage protection (V) 16.2V for NiMH
Over voltage protection 13V for Li-ion
Item Specification
Vendor & model name Ambit T62.066.C.00 / Ambit T62.064.C.00
Input voltage (V) 7.3 (min.) - 20 (max.)
Input current (mA) - 420 (typ.) 550 (max.)
Output voltage (Vrms, no load) 1000 (min.) - 1500 (max.)
Output voltage frequency (kHz) 25 (min.) 42 (typ.) 60 (max.)
Output current (mArms) 1.5~5.5 (min.) 2.0~6.0 (typ.) 2.5~6.5 (max.)
Item Specification
Vendor & model name HITACHI TORiSAN IBM GOLDSTAR
LMG9900ZWCC LM-FH53-22NAW ITSV45E LP121S1-J
Mechanical Specifications
LCD display area 11.3 11.3 11.3 12.1
(diagonal, inch)
Display technology STN STN TFT TFT
Resolution SVGA (800x600) VGA (800x600) SVGA (800x600) SVGA (800x600)
Supported colors -- -- 262,144 colors 262,144 colors
Optical Specification
Contrast ratio 30 (typ.) 30 (typ.) 100 (typ.) 100 (typ.)
2
Brightness (cd/m ) 70 (typ.) 70 (typ.) 70 (typ.) 70 (typ.)
Brightness control keyboard hotkey keyboard hotkey keyboard hotkey keyboard hotkey
Contrast control using keyboard using keyboard none none
hotkey hotkey
Electrical Specification
Supply voltage for LCD 3.3 or 5 (typ.) 3.3 (typ.) 3.3 3.3 (typ.), 3.63
display (max.)
Supply voltage for LCD 590 (typ.) 590 (typ.) 590 480
backlight (Vrms)
The LCD ID code can be set by using the LCD ID utilization utility
(370pw.exe/370pr.exe). Please refer to the software specification section for details.
Item Specification
Vendor & model name Delta ADP-45GB REV.E2
Input Requirements
Nominal voltages (Vrms) 90 - 264
Frequency variation range (Hz) 47 - 63
Maximum input current (A, @90Vac, full load) 1.5 A
Inrush current The maximum inrush current will be less than 50A and 100A
when the adapter is connected to 115Vac(60Hz) and
230Vac(50Hz) respectively.
Efficiency It should provide an efficiency of 83% minimum, when
measured at maximum load under 115V(60Hz)
Output Ratings (CV mode)
DC output voltage (V) +19
Noise + Ripple (mV) 300
Load (A) 0 (min.) 2.4 (max.)
Dynamic Output Characteristics
Turn-on delay time (s, @115Vac) 2
Hold up time (ms; @115 Vac input, full load) 5 (min.)
Over Voltage Protection (OVP, V) 26
Short circuit protection Output can be shorted without damage
Electrostatic discharge (ESD, kV) ±15 (at air discharge)
Dielectric Withstand Voltage
Primary to secondary 3000 Vac (or 4242 Vdc), 10 mA for 1 second
Leakage current 0.25 mA maximum @ 254 Vac, 60Hz.
Regulatory Requirements
Internal filter meets:
1. FCC class B requirements.
2. CISPR 22 Class B requirements.
1.5.1 BIOS
The BIOS is compliant to PCI v2.1, APM v1.2, E-IDE and PnP specification. It also defines the hotkey
functions and controls the system power-saving flow.
Press the scale hotkeys (Fn- →and Fn -←) to increase and decrease
the brightness or contrast level.
Contrast Control Notebooks with TFT displays do not show the brightness control
icon.
Fn-F3 Display Toggle Switches display from LCD to CRT to both LCD and CRT.
Fn-F4 Battery Gauge Displays the battery gauge.
Fn-F5 Volume Control Press the scale hotkeys (Fn-→ and Fn-←) to increase and decrease
the output level.
When the available hotkey is toggled, the system will issue a beep to enter the assigned
process.
1.5.1.2 MultiBoot
The system can boot from the FDD, External FDD, HDD, CD-ROM. The user can select the desired
booting process to boot the system. If the CD-ROM is bootable, the BIOS will override the other process to
boot the system directly.
STANDBY MODE
The notebook consumes very low power in standby mode. Data remain intact in the system memory until
battery is drained.
The necessary condition for the notebook to enter standby mode is that the reserved disk space size for
saving system and video memory is insufficient so the notebook is unable to enter hibernation mode. In this
situation, there are three ways to enter standby mode:
• Set a value for the System Standby/Hibernation Timer in Setup. If the waiting time specified by this
timer elapses without any system activity, the notebook goes into standby mode.
Condition Description
The condition to enter • “Hard Disk Drive” is [Disabled] in System Security of BIOS SETUP.
Standby Mode • “Hard Disk 0” is [None] in Basic System Configuration of BIOS SETUP.
• HDD has not located enough free contiguous disk space generated by Sleep Manager
and this free space is not corrupted.
• Standby/Hibernation Timer times-out or Standby/Hibernation HotKey pressed and
there is no activity within 1/2 second.
The condition of • Issue a beep.
Standby Mode • Flash standby LED with 1 Hz frequency.
• Disable the mouse, serial and the parallel port.
• The keyboard controller, HDD and VGA enter the standby mode.
• Stop the CPU internal clock.
• All the functions are disabled except the keyboard, battery low warning and modem
ring wake up from standby (if enabled).
The condition back to Any one of following activities will let system back to Normal Mode:
On Mode • Any keystroke (Internal KB or External KB)
• Modem ring.
HIBERNATION MODE
In hibernation mode (also known as zero-volt hibernation-to-disk mode), power shuts off. The notebook
saves all system information onto the hard disk before it enters hibernation mode. Once you turn on the
power, the notebook restores this information and resumes where you left off upon leaving hibernation
mode.
• Set a value for the System Standby/Hibernation Timer in Setup. If the waiting time specified by this
time elapses without any system activity, the system goes into hibernation mode
• Enable the Suspend upon Battery-low parameter in Setup. If a battery-low condition takes place, the
notebook enters hibernation mode in about five minutes.
When the PCMCIA I/O card is detected, the following warning pop-up message will be
displayed on the screen by the BIOS. The system will wait for the specified key to continue.
Warning!!
A PCMCIA card is detected!!
If you are using a fax/modem or LAN cards, please
disconnect with server or complete transmission before
entering standby/hibernation mode, otherwise :
1) File server will be shut down if LAN card is used.
2) Data will be lost if a modem card is used.
Press <F1> to enter standby/hibernation mode.
Press <F2> to cancel.
Condition Description
The condition to enter • “Hard Disk Drive” is not [Disabled] in System Security of BIOS SETUP.
Hibernation Mode
• “Hard Disk 0” is not [None] in Basic System Configuration of BIOS SETUP.
• HDD has already located enough free contiguous disk space generated by the
Sleep Manager and this free space is not corrupted.
• Standby/Hibernation Timer times-out or Standby/Hibernation Hotkey pressed and
there is no activity within 1/2 second.
The condition of • Except the RTC, 6375 (state machine), KB controller and power switch, all the
Hibernation Mode system components are off.
The condition back to On • Turn off then on the system.
Mode
Condition Description
The condition to enter • Pointing device is idle until Display Standby Timer times-out or LCD cover is
Display Standby Mode closed.
The condition of Display • All the system components are on except LCD backlight and CRT horizontal
Standby Mode frequency output (if CRT is connected)
The condition back to On • Any keystroke (Internal KB or External KB)
Mode
• Pointing device activity
The VGA BIOS should support DPMS (Desktop Power Management System) for the standby
and hibernation mode function call. When the Display Standby Timer expires, the system
BIOS will execute the DPMS service routines.
Condition Description
The condition to enter HDD Standby • Display Standby Timer times-out or LCD cover is closed.
Mode
The condition of HDD Standby Mode • All the system components are on except HDD spindle motor
The condition back to On Mode • Any access to HDD
BATTERY LOW
When the battery capacity is low and has no adapter plugged, the system will generate the following battery
low warning:
• If the AC adapter does not plug in within 3 minutes and the “Standby/Hibernation upon Battery-low”
in BIOS SETUP is enabled, the system will enter Standby/0-Volt Hibernation Mode. The battery low
warning will stop as soon as the AC adapter is plugged into the system.
1. If the original brightness is over 75% and the AC power is on-line, the BIOS will change the brightness
to 75% after the AC power is off-line.
2. If the original brightness is below 75%, the brightness maintains the same level even if the AC power is
off-line.
3. If the brightness is already changed by the hotkey under DC power, it will not be changed after the AC
power is plugged in.
4. If the brightness is not changed by the hotkey under DC power, the brightness will be changed back to
the old setting — the previous brightness parameter under AC power.
5. If the previous brightness parameter does not exist, the brightness will not be changed in process 4.
• Windows 952
2 In some areas, a different operating system may be pre-loaded instead of Windows 95.
3 The system utilities and application software list may vary.
Item Specification
Temperature
Operating (ºC) +5°C ~ +35°C
Non-operating(ºC) -20°C ~ +60°C
Humidity
Operating (non-condensing) 20% ~ 80%
Non-operating (non-condensing) 20% ~ 80%
Operating Vibration (unpacked)
Operating 5 - 25.6Hz, 0.38mm; 25.6 - 250Hz, 0.5G
Sweep rate > 1 minute / octave
Number of test cycles 2 / axis (X,Y,Z)
Non-operating Vibration (unpacked)
Non-operating 5 - 27.1Hz, 0.6G; 27.1 - 50Hz, 0.41mm; 50~500Hz, 2G
Sweep rate > 2 minutes / octave
Number of text cycles 4 / axis (X,Y,Z)
Shock
Non-operating (unpacked) 40G peak, 11±1ms, half-sine
Non-operating (packed) 50G peak, 11±1ms, half-sine
Altitude
Operating 10,000 feet
Non-operating 40,000 feet
ESD
Air discharge 8kV (no error)
12.5kV (no restart error)
15kV (no damage)
Contact discharge 4kV (no error)
6kV (no restart error)
8kV (no damage)
Item Specification
Weight (includes battery)
FDD model 2.6 kg. (5.7 lb.)
CD-ROM model 2.8 kg. (6.2 lb.)
Dimensions WxDxH
(main footprint) 306mm x 228mm x 46mm (12.05” x 8.98” x 1.81”)
The M1521 provides a complete integrated solution for the system controller and data path
components in a Pentium-based system. It provides 64-bit CPU bus interface, 32-bit PCI bus
interface, 64/72 DRAM data bus with ECC or parity, secondary cache interface including pipeline
burst SRAM or asynchronous SRAM, PCI master to DRAM interface, four PCI master arbiters, and
a UMA arbiter. The M1521 bus interfaces are designed to interface with 3V and 5V buses. It
directly connects to 3V CPU bus, 3V or 5V tag, 3V or 5V DRAM bus, and 5V PCI bus.
2.2.1 Features
• Supports all Intel/Cyrix/AMD 586-class processors (with host bus of 66 MHz, 60 MHz and
50 MHz at 3V)
• supports M1/K5/Dakota CPUs
• supports linear wrap mode for M1
586
CPU
CPU Bus
DRAM
SRAM M1521 UMA
BGA Graphic
controller
PCI Bus
IDE Master
M1523 USB connector
CD HDD
ISA Bus
TTL
SRAM MD
M1521 MA DRAM
CTLR
tag 8/11-bit 328-BGA
PCI
ISA
128K/256K
Flash XD - TTL
SWAP ECC
8 QWORD 72-bit
MUX MUX MD_OUT
SWAP
MUX
SWAP
PB_IN[63:0]
H/L DW swap
for 32-bit DRAM
6 DWORD
MUX PCI_OUT
HDIN[63:0]
HD_IN 64-bit 5 DWORD
PB_OUT[63:0]
P_IN[31:0]
6 DWORD PCI_IN
M1521
One eight-byte bidirectional line buffer is provided for ISA/DMA master memory read/writes. One
32-bit wide posted-write buffer is provided for PCI memory write cycles to the ISA bus. It also
supports a PCI to ISA IRQ routing table and level-to-edge trigger transfer.
The chip has two extra IRQ lines and one programmable chip select for motherboard Plug-and-
Play functions. The interrupt lines can be routed to any of the available ISA interrupts.
The on-chip IDE controller supports two IDE connectors for up to four IDE devices providing an
interface for IDE hard disks and CD-ROMs. The ATA bus pins are dedicated to improve the
performance of IDE master.
The M1523 supports the Super Green feature for Intel and Intel compatible CPUs. It implements
programmable hardware events, software event and external switches (for suspend/turbo/ring-in).
The M1523 provides CPU clock control (STPCLKJ). The STPCLKJ can be active (low) or inactive
(high) in turn by throttling control.
2.3.1 Features
• Technology
• 0.6µm, triple-metal CMOS process
• Buffers
• 8-byte bidirectional line buffers for DMA/ISA memory read/write cycles to PCI bus
• 32-bit posted-write buffer for PCI memory write and I/O data write (for sound card) to ISA
bus
• Interrupt controller
• Provides 14 interrupt channels
• Independently programmable level/edge triggered channels
• Counter/Timers
• Provides 8254 compatible timers for system timer, refresh request, speaker output use
• Keyboard controller
• Built-in PS2/AT keyboard controller
• The specific I/O is used to save the external TTL buffer
• PMU interface
• Supports CPU SMM mode, SMI feature
• Supports programmable stop clock throttle
• Supports the APM control
• Provides external suspend mode switch/turbo switch/ring-in switch
• Provides four system states for power saving (on, doze, standby, suspend)
• Provides three timers from 1 second to 300 minutes to individually monitor VGA, MODE,
IN status
• Supports RTC alarm wake up control
• IDE interface
• Built-in PCI IDE master controller
• Supports PIO modes up to mode 5 timings, and multiword DMA mode 0, 1, 2
• 8 x 32-bit pre-read and posted-write buffers
• Dedicated pins for ATA interface
2.4.1 Features
• Four operating states - ON, DOZE, SLEEP, APM
• Two output pins depending on operating state, each pin is programmable and power
configurable
• 24 General Purpose I/O pins. Each pin can be programmed to become input or output
• LCD control
75 GPIOC3
Vss 1 74 GPIOC2
AD23 2 73 GPIOC1
AD22 3 72 GPIOC0
AD21 4 71 GPIOA7
AD20 5 70 GPIOA6
AD19 6 69 GPIOA5
AD18
AD17
7
8
ALi 68
67
GPIOA4
GPIOA3
AD16 9 66 GPIOA2
CBEJ2 10 65 GPIOA1
VDD5 11
FRAMEJ 12 M7101 64
63
GPIOA0
Vss
IRDYJ 13 62 CLK32
TRDYJ 14 61 SEL1
DEVSELJ 15 60 SEL0
PAR 16 59 VDD5
CBEJ1 17 58 DISPLAY
SMIJ 18 57 CCFT
Vss 19 56 FPVEE
AD15 20 55 SPKCTL
AD14 21 54 SQWO
AD13 22 53 SLED
AD12 23 52 DRQ
AD11 24 51 CRT
AD10 25
GPIOA5 (69) O External General Purpose I/O B write. When SQWO is pull low
/GPIOWB 4.7K, the GPIOA5 will become GPIOWA. External General purpose
A R/W control pulse, When write index 0F0h with a byte or a word.
A 74373 latch pulse will be generated at this pin. The 74373 input
should be connected to PCI AD[23:16] if a byte command. If a word
command, two 74373s will be used and inputs are connected to PCI
AD[31:16]. The write action also will write into the internal register.
So when reading the offset, the value will be sent by M7101 to host.
GPIOA4 (68) O External General Purpose I/O B read. When SQWO is pull low
/GPIORBJ 4.7K, the GPIOA0 will become GPIORAJ. External General
purpose A Read control pulse. When Read index 0F1h with a byte
or a word, a 74245 OEJ pulse will be generated at this pin. The
74245 output should be connected to PCI AD[23:16] if a byte
command. If a word command, two 74245 will be used and4
outputs are connected to PCI AD[31:16]. When read index 0E1h,
M7101 will send DEVSELJ, TRDYJ but float the AD[31:0] because
the data will be sent by 74245. The write action has no meaning
and nothing will be done.
GPIOA3 (67) O Contrast2. When offset 0F6h D14=‘0’ and D9=‘1’, this pin will be
/CONTRAST2 /O the LCD contrast output 2. It is a 1Khz signal with programmable
duty cycle controlled by offset 0FBh D[15:13].
/SLOWDOW
N SLOWDOWN (default). When offset 0F6h D14=‘1’, this pin will be
the slow down clock control output pin.
GPIOA2 (66) O Contrast1. When offset 0F6h D14=’0’ and D8=’1’, this pin will be
/CONTRAST1 the LCD contrast output1. It is a 1 KHz signal with programmable
duty cycle controlled by offset 0FBh D[12:8].
GPIOA1 (65) O External General Purpose I/O A write. When SPKCTL is pull low
/GPIOWA 4.7K, the GPIOA1 will become GPIOWA. External General purpose
A R/W control pulse, When write index 0E0h with a byte or a word.
A 74373 latch pulse will be generated at this pin, The 74373 input
should be connected to PCI AD[23:16] if a byte command. If a word
command , two 74373s will be used and inputs are connected to
PCI AD[31:16]. The write action also will write into the internal
register. So when reading the offset, the value will be sent by
M7101 to host.
GPIOB2 (83) I INIT Input. When DISPLAY is pulled low, this pin will be INIT input.
/IN_INIT
GPIOB1 (82) I SMIJ Input. When DISPLAY is pulled low, this pin will be SMIJ
/IN_SMIJ input.
GPIOB0 (81) I SMIJ Input. When DISPLAY is pulled low, this pin will be INTR
/IN_INTR input.
• When SLED default is pulled high, the chip will be in normal mode.
• When SLED is pulled low by 4.7K resistor, the chip will be in test mode.
• When GPIOC2 pull low, the PCI ports are 0078/007A and offset 0F6h D15 will be set, otherwise,
0178/017A.
Original D6=1 D7=1 D8=1 D9=1 D10=1 D11=1 D12=1 D13=1 D14=1
pin
definition
GPIOA7 POSSTA
GPIOA6 SPEKIN
GPIOA3 CONTRAST2 SLOWDN
GPIOA2 CONTRAST1
GPIOB7 STPCLKJ
GPIOB3 BRDYJ
GPIOC7 VCSJ
GPIOC6 SETUP
GPIOC5 EXTSW
GPIOC4 EJECYJ
GPIOC3 DOCKJ
• Pull high : GPIOA0, GPIOA4, GPIOB1, GPIOB3, GPIOB6, GPIOB7, GPIOC1, GPIOC2,
GPIOC5, GPIOC6, GPIOC7.
PCI interface
The PCI interface is running at PCICLK frequency. From the point of PCI bus, M7101 is a hidden
component. There are no PCI configuration spaces built in. So using PCI configuration read/write
method cannot detect the existence of M7101.
M7101 just decodes the I/O 0178h/017Ah or 0078h/007Ah address. When it detects the address,
it will assert the DEVSELJ signal and TRDYJ when data is ready. M7101 is only a PCI slave
device, no REQJ and GNTJ signal required. All the PCI interface timing can meet the
requirements of PCI spec. V2.1.
M7101 will monitor the PCI bus behavior to detect the Device access like HDD, SIO, PIO, VGA
memory range, Floppy, KBC and IO&MEM group. It will decode these addresses but not assert
DEVSELJ. The interface is static design. So the input PCICLK can be changed from 33 MHz to 0
Hz without glitch.
There is a Lock register at offset 0D1h. When set D5 to 1 will unlock I/O port 017Ah/007Ah. Host
can read or write I/O port 017Ah/007Ah. When set D5 to 0, then Host cannot I/O read/write I/O
port 017Ah/007Ah except the offset 0D1h. No matter lock or unlock, when access to I/O port
017Ah, DEVSELJ will always be active.
FRAMEJ='1'
FRAMEJ='0'
OVER_S
IRDYJ='1' START_S
IRDYJ='0'
HITCMD
HITCMD3
1 HITCMD2
2.5.1 Features
HIGH PERFORMANCE
Based on a totally new internal architecture, the C&T65550, integrates a powerful 64-bit graphics
accelerator engine for Bit Block Transfer (BitBLT), hardware cursor, and other functions intensively
used in graphical User Interfaces (GUls) such as Microsoft Windows. Superior performance is
also achieved through a direct 32-bit interface to the PCI Local Bus. The C&T65550 offers
exceptional performance when combined with CHIPS advanced linear acceleration driver
technology .
The C&T65550 implements independent multimedia capture (and display systems on-chip. The
capture system places data in display memory (usually off screen) and the display system places it
in a window on the screen.
The capture system can receive data from either the system bus or from the ZV enabled video
port in either RGB or YUV format. The input data can also scaled down before storage in display
memory (c.g., from any size larger than 320x240 down to 352x248). Capture of input data may
also be double buffered for smoothing and to prevent image tearing.
The display system can independently place either RGB or YUV data from any where in display
memory into an on-screen window which can be any size and located at any pixel boundary (YUV
data is converted to RGB "on-the-fly" on out put). Non-rectangular windows .are supported via
color keying. The data can be functionally zoomed on output up to 8x to fit the onscreen window
and can be horizontally and vertically inter polated to scale or zoom artifacts. Interlaced and non-
interlaced data are supported in both capture and display systems.
The C&T65550 supports a wide variety of monochrome and color Single-Panel, Single-Drive (SS)
and Dual-Panel, Dual Drive (DD) standard and high-resolution passive STN and active matrix
TFT/MIM LCD, and EL panels. For monochrome panels, up to 64 gray scales are supported. Up to
4096 different colors can be displayed on passive STN LCDs and up to 16M colors on 24-bit active
matrix LCDs.
The C&T65550 employs a variety of advanced power management features to reduce power
consumption of the display sub-system and extend battery life. Although optimized for 3.3V
operation, The C&T65550 controller's internal logic. memory interface, bus interface, and panel
interfaces can he independently configured to operate at either 3.3V or 5V.
SOFTWARE COMPATIBILITY/FLEXIBILITY
The C&T65550 are fully compatible with VGA at the register, and BIOS levels. CHIPS and third-
party vendors supply fully VGA-compatible BIOS, end-user utilities and drivers for common
application programs
Video Memory
Memory Controller
64-bit
Video Graphics
Capture Scaling Engine
Port
Analog
Capture RGB
YUV to RGB
Color Key Zoom
Digital
PCI Bus Bus Interface RGB
Mono Mono Mono Color Color Color Color STN Color Color Color Color
65550 SS DD DD TFT TFT TFT HR STN SS STN SS STN DD STN DD STN DD
Pin# Pin 8-bit 8-bit 16-bit 9/12/16 18/24 bit 18/24 bit 8-bit 16-bit 8-bit 16-bit 24 bit
Name bit (X4bP) (4bP) (4bP) (4bP)
71 P0 - UD3 UD7 B0 B0 B00 R1 R1 UR1 UR0 UR0
72 P1 - UD2 UD6 B1 B1 B01 B1 G1 UG1 UG0 UG0
73 P2 - UD1 UD5 B2 B2 B02 G2 B1 UB1 UB0 UB0
74 P3 - UD0 UD4 B3 B3 B03 R3 R2 UR2 UR1 LR0
75 P4 - LD3 UD3 B4 B4 B10 B3 G2 LR1 LR0 LG0
76 P5 - LD2 UD2 G0 B5 B11 G4 B2 LG1 LG0 LB0
78 P6 - LD1 UD1 G1 B6 B12 R5 R3 LB1 LB0 UR1
79 P7 - LD0 UD0 G2 B7 B13 B5 G3 LR2 LR1 UG1
81 P8 P0 - LD7 G3 G0 G00 SHFCLKU B3 - UG1 UB1
82 P9 P1 - LD6 G4 G1 G01 - R4 - UB1 LR1
83 P10 P2 - LD5 G5 G2 G02 - G4 - UR2 LG1
84 P11 P3 - LD4 R0 G3 G03 - B4 - UG2 LB1
85 P12 P4 - LD3 R1 G4 G10 - R5 - LG1 UR2
86 P13 P5 - LD2 R2 G5 G11 - G5 - LB1 UG2
87 P14 P6 - LD1 R3 G6 G12 - B5 - LR2 UB2
88 P15 P7 - LD0 R4 G7 G13 - R6 - LG2 LR2
90 P16 - - - - R0 R00 - - - - LG2
91 P17 - - - - R1 R01 - - - - LB2
92 P18 - - - - R2 R02 - - - - UR3
93 P19 - - - - R3 R03 - - - - UG3
94 P20 - - - - R4 R10 - - - - UB3
95 P21 - - - - R5 R11 - - - - LR3
96 P22 - - - - R6 R12 - - - - LG3
97 P23 - - - - R7 R13 - - - - LB3
70 SHFCLK SHFCLK SHFCLK SHFCLK SHFCLK SHFCLK SHFCLK SHFCLK SHFCLK SHFCLK SHFCLK SHFCLK
Pixels / 8 8 16 1 1 2 2-2/3 5-1/3 2-2/3 5-1/3 8
Clock:
2.6.1 Overview
The PCI1131 is a bridge between the PCI local bus and two PC Card sockets supporting both 16-
bit and 32-bit CardBus PC Cards, and is compliant with the PCI Local Bus Specification Revision
2.1 and PCMCIA's 1995 PCI Card Standard. The PCI 1131 PC Card interface recognizes and
identifies PC Cards installed at power-up, run-time, and switches protocols automatically to
accommodate 16-bit and 32-bit cards. Support for new 1 6-bit PC Card features such as multi-
function cards, 3.3V cards, and DMA, as well as backward compatibility to the PCMCIA Release
2.1-compliant PC Cards are included in the PCI1131. CardBus cards operating at up to 33MHz
and with a 32-bit data path offer higher performance, and the PCI1131 allows applications to take
full advantage of this bandwidth. The PCI1131 core is powered at 3.3V to provide low power
dissipation, but can independently support either 3.3V or 5V signaling on the PCI and PC Card
interfaces.
Host software interacts with the PCI1131 through a variety of internal registers which provide
status and control information about the PC Cards currently in use, and the internal operation of
the PCI1131 itself. These internal registers are accessed by application software either through the
PCI Configuration header, or through E programmable windows mapped into PCI memory or l/O
address space. The concept of windows is also user by the PCI1131 to pass cycles between PCI
and PC Card address spaces, and host software must program the location and size of these
windows when the PCI1131 or PC Card is initialized.
The PCI1131 also communicates via a three-line serial protocol to he TI TPS2206 Dual PCMCIA
Power Switch. The TPS2206 switches Vcc and Vpp supply voltage to the two PC Card sockets
independently. Host software has indirect control over the TPS2206 by writing to internal PCI1131
registers. In order to prevent damage to low-voltage CardBus PC Cards, the PCI1131 will allow
only valid Vcc settings to be applied to such cards.
The TPS2206 is the follow-on device to the TPS2202. The PCI1131 will also
interface with the TPS2202.
The PCI1131 can notify the host system via interrupts when an event occurs which requires
attention from the host. Such events are either card status change events (CSC) or functional
interrupts from a PC Card. CSC events occur within the PCI1131 or at the PC Card interface, and
indicate a change in the status of the socket (i.e., card insertion or removal). Functional interrupts
are interrupts which originate from the PC Card application itself, and are passed from the card to
the host system. Both CSC and functional interrupts may be individual masked and routed to a
variety of system interrupts. The PCI1131 can signal the system interrupt controll via PCI-style
interrupts, ISA IRQ's, or with the Serialized IRQ protocol.
The following sections describe in greater detail how the PCI1131 interacts at an electrical,
protocol, and software level at its PCI, PC Card, TPS2206, and interrupt interfaces
The Texas Instruments PCI1131 is a high-performance PCI-to-PC Card controller that supports
two independent PC Card sockets compliant with the1995 PC Card Standard. The PCI1131
provides a rich set of features which make it the best choice for bridging between PCI and PC
Cards in both notebook and desktop computers. The 1995 PC Card Standard retains the 16-bit PC
Card specification defined in PCMCIA Release 2.1, and defines the new 32-bit PC Card, called
CardBus, capable of full 32-bit data transfers at 33 MHz. The PCI1131 supports any combination
of 16-bit and CardBus PC Cards in its two sockets powered at 5V or 3.3V as required.
The PCI1131 is compliant with the PCI Local Bus Specification Revision 2.1, and its PCI interface
can act as either a PCI master device or a PCI slave device. The PCI bus mastering is initiated
during 16-bit PC Card DMA transfers or CardBus PC Card bus mastering cycles.
All card signals are internally buffered to allow hot insertion and removal without external
buffering. The PCI1131 is register compatible with the Intel 82365SL-DF ExCA controller. The
PCI1131 internal data-path logic allows the host to access 8-, 16-, and 32-bit cards using full 32-bit
PCI cycles for maximum performance. Independent, 32-bit write buffers allow fast posted writes to
improve system-bus utilization.
An advanced CMOS process is used to achieve low system power consumption while operating at
PCI clock rates up to 33 MHz. Several low-power modes allow the host power management
system to further reduce power consumption.
All unused PCI1131 pins should be pulled high with 43k ohm pull-up resistors.
2.6.3 Features
• 3.3-V Core Logic With Universal PCI Interface Compatible and 3.3-V or 5-V PCI Signaling
Environments
• Mix and Match 5W3.3V PC Card16 Cards and 3.3V CardBus Cards
• Supports Two PC Card ™ or CardBus Slots With Hot Insertion and Removal
• Supports Burst Transfers to Maximize Data Through put on the PCI and CardBus Bus
• Multi-function PCI Device with Separate Configuration Spaces for each Socket
• Five PCI Memory Windows and Two l/O Windows Available to each PC Card16 Socket
• Two l/O Windows and Two Memory Windows Available to each CardBus socket
• Texas Instruments (TI™) Extension Registers Mapped in the PCI Configuration Space
≠ Terminal name is preceded with B_. As an example, the full name for terminal 55 is B_A25.
D13 89 23
D12 87 20
D11 84 18
D10 147 81
D9 145 79
D8 142 77
D6 90 24
D5 88 21
D4 85 19
D3 83 17
D2 146 80
D1 144 78
D0 141 76
1 6-bit PC Card Interface Control Signals (Slots A and B)
CD1 82 16 I PC Card Detect 1 and Card Detect 2. CD1 and CD2 are connected to
CD2 140 74 ground internally on the PC Card. When a PC Card is inserted into a
socket, these signals are pulled low. The signal status is available by
reading the Interface Status Register
BVD1 I Battery Voltage Detect 1. Generated by 16-bit memory PC Cards that
(STSCHG/ 138 include batteries. BVD1 is used with BVD2 as an indication of the
72 condition of the batteries on a memory PC Card. Both BVD1 and BVD2
are kept high when the battery is good. When BVD2 is low and BVD1 is
RI) high, the battery is weak and needs to be replaced. When BVD1 is low,
the battery is no longer serviceable and the data in the memory PC
Card is lost. See the Card Status Change Interrupt Configuration
Register for enable bits (Section 8.6). See the Card Status Change
Register and the Interface Status Register for the status bits for this
signal.
Status Change. STSCHG is used to alert the system to a change in the
READY, Write Protect, or Battery Voltage Dead condition of a 16-bit I/O
PC Card.
Ring Indicate. RI is used by 1 6-bit modem cards to indicate ring
detection.
+ Terminal name is preceded with A_. As an example, the full name for terminal 121 is A_A25.
≠ Terminal name is preceded with B_. As an example, the full name for terminal 55 is B_A25.
+ Terminal name is preceded with A_. As an example, the full name for terminal 121 is A_A25.
≠ Terminal name is preceded with B_. As an example, the full name for terminal 55 is B_A25.
WE 110 46 O Write Enable . WE is used to strobe memory write data into 16-bit
Memory PC Cards. VVE is also used for memory PC Cards that employ
programmable memory technologies.
(DMA Terminal Count) This pin is used as TC during DMA operations to
a 16-bit PC Card which supports DMA. The PCI 1131 asserts this
signal to indicate Terminal Count for a DMA read operation.
READY 135 69 I Ready . The ready function is provided by the READY signal when the
(IREQ) 16-bit PC Card and the host socket are configured for the memory-only
interface. READY is driven low by the 16-bit Memory
PC Cards to indicate that the memory card circuits are busy processing
a previous write command. READY is driven high when the 16-bit
Memory PC Card is ready to accept a new data transfer.
Interrupt Request. IREQ is asserted by a 16-bit I/O PC Card to indicate
to the host that a device on the 16-bit I/O PC Card requires service by
the host software. IREQ is high (deasserted) when no interrupt is
requested.
+ Terminal name is preceded with A_. As an example, the full name for terminal 121 is A_A25.
≠ Terminal name is preceded with B_. As an example, the full name for terminal 55 is B_A25.
TERMINAL I /O FUNCTION
NAME NO TYPE
Interrupt Terminals
IRQ15/ I/O Interrupt Request 15. This terminal indicates an interrupt request
RI_OUT 163 from one of the PC Cards. RI_OUT allows the RI input from the 1 6-
bit PC Card, CSTSCHG from CardBus Cards or PC Card removal
events to be output to the system. This signal is configured in the
Card Control Register of the TI Extension Registers.
PC Card Power Switch Terminals
LATCH 150 O Power Switch Latch is asserted by the PCI1131 to indicate to the PC
Card power switch that the data on the DATA line is valid.
CLOCK 151 O Power Switch Clock. Information on the DATA line is sampled at the
rising edge of CLOCK. The frequency of the clock is derived from
dividing the PCICLK by 36. The maximum frequency of this signal is
2 MHz.
DATA 152 O Power Switch Data is used by the PCI1131 to serially communicate
socket power control information.
Speaker Control Terminal
SPKROUT/ I/O Speaker. SPKROUT carries the digital audio signal from the PC
SUSPEND 149 Card.
SUSPEND, when enabled, this signal places the PCI1131 in
PCI1131 Suspend Mode (Section 6.0) . This pin is configured in the
Card Control Register (Section 7.29) of the TI Extension Registers.
Power Supply Terminals
GND I Device ground terminals
13,22,44 75 96,129,
153, 167, 81
194,207
VccA 120 I Power-supply terminal for PC Card A (5V or 3.3V)
VccB 38 I Power-supply terminal for PC Card B (5V or 3.3 V)
VccP 148, 172 I Power-supply terminal for PCI interface (5V or 3.3V)
Vcc I Power-Supply terminal for core logic (3.3V)
7, 31, 64, 86, 113,
143,164, 175, 187,
201
The PC87336 FDC uses a high performance digital data separator eliminating the need for any
external filter components. It is fully compatible with the PC8477 and incorporates a superset of
DP8473, NEC PD765 and N82077 floppy disk controller functions. All popular 5.25” and 3.5”
floppy drives, including the 2.88 MB 3.5” floppy drive, are supported. In addition, automatic media
sense and 2 Mbps tape drive support are provided by the FDC.
The two UARTs are fully NS16450 and NS16550 compatible. Both ports support MIDI baud rates
and one port also supports IrDA’s the HP SIR and Sharp SIR compliant signaling protocol.
The parallel port is fully IEEE 1284 level 2 compatible. The SPP(Standard Parallel Port) is fully
compatible wit ISA and EISA parallel ports. In addition to the SPP, EPP(Enhanced Parallel Port)
and ECP(Extended Capabilities Port) modes are supported by the parallel port.
A set of configuration registers are provided to control the Plug and Play and other various
functions of the PC87336. These registers are accessed using two 8-bit wide index and data
registers. The ISA I/O address of the register pair can be relocated using a power-up strapping
option and the software configuration after power-up.
When idle, advanced power management features allows the PC87336 to enter extremely low
power modes under software control. The PC87336 can operate from a 5V or a 3.3V power
supply. An unique I/O cell structure allows the PC87336 to interface directly with 5V external
components while operating from a 3.3V power supply.
2.7.1 Features
• 100% compatible with ISA, and EISA architectures
• The UARTs:
• Software compatible with the PC16550A and PC16450
• MIDI baud rate support
• Infrared support on UART2(IrDA and Sharp-compliant)
UART
Configuration UART
+ IrDA/HP & Sharp IR
Registers (16550 or 16450)
(16550 or 16450) Floppy Disk Floppy
Controller with Drive
Digital Data Interface
Separator
Floppy
Drive (Enhabced 8477)
General IEEEE1284
Power Interface
Purpose Parallel Port
Down Logic
Registers
Hifh Current Driver
OSC Interrupt
I/O Ports Control and
Interrupt Data Handshake DMA
NOTE: When the TERI bit of the MSR is set and Modem Status
interrupts are enabled, an interrupt is generated.
/RTS1 72, 64 O UARTs Request to Send. When low, this output indicates to the
/RTS2 modem or data set that the UART is ready to exchange data. The
RTS signal can be set to an active low by programming bit 1 (RTS) of
the Modem Control Register to a high level. A Master Reset
operation sets this signal to its inactive (high) state. Loop mode
operation holds this signal to its inactive state.
SIN1 73, 65 I UARTs Serial Input. This input receives composite serial data from
SIN2 the communications link (peripheral device, modem, or data set).
SIRQ1 58, I System interrupt 1, 2, and 3. This input can be routed to one of the
SIRQ2 49, following output pins: IRQ3-IRQ7, IRQ9-IRQ12. SIRQ12 and
SIRQ4 47 SIRQ13 can be also routed to IRQ15. Software configuration
determines to which output pin the input pin is routed to.
SIRQ1 is multiplexed with IRQ15, SRIQ12 is multiplexed with
DRATE1/MSEN1/CS0, and SIRQ3 is multiplexed with
DRV2/PNF/DR23.
SLCT 80 I Parallel Port Select. This input is set high by the printer when it is
selected. This pin has a nominal 25 KΩ pull-down resistor attached
to it.
/SLIN 79 I/O Parallel Port Select Input. When this signal is low, it selects the
printer. This pin is in a tristate condition 10 ns after a 0 is loaded into
the corresponding Control Register bit. The system should pull this
pin high using a 4.7 KΩ resistor.
SOUT1 71, 63 O UARTs Serial Output. This output sends composite serial data to the
SOUT2 communications link (peripheral device, modem, or data set). The
SOUT signal is set to a marking state (logic 1) after a Master Reset
operation.
/STB 93 I/O Parallel Port Data Strobe. This output indicates to the printer that a
valid data is available at the printer port. This pin is in a tristate
condition 10 ns after a 0 is loaded into the corresponding Control
Register bit. The system should pull high using a 4.7 KΩ.
/STEP 38 O FDC Step. This output signal issues pulses to the disk drive at a
(Normal Mode) software programmable rate to move the head during a seek
operation.
/STEP 79 O FDC Step. This pin gives an additional step signal in PPM Mode
(PPM Mode) when PNF = 0.
2.8.1 Features
• Built-in OPL3
• Built-in Joystick
• Supports multi-purpose pin function (Support 16-bit address decode, DAC interface for OPL4-
ML, Zoomed Video port, EEPROM interface, MODEM interface, IDE CD-ROM interface)
• Supports Power Management(power down, power save, partial power down, and
suspend/resume) ..
• +5V/ +3.3V power supply for digital, 5V power supply for analog.
2.9.1 Overview
Ambit T62.062.C.00 charger is designed exclusively for TI Extensa 610 notebook computer as a
power management and battery charger module which can charge a 9 cells Nickel-Metal Hydride
(NiMH) or 9 cells with 3’s parallel and 3’s serial Lithium Ion(LIB) Battery pack. When charging the
NiMH battery , the determination of the battery full capacity for the charger is based on zero delta
Voltage (0 V), temperature increment gradient (T/t), minus delta voltage (-V) and maximum
voltage (Max. V). On the other hand, if charging the LIB battery, constant current and constant
voltage the typical LIB battery charging mode will be applied precisely. It is important to notice that
every battery pack to be used must have a built-in 103AT-2 NTC thermistor (maximum 70thermal
breaker included for NiMH battery). Otherwise, most of the charger functions so as to be failed.
The charger permits a soft charging of NiMH battery to full capacity whereas over-charging is well
protected. Fast charge begins with the application of the external AC adapter or the replacement
of a new plugged in battery whichever NiMH or LIB battery. For safety, at the beginning of
charging, battery will not be charged until its temperature within a certain interval and if start
voltage is lower than another certain value, the charger module provides trickle charge current to
charge the battery which prevents fast charging could possibly damage the battery. In addition,
maximum temperature protection and safe timer is provided during quick charge. To maintain the
capacity once the NiMH reaches full energy level, trickle charge current will be continuously
provided to the battery by the charger.
2.9.2 Features
• Designed for charging a 9 cells Nickle-Metal Hydride Battery pack or 9 cells (3 parallel,
3 serial) Lithium- Ion Battery pack
• Charging LIB battery following the constant current then constant voltage mode
• Providing low battery warning signals when the system using battery as the main power
source
Output current 3A
Operating temperature 0 to 60
(Supply current) 10 mA
Battery in use (High) BAT-IN-USE# @I load=100uA 2.7 5 5.25 V
(Low) 0.7 V
(Supply current) 100 uA
Power Output DCBAT OUT - - 3 A
Charge Indicator BT-QCHG Quick
(High) 3.5 5 5.25 V
(Low) - - 0.8 V
(Supply current) - - 100 uA
Battery Low 1 BL1# @I load=100uA
(High) 2.7 5 5.25 V
(Low) - - 0.7 V
(Supply Current) - - 100 uA
Battery Low 2 BL2# @I load=100uA
(High) 2.7 5 5.25 V
(Low) - - 0.7 V
(Supply Current) - - 100 uA
BATTERY LOW VOLTAGE WARNING SIGNAL
Battery Low 1 (NiMH) @25 10.53 10.70 10.86 V
(LIB) TC125PPM/ 8.50 8.65 8.80
Battery Low 2 (NiMH) @25 10.19 10.35 10.50 V
(LIB) TC125PPM/ 8.08 8.23 8.38
Battery Low 3 (NiMH) @25 9.07 9.22 9.36 V
(LIB) TC125PPM/ 7.58 7.73 7.88
CHARGE PARAMETER
External Adapter System not in use 1.8 1.9 2.0 A
Charge current System in use 0.58 0.65 0.72 A
DC_BAT_OUT 1o o2 DC_BAT_OUT
DC_BAT_OUT 3o o4 DC_BAT_OUT
GND 5o o6 GND
SYSTEM ON 9o o 10 DISABLE
BT_QCHG 11 o o 12 AD5V
SMI 13 o o 14 S.I.U.
TH 15 o o 16 BL1#
ID 17 o o18 BL2#
When the charger module charges a 9 cells NiMH battery, 0V and T/ t, max T and - v detentions
will be used as the main methods to determine the full charged battery. To ensure safety for the
battery and system, fast charging NiMH battery after long period of storage time, the module will
disable 0V detection during a short “ hold-off” period at the start of fast charging. Also when
‘charge in use’ the 0V and -V detection will be disabled during whole charging period.
When system not in use power, the quick charge current will be limited by the Adapter to
1.9A0.1A. If system in use the charge current will be limited by charger module to 0.650.07A.
When battery voltage lower than 1.0v/cell the charger module will precharge the battery (with 1/8
duty cycle/2HZ) and 50/150 minutes maximum timer.
When battery is fully charged, the charger module will offer 25mA 5mA trickle current to maintain
the battery at 100% capacity.
The BT-QCHG pin will send a logic high signal for LED indication by the charger, when precharge
or quick charge is on.
When the charger module charges a 9 cells (3’s parallel , 3’s serial) LIB battery. The charger will
offer 1.90.1A charger current when system not in use power whereas 0.650.07A when system in
use power. Quick charge will be terminated when charge current less then 150mA60mA. Then
12.67V 0.05V constant voltage with one hour timer will be applied to charge battery. Also if battery
voltage lower than 7.50.2V the charger will precharge the battery, using 200mA60mA with 2 hours
maximum timer.
When battery is fully charged the charger module stop charge. But the charger module will
recharge the battery if battery voltage lower then 11.4V 0.2V.
The BT-QCHG pin will send a logic high signal for LED indication, when precharge or quick charge
is on.
When system turned on, the charger will check AC power inserted or not . If AC power inserted,
then AC power will be the role of power provider. If not, the charger will discharge the battery
already inserted in the notebook system.
If system in use power when Adapter not inserted and battery voltage lower than BL1 voltage, the
charger module will indicate a battery Low 1 signal . And if battery voltage lower than BL2 voltage
, the charge will indicate a Battery Low 2 signal .
In addition, when system sends a ‘disable’ signal to charger module, system will be turned off by
the charger module immedietly.
For safety, the charger module inhibits charging until the battery voltage and temperature are
within the configured ranges. If the voltage is less than the low voltage threshold , the charger
module provides trickle current to charge the battery . This prevents fast charging could possibly
damage the battery. Also when the temperature of battery pack is over the temperature threshold,
the charger module will not charge the battery until its temperature within a configured range. This
prevents reducing the battery’s service life.
Concludely, in order to ensure safety for the battery and system, charge may be terminated when
the battery temperature over a threshold or after a safety time period.
The converter also supplies P.G. signal, 2.35V/2.45V/2.9V/3.1V switch for CPU and ON/OFF
control.
Input:
• DC BATT_IN:7V-8V DC
Output:
Input:
• DCBATT_IN :8V-21V DC
Output:
2.10.4 Control
• VCPU Control: Control switch can switch Vcpu output voltage to 2.35V2.45V2.9 or 3.1V.
• ON/OFF: A logic low will turn off +5V,+3.3V, 2.35V/2.45V/2.9V/3.1V,+12V and +6V
main o/p. The DC/DC converter draws about 30uA when the notebook computer is in
shutdown mode.
2.10.5 Application:
The recommended value is two pieces of 10uf/50V ceramic capacitor(or the same grade
capacitor, such as SANYO OS-CON capacitor) with less than 150mohm ESR. And it should be
located less than 10mm away from DCBATT_IN pin.
Efficiency:
Environment:
• Operating
• Temperature: 0 to 65
• Relative Humidity: 10% to 95%
• Shipping/Storage
• Temperature: 25 to 85
• Relative Humidity: 10% to 95%
Electrical Characteristics
J2:SM02(8.0)B-BHS-1-TB2P (JST)
Electrical Characteristics
Operation Conditions
J2:SM02(8.0)B-BHS-1-TB2P (JST)
Setup Utility
• System Security
Read through the Setup Screen Notes before navigating the Setup screens.
• From the main menu, press ↑ , ↓ , ← or → to move from one menu item to another and press
Enter to enter the selected menu.
• When accessing multi-page sections, press PgDn and PgUp to go through the pages.
• Parameters displayed in low brightness (grayed-out) are not user-configurable. The notebook
detects and sets the values for these parameters.
• Most of the Setup parameters are self-explanatory. Press F1 for help on individual
parameters.
[Yes] [No]
• Select [Yes] to save the changes you made to the configuration values or [No] to
abandon the changes and retain the current values.
The notebook displays the current date in MM/DD/YY format and the current time in HH:MM:SS
format. It uses a 24-hour clock; for example, 6:25 PM displays as 18:25:00.
The default setting for Diskette Drive A is [1.44 MB 3.5-inch] and this setting applies to
both an internal and external floppy drive configuration. Diskette Drive B, by default, is set to
[None]. Enable this parameter if two floppy drives are connected to the notebook.
The default setting for IDE Drive 0 is [Auto]. With this setting, the BIOS automatically detects
your drive parameters. You can also opt to key in your drive parameters by setting this parameter
to [User]. To determine your drive parameters, look at the data on the label pasted on your
hard disk drive (or supplied in vendor documentation) and type in the parameters. Be sure to set
the correct drive parameters; otherwise an error message appears when you boot up the notebook.
We suggest you set this parameter to [Auto].
The default setting for Large Hard Disk Capacity is [Enabled]. Set this parameter to
[Disabled] if you use the UNIX operating system on this computer.
The notebook can test main memory for errors when you turn it on. The default setting,
[Disabled], allows the notebook to bypass the memory test and speed up the self-test
procedure.
If you connect an external monitor, you can switch display between the LCD and the external
display. This parameter determines which display device the notebook uses on boot-up. Table 3-
1 describes the different settings.
Setting Description
Auto (default) If an external display is present, the notebook uses the external
display; otherwise, the LCD is the display device.
Both The notebook uses the external display and LCD simultaneously.
In Quiet Boot mode, the notebook does not display POST messages on your display. The default
setting is [Enabled].
System Security
This parameter allows you to enable or disable the read/write functions of the floppy drive. The
following table summarizes the available options.
Setting Description
Normal (default) Floppy drive functions normally
Write Protect Disables the floppy drive write function on a diskette’s boot sector. This option is
Boot Sector for operating systems that access the floppy drive 100 percent via BIOS only.
Disabled Disables the floppy drive
This parameter allows you to enable or disable the read/write functions of the hard disk drive. The
following table summarizes the available options.
Setting Description
Normal Hard disk drive functions normally
(default)
Write Protect Disables the hard disk drive write function on the hard disk’s boot sector. This
Boot Sector option is for operating systems that access the hard disk 100 percent via BIOS only.
Disabled Disables the hard disk drive
This parameter determines which drive the notebook boots from when you turn it on. The
following table lists the three possible settings.
Setting Description
Drive A Then C Notebook boots from floppy drive A. If there is no system disk in drive A, the
(default) notebook boots from hard disk C. If the hard disk is a non-system disk, an error
message appears.
Drive C Then A Notebook boots from hard disk C. If hard disk C is not a system disk, the notebook
boots from floppy drive A. If no diskette is present or if the diskette in floppy drive
A is a non-system disk, an error message appears.
Drive C Notebook boots from hard disk C. If hard disk C is not a system disk, an error
message appears.
Drive A Notebook boots from floppy drive A. If no diskette is present or if the diskette in
floppy drive A is a non-system disk, an error message appears.
An installed PCMCIA bootable card overrides the System Boot Drive setting.
The notebook supports SRAM card boot.
When enabled the notebook checks the CD-ROM drive first and boots from there, if possible,
before checking the System Boot Drive control setting.
There are two image types/formats for CD-ROMs - floppy drive and hard disk. See Table 3-5 for a
description.
The serial port can accommodate a modem, serial mouse, serial printer, or other serial devices.
The default setting for the serial port base address is 3F8h(IRQ 4)1.
• 2F8h(IRQ 3)
• 3E8h(IRQ 4)
• 2E8h(IRQ 3)
• Disabled
Make sure the serial port base address does not conflict with the address used by a PCMCIA card,
if one is installed.
The parallel port can accommodate a parallel printer or other parallel devices. The default setting
for the parallel port base address is [378h(IRQ 7)]1. The other options for this parameter are:
• 278h(IRQ 5)
• 3BCh(IRQ 7)
• Disabled
ECP or Extended Capabilities Port supports a 16-byte FIFO (first in, first out) which can be
accessed by host DMA cycles and PIO cycles. ECP boosts I/O bandwidth to meet the demands
of high-performance peripherals. EPP or Enhanced Parallel Port is a parallel port interface that
greatly improves performance for bi-directional block-mode data transfers. EPP provides greater
throughput by supporting faster transfer times and a mechanism that allows the host to address
peripheral device registers directly.
If you set EPP as the parallel port operation mode, do not use
3BCh as the parallel port base address; otherwise, I/O conflicts
may occur.
Set the ECP DMA Channel parameter if you set the Parallel Port Operation Mode to [Enhanced
Capabilities Port(ECP)]. The default value, with ECP selected, is [0].
3.4.8 Passwords
Two passwords are implemented in this notebook. The Setup Password prevents unauthorized
access to the Setup utility, while the Power On Password prevents unauthorized access to the
notebook during boot-up and resume from hibernation.
Setting a Password
To set a password, select the desired password (Setup and Power On) to set or edit, and press ←
or → . The password prompt (a key) appears:
A message below the menu prompts you to enter a password. The password may consist of up to
seven characters which do not appear on the screen when you type them. After typing your
password, press Enter. Another prompt appears asking you to retype your password to verify your
first entry.
After setting a password, the notebook sets this parameter to [Enabled]. The next time you
boot the notebook, resume from hibernation mode or run the Setup utility, the password prompt
appears. Key in the appropriate password (Power On or Setup). If the password you entered is
incorrect, an “X” appears. You have three chances to type in the correct password. After three
tries, the following message appears:
The notebook freezes up and disables all devices. You must turn off the notebook and turn it on
again to retry. If you forget your password, you must reset the configuration values stored in
CMOS to defaults. Resetting CMOS requires opening up the notebook, so contact your dealer for
assistance.
Removing a Password
To remove a password, select the desired password (Setup and Power On) to remove and press
← or → to set it to [None].
The notebook comes pre-installed with a Windows 95 version which has built-in support for
CardBus. In this case, CardBus Support is not needed and set to [Disabled]. If in case you
install an older version of Windows 95 which does not have built-in Cardbus driver support, you
need to enable this parameter. The default setting is [Disabled].
With enabled, all the timers in Setup take effect unless specifically disabled by the user. Select
[Disabled] to turn off all the timers. The default setting is [Enabled].
You cannot disable this parameter in Setup if APM is installed under DOS,
Windows or Windows 95. To disable APM, type Power Off under DOS, or
disable the Power icon in the Windows Control Panel.
The notebook shuts off the LCD backlight and turns off the CRT video as well, if there is no
activity from the keyboard or external PS/2 mouse within the period specified by this timer. To
turn the display back on, press a key or move the mouse.
The valid values for this timer range from 1 to 15 minutes with default set at [1]. Select [Off]
to disable the timer.
The hard disk drive enters standby mode if there are no disk read/write operations within the
period specified by this timer. The hard disk returns to normal mode once the notebook accesses
it.
This parameter enables you to set a timeout period for the notebook to enter either standby or
hibernation mode. The System Sleep Mode parameter determines which sleep mode the
notebook will enter into.
The valid values for this timer range from 1 to 15 minutes with default set at [3]. Select [Off]
to disable the timer.
This parameter tells the notebook which sleep mode (Standby or Hibernation) to enter into when
the System Sleep Timer times out. The default setting is [Hibernation].
When enabled, the notebook resumes from standby mode at the specified Resume Date and
Resume Time parameter settings.
The Resume Date and Resume Time parameters let you set the date and time for the resume
operation. The date and time fields take the same format as the System Date and Time
parameters in the Basic System Settings screen.
Setting a resume date and time that is not valid automatically disables these
fields. A successful resume occurring from a date and time match
automatically disables these fields.
When enabled, the notebook wakes up from standby mode and returns to normal mode when a
PCMCIA modem detects a ringing tone. The default setting is [Enabled].
This parameter allows you to enable or disable the warning beep generated by the notebook when
a battery-low condition occurs. The default setting is [Enabled].
This parameter enables the notebook to enter standby or hibernation mode when a battery-low
condition takes place. The default setting is [Enabled].
F1=Help, Esc=Exit
The items in this screen are not user-configurable. See table below.
Item Description
CPU ID Shows the processor type
CPU Clock Shows the processor speed
System memory Shows the total system memory
Video memory Shows the total video memory
Floppy Disk A Shows the floppy drive A type
Security Shows floppy drive A security setting
Floppy Disk B Shows the floppy drive B type
Security Shows floppy drive B security setting
Hard Disk Shows the IDE drive type and size and its security setting
Security Shows hard disk drive security setting
CD ROM Shows the presence of a CD-ROM drive
System Boot Drive Shows the boot sequence setting
CD ROM Bootable Shows if the CD ROM Bootable feature is enabled or not
Serial Port 1 Shows the serial port base address and IRQ
Parallel Port Shows the parallel port base address and IRQ
Operation Mode Shows the parallel port operation mode
Internal Cache Shows the internal cache size and setting
External Cache Shows the external cache size
Pointing Device Shows the presence of a pointing device
Internal KB Shows the internal keyboard type
This screen may show other items which are not in this list if certain parameters
settings are changed and enabled.
[Yes] [No]
Select [Yes] to load the default settings or [No] to abort the operation.
• Wrist grounding strap and conductive mat for preventing electrostatic discharge
• Flat-bladed screwdriver
• Phillips screwdriver
• Hexagonal screwdriver
• Tweezers
• Plastic stick
The screws for the different components vary in size. During the
disassembly process, group the screws with the corresponding
components to avoid mismatch when putting back the components.
Before proceeding with the disassembly procedure, make sure that you do the following:
2. Unplug the AC adapter and all power and signal cables from the system.
3. Remove the battery pack from the notebook by (1) pressing the battery compartment cover
release button, and sliding out the cover. Then (2) pull out the battery pack.
Unplug the cable by simply pulling out the cable from the connector.
You can use a plastic stick to lock and unlock connectors with locks.
To unplug the cable, first unlock the connector by pulling up the two clasps on both sides of
the connector with a plastic stick. Then carefully pull out the cable from the connector.
To plug the cable back, first make sure that the connector is unlocked, then plug the cable
into the connector. With a plastic stick, press the two clasps on both sides of the connector to
secure the cables in place.
The disassembly procedure described in this manual is divided into four major sections:
The following table lists the components that need to be removed during servicing. For example,
if you want to remove the motherboard, you must first remove the keyboard, then disassemble the
inside assembly frame in that order.
The flowchart on the succeeding page gives a clearer and more graphic representation on the
entire disassembly sequence. Please refer to it from time to time.
2. Remove the screw from the memory expansion door and remove the door.
The memory door screw is part of the memory door and does not
separate from the memory door.
4. Align the connector edge of the memory module with the key in the connector. Insert the
edge of the memory module board into the connector. Use a rocking motion to fully insert the
module. Push downward on each side of the memory module until it snaps in place.
To remove the memory module, release the slot locks found on both ends of the memory slot
to release the DIMM. Then pull out the memory module.
1. Turn the computer over and locate the hard disk drive bay cover.
2. Remove the screw that secures the hard disk drive bay cover. Then slide out and remove the
the cover. Set aside the cover.
Be careful pulling the hard disk drive out. Make sure the connector
of the hard disk drive transfer board doesn’t loosen while removing
the hard disk drive.
If you want to install a new hard disk drive, reverse the steps described above.
1. Slide out (1) and pull up (2) the two display hinge covers on both sides of the notebook.
2. Unplug the keyboard connectors (CN1 and CN2) from the keyboard connection board. Set
aside the keyboard.
Remove the four screws that secure the heat sink to the housing.
2. Unplug the internal drive cable (CN14/CN17 for CD-ROM or CN14 for FDD).
Ensure the drive cables do not become hooked on the inside frame
assembly when removing and reinstalling the drive.
The unique ZIF (zero insertion force) socket allows you to easily remove the CPU. Follow these
steps to remove the CPU and install a replacement CPU. See figure below.
1. Insert a flat-blade screwdriver into the opening at the left end of the socket (labeled OPEN)
and push towards the other end of the socket.
2. Pull out the CPU. Then insert the replacement CPU. Insure the CPU is properly keyed
before pressing it into the socket.
3. Insert a flat-blade screwdriver into the opening at the right end of the socket (labeled LOCK)
and push towards the other end of the socket.
New CPU
Old CPU
2. Remove the four display hinge screws. Then detach the display from the main unit and set
aside.
Figure 4-16 Detaching the Top Cover from the Base Assembly
Remove four screws that secure the inside frame assembly to the base assembly. Then detach
the inside frame assembly from the base assembly.
When installing the fan, the fan hole should face the rear of the unit
to draw thermal air out of the system.
2. Remove the audio board by (1) unplugging the audio board connector (CN5), and then (2)
pulling up the audio board.
4. Unplug the (a) LCD cover switch cable (CN8) and (b) speaker cables (CN7 and CN10).
CN7
CN8
CN10
Figure 4-21 Unplugging the LCD Cover Switch and Speaker Cables
6. Remove seven screws that secure the motherboard to the inside assembly frame. Then
release the latch and pull up the motherboard to detach it from the inside assembly frame.
Figure 4-23 Detaching the Motherboard from the Inside Assembly Frame
The PC Card Connector Module is normally part of the motherboard spare part. The following
removal procedure is for reference only.
The touchpad is connected to the top cover. Follow these steps to remove the touchpad
assembly:
2. Remove the three screws and disconnect the touchpad cable (J2), then remove the touchpad
main sensor and connector unit.
Screw list:
Touchpad mylar
¶ x 3, M2L4
Touchpad cable
Touchpad knob
1. Remove the oval LCD bumpers at the top of the display and the long bumper on the LCD
hinge.
Screw List:
or
x4, M2.5L6
x1, M2.5L6(for 11.3” TFT LCD)
x1, M2.5x8(for 11.3” STN and 12.1” TFT LCD)
Screw List:
x4, M2.5L6
x1, M2.5L6(for TFT LCD)
x1, M2.5x8(for STN LCD)
STN and TFT LCDs use the same bezel but different panels.
1
2
3
1 1
4. Twist (1), then slide out (2) and remove the Hinge Cable Cover.
The hinge cable cover cannot be removed unless the LCD bezel is
removed.
6. Tilt the LCD Panel away for the display cover. Then unplug the LCD Panel from the Display
Cable Assembly.
2
1
Figure 4-33 Removing the DC-AC Inverter and LCD ID Inverter Boards
5. Remove five screws that secure the LCD cable to the display back over, then remove the
LCD cable assembly.
Screw list:
x1, M2L4
x4, M2.5L5
610XX-X X X
Keyboard Language Version
0: Swiss/US G: German
1: US(110V) I: Italian
2: US(220V) J: Japanese
3: US w/o power cord N: Norwegian
4: US K/B w/o power cord(ACLA) R: Russian
5: US(110V for AAB) S: Spanish(220V)
6: US(220V)with CCIB for P.R. Chinese T: Thailand
7: Spanish w/o power cord U: UK(250V)
8: Turkish W: Swedish/Finnish
A: Arbic S: Swiss/German
C: Chinese Y: Swiss/French
D: Danish K: Korean
F: French Z: w/o Keyboard
LCD
C :11.3" DSTN
CX:11.3" TFT
DX:12.1" TFT
Spare Parts
This appendix lists the spare parts of the notebook TI EXTENSA 610.
Table C-1 Spare Parts List
Power
AC ADAPTER ASSY,EXTENSA 61X w/power cord 91.48428.011 9811754-0001
BATTERY PACK,EXTENSA 61X,NIMH SANYO 91.46928.012 9811738-0001
BATTERY PACK,EXTENSA 61X,NIMH TOSHIBA 91.46928.007 9811738-0003
LI-ION 91.46928.003 370/370P, EXT61X 91.46928.003 9811763-0001
Memory
8 MB memory modules 91.46910.001 9811344-0001
16 MB memory modules 91.46910.002 9811344-0002
32 MB memory modules 91.46910.003 9811344-0003
Schematics
This appendix shows the schematic diagrams of the notebook.
3.3V 2.9V
3.3V
3 3 3 3 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 3 3 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1
2 1 0 0 8 8 8 8 8 1 0 9 8 7 6 5 5 4 4 3 2 1 1 0 9 8 2 2 2 2 2 1 1 0 7 7 7 7 7 6 0 9 8 7 6 5 4 3 2 1 0 9 8 1 1 1 1 3 3 3 4 4 6 6 2 4 U21 R214
2 $CPUA[3..31] 0 5 6 3 9 7 5 3 1 7 7 7 7 7 7 7 3 7 4 7 7 7 3 7 7 7 9 7 5 3 1 9 1 0 9 7 5 3 1 9 8 8 8 8 8 8 8 8 8 8 8 8 8 7 5 3 1 9 7 1 2 3 7 8 4 3 5 3 5 4 2
10KR3
##
$CPUA3 258 V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V N N N N N N N N N N N N 322 2 R214 NOT INSTALL
A3-AL35 C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C UPVRM#-AH32
$CPUA4 294 C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C | | | | | | | | | | | |
$CPUA5 255 A4-AM34 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 A B A A C R S S WWA A 262
$CPUA6 A5-AK32 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1 2 3 3 1 3 3 3 3 3 L L AM2-ADSC#
293 A6-AN33 A A E E A A A A A A A A A Y W U U S T Q N L L J G E A A A A A A A E A A A A A A A A A A Y WU S Q N L J G A A A A A A 7 4 3 5 3 5 1 1 AJ5-ADS# 220 $CPUADS# 2,5
$CPUA7 256 J J 2 2 N N N N N G E C A 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 1 J 1 N N N N N N G E C A 1 1 1 1 1 1 1 1 1 1 1 1 1 9 7 9 266 2
$CPUA8 292 A7-AL33 2 1 7 1 2 2 2 2 2 3 3 3 3 7 7 7 3 7 4 7 7 7 3 7 7 7 9 7 5 3 1 9 1 5 1 1 1 1 1 9 1 1 1 1 7 5 3 1 AM6-W/R#
141
$WR#
A8-AM32 9 9 9 7 5 3 1 7 7 7 7 1 9 7 5 3 1 T4-M/IO# $MIO# 2
$CPUA9 253 227 2
$CPUA10 A9-AK30 AK4-D/C# $DC#
291 A10-AN31 AC5-PRDY 192
$CPUA11 254 243 4
$CPUA12 A11-AL31 AK20-RESET $CPURST
252 A12-AL29
$CPUA13 251 182 $WBWT# 3.3V
$CPUA14 250 A13-AK28 AA5-WBWT# 133 $TRST#
$CPUA15 A14-AL27 Q33-TRST#
249 A15-AK26 P34-TMS 124
$CPUA16 248 A16-AL25 N33-TDO 123 RP19
$CPUA17 247 A17-AK24 N35-TDI 125 $WBWT# 1 10
$CPUA18 246 114 $TCK $HLOCK# 2 9 $CACHE#
$CPUA19 245 A18-AL23 M34-TCK 210 $AP 3 8 $FRCMC#
$CPUA20 A19-AK22 AG3-SMIACT# $SMIACT# 2 $BUSCHK# $PEN#
244 A20-AL21 AB34-SMI# 184 $CPUSMI# 8 4 7
$CPUA21 204 240 5 6 $FLUSH#
A21-AF34 AL17-SCYC 3.3V
$CPUA22
$CPUA23
$CPUA24
$CPUA25
$CPUA26
216
203
215
222
214
A22-AH36
A23-AE33
A24-AG35
A25-AJ35
P55C/P54C AC35-R/S#
AL3-PWT
R4-PM1/BP1
195
226
131
130
SRP10K
RP18
3.3V
U22
8 1 8
TH_DQ 2 DQ VDD 7
8 TH_CLK 3 CLK/CONV# THIGH 6 R103 CPU_TH 20
8 TH_RST# 4 RST# TLOW 5 CPU_TL
GND TCOM 1 2 TH_COM 8,13
1,5 $CPUD[0..63] DS1620 33R3
$CPUD[0..63]
$ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $
C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C
P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P
U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U
D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D
6 6 6 6 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2
3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4
+5V
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 8 TH_DQ_VGA U18
2 4 4 4 6 6 8 6 8 8 8 0 0 1 0 0 2 1 2 1 3 1 2 2 3 3 3 6 4 6 6 7 7 7 8 7 8 8 9 U48 1 8
1 1 3 2 1 2 3 3 1 2 4 1 3 4 6 1 2 7 4 8 7 7 5 6 5 8 5 6 8 5 6 7 8 6 7 8 5 6 7 9 DQ VDD
TH_CLK 2 7
TH_RST# 3 CLK/CONV# THIGH
6
HH H H H H H H H H H H H HH H HH H HH HH H H H H H H H H H H H H HH HH H 4 RST# TLOW 5
DD D D D D D D D D D D D DD D DD D DD DD D D D D D D D D D D D D DD DD D GND TCOM TH_COM_VGA 13
6 6 6 6 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2
$BE#[0..7] 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 185 $CPUD23 DS1620
1 $BE#[0..7] HD23 210 $CPUD22 1
HD22 197 $CPUD21 R97
HD21 212 $CPUD20 100KR3
$BE#0 146 HD20 198 $CPUD19
$BE#1 147 HBEJ0 HD19
230
HBEJ1 HD18 $CPUD18 2
$BE#2 148 211 $CPUD17
$BE#3 155 HBEJ2 HD17 232 $CPUD16
$BE#4 156 HBEJ3 HD16 250 $CPUD15
$BE#5 157 HBEJ4 HD15
231 $CPUD14
$BE#6
$BE#7
158
HBEJ5
HBEJ6
ALADDIN3 HD14
HD13 252 $CPUD13
$CPUD12
165 HBEJ7 HD12 209
HD11 272 $CPUD11
$CPUA3 259 251 $CPUD10
$CPUA4 299 HA3 HD10 271 $CPUD9
$CPUA5 HA4 HD9 $CPUD8
236 229
$CPUA6
$CPUA7
300 HA5
HA6 CPU BUS & CACHE HD8
HD7 196 $CPUD7
$CPUD6
296 HA7 HD6 249
$CPUA8 256 270 $CPUD5
$CPUA9 255 HA8 HD5 269 $CPUD4
$CPUA10 HA9 HD4
295 292 $CPUD3
$CPUA11
$CPUA12
275 HA10
HA11
M1521 HD3
HD2 290 $CPUD2
$CPUD1
235 291
$CPUA13 294 HA12 HD1 289 $CPUD0
$CPUA14 254 HA13 HD0
$CPUA15 HA14 $TAG10
274 HA15 TIO10/MWEJ1 308
$CPUA16 234 307 $TAG9 FOR CACHE & SDRAM
$CPUA17 HA16 TIO9/SRASJ1 $TAG8 NOT AVAILABLE IN II
293 HA17 TIO8/SCASJ1 287
$CPUA18 273 306 $TAG7
$CPUA19 253 HA18 TIO7 286 $TAG6
$CPUA20 HA19 TIO6 $TAG5
233 HA20 TIO5 266
$CPUA21 257 222 $TAG4
$CPUA22 238 HA21 C C TIO4 265 $TAG3
$CPUA23 HA22 A A B TIO3 $TAG2
237 HA23 D D W TIO2 245
$CPUA24 278 K V S E 244 $TAG1
$CPUA25 277 HA24 E S J J J TIO1 191 $TAG0
$CPUA26 258 HA25 N C H M H / / / TIO0
HA26 H E B B A J A L H I C C C C $TAG[0..7]
H H H H H A A O R H / C M O I A L A A C GC GT $TAG[0..7] 5
A A A A A D D F ND O I H I C D T WC K A A C WO C W
2 2 2 3 3 S S F AY L N E O K C MR T I 4 3 S E E S E
7 8 9 0 1 J J J J J D V J J J J J J J N J J J J J J J
1521-27/A
2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 2 2 2 2 1 2 2 2 3 2 3 2
9 9 3 7 7 1 0 8 7 6 5 4 3 2 1 1 1 1 1 5 6 8 8 0 4 0 6
7 8 9 9 6 3 0 9 9 9 9 9 9 9 8 5 6 7 8 0 3 3 4 4 3 5 4
$ $ $ $ $ $TWE# 5
C C C C C $BWE# 5
P P P P P $COE# 5
U U U U U $GWE# 5
A A A A A $CCS# 5
2 2 2 3 3 $CADS# 5
7 8 9 0 1 $CADV# 5
$CPUA[3..31]
1,5 $CPUA[3..31] $21CLK $21CLK 7
1 $CPUADS# $CPUADS# $SMIACT# 1
$EADS# $WR# $SMIACT#
1 $EADS# $BOFF# $HITM# $WR# 1
1 $BOFF# $HITM# 1
1 $NA# $NA#
1,8 $BRDY# $BRDY#
$AHOLD
1 $AHOLD $KEN#
1 $KEN# $CACHE#
1 $CACHE#
1 $MIO# $MIO#
1 $HLOCK# $HLOCK#
$DC#
1 $DC#
ACER
TAIPEI TAIWAN R.O.C
Title
370P/J (M1521 CPU TO PCI BRIDGE)
Size Document Number REV
A3 96149 SC
Date: February 12, 1997 Sheet 2 of 25
3.3V
6 MD[0..63]
MD[0..63]
M MM M M M M M M M MM M M MM M M MM M M MM M M M MMMMMM MMMMM
D DD D D D D D D D DD D D DD D D DD D D DD D D D D D D D DD D DD D D
3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0 +5V
7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
1 1 2 2 2 2 1 1 1 1 1 2 2 2 1 1 1 1 1 2 2 2 2 1 1 1 2 2 1 1 1 2 2 2 2 3 3 3 3 3 3 3 3 3 3 3 3
7 9 0 2 4 6 3 7 1 5 1 7 9 9 4 6 7 8 9 0 4 4 5 3 3 3 5 5 8 1 5 6 8 9 0 2 2 8 0 0 1 0 0 0 0 9 0 0 9 1 9 2 0 1 1 1 1 1 1 1 1 1 1 2 U0
4 3 5 8 7 7 4 6 7 7 9 8 7 9 4 2 3 4 2 6 8 6 3 5 6 8 8 9 0 1 3 4 2 4 8 7 5 8 5 6 9 1 2 7 8 0 3 4 4 4 5 4 9 0 1 2 3 4 5 6 7 8 9 0
AD[0..31] AD[0..31] 4,8,17,20,21,24
MMMMMMMMMMM MMMMMMMMMMMMMMMM MMMMMMMMMM M 3 3 3 3 3 3 3 3 3 3 5 V V V VV V V V V V V V V V V
D D D D D D D DD D D D D DD D D D D D D D D D D DD D D DD D D D D D D D V V V V V V V VV V VS S S SS S S S S S S S S S S
3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0 S S S SS S S S S S S S S S S
MD38 163 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
MD39 MD38 AD0 RP42
152 MD39 AD0 15
+5V MD40 112 14 AD1 RASJ2 1 8 RAS#2 6
MD41 98 MD40 AD1
33 AD2 RASJ1 2 7 RAS#1 RAS#2
MD42 MD41 AD2 AD3 RASJ0 RAS#0 RAS#1 6
60 MD42 AD3 13 3 6 RAS#0 6
MD43 20 52 AD4 MWEJ0 4 5 MWE#0 6
MD44 MD43 AD4 AD5 MWE#0
77 MD44 AD5 32
MD45 56 12 AD6 SRN10
MD46 75 MD45 AD6 51 AD7 R98
MD47 54 MD46 AD7 11 AD8 RASJ3 1 2 RAS#3
R95
MD48
MD49
268 MD47
MD48
ALADDIN3 AD8
AD9
50 AD9
AD10 10R3
RAS#3 6
226 MD49 AD10 30
MGNTJ 1 2 MD50 207 10 AD11
MD51 195 MD50 AD11 49 AD12 RP43
10KR3 MD52 183 MD51 AD12 29 AD13 CASJ7 1 8 CAS#7
MD53
MD54
172 MD52
MD53
PCI & DRAM AD13
AD14 9 AD14
AD15
CASJ6
CASJ3
2 7 CAS#6
CAS#3
154 MD54 AD15 48 3 6
R45 MD55 143 47 AD16 CASJ2 4 5 CAS#2
REQ#1 1 2 MD56 MD55 AD16 AD17
100 MD56 AD17 27
MD57 79 7 AD18 SRN10
10KR3
R129
MD58
MD59
40
39
MD57
MD58
M1521 AD18
AD19 46
26
AD19
AD20 CASJ5 1
RP41
8 CAS#5
GNT#1 MD60 MD59 AD20 AD21 CASJ1 CAS#1
1 2 18 MD60 AD21 6 2 7
MD61 37 MD61 AD22 45 AD22 CASJ4 3 6 CAS#4
10KR3 MD62 16 25 AD23 CASJ0 4 5 CAS#0
MD63 55 MD62 AD23 66 AD24
MD63 AD24 44 AD25 SRN10 CAS#[0..7] 6
AD25
133 MPD0 AD26 24 AD26
123 MPD1 AD27 4 AD27
142 23 AD28
113 MPD2 AD28 3 AD29
132 MPD3 AD29 22 AD30
MPD4 AD30 AD31
124 MPD5 AD31 2
134 MPD6
122 MPD7 CBEJ0 31 CBE#0
R R 28 CBE#1
285 R R R R R R A A CBEJ1 8 CBE#2
32K A A A A A A S S CBEJ2
5 CBE#3
S S S S S S J J CBEJ3
J J J J J J 6 7
0 1 2 3 4 5 / / D 5 CBE#[0..3] CBE#[0..3] 4,8,17,21
/ / / / / / S S P P E F P V
7 32K2 M C C C C C C C C S S S S S S C R M M S H H G G G G R R R R L S T I V R C S
WM M M M M M A A A A A A A A C C C C C C A A R GP R E L O N N N N E E E E O T R R S A L U
E A A A A MMMMMMMMA A S S S S S S S S S S S S S S S S E N R S RP D L T T T T Q Q Q Q C O D D E M K V V V V S +5V
J A A B B A A A A A AA A 1 1 J J J J J J J J J J J J J J J J Q T I T RA A D J J J J J J J J K P Y Y L E I S S S S P
0 0 1 0 1 2 3 4 5 6 7 8 9 0 1 0 1 2 3 4 5 6 7 0 1 2 3 4 5 0 0 J J O J J R J J 0 1 2 3 0 1 2 3 J J J J J J N S S S S J 1
1521-27/B R99
2 2 2 2 2 3 2 2 2 2 2 2 3 3 2 1 1 1 1 1 1 1 1 1 1 1 9 1 1 1 1 3 3 3 2 9 9 6 6 6 7 7 7 6 6 7 7 8 9 8 8 8 8 9 3 3 3 3 3 10KR3
1 6 2 8 4 0 8 6 4 2 8 4 0 0 6 4 5 3 6 3 4 2 6 2 1 0 6 7 8 7 8 2 2 2 2 3 2 5 4 8 0 2 4 7 9 1 3 5 1 8 7 9 6 0 2 2 2 2 2
MWEJ0 9 0 0 0 0 1 1 1 1 1 2 2 3 2 2 1 1 1 1 0 0 0 0 1 0 9 1 1 0 0 7 5 6 3 1 2 3 4 8
2
+5V
RP14
GNT#3 1 10
REQ#3 2 9 INTD# 4,21
SERR# INTC# INTD#
3 8 INTC# 4
GNT#2 4 7 INTB# INTB# 4
M M 5 6 INTA#
8 7 6 5 8 7 6 5 8 7 6 5 +5V INTA# 21
R G
RP44 RP46 RP45 E N SRP4K7 +5V
SRN10 SRN10 SRN10 Q T RP16
$P21CLK 7
J J 1 10
FRAME# 4,8,17,21 TRDY# 2 9 CBE#0
1 2 3 4 1 2 3 4 1 1 2 3 4 DEVSEL# FRAME# IRDY# 3 8 REQ#0
R110 IRDY# DEVSEL# 4,8,17,21 FRAME# 4 7 GNT#0
MM M MMM MMMM IRDY# 4,8,17,21
MAA0 A A A A A A 10R3
1 A A AA TRDY# 5 6 LOCK#
6 MAA0 TRDY# 4,8,17,21 +5V
6 MAA1 MAA1 2 3 4 5 6 7 R109 8 9 1 1 STOP# STOP# 4,17,21
2 10R3 0 1 C C C C C C C C LOCK# SRP4K7
REQ#3 LOCK#
A A A A A A A A
2 S S S S S S S S R R R R REQ#2 +5V
MA[2..11] J J J J J J J J A A A A REQ#1 RP15
6 MA[2..11] REQ#1 21
6 MAB0 0 1 2 3 4 5 6 7 S S S S REQ#0 STOP# 1 10
6 MAB1 J J J J GNT#3 DEVSEL# 2 9
0 1 2 3 GNT#2 17,21 PERR#
PERR# 3 8 CBE#1
GNT#1 REQ#2 4 7 CBE#3
GNT#0 GNT#1 21
5 6 CBE#2
REMOVE BUS BRANCH:PRASJ[0..5] PHOLD# +5V
PHLDA# PHOLD# SRP4K7
PAR PHLDA#
PAR 4,8,17,21
8 MREQJ
PCIRST# ACER
24 PCIRST# SERR#
4 SERR# TAIPEI TAIWAN R.O.C
Title
370P/J (M1521 PART2)
Size Document Number REV
A3 96149 SC
Date: February 12, 1997 Sheet 3 of 25
3.3V
8 $23STP#
8 $1523INTR
1 $IGNNE#
1 $A20M#
1 $FERR# $1523SMI# 8
1,24 $CPURST IRQ8# $1523INIT 8
13 EXTSW# SIRQI IRQ8# 9
1 $NMI 1 SIRQI 14
23 PWRGOOD R12
7 $ALA14M
10KR3 KBCS#
KBCS# 10,24
IRQ1 10
IRQ1
2 P P IOCS16# 13
2 U U MEMCS16# 13
3 L L SBHE#
1 BALE SBHE# 13
U L L BALE 13
S R11 L L RTCROMCS#
4K7R3 3 RTCROMCS# 9,13,24
B 2 SYSCLK
+5V TC SYSCLK +5V
C TC 11,24
K 2 REFRESH# 13
REFRESH#
3.3V 2 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1
5 0 5 2 0 7 4 8 5 3 0 8 5 2 4 6 5 4 1 5 6 5 6 5 5 5 5 5 4 1 1 4 4 5 5 5 5 5 8 0 9 U32 R88
3 8 6 0 5 2 0 2 7 4 4 2 2 6 1 6 0 9 3 7 8 1 7 2 6 5 4 1 0 9 6 5 5 4 4 3 2 1 9 7 6 2 8 3 6 1
16,24 SPKR SPKR PULLL2 1 2
24 SPLED
SPLED 3 V V V V V V VV V V V V VV U U U O P N ER F A I I S S C R R S S M K K K I MS B RS T R 10KR3
V C C C C C C SS S S S S SS S S S S WM X S E 2 GN T M P T T I I S B B B O1 B A T Y C E
C C C C C C SS S S S S SS B B B C GI T T R 0 NT P I U C C R R C D C I 1 6 H L CS F
63 C P P 1 SD R M NR C J R 3 3 Q Q L A L N 6 J E E RC S 169
AD[0..31] SPKR L 1 1 4 WR J J E L / S 2 2 I I K T K H J J O L H NOWSJ 0WS# 11,13
AD[0..31] 64 SPLED K 1 0 M / V J K A T K K I A / / M K J IOCHKJ 160 IOCHK# 13
A J P I O / K I C 159 R49
AD31 73 P / I I B R S XDIR 173 XDIR 13,24 23USBCK 1 2
AD30 74 AD31 I A C R C Q J AEN 172 AEN 11,13,15
AD30 C P C Q S 1 IOCHRDYJ IOCHRDY# 11,13
AD29 75 AD29 R I S 8 J MEMWJ 27 MEMWJ 10KR3
AD28 76 E C J J 24 MEMRJ
AD27 77 AD28 Q G MEMRJ 180 IORJ
AD27 J N IORJ
AD26 78
AD26 T IOWJ
178 IOWJ
AD25 79 176
AD24 80 AD25 SMEMRJ/LMEGJ 174 R169
AD23 AD24 SMEMWJ/RTCAS RTCAS 9 PULLL3
83 AD23 DACKJ0/DMAACKJ 47 DACK#0 11,15 1 2
AD22 84 48
AD21 85 AD22 DACKJ1/DMAREQ DACK#1 11,15 10KR3
AD21 DACKJ2/DACKOJ 204 DACK#2 11
AD20 86 AD20 184
AD19 87 DACKJ3/PCSJ 28 DACK#3 15
AD18
AD17
88
89
AD19
AD18
ALADDIN3 DACKJ5/DAK_SEL0
DACKJ6/DAK_SEL1
32
36
AD16 90 AD17 DACKJ7/DAK_SEL2 25
AD15 100 AD16 DREQ0 189 DRQ0 11,13,15
AD15 DREQ1 DRQ1 11,13,15
AD14 101 AD14 DREQ2 166 11,13
AD13 102 186 DRQ2 R91
AD12
AD11
103
106
AD13
AD12 PCI-ISA BRIDGE DREQ3
DREQ5 30
34
DRQ3
DRQ5
13,15
13 IORJ 1 2 IOR# 10,11,13,15,24
AD10 AD11 DREQ6 DRQ6 13 33R3
107 38
AD9
AD8
108
109
AD10
AD9
& DREQ7
IRQ3
202
200
IRQ3
IRQ4
DRQ7
IRQ3
13
11,13,15,21 IOWJ 1
R48
2
AD7 AD8 IRQ4 IRQ5 IRQ4 11,13,15,21 IOW# 10,11,13,15,24
111 198
AD6 112 AD7
AD6
IDE IRQ5
IRQ6
196 IRQ6 IRQ5
IRQ6
11,13,15,21
11,13,15,21 33R3
R223
AD5 113 AD5 IRQ7 194 IRQ7 IRQ7 11,13,15,21
AD4 114 164 IRQ9 MEMRJ 1 2
AD3 AD4 IRQ9 IRQ10 IRQ9 11,13,15,21 MEMR# 9,13
115 AD3 IRQ10 11 IRQ10 11,13,15,21
AD2 116 13 IRQ11 33R3
AD1 117 AD2 IRQ11 155 IRQ12 IRQ11 11,13,15,21 R221
AD0 118 AD1 IRQ12/MDATA
22 IRQ14 IRQ12 10,13,21 MEMWJ 1 2
21 INTA# INTA#
INTB#
67 AD0
INTAJ_MI
M1523 IRQ14
IRQ15 20 IRQ15
SD0
IRQ14
IRQ15
13,14,21
11,13,14
33R3
MEMW# 9,13
3 INTB# 68 INTBJ_S0 XD0 171
3 INTC# INTC# 69 170 SD1
INTD# 70 INTCJ_S1 XD1 168 SD2
3,21 INTD# FRAME# INTDJ_S2 XD2
3,8,17,21 FRAME# 92 FRAMEJ XD3 167 SD3
3,8,17,21 IRDY# 93 165 SD4
IRDY# TRDY# 94 IRDYJ XD4 163 SD5
3,8,17,21 TRDY# DEVSEL# 95 TRDYJ XD5 162 SD6
3,8,17,21 DEVSEL# STOP# 96 DEVSELJ XD6 161 SD7
3,17,21 STOP# SERR# STOPJ XD7
3,17,21 SERR# 97 SERRJ SD15 42 SD15
3,8,17,21 PAR PAR 98 PAR SD14 41 SD14
CBE#3 81 39 SD13
CBE#2 91 CBEJ3 SD13 37 SD12
CBE#1 99 CBEJ2 SD12 35 SD11
CBE#0 CBEJ1 SD11 SD10
110 CBEJ0 SD10 33
65 PHLDAJ SD9 31 SD9
CBE#[0..3] 66 29 SD8
CBE#[0..3] 71 PHOLDJ SD8 5 SA0
PCICLK SA0 4 SA1
SA1 SA2
14 VDD/VBAT SA2 3
I I I I SD[0..15] 9,10,11,13,15
PHLDA# I I I I I I I I D D D D
PHLDA# PHOLD# D D D D D D I I I I I I I I I I D D I I I I I I E E E E
PHOLD# $P23CLK E E E E E E D D D D D D D D D D I I E E D D D D D D P P S S
7 $P23CLK _ _ _ _ _ _ E E E E E E E E E E D D I I E A A E E E C C C C L L L L L L L S S S S S S S SS S
D D D D D D _ _ _ _ _ _ _ _ _ _ R R OO R K K _ _ _ S S S S A A A A A AA A A A A A A A AA A SS S S SS S
1 1 1 1 1 1 D D D D D D D D D D Q Q WR D J J A A A 1 3 1 3 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 AA A A AA A
3.3V 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 0 1 J J Y 0 1 1 2 0 J J J J 3 2 1 0 9 8 7 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3
M1523
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2
3 3 3 2 2 2 2 1 2 2 2 2 2 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 5 8 0 2 8 9 1 3 7 7 7 8 8 8 8 9 9 9 9 9 9 0 0 0 0
5 2 0 8 6 4 2 9 1 3 5 7 9 1 3 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 5 7 9 1 5 7 8 0 2 3 5 7 9 1 3 5 7
C175
SCD1U S S S S S S S S S SS S S S
D D D D D D D D D D D D D D D D A A A A A A A A A AA A A A
S S S S S S S S S S S S S S S S 1 1 1 1 1 1 1 9 8 7 6 5 4 3
D D D D D D D D D D D D D D D D S 6 5 4 3 2 1 0
1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0 A
5 4 3 2 1 0 1 SA[0..16] 8,9,10,11,13,15
SA[0..16]
L L L L L L L 7
A A A A A A A
2 2 2 2 1 1 1 SA17 13
14 DSD[0..15] 3 2 1 0 9 8 7 13
DSD[0..15] SA18
LA[17..23] SA19 13
LA[17..23] 13
IDE_DRQ0 ACER
14 IDE_DRQ0 IDE_DRQ1 IDESCS3J
14 IDE_DRQ1 IDEIOWJ IDESCS1J IDESCS3J 14 TAIPEI TAIWAN R.O.C
14 IDEIOWJ IDEIORJ IDEPCS3J IDESCS1J 14
14 IDEIORJ IDEPCS3J 14 Title
14 IDERDY IDERDY IDEPCS1J 14
IDE_DACK0# DSA0 IDEPCS1J 370P/J (M1523 PCI TO ISA & IDE CONTROLLER)
14 IDE_DACK0# DSA0 14
14 IDE_DACK1# IDE_DACK1# DSA2 DSA2 14 Size Document Number REV
14 DSA1 DSA1 A3 96149 SC
Date: February 12, 1997 Sheet 4 of 25
## ADD CX1,CX2,CX7,CX8,CX9
1 $BE#[0..7]
4 1 6 9 1 2 2 5 6 7 7 U49 4 1 6 9 1 2 2 5 6 7 7 U51
1 5 5 1 4 1 0 7 4 1 0 7 1 5 5 1 4 1 0 7 4 1 0 7
$CPUD[0..63] 1,2
3.3V
3.3V R212
R220 $TAG[0..7] 2 CS2
1 2
1 2
U50 10KR3
0R3 1 28
26 A14 VCC 19 $TAG7
$CPUA5 10 A13 D7 18 $TAG6
$CPUA6 9 A0 D6 17 $TAG5
A1 D5 3.3V R216
$CPUA7 8 A2 D4 16 $TAG4
$CPUA8 7 15 $TAG3 1 2 $C_MODE MODIFICATION: $C_MODE PULLED UP TO 100K
$CPUA9 6 A3 D3 13 $TAG2
$CPUA10 A4 D2 $TAG1 100KR3 PULL UP: PENTIUM BURST MODE
5 A5 D1 12
$CPUA11 4 A6 D0 11 $TAG0 PULL LOW: CYRIX LINEAR BURST MODE
$CPUA12 3 A7
$CPUA17 2 A12
$CPUA13 25 A8 20 $AMSTATE#
$CPUA14 24 CS1* 22
$CPUA16 A9 OE*
23 A11 WE* 27 $TWE# 2
$CPUA15 21 A10 GND 14
S32K8-15
R100
$H_ZZ 1 2 $AMSTATE#
$AMSTATE# 8
DUMMY-R3
ACER
3.3V R210 TAIPEI TAIWAN R.O.C
1 2 FTNC Title
10KR3 370P/J (256KB CACHE)
Size Document Number REV
A3 96149 SC
Date: February 12, 1997 Sheet 5 of 25
3.3V
3.3V CN21
145
1 2
3.3V MD0 3 4 MD32
MD1 5 6 MD33
C271 MD2 7 8 MD34
SC4D7U16V6ZY MD3 9 10 MD35
C268 C225 C224 C234 C244 11 12
SC4D7U16V6ZY SCD1U SCD1U SCD1U SCD1U MD4 13 14 MD36
MD5 15 16 MD37
3 MA[2..11] MA[2..11] MD6 17 18 MD38
MD7 19 20 MD39
3 MD[0..63] 3.3V 21 22
MD[0..63] CAS#0 CAS#4
23 24
CAS#1 25 26 CAS#5
27 28
CN20 C261 C186 C107 C241 3 MAB0 MAB0 29 30 MA3
145 SC4D7U16V6ZY SCD1U SCD1U SCD1U 3 MAB1 MAB1 31 32 MA4
MA2 33 34 MA5
1 2 35 36
MD0 3 4 MD32 MD8 37 38 MD40
MD1 5 6 MD33 MD9 39 40 MD41
MD2 7 8 MD34 MD10 41 42 MD42
MD3 9 10 MD35 3.3V MD11 43 44 MD43
11 12 45 46
MD4 13 14 MD36 MD12 47 48 MD44
MD5 15 16 MD37 MD13 49 50 MD45
MD6 17 18 MD38 CX25 CX26 CX27 CX28 MD14 51 52 MD46
MD7 19 20 MD39 SCD1U SCD1U SCD1U SCD1U MD15 53 54 MD47
21 22 55 56
CAS#0 23 24 CAS#4 57 58
CAS#1 25 26 CAS#5 ## ADD NEW COMPONENT 59 60
27 28
MAA0 29 30 MA3
3 MAA0 MAA1 31 32 MA4
3 MAA1 MA2 MA5
33 34 61 62
35 36 63 64
MD8 37 38 MD40 65 66
MD9 39 40 MD41 3 MWE#0 MWE#0 67 68
MD10 41 42 MD42 3 RAS#2 69 70
MD11 43 44 MD43 71 72
45 46 3 RAS#3 73 74
MD12 47 48 MD44 75 76
MD13 49 50 MD45 77 78
MD14 51 52 MD46 79 80
MD15 53 54 MD47 81 82
55 56 MD16 83 84 MD48
57 58 MD17 85 86 MD49
59 60 MD18 87 88 MD50
MD19 89 90 MD51
91 92
MD20 93 94 MD52
61 62 MD21 95 96 MD53
63 64 MD22 97 98 MD54
65 66 MD23 99 100 MD55
MWE#0 67 68 101 102
69 70 MA6 103 104 MA7
3 RAS#0 71 72 MA8 105 106 MA11
3 RAS#1
73 74 107 108
75 76 MA9 109 110
77 78 MA10 111 112
79 80 113 114
81 82 CAS#2 115 116 CAS#6
MD16 83 84 MD48 CAS#3 117 118 CAS#7
MD17 85 86 MD49 119 120
MD18 87 88 MD50 MD24 121 122 MD56
MD19 89 90 MD51 MD25 123 124 MD57
91 92 MD26 125 126 MD58
MD20 93 94 MD52 MD27 127 128 MD59
MD21 95 96 MD53 129 130
MD22 97 98 MD54 MD28 131 132 MD60
MD23 99 100 MD55 MD29 133 134 MD61
101 102 MD30 135 136 MD62
MA6 103 104 MA7 MD31 137 138 MD63
MA8 105 106 MA11 139 140
107 108 141 142
MA9 109 110 143 144
MA10 111 112
113 114 146
CAS#2 115 116 CAS#6 3.3V
CAS#3 117 118 CAS#7 SDIMM144
119 120
MD24 121 122 MD56
MD25 123 124 MD57 C260 C257 C270 C272
MD26 125 126 MD58 SC4D7U16V6ZY SCD1U SCD1U SCD1U
MD27 127 128 MD59
129 130
MD28 131 132 MD60
MD29 133 134 MD61 3.3V
MD30 135 136 MD62
MD31 137 138 MD63
139 140
141 142 C130 C259 C264 C269
143 144 SC10U16V SCD1U SCD1U SCD1U
146
SDIMM144
3 CAS#[0..7] CAS#[0..7]
ACER
TAIPEI TAIWAN R.O.C
Title
370P/J (DIMM SOCKET)
Size Document Number REV
A3 96149 SC
Date: February 12, 1997 Sheet 6 of 25
3.3V 3.3V
1 1
R180 R179
22KR3 22KR3
2 3.3V 2 3.3V
FOR CY2263
1 1 $BF1 $BF2
R105 R106 S0 S1 CLOCK
SW3 10KR3 10KR3 1 1 1.5X +5V +5V
1 8 FS1 0 0 50MHZ 1 0 2X
2 7 2 2 0 1 60MHZ 0 1 3X
3 6 FS0 1 0 66.6MHZ 0 0 2.5X +5V U47A +5V 1 U47B
$BF1 4 0
4 5 1 1 33MHZ R192 R201
$BF0
14 VCC P Q 5 1 2 CLK7M 10 14 VCC P Q 9 1 2 CLK4M 8
KHS04 2 D R 12 D R
33R3 33R3 ##
KBD14M 3 11
CLK CLK
Q 6 Q 8
7 C 7 C
3.3V GND L GND L
SSHCT74 SSHCT74
L8 1
1 3
1 2
MLB321611 C87 C101 C99 C85 C86 C100 +5V +5V
SC10U16V SC100P SCD1U SCD1U SCD1U SCD1U
+5V 1
1 U41D R59
4 0R3
9 8 2 U39 R92
INVAPMSEL0 C83 R90
1 VDD CPU0 6 1 2 $CPUCLK 1
8 VDD 7 1 2 R89 5
7 SSHCT04 3 2 14 CPU1 33R3 $L2CLK1
VDD CPU2 9 1 2 $L2CLK2 5
SC10P X2 26 10 33R3
XTAL4P-14.318MHZ 32 VDD CPU3 33R3
VDD CPU4 12
C84 2 13 R87
4 1 XIN CPU5 R61
3 XOUT CPU6 17 1 2 $21CLK 2
$AMSTATE 5 21 1 2 R60
SC10P 8 $AMSTATE CPUEN1 PCI0 $P21CLK 3
19 22 R64 1 33R3 2 4
3.3V 18 CPU-PCIEN PCI1 24 1 2 33R3 R62 $P23CLK
U34A SEL PCI2 R63 33R3 1 $VGACLK 17
1 15 S1 PCI3 25 2 $CARDCLK 21
4 1 16 27 33R3 1 2
S0 PCI4 33R3 $P7101CLK 8
4 VSS EPCI 28
FS1 2 3 11 30 R67 33R3
20 VSS USB-CLK 31 1 2
3.3V 23 VSS IOCLK R167 $P24M 11
VSS REF0 34
7 SSLVC125 1 U34B 29 33 33R3 1 2
4 4 VSS REF1 $AUDIO14M 15
CY2263 33R3
FS0 5 6 R163
1 2 $ALA14M 4
1 1
7 SSLVC125 RX8 RX9 33R3
22KR3 22KR3 R68
1 2 17
3.3V $G14.318M
2 2
33R3 KBD14M
R166
1 2
C105 33R3
SC47P
R96
1 2
+5V 2 1
2MR5 X3
+5V CAN32768
1 U19C 1 U19A 3 4
4 4
C223 5 6 1 2
SCD1U
7 SSHC14 7 SSHC14 ## REMOVE R65,R178,R182,R181,R66 PAD
+5V
1 U19D
4
9 8 32K1 8
32K1
7 SSHC14 +5V
1 U19B
4
3 4 32K2
32K2 3,17
7 SSHC14 ACER
TAIPEI TAIWAN R.O.C
Title
370P/J (CY2263 CLOCK GENERATOR)
Size Document Number REV
A3 96149 SC
Date: February 12, 1997 Sheet 7 of 25
+5V +5V 3.3V
1 U43C 1 1 U13C
4 4 0 CLOSE TO U34
$7101STP# 9 R107
1 U26B 8 9 8 1 2
4 4 +5V 3.3V 10 $STPCLK# 1
4 $23STP# 47R3
LLED# 5 6 16 7 SSHCT08 7 SOLCX125M
LED#
STANDBY# +5V
VR_U/D# 19
7 SSHC125 TH_DQ_VGA TH_DQ_VGA 2
PWR_SW# 23 16
TH_COM PWR_SW# DISPLED#
BLVR# 19 1 $CPUSMI# EXCACD# TH_COM 2 U26C
EXCACD# 24 1 1
7 $P7101CLK 9,13 4 0
XSA17 R122
TPX1 TPX2 XSA16 9,13
4 LLED# 9 8 1 2 19
TP-1 TP-1 SA16 PLED#
1 470R3
## REMOVE U15 PAD, CIRUIT MODIFY 8 1 7 5 1 0 2 9 6 3 1 8 7 7 7 7 7 7 7 U20 7 SSHC125
9 8 6 9 1 0 6 0 3 8 9 1 0 9 8 7 5 4 3 2
P S V VV V V V V V V V G G GG G G G G +5V
C M D DD D D S S S S S P P P P P P P P
AD0 37 I I D DD D D S S S S S I I I I I I I I
AD1 AD00 C J 5 5 5 3 3 O O OO O O O O
36 AD01 L C C C C C C C C
U36 AD2 35 AD02 K 7 6 5 4 3 2 1 0 GPIOB7 88 $7NDSTP#
AD24 3 D0 Q0 2 ID_CLK 19
AD3 34 AD03 ( ( ( ( ( GPIOB6 85 AMSTATE
AD25 4 5 AD4 33 V S E E D 87 R183
AD26 7 D1 Q1 6 FLASH_ON 9,13 AD04 C E X J O GPIOB5 $CPUINIT 1
D2 Q2 3_MODE 12,14 AD5 32
AD05 S T T E C GPIOB4
86 PWR_SW# 1 2
AD27 8 D3 Q3 9 2 AD6 31 J U S C K 84 2
AD28 13 12 TH_CLK AD7 30 AD06 ) P WT J GPIOB3 83 $BRDY# TPX5 47KR3
D4 Q4 TH_RST# 2 AD07 ) ) J ) GPIOB2 $1523INIT 4 TP-1 R194
AD29 14
D5 Q5
15
DISABLELED 16 AD8 28
AD08 ) GPIOB1
82
$1523SMI# 4
AD30 17
D6 Q6 16 ENAUDIO 16 AD9 27 81 4 17 STANDBY# 1 2
AD31 18 19 AD10 25 AD09 GPIOB0 $1523INTR STANDBY#
D7 Q7 AD11 24 AD10 71 10KR3
1 20 +5V AD11 GPIOA7 TH_DQ 2 R187
OC VCC AD12 23 AD12 (SPKR)GPIOA6 70
BDATA 13
GPIOWF1 11 10 AD13 22 69 ID_DATA 1 2
G GND AD14 21 AD13 GPIOA5 68 BATCNTL 13
SSHCT373 AD15 20 AD14 GPIOA4 67 ID_DATA 19 R93 10KR3
AD16 AD15 GPIOA3 DISABLE 23 1 VEEVR#
9 AD16 GPIOA2 66 2 VEEVR# 19
AD17 8 AD17 GPIOA1 65 GPIOWF1
AD18 7 AD18 GPIOA0 64 GPIORF1# 0R3
AD19 6 GPIORF1# 20,24
AD20 AD19
5 AD20
AD21 4 AD21 CLK32 62 32K1 7
AD22 3 61 32K1
AD23 2 AD22 SEL1 60 AAPMSEL0 PHOLD#
AD24 AD23 SEL0 DISPLAY
98 AD24 DISPLAY 58 DISPLAY 20
AD25 97 57 ENBL +5V
+5V AD26 AD25 CCFT ENBL 20 U5D
96 AD26 FPVEE 56 ENAVEE 17 1
AD27 95 AD27 4
RP12 AD28 94 D P H S STANDBY# 12
FDDIN# 1 10 AD29 93 AD28 F E S W OU S 11
12 FDDIN# LIB/MH# GPIORF1# AD30 AD29 R I T V C C C C U R C T S A P AAPMSEL0 INVAPMSEL0
23 LIB/MH# 2 9 92 AD30 A R R S B B B B S GO K T V L C S SK 13
3 8 HOTKEY# AD31 91 AD31 M D D E E E E EP R OV R E A D L L P P C D L QC
4 7 VSW1 E Y Y L J J J J A S OS R T Y T D B B W S R R E WT 1 7 SSHCT32
3 MREQJ 5 6 VSW33,4,17,20,21,24 AD[0..31] J J J J 0 1 2 3 R T D WI C J E S J J R 2 T QD OL ## CIRUIT MODIFY RX7
+5V M7101 +5V 10KR3
SRP10K 1 1 1 1 2 1 1 9 1 3 4 4 4 4 4 4 4 4 4 4 5 5 5 5 5 5
2 3 4 5 9 7 0 9 6 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5
C 2
3,4,21 P O 16 +5V
FRAME# LLED# SPKR_OFF U43B
3,4,21 IRDY# WV 1
3,4,21 R E 16 4
TRDY# SLED 4
3,4,21 DEVSEL# G R DRQ2 11,13 VSW1 19
3,4,21 CBE#0 O _ 6
3,4,21 CBE#1 O S BT_SENSE 23 5 VSW3 19
3,4,21 CBE#2 D W 6377_BIU# 23
7 SSHCT08
(M71XX CONFIGURATION) 3,4,21 CBE#3 6377_BBL2# 23
3,4,17,21 PAR +5V 6377_BBL1# 23
23 PWRGOOD
20 COVER_SW +5V
R196 HOTKEY# HOTKEY# 10
DISPLAY 1 2 +5V 1 U43D
1 U43A +5V 4
4K7R3 4 $7101STP# 12
R193 11 RI1# 1 1 U38E 11 CCINTR CCINTR 19
ENBL 1 2 3 4 $1523INTR 13
21 RING_OUT# 2
4K7R3 10 11 IRQ8# 7 SSHCT08
R195 SSHCT08 IRQ8# 9
7
LLED# 1 2
7 SSHC14
4K7R3
U27
24 11 SD7 +5V
PWRGOOD# VCC AD7 SD6
23 PWRGOOD# 13 CS$ AD6 10
4 RTCAS RTCAS 14 9 SD5 1
RTCRW 15 AS AD5 8 SD4 R9
24 RTCRW R/W$ AD4
24 RTCDS RTCDS 17 DS 7 SD3 10KR3
G1 18 AD3 6 SD2
1 2 21 RST$ AD2 5 SD1 2
22 RCL$ AD1 4 SD0 DX2
GAP-OPEN 20 EXTRAM AD0 19 2 1 IRQ8#
BC INT$ IRQ8# 4,8
2 23
X1 SQW 1 S1N4148
MOT RTCIRQ8#
3 X2 VSS 12
1 VSS 16
BT1
BH-12 BQ3285E TPX3
2 CX31 X1 CX30 TP-1
SC3P50V3KN
1 2 SC3P50V3KN
XTAL-32.768KHZ
HDD+5V
C265
SCD1U
4 SA[0..15]
U52
SA0 20 8
SA1 19 A0 VCC
SA2 18 A1 21 SD0
SA3 A2 DQ0 SD1
17 A3 DQ1 22
SA4 16 23 SD2
SA5 15 A4 DQ2 25 SD3
SA6 14 A5 DQ3 SD4
A6 DQ4 26
SA7 13 27 SD5
SA8 3 A7 DQ5 SD6
A8 DQ6 28
SA9 2 29 SD7
SA10 31 A9 DQ7
SA11 A10
1 A11
SA12 12 A12 WE# 7 MEMW# MEMW# 4
SA13 4
A13
+5V SA14 5
U45C SA15 11 A14 24
1 A15 VSS
4 10 BIOSVPP
8 XSA16 A16
4 RTCROMCS# RTCROMCS# 9 8 XSA17
8 30 CE VPP 9
13 DISROM DISROM 10 MEMR# 32 6
4 MEMR# OE A17
7 SSHCT32 28F020-1 C266
SCD1U
3
2 Q8
BIOSCE# S2N3906
1
U52 IS TSOP PACKAGE,
MUST BE INSTALL. 1 +12V
R222
10KR3
2
3
FLASH_ON 2 Q9
8 FLASH_ON RN1424
1
ACER
TAIPEI TAIWAN R.O.C
Title
370P/J (RTC AND BIOS)
Size Document Number REV
A3 96149 SC
Date: February 12, 1997 Sheet 9 of 25
+5V
+5V
K K K K K K K K K K K K K K K K
4,9,11,13,15 SD[0..7] C C C C C C C C C C C C C C C C RP17
SD[0..7] MCLK
O O O O O O O O O O O O O O O O 1 10
L L L L L L L L L L L L L L L L MDATA 2 9
1 2 3 4 5 6 7 8 9 1 1 1 1 1 1 1 XCLK 3 8
0 1 2 3 4 5 6 XDATA 4 7
+5V 5 6 SW2
+5V +5V 1 8
4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 U16 SRP10K 2 7
8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3
3 6
P P P P P P PP P PP P P PP P 4 5
RP34 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
KROW1 1 10 KROW8 49 P37 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 P20 32 HOTKEY# 8 KHS04
KROW2 2 9 KROW5 KROW7 50 31 HOTKEY#
KROW3 KROW6 KROW6 P36 P21
3 8 51 P35 P22 30
KROW4 4 7 KROW7 KROW5 52 P34 P23 29
5 6 KROW8 KROW4 53 28
KROW3 P33 P24
54 P32 P25 27 CLLED# 16
SRP10K KROW2 55
P31 P26
26
NLLED# 16
KROW1 56
P30 P27 25
SLLED# 16
57 24
TDATA
TCLK
58
59
VCC
P61/CNTR0
P
4
VSS
XOUT
23
22
CLK7M 7 TRACKSTICK CONN
P60/INT5/OBF2 5 XIN
SD7 60 / 21 +5V +5V
SD6 61 DQ7 I P40 20
SD5 62 DQ6 P B P41/INT0 19 ST+5VA 1
DQ5 5 P P P F P P RESET#
SD4 63 DQ4 3 5 P P 4 4 0 4 4 CNVSS 18 R215
SD3 64 / 2 5 5 7 6 # 4 3 17 XDATA PCIRST# 24 10KR3
DQ3 S / 1 0 / / / / / P42/INT1 +5V CN19 +5V
R S / / I I O O I
D D D WR C D C T R N N B B N 11 1 Y-COOD 2
QQQR D S AY L X X T T F F T 1 12 2 X-COOD 1
2 1 0 # # # 0 # K D D 4 3 1 0 2 R74 13 3 R197
M38802M2 10KR3 14 4 10KR3
1 1 1 1 1 1 1 STCLOCK
1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 15 5
2 16 6 2
SD2 XCLK 17 7 TDATA
SD1 IRQ1 4 18 8 TCLK
SD0 IRQ12 IRQ1 19 9
IOW# IRQ12 4 20 10
4 IOW# IOR#
4 IOR# MOLEX-CON10-2 C231
4 KBCS# SA2 SC47P C255
4 SA2 SC47P
7 FS1
7 FS0 CX40
7 $BF1
SC4D7U16V6ZY
7 $BF0
MDATA
MCLK
ST+5VA
CX41
C229
SCD1U SC1U16V5JX
CN15
KCOL16 1 30 KCOL4
KCOL15 2 29 KCOL3
+5V KCOL14 3 28 KCOL2
KCOL13 4 27 KCOL1
SW1 L5 KCOL12 5 26 KROW8
1 2 1 2 KCOL11 6 25 KROW7
KCOL10 7 24 KROW6
SPOLY100-1 MLB321611 KCOL9 8 23 KROW5
CN1 KCOL8 9 22 KROW4
8 KCOL7 10 21 KROW3
R1 150R3 L1 KCOL6 11 20 KROW2
MCLK 1 2 1 2 5 KCOL5 12 19 KROW1
MLB321611 3 13 18
R123 L2 1 Y-COOD 14 17
MDATA 1 2 1 2 2 9 X-COOD 15 16 STCLOCK
4
150R3 R113 L4 MLB321611 6 MOLEX-CONN30E
XDATA 1 12 2
150R3 MLB321611
L3 7 MINDIN6
XCLK 1 2 1 2
R112 150R3 MLB321611 KB BD CONN.
C167
SC47P
C166 C132 C160
C133 C168 SC47P SC4D7U16V6ZY SCD1U
SC47P SC47P
ACER
TAIPEI TAIWAN R.O.C
Title
370P/J (KB CONTROLLER)
Size Document Number REV
A3 96149 SC
Date: February 12, 1997 Sheet 10 of 25
+5V
+5V
SB: CHANGE MAX213 TO MAX3243
C164
U2
C163 SCD1U 28 26 C161
24 C1+ VCC
27 C162
C1- V+
1 C2+ V- 3
12 SCD1U 2 SCD1U
PD[0..7] SOUT1 C2- SCD1U
14 T1IN T1OUT 9 PSOUT1 12
P P PP P PP P RTS1# 13 10 12
DTR1# 12 T2IN T2OUT
11
PRTS1#
D D DD D DD D T3IN T3OUT PDTR1# 12
0 1 2 3 4 5 6 7 20 R2OUTB
ACK# SIN1 19 4 12
STROB# BUSYP DSR1# R1OUT R1IN PSIN1
BUSYP 12 18 R2OUT R2IN 5 PDSR1# 12
PE CTS1# 17 R3OUT R3IN 6 PCTS1# 12
4 IRQ[3..7] SLCT 8 RI1# RI1# 16 R4OUT R4IN 7 PRI1# 12
DCD1# 15 8
R5OUT R5IN PDCD1# 12
I I I I I 23 FORCEON
+5V R R R R R 22
SLCTIN# FORCEOFF#
QQ QQQ 21 INVALID# GND 25
3 4 5 6 7 INIT#
ERROR# MAX3243
24 RSTDRV AUTOFD#
1
0 9 9 9 9 9 9 9 9 9 9 8 8 8 8 8 8 8 8 8 8 7 7 7 7 U6
0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6
MI I V I I I S P P P P V P P P P A B P S S I E A
R R R D R RR T D D D D S D D D D C U E L L N R F
QQ D QQQB 0 1 2 3 S 4 5 6 7 K S / C I I R D
3 4 C 5 6 7 / / / / / D / / / / / Y WT N T / /
1 / WI T WR D M D M D / D / / / H D 75 DCD1#
4,13 0WS# CS1/ZWS A R N R P D S S R S R W A WS D D S DCD1
4,8 2 D I D K A K E A E 1 A T GT I S T 74 DSR1#
DRQ2 3 DRQ2 R T E O T C N T N I A A E R E R DSR1 73 SIN1
4 DACK#2 DACK2 A E X A H 0 E 1 T T P L B SIN1 RTS1#
4 TC 4 TC T G 0 / E / / RTS1/BADDRO 72
7 $P24M 5 E M A D 71 SOUT1
X1/OSC 0 T S E SOUT1/BOUT1/BOUT1/BADDR1 CTS1#
6 X2 CTS1 70
7 R T N 69 DTR1#
VSSC 1 R S DTR1/CFG1
SD7 8 B E 68 RI1#
SD6 D7 L RI1 SA15
9 D6 DCD2/A15 67
SD5 10 66
SD4 D5 DSR2/IRRX2/IRQ12
11 D4 SIN2/IRRX1 65
SD3 12 D3 RTS2/A14 64 SA14
SD2 13 63 SOUT2
SD1 14 D2 SOUT2/BOUT2/CFG0/IIRTX 62 SA13
SD0 15 D1 CTS2/A13 61 SA12
D0 DTR2/A12
4 IOW# 16 WR R12/A11 60 SA11
17 D 59
4 IOR# RD R VSSE
4 AEN 18 AEN A IRQ15/SIRQI1
58
IRQ15 4,13 SA[11..15] 4
SA9 19 D T 57
SA8 20 A9 R E IRQ11 56 IRQ11 4
4,9,10,13,15 SD[0..7] SA7 A8 V 1 IRQ10 IRQ10 4
21 A7 2 / IRQ9 55 IRQ9 4
SA6 22 / M 54 4
SA5 A6 P S DRQ0 DRQ0
23 A5 DACK0 53 DACK#0 4
SA4 24 D N E 52
SA3 A4 E F N DACK1 DACK#1 4
25 N / 1 D 51 4
A3 S D / R IOCHRDY IOCHRDY#
E R C A
M L 2 S T
T / 3 0 E
R A / / 0
D 1 D D S S /
S H R WW / R I R I R M
K D D D T GD S V I 1 M N A R V I S
A C R S A R A A T D S D D / T D T Q D Q E
A A A 1 H Q E T WK T T E I S L R PR E E 1 D 1 N
2 1 0 0 G 1 L A P O E A P R B E 0 D0 X 1 3 B 2 0 +5V
87336Q
2 2 2 2 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 5
6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0
+5V R141
SA2 1 2 RTS1#
SA1
SA0 C23 10KR3
RPM 14
SA10 INDEX# 14 SCD1U R140
MTR0# MTR0# 14 1 2 SOUT1
4 SA[0..10] DR1# 12 10KR3
12,14 DSKCHG DR0# 14 R139
4 DRQ1 MTR1# 12 SOUT2
12,14 HDSEL 1 2
14 RDATA#
12,14 10KR3
WRTPRT# R44
12,14 TRK0# 1 2 DTR1#
12,14 WGATE#
14 WDATA#
12,14 STEP# 10KR3
12,14 FDIR
RP27
AUTOFD# 1 8 PAUTOFD#
ERROR# 2 7 PERROR# PAUTOFD# 12
PERROR# 12
INIT# 3 6 PINIT# PINIT# 12
SLCTIN# 4 5 PSLCTIN# 12
PSLCTIN#
SRN33
RP30
SLCT 1 8 PSLCT 12
PE PPE PSLCT
2 7 PPE 12
ACK# 3 6 PACK# 12
STROB# 4 5 PSTROB# PACK#
PSTROB# 12 ACER
SRN33 TAIPEI TAIWAN R.O.C
Title
370P/J (NS87336 SUPER I/O)
Size Document Number REV
A3 96149 SC
Date: February 12, 1997 Sheet 11 of 25
+5V
FDDCHG
4 5 6 +5V
D7 11 PD[0..7]
RB731U U24
24 VCC B9 23 EXTDSKCHG
FDDDCHG 3 2 1 EXTINDEX# 2 B0 22 11
3 A9 21 DSKCHG C142
14 INDEX# A0 A8 EXTMTR1# MTR1# 11 SC150P C137 C141
11 DR1# 4 A1 B8 20
EXTDR1# 5 19 EXTFDIR SC150P SC150P
RP22 EXT3_MODE 6 B1 B7 18
PAUTOFD# B2 A7 FDIR 11 C136 C140
1 10 8,14 3_MODE 7 A2 A6 17 STEP# 11
PERROR# 2 9 PSLCT 8 16 EXTSTEP# SC150P SC150P
PINIT# PPE 11 HDSEL EXTHDSEL A3 B6 EXTWGATE#
3 8 9 B3 B5 15
PSLCTIN# 4 7 PACK# EXTWDATA# 10 14 11,14 C135 C139
5 6 11 B4 A5 WGATE# SC150P SC150P
14 WDATA# A4
1 OEA
SRP4K7 FDDRDY# 13 C134 C138 CN3
OEB SC150P SC150P
12 GND 26
QQST3384 PSTROB# 1
11 PSTROB#
11 PAUTOFD# PAUTOFD# 14
RP21 PPD0 2
PPD0 1 10 +5V PERROR# 15
PPD1 2 9 PPD4 11 PERROR#
PPD1 3
PPD2 3 8 PPD5 U1 PINIT# 16
PPD3 PPD6 11 PINIT# PPD2
4 7 24 VCC B9 23 4
5 6 PPD7 EXTRDATA# 2 22 PSLCTIN# 17
B0 A9 11 PSLCTIN# PPD3
14 RDATA# 3 A0 A8 21 5
SRP4K7 11,14 TRK0# 4 20 18
EXTTRK0# 5 A1 B8 19 PPD4 6
RP23 EXTWRTPRT# B1 B7
6 B2 A7 18 19
PD0 1 8 PPD0 11,14 7 17 PPD5 7
PD1 PPD1 WRTPRT# A2 A6
2 7 8 A3 B6 16 20
PD2 3 6 PPD2 9 15 PPD6 8
PD3 4 5 PPD3 10 B3 B5 14 21
11 B4 A5 PPD7 9
SRN33 1 A4 22
FDDRDY# 13 OEA PACK# 10
12 OEB 11 PACK# R114
GND 23
RP24 1 2 11
PD4 1 8 PPD4 QQST3384 11 BUSYP 24
PD5 2 7 PPD5 33R3 PPE 12
PD6 3 6 PPD6 11 PPE
25
PD7 4 5 PPD7 11 PSLCT 13
PSLCT
SRN33 +5V 27
+5V FDD5V 1
1 RX11 PRNT25-4-D
R115 +5V 10KR3 C146 C150
+5V FDDDCHG +5V 10KR3 U23 SC150P SC150P
1 U19E 1 U19F 1 8 2
4 4 GND OUT C145 C149
2 2 IN OUT 7
R21 R116 3 6 SC150P SC150P
FDDIN# IN OUT C165 C8
11 10 1 2 13 12 1 2 4
EN# OUT
5
SCD1U SC10U16V C144 C148
560KR3 100KR3 TPS2013D CN4 SC150P SC150P
7 SSHC14 C172 7 SSHC14 10
SCD1U C9 5 C143 C147
9 11 SC150P SC150P
FDDCHG 4 PRI1#
SCD1U 8 PDTR1# 11
PCTS1# 11
3 PSOUT1 11
FDD5V 7 PRTS1# 11
FDD5V 2
C10 6 PSIN1 11
CN5 1 PDSR1# 11
27 PDCD1# 11
11
SC680P
EXTINDEX# 1 14 RS232-9-4-D
2 15
3 16 EXTDSKCHG
C153 C156
EXTDR1# 4 17 SC680P SC680P
5 18 EXTMTR1#
C151 C154 C157
6 19 EXTFDIR SC680P SC680P SC680P
EXT3_MODE 7 20 EXTSTEP#
C158
EXTWDATA# 8 21 C152 C155 SC680P
R27 SC680P SC680P
FDDIN# 1 2 9 22
8 FDDIN#
330R3 10 23 EXTWGATE#
## CIRCUIT MODIFY 11 24
EXTRDATA# 12 25 EXTTRK0#
EXTHDSEL 13 26 EXTWRTPRT#
28 +5V
+5V 1 U5C
AMP-CONN26 FDD5V 1 U38C 4
4 FDDIN# 9
THIS CONN. IS BUILDED BY TOP VIEW, R119 8 FDDRDY#
WE COUNT THE PINS MUST MIRROR IT. 1 2 5 6 10
100KR3 7 SSHCT32
EXT. FDD CONN. 7 SSHC14 ACER
C7 TAIPEI TAIWAN R.O.C
SCD1U Title
370P/J (||PORT,SERIAL PORT,EXT. FDD)
Size Document Number REV
A3 96149 SC
Date: February 12, 1997 Sheet 12 of 25
HDD+5V HDD+5V HDD+5V HDD+5V
4,9,10,11,15 SD[0..15]
HDD+5V HDD+5V
GF1
SD5 35 1 4 SA[0..16]
RP47
SD6 36 A1 B1 2 SD0 1 10
A2 B2 RP49
SD7 37 A3 B3 3 SD1 2 9 SD4
SD8 38 A4 B4 4 SA0 SD2 3 8 SD5 MEMR# 1 10
SD9 39 A5 B5 5 SA1 SD3 4 7 SD6 MEMW# 2 9 EXTSW# 4
SD10 40 A6 B6 6 SA2 5 6 SD7 IOR# 3 8
SD11 41 A7 B7 7 SA3 IOW# 4 7 IOCHK# 4
SD12 42 8 SA4 SRP10K 5 6 RSTDRV
SD13 43 A8 B8 9 SA5 HDD+5V HDD+5V
SD14 A9 B9 SA6 SRP10K
44 A10 B10 10
SD15 45 A11 B11 11 SA7
46 12 SA8
A12 B12 SA9
4 XDIR 47 A13 B13 13
23 PWRGOOD 48 A14 B14 14 SA10 RP50
8 FLASH_ON 49 A15 B15 15 SA11 SD8 1 10
9 DISROM 50 16 SA12 SD9 2 9 SD15 RP2
51 A16 B16 17 SA13 SD10 3 8 SD14 DRQ1 1 10
4 MEMW# A17 B17 SA14 SD11 SD13 4 DRQ1 DISROM DRQ0
4 MEMR# 52 A18 B18 18 4 7 2 9 DRQ0 4
4 LA20 53 19 SA15 5 6 SD12 4 DRQ3 3 8 DRQ5 4
A19 B19 SA16 DRQ3 DRQ2 DRQ6 DRQ5
4 LA21 54 A20 B20 20 4,8 DRQ2 4 7 DRQ6 4
55 21 SRP10K 5 6 DRQ7
4 LA22 56 A21 B21 22 SA17 4 HDD+5V HDD+5V DRQ7 4
4 LA23 57 A22 B22 23 SA18 4 SRP4K7
4 IRQ11 A23 B23 SA19 4
58 A24 B24 24 SBHE# 4
4 BALE 59 A25 B25 25 XSA16 8
60 26 8
61 A26 B26 27 XSA17 RP48 +5V
4 IOR# 62 A27 B27 28 MEMR# RTCROMCS# 4 SBHE#
4 IOW# A28 B28 1 10
4 AEN 63 29 MEMW# 4 LA19 2 9 LA23 RP4
64 A29 B29 30 SD0 3 8 LA22 1 10
4 IOCHRDY# 65 A30 B30 31 SD1 4 LA18 LA21 4 IRQ12
24 RSTDRV A31 B31 4 LA17 4 7 2 9
66 32 SD2 5 6 LA20 3 8
A32 B32 SD3 4,11,14 IRQ15
67 A33 B33 33 4 7
68 34 SD4 SRP10K 5 6 4,14,21
A34 B34 +5V IRQ14
MS-DBG-GF68 SRP4K7
R224
1 2 IOCHRDY#
THIS GOLDEN FINGER IS REVISED BY PEACH(9/24). RP3
IRQ11 1 10 1KR3
IRQ10 2 9 IRQ3
4 IRQ10 IRQ9 IRQ4 IRQ3 4
4 IRQ9 3 8 IRQ4 4
IRQ7 4 7 IRQ5
4 IRQ7 IRQ6 IRQ5 4
5 6 IRQ6 4
CN9 +5V
CON2-10 SRP10K
FAN CONN.
FANPOWER 1 2 R143
1 2 MEMCS16# 4
4K7R3
R10
C173 1 2 4
SCD1U IOCS16#
+5V +5V C174 4K7R3
1 U44D 1 U46F SCD1U R153
4 4 +5V 1 2
12 R120 U2X REFRESH# 4
2 TH_COM_VGA 4K7R3
11 13 12 1 2 1 GND OUT 8
2 TH_COM 13 2 IN OUT 7 R52
100KR3 3 IN OUT 6 1 2 0WS# 4,11
7 SSHCT32 7 SSHCT04 4 5
EN# OUT 4K7R3
TPS2013D
## CHANGE COMONENT
BT_QCHG 23
8 BATCNTL
R137
23 DQ 1 2
4 5 6
1KR3 U29
IMD1A108
+12V 3 3 2 1
1 Q5
2N7002 1
2 R150
1 10KR3
R131 1
1MR3 R138 2
4K7R3
2 ACER
2 5VSB_DC
TAIPEI TAIWAN R.O.C
Title
BDATA 8 370P/J (GOLDEN FINGER I/F)
Size Document Number REV
A3 96149 SC
Date: February 12, 1997 Sheet 13 of 25
+5V HDD+5V ## ADD CX3,CX4 +5V CDROM+5V
FX1 FX2
1 2 CLOSE TO CN17 HDD CONN 1 2
+5V FUSE-2D5A125V HDD+5V FUSE-2D5A125V
FX1, FX2 P/N:69.41501.001
1 FX1, FX2 P/N:69.41501.001
R124
4K7R3 4 CN16 CX3 CX4
3 SC4D7U16V6ZY SCD1U
2
HDD_LED#
1
IDE_D8 2 21 PCIRST#
IDE_D9 3 22 IDE_D7
IDE_D10 4 23 IDE_D6 CN17
HDD+5V IDE_D11 5 24 IDE_D5 33 34
IDE_D12 6 25 IDE_D4
1 IDE_D13 7 26 IDE_D3 1 2
R206 PCIRST# 24
IDE_D14 8 27 IDE_D2 IDE_D8 3 4 IDE_D7
4K7R3 IDE_D15 9 28 IDE_D1 IDE_D9 5 6 IDE_D6
10 29 IDE_D0 IDE_D10 7 8 IDE_D5
2 4 IDE_DRQ0 IDE_IOR# 11 30 IDE_D11 9 10 IDE_D4
IDE_RDY 12 31 IDE_IOW# IDE_D12 11 12 IDE_D3
13 32 IDE_D13 13 14 IDE_D2 +5V
14 33 IDE_D14 15 16 IDE_D1 +5V
4 IDE_DACK0# IDE_D15 IDE_D0 1
15 34 IRQ14 4,13 17 18
IDE_A2 16 35 IDE_A1 19 20 1 R200
IDE_CS3# 17 36 IDE_A0 4 IDE_DRQ1 21 22 R199 1KR3
HDD+5V 18 37 IDE_CS1# IDE_IOW# 23 24 4K7R3
19 38 HDD_LED# IDE_IOR# 25 26 2 IDE_RDY
20 39 HDD+5V 27 28 2 IDE_DACK1# 4
40 1 29 30 R198
RP33 41 R203 1 2
DSD4 5K6R3 SIRQI 4
1 10 +5V 31 32
DSD5 2 9 DSD0 R202 0R3
DSD6 3 8 DSD1 HRS-CON40-1 2 MOLEX-CONN30A 1 2
DSD7 DSD2 4 IRQ15 4,13
4 7 2
5 6 DSD3 DUMMY-R3
+5V
SRP10K HDD CONN.
CD-ROM 2 CONN.
RP35
DSD8 1 10 HDD+5V DSD12
DSD9 2 9
DSD10 3 8 DSD13 +5V +5V
DSD11 4 7 DSD14 1 U17A 1 U46B
5 6 DSD15 4 4
HDD+5V HDD_LED# 1 +5V
SRP10K 3 3 4 CDROM+5V
CDROM_LED# 2 MEDIA_LED# 16 CDROM+5V 1
R175
7 SSHC00 7 SSHCT04 4K7R3
C104 C93 C92 2
C103 CN14 SCD1U SCD1U SC10U16V
SC10U16V 41 44
4 DSD[0..15] IDE_A1
1 2
IDE_A2 3 4 IDE_A0
CD_CS3# 5 6 CD_CS1#
7 8 CDROM_LED#
9 10
11 12
15 CD_AUDR 13 14
15 16 CD_AUDL 15
RP37 11 HDSEL 17 18
DSD0 1 8 IDE_D0 11,12 RDATA# 19 20
DSD1 2 7 IDE_D1 11,12 WRTPRT# 21 22
DSD2 3 6 IDE_D2 23 24
DSD3 4 5 IDE_D3 11,12 TRK0#
11,12 25 26 8,12
WGATE# 27 28 3_MODE
SRN47 11,12 WDATA# R174
11 STEP# 29 30
11 FDIR 31 32 1 2
RPM 11
RP36 11 MTR0# 33 34
DSD4 1 8 IDE_D4 RP32 11 35 36 0R3
DSD5 2 7 IDE_D5 1 8 IDE_A0 DSKCHG 37 38
DSD6 IDE_D6 4 DSA0 IDE_A1 11 DR0#
3 6 4 DSA1 2 7 11,12 INDEX# 39 40
DSD7 4 5 IDE_D7 4 DSA2 3 6 IDE_A2
4 IDERDY 4 5 IDE_RDY 43 42
SRN47
SRN47 MOLEX-CONN40A
RP39 +5V
DSD8 1 8 IDE_D8
DSD9 2 7 IDE_D9 RP31 R84
DSD10 3 6 IDE_D10 4 1 8 CD_CS3# INDEX# 1 2
DSD11 4 5 IDE_D11 IDESCS3J 2 7 CD_CS1#
4 IDESCS1J AUD_GND AUD_GND
4 IDEPCS3J 3 6 IDE_CS3# R172 1KR3
SRN47 4 IDEPCS1J 4 5 IDE_CS1# DSKCHG 1 2
RP38 SRN47 1KR3 R176 FDD/CD-ROM CONN.
DSD12 1 8 IDE_D12 TRK0# 1 2
DSD13 2 7 IDE_D13
DSD14 3 6 IDE_D14 R204 R177 1KR3
DSD15 4 5 IDE_D15 4 IDEIORJ 1 2 IDE_IOR# WRTPRT# 1 2
SRN47 47R3 1KR3 R184
RDATA# 1 2
R205 ACER
4 IDEIOWJ 1 2 IDE_IOW# 1KR3
TAIPEI TAIWAN R.O.C
47R3 THESE RESISTORS MUST BE CLOSED FDD CONN. Title
370P/J (IDE & CD-ROM & FDD CONN)
Size Document Number REV
A3 96149 SC
Date: February 12, 1997 Sheet 14 of 25
DVDD3 C68
AUX2R
SC1U16V5JX
CX15 CX16 C67 CX17 C39 R71 C216
SCD1U SCD1U SCD1U SC10U10V6JY AUX2L 14 CD_AUDR 1 2 CD_R
SC1U16V5JX 10KR3 R70 C75 SC1U16V5JX
14 CD_AUDL 1 2 CD_L
## ADD CX15,CX16
10KR3 1
SC1U16V5JX
AVDD5 1 R72
R73 220KR3
1 220KR3
R146 G3 2
7K5R5F C38 1 2 2
16 LINE_IN_R C40 GAP-CLOSE
2
SC1U16V5JX AUD_GND
C6 1 16 LINE_IN_L
AUD_GND
SC10U16V R8 SC1U16V5JX CD_L
7K5R5F CD_R
AVDD5
2 MIN C62 +7V
C61 AVDD5
SOUND_L 16
C195 16
C201 SC1U16V5JX SOUND_R
16 MIC_IN_C
SC1U16V5JX C94
SC1U16V5JX
+5V C194 SC1U16V5JX
SCD01U S S S S T T A A DVDD3 SCD1U
B B Y Y R R U U V V U35
L7 DVDD3 F F N N E E X X R R 1 8
1 2 C65 2 OUT INPUT 7
L L H H C C 2 2 E E SENSE FB
AVDD5 T T L R R L L R F F SC1U16V5JX 3 6
MLB321611 SD 5V/TAP
R L O I 4 5
C63 GND ERROR
CX14 C47 CX29 C76 LP2951ACM
1 SCD1U SCD1U SCD1U SC10U10V6JY
C41 0 9 9 9 9 9 9 9 9 9 9 8 8 8 8 8 8 8 8 8 8 7 7 7 7 U31 SC1000P50V3JN
0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 1
MIN
S S S
S T T A A MMV V AA L L A A OOVV V V A R54
SC1U16V5ZY B B Y
Y R R U U I I R R VV I I U U U U OOOOD 10KR3
F F N
N E E X X C N E E SD N N X X T T CC C C F ## ADD CX14
1 1 L L S
S C C 2 2 F F SD E E I I L R I I OOL 2 C215
R53 AVSS T T H
H R L L R OI L R L R L R R L T
2 AVDD R L
R L L ADFLTR 75
220KR3 3 GP0 DVSS 74
DVDD3 4 73 SC1000P50V3JN C43
2 5 GP1 SEL0 72 SYNHL
6 GP2 SEL1 71
GP3 SEL2
7 GP4 MP0 70 SC1000P50V3JN
8 GP5 MP1 69
9 68 SA12 C46 VREFO
10 GP6 MP2 67 SA13 SYNHR
11 GP7 MP3 66 SA14
DVSS MP4 SA15 SC1000P50V3JN C66 C48
24 RSTDRV 12 RESET MP5 65
4 IOW# 13 64 19,21 SCLK SC10U16V SCD1U
IOW# MP6 A_A7 SDATA C44
4 IOR# 14 IOR# MP7 63 A_INPACK# 22
15 62 22 LRCLK SBFLTR
16 DVDD MP8 61 A_SPKR# DVDD3
4 AEN SA11 AEN MP9 R158 SC1000P50V3JN
17 A11 DVDD 60
SA10 18 59 1 2 R159
SA9 19 A10 VOLUP# 58 1 2 FROM PMU GPIO. C42
20 A9 VOLDW# 57 SA0 22KR3 SBFLTL
4 IRQ3 IRQ3 A0 SA1 22KR3
4 IRQ5 21 IRQ5 A1
56
22 55 SA2 SC1000P50V3JN VREFI
4 IRQ7 IRQ7 A2
4 IRQ9 23 IRQ9 X33O 54
4 24 53 X33I C50
IRQ10 25 IRQ10 X33I 52 TRECL C64 C45
4 IRQ11 IRQ11 D D X24O X24I SC10U16V SCD1U
X24I 51
A D A SCD01U
D C D A D C D D D
R K R C R K V V V R T
Q0 QK Q3 D D D D D S DD D D A A A A AA S X X C49
0 # 1 1 3 # 0 1 2 3 D S 4 5 6 7 8 7 6 5 4 3 S D D TRECR
YMF715
2 2 2 2 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 5 SCD01U
6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0
+5V
INVAPMSEL0
S S S S S S U28
A A A A A A 7 $AUDIO14M 1 X1 8 R136
2 X2 7 1 2 X33I
4 DRQ0 8 7 6 5 4 3 VDD PD#
4 DACK#0 SA[0..15] 4 3 GND 33.9M 6
4 DRQ1 4 5 33R3 C177
C176 16.9M 24.6M R144 SC10P
4 DACK#1 SS S S S S S S
4 DRQ3 DD D D D D D D SCD1U MK1422 1 2 X24I
4 DACK#3 0 1 2 3 4 5 6 7
33R3 C184
SC10P
4,9,10,11,13 SD[0..7]
ACER
TAIPEI TAIWAN R.O.C
Title
370P/J (AUDIO YMF-715)
Size Document Number REV
A3 96149 SC
Date: January 27, 1997 Sheet 15 of 25
RX2
+5V 1 2 5VSB_DC
1 47KR3
R25 3
22KR3 LED# 2 QX1
+5V 8 LED# RN1424
2 1 U38F 1
4 5VSB_DC
1 U25A
DISPLED 13 12 4
DISPLED# 8
## CIRCUIT MODIFY 1
3 CHARGELED
7 SSHC14 2
5VSB_DC
1 U25C 7 SSHC00
+5V 4
9 5VSB_DC
L16 23 BT_QCHG U25B 5VSB_DC
8 1
1 2 AMPVCC 10 4 1 U25D
4 4
MLB321611 7 SSHC00 6 12
5 11 BBT_QCHG
BBT_QCHG 19
C182 CX36 R7 13
SCD1U SC1U16V5JX 1 2 7 SSHC00
5VSB_DC SSHC00
7
47KR3
D8
1 DISPLED 1 2
6 U4 R6
47KR3 S1N4148
C5
V 2 SC100P C179
D
R24 D VO1 5 1 2 LINE_OUT_L
SOUND_L 1 2 4 IN- VO2 8
3 IN+ ST100U10VDK
22KR3 2 SPEAKERLB 3.3V G4 CN12
1 BYPASS 1 2
ENAUDIO SHUTDOWN 1 1
RX13 GAP-CLOSE 2
G 8 SLED 3
N 2K2R3
C169 D 4
C178, C179 P/N:80.10711.141 CHARGELED
SC1U25V5MY LM4861 BATPRLED# 5
7 2 6
CX37 14 MEDIA_LED# 7
SCD1U 10 SLLED# 8
10 NLLED# 9
10 CLLED# 10
LINE_OUT_L 11
12
13
14
15
AMPVCC 16
SPKR_L 17
18
SPKR_R 19
CX32 20
SCD1U SCON20-2
LINE_OUT_R
1
6 UX4 R26
47KR3
C28
V SC100P C178
D 2 15 LINE_IN_L
R5 D VO1 5 1 2 LINE_OUT_R
1 2 4 8
SOUND_R 3 IN- VO2 ST100U10VDK
22KR3 2 IN+ SPEAKERRB
BYPASS 15 LINE_IN_R
1 SHUTDOWN 1
G RX12
N 2K2R3
CX34 D
SC1U25V5MY LM4861 2 15 MIC_IN_C
7
CX35
SCD1U
+5V
+5V 1 U5A
1 U5B 4
4 1
4 23 6377_BIU# 3 BATPRLED#
+5V 8 DISABLELED 6 2
+5V +5V LED# 5
7 SSHCT32
1 U44B 7 SSHCT32
4 D10
4 SPKR 4 C253 R217 2 1
6 1 2 BZ1 CN7
8 SPKR_OFF 5 S1N4148 1 SPKR_L 1
+5V SCD1U 47KR3 SPEAKERLB
SSHCT32 R213 2
7
RX1 1 2 2 CON2-10
1 2
+5V 3 33R3 C252 BUZZER-3
47KR3 1 U44C C254 1 Q7 SC22P
4 SMPSA13
21 PCMSPK 9 2
8 SCD1U D11 CN10 ACER
## ADD RX1 10 2 1 SPKR_R 1
SPEAKERRB TAIPEI TAIWAN R.O.C
7 SSHCT32 S1N4148 2 Title
CON2-10
370P/J (AUDIO AMP & CONN)
Size Document Number REV
A3 96149 SC
Date: February 12, 1997 Sheet 16 of 25
+5V
18 VAA[0..8] VGAPWR
18 C228
VMBD[0..15] VRAMVCC CVCC0 SCD1U
3.3V CVCC1
18 VMAD[0..15] +5V
V V V V V V V V V
V V VV VV V V V V V V V V V V V V V V V V V V V VV V V V V V A A A A A A A A A
M M MM MM M M M M M M M M M M M M M M M M M M M MM M M M M M A A A A A A A A A
A A AA AA A A A A A A A A A A B B B B B B B B B BB B B B B B 0 1 2 3 4 5 6 7 8 AVCC
D D DD DD D D D D D D D D D D D D D D D D D D D DD D D D D D
RP13 R55 0 1 2 3 4 5 6 7 8 9 1 1 1 1 1 1 0 1 2 3 4 5 6 7 8 9 1 1 1 1 1 1
1 8 VAA0 1 2 0 1 2 3 4 5 0 1 2 3 4 5 RP10
2 7 VAA5 PCASAL# 1 8 18
3 6 4K7R3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 PCASAH# VCASAL#
2 7 VCASAH# 18
4 5 6 6 6 6 6 6 6 6 7 7 7 7 7 7 7 7 2 2 2 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 5 5 5 5 5 4 5 4 0 6 8 8 0 0 U12 PWEA# 3 6
2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 7 8 9 0 1 2 3 4 5 6 7 8 0 1 3 4 5 6 7 8 9 0 1 2 3 9 9 2 8 2 8 6 0 1 5 6 VWEA# 18
PRASA# 4 5 VRASA# 18
SRN4K7
MMMMMMMMMMMMMMMM M MMMMM MMMMMMMMMM A A A A A A AA A A B B MM MD I I C C SRN33
A A A A A A A A A A A A A A A A B B BB B B BB B B B B B B B B A A A A A A AA A V V V V V V V VV V V
D D D D D D D D D D D D D D D D D D DD D D DD D D D D D D D D 0 1 2 3 4 5 6 7 8 C C C C C C C CC C C RP11
R41 0 1 2 3 4 5 6 7 8 9 1 1 1 1 1 1 0 1 2 3 4 5 6 7 8 9 1 1 1 1 1 1 C C C C C C C CC C C 8 1
AD22 1 2 11 0 1 2 3 4 5 0 1 2 3 4 5 A B C 0 1 156 7 2
IDSEL RASA# PCASBH# VRAMOE# 18
33R3 RASB# 123 6 3 VCASBH# 18
3,4,21 22 159 PCASBL# 5 4 18
FRAME# 23 FRAME# CASAH# 160 VCASBL#
3,4,21 IRDY# IRDY# CASAL# UD[0..3] 19
3,4,21 TRDY# 24 TRDY# CASBH# 125 SRN33
3,4,21 DEVSEL# 25 DEVSEL# CASBL# 126 RP1
3,4,21 27 157 1 8 UD3
STOP# 31 STOP# WEA# 124 2 7 UD2
3,4,21 CBE#[0..3] 3,4,8,21 PAR PAR WEB# U8 UD1
OEAB# 155 3 6
+5V CBE#0 43 1 20 4 5 UD0
CBE#1 32 C/BE0# 71 2 19
1 CBE#2 21 C/BE1# P0
72 SRN22
C/BE2# P1 3 18
R191 CBE#3 10 73 4 17
10KR3 C/BE3# P2
74 RP26
P3 5 16
207 75 6 15 1 8 LD3
RESET# P4 LD2
2 P5 76 7 14 2 7
179 78 8 13 3 6 LD1
ROMA0 P6 LD0
24 PCIRST# 180 ROMA1 P7 79 9 12 4 5
182 ROMA2 P8
81 10 11
183 82 SRN22
185 ROMA3 P9 83 QPRN-R27C15
ROMA4 P10 U11 LD[0..3] 19
187 ROMA5 P11 84
189 85 1 20 RP25
191 ROMA6 P12 86 2 19 1 8 SUD3
192 ROMA7 P13
87 SUD2
ROMA8 P14 3 18 2 7
190 ROMA9 P15 88 4 17 3 6 SUD1
186 5 16 4 5 SUD0
ROMA10
188 ROMA11 MCD0 106 6 15
G5 193 107 Y0 7 14 SRN22
1 2 194 ROMA12 MCD1
109 Y1 8 13 RP20
ROMA13 MCD2 Y2 SUD7
196 ROMA14 MCD3 110 9 12 1 8
GAP-CLOSE 195 ROMA15 MCD4 111 Y3 10 11 2 7 SUD6
197 ROMA16 MCD5 112 Y4 3 6 SUD5
RGBGND 198 113 Y5 QPRN-R27C15 4 5 SUD4
200 ROMA17 MCD6 114 Y6
ROMOE# MCD7 115 Y7 SRN22
199 MCD8 116 UV0 SUD[0..7] 19
A20 MCD9 117 UV1
MCD10 UV2
7 $VGACLK 201 118 19
28 CLK MCD11 119 Y[0..7]
A23 MCD12 UV3 U8,U10,U11: P/N 69.20010.001
3,21 PERR# 29 PERR# MCD13 120
4 SERR# 30 SERR# MCD14 121 UV4
MCD15 122 UV5
7 $G14.318M 203 REFCLK
204 101
(RESERVED) RASC# UV7
7 32K2 154 32KHZ CASCH# 103
8 STANDBY# 178 STNDBY# CASCL# 104 UV6
WEC# 102
53 100 19
DDC_DATA 54 ACTI OEC# ZV_PCLK UV[0..7]
19 DDC_CLK 70 ENABKL 55 ZV_PCLK 19
20 SHFCLK 69 SHFCLK RSET
20 MOD 68
M
20 LP LP R 60 R 20
20 67 58 20
FLM 62 FLM G 57 G
61 ENAVDD B 65 B 20
ENAVEE HSYNC 64 HSYNC 20
VSYNC VSYNC 20
MMM C C
A A A A A A A A A A A A A A A A A A A AA A A AA A A A A A A A H A B B B B GGGD DI I G G
D D D D D D D D D D D D D D D D DD D DD D D DD D D D D D D D C C C C C C C C C R G GGGGN N N GGG G N N
0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 A A A A A A A A A E N N N N N D D D N NN N D D
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 0 1 2 3 4 5 6 7 8 F D D D D D A B C D DD D 0 1
5 5 4 4 4 4 4 4 4 4 3 3 3 3 3 3 2 1 1 1 1 1 1 1 9 9 9 9 9 9 9 9 9 9 5 1 2 3 5 1 1 1 8 6 7 1 2 2 CT65550
1 0 9 8 7 6 5 4 1 0 8 7 6 5 4 3 0 9 8 7 6 5 4 3 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 9 6 2 6 9 2 6 3 0 9 3 7 8 0 0
18 ENAVDD 1 9 5 4 2 8
A A AA AA A A A A A A A A A A A A A A A A A A A A A A A A A A 1
D D DD DD D D D D D D D D D D D D D D D D D D D D D D D D D D R37
0 1 2 3 4 5 6 7 8 9 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 560R3
8,19 ENAVEE MOAT
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 RGBGND
3,4,8,20,21,24 AD[0..31] Z Z 2
RP28 V V
R0 5 4 U10 _ _
R1 6 3 20 1 V H
R2 7 2 19 2 R R RGBGND
R3 8 1 18 3 E E
17 4 F F
SRN22 16 5
RP29 ZV_HREF 19
15 6 ZV_VREF 19
R4 5 4 14 7
R5 6 3 13 8
R6 7 2 12 9 ACER
R7 8 1 11 10
TAIPEI TAIWAN R.O.C
19 R[0..7] SRN22 QPRN-R27C15 Title
370P/J (VGA CT65550)
Size Document Number REV
A3 96149 SC
Date: February 12, 1997 Sheet 17 of 25
VGAPWR
17 VMBD[0..15]
ACER
TAIPEI TAIWAN R.O.C
Title
370P/J (VRAM & VGA BYPASS CAPACITOR)
Size Document Number REV
A3 96149 SC
Date: January 27, 1997 Sheet 18 of 25
17 Y[0..7]
+5V 17 UV[0..7]
R125
8 VSW1 1 2
1KR3
ACER
TAIPEI TAIWAN R.O.C
Title
370P/J (CRT CONN.& ZV PORT)
Size Document Number REV
A3 96149 SC
Date: February 12, 1997 Sheet 19 of 25
R16 L9
17 R 1 2 1 2 CRT_R 19
NL322522T-2R2
10R3 R14 L10
17 G 1 2 1 2 CRT_G 19
NL322522T-2R2
10R3 R13 L11
17 B 1 2 1 2 CRT_B 19
NL322522T-2R2
10R3
+5V
1 1 1 C13
R19 R18 R17 SC47P
75R3 75R3 75R3 C12
SC47P C14
2 2 2 SC47P
2 1 2 1 2 1
D3 D1 D2
BAV99LT1 BAV99LT1 BAV99LT1
RGBGND
3 3 3
R155 R111
17 FLM 1 2 1 2 PLFS 19
PLFS R40 L14
10R3 C204 22R3 1 2 1 2
SC33P 17 HSYNC CRT_HS 19
10R3 BK2125HS330
R165 R121 R39 L15
17 LP 1 2 1 2 PLP 19 17 VSYNC 1 2 1 2 19
PLP CRT_VS
10R3 C218 22R3 +5V 10R3 BK2125HS330
SC33P
THESE COMPONENTS 68.00031.001
R162 R117
17 MOD 1 2 1 2 PMOD 19
PMOD 2 1 2 1
10R3 C217 22R3 D5 D4 C16
SC33P BAV99LT1 BAV99LT1 SC47P
3 3 C17
SC47P
R157 R132
17 SHFCLK 1 2 1 2 PSHFCLK 19
PSHFCLK
22R3 C212 0R3 8 GPIORF1#
SC56P
U26 MUST BE 74AHC125
+5V
1 1 U26D
4 3
3.3V
23 LIB/MH# 12 11 AD16 3,4,8,17,21
1 U13A
4 1
7 SSHC125 R56
8 DISPLAY DISPLAY 2 3 1 2 19
LCD_DISPLAY
+5V 22R3
3.3V 7 SOLCX125M
1 1 1 U34C
R128 4 0
100R3
2 CPU_TH 9 8 AD17 3,4,8,17,21
2
CN8
7 SSLVC125
1
2
C2 CON2-10
SC100P
+5V
1 U26A
8 4 1
COVER_SW R133
8 ENBL 2 3 1 2 19
CCFT_ON
100R3
7 SSHC125
COVER_SW
1
1 R134
R4 10KR3
10KR3
2
2
ACER
TAIPEI TAIWAN R.O.C
Title
370P/J (LCD I/F)
Size Document Number REV
A3 96149 SC
Date: February 12, 1997 Sheet 20 of 25
3.3V
3,4,8,17,21 CBE#2 3,4,8,17,21 CBE#3
3,4,8,17 FRAME# 8 RING_OUT#
3,4,8,17 IRDY# A C 7 $CARDCLK IRQ14 4,13
D B 24 PCIRST# C73 C187 C188 C202 C214 C190 C34
3,4,8,17 TRDY# IRQ12 4
SCD1U SCD1U SCD1U SCD1U SCD1U SCD1U SCD1U
3,4,8,17 DEVSEL# 2 E IRQ11 4
0 # 1
3,4,17 STOP# R185 IRQ10 4 3.3V
3,17 PERR# 3 IRQ9 4
4 SERR# 3 GNT#1 0R3 4
1 IRQ7
3,4,8,17 PAR R148 3 REQ#1 3.3V
3,4,8,17,21 CBE#1 2 I I I I I I
C P S P S D T I F C 33R3 R R R R R R
B A E E T E R R R B Q Q Q Q Q Q A_SLOT_VCC C74 C198 C37 C35 C209
E R R R O V D D A E 2 1 1 1 1 9 7 SC1KP SC1KP SC1KP SC10U16V SC10U16V
AD[0..31] # R R P S Y Y M # 4 2 1 0 +5V
AD[0..31]
1 # # # E # # E 2
A A AA L # A A A A A A AA A A A A A A A A
3.3V D D DD # D D D D D D DD D D D D D D D D
1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3
2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 ## ADD CX10,CX11
B_SLOT_VCC
2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 0 0 0 0 0 0 0 0 0 9 9 9 9 9 9 9 9 9 9 8 8 8 8 8 8 8 8 8 8 7 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 5 5 5 U33 1
R164 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 R161 CX10
100R3 100R3 SCD1U R151
A GA A A C P V S PS D T I GF C A A A A V A A A A I GC A A AA V A A V A A RGGR P V I I I I I I I 1130_INTB# 1 2 INTD#
D N D D D / A C E ET E R R N R/ D D D D C D D D D D N/ D D DD C D D C D D EN N S C C R R R R R R R INTD# 3,4
2 1 D 1 1 1 B R C R ROV D D D AB 1 1 1 1 C 2 2 2 2 S DB 2 2 2 2 C 2 2 C 3 3 QT D T L C QQ Q Q Q Q Q 2
CX11 2 3 4 5 E R RP S Y Y ME 6 7 8 9 0 1 2 3 E E 4 5 6 7 8 9 P 0 1 I K 1 1 1 1 1 9 7 RX10 0R3
SCD1U AD11 1 1 E E2 L 3 N 5 4 2 1 0 / 156 1 2 IRQ5
AD11 L / I IRQ5 IRQ5 4
AD10 2 R R 155 1130_INTB#
AD9 3 AD10 I Q IRQ4/INTB 154 0R3 1130_INTA#
AD8 AD9 _ S IRQ3/INTA
4 AD8 O E GND 153
CBE#0 5 U R 152 22 R152
CBE#0 AD7 6 C/BE0 T DATA 151 SER_DATA 1130_INTA# 1 2
AD7 CLOCK SCLK 22 INTA# 3,4
7 150 22
AD6 8 VCC LATCH 149 SER_LATCH 0R3
AD5 AD6 SPKROUT/SUSPEND PCMSPK 16 3.3V
9 AD5 VCCP 148
AD4 10
AD4 A_CAD31 147 A_D10 1 1 U34D
AD3 11 146 A_D2 3 4
AD2 12 AD3 A_RSVD 145 A_D9
13 AD2 A_CAD30 144 A_D1 11 12
AD1 14 GND A_CAD29 143
AD0 AD1 VCC A_D8
15 AD0 A_CAD28 142
22 B_CD1# B_CD1# 16 141 A_D0 7 SSLVC125
B_D3 17 B_CCD1 A_CAD27
140 A_CD2#
B_D11 B_CAD0 A_CCD2 A_CD2# 22
18 139 A_WP 19,22
B_D4 19 B_CAD2 A_CCLKRUN 138 A_STSCG# A_WP
B_D12 B_CAD1 A_CSTSCHG A_STSCG# 22
20 B_CAD4 A_CAUDIO 137 A_SPKR# A_SPKR# 22
B_D5 21 B_CAD3 A_CSERR 136 A_WAIT# A_WAIT# 22
22 GND A_CINT 135 A_IREQ# A_IREQ# 22
B_D13 23 134 A_VS1 22
B_D6 24 B_CAD6 A_CVS1 133 A_A0 A_VS1
B_D14 25 B_CAD5 A_CAD26
132
B_RSVD A_CAD25 A_A1
B_D7 26 131 A_A2
B_D15 B_CAD7 A_CAD24 A_REG#
27 130 22
B_CE1# 28 B_CAD8 A_CC/BE3 129 A_REG#
22 B_CE1# B_A10 29 B_CC/BE0 GND 128 A_A3 INVAPMSEL0
B_CE2# B_CAD9 A_CAD23
22 B_CE2# 30 B_CAD10 A_CREQ 127 A_INPACK# 22
31 126 A_A4
B_OE# 32 VCC A_CAD22 125 A_A5
22 B_OE# B_IORD# 33 B_CAD11 A_CAD21 124 A_RESET
22 B_IORD# B_A11 B_CAD13 A_CRST A_RESET 22
34 123 A_A6
B_IOWR# 35 B_CAD12 A_CAD20 122 A_VS2
22 B_IOWR# B_CAD15 A_CVS2 A_VS2 22
B_A9 36 121 A_A25
B_A17 37 B_CAD14 A_CAD19 120
B_CAD16 VCCA A_A7
38 119
B_A8 39 VCCARDBUS A_CAD18 118 A_A24
B_A18 40 B_CC/BE1 A_CAD17 117 A_A12
B_A13 B_RSVD A_CC/BE2 A_A23
41 B_CPAR A_CFRAME 116
B_A19 42 B_CBLOCK A_CIRDY 115 A_A15
B_A14 43 114 A_A22
44 B_CPERR A_CTRDY R160
GND VCC 113
B_A20 45 112 1 2 A_A16
B_WE# B_CSTOP A_CCLK A_A21
22 B_WE# 46 B_CGNT A_CDEVSEL 111
B_A21 R168 47 B_CDEVSEL A_CGNT 110 33R3 A_WE# A_WE# 22
B_A16 1 2 48 109 A_A20
B_A22 49 B_CCLK A_CSTOP 108 A_A14
B_A15 33R3 50 B_CTRDY A_CPERR 107 A_A19
B_A23 B_CIRDY A_CBLOCK A_A13
51 B_CFRAME A_CPAR 106
B_A12 52 B_CC/BE2 A_RSVD 105 A_A18
$CARDCLK
B B
B B _ _ A A
B B B B B B B _ B B B B _ C C B B B B B _ A A A A A A A _ 1
_ _ _ B _ B _ _ B _ C _ _ _ B B _ C S C B _ _ _ _ B _ A A A A A A A A A A A C A _ _ _ _ _ _ _ C R149
C C C _ C _ C C _ C C C C C _ _ C A T L _ C C C C _ C _ _ _ _ _ _ _ _ _ _ _ C _ C C C C C C C C DUMMY-R3
A A A C A C A A C A / A A A C C S U S K C A A A A R A C C C C C C C C R C C / C A A A A A A A /
D D D V D R D D R D B V D D D V I E D C R C GD D D D S D C A A A V A A A A S A A B A GD D D D D D D B
1 1 1 S 2 S 2 2 E 2 E C 2 2 2 S N R I H U D N 2 2 2 3 V 3 D D D D C D D D D V D D E D N 1 1 1 1 1 1 1 E 3.3V
7 8 9 2 0 T 1 2 Q 3 3 C 4 5 6 1 T R O G N 2 D 7 8 9 0 D 1 1 0 2 1 C 4 3 6 5 D 7 8 O 9 D 0 1 3 2 5 4 6 1 2
PCI1131
5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 6 7 7 7 7 7 7 7 7 7 7 8 8 8 8 8 8 8 8 8 8 9 9 9 9 9 9 9 9 9 9 1 1 1 1 1 C189
3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 0 0 0 0
0 1 2 3 4 SC33P
B A A A A A A
B B B B B _ A _ A _ A _ A _ A _ _
_ _ _ _ _ D _ D _ D _ D _ D _ D A
D D D D D 1 D 1 D 1 D 1 D 1 D 1 1
22 B_RESET 0 8 1 9 2 0 3 1 4 2 5 3 6 4 7 5 0
B_D[0..15] A_D[0..15] A_D[0..15] 22
B B A
_ B _ B B B B BB B B A _
A_ A _ _ _ _ _ _ _ B B B _ A A _ A I A
2 A 2 A A A A B AA A _ _ _ S B A _ _ A I _ OA _ A
4 7 5 6 5 4 3 _ 2 1 0 B I WS T _ _ C C _ O A W_ A _
22 B_A[0..25] R _ R A P S BC C E E O R 1 R A 1 A
22 B_VS2 E V E I K C _ D D 1 2 E D 1 # 9 7 8
22 B_INPACK# G S Q T R G W2 1 22 A_CE1# # # # # A_A[0..25] 15,19,22
22 B_REG# # 1 # # # # P# # 22 A_CE2# ACER
22 B_VS1 22 A_OE# TAIPEI TAIWAN R.O.C
22 B_IREQ# 22 A_IORD# A_IOWR# 22
22 B_WAIT# Title
22 B_SPKR# 370P/J (PCI1131 CARD BUS CONTROLLER)
22 B_STSCG# Size Document Number REV
22 B_WP
22 B_CD2# A3 96149 SC
22 A_CD1# Date: February 12, 1997 Sheet 21 of 25
A_VPP A_SLOT_VCC
1
C208 R156 C207 C210 C203 A_D[0..15] B_D[0..15]
SCD1U 100KR3 SC10U16V SC1000P50V3KX SCD1U 21 A_D[0..15] 1 B_D[0..15] 21
A_A[0..25] 6 CN13 B_A[0..25]
19,21 A_A[0..25] 2 B_A[0..25] 21
2
SKT1
81 1
82 2
5 3 83 3
6 4 A_D3 84 4 B_D3
B_VPP B_SLOT_VCC A_CD1# 85 5 B_CD1#
21,24 A_CD1# B_CD1# 21,24
86 6
1 A_D4 87 7 B_D4
2 1 C180 R142 C20 C22 C21 A_D11 88 8 B_D11
SCD1U 100KR3 SC10U16V SC1000P50V3KX SCD1U A_D5 89 9 B_D5
A_D12 90 10 B_D12
2 A_D6 91 11 B_D6
A_D13 92 12 B_D13
PCM-SKT A_D7 93 13 B_D7
A_D14 94 14 B_D14
95 15
A_CE1# 96 16 B_CE1#
21 A_CE1# A_D15 97 17 B_D15 B_CE1# 21
3.3V A_A10 98 18 B_A10
A_CE2# 99 19 B_CE2#
1 21 A_CE2# A_OE# 100 20 B_OE# B_CE2# 21
C183 U30 21 A_OE# A_VS1 B_VS1 B_OE# 21
21 A_VS1 101 21 B_VS1 21
2 ST2D2U 15 3.3V AVPP 8 A_VPP A_A11 102 22 B_A11
+5V 16 9 A_IORD# 103 23 B_IORD#
3.3V AVCC A_SLOT_VCC 21 A_IORD# B_IORD# 21
17 3.3V AVCC 10 104 24
1 5V AVCC 11 A_A9 105 25 B_A9
1 2 A_IOWR# 106 26 B_IOWR#
C59 C60 C33 +12V 30 5V 20 21 A_IOWR# A_A8 107 27 B_A8 B_IOWR# 21
SCD1U 2 ST2D2U SCD1U 5V BVCC B_SLOT_VCC A_A17 B_A17
7 12V BVCC 21 108 28
24 12V BVCC 22 A_A13 109 29 B_A13
C58 23 A_A18 110 30 B_A18
SC1U25V5MY BVPP B_VPP +5V A_A14 B_A14
111 31
6 25 R145 A_A19 112 32 B_A19
14 RESET NC 1 2 113 33
24 PCIRST# RESET# C185 A_WE# 114 34 B_WE#
3 DUMMY-R3 SCD1U 21 A_WE# A_A20 115 35 B_A20 B_WE# 21
21 SER_DATA DATA
4 A_IREQ# 116 36 B_IREQ#
21 SCLK CLOCK 21 A_IREQ# A_A21 B_A21 B_IREQ# 21
21 SER_LATCH 5 LATCH NC 26 117 37
27 A_SLOT_VCC 118 38 B_SLOT_VCC
NC
NC 28 119 39
29 A_VPP 120 40 B_VPP
NC
GND 12 121 41
19 122 42
13 NC 123 43
NC A_A16 B_A16
18 OC# 124 44
A_A22 125 45 B_A22
A_A15 126 46 B_A15
TPS2206 A_A23 127 47 B_A23
128 48
A_A12 129 49 B_A12
A_A24 130 50 B_A24
A_A7 131 51 B_A7
A_A25 132 52 B_A25
A_A6 133 53 B_A6
21 A_VS2 134 54 B_VS2 21
B_SLOT_VCC B_SLOT_VCC A_VS2 A_A5 135 55 B_A5 B_VS2
A_SLOT_VCC A_SLOT_VCC 21 A_RESET A_RESET 136 56 B_RESET B_RESET 21
137 57
RP9 RP8 A_A4 138 58 B_A4
B_STSCG# 1 10 A_STSCG# 1 10 21 A_WAIT# A_WAIT# 139 59 B_WAIT# B_WAIT# 21
B_SPKR# 2 9 B_INPACK# A_A6 2 9 A_A16 A_A3 140 60 B_A3
B_WAIT# 3 8 B_RESET A_A24 3 8 A_A10 15,21 A_INPACK# A_INPACK# 141 61 B_INPACK# B_INPACK# 21
B_WP 4 7 B_A15 A_RESET 4 7 A_A23 A_A2 142 62 B_A2
5 6 B_A22 5 6 A_A25 21 A_REG# A_REG# 143 63 B_REG# B_REG# 21
A_A1 144 64 B_A1
SRP10K SRP10K 15,21 A_SPKR# 145 65 B_SPKR# 21
A_SPKR# B_SPKR#
146 66
A_A0 147 67 B_A0
21 A_STSCG# A_STSCG# 148 68 B_STSCG# B_STSCG# 21
A_D0 149 69 B_D0
A_D8 150 70 B_D8
B_SLOT_VCC B_SLOT_VCC A_D1 151 71 B_D1
A_SLOT_VCC A_SLOT_VCC A_D9 152 72 B_D9
A_D2 153 73 B_D2
RP7 RP6 A_D10 154 74 B_D10
B_A14 1 10 A_A19 1 10 155 75
B_A19 2 9 A_A14 2 9 A_A17 21 A_WP 156 76 B_WP 21
B_A20 3 8 A_A18 3 8 A_A20 A_WP A_CD2# 157 77 B_CD2# B_WP
B_IREQ# A_A13 A_IREQ# 21,24 A_CD2# B_CD2# 21,24
4 7 4 7 158 78
5 6 B_A21 5 6 A_A21 159 79
160 80
SRP10K SRP10K
3.3V 3.3V PCM-CONN160
1
6
R83 R80 1
1 2 B_VS2 1 2 A_VS2 A_SLOT_VCC
A_SLOT_VCC A_SLOT_VCC
22KR3 22KR3
RP5 R82 R46 R76
A_INPACK# 1 10 1 2 B_VS1 1 2 A_VS1 1 2 A_A8
A_A7 2 9 A_WP
A_A22 3 8 A_SPKR# 22KR3 22KR3 22KR3
A_A12 4 7 A_A15 R186 R81 R77
5 6 A_WAIT# 1 2 B_CD2# 1 2 A_CD2# 1 2 A_A9
ACER
SRP10K 22KR3 22KR3 22KR3
R47 R79 R78 TAIPEI TAIWAN R.O.C
1 2 B_CD1# 1 2 A_CD1# 1 2 A_A11 Title
22KR3 22KR3 22KR3 370P/J (PCMCIA SOCKET)
Size Document Number REV
A3 96149 SC
Date: February 12, 1997 Sheet 22 of 25
## REMOVE C27,ADD CX12 CX13 CX6
## REMOVE C69,ADD CX20,CX21
## REMOVE C52 C51,ADD CX22,CX23 ## 5VSB_DC IS PROVIDED BY CHARGER
+5V
1 7 SSHC14 7 SSHC14
C181 CX6
2 ST22U35VDM SC10U50V
9 CHARGER CONN.
PWRGOOD#
1 C29
3 R135 SCD1U
THESE CAPACITORS MUST BE CLOSED DC/DC. 2 Q6 10KR3
RN2424
1 ## 2
3 DISABLE 8
1 Q3
2N7002
2 ##
1
D9 R29
8,20 1 2 1MR3
LIB/MH# ##
S1N4148 2
CLOSE TO THE BAT CONN
BT+ L17 CN18
1 2 1
ID 2
BTS SCHOKE-D 3
13 DQ DQ 4
5
BT- 6
+5V
MOLEX-CON6
C250 1
SC1000P50V3KX R211
C131 22KR3 5VSB_DC
SC1000P50V3KX ## ADD U1 RX5 CX5
C126 C125 2
SCD1U SCD1U C128 8 1
SC1000P50V3KX BT_SENSE RX4
22KR3
C129 3 2
SC1000P50V3KX 1 Q2
1 BC848CLT1 RTCIRQ8# 5VSB_DC
BGND
R209 2 USE MOTOROLA BC84CLT1 (84.00848.011) 1 U1XB
220KR3 4
CX18 5
2 SCD1U 4 RESERVE
5VSB_DC 6
1 U1XC RX5
4 1 2 7 TSHC02
8
10 10KR3
9 CX5
SCD1U
7 TSHC02
BAT_USE#
BBL2# BBL1#
2
2 R30
R32 470R3 2
470R3 R28
1 470R3
1
1
6377_BBL2# 8 6377_BIU# 8,16 ACER
6377_BBL2# 6377_BIU# 6377_BBL1# 6377_BBL1# 8 TAIPEI TAIWAN R.O.C
Title
370P/J (CHARGER,DC/DC)
Size Document Number REV
A3 96149 SC
Date: February 12, 1997 Sheet 23 of 25
COMMON ALADDIN III
+5V
R171
1 2
+5V
1 U41A 10KR3
4
4 XDIR
3,10,14,17,21,22 PCIRST# 2 1 $CPURST 4 PULL L: 5V suspend mode enable.
R43
+5V 7 SSHCT04 1 2 PULL H: 5V suspend mode disable.
1 U41B
4 10KR3
L: DMA DACK[7:5,3:0] polling enable.
11,13,15 4 3 4 SPLED *** If L, add ALDN3 P.21 MUX!
RSTDRV H: DMA DACK[7:5,3:0] polling disable.
7 SSHCT04
R42 L: Internal keyboard cntrler enable.
4 SPKR 1 2
H: Internal KBC disable.
10KR3
+5V
U17C
POWER: VCC_IDE & GND R20 L: Internal RTC enable.
1
4 1 2 *** Refer to CKT down left.
+5V PHOLD# H: Internal RTC disable.
9
8 1 U45A 10KR3
10 4
1 R38 L: External I/O APIC mode supported.
SSHC00 4 IOW#
7 3 RTCRW 9 4 TC 1 2
2 H: Ext. I/O APIC mode not supported.
4 RTCROMCS# 10KR3
7 SSHCT32
R170
4 KBCS# 1 2
5VSB_DC +5V
1 U1XA 1 U45B 560R3
4 4 R173
2 4 RTCROMCS# 1 2 Must pull High.
1 6 RTCDS 9
3 4 IOR# 5 10KR3
7 SSHC02 7 SSHCT32
5VSB_DC
1 U1XD
4
11
13
12
7 SSHC02
+5V
1 U46C
4
5 6
+5V
1 U38D 7 SSHCT04
4
9 8
+5V
1 U46D
7 SSHC14 4
9 8
7 SSHCT04
+5V
1 U46E
4
+5V 11 10
1 U41E +5V
4 1 U45D
7 SSHCT04 4
11 10 22 A_CD1# 12
11
13 +5V
SSHCT04 22 A_CD2# U17D
7 1
+5V 7 SSHCT32 4
1 U46A 12
+5V 4 11
U41F 13 EXCACD# 8
1
4 1 2
+5V 7 SSHC00
13 12 1 U44A
7 SSHCT04 4
22 B_CD1# 1
7 SSHCT04 3 ACER
22 B_CD2# 2
TAIPEI TAIWAN R.O.C
7 SSHCT32 Title
370P/J (H/W JUMPER SETTING)
Size Document Number REV
A3 96149 SC
Date: February 12, 1997 Sheet 24 of 25
BYPASS CAPACITORS
CPU
3.3V
M1521
2.9V 2.9V C108 C240 C213 C232
SCD1U SCD1U SCD1U SCD1U
3.3V
C238 1 C246 1 1
C120 C113 C251 C122
SCD1U SC1000P50V3KX SC2K2P ST100U10VDK 2 ST100U10VDK
2 2 ST100U10VDK C248
C110 C118
SCD1U SC1U16V5ZY SC10U16V
CLOSE TO PIN7,9,11,13,15,17 P/N: 80.15711.341
7343,D SIZE 3.3V
2.9V 2.9V
CLOSE TO PIN 105,106,119
C245 C36 C247 C206 C258
3.3V 3.3V SCD1U SCD1U SCD1U SCD1U SCD1U
C119 C121 C115 C127 C112 C114
SCD1U SC1000P50V3KX
SC2K2P SCD1U SC1000P50V3KX
SC2K2P
C124 C123 C111 C239 C243
SCD1U SCD1U SC1U16V5ZY SCD1U SCD1U
CLOSE TO PIN 269,271,273,275,277,279 CLOSE TO PIN88,98,108,118,128,138
+5V
3.3V
CLOSE TO PIN 201,202 CLOSE TO PIN 190,203,204
C116 C219 C220 C95
1 SCD1U SCD1U SCD1U SCD1U
C106 C117
SCD1U 2 ST100U10VDK
C230
CLOSE TO PIN 157,167,177,187,197,207,217 SC4D7U16V6ZY
CLOSE TO PIN 87,97,107,117,127,137,147
CLOSE TO PIN 72
CACHE CLOSE TO PIN 40 CLOSE TO PIN 105
CY2 CY1 CY3
3.3V SCD1U SC4D7U16V6ZY SC1000P50V3KX
+5V
3.3V
C102 C15
SCD1U SC1000P50V3KX
C262 C109
SCD1U SCD1U
CLOSE TO PIN 53 CLOSE TO PIN 72
+5V
C227
SC10U16V
ACER
TAIPEI TAIWAN R.O.C
Title
370P/J (BYPASS CAPACITORS)
Size Document Number REV
A3 96149 SC
Date: January 27, 1997 Sheet 25 of 25
A p p e n d i x E
Checkpoint Description
04h • Check CPU ID
• Dispatch Shutdown Path
Note: At the beginning of POST, port 64 bit 2 (8042 system flag) is read to
determine whether this POST is caused by a cold or warm boot. If it is a cold
boot, a complete POST is performed. If it is a warm boot, the chip initialization
and memory test is eliminated from the POST routine.
Checkpoint Description
2Ch • 128K base memory testing
• Set default SS:SP= 0:400
Note: The 128K base memory area is tested for POST execution. The remaining
memory area is tested later.
Checkpoint Description
7Ch • Reset pointing device
• Check pointing device
70h • Parallel port testing
74h • Serial port testing
78h • Math Coprocessor testing
80h • Set security status
84h • KB device initialization
• Set KB led upon setup requests
Note: If keyboard Number Lock is enabled, the NumLock LED (if present) should be
turned on.
• Enable KB device
6Ch • FDD testing & parameter table setup
Note: The FDD LED should flash once and its head should be positioned