80286 microprocessor
In early 1980 Intel source for two of most important
components of PC : CPU and Memory (Dynamic RAM).
And in 1982 Intel introduced 80286 used 1300,000 NMOS
with 24 address pin and 16 pin for data and change
package from DIP to LCC (Leaded chip carrier)
80286 has fully compatible with 8088/8086 with new
instruction and capabilities.
IBM PC AT
In 1984 IBM used 80286 for design of PC AT
Many company cloning IBM PC AT and was more
successful than IBM such as Compaq.
In mid 1980 the drop in DRAM memory price caused Intel
withdraw from this market and shifted resources to
microprocessor design.
80386
In 1985 Intel introduced the 80386 microprocessor
80386 has 32-bit register and 32 bit address bus, allowing
it to address 4GB of memory.
80386 used 275,000 CMOS transistors packaged in 132-
pin PFA (Pin grid array)
2 popular versions of 80386: 80386DX and 80386SX.
While both at internally 32-bit microprocessor
80386SX has 16-bit external data bus and 24-bit address
bus
80386SX PC can running 32-bit software for 3086 without
the added cost of a larger motherboard.
In 1990 AMD and Cyrix began producing the 80386
microprocessor.
80486
8046 was the first 1 million-transistor microprocessor. (1.2
million CMOS transistor) packaged in 168-pin PGA like
386
8046 was 32-bit microprocessor with capability of 4GB of
memory.
Intel integrated 80387 Math coprocessor in addition to 8K
bytes of cache memory into a single chip.
80486SX is exactly like 80486 except it does not contain
the math coprocessor. A math coprocessor for 80486Sx is
80487SX.
8088/8086 Microprocessor
Data bus
8088 and 8086 are both 40-pin microprocessor chips, with
some differences in address and data buses.
Both are 16-bit processors internally, But
8088 has 8-bit data bus (AD0-AD7)
8086 has 16-bit data bus (AD0-AD15)
AD0-AD7/15 mean address and data bus multiplexed for
minimum number of pin.
When ALE (Address latch enable) is activate (Sets high)
use for indicate when AD0-AD7/15 is address. This
process call demultiplexing
Address bus
To demultiplex address signals from address/data pins,
Latch must be use.
Most widely use of latch is 74LS373
In any system all address must be latched to provide a
stable, high-drive capability for system.
Pin descriptions
CLOCK
Microprocessor require a very accurate clock for
synchronization event and driving CPU
8084 is clock generator for Intel microprocessor
RESET
to terminate present activities of microprocessor and
automatically contain data shown in table
Table 1-3
READY
ready is input signal used to inserted wait state for slow
memories and I/O.
TEST
Input from 8087 coprocessor for synchronize 8087 and
8088/8086.
If it is low, executing of program will continue, If not it
will stop executing.
Minimum/Maximum mode
Function of pins 24-31 of 8088/8086 depending on mode
of processor.
Minimum mode is selected by connecting ping MN/MX to
+ 5V and ground for maximum mode.
Minimum mode
Pins 24-31 are used as memory and I/O control signal that
generated internal of 8088/8086.
Similarly to earlier 8085A 8-bit microprocessor
/S0, /S1 and /S2 (Status signals, pins 26, 27 and 28)
Three status signal output pins from 8088/8086 to 8288 to
produces all control signal such as DT/R, DEN,
MC/PDEN, ALE, INTA,IOR IOW, MRD, MRWT.
Input Pins
/RES (Reset in)
Active-low signal to generated RESET connected to
power-good signal from power supply.
When switch on power supply and low on this signal 8084
force CPU to reset called cold boot.
F / /C (Frequency/Clock select)
Select two sources of clock : Generated internally 8284
(using Crystal) or receive clock from EFI pin.
IBM PC connected this pin to low mean generated
internally.
/ASYNC
Ready synchronization select, active low pin for device
that are not able to adhere in setup time.
IBM PC connected this pin to low make system design
easier with slower logic gates.
Output signals
RESET
Active-high signal to RESET 8088/8086 CPU.
OSC (Oscillator)
Provides clock equal to crystal use for expansion slot.
CLK (Clock)
One-third clock (4.772776 MHz) frequency from crystal
or EFI pin, with 33% of duty cycle.
Connected to clock input of 8088/8086 and all devices that
must be synchronized with CPU.
READY
Connected to READY pin of CPU to insert WAIT state
due to slowness of devices that CPU trying to connect.
CLK (Clock)
Input from 8284 clock generator to synchronize all
command and control signal with CPU.
Output signals
DT / /R (Data transmit/receive)
Use to control direction of data in and out for 8088/8086.
In IBM PC it is connected to DIR pin of 74LS245.
When CPU is writing this pin is high and allow data go
from A to B of 74LS245.
When CPU is reading this pin is low and allow data go
from B to A of 74LS245.
Overview of timing