FIRST STATUS REPORT UP TO FEBRUARY-2010

Introduction

My project is useful in as wireless sensor data compressing and processing in many fields
of interest such as mineral processing, patient monitoring, sensor data instrumentation,
biomedical instrumentation and radar sensor data processing.

However, Wireless Sensor Network is driven by a severe Recent technological

breakthrough in low power processing units and communication devices have enabled the
development of distributed autonomous nodes able to sense environmental data, compute
and transmit it using wireless communication to a base station.

My project work analyzes the Transmitter and Receiver methods of ADC & Compressor
Block and HDLC procedure implementation commonly used nowadays, and points out
their defects. I did software Programming of ADC & Compressor Block and HDLC
procedures, that is flexible, which can be used in many different HDLC applications by
modification of it.

I was observed in my programs take many resources out of the processor and consume less
latency when running on system processor. I had widely usage of FPGA, HDLC
procedures can be implemented on FPGA by hardware programming. This programmable
Hardware architecture can process multi-channel signals in parallel.

I had studied sensors and data compression and HDLC protocol. I will do the these
sensors are sending ADC compressor block and compressed after that data sending to
HDLC framer.
Aim of project

In my project main aim of this project is to model and design an efficient wireless system
that is easy to integrate with other technologies and techniques (packet based data
communication, data buffering management, data security & compressing and RF based
wire less communication) infrastructures at a low cost.

The system would read analogue information recorded by programmable no of multi

sensors in a transmitting unit attached to the system.

The recorded data are converted digitally using analogue-to-digital converter. and sent to
frequency shift keying (FSK) transmitter.

The design includes high data link controller (HDLC) protocols, is a bit oriented protocols
that is used as a data link for most of the current communication systems.

Motivation

Previously the data is transmitted on fixed amount of files due to absent of compressor
techniques and data is not transmitted properly due to absent of Cyclic redundancy check.

But In my project I used compressor techniques which are extensively compressed require
input data from sensor, these data is compressed with in single file using Compressor
block, block is consist of Channel counter, FIFO, RLE, MUX .

These Sensors are sending to channels and these channels are connected ADC multiplexer
and next these ADC multiplexer is selecting the channels. Channel counter is counting
the number of channels.
Fifo is here used to data storage purpose.
Run lenth encoding is data compressing purpose used.
Here I taking another FIFO these are compressed data storage purpose used.
After compressor block ,Cyclic redundancy checking is used for error detection technique
using HDLC Framer block, block is consist of DLC, parallel to serial conversion used for
serial data communication.
DLC is used to counting the data length.
HDLC was defined by ISO for use on both point-to-point and multipoint data links.

Block diagram

Fig:Configurable multichannel sensor data processor

Literature Survey

Recent advancement in wireless communications electronics has enabled the development

low cost sensor networks. The sensor network can be used various application areas like
health, military ,home. There are different technical issues that researchers are currently
resolving.

Wireless communications and elctronics have enabled the development of lowcost,

lowpower, multifunctional sensor nodes that are small size and communicated untethered
in short distances. These tiny sensor nodes, which consist of sensing and data processing,
communicating components, leverage the idea of sensor networks represent a significant
improvement over traditional sens

Next I had studied about the different blocks, modules with their inner functionality
of ADC compressor block and HDLC blocks with the help of configurable Multichannel
sensor data processor block diagram.

Sensors

I had studied about the sensors here I used 32 sensors

The main idea is to the sensors are used to temperature sensor used to Patient monitoring,
image sensor is used CCTV cameras and gas sensor is used to Industrial purpose, my
project using 0-31 sensors, these sensor sending through channels .

channels

I had studied about the channels here I uesd 32 channels in this project.channel refers
either to a physical transmission medium such as a wire, or to a logical connection over a
multiplexed medium such as a radio channel. A channel is used
to convey an information signal.
Multiplexer

Multiplexer is a device that performs multiplexing,it selects one of many analog or digital
input signals and forwards the selected input into a single line. A multiplexer of 2 n inputs
has n select lines, which are used to select which input line to send to the output. In this
project I had learned multiplexer functionality.

Here I taking the 32:1 multiplexer in this design is for selecting any one of the 32 channels.
This multiplexer has five select lines in order to select 32 channels. There five select lines
get the input information from channel counter. This multiplexer scans data from the
sensors and then transfer each data word immediately to the FIFO.

Channel Counter

I had learned about the channel counter functionality.In this project we have used 32
sensors may be selected using a channel counter and ADC multiplexer channel counter is
triggered by clock signal in order to select channels one by one we have used five bit
binary counter logic countover is the signal which is active when capturing data from the
sensors is completed or when the FIFO is full.

FIFO

I had learned first in first out functionality it used for data storage purpose.FIFO is a
logic block which is used twice in compression logic. One for capturing input data.
Another is for storing compressed data. Data first entered into the FIFO is the data which is
retrieved from the FIFO. Input FIFO and output FIFO enabled, FIFO disable, FIFO Read
and FIFO Write are the operations . First in First Out is a memory that stores information
Run lenghth encoding

In my project I had learned run length encoding functioning. These are used for data
compressing technique to reduce the volume of data to be transmitted the text, fax, image,
purpose . RLE is a conceptually simple form of compression.RLE is a lossless data
compression technique.

Lossless compression is possible because most real-world data has statistical redundancy.
Lossless compression usually exploit statistical redundancy in such a way as to represent
the sender's data more concisely without error. The human eye is more sensitive to
suitable variations in luminance than it is to variations in color. JPEG image compression
works in part by "rounding off" some of this less-important information.

These adc compressor block signal are sending to the HDLC framer .

FPGA

I had studied about the FPGA applications

The prototyping of designs later to be implemented in gate arrays, and also emulation of
entire large hardware systems. The former of these applications might be possible using
only a single large FPGA and the latter would entail many FPGAs connected by some sort
of interconnect; for emulation of hardware.

The usage of FPGAs as custom computing machines. This involves using the
programmable parts to “execute” software, rather than compiling the software for
execution on a regular CPU.
 SECOND STATUS REPORT UP TO JUNE-2010

Next I had studied about the different blocks, modules with their inner functionality
of HDLC blocks and decompressor block with the help of configurable Multichannel
sensor data processor block diagram.

HDLC Framer
Here I used to ADC compressorblock signal sending to the HDLC framer. I had studied
about the HDLC framer working functionality with combined all subblocks of HDLC
framer,these are parallel to serial converter,cyclic redundancy check ,data length counter
and multiplexer. HDLC uses the term "frame" to indicate an entity of data(or a protocol
data unit) transmitted from one station to another.

Serializer and deserializer

I had learned about the serializer and deserializer functionality. The serializer are used
for serial data communication purpose. And deserializer is used for conversion of serial to
parallel conversion communication purpose. (SerDes pronounced sir-dees) is a pair of
functional blocks commonly used in high speed communications to compensate for limited
input/output. These blocks convert data between serial data and parallel interfaces in each
direction. Although the term "SerDes" is generic, in speech it is sometimes used as a more
pronounceable synonym.

cyclic redundancy check

I had learned about CRC functioning. These are used for error detection technique
Purpose.A cyclic redundancy check (CRC) or polynomial code checksum is an insecure
hash function designed to detect accidental changes to raw computer data, and is
commonly used in digital networks and storage devices such as hard disk drives.
Data length counter

I had studied about data length counter functioning. These is used for counting the
length of the data purpose. In digital logic and computing, a counter is a device which
stores (and sometimes displays) the number of times a particular event or process has
occurred, often in relationship to a clock signal. Usually, counter circuits are digital in
nature, and count in natural binary. Many types of counter circuit are available as digital
building blocks.

Transmitter State Machine

In my project I used transmitter state machine this is controlling adc compressor block
and HDLC framer

Top module of transmitter

In my project I integrated the adc compressor block and HDLC framer and transmitter
state machine controller and I used in VHDL language code.

HDLC Deframer

After transmitter signal these are received by the HDLC Deframer consist of open flag
detector, serial to parallel converter, cyclic redundancy check and Data length counter.

Open flag detecter

In my project I had studied open flag detecter functionality this is used for detecting
the flag sequence like start point to stop point purpose.
Demultiplexer

I had learnerd about the demultiplexer functionality .Demultiplexer as a single-input,

multiple-output switch. The schematic symbol for a multiplexer is an isosceles
trapezoid with the longer parallel side containing the input pins and the short parallel side
containing the output pin.
Decompressor & Application interface block

I had studied about HDLC Deframer signal sending to the Decompressor Block, the
Decompressor and application interface block working functionality with combined all
subblocks of FIFO,RLE and channel counter.
After Decompressor sensor data,these are giving to the monitor for observe the patient
pulses or depending upon the our require applications.

Receiver state machine

Also I used receiver state machine this is controlling HDLC deframer and
decompressor block and I used VHDL language code.

Top module of receiver

In this project I integrated the HDLC deframer and Decompressor & application
interface block and receiver state machine.
Technical Approach

In my project I used given below tools ,these tools are used to simulation, synthesis and
FPGA implementation purpose .

VLSI EDA TOOLS

Active-HDL:

Active-HDL is an integrated environment designed for development of VHDL, Verilog,

EDIF and mixed VHDL-Verilog-EDIF designs and simulation process.

Xilinx ISE:

Integrated Software Environment (ISE) enables the HDL test bench generator and us to
quickly verify the functionality of these sources using the integrated simulation capabilities
(ModelSim). HDL sources could be synthesized and implemented using the Xilinx
Synthesis Technology (XST) and implementation tools.
The over all System Architecture will be designed using VHDL language and simulation,
synthesis and implementation will be done using various FPGA based Xilinx ISE
EDA Tools. In this research work sensor will implement these on sensor data

LANGUAGE
My project code and FPGA implementation using VHDL coding.
Conclusion:

Finally here I done all modules and blocks like ADC compressor block , HDLC framer
and HDLC defreamer ,and decompressor block.Here vhdl code simulating, synthesizing
and observed the wave forms and RTL schematic results after that my project
implemented on FPGA. The proposed system performance can be improved by re-
considering the system architecture design by including the some of the techniques, which
are exiting in the latest re-configurable FPGA Hardware resources.

Future scope

As the further scope of project use viterbi decoder at receiver in order to correct error and
send this to hdlc deframer and rle decompression in order to get reliable data in order.