Synchronous Sequential
Logic
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Sequential Logic
Sebuah sistem digital dapat merupakan combinational logic atau sequential
logic. Jenis yang kedua memiliki elemen penyimpanan.
feedback path
Informasi yang disimpan dalam elemen memory pada suatu saat menentukan
keadaan dari rangkaian sequential pada saat itu.
Rangkaian sequential menerima informasi dari input eksternal. Input-input ini
bersama dengan keadaan saat ini dari elemen penyimpan, menentukan nilai dari
output.
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Synchronous Sequential Logic
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Synchronous Clocked Sequential Logic
undefined state
Dalam kondisi normal, kedua input latch tetap 0 kecuali keadaan berubah.
Jika S = 1 latch dalam keadaan ‘set’ : Q = 1, Q’ = 0.
Sebelum R reset ke 1, S harus kembali ke 0 untuk menghindari
kemunculan dari keadaan tak tentu dimana kedua output = 0
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SR LATCH with NAND ( S ' R' )
undefined state
Jika D = 1, Q = 1 ‘set’
Jika D = 0, Q = 0 ‘reset’
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Symbols for Latches
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Flip-Flops
•D-latch di-trigger setiap kali pulsa menjadi high atau level logic
“1”.
• Selama pulsa input tetap pada level ini, setiap perubahan pada
input data akan mengakibatkan perubahan output dan state dari
latch.
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Positive level
Positive-edge triggered
Negative-edge triggered
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Edge-Triggered Flip-Flop
Rangkaian mempunyai input D dan merubah outputnya pada saat negative side
dari clock, CLK.
Jika CLK“0”, output inverter “1”. Latch slave enabled dan output Q sama
dengan output master, Y. Latch master disabled (CLK = 0).
Jika CLK berubah ke high, input D ditransfer ke latch master. Slave tetap
disabled selama C low. Setiap perubahan input merubah Y, tetapi tidak Q.
∴ Output flip-flop dapat berubah jika CLK mengalami transition 1 0
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Edge-Triggered Flip-Flop: Graphic Symbols
D = JQ'+ K ' Q
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Characteristic Tables and Equations
Q(t) = present state
J K Q(t+1) Q(t+1) = next state after one clock period
0 0 Q(t) No change
0 1 0 Reset
1 0 1 Set
1 1 Q’(t) Complement T Q(t+1)
0 Q(t) No change
Q (t + 1) = JQ'+ K ' Q 1 Q’(t) Complement
Q (t + 1) = T ⊕ Q = TQ '+T ' Q
D Q(t+1)
0 0 Reset
1 1 Set
Q (t + 1) = D
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Analysis of Clocked Sequential Circuits
State Equation
State equation (transition equation) menentukan next state sebagai
fungsi dari present state and input.
State Table
State table (transition table) terdiri dari: present state, input
next state dan output.
State Diagram
Informasi dalam state table dapat direpresentasikan secara grafis dengan
state diagram. State dinyatakan dengan lingkaran dan transisi antar
state dinyatakan dengan garis berarah yang menghubungkan kedua lingkaran.
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Analysis of Clocked Sequential Circuits
Analysis Procedure
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Example of a Sequential Circuit
State Equations
A(t + 1) = A(t ) x(t ) + B(t ) x(t )
B(t + 1) = A' (t ) x(t )
y = [ A(t ) + B (t )]x' (t )
(t+1) next state of the flip-flop
one clock edge later.
A(t + 1) = Ax + Bx
B(t + 1) = A' x
y = ( A + B ) x'
Flip-flop input equations
(excitation equations)
DA = Ax + Bx
DB = A' x
note
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Example of a Sequential Circuit (continued)
A(t + 1) = Ax + Bx
B(t + 1) = A' x
y = ( A + B ) x'
Present Next
State Input State Output
A B x A B y
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 0 0 1
0 1 1 1 1 0
1 0 0 0 0 1
1 0 1 1 0 0
1 1 0 0 0 1
1 1 1 1 0 1
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Example of a Sequential Circuit (continued)
c
Present Next
State Input State Output
A B x A B y
0 0 0 0 0 0
0 0 1 0 1 0 a
0 1 0 0 0 1
0 1 1 1 1 0 b a
1 0 0 0 0 1
1 0 1 1 0 0 c
1 1 0 0 0 1
Mealy model
1 1 1 1 0 1
DA = A ⊕ x ⊕ y
A(t + 1) = A ⊕ x ⊕ y
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Example of Sequential Circuit with JK Flip-Flops
1. Persamaan input Flip-Flop :
JA = B KA = Bx'
JB = x' KB = A⊕x
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Example of Sequential Circuit with JK FF (2)
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Example: T Flip-Flops circuit (2)
2. Substitusikan persamaan input equations kedalam persamaan
karakteristik flip-flop untuk memperoleh persamaan state.
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Example: T Flip-Flops circuit (3)
Present Next
State Input State Output
A B x A B y
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 0 1 0
0 1 1 1 0 0
1 0 0 1 0 0
1 0 1 1 1 0
1 1 0 1 1 1
1 1 1 0 0 1
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State Reduction
Goal: reduce the number of states while keeping the external
input-output requirements unchanged.
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State Reduction
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State Reduction
State Reduction Algorithm: Two states are equivalent if,
for each member of the set inputs, they give the same output
and send the circuit to the same state or equivalent state.
Present State Next State Output
x=0 x=1 x=0 x=1
a a b 0 0
b c d 0 0
c a d 0 0
d e f 0 1
e a f 0 1
f e g f 0 1 equivalent states
g a f 0 1
row with present state g is removed, and state g is replaced by state e each time it
occurs.
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State Reduction
State Reduction Algorithm: Two states are equivalent if,
for each member of the set inputs, they give the same output
and send the circuit to the same state or equivalent state.
Present State Next State Output
x=0 x=1 x=0 x=1
a a b 0 0
b c d 0 0
c a d d 0 0
d e f d 0 1
equivalent e a f 0 1
states f e f 0 1
row with present state f is removed, and state f is replaced by state d each time it
occurs.
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State Reduction
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State Coded Binary Assignment
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Sequential Circuits: Design Procedure
Recommended Design Steps
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State Diagram
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Sequence Detector Sequential Circuit
• State table is derived directly from the state diagram.
• We choose 2 D Flip-Flops (outputs A, B)
• There is one input x and one output y
D flip-flop state Equations:
A(t + 1) = D A ( A, B, x) = Σ(3,5,7)
Present Next A(t + 1) = DB ( A, B, x) = Σ(1,5,7)
State Input State Output
y ( A, B, x) = Σ(6,7)
A B x A B y
0 0 0 0 0 0
0 0 1 0 1 0 This state table is the result
0 1 0 0 0 0 of Moore implementation:
0 1 1 1 0 0 output depends on the
present state only.
1 0 0 0 0 0
1 0 1 1 1 0
1 1 0 0 0 1
1 1 1 1 1 1
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Sequence Detector Sequential Circuit
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Sequential Circuit Logic Diagram
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Excitation table
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Synthesis using JK Flip-Flops
In order to determine the input equations for the JK flip-flops, it is necessary
to derive a functional relationship between the state table and the input equations.
Present Next
Input Flip-Flop inputs
State State
A B x A B JA KA JB KB
0 0 0 0 0 0 X 0 X
0 0 1 0 1 0 X 1 X
0 1 0 1 0 1 X X 1
0 1 1 0 1 0 X X 0
1 0 0 1 0 X 0 0 X
1 0 1 1 1 X 0 1 X
1 1 0 1 1 X 0 X 0
1 1 1 0 0 X 1 X 1
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Synthesis using JK Flip-Flops
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Synthesis using JK Flip-Flops
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Synthesis using T Flip-Flops
K-Map ?
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