7/16/2010

COMBINATIONAL CIRCUITS VS.

SEQUENTIAL CIRCUITS
LESSON 1
SYNCHRONOUS SEQUENTIAL
CIRCUITS n Combinational m
inputs Circuit outputs

Latches and Flip-flops

Sequential Circuit Analysis
Designing with Flip-flops (D, RS, JK, T)
Designing with Unused States
Synchronous Counters Block Diagram of a Combinational Circuit

COMBINATIONAL CIRCUITS VS. COMBINATIONAL CIRCUITS VS.

SEQUENTIAL CIRCUITS SEQUENTIAL CIRCUITS

Inputs Outputs
A combinational circuit consists of input variables,

output variables, logic gates, and interconnections.
Combinational
Next State Present State
circuit
A sequential circuit is specified by a time sequence of
Storage inputs, outputs, and internal states.
Elements
asynchronous

synchronous

Block Diagram of a Sequential Circuit

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SEQUENTIAL CIRCUITS SEQUENTIAL CIRCUITS

Two types of Sequential circuits
Synchronization is achieved by a timing device called

Asynchronous sequential circuit

its behavior depends upon the order in which its input
signals change and can be affected at any instant of
time.
clock generator which produces a periodic train of
clock pulses

Synchronous sequential circuits that use clock pulses
as inputs to storage elements are called clocked
sequential circuits

Synchronous sequential circuit
The storage elements used in clocked sequential

is a system whose behavior can be defined from the circuits are called flip-flops
knowledge of its signals at discrete instants of time.

LATCHES SR LATCH WITH NOR GATES

the most basic storage elements from which flip-flops 2

are usually constructed R (Reset) 1 Q
3

two types of Set/Reset (SR) latches

SR latch with NOR gates (NOR latch)

SR latch with NAND gates (NAND latch)
2
1
3 Q'
S (Set)

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SR LATCH WITH NOR GATES SR LATCH WITH NAND GATES

S R Q Q' State 1
S (Set) 3 Q
1 0 1 0 2
Set
0 0 1 0
0 1 0 1
Reset
0 0 0 1 1
1 1 0 0 Undefined 3
Q'
2
R (Reset)

SR LATCH WITH NAND GATES FLIP-FLOPS

A flip-flop is a binary storage device that is

S R Q Q' State capable of storing one bit of information and has
a timing characteristic
0 1 1 0
Set
1 1 1 0
Four known types

RS flip-flop
1 0 0 1
Reset
D flip-flop
1 1 0 1
JK flip-flop

T flip-flop
0 0 1 1 Undefined

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RS FLIP-FLOP D FLIP-FLOP

S 1 S Q 1
3 1 D
Q 3 1
Q
2
2
3
CP SR F/f
2
2
3
D Q
CP CP D F/f
CP R Q’ 1

1
1
3
1
3 2
3
Q' Q’
3 2 Q' 1 2 2

2
R

CP S R Next State of Q CP D Next State of Q

0 X X No change
0 X No change
1 0 0 No change
1 0 1 Q=0; Reset state 1 0 Q=0; Reset state
1 1 0 Q=1; Set state 1 1 Q=1; Set state
1 1 1 Undefined

JK FLIP-FLOP T FLIP-FLOP
T Q
1
2 12 2
K 13 1 Q J Q 1 CP T F/f
3 2 12 2
T 13 1 Q
3
CP CP JK F/f Q’
U5A 2 CP
1
2 12 3
1
Q' K Q’
J 13
1
U5A 2
1
2 12 3 Q'
13

CP J K Next State of Q
0 X X No change CP T Next State of Q
1 0 0 No change
0 X No change
1 0 1 Q=0; Reset state
1 1 0 Q=1; Set state 1 0 No change
1 1 1 Complement 1 1 Complement

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ANALYSIS OF CLOCKED SEQUENTIAL

FLIP-FLOP CHARACTERISTIC TABLES CIRCUITS
Example 1
(a) JK Flip-flop (c) D Flip-flop
J K Q(t+1) State D Q(t+1) State
0 0 Q(t) No change 0 0 Reset A sequential circuit with two D flip-flops, A and B;
0 1 0 Reset 1 1 Set two inputs, x and y; and output, z, is specified by
1 0 1 Set the following next-state and output equations:
1 1 Q'(t) Complement
A(t+1) = x'y + xA
B(t+1) = x'B + xA
(b) SR Flip-flop (d) T Flip-flop
S R Q(t+1) State
z=B
T Q(t+1) State
0 0 Q(t) No change 0 Q(t) No change
0 1 0 Reset 1 Q'(t) Complement (a) Draw the logic diagram of the circuit.
1 0 1 Set
1 1 ? Undefined
(b) Derive the state table.
(c) Derive the state diagram.

SOLUTION - (A) LOGIC DIAGRAM SOLUTION - (B) STATE TABLE

Present State Inputs Next State Output
At Bt x y A(t+1) B(t+1) z
1
3 0 0 0 0 0 0 0
2
0 0 0 1 1 0 0
74LS08
4

1 0 0 1 0 0 0 0
1 2 4 3 2 5 A
X
PR

6 2 D Q 0 0 1 1 0 0 0
5 3
CLK 0 1 0 0 0 1 1
74LS04 74LS32
6 A'
CL

74LS08
Q 0 1 0 1 1 1 1
Y 74LS74
0 1 1 0 0 0 1
1

0 1 1 1 0 0 1
10

1 0 0 0 0 0 0
4
9 6 12 9 B Z 1 0 0 1 1 0 0
PR

8 5 D Q
10 11 1 0 1 0 1 1 0
CLK
74LS32
74LS08 8 B' 1 0 1 1 1 1 0
CL

Q
74LS74 1 1 0 0 0 1 1
13

1 1 0 1 1 1 1
+5V
1 1 1 0 1 1 1
CP
1 1 1 1 1 1 1

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SOLUTION - (C) DIAGRAM SEATWORK

00/0, 10/1, 11/1 A sequential circuit has three D flip-flops, A, B, and

10/0, 00 01 00/1 C, and one input, x. It is described by the
11/0 following flip-flop input functions:
DA = (BC’ + B’C)x + (BC + B’C’)x’
01/0 00/0 01/1 00/1 DB = A
DC = B

01/1,
01/0 10 11 10/1, (a) Derive the state table for the circuit.
10/0, 11/0 11/1 (b) Draw two state diagrams: one for x = 0 and the
other for x = 1.
(30 minutes only)

FLIP-FLOPS OTHER THAN D FLIP-FLOP LOGIC DIAGRAM

Example 2

7
4 15 A 1 2 9 11 B

PR

PR
J Q J Q

A sequential circuit has two JK flip-flops, one 1

CLK
74LS04
6
CLK
16 14 12 10 B'
input x, and one output y. The logic diagram of the

CL

CL
K Q K Q
74LS76 74LS76
circuit is shown below. Derive the state table and

8
the state diagram of the circuit. CP
4
1 6 y
3 5
2
x 74LS136
74LS136

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(A) STATE TABLE

SOLUTION
Present

The first thing to do, when a logic diagram is State Input Next State Output Flip-flop Inputs
given, is to obtain the flip-flop input and output
functions. These are the ff.: At Bt x At+1 Bt+1 y JA KA JB KB
JA = B KA = B’ 0 0 0 0 1 0 0 1 1 1
JB = (Ax’ + A’x)’ = A xnor x 0 0 1 0 0 1 0 1 0 0
KB = (Ax’ + A’x)’ = A xnor x 0 1 0 1 1 1 1 0 1 1
y = ((A'x + Ax') + B') + ((A'x + Ax')' + B)
0 1 1 1 0 0 1 0 0 0
= A xor x xor B
1 0 0 0 0 1 0 1 0 0

To plot the next-state values in the state table, use 1 0 1 0 1 0 0 1 1 1
the characteristic table of the JK flip-flop. 1 1 0 1 0 0 1 0 0 0
1 1 1 1 1 1 1 0 1 1

(B) STATE DIAGRAM SEATWORK

A sequential circuit has two JK flip-flops, A and
0/0 B; two inputs, x and y; and one output, z. The
1/1 00 01 flip-flop input functions and the circuit output
function are as follows:
1/0 JA = Bx + B’y’ KA = B’xy’
JB = A’x KB = A + xy’
0/1 0/1
1/0 z = Axy + Bx’y’

(a) Draw the logic diagram of the circuit.

(b) Tabulate the state table.
10 11 1/1 (c) Derive the next-state equations for A and B.
0/0 (30 minutes only)

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STATE REDUCTION
REDUCED STATE TABLE
Example:
Present Next State Output Present Next State Output
State x=0 x=1 x=0 x=1 State x=0 x=1 x=0 x=1
a a b 0 0 a a b 0 0
b c d 0 0 b c d 0 0
c a d 0 0 c a d 0 0
d e f 0 1 d e d 0 1
e a f 0 1 e a d 0 1
f g f 0 1
g a f 0 1

State table to reduce

STATE ASSIGNMENT REDUCED STATE TABLE WITH BINARY

ASSIGNMENT 1
State Assignment 1 Assignment 2 Assignment 3
a 001 000 000 Present Next State Output
b 010 010 100 State x=0 x=1 x=0 x=1
c 011 011 010 001 001 010 0 0
d 100 101 101 010 011 100 0 0
e 101 111 011 011 001 100 0 0
100 101 100 0 1
101 001 100 0 1

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EXAMPLE FLIP-FLOP EXCITATION TABLES

Reduce the number of states in the following state table and Q(t) Q(t+1) S R Q(t) Q(t+1) J K
tabulate the reduced state table. 0 0 0 X 0 0 0 X
0 1 1 0 0 1 1 X
Present Next State Output
1 0 0 1 1 0 X 1
State x=0 x=1 x=0 x=1
1 1 X 0 1 1 X 0
a f b 0 0
(a) RS flip-flop (b) JK flip-flop
b d c 0 0
c f e 0 0
Q(t) Q(t+1) D Q(t) Q(t+1) T
d g a 1 0
0 0 0 0 0 0
e d c 0 0
0 1 1 0 1 1
f f b 1 1
1 0 0 1 0 1
g g h 0 1
1 1 1 1 1 0
h g a 1 0
(c) D flip-flop (d) T flip-flop

DESIGN PROCEDURE DESIGN PROCEDURE

1. The word description of the circuit behavior is 5. Determine the number of flip-flops needed and
stated. assign a letter symbol to each.
2. From the given information about the circuit, 6. Choose the type of flip-flop to be used.
obtain the state table. 7. From the state table, derive the circuit excitation
3. The number of states may be reduced by state- and output tables.
reduction methods if the sequential circuit can 8. Using the map or any other simplification method,
be characterized by input-output relationships
independent of the number of states. derive the circuit output functions and the flip-
flop input functions.
4. Assign binary values to each state if the state
table obtained in step 2 or 3 contains letter 9. Draw the logic diagram.
symbols.

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STATE DIAGRAM FOR THE STATE TABLE

DESIGN EXAMPLE

1 Next State
0 00 11 0 Present State x=0 x=1
A B A B A B
0 0 0 0 0 1
1 1 0 1 1 0 0 1
1 0 1 0 1 1
1 1 1 1 0 0
1 0
01 10
0

EXCITATION TABLE K-MAPS FOR THE CIRCUIT

Bx Bx
Inputs of Outputs of
Combinational Circuit Combinational Circuit A 00 01 11 10 A 00 01 11 10
Present State Input Next State Flip-flop Inputs 0 1 0 X X X X
A B x A B JA KA JB KB 1 X X X X 1 1

0 0 0 0 0 0 X 0 X JA = Bx’ KA = Bx
0 0 1 0 1 0 X 1 X
0 1 0 1 0 1 X X 1 Bx Bx
0 1 1 0 1 0 X X 0 A 00 01 11 10 A 00 01 11 10
1 0 0 1 0 X 0 0 X 0 1 X X 0 X X 1
1 0 1 1 1 X 0 1 X 1 1 X X 1 X X 1
1 1 0 1 1 X 0 X 0 JB = x KB = A’x’ + Ax
1 1 1 0 0 X 1 X 1

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LOGIC DIAGRAM SEATWORK

Design a sequential circuit with two JK flip-flops, A

11

10

15

14
B B' A A'
and B, and two inputs, E and x. If E = 0, the circuit

Q
7 8 2 3
PR CL PR CL
remains in the same state regardless of the value of

CLK

CLK
K

K
x. When E = 1 and x = 1, the circuit goes through the

J
12

16
state transitions from 00 to 01 to 10 to 11 back to 00,
9

1
CP and repeats. When E = 1 and x = 0, the circuit goes

3
through the state transitions from 00 to 11 to 10 to
01 back to 00, and repeats.

(30 minutes only)

2

1
1 2
x

DESIGN WITH D FLIP-FLOPS MAPS FOR INPUT AND OUTPUT FUNCTIONS

Design a clocked sequential circuit that operates according to
the state table shown. Flip-flop input functions from Bx
the state table: A 00 01 11 10
Present State Input Next State Output DA(A, B, x) = Σ(2, 4, 5, 6) 0 1
A B x A B y DB(A, B, x) = Σ(1, 3, 5, 6) 1 1 1 1
0 0 0 0 0 0 y(A, B, x) = Σ(1, 5) DA = AB’ + Bx’
0 0 1 0 1 1
0 1 0 1 0 0 Bx Bx
0 1 1 0 1 0 A 00 01 11 10 A 00 01 11 10
1 0 0 1 0 0 0 1 1 0 1
1 0 1 1 1 1 1 1 1 1 1
1 1 0 1 1 0 DB = A’x + B’x + ABx’ y = B’x
1 1 1 0 0 0

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LOGIC DIAGRAM DESIGN WITH UNUSED STATES

1
3 Present State Input Next State Flip-flop Inputs Output

4
2 1
3 2 5
A

PR
x 2 D Q A B C x A B C SA RA SB RB SC RC y
1 2 1 3
3 CLK
2 6
A' 0 0 1 0 0 0 1 0 X 0 X X 0 0

CL
Q

0 0 1 1 0 1 0 0 X 1 0 0 1 0

1
0 1 0 0 0 1 1 0 X X 0 1 0 0
1
3
0 1 0 1 1 0 0 1 0 0 1 0 X 0
2
0 1 1 0 0 0 1 0 X 0 1 X 0 0

10
1 1
3 2 9 12 9
B 0 1 1 1 1 0 0 1 0 0 1 0 1 0

PR
2 8 D Q
11
CLK
B' 1 0 0 0 1 0 1 X 0 0 X 1 0 0
1 8

CL
2 12 Q
13 1 0 0 1 1 0 0 X 0 0 X 0 X 1

13
CP
y
1 0 1 0 0 0 1 0 1 0 X X 0 0
1 0 1 1 1 0 0 X 0 0 X 0 1 1

MAPS FOR FLIP-FLOP INPUTS

Cx
Cx Cx
AB 00 01 11 10
AB 00 01 11 10 AB 00 01 11 10
00 X X
00 X X 00 X X X X MAPS FOR FLIP-FLOP 01
01 1 1 01 X X
INPUTS AND OUTPUTS 11 X X X X
11 X X X X 11 X X X X
10 1 1
10 X X X 10 1
y = Ax
SA = Bx RA = Cx’
Cx Cx
Cx Cx
AB 00 01 11 10 AB 00 01 11 10
AB 00 01 11 10 AB 00 01 11 10
00 X X X 00 X X 1
00 X X 1 00 X X X
01 1 X 01 X 1
01 X 01 1 1 1
11 X X X X 11 X X X X
11 X X X X 11 X X X X
10 1 X 10 X 1
10 10 X X X X
SC = x’ RC = x
SB = A’B’x RB = BC + Bx

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LOGIC DIAGRAM W/ RS FLIP-FLOPS STATE DIAGRAM

12
1 11
x 3 S Q
A 13 0/0
2
y
0/0
CP 001
1 2 4
6
R Q' A' 0/0 000
5 0/0 1/0
0/0
1/0
1
2
13
12 S Q B 101 011 010
CP 0/0
1
9 3 R Q' B' 0/0 1/0 1/0
10
8 2 1/1 110

1/1 0/0
S Q C 100
1/1
CP 1/1
R Q' C' 111
CP

SEATWORK DESIGN OF COUNTERS

Design the sequential circuit specified by the state
Present State Next State Flip-flop inputs
diagram below using RS flip-flops.
000 111 A B C A B C TA TB TC
(30 minutes only)
0/0 0 0 0 0 0 1 0 0 1
0 0 1 0 1 0 0 1 1
1/1 001 0/0 0 1 0 0 1 1 0 0 1
001 110
1/0 0 1 1 1 0 0 1 1 1
101 010
0/0 1 0 0 1 0 1 0 0 1
0/0 1/1
010 101 1 0 1 1 1 0 0 1 1
1/1 011 0/0 1 1 0 1 1 1 0 0 1
1 1 1 0 0 0 1 1 1
1/1
011 100
100

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MAPS FOR 3-BIT BINARY COUNTER LOGIC DIAGRAM OF A 3-BIT BINARY COUNTER

T Q
A
BC Bx
A 00 01 11 10 A 00 01 11 10 CP

3
0 1 0 1 1 Q'
1 1 1 1 1
TA = BC TB = C T Q B
CP

2
Bx Q'
A 00 01 11 10
1 T Q C
0 1 1 1 1
CP
1 1 1 1 1
Q'
TC = 1
CP

COUNTER W/ NONBINARY SEQUENCE STATE DIAGRAM AND LOGIC DIAGRAM OF

Present State Next State Flip-flop Inputs COUNTER
A
A B C A B C JA KA JB KB JC KC J Q
0 0 0 0 0 1 0 X 0 X 1 X CP
000 111 K Q'
0 0 1 0 1 0 0 X 1 X X 1
0 1 0 1 0 0 1 X X 1 0 X
1 0 0 1 0 1 X 0 0 X 1 X 001 110 J Q
CP B
1 0 1 1 1 0 X 0 1 X X 1
K Q'
1 1 0 0 0 0 X 1 X 1 0 X
010 101
The simplified functions are: J Q
JA = B KA = B CP C
100 011 K Q'
JB = C KB = 1
JC = B’ KC = 1 1 CP

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SEATWORK
Design the following nonbinary sequence counters as
specified in each case. Treat the unused states as don’t-
care conditions. Analyze the final circuit to ensure that
it is self-correcting. If your design produces a nonself-
correcting counter, you must modify the circuit to make it
self-correcting.

(a) Design a counter with the following repeated binary

sequence: 0, 1, 2, 3, 4, 5, 6. Use JK flip-flops.
(b) Design a counter with the following repeated binary
sequence: 0, 1, 2, 4, 6. Use D flip-flops.
(c) Design a counter with the following repeated binary
sequence: 0, 1, 3, 5, 7. Use T flip-flops.
(d) Design a counter with the following repeated binary
sequence: 0, 1, 3, 7, 6, 4. Use T flip-flops.

(45 minutes only)

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