Evaluation Board TSC695

..............................................................................................

User Guide
 Table of Contents

Section 1
Introduction ........................................................................................... 1-1
1.1 Description ................................................................................................1-1
1.2 Features ....................................................................................................1-1

Section 2
Processor.............................................................................................. 2-5
2.1 Processor Package ...................................................................................2-5
2.3 Data Buffers Control..................................................................................2-7
2.4 Processor Socket Part Number.................................................................2-8
2.5 Emulation Capability .................................................................................2-8
2.6 Debug Jumper ..........................................................................................2-8
2.7 PROM8 Jumper ........................................................................................2-8

Section 3
ROM (or Flash) ................................................................................... 3-11
3.1 Flash 8-bit ...............................................................................................3-11
3.2 Flash 40-bit .............................................................................................3-11
3.4 Flash - Expansion SIMM .........................................................................3-13
3.5 Example of Flash - Expansion SIMM ......................................................3-14

Section 4
RAM .................................................................................................... 4-15
4.1 RAM - Bank 0..........................................................................................4-15
4.2 RAM - Bank 1..........................................................................................4-15
4.4 RAM - Expansion SIMM B ......................................................................4-16
4.5 Example of RAM - Expansion SIMM.......................................................4-17

Section 5
FPGA .................................................................................................. 5-19
5.1 FPGA Part Number .................................................................................5-19
5.2 FPGA Socket Part Number .....................................................................5-19
5.3 FPGA Pin-out ..........................................................................................5-20
5.4 FPGA Clocks...........................................................................................5-22
5.5 FPGA Downloading.................................................................................5-23

Section 6
DMA.................................................................................................... 6-25

Section 7
TSC695 Power & Clock ...................................................................... 7-27
7.1 TSC695 Power........................................................................................7-27
7.2 TSC695 Clocks .......................................................................................7-27

Evaulation Board TSC695 User Guide 1

4139G–AERO–11/05
 Table of Contents

Section 8
Reset, HALT, EWDINT and Status LED’s .......................................... 8-29
8.1 RESET ....................................................................................................8-29
8.2 HALT .......................................................................................................8-30
8.3 EWDINT ..................................................................................................8-31
8.4 Status LED’s ...........................................................................................8-31

Section 9
Test Points .......................................................................................... 9-33

Section 10
Logic Analizer POD’s ........................................................................ 10-35
10.1 POD 1 ...................................................................................................10-35
10.2 POD 2 ...................................................................................................10-36

Section 11
Serial Links ....................................................................................... 11-39
11.1 Serial A .................................................................................................11-39
11.2 Serial B .................................................................................................11-39
11.3 SUN Connection ...................................................................................11-40
11.4 PC Connection ......................................................................................11-41

Section 12
Tap Connector .................................................................................. 12-43

Section 13
Expansion Connectors...................................................................... 13-45
13.1 3 x 32 points connector - P1 .................................................................13-45
13.2 3 x 32 points connector - P2 .................................................................13-46
13.3 3 x 32 points connector - P3 .................................................................13-47

Section 14
Board Implementation....................................................................... 14-49

Section 15
Deviations ......................................................................................... 15-51
15.1 CB[6:0] and DPAR on FPGA ................................................................15-51
15.2 Reset and HALT Driven by JTAG Connector........................................15-51
15.3 TSC695 Signals on FPGA ....................................................................15-51

Section 16
Schematics ....................................................................................... 16-53

Section 17
Document History ............................................................................. 17-73

Evaulation Board TSC695 User Guide 2

4139G–AERO–11/05
 Section 1
Introduction

1.1 Description The eVAB-695 is a board used to evaluate and demonstrate the TSC695 32-bit RISC
embedded processor implementing the SPARC architecture V7 specification.
The TSC695 includes on chip an Integer Unit (IU), a Floating Point Unit (FPU), a Mem-
ory Controller and a DMA Arbiter. For Real Time applications, the TSC695 offers a high
security Watch Dog, two Timer’s, an Interrupt Controller, Parallel and Serial interfaces.
Fault tolerance is supported using specific parity on internal/external buses and an
EDAC on the external data bus. The design is highly testable with the support of an On-
Chip Debugger (OCD), an internal and boundary scan through JTAG interface.
This board is based on the TSC695, a ROM space, a SRAM space and DPRAM space.
Several extension connectors and a large range of memory mapping produces an high
flexibility to the evaluation or the demonstration. Free user interfaces are also proposed
to customize the application.

1.2 Features The eVAB-695 board is designed in standard VME. It is a board in B / 2U format (23.3 x
16 cm or 9.2 x 6.3 inches). The rear and front 96-pin connectors only respect the power
lines of the VME bus.
1.2.1 Processor The TSC695 includes all the major features (except co-processor implementation and
master/checker mode) of the ERC32 chip-set. The component can be divided in six
blocks:
• IU based on SPARC V7.0 architecture
• FPU compliant to ANSI/IEEE 754 standard
• specific memory controller
• slave DMA arbiter
• seven peripherals:
– 1 watchdog (or NMI)
– 2 timers
– 1 interrupt controller
– 1 GPI
– 2 UART’s
• JTAG controller with OCD
1.2.2 ROM The eVAB-695 can have either a 8-bit boot-Flash for 512 Kbytes of code either a 40-bit
boot-Flash for 2 Mbytes of code.
Up to 4M bytes of code using one SIMM module can be mounted as ROM expansion.
The eVAB-695 is equipped with RDBmon a remote debugger.

Evaluation Board TSC695 User Guide 1-1

Rev. 4139G–AERO–11/05
Introduction

1.2.3 RAM The eVAB-695 have 2 banks of 40-bit SRAM for 2 Mbytes of data/code each.
Up to 8M bytes of data/code using 2 SIMM modules can be mounted as RAM
expansion.
1.2.4 FPGA The board is provided without FPGA. A capability is given to mount an ALTERA 10K50
FPGA on board.
Note: The FPGA interface has been used by Atmel for internal prototyping needs. It
has only been partially validated.
The FPGA area receives all signals of the TSC695 except for the address and data
buses. The FPGA receives the address and data buffered buses. Some other FPGA
I/O’s are connected to the expansion connectors.
The FPGA is downloaded via either a serial PROM (not provided), either via the Bit-
Blaster connector.

1.2.5 Expansion 3 expansion connectors are provided. P1 and P2 are reserved for system expansion
Connectors (processor emulation, DMA, exchange RAM, ...) and P3 is dedicated for I/O expansion.
1.2.6 Debugging • 1 connector TAP-JTAG for hardware debugging
• 4 x 34-bit pods for logic analysis
• 32 couples of signal/Gnd for test points
• system halt input
• NMI input (cf EWDINT)

1.2.7 Power The eVAB-695 can be powered (Vcc board) in 5 or 3.3 volts with a proper choice of
components.
Each of the TSC695 Vcc core (VccI) and the TSC695 Vcc buffers (VccO) can be pow-
ered separately from the Vcc board.

1-2 Evaluation Board TSC695 User Guide

4139G–AERO–11/05
 Introduction

1.3 Board Block

Diagram

Figure 1-1. Board Block Diagram

Expansion Connector P1 Expansion Connector P2

MDMAREQ/MDMAGNT
695E (*)
4 x 34-bit
Interface
Memory

MEM & I/O Ctrl

RAM Ctrl
FPGA pods
RASI...
FPU

BD[39:0]
BRA[31:0]
D[39:0]
RA[31:0]

Boot ROM 1
SYSCLK
ALE

DMA

Boot ROM 2 SIMM

IU DMA

RAM Bank[1,0]

Internal
Peripherals Bank[m,n] SIMM A
RAM Bank[r, s]
SIMM B
(*)
CLK Serial
&
Reset FPGA Area PROM

LSa LSb TAP I/O Connector P3 BitBlaster

The processor TSC695 is placed in the centre of the board to be compatible with the
SEU test equipment.
The serial A and B connectors, the RESET and HALT switches and the LED’s for board
status are placed on the left of P3 on the front side. P1 and P2 are placed on rear side.

Evaluation Board TSC695 User Guide 1-3

4139G–AERO–11/05
 Section 2
Processor

2.1 Processor The processor is the TSC695. The package used is the package provided to customers,
Package the 256-pin MQFP-F package. This component is mounted on a special support, with a
chip-carrier. The component is placed bottom to top in its support. An hole is made on
the board, under the component, to access the die when the lid is removed (SEU tests).

Figure 2-1. TSC695 Top View

GPINT

VCCO

VCCO

VCCO

VCCO

VCCO

VCCO

VCCO

VCCO

VCCO

VCCO
GPI[7]

GPI[6]
GPI[5]
GPI[4]
GPI[3]

GPI[2]
GPI[1]
GPI[0]
VSSO

VSSO

VSSO

VSSO

VSSO

VSSO

VSSO

VSSO

VSSO

VSSO
D[31]
D[30]

D[29]
D[28]
VCCI
D[27]
D[26]

D[25]
D[24]
D[23]
D[22]

D[21]
D[20]
D[19]
D[18]

D[17]
D[16]
VCCI
D[15]
D[14]

D[13]
D[12]
D[11]
D[10]
VSSI

VSSI

D[9]
D[8]
D[7]
D[6]

D[5]
D[4]
D[3]
D[2]

D[1]
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
1
2
3
4
5
6
7
8
9

RTC 256 65 RSIZE[1]

INST 255 66 RSIZE[0]
FLUSH 254 67 RASI[3]
VSSO 253 68 VCCO
VCCO 252 69 VSSO
DIA 251 70 RASI[2]
INULL 250 71 RASI[1]
DEBUG 249 72 RASI[0]
TMODE[0] 248 73 RA[31]
TMODE[1] 247 74 RA[30]
EWDINT 246 75 VCCO
IWDE 245 76 VSSO
WDCLK 244 77 RA[29]
MDS 243 78 RA[28]
MHOLD 242 79 RA[27]
DDIR 241 80 VCCO
VSSO 240 81 VSSO
VCCO 239 82 RA[26]
DDIR 238 83 RA[25]
BUFFEN 237 84 RA[24]
MEMWR 236 85 VCCI
VSSO 235 86 VSSI
VCCO 234 87 VCCO
OE 233 88
VSSI VSSO
232 89
VCCI RA[23]
231 90

TSC695
MEMCS[0] 230 RA[22]
91
MEMCS[1] 229 92 RA[21]
MEMCS[2] 228 93 VCCO
VSSO 227 94 VSSO
VCCO 226 95 RA[20]
MEMCS[3] 225 96 RA[19]
MEMCS[4] 224 97 RA[18]
MEMCS[5] 223 98 VCCO
MEMCS[6]
MEMCS[7]
MEMCS[8]
VSSO
222
221
220
219
(top view) 99
100
101
102
VSSO
RA[17]
RA[16]
RA[15]
VCCO 218 103 VCCO
MEMCS[9] 217 104 VSSO
ROMCS 216 105 RA[14]
PROM8 215 106 VCCI
VSSI 214 107 VSSI
VCCI 213 108 RA[13]
ALE 212 109 RA[12]
CB[0] 211 110 VCCO
VSSO 210 111 VSSO
VCCO 209 112 RA[11]
CB[1] 208 113 RA[10]
CB[2] 207 114 RA[9]
CB[3] 206 115 VCCO
CB[4] 205 116 VSSO
VSSO 204 117 RA[8]
VCCO 203 118 RA[7]
CB[5] 202 119 RA[6]
CB[6] 201 120 VCCO
BA[0] 200 121 VSSO
BA[1] 199 122 RA[5]
SYSRESET 198 123 RA[4]
RESET 197 124 RA[3]
VSSO 196 125 VCCO
VCCO 195 126 VSSO
MEXC 194 127 RA[2]
DXFER 193 128 RA[1]
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
RLDSTO

VSSO
VCCO

WRT

VSSO
VCCO

VSSO
VCCO

VSSO
VCCO
CPUHALT
SYSHALT

ROMWRT

DMAGNT
DMAREQ

VSSO
VCCO

TRST
CLK2

TDO

VSSO
VCCO

VSSO
VCCO
RD

IOWR

CPAR

IUERR

SYSERR

NOPAR

BUSERR

DPAR
RASPAR
RAPAR
LOCK

WE

IOSEL[0]
IOSEL[1]
IOSEL[2]

IOSEL[3]

TxB
RxB
RxA
TxA

EXTINTACK
VSSI
VCCI
EXTINT[0]
EXTINT[1]
EXTINT[2]
EXTINT[3]
EXTINT[4]
SYSAV

BUSRDY

VSSI
VCCI
EXMCS

DMAAS
DRDY

TCK
TDI
TMS

SYSCLK

RA[0]

Evaluation Board TSC695 User Guide 2-5

Rev. 4139G–AERO–11/05
Processor

2.2 Processor Pin-

Out Table 2-1. TSC695 Pin-out
Pin Signal Pin Signal Pin Signal Pin Signal
1 GPIINT 65 D[0] 129 RA[0] 193 DXFER
2 GPI[7] 66 RSIZE[1] 130 VCCO 194 MEXC ]
3 VCCO 67 RSIZE[0] 131 VSSO 195 VCCO
4 VSSO 68 RASI[3] 132 RAPAR 196 VSSO
5 GPI[6] 69 VCCO 133 RASPAR 197 RESET ]
6 GPI[5] 70 VSSO 134 DPAR 198 SYSRESET ]
7 GPI[4] 71 RASI[2] 135 VCCO 199 BA[1]
8 GPI[3] 72 RASI[1] 136 VSSO 200 BA[0]
9 VCCO 73 RASI[0] 137 SYSCLK 201 CB[6]
10 VSSO 74 RA[31] 138 TDO 202 CB[5]
11 GPI[2] 75 RA[30] 139 TRST ] 203 VCCO
12 GPI[1] 76 VCCO 140 TMS 204 VSSO
13 GPI[0] 77 VSSO 141 TDI 205 CB[4]
14 D[31] 78 RA[29] 142 TCK 206 CB[3]
15 D[30] 79 RA[28] 143 CLK2 207 CB[2]
16 VCCO 80 RA[27] 144 DRDY ] 208 CB[1]
17 VSSO 81 VCCO 145 DMAAS 209 VCCO
18 D[29] 82 VSSO 146 VCCO 210 VSSO
19 D[28] 83 RA[26] 147 VSSO 211 CB[0]
20 VCCI 84 RA[25] 148 DMAGNT ] 212 ALE ]
21 VSSI 85 RA[24] 149 EXMCS ] 213 VCCI
22 D[27] 86 VCCI 150 VCCI 214 VSSI
23 D[26] 87 VSSI 151 VSSI 215 PROM8 ]
24 VCCO 88 VCCO 152 DMAREQ ] 216 ROMCS ]
25 VSSO 89 VSSO 153 BUSERR ] 217 MEMCS[9] ]
26 D[25] 90 RA[23] 154 BUSRDY ] 218 VCCO
27 D[24] 91 RA[22] 155 ROMWRT ] 219 VSSO
28 D[23] 92 RA[21] 156 NOPAR ] 220 MEMCS[8] ]
29 D[22] 93 VCCO 157 SYSHALT ] 221 MEMCS[7] ]
30 VCCO 94 VSSO 158 CPUHALT ] 222 MEMCS[6] ]
31 VSSO 95 RA[20] 159 VCCO 223 MEMCS[5] ]
32 D[21] 96 RA[19] 160 VSSO 224 MEMCS[4] ]
33 D[20] 97 RA[18] 161 SYSERR ] 225 MEMCS[3] ]
34 D[19] 98 VCCO 162 SYSAV 226 VCCO
35 D[18] 99 VSSO 163 EXTINT[4] 227 VSSO
36 VCCO 100 RA[17] 164 EXTINT[3] 228 MEMCS[2] ]
37 VSSO 101 RA[16] 165 EXTINT[2] 229 MEMCS[1] ]
38 D[17] 102 RA[15] 166 EXTINT[1] 230 MEMCS[0] ]
39 D[16] 103 VCCO 167 EXTINT[0] 231 VCCI
40 VCCI 104 VSSO 168 VCCI 232 VSSI
41 VSSI 105 RA[14] 169 VSSI 233 OE ]
42 D[15] 106 VCCI 170 EXTINTACK 234 VCCO
43 D[14] 107 VSSI 171 IUERR ] 235 VSSO
44 VCCO 108 RA[13] 172 VCCO 236 MEMWR ]
45 VSSO 109 RA[12] 173 VSSO 237 BUFFEN ]
46 D[13] 110 VCCO 174 CPAR 238 DDIR
47 D[12] 111 VSSO 175 TXA 239 VCCO
48 D[11] 112 RA[11] 176 RXA 240 VSSO
49 D[10] 113 RA[10] 177 RXB 241 DDIR ]
50 VCCO 114 RA[9] 178 TXB 242 MHOLD ]
51 VSSO 115 VCCO 179 IOWR ] 243 MDS ]
52 D[9] 116 VSSO 180 IOSEL[3] ] 244 WDCLK
53 D[8] 117 RA[8] 181 VCCO 245 IWDE
54 D[7] 118 RA[7] 182 VSSO 246 EWDINT
55 D[6] 119 RA[6] 183 IOSEL[2] ] 247 TMODE[1]
56 VCCO 120 VCCO 184 IOSEL[1] ] 248 TMODE[0]
57 VSSO 121 VSSO 185 IOSEL[0] ] 249 DEBUG
58 D[5] 122 RA[5] 186 WRT 250 INULL
59 D[4] 123 RA[4] 187 WE ] 251 DIA
60 D[3] 124 RA[3] 188 VCCO 252 VCCO
61 D[2] 125 VCCO 189 VSSO 253 VSSO

2-6 Evaluation Board TSC695 User Guide

4139G–AERO–11/05
 Processor

Table 2-1. TSC695 Pin-out (Continued)

Pin Signal Pin Signal Pin Signal Pin Signal
62 VCCO 126 VSSO 190 RD 254 FLUSH
63 VSSO 127 RA[2] 191 RLDSTO 255 INST
64 D[1] 128 RA[1] 192 LOCK 256 RTC

2.3 Data Buffers

Control

Figure 2-2. Data Buffers Control Schematic

BD [31:0]
BCB [6:0] | BDPAR

U22 U23 U24 U25 U26

xx245 xx245 xx245 xx245 xx245

G3 G3 G3 G3 G3

CB [6:0] | DPAR
D [31:0]
FPGA - C6

EXT_D_BUFFEN
P2 - C24
EXT_C_BUFFEN
2 1 P2 - C23
FPGA - C7
4 3
BUFFEN BUFFEN
TSC695 - 237 6 5 P2 - B30
POD3 - pin26 FPGA - AD4
J32

Figure 2-3. Data Buffers Control Configuration

J28 J20
J6 J32
EXT_D_BUFFEN 2 1 EXT_C_BUFFEN
J5 J4
DATA_BUFFEN 4 3 CB_BUFFEN
U7 J18

J32
BUFFEN 6 5 BUFFEN
J19
U8

U9 U1 Data Check

Controled by mP J32 / 3-5 J32 / 4-6

Controled by P2
J32 / 3-1 J32 / 4-2
or FPGA

Evaluation Board TSC695 User Guide 2-7

4139G–AERO–11/05
Processor

2.4 Processor The socket used for the TSC695 device is made by ENPLAS (www.enplas.com).
Socket Part The socket reference is: FPQ-256-0.508-01.
Number The chip carrier reference is: CA-256-0.508-01.

2.5 Emulation Excepted for TMODE[1,0], DEBUG, ROMWRT ], NOPAR ] and JTAG port, all TSC695
Capability signals are available on P1 & P2 connectors. In this way, an emulation of the processor
(support empty) can be done through P1 & P2 (ex: MCM or ERC32 chip-set).

2.6 Debug Jumper The debug jumper drives directly the TSC695 input pin "DEBUG" to Vcc or Gnd.

Figure 2-4. Processor - Debug Jumper

J28J20
J6
J19

U7 J5 J4 1 ON
J18 Debug On J19 / 1-2
2 DEBUG
U8 J19 OFF Debug Off J19 / 2-3
3

U9 U1

2.7 PROM8 Jumper The PROM8 jumper drives directly the TSC695 input pin "PROM8" to Vcc or Gnd.

Figure 2-5. Processor - PROM8 jumper

J20
J7

PROM8
J4 U13 U14 U15
ON OFF PROM8 J8 / 2-3
J8 J8 PROM40 J8 / 1-2
J30 U12
3 2 1
U1 J29 J14
U28

2-8 Evaluation Board TSC695 User Guide

4139G–AERO–11/05
 Processor

2.8 Parity Jumper The PARity jumper drives directly the TSC695 input pin "NOPAR" to Vcc or Gnd.

Figure 2-6. Processor - Parity jumper

J4 U13 U14 U15

J9
J8
J30 U12
1 ON
J29 Parity On J9 / 1-2
J14 2 PARity
U1 U28 Parity Off J9 / 2-3
3 OFF
J9
U27

Evaluation Board TSC695 User Guide 2-9

4139G–AERO–11/05
 Section 3
ROM (or Flash)

128K x 8 or 512K x 8 components can be used. PROM’s, EPROM’s or Flash devices

are available. The capacity must be correctly programmed in the Memory Configuration
Register (field psiz) of the TSC695. The capacity will be the total of the on board capac-
ity included the expansion SIMM module.
The on-board ROM’s are placed in sockets.

3.1 Flash 8-bit It is possible to use the 8-bit mode. The device to be use is a 32-pin PLCC and is
located in U12.

Table 3-1. Flash 8-bit Configuration

Capacity (8-bit Mode)
128K x 8
128K bytes of code
Ex: using Flash 29F010
512K x 8
512K bytes of code
Ex: using Flash 29F040

3.2 Flash 40-bit It is possible to use the 40-bit mode. The devices to be used are 32-pin PLCC and are
located in U14 for byte 3 D[24:31], in U15 for byte 2 D[16:23], in U16 for byte 2 D[8:15], in U17
for D[0:7]byte 20, Parity on D7 of U13 (MSB), CB [0:6] of U13.

Table 3-2. Flash 40-bit Configuration

Capacity (40-bit Mode)
128K x 8
512K bytes of code
Ex: using Flash 29F010
512K x 8
2M bytes of code
Ex: using Flash 29F040

Evaluation Board TSC695 User Guide 3-11

Rev. 4139G–AERO–11/05
ROM (or Flash)

3.3 Flash 8-bit/ If no FPGA is implemented, the Flash 8-bit and the Flash 40-bit cannot be present at the
Flash 40-bit same time. Only the decoding made in FPGA can allow the presence of both the Flash
Selection 8-bit and the Flash 40-bit.

3.3.1 Schematic

Figure 3-1. Flash 8-bit / Flash 40-bit Selection Schematic

J8
off 1 Other conditions
215 C5 H26
PROM8 2 BOOTROM1_40_CS
on 3
BOOTROM1_8_CS
TSC695 C4 2 1
PROM8 J2 Flash_8_CS
FPGA J16 4 3
Flash_40_CS
ROMCS 216
6 5
FlashCS

3.3.2 FlashCS Jumper

Figure 3-2. FlashCS Jumper Configuration

U14 U15 U16 J16

BOOTROM1_8_CS 2 1 BOOTROM1_40_CS
J30
U12 U17 Flash_8_CS 4 3 Flash_40_CS
J14
J31 J16 ROMCS 6 5 ROMCS
U28

J9

J3 FPGA configured J16 / 1-3 J16 / 2-4

J29 U27 No FPGA J16 / 3-5 J16 / 4-6

3-12 Evaluation Board TSC695 User Guide

4139G–AERO–11/05
 ROM (or Flash)

3.3.3 Flash 8-bit Write In ROM8-bit mode, the input write signal of the Flash (U12) can be powered either by
MEMWR either by WR.

Figure 3-3. Flash 8-bit Write Jumper Configuration

J20
J7

J30
J4 U13 U14 U15 1 MEMWR WR_U12 = MEMWR J30 / 1-2
2 WR_U12
J8 WR_U12 = WR J30 / 2-3
J30 U12 3 WR
U1 J29 J14
U28

3.4 Flash - Up to 4M bytes of code using a 72-pin SIMM proprietary module on connector can be
Expansion SIMM mounted as Flash (ROM) expansion on the J3 connector.

3.4.1 Flash - Expansion The operating mode is the mode selected in boot ROM space (ROM_8 or ROM_40).
SIMM selection
„ If no FPGA is implemented, the Flash 8-bit and the Flash 40-bit cannot be present in
the same time in the SIMM expansion. The on-SIMM Flash’s selection can be made
by ROMCS signal using J31 connector.
„ If FPGA is implemented, the on-SIMM Flash can be selected either by the
BOOTROM2_8_CS (FPGA pin J4) or BOOTROM2_40_CS (FPGA pin J3) signals
coming from the FPGA. J31 connector is used for the selection. Only a decoding
made in FPGA can allow the presence on SIMM of both a Flash 8-bit and a Flash 40-
bit.

3.4.2 Schematic

Figure 3-4. Flash - Expansion SIMM Selection Schematic

J8
off 1 Other conditions
215 2 C5 J3
PROM8 BOOTROM2_40_CS
on 3
BOOTROM2_8_CS
TSC695 C4 2 1
PROM8 J4 SIMM_8_CS
FPGA J31 4 3
SIMM_40_CS
ROMCS 6 5
216
On-SIMM
FlashCS

Evaluation Board TSC695 User Guide 3-13

4139G–AERO–11/05
ROM (or Flash)

Figure 3-5. Flash - Expansion SIMM Selection

U14 U15 U16 J31

BOOTROM2_8_CS 2 1 BOOTROM2_40_CS
J30
U12 U17 SIMM_8_CS 4 3 SIMM_40_CS
J14 J31 J16 ROMCS 6 5 ROMCS
U28

J9

J3 FPGA configured J31 / 1-3 J31 / 2-4

J29 U27 No FPGA J31 / 3-5 J31 / 4-6

3.4.3 Flash - Expansion This pin-out is compatible to the SIMM module of SRAM expansion.
SIMM pin-out
„ Bottom view:
SIMM_8_CS

MEMWR
+VCC

BRA13
BRA14
BRA15
BRA16

BRA17
BRA18

BRA19
BRA20
BRA21
BCB00
BCB01

BCB02
BCB03
GND

GND
BD00
BD01
BD02
BD03

BD08
BD09
BD10
BD11

BD16
BD17

BD18
BD19

BD24
BD25
BD26
BD27
BA00
BA01

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71

SIMM_40_CS
+VCC
BRA02
BRA03
BRA04

BRA05
BRA06

BRA07
BRA08
BRA09
BRA10

BRA11
BRA12
BCB04
BCB05
BCB06
BCB07
GND

GND
BD04
BD05

BD06
BD07

BD12
BD13
BD14
BD15

BD20
BD21

BD22
BD23

BD28
BD29
BD30
BD31
OE

„ Top view:
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

3.5 Example of Flash This module can expand the Flash capacity from 512K to 1M bytes of code in 8-bit
- Expansion mode and 2M to 4M bytes of code in 40-bit mode.
SIMM

Figure 3-6. Example of Flash - Expansion SIMM module

BD[7:0] BD[15:8] BD[23:16] BD[31:24] BCB[7:0]

BA[1:0] BRA[20:2]
BRA[18:2]
(512K x 8)

(512K x 8)

(512K x 8)

(512K x 8)

(512K x 8)

(512K x 8)
FLASH

FLASH

FLASH

FLASH

FLASH

FLASH

MEMWR
OE

BRA[19] A 0
139

BRA[20] B BRA[21] A 0
139

1 B
2 1
1/ 2

3 2
1/ 2

G
SIMM_40_CS G 3
SIMM_8_CS

3-14 Evaluation Board TSC695 User Guide

4139G–AERO–11/05
 Section 4
RAM

The RAM space (in 40-bit mode) is built in banks of 2M bytes of code/data.
The two first banks are implemented on board, the other ones (up to 4) can imple-
mented on two 72-pin SIMM modules as RAM expansion.
The on-board RAM’s are soldered.

4.1 RAM - Bank 0 The first bank (Bank 0) is composed of five 512K x 8 SRAM’s selected by MEMCS[0] of
the TSC695. The total capacity is 2M bytes of code/data.
The devices used are located in U2 for check byte + parity, U3 for byte 3 (D[0..7]), U4 for
byte 2 (D[8..15], U5 for byte 1 (D[16..23]) and U6 for byte 0 (D[24..31]).
„ First word address: 0x02000000
„ Last word address: 0x021FFFFC

4.2 RAM - Bank 1 The second bank (Bank 1) is composed of five 512K x 8 SRAM’s selected by MEMCS[1]
of the TSC695. The total capacity is 2M bytes of code/data.
The devices used are located in U7 for check byte + parity, U8 for byte 3 (D[0..7]), U9 for
byte 2 (D[8..15], U10 for byte 1 (D[16..23]) and U11 for byte 0 (D[24..31]).
„ First word address: 0x02200000
„ Last word address: 0x023FFFFC

Evaluation Board TSC695 User Guide 4-15

Rev. 4139G–AERO–11/05
RAM

4.3 RAM - Expansion Up to 2 banks of RAM using a 72-pin SIMM module on connector can be mounted as
SIMM A RAM expansion A on the J1 connector.
This space is selected by the J1 jumper (from MEMCS[2] to MEMCS[9]).
4.3.1 RAM - Expansion
SIMM A selection

Figure 4-1. RAM - Expansion SIMM A Selection

CS2A
J28 J20 MEMCS[6]
J6 J7
MEMCS[7]
MEMCS[2] MEMCS[8]
U13 U14 MEMCS[3] MEMCS[9]
U7
J5 J4
J18
MEMCS[4]
MEMCS[5] CS1A

4.3.2 RAM - Expansion This pin-out is compatible with the SIMM module of Flash expansion.
SIMM A pin-out
„ Bottom view:

MEMWR
+VCC

+VCC
GND

GND

GND
CS1A

RA13
RA14
RA15
RA16

RA17
RA18

RA19
RA20
RA21
CB00
CB01

CB02
CB03
D00
D01
D02
D03

D08
D09
D10
D11

D16
D17

D18
D19

D24
D25
D26
D27
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71

+VCC
GND

GND

CS2A
RA02
RA03
RA04

RA05
RA06

RA07
RA08
RA09
RA10

RA11
RA12
CB04
CB05
CB06
CB07
D04
D05

D06
D07

D12
D13
D14
D15

D20
D21

D22
D23

D28
D29
D30
D31
OE

„ Top view:

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

4.4 RAM - Expansion Up to 2 banks of RAM using a 72-pin SIMM module on connector can be mounted as
SIMM B RAM expansion B on the J2 connector.
This space is selected by jumpers on board (from MEMCS[2] to MEMCS[9]).
4.4.1 RAM - Expansion Figure 4-2. RAM - Expansion SIMM B selection
SIMM B selection

CS2B
J28 J20 MEMCS[6]
J6 J7 MEMCS[7]
MEMCS[8]
MEMCS[2] MEMCS[9]
U13 U14 MEMCS[3]
J5 J4
U7 J18 MEMCS[4]
MEMCS[5]
CS1B

4-16 Evaluation Board TSC695 User Guide

4139G–AERO–11/05
 RAM

4.4.2 RAM - Expansion This pin-out is compatible to the SIMM module of Flash expansion.
SIMM B pin-out
„ Bottom view:

MEMWR
+VCC

+VCC
GND

GND

GND
CS1B

RA13
RA14
RA15
RA16

RA17
RA18

RA19
RA20
RA21
CB00
CB01

CB02
CB03
D00
D01
D02
D03

D08
D09
D10
D11

D16
D17

D18
D19

D24
D25
D26
D27
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71

+VCC
GND

GND

CS2B
RA02
RA03
RA04

RA05
RA06

RA07
RA08
RA09
RA10

RA11
RA12
CB04
CB05
CB06
CB07
D04
D05

D06
D07

D12
D13
D14
D15

D20
D21

D22
D23

D28
D29
D30
D31
OE

„ Top view:
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

4.5 Example of RAM One module can expand the RAM capacity from 1 bank or 2 banks.
- Expansion
SIMM

Figure 4-3. Example of RAM - Expansion SIMM module

D[7:0] D[15:8] D[23:16] D[31:24] CB[7:0]

RA[20:2]
(512K x 8)

(512K x 8)

(512K x 8)

(512K x 8)

(512K x 8)

MEMWR
SRAM

SRAM

SRAM

SRAM

SRAM

OE
CS1

CS2

Evaluation Board TSC695 User Guide 4-17

4139G–AERO–11/05
 Section 5
FPGA

For internal prototyping needs, Atmel has developed an FPGA area on the TSC695
board. This interface has only been partially validated (not all of the signals have been
execrised). The following section gives the key points for the integration of an additional
FPGA on the board.

Atmel does not intend to fully validate the FPGA interface. No support will be provided
by Atmel in case of integration of such an FPGA on-board at the reserved location.
The FPGA can be useful to add some functions to the board. A dedicated area has been
reserved on-board to fit this expansion mode requirement.

5.1 FPGA Part The eVAB-695 board is designed to ease integration of an ALTERA EPF-10K50 to the
Number board. The FPGA (BGA-356 package) should be placed in a socket.
Depending on the board powering , 3.3V or 5V FPGA shall be used.
„ 5.0 Volts:ALTERA EPF-10K50BC356-3
„ 3.3 volts:ALTERA EPF-10K50VBC356-3

5.2 FPGA Socket The socket used for the FPGA device is made by E-Tec (www.e-tec.ch).
Part Number The socket reference is: BPW356-1270-26AA01.

Evaluation Board TSC695 User Guide 5-19

Rev. 4139G–AERO–11/05
FPGA

5.3 FPGA Pin-out

Figure 5-1. FPGA Pin-out

26 25 24 23 22 21 20 19 181716 151413 121110 9 8 7 6 5 4 3 2 1

A
B
C
Indicates location of pin A1 D
E
F
G
H
EPF-10K50BC356-3 EPF-10K50BC356-3 J
K
EPF-10K50VBC356-3 EPF-10K50VBC356-3 L
M
N
BGA-356 BGA-356 P
R
T
U
Top View Bottom View V
W
Y
AA
AB
AC
AD
AE
AF

5-20 Evaluation Board TSC695 User Guide

4139G–AERO–11/05
 FPGA

Table 5-1. FPGA Pin-out with Inter-connections

Pin Signal Pin Signal Pin Signal Pin Signal Pin Signal
A1 Vcc (power) D1 P3-A29 L1 P3-B10 U1 P3-C19 AD1 GPI[5]
A2 Gnd (power) D2 nCONFIG L2 P3-B11 U2 P3-C20 AD2 Gnd (power)
A3 BRA[0} D3 Gnd (MSEL1) L3 P3-B14 U3 P3-C21 AD3 Data0
A4 BRA[1] D4 Gnd (MSEL0) L4 P3-B15 U4 P3-C22 AD4 BUFFEN ]
A5 BRA[2] D5 Vcc (power) L5 P3-B16 U5 Vcc (power) AD5 (Data2 - "open")
A6 BRA[3] D22 Vcc (TMS) L22 P3-B17 U22 (RDYnBSY - AD6 (Data4 - "open")
A7 Vcc (power) D23 Gnd (TRST) L23 P3-B18 U23 P3-C23 AD7 GPI[6]
A8 BRA[4] D24 nSTATUS L24 P3-B19 U24 P3-C24 AD8 (Data6 - "open")
A9 BRA[5] D25 Vcc (power) L25 P3-B20 U25 P3-C25 AD9 GPI[7]
A10 Gnd (power) D26 P3-A30 L26 P3-B21 U26 Gnd (power) AD10 TXA
A11 BRA[6] AD11 TXB
A12 BRA[7] E1 P3-A31 M1 Gnd (power) V1 P3-C26 AD12 CB[0]
A13 Vcc (input) E2 P3-A32 M2 P3-A17 V2 Vcc (power) AD13 Vcc (DEV_CLRn)
A14 SYSCLK E3 BD[0] M3 P3-A18 V3 P3-C27 AD14 Gnd (power)
A15 BRA[8] E4 BD[1] M4 P3-A19 V4 P3-C28 AD15 CB[1]
A16 BRA[9] E5 BD[2] M5 P3-A20 V5 P3-C29 AD16 CB[2]
A17 BRA[10] E22 BD[3] M22 P3-A21 V22 P3-C30 AD17 CB[3]
A18 BRA[11] E23 BD[4] M23 Vcc (power) V23 P3-C31 AD18 Vcc (power)
A19 BRA[12] E24 BD[5] M24 P3-A22 V24 P3-C32 AD19 CB[4]
A20 Gnd (power) E25 BD[6] M25 P3-A23 V25 IOSEL[0] ] AD20 Gnd (power)
A21 BRA[13] E26 BD[7] M26 Vcc (power) V26 IOSEL[1] ] AD21 CB[5]
A22 BRA[14] AD22 CB[6]
A23 Vcc (power) F1 Vcc (power) N1 Vcc (power) W1 Gnd (power) AD23 Gnd (CS)
A24 BRA[15] F2 BD[8] N2 P3-A24 W2 IOSEL[2] ] AD24 Vcc (nCS)
A25 BRA[16] F3 BD[9] N3 P3-A25 W3 IOSEL[3] ] AD25 Gnd (TCK)
A26 Vcc (power) F4 Vcc (power) N4 P3-A26 W4 IOWR ] AD26 Vcc (power)
F5 BD[10] N5 P3-A27 W5 FLUSH
B1 Gnd (power) F22 BD[11] N22 P3-A28 W22 Vcc (power) AE1 Gnd (power)
B2 BRA[17] F23 BD[12] N23 P3-B23 W23 INST AE2 Gnd (power)
B3 BRA[18] F24 BD[13] N24 P3-B24 W24 INULL AE3 DPAR
B4 Vcc (power) F25 BD[14] N25 P3-B25 W25 DIA AE4 CPAR
B5 BRA[19] F26 BD[15] N26 Gnd (power) W26 IUERR ] AE5 (Data5 - "open")
B6 BRA[20] AE6 RAPAR
B7 BRA[21] G1 BD[16] Y1 SYSERR ] AE7 Gnd (power)
B8 BRA[22] G2 BD[17] Y2 CPUHALT ] AE8 RASPAR
B9 BRA[23] G3 BD[18] Y3 SYSAV AE9 TCK(of 695E)
B10 BRA[24] G4 BD[19] Y4 RTC AE10 TMS(of 695E)
B11 BRA[25] G5 BD[20] Y5 GPIINT AE11 TRST ](of 695E)
B12 BRA[26] G22 BD[21] Y22 EXTINTACK AE12 TDI(of 695E)
B13 Gnd (power) G23 BD[22] Y23 RESET ] AE13 Gnd (input)
B14 Vcc (input) G24 BD[23] Y24 EWDINT AE14 Vcc (DEV_OE)
B15 BRA[27] G25 BD[24] Y25 IWDE AE15 TDO(of 695E)
B16 BRA[28] G26 BD[25] Y26 WDCLK AE16 RESET_HALT[0]
B17 BRA[29] AE17 RESET_HALT[1]
B18 BRA[30] H1 BD[26] P1 P3-B26 AA1 Vcc (power) AE18 MEMCS[0] ]
B19 BRA[31] H2 BD[27] P2 Vcc (power) AA2 LOCK AE19 MEMCS[1] ]
B20 RSIZE[0] H3 BD[28] P3 P3-B27 AA3 DXFER AE20 MEMCS[2] ]
B21 RSIZE[1] H4 BD[29] P4 P3-B28 AA4 RD AE21 MEMCS[3] ]
B22 Gnd (power) H5 BD[30] P5 P3-B29 AA5 RLDSTO AE22 MEMCS[4] ]
B23 RASI[0] H22 Vcc (power) P22 P3-B30 AA22 WRT AE23 Vcc (nRS)
B24 RASI[1] H23 Gnd (power) P23 P3-C1 AA23 WE ] AE24 Vcc (nWS)
B25 Gnd (power) H24 Vcc (power) P24 P3-C2 AA24 Gnd (CLKUSR) AE25 Gnd (power)
B26 Gnd (power) H25 BD[31] P25 P3-C3 AA25 RXA AE26 Gnd (power)
H26 BOOTROM1_40_CS ] P26 P3-C4 AA26 RXB
C1 RASI[2] AF1 Vcc (power)
C2 Gnd (power) J1 Vcc (power) R1 Gnd (power) AB1 Vcc (power) AF2 (Data3 - "open")
C3 RASI[3] J2 BOOTROM1_8_ R2 P3-C5 AB2 SYSHALT ] AF3 Vcc (power)
C4 ROMCS ] J3 BOOTROM2_40 R3 P3-C6 AB3 EXTINT[0] AF4 (Data7 - "open")
C5 PROM8 ] J4 BOOTROM2_8_ R4 P3-C7 AB4 FPGA-RA26 AF5 MEMCS[5] ]
C6 P2-C24 J5 DMAAS R5 P3-C8 AB5 EXTINT[1] AF6 MEMCS[6] ]
C7 P2-C23 J22 DMAREQ ] R22 P3-C9 AB22 EXTINT[2] AF7 Vcc (power)
C8 P2-C22 J23 BUSERR ] R23 P3-C10 AB23 EXTINT[3] AF8 MEMCS[7] ]

Evaluation Board TSC695 User Guide 5-21

4139G–AERO–11/05
FPGA

Table 5-1. FPGA Pin-out with Inter-connections (Continued)

Pin Signal Pin Signal Pin Signal Pin Signal Pin Signal
C9 Gnd (power) J24 BUSRDY ] R24 P3-C11 AB24 EXTINT[4] AF9 MEMCS[8] ]
C10 P2-C21 J25 DMAGNT ] R25 P3-C12 AB25 GPI[0] AF10 MEMCS[9] ]
C11 P2-C20 J26 Gnd (power) R26 Gnd (power) AB26 GPI[1] AF11 Gnd (power)
C12 P2-C19 AF12 MEXC ]
C13 Gnd (power) K1 Gnd (power) T1 Gnd (power) AC1 GPI[2] AF13 GCLK_1
C14 Vcc (power) K2 DRDY ] T2 P3-C13 AC2 Gnd (nCE) AF14 Gnd (input)
C15 Vcc (power) K3 P3-B3 T3 P3-C14 AC3 Vcc (TDI) AF15 MHOLD ]
C16 P2-C18 K4 P3-B4 T4 P3-C15 AC4 GPI[3] AF16 Vcc (power)
C17 P2-C17 K5 Vcc (power) T5 P3-C16 AC5 DCLK AF17 ALE ]
C18 P2-C16 K22 P3-B5 T22 P3-C17 AC22 (nCEO - "open") AF18 DDIR
C19 master_DMARE K23 P3-B6 T23 P3-C18 AC23 (TDO - "open") AF19 Gnd (power)
C20 master_DMAGN K24 P3-B7 T24 INIT_DONE AC24 CONF_DONE AF20 OE ]
C21 master_DMAAS K25 P3-B8 T25 Vcc (power) AC25 Vcc (power) AF21 EXMCS ]
C22 master_DRDY ] K26 P3-B9 T26 Vcc (power) AC26 GPI[4] AF22 MEMWR ]
C23 P3-A15 AF23 BA[0]
C24 P3-A16 AF24 BA[1]
C25 Gnd (power) AF25 Gnd (power)
C26 Vcc (power) AF26 Vcc (power)

5.4 FPGA Clocks Two separate clocks must be provided to the FPGA.
5.4.1 FPGA Clocks Figure 5-2. FPGA Clocks Schematic
Schematic 1
CLK2
TSC695 2 pin AF13
3
GCLK_1 GCLK_0 pin A14 SYSCLK
ECLK TSC695
SMB connector GCLK1 FPGA
J14 connector

5.4.2 FPGA Clocks

Jumper

Figure 5-3. FPGA Clocks Selection

J4 U13 U14 U15

J8 J14
J30 U12
J29 1 CLK2
J14 GCLK_1 / CLK2 J14 / 1-2
U1 U28 2 GCLK_1
ECLK GCLK_1 / ECLK J14 / 2-3
J9 3
U27

5-22 Evaluation Board TSC695 User Guide

4139G–AERO–11/05
 FPGA

5.4.3 FPGA External

Clock

Figure 5-4. FPGA External Clock Location

J26

J23 J24
X2 X1 ECLK
J14 J15 connector
J13 3
J11 J17

J25 J15

5.5 FPGA Two ways are available for downloading the FPGA.
Downloading
5.5.1 Serial PROM No serial PROM is provided with the board. The serial PROM (EPC1) method is possi-
ble if no bit-blaster is mounted. The serial PROM shall be mounted on an 8-pin socket
(not provided with the board) and can be powered in 5 or 3 Volts.

Figure 5-5. FPGA Serial PROM location

U14 U15 U16

J30
U12 U17

J14
J31 J16
U28
J9

J3

J29 U27

5.5.2 Bit-Blaster The bit-blaster method is available if no serial PROM is mounted.

Figure 5-6. Bit-Blaster Connector

E
N
C O US
D F_ IG
LK O
C D

U27
N F
0
nCTAT
O N
nS at a

U1
D

J27
J29 J3
J26 J21
J24
J12 9 7 5 3 1
X1 J12 top view
J13
10 8 6 4 2

J17
nd
c
c

nd
c
n.
n.
Vc
G

J25 J15

The bit-blaster must always be powered in 5 Volts (J12-4). A DC/DC converter

(MAX682) is used. This converter provides 5 Volts, named Vbb, from a source 2.7 Volts

Evaluation Board TSC695 User Guide 5-23

4139G–AERO–11/05
FPGA

up to 5.5 Volts. Vbb powers the pull-up resistors on INIT_DONE, nCONFIG,

CONF_DONE and nSTATUS signals.

Figure 5-7. Bit-Blaster DC/DC Converter

C = 1uF
C144
Vcc (2.7 to 5.5V) 6 7
Cxn Cxp
3 IN MAX682 J12-7
1 8 Vbb (5V)
SKIP OUT
R33 U33

R11

E R13

R12

R14
2

4.7K

4.7K

4.7K

4.7K
SHDN
R = 390K

S
Gnd PGnd

N
N

TU
FI
O
C145 C = 47uF

N
D
C = 2.2uF

TA
_D
C146

O
F_
4 5 tantale

nC

nS
IT

N
IN

O
C
Gnd

5-24 Evaluation Board TSC695 User Guide

4139G–AERO–11/05
 Section 6
DMA

A special feature is proposed to build a DMA master with the FPGA. Then another
eVAB-695, seen as target, can be accessed in DMA slave. To be able to communicate
between the two eVAB-695’s via P1 & P2, the address line RA26 of P1 is driven by the
FPGA (pin AB4). Only with an inversion of this line during the DMA master session, the
extended RAM space of the master (address 0x04000000 to 0x0FFFFFFF) can be
mapped to the boot-PROM, extended PROM, exchange Memory areas of the slave. In
the same way a part of the extended I/O space of the master (address 0x14000000 to
0x17FFFFFF) can be mapped to the I/O areas 0 to 3 of the slave.

Figure 6-1. DMA - Address 26 Configuration

J28 J20
J6

J18

U7
J5 J4
1 FPGA-RA26
J18 DMA On J18 / 1-2
2 P1-RA26
U8
J19
3 695E-RA26 DMA Off J18 / 2-3

U9 U1

Evaluation Board TSC695 User Guide 6-25

Rev. 4139G–AERO–11/05
 Section 7
TSC695 Power & Clock

The board can be powered (Vcc board) by the connector P1, P2 or/and P3. It can also
be powered by J20 and J28, allowing to separate the core Vcc and the I/O Vcc on the
TSC695.

7.1 TSC695 Power

Figure 7-1. TSC695 Power Configuration

J28 J20 Vcc
J6 J7 (board)
VccI VccO
(TSC695 core) (TSC695 I/O)

U13 U14
Gnd
J5 J4
U7 J18
c b a c b a
J28 J20

c b a c b a
J28 J20
from P1P2P3(PCB) from P1P2P3(PCB)
Default Connections

7.2 TSC695 Clocks CLK2 clock can be provided either by an oscillator (X1 - format 1 or 1/2 format) or by
J25 connector.

Evaluation Board TSC695 User Guide 7-27

Rev. 4139G–AERO–11/05
TSC695 Power & Clock

Figure 7-2. TSC695 clocks

74LV04-U34
CLK2-J25 1 2 3 4 100 W-R36
CLK2
5 TSC695-pin 143
Vcc 74LV04-U34
X1 1 5 6 100 W-R37
CLK2
oscillator P1-pin A10
1 74LV04-U34
2 9 8 100 W-R38
GCLK_1
ECLK-J15 3 FPGA-pin AF13
GCLK1-J14
WDCLK
Vcc 74LV04-U34 TSC695-pin 244
1 X2 5 11 10 13 12 WDCLK
oscillator P2-pin A23
WDCLK
FPGA-pin Y26

Figure 7-3. Clocks - X1, X2 and J25 Location

J26 J26

J23 J24 J23 J24

X2 X1 X2 X1
J13 J13
J11 J17 J11 J17

J25 J15 J25 J15

7-28 Evaluation Board TSC695 User Guide

4139G–AERO–11/05
 Section 8
Reset, HALT, EWDINT and Status
LED’s

Two dedicated push buttons and four status LED’s are available on front side.
SMB connectors can be used to input HALT and EWDINT.
RESET and HALT can be provided by the TAP connector.
The other sources for RESET and HALT are managed into the FPGA.

8.1 RESET

8.1.1 Schematic

Figure 8-1. RESET Schematic

4.7KW

4.7KW

R15 R16
1
3 9 12
BP RESET 8 11
2 SYSRESET
13 TSC695
4.7KW

S1 U30 10
"On-Mom" U30
R17
4
6
4.7mF 5
RESET_HALT[1]

Other RESET sources

pin AE17

FPGA

Evaluation Board TSC695 User Guide 8-29

Rev. 4139G–AERO–11/05
Reset, HALT, EWDINT and Status LED’s

8.1.2 Push Button Figure 8-2. Reset Push Button Location

Location
J1
U29 J23
J2

D2

S1 J10 S2 J11

D1 D3

8.2 HALT

8.2.1 Schematic Figure 8-3. HALT schematic

4.7KW

4.7KW
R18 R19
1
3 9 12
BP HALT 8 11
2 SYSHALT
13 TSC695
4.7KW

S2 U31 10
"On-On" R20 U31
4
6
5 SYSHALT
SMB connector
RESET_HALT[0]

J27
Other HALT sources

pin AE16

FPGA

8.2.2 Push Button Figure 8-4. HALT Push Button Location

Location

U29 J23
J2 J1

D2

S1 J10 S2 J11

D1 D3

8-30 Evaluation Board TSC695 User Guide

4139G–AERO–11/05
Reset, HALT, EWDINT and Status LED’s

8.2.3 SMB Connector Figure 8-5. HALT - SMB Connector Location

Location

U27
U1
J27 J3
J29
J26 J21
J24
X1 J12
J13

J17

J25 J15

8.3 EWDINT EWDINT can be used as NMI. A SMB connector is provided to input this external signal.

Figure 8-6. EWDINT - SMB Connector Location

U27
U1
J29
J27
J3
J26 J21
J24
X1 J12
J13

J17

J25 J15

8.4 Status LED’s

8.4.1 Schematic

Figure 8-7. LED’ Schematic

green
ALE 4.7KW
D1
"RUN"
TSC695
green
SYSAV 4.7KW
D2
"SYSTEM AVAILABLE"
TSC695
red
D3
CPUHALT 4.7KW "HALT"
TSC695

8-31 Evaluation Board TSC695 User Guide

4139G–AERO–11/05
Reset, HALT, EWDINT and Status LED’s

8.4.2 LED’s Location Figure 8-8. LED’s Location

U29 J23
J2 J1

D2
S1 J10 S2 J11

D1 D3

8-32 Evaluation Board TSC695 User Guide

4139G–AERO–11/05
 Section 9
Test Points
Table 9-1. Test Points Table
J29
Signal Pin nbr Signal

Gnd - 1 RTC

Gnd - 2 GPI [0]

Gnd - 3 GPI [1]

Gnd - 4 GPI [2]

Gnd - 5 GPI [3]

Gnd - 6 GPI [4]

Gnd - 7 GPI [5]

Gnd - 8 GPI [6]

Gnd - 9 GPI [7]

Gnd - 10 EWDINT

Gnd - 11 SYSCLK

Gnd - 12 RESET
Gnd - 13 SYSRESET ]

Gnd - 14 SYSERR ]

Gnd - 15 CPUHALT ]

Gnd - 16 ROMCS ]

Gnd - 17 MEMCS 0 ]

Gnd - 18 IOSEL 0 ]
Gnd - 19 OE ]

Gnd - 20 MEMWR ]

Gnd - 21 IOWR ]
Gnd - 22 WE ]

Gnd - 23 BUFFEN ]

Gnd - 24 DDIR

Gnd - 25 MHOLD ]

Gnd - 26 INST

Gnd - 27 RA [2]

Gnd - 28 D [0]

Evaluation Board TSC695 User Guide 9-33

Rev. 4139G–AERO–11/05
Test Points

Gnd - 29 TxA

Gnd - 30 TxB

Gnd - 31 RxA

Gnd - 32 RxB

Figure 9-1. Test Points Location

U13 U14 U15 U16

J30

J8
U12 U17
pin 1
U1 J14
J31 J16

U28

J9

J3

J29 U27

pin 32

J27

J26 J21
J24
J12
J13

J17

9-34 Evaluation Board TSC695 User Guide

4139G–AERO–11/05
 Section 10
Logic Analyzer POD’s

Four pod’s for logic analyzer and are available on board. They can provide inputs for a
dis-assembler.

10.1 POD 1
Table 10-1. Pod 1 Table
Logic Analyzer Logic Analyses

J21
E2 - Even A2/A3 A0/A1 E1 - Odd
Signal Pin nbr Signal
(red) (brown) (orange) (brown)

- 1 39 38 -
- 2 37 -
Gnd

K clock CK0 DMAGNT ] 3 36 SYSCLK CK1 J clock

E2:15 A3:7 BRA [31] 4 35 BRA [15] A1:7 E1:15

E2:14 A3:6 BRA [30] 5 40 34 BRA [14] A1:6 E1:14

E2:13 A3:5 BRA [29] 6 33 BRA [13] A1:5 E1:13

Gnd

E2:12 A3:4 BRA [28] 7 32 BRA [12] A1:4 E1:12

E2:11 A3:3 BRA [27] 8 31 BRA [11] A1:3 E1:11

E2:10 A3:2 BRA [26] 9 41 30 BRA [10] A1:2 E1:10

E2:9 A3:1 BRA [25] 10 29 BRA [9] A1:1 E1:9

Gnd

E2:8 A3:0 BRA [24] 11 28 BRA [8] A1:0 E1:8

E2:7 A2:7 BRA [23] 12 42 27 BRA [7] A0:7 E1:7

E2:6 A2:6 BRA [22] 13 26 BRA [6] A0:6 E1:6

Gnd

E2:5 A2:5 BRA [21] 14 25 BRA [5] A0:5 E1:5

E2:4 A2:4 BRA [20] 15 24 BRA [4] A0:4 E1:4

E2:3 A2:3 BRA [19] 16 43 23 BRA [3] A0:3 E1:3

E2:2 A2:2 BRA [18] 17 22 BRA [2] A0:2 E1:2

Gnd

E2:1 A2:1 BRA [17] 18 21 BRA [1] A0:1 E1:1

E2:0 A2:0 BRA [16] 19 20 BRA [0] A0:0 E1:0

Evaluation Board TSC695 User Guide 10-35

Rev. 4139G–AERO–11/05
Logic Analyzer POD’s

10.2 POD 2
Table 10-2. Pod 2 Table
Logic Analyzer Logic Analyzer

J22

E4 - Even D2/D3 D0/D1 E3 - Odd

Signal Pin nbr Signal
(yellow) (blue) (yellow) (orange)

- 1 39 38 -

- 2 37 -

Gnd
M clock Q0 EXMCS ] 3 36 ALE ] CK2 L clock

E4:15 D3:7 D [31] 4 35 D [15] D1:7 E3:15

E4:14 D3:6 D [30] 5 40 34 D [14] D1:6 E3:14

E4:13 D3:5 D [29] 6 Gnd 33 D [13] D1:5 E3:13

E4:12 D3:4 D [28] 7 32 D [12] D1:4 E3:12

E4:11 D3:3 D [27] 8 31 D [11] D1:3 E3:11

E4:10 D3:2 D [26] 9 41 30 D [10] D1:2 E3:10

E4:9 D3:1 D [25] 10 29 D [9] D1:1 E3:9

Gnd

E4:8 D3:0 D [24] 11 28 D [8] D1:0 E3:8

E4:7 D2:7 D [23] 12 42 27 D [7] D0:7 E3:7

E4:6 D2:6 D [22] 13 26 D [6] D0:6 E3:6

Gnd

E4:5 D2:5 D [21] 14 25 D [5] D0:5 E3:5

E4:4 D2:4 D [20] 15 24 D [4] D0:4 E3:4

E4:3 D2:3 D [19] 16 43 23 D [3] D0:3 E3:3

E4:2 D2:2 D [18] 17 22 D [2] D0:2 E3:2

Gnd

E4:1 D2:1 D [17] 18 21 D [1] D0:1 E3:1

E4:0 D2:0 D [16] 19 20 D [0] D0:0 E3:0

10-36 Evaluation Board TSC695 User Guide

4139G–AERO–11/05
Logic Analyzer POD’s

10.3 POD 3
Table 10-3. Pod 3 Table
Logic Analyzer Logic Analyzer

J23

E6 - Even C2/C3 C0/C1 E5 - Odd

Signal Pin nbr Signal
(blue) (white) (grey) (green)

- 1 39 38 -

- 2 37 -

Gnd
P clock CK3 RESET ] 3 36 IOSEL [0] ] Q1 N clock

E6:15 C3:7 LOCK 4 35 CPUHALT ] C1:7 E5:15

E6:14 C3:6 RLDSTO 5 40 34 SYSERR ] C1:6 E5:14

E6:13 C3:5 MEMCS [0] ] 6 Gnd 33 DDIR C1:5 E5:13

E6:12 C3:4 DXFER 7 32 RASI [3] C1:4 E5:12

E6:11 C3:3 RD 8 31 DMAREQ ] C1:3 E5:11

E6:10 C3:2 FLUSH 9 41 30 DMAAS C1:2 E5:10

E6:9 C3:1 INULL 10 29 DRDY ] C1:1 E5:9

Gnd

E6:8 C3:0 INST 11 28 RASI [2] C1:0 E5:8

E6:7 C2:7 ROMCS ] 12 42 27 OE ] C0:7 E5:7

E6:6 C2:6 DIA 13 26 BUFFEN ] C0:6 E5:6

Gnd

E6:5 C2:5 MEXC ] 14 25 RIZE [1] C0:5 E5:5

E6:4 C2:4 BA [1] 15 24 RASI [1] C0:4 E5:4

E6:3 C2:3 WE ] 16 43 23 MEMWR ] C0:3 E5:3

E6:2 C2:2 MDS ] 17 22 IOWR ] C0:2 E5:2

Gnd

E6:1 C2:1 MHOLD ] 18 21 RIZE [0] C0:1 E5:1

E6:0 C2:0 BA [0] 19 20 RASI [0] C0:0 E5:0

10-37 Evaluation Board TSC695 User Guide

4139G–AERO–11/05
Logic Analyzer POD’s

10.4 POD 4
Table 10-4. Pod 4 Table
Logic Analyzer Logic Analyzer

J24

E8 - Even E2/E3 E0/E1 E7 - Odd

Signal Pin nbr Signal
(grey) (violet) (green) (violet)

- 1 39 38 -

- 2 37 -

Gnd
R clock Q3 EXTINTACK 3 36 BUSERR ] Q2 Q clock

E8:15 E3:7 EXTINT [4] 4 35 BUSRDY ] E1:7 E7:15

E8:14 E3:6 EXTINT [3] 5 40 34 RTC E1:6 E7:14

E8:13 E3:5 EXTINT [2] 6 Gnd 33 EWDINT E1:5 E7:13

E8:12 E3:4 EXTINT [1] 7 32 GPIINT E1:4 E7:12

E8:11 E3:3 EXTINT [0] 8 31 GPI [5] E1:3 E7:11

E8:10 E3:2 RAPAR 9 41 30 GPI [4] E1:2 E7:10

E8:9 E3:1 RASPAR 10 29 GPI [3] E1:1 E7:9

Gnd

E8:8 E3:0 CPAR 11 28 GPI [2] E1:0 E7:8

E8:7 E2:7 DPAR 12 42 27 GPI [1] E0:7 E7:7

E8:6 E2:6 CB [6] 13 26 GPI [0] E0:6 E7:6

Gnd

E8:5 E2:5 CB [5] 14 25 IOSEL [3] ] E0:5 E7:5

E8:4 E2:4 CB [4] 15 24 IOSEL [2] ] E0:4 E7:4

E8:3 E2:3 CB [3] 16 43 23 IOSEL [1] ] E0:3 E7:3

E8:2 E2:2 CB [2] 17 22 MEMCS [3] ] E0:2 E7:2

Gnd

E8:1 E2:1 CB [1] 18 21 MEMCS [2] ] E0:1 E7:1

E8:0 E2:0 CB [0] 19 20 MEMCS [1] ] E0:0 E7:0

10-38 Evaluation Board TSC695 User Guide

4139G–AERO–11/05
 Section 11
Serial Links

11.1 Serial A

Figure 11-1. Serial link A Configuration

J10 front view

J1
U29 J23
J2
5 4 3 2 1 RxA TSC695 J10 / 2
D2

S1 J10 S2 J11 9 8 7 6 TxA TSC695 J10 / 3

D1 D3
Gnd J10 / 5

11.2 Serial B

Figure 11-2. Serial Link B Configuration

J11 front view

U29 J23

5 4 3 2 1 RxB TSC695 J11 / 2

J25
D2
J10 S2 J11 9 8 7 6 TxB TSC695 J11 / 3

D1 D3
Gnd J11 / 5

Evaluation Board TSC695 User Guide 11-39

Rev. 4139G–AERO–11/05
Serial Links

11.3 SUN Connection

Figure 11-3. SUN Connection Lay-out

SUN / DB 25 serial port eVAB-695E / DB 9 serial port

(A or B) (A or B)
Function Pin Nb Pin Nb Function
... ... ... ...
Tx. SUN 2 2 Rx. TSC695
Rx. SUN 3 3 Tx. TSC695
.. .. .. .. .. .. ... ...
Gnd SUN 7 5 Gnd TSC695
.. .. .. .. .. .. .. .. .. .. .. ..

SUN / DB 25 serial port eVAB-695E / DB 9 serial port

(both A and B) (A or B)
Function Pin Nb Pin Nb Function
... ... ... ...
TxA SUN 2 2 Rx. TSC695
RxA SUN 3 3 Tx. TSC695
.. .. .. .. .. .. ... ...
Gnd SUN 7 5 Gnd TSC695
.. .. .. .. .. .. .. .. .. .. .. ..
.. .. .. .. .. ..
.. .. .. .. .. .. eVAB-695E / DB 9 serial port
.. .. .. .. .. .. ( B or A)
.. .. .. .. .. ..
Pin Nb Function
TxB SUN 14 ... ...
... ... 2 Rx. TSC695
RxB SUN 16 3 Tx. TSC695
.. .. .. .. .. .. ... ...
5 Gnd TSC695
.. .. .. .. .. ..

11-40 Evaluation Board TSC695 User Guide

4139G–AERO–11/05
Serial Links

11.4 PC Connection

Figure 11-4. PC Connection Lay-out

PC / DB 9 serial port eVAB-695E / DB 9 serial port

(COM1 or COM2) (A or B)
Function Pin Nb Pin Nb Function
... ... ... ...
Rx. PC 2 2 Rx. TSC695
Tx. PC 3 3 Tx. TSC695
... ... ... ...
Gnd PC 5 5 Gnd TSC695
.. .. .. .. .. .. .. .. .. .. .. ..

11-41 Evaluation Board TSC695 User Guide

4139G–AERO–11/05
 Section 12
Tap Connector

The J13 connector is the TAP connector used for JTAG. It is a male M50 type connector
14 leads.

Figure 12-1. Tap Connector Lay-out

)
69 )
5E
O E
9 D 5
I(T DI6
K
U27

TDO(T
TM CL

TDST
U1

SY.c

TR K
TCS
n
J27
J29 J3
J26 J21
J24 J12 14 13 12 11 10 9 8
X1 J13 top view
J13 1 2 3 4 5 6 7

J17

GT
nd
CP n.c
c

ES T
SY ES T
SY SH ET

E
U H n.

SR AL
R AL

J25 J15

Vcc
R34

C146
U33 C144
C145
TCK TCK
R7
J13-11 TSC695-pin 142
R35 R34 C129
J17
R35

Bottom View

TCK can be received a pull-up and/or a pull-down resistor. The default configuration has
no resistor.
TMS, TDI, TRST pads of the TSC695 has an internal pull-up resistor.

Evaluation Board TSC695 User Guide 12-43

Rev. 4139G–AERO–11/05
 Section 13
Expansion Connectors

13.1 3 x 32 points
connector - P1 Table 13-1. P1 Connector Pin Definition
P1
Pin nbr Signal row A Signal row B Signal row C Pin nbr
32 Vcc Vcc Vcc 32
31 --- --- --- 31
30 D [13] RAPAR RA [25] 30
29 D [12] RA [31] RA [24] 29
28 D [11] RA [30] RA [23] 28
27 D [10] RA [29] RA [22] 27
26 D [09] RA [28] RA [21] 26
25 D [08] RA [27] RA [20] 25
24 D [07] RA [26] RA [19] 24
23 D [06] Gnd RA [18] 23
22 D [05] *8RSIZE [1] RA [17] 22
21 D [04] RSIZE [0] RA [16] 21
20 D [03] Gnd RA [15] 20
19 Gnd RASPAR RA [14] 19
18 SYSCLK D [31] RA [13] 18
17 Gnd D [30] RA [12] 17
16 ALE D [29] RA [11] 16
15 Gnd D [28] RA [10] 15
14 D [02] D [27] RA [09] 14
13 D [01] D [26] RA [08] 13
12 D [00] D [25] RA [07] 12
11 Gnd D [24] RA [06] 11
10 CLK2 D [23] RA [05] 10
9 Gnd D [22] Gnd 9
8 DPAR D [21] RA [04] 8
7 CB [06] D [20] RA [03] 7
6 CB [05] D [19] RA [02] 6
5 CB [04 D [18] RA [01] 5
4 CB [03] D [17] RA [00] 4
3 CB [02] D [16] BA [01] 3
2 CB [01] D [15] BA [00] 2
1 CB [00] D [14] CPAR 1

Evaluation Board TSC695 User Guide 13-45

Rev. 4139G–AERO–11/05
Expansion Connectors

13.2 3 x 32 points
connector - P2 Table 13-2. P2 Connector Pin Definition
P2

Pin nbr Signal row A Signal row B Signal row C Pin nbr

32 EXTINTACK Vcc slave_DMAREQ ] or DMAREQ ] 32

31 EXTINT[4] Gnd slave_DMAGNT ] or DMAGNT ] 31

30 EXTINT[3] BUFFEN ] slave_DMAAS or DMAAS 30

29 EXTINT[2] DDIR slave_DRDY ] or DRDY ] 29

28 EXTINT[1] DDIR* master_DMAREQ ] or FPGA [pin C19] 28

27 EXTINT[0] WE master_DMAGNT ] or FPGA [pin C20] 27

26 MEXC ] RD master_DMAAS or FPGA [pin C21] 26

25 EWDINT EXMCS ] master_DRDY ] or FPGA [pin C22] 25

24 IWDE MEMCS [9] ] EXT_D_BUFFEN ] or FPGA [pin C6] 24

23 WDCLK MEMCS [8] ] EXT_C_BUFFEN ] or FPGA [pin C7] 23

22 RTC Gnd FPGA [pin C8] 22

21 Tx A MEMCS [7] ] FPGA [pin C10] 21

20 Rx A MEMCS [6] ] FPGA [pin C11] 20

19 Tx B MEMCS [5] ] FPGA [pin C12] 19

18 Rx B MEMCS [4] ] FPGA [pin C16] 18

17 MHOLD ] MEMCS [3] ] FPGA [pin C17] 17

16 MDS ] MEMCS [2] ] FPGA [pin C18] 16

15 INULL MEMCS [1] ] RESET ] 15

14 DIA MEMCS [0] ] SYSRESET ] 14

13 FLUSH Vcc CPUHALT ] 13

12 INST Gnd SYSHALT ] 12

11 DXFER ROMCS ] BUSRDY ] 11

10 WRT IOSEL [3] ] SYSAV 10

9 GPI [7] IOSEL [2] ] BUSERR ] 9

8 GPI [6] IOSEL [1] ] SYSERR ] 8

7 GPI [5] IOSEL [0] ] IUERR ] 7

6 GPI [4] IOWR ] LOCK 6

5 GPI [3] MEMWR ] RLDSTO 5

4 GPI [2] OE ] RASI [3] 4

3 GPI [1] --- RASI [2] 3

2 GPI [0] Gnd RASI [1] 2

1 GPIINT Vcc RASI [0] 1

13-46 Evaluation Board TSC695 User Guide

4139G–AERO–11/05
Expansion Connectors

13.3 3 x 32 points
connector - P3 Table 13-3. P3 Connector Pin Definition
P3

Pin nbr Signal row A Signal row B Signal row C Pin nbr

32 FPGA [pin E2] Vcc FPGA [pin V24] 32

31 FPGA [pin E1] Gnd FPGA [pin V23] 31

30 FPGA [pin D26] FPGA [pin P22] FPGA [pin V22] 30

29 FPGA [pin D1] FPGA [pin P5] FPGA [pin V5] 29

28 FPGA [pin N22] FPGA [pin P4] FPGA [pin V4] 28

27 FPGA [pin N5] FPGA [pin P3] FPGA [pin V3] 27

26 FPGA [pin N4] FPGA [pin P1] FPGA [pin V1] 26

25 FPGA [pin N3] FPGA [pin N25] FPGA [pin U25] 25

24 FPGA [pin N2] FPGA [pin N24] FPGA [pin U24] 24

23 FPGA [pin M25] FPGA [pin N23] FPGA [pin U23] 23

22 FPGA [pin M24] Gnd FPGA [pin U4] 22

21 FPGA [pin M22] FPGA [pin L26] FPGA [pin U3] 21

20 FPGA [pin M5] FPGA [pin L25] FPGA [pin U2] 20

19 FPGA [pin M4] FPGA [pin L24] FPGA [pin U1] 19

18 FPGA [pin M3] FPGA [pin L23] FPGA [pin T23 18

17 FPGA [pin M2] FPGA [pin L22] FPGA [pin T22] 17

16 FPGA [pin C24] FPGA [pin L5] FPGA [pin T5] 16

15 FPGA [pin C23] FPGA [pin L4] FPGA [pin T4] 15

14 IWDE FPGA [pin L3] FPGA [pin T3] 14

13 EWDINT Vcc FPGA [pin T2] 13

12 SYSCLK Gnd FPGA [pin R25] 12

11 RESET ] FPGA [pin L2] FPGA [pin R24] 11

10 GPIINT FPGA [pin L1] FPGA [pin R23] 10

9 RTC FPGA [pin K26] FPGA [pin R22] 9

8 GPI [7] FPGA [pin K25] FPGA [pin R5] 8

7 GPI [6] FPGA [pin K24] FPGA [pin R4] 7

6 GPI [5] FPGA [pin K23] FPGA [pin R3] 6

5 GPI [4] FPGA [pin K22] FPGA [pin R2] 5

4 GPI [3] FPGA [pin K4] FPGA [pin P26] 4

3 GPI [2] FPGA [pin K3] FPGA [pin P25] 3

2 GPI [1] Gnd FPGA [pin P24] 2

1 GPI [0] Vcc FPGA [pin P23] 1

13-47 Evaluation Board TSC695 User Guide

4139G–AERO–11/05
Expansion Connectors

– slave_DMAREQ* is DMAREQ* from TSC695

– slave_DMAGNT* is DMAGNT* from TSC695
– slave_DMAAS is DMAAS from TSC695
– slave_DRDY* is DRDY* from TSC695

13-48 Evaluation Board TSC695 User Guide

4139G–AERO–11/05
 Section 14
Board Implementation

Figure 14-1. Board Implementation - Lay-out

Power
P1 P2

PROM 40
Debug RA26

BUFFEN
CS RAM

CS RAM
SIMM B

SIMM A

GCLK1 WRROM

PROM8/40
PROM
SRAM Bank 0

SRAM Bank 1

8
Par/NoPar
Simm SRAM B
Simm SRAM A

EPC1

FlashCS
pin 1
Simm PROM

SIMMCS
pin A1

TSC 695
FPGA
Test Points

10K50

POD 2
Syshalt
EWDINT POD 1
Oscillators
MAX POD 3 POD 4
WDCLK CLK2 BitBlaster
Reset

TAP
Halt

LS A LS B P3
CLK2

ECLK
RUN
SAV
HLT

Evaluation Board TSC695 User Guide 14-49

Rev. 4139G–AERO–11/05
Board Implementation

Figure 14-2. Board Implementation - References

J28 J20
J6 J7

J5 J4 J32 U13 U14 U15 U16

U2 U7 J18
eVAB-695E-Rev.D
J8
U3 U8 J19 J30 U12 U17

J14 J31 J16

U4 U9 U28
J9
J2 J1 U5 U10 U1 J3
U27
U6 U11

J22
J27
J29
J26 J21
U29 J23 J24
J12
X2 X1
D2
J13
S1 J10 S2 J11 J17
D1 D3 J25 J15

14-50 Evaluation Board TSC695 User Guide

4139G–AERO–11/05
 Section 15
Deviations

15.1 CB[6:0] and The signals CB[7:0] and DPAR connected on FPGA are those of the TSC695 and not
DPAR on FPGA those buffered for the other space than SRAM. Note that data connected to FPGA are,
effectively, those coming from data buffers.
==> Disable the enable buffer for CB[7 :0] and DPAR (U26 - xx245) using
EXT_C_BUFFEN on FPGA (pin C7) and drive directly CB[7:0] and DPAR.

15.2 Reset and HALT The "Reset in" and "HALT in" (from JTAG con to FPGA or CPU) are not possible.
Driven by JTAG ==> If these functions are needed, use the 2x n.c pins of the JTAG connector and con-
Connector nect them to FPGA, pins AD5 and AD6 ("open").

15.3 TSC695 Signals Note that the following signals are missing:
on FPGA „ TMODE[1,0] (not useful)
„ DDIR* (but DDIR exits)
„ ROMWRT* (on board pulldown)
„ DEBUG
„ MDS*
„ NOPAR*
Note: This shall be taken into account in the FPGA implementation.

Evaluation Board TSC695 User Guide 15-51

Rev. 4139G–AERO–11/05
 Section 16
Schematics
The following section illustrates the schematic diagrams for the TSC695 Evaluation
Board.

Evaluation Board TSC695 User Guide 16-53

Rev. 4139G–AERO–11/05
Schematics

16-54 Evaluation Board TSC695 User Guide

4139G–AERO–11/05
Schematics

16-55 Evaluation Board TSC695 User Guide

4139G–AERO–11/05
Schematics

16-56 Evaluation Board TSC695 User Guide

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Schematics

16-57 Evaluation Board TSC695 User Guide

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Schematics

16-58 Evaluation Board TSC695 User Guide

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Schematics

16-59 Evaluation Board TSC695 User Guide

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Schematics

16-60 Evaluation Board TSC695 User Guide

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Schematics

A
B

16-61 Evaluation Board TSC695 User Guide

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Schematics

A
B

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Schematics

16-63 Evaluation Board TSC695 User Guide

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Schematics

16-64 Evaluation Board TSC695 User Guide

4139G–AERO–11/05
 Schematics

Evaluation Board TSC695 User Guide 16-65

4139G–AERO–11/05
Schematics

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 Section 17
Revision History

17.1 Changes from

Revision B 08/99
to Revision C 1. Changed logic analizer pod’s signals.
01/00 2. Added WDCLK on board.
3. New Flash SIMM selection.
4. Placed DC/DC convertor for FPGA.
5. Buffering of clock signals.

17.2 Changes from

Revision C 01/00 1. Updating P3 Connector.
to Revision D 2. Schematic for R34/R35 (TAP).
04/00

17.3 Changes from 1. Permutation of J20 and J28 names.

Revision D 04/00 2. Permutation VccO and VccI.
to Revision E 3. Addition of board schematics.
03/01

17.4 Changes from 1. Changing TSC695E to TSC695.

Revision E 03/01 2. Changing eVAB-695E to eVAB-695.
to Revision F 3. Addition of BUFFEN* controls for on-board data buffers.
08/03

17.5 Changes from 1. Changing +5V to +VCC (board documentation is applicable for 3V and 5V
Revision F 08/03 boards)
to Revision G 2. Precision on memory mount process (socket versus soldering)
11/05 3. Precision given on FPGA area

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Rev. 4139G–AERO–11/05
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