CHAPTER 1
INTRODUCTION
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1.1 CRYPTOGRAPHY
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2) The number of keys used: If both sender and receiver use the same key, the
system is referred to as symmetric, single-key, secret-key, or conventional
encryption. If the sender and receiver each uses a different key, the system is
referred to as asymmetric, two-key, or public-key encryption.
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Not only is it used over the Internet, but also it is used in phones,
televisions, and a variety of other common household items. Without
cryptography, hackers could get into out e-mail, listen in on our phone
conversations, tap into our cable companies and acquire free cable service, or
break into our bank/brokerage accounts.
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Namely, the adoption rate may depend on the level of demand. For
example, SSL-encapsulated HTTP gained a lot more usage much more
quickly than simpler link-layer encryption has ever achieved. The adoption
rate may depend on the level of demand.
• Secure communication:
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• Electronic commerce :
Over the past few years there has been a growing amount of business
conducted over the Internet. This form of business is called electronic
commerce or E-Commerce. E-Commerce is comprised of online banking,
online brokerage accounts, and Internet shopping, to name a few of the many
applications. One can book plane tickets, make hotel reservations, rent a car,
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transfer money from one account to another, buy cloths, books and so on all
while sitting in front of a computer. However, simply entering a credit card
number on the Internet leaves one open to fraud. One cryptographic solution
to this problem is to encrypt the credit card number or other private
information when it is entered online; another is to secure the entire session.
When a computer encrypts this information and sends it out on the Internet, it
is incomprehensible to a third party viewer. The web server or Internet
shopping center receives the encrypted information, decrypts is, and proceeds
with the sale without fear that the credit card number or other personal
information slipped into the wrong hands. As more and more business is
conducted over the Internet, the need for protection against, fraud, theft and
corruption of vital information increases.
• Key Recovery:
First of all, if a user loses or accidentally deletes his or her key, key
recovery could prevent a disaster.
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Key recovery techniques are in use in some instances; however the use of
key recovery as a law enforcement technique is somewhat controversial.
• Other Applications:
• In Private key Cryptography, both the sender and the recipient share
a key that must be kept private. In order to communicate with each other, the
key must be passed between the two; this process is known as the key
distribution and is quite complicated and difficult to do properly. The most
famous example of this type of cryptography is the Data Encryption Standard
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(DES), other examples include Triple DES, RC2, RC4 IDEA and Skipjack.
This is also known as symmetric cryptography.
• While in Public Key Cryptography, each party has two sets of keys,
one key is published to the public, called the Public Key, while the other is
kept secret and only known by the owner, the Private Key. Anyone wishing
to communicate with a certain party securely will encrypt the communicated
data with the recipient's public key which is available and on the other side
only the party that holds the matching private key can decrypt the cipher
text. Example Public key algorithms: Diffie-Hellman, RSA and Merkle-
Hellman.
The public key system eliminates the key distribution process that
hampers all private key systems since there is no need to communicate
secret keys among communicating parties.
CHAPTER 2
ENCRYPTION AND DECRYTION SYSTEM
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SENDER RECIPIENT
M S M S M M
E E E E E E
S C S C S S
S T U S INFORMATION CHANNEL U S S
A R A R A A
G E G E G G
E E E E
SECRET SECRET
INFORMATION INFORMATION
(KEY) (KEY)
-- ALGORITHM
SECURITY RELATED TRANSFORMATION
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SENDER C C RECIPIENT
I I P
P P P L
L
A
H H A
E E I
I
INFORMATION CHANNEL N
N R R
T
T T T E
E
X
E E X
X X T
T
T T
The above figure enables us to take a closer look at the essential elements
of a symmetric encryption scheme.
Cipher text: This is the scrambled message produced as output. It depends on
the plaintext and the secret key. For a given message, two different keys will
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produce two different cipher texts. The cipher text is an apparently random
stream of data and, as it stands, is unintelligible.
Decryption algorithm: This is essentially the encryption algorithm run in
reverse. It takes the cipher text and the secret key and produces the original
plaintext.
2.2 CRYPTANALYSIS
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• Encryption algorithm
Known plain text • Cipher text to be decoded
• One or more pairs of plain text cipher text
formed with the secret key
• Encryption algorithm
Chosen plain text • Cipher text to be decoded
• Purported cipher text chosen by cryptanalyst,
together with its corresponding decrypted
plaintext generated with the secret key.
• Encryption algorithm
• Cipher text to be decoded
Chosen cipher
text • Plain text message chosen by the cryptanalyst
together with its corresponding cipher text
generated with the secret key.
• Purported cipher text chosen by cryptanalyst,
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The cipher text-only attack is the easiest to defend against because the
opponent has the least amount of information to work with. In many cases,
however, the analyst has more information. The analyst may be able to capture
one or more plaintext messages as well as their encryptions. Or the analyst may
know that certain plaintext patterns will appear in a message. For example, a
file that is encoded in the postscript format always begins with the same
pattern, or there may be a standardized header or banner to an electronic funds
transfer message, and so on. All these are examples of known plaintext. With
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this knowledge, the analyst may be able to deduce the key on the basis of the
way in which the known plaintext is transformed.
Closely related to the known-plaintext attack is what might be referred to
as a probable-word attack. If the opponent is working with the encryption of
some general prose message, he or she may have little knowledge of what is in
the message. However if the opponent is after some very specific information,
then parts of the message may be known. For example, if an entire accounting
file is being transmitted, the opponent may know the placement of certain
keywords in the header of the file. As another example, the source code for a
program developed by corporation X might be including a copyright statement
in some standardized position.
If the analyst is able somehow to get the source system to insert in to the
system a message chosen by the analyst, then a chosen-plaintext attack is
possible. An example of this strategy is differential cryptanalysis, which is
studied later. In general, if the analyst is able to choose the messages to
encrypt, the analyst may deliberately pick patterns that can be expected to
reveal the structure of the key.
The earlier table lists two other types of attack: chosen cipher text and chosen
text. These are less commonly employed as cryptanalytic techniques but are
nevertheless possible avenues of attack.
Only relatively weak algorithms fail to withstand a cipher text-only
attack. Generally, an encryption algorithm is designed to withstand a known-
plaintext attack.
Two more definitions are worthy of note. An encryption scheme is
unconditionally secure if the cipher text generated by the scheme does not
contain enough information to determine uniquely the corresponding plaintext,
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no matter how much cipher text is available. That is, no matter how much time
an opponent has, it is impossible for him or her to decrypt the cipher text,
simply because the required information is not there. With the exception of a
scheme known as the one-time pad (described later), there is no encryption
algorithm that is unconditionally secure. Therefore, all that the users of an
encryption algorithm can strive for is an algorithm that meets one or both of the
following criteria:
The cost of breaking the cipher exceeds the value of the encrypted information.
The time required to break the cipher exceeds the useful life time of the
information.
An encryption scheme is said to be computationally secure if the
foregoing two criteria are met. The rub is that it is very difficult to estimate the
amount of effort required to crypt analyze cipher text successfully.
As a first cut, we can consider the time required to use a brute-force
approach, which simply involves trying every possible key until an intelligible
translation of the cipher text into plaintext is obtained. On average half of all
possible keys must be tried to achieve success.
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Problem of digital signatures: The problem that Diffie pondered, and that
was apparently unrelated to the first was that of "digital signatures." If the use
of cryptography was to become widespread, not just in military situations but
for commercial and private purposes, then electronic messages and documents
would need the equivalent of signatures used in paper documents. That is,
could a method be devised that would stipulate, to the satisfaction of all parties,
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that a digital message had been sent by a particular person? This is a somewhat
broader requirement than that of authentication, and its characteristics and
ramifications are explored in the next sections.
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Public-key algorithms rely on one key for encryption and a different but
related key for decryption. These algorithms have the following important
characteristics:
(1) It is computationally infeasible to determine the decryption key given only
the knowledge of the encryption key.
(2) Either of the two related keys can be used for encryption, with the other
used for decryption.
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Decryption algorithm: This algorithm accepts the cipher text and the matching
key and produces the original plaintext.
SENDER C C RECIPIENT
I I P
P P P L
L
A
H H A
E E I
I
INFORMATION CHANNEL N
N R R
T
T T T E
E
X
E E X
X X T
T
T T
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2.3.2.1 ENCRYPTION:
ESSENTIAL STEPS:
Each user generates a pair of keys to be used for the encryption and
decryption of the message
Each user places one of the two keys in a public register or other
accessible files. This is a public key. The companion key is kept private.
If a person ‘A’ wishes to send a confidential matter to the second person
‘B’ the first person will encrypt the data by the B's public key.
When ‘B’ receives the message, he decrypts it using his private key. No
other person could be able to decrypt the message until and unless the
any other person knows the B's private key.
Y = E Kub(X). (ENCRYPTION)
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• The intended receiver ,in possession of the matching private key ,is able to
invert the transformation:
X = D Krb(Y). (DECRYPTION)
SENDER RECIPIENT
(A) (B)
C C
I I P
P P P L
L
A
H H A
E E I
I
INFORMATION CHANNEL N
N R R
T
T T T E
E
X
E E X
X X T
T
T T
B’S
B’S
PUBLIC KEY
PRIVATE KEY
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2.3.2.2. AUTHENTICATION:
ESSENTIAL STEPS:
SENDER RECIPIENT
(A) (B)
C C
I I P
P P P L
L
A
H H A
E E I
I
INFORMATION CHANNEL N
N R R
T
T T T E
E
X
E E X
X X T
T
T T
A’S
A’S
PRIVATE KEY
PUBLIC KEY
Because the message was encrypted using A’s private key , only A could
have prepared the message. Therefore, the entire encrypted message serves
as a digital signature.
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The emergence of public key systems has introduced the concept of digital
signature. A sample digital signature scenario goes as follows:
ESSTENTAL STEPS:
If the initial data is obtained then this will authenticate the data and the
sender.
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D D
I I
G C G
C
I I I
T I T
P P
A P A
L H P
A L H L
L E L L
I E A
Y R Y
N R I
S S N
T T
I T I
E E T
X G E G
N X N E
T X X
E T E
T T
D D
D D
A A
T T
A A
Information
A’s Private B’s Public
Channel
Key (kra) Key (kub) B’s Private A’s Public
Key (krb) Key (kua)
KEY
KEY PAIR
PAIR SOURCE
SOURCE
Encryption/Decryption Algorithm
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Some public- key algorithms are suitable for all three applications , whereas
others can be used only for one or two of these applications
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The RSA algorithm is named after Ron Rivest, Adi Shamir and Len
Adleman, who invented it in 1977. The basic technique was first discovered in
1973 by Clifford Cocks but this was a secret until 1997.
The RSA algorithm can be used for both public key encryption and
digital signatures. Its security is based on the difficulty of factoring large
integers.
The RSA Algorithm makes use of an expression with exponentials.
Plain text is encrypted in blocks with each block having a binary value less
than some numbers n. that is, the block size must be less than or equal to
k k k +1
log 2 (n) , in practice, the block size is 2 bits, where 2 <n≤2
e
C =M mod n
d
= C mod n = (M e) mod n = M
e ed
M mod n
Both sender and receiver must know the value of n. the sender knows the value
of e, and only the receiver knows the value of d.
Thus, this is a public-key encryption algorithm with a public key of
Ku = {e, n} and a private key of Kr = {d, n}. For the algorithm to be
satisfactory for public key encryption the following requirements must be met.
ed
1. It is possible to find values of e, d, n such that M =M mod n for all
M< n.
e d
2. It is relatively easy to calculate M and C for all values of M<n.
3. It is infeasible to determine d given e and n.
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Given two prime numbers, p and q, and two integers, n and m. such that n=p*q
and 0<m<n and arbitrary integer k, the following relationship holds
kφ ( n ) +1 k ( p −1)( q −1) +1
m =m ≡ m mod n
d = e −1 mod φ (n)
The private key consists of {d, n} and public key consists of {e, n}. Suppose
that user A has published its public key and the user B wishes to send the
message M to A., then B calculates C = M e mod n and transmits C. On receipt of
this cipher text, user A decrypts by calculates M = C d mod n . The algorithm for
computing ab mod n , b is represented in binary.
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Key Generation :
such that their product n = p*q is of the required bit length, e.g. 1024
bits. [See note 1].
2. Compute n = p*q and (φ) phi = (p-1)*(q-1).
3. Choose an integer e, 1 < e < phi, such that gcd(e, phi) = 1. [See note 2].
4. Compute the secret exponent d, 1 < d < phi, such that
ed ≡ 1 (mod phi). [See note 3].
5. The public key is (n, e) and the private key is (n, d). The values of p, q,
a)Encryption:
The encryption is carried out as;
Sender does the following:-
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b)Decryption
Recipient does the following:-
Summary of RSA:
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i.e. find a value for d such that phi divides (ed-1) i.e. find d such that 20
divides 3d-1. Simple testing (d = 1, 2, ...) gives d = 7 Check: ed-1 = 3.7 - 1
= 20, which is divisible by phi.
This is least possible value for the modulus n for which the RSA algorithm
works.
Now say we want to encrypt the message m=7 c=m^e mod n = 7^3 mod 33 = 343
mod 33=13. Hence the cipher text c = 13.
Note that we don't have to calculate the full value of 13 to the power 7 here.
We can make use of the fact that
so we can break down a potentially large number into its components and
combine the results of easier, smaller calculations to calculate the final value.
= 13^(3+3+1) mod 33
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= (13^3*13^3*13) mod 33
= (19*19*13) mod33
= 4693 mod 33
=7.
The defense against the brute-force approach is the same for RSA as for other
cryptosystems, namely, use a large key space. Thus, the larger the number of
bits in e and d, the better. However, because the calculations involved, both in
key generation and in encryption /decryption, are complex, the larger the size
of the key, the slower the system will run.
The Factoring Problem
We can identify three approaches to attacking RSA mathematically:
• Factor n into its two prime factors. This enables calculation of
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combination of a safe by observing how long it takes for some one to turn the
dial from number to number. The attack can be explained using the modular
exponentiation algorithm, but the attack can be adapted to work with any
implementation that does not run in fixed time. In this algorithm, modular
exponentiation is accomplished bit by bit, with one modular multiplication
performed at each iteration and an additional modular multiplication performed
for each 1 bit.
As Kocher points out in his paper, the attack is simplest to
understand in an extreme case. Suppose the target system uses a modular
multiplication function that is very fast in almost all cases but in a few cases
takes much more time than an entire average modular exponentiation. The
attack proceeds bit by bit starting with the leftmost bit, bk. Suppose that the
first j bits are known ( to obtain the entire exponent, start with j = 0 and repeat
the attack until the entire exponent is known ). For a given cipher text, the
attacker can complete the first j iterations of the for loop. The operation of the
subsequent step depends on the unknown exponent bit. If the bit is set, d ¬(d *
a ) mod n will be executed. For a few values of a and d, the modular
multiplication will be extremely slow, and the attacker knows which these are.
Therefore, if the observed time to execute the decryption algorithms is always
slow when this particular iteration is slow with a 1 bit, then this bit is assumed
to be 1. If a number of observed execution times for the entire algorithm are
fast, then this bit is assumed to be 0.
In practice, modular exponentiation implementations do not involve
such extreme time variations, in which the execution time of a single iteration
can exceed the mean execution time of the entire algorithm. Nevertheless, there
is enough variation to make this attack practical.
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• Electronic mail
• Software distribution
• Data storage
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CHAPTER 3
LANGUAGE OVERVIEW
Figure 3.1 shows a typical process for the design of a digital system.
Specification
Analysis
s
HDL(VHDL)
RTL Coding
Synthesis
Gate Level Net list
Timing Analysis
Implementation FPGA
Analysis:
The first step in a high level design is the analysis of the system to be
designed. The process involved the specifying the behavior expected of the
design. The designer puts enough detail into the specification so that the design
can be built.
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RTL coding:
After the specification has been completed, the design or the designer can
begin the process of implementation. The designer created the RTL description
that describes the clock behavior of the design.
Simulation:
The synthesis tool converts the RTL description into a net list in the target
FPGA or ASIC technology. The designer reads the RTL description, if there
are no errors the designer can synthesize the design and map the design to the
target technology.
Timing Analysis:
Typical timing analysis uses a timing analyzer that gives a number of report
types that can be generated so that the designer can make sure the critical paths
of the design and can verify whether they are within the specified or required
timings.
Implementation:
Implementation describes the process of downloading the synthesized RTL
description on to the target technology like FPGA or ASIC’s .
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ranging from the Arithmetic level to the gate level. The complexity of
digital system being modeled could vary from that of a simple gate to a
complete digital electronic system or any thing in between. The digital
system can also be described hierarchically.
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• The capability of defining new data types provides the power to describe
and simulate design techniques at a very high level of abstraction
without any concern about the implementation details.
ENTITY:
All designs are expressed in terms of entities. An entity is the
most basic building block in a design. The uppermost level of the design is
the top level entity. If the design is hierarchical, then the top-level
description will have lower level descriptions contained in it . These
lower level descriptions will be lower entities contained in the top-level
entity description.
ENTITY DECLARATION:
ENTITY entity_make IS
PORT (port1: port1_type;
Port2: port2_type);
END entity;
ARCHITECTURE:
All entities that can be simulated have an architecture
description.
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The architecture describes the behavior of the entity. A single entity can have
multiple architectures. One architecture might be behavioral while another
might be structural description of the design.
• As a system of inter-connected components (to represent the structure)
• As a set of concurrent assignment statements (to represent dataflow)
• As a set of assignments (to represent behavior)
• As any combination of the above three.
SYNTAX:
ARCHITECTURE architecture_name OF entity IS
-- declare some signals here
BEGIN
-- put some concurrent signals here
END architecture_name;
PACKAGES:
Package is a collection of commonly used data
types and subprograms used in a design. It can be treated as a toolbox that
contains tools used to build designs
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-- do some stuff;
END package_name;
PACKAGE BODY:
PACKAGEBODY package_name IS
-- put subprograms bodies here
END package_name;
BUS: The term bus usually brings to mind a group of signals or a particular
method of communication used in the design of hardware. In VHDL, a bus is a
special kind of signal that may have its drivers turned off.
______________________________________________________________________________
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END IF;
END IF;
Case Statement:
CASE expression IS
WHEN some_value=>
Perform some operation;
WHEN some other value =>
Perform some other operation;
WHEN others =>
Perform some other operation;
END CASE;
For Loop:
FOR loop_variable IN start_value TO end_value LOOP
do some stuff;
END LOOP;
While Loop:
WHILE condition LOOP
do some stuff;
END LOOP;
Component Declaration:
COMPONENT component_name
PORT (port1_name : port_type;
port2_ name : port_type;
port3_name : port_type);
END COMPONENT;
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Component Instantiation:
Instance name: component_name PORT MAP (first port, second_port,
third_port);
Instancename: component_name PORT MAP
(formal1=>actual1,formal2=>actual2);
Signal Declaration:
SIGNAL signal1_name: signal1_type;
SIGNAL signal2_name: signal2_type;
Variable Declaration:
VARIABLE variable1_name: variable1_type;
VARIABLE variable2_name: variable2_type;
Function Declaration:
FUNCTION function_name (parameter1:parameter1_type,
parameter2:parameter2_type);
RETURN return_type;
Library Declaration:
LIBRARY library_name;
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BEHAVIORAL:
The highest level of abstraction supported in VHDL is called the
behavioral level of abstraction. When creating a behavioral description of a
circuit, you will describe your circuit in terms of its operation over time. The
concept of time is the critical distinction between behavioral description of
circuits and lower-level descriptions(specifically descriptions created at the
dataflow level of abstraction).
Examples of behavioral forms of representation might include state
diagrams, timing diagrams and algorithmic descriptions.
In a behavioral description, the concept of time may be expressed
precisely, with actual delays between related events(such as the propagation
delays within gates and on wires),or it may simply be an ordering of operations
that are expressed sequentially (such as in a functional description of flip-flop).
When you are writing WHDL for input registers in your circuit. It is unlikely,
however, that your synthesis tool will be capable of creating precisely the same
behavior in actual circuitry as you have defined in the language.(Synthesis
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tools today ignore detailed timing specifications, leaving the actual timing
results at the mercy of the target device technology.) I t is also unlikely that
your synthesis tool will be capable of accepting and processing a very wide
range of behavioral styles.
DATAFLOW:
In the dataflow level of abstraction, you describe your circuit
in terms how data moves through the system. At the heart of most digital
systems today are registers, so in the dataflow level of how information is
passed between registers in the circuit. You will probably describe the
combinational logic portion of your circuit at a relatively high level(and let a
synthesis toll figure out the detailed implementation in logic gates), but you
will likely be, quite specific aabout the placement and operation of registers in
the complete circuit.
The dataflow level of abstraction is often called register
transfer logic, or RTL. This level of abstraction is an intermediate level that
allows the drudgery of combinational logic to be simplified (and , presumably,
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taken care of by logic synthesis tools) while the more important parts of the
circuit, the registers, are more completely specified.
There are some drawbacks to using a dataflow method of design in VHDL.
First, there are no built-in registers in VHDL; the language was designed to be
general-purpose, and VHDL’s designers on its behavioral aspects placed the
emphasis. If you are going to write VHDL at the dataflow level of abstraction,
you will be using in your design. These elements must be provided in the form
of components (using VHDL’s hierarchy features) or in the form of
subprograms(functions or procedures).But for hardware designers, it can be
difficult to relate the sequential descriptions and operation of behavioral VHDL
with the hardware being described (or modeled). For this reason, many VHDL
users, particularly those who are using VHDL as an input to synthesis, prefer to
stick with levels of abstraction that are easier to relate to actual hardware
devices(such as logic gates and flip-flops). These users are often more
comfortable using the dataflow level of abstraction.
STRUCTURAL
The third level of abstraction, structure, is used to describe a
circuit in terms of its components. Structure can be used to create a very –
high-level-description(such as a block diagram).
In a gate-level description of a circuit, for example,
components such as basic logic gates and flip-flops might be connected in
some logical structure to create the circuit. This is what is often called a net
list. For a higher-level circuit-one in which the components being connected
are larger functional blocks-structures might simply be used to segment the
design description into manageable parts.
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CHAPTER 4
DESIGN APPROACH
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MESSAGE
READ
INPUT BUFFER N
O/P
R1, R2, R3
e(0),e(1),e(2) C1 ,C2
DO NE1 DO NE2
0
R
CONTROL UNIT
RST
WRITE
CYPHERTEXT
CIPHERTEXT
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READ
INPUT BUFFER N
O/P
R1, R2, R3
d(0),d(1),d(2) C1 ,C2
DO NE1 DO NE2
0
R
CONTROL UNIT
RST
WRITE
MESSAGE
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RST
INPUT BUFFER
READ
MESSAGE / CIPHERTEXT
Input buffer is the module which performs the function of storing and
reading the data which is given as the input to it when the READ control signal
is set to ‘1’.
The input data is plain text block which is passed to the multiplier on
receiving the control signal from the control unit.
OPERATION:
• When the RST is set to ‘1’ then the output will be “----------------”.
• When RST is set to ‘0’ then the input buffer gets enabled.
• When READ is ‘1’ then the data (MESSAGE / CIPHER TEXT) is
taken as input to the system.
• On receiving the appropriate signal from the control unit it transfer the
data to the multiplier unit.
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RST
OUTPUT BUFFER
WRITE
The input data is plain text/cipher text block which is passed as out
put of the system on receiving the control signal from the control unit.
OPERATION:
When RST is set to ‘1’ then output is cleared.
When RST is set to ‘0’ then the input buffer gets enabled .
When WRITE is ‘1’ then the data (MESSAGE / CIPHER TEXT) is taken as
output to the system .
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On receiving the appropriate signal from the control unit it transfer the data as
the output of the system (ENCRYPTION SYSTEM / DECRYPTION
SYSTEM).
4.3.3 MULTIPLIER:
The multiplier unit performs the multiplication operation and
passes the result to the modulus unit as per the signal of the control unit
Input to the multiplier unit is data (MESSAGE / CIPHER
TEXT), output of modulus unit (i.e. R1 or R2 or R3), RST, control signal
(C1, C2) and CLK.
OPERATION:
• When C1=1 and C2=1 then the output of multiplier output port
(o/p) (32 bit ) is initialized to 1.
• When C1 =1 and C2= 0 the multiplier begins to perform the
multiplication operation .
• The multiplier performs the multiplication operation as shown in
STEP 1, STEP 3 and STEP 5 producing a 32 bit result.
• On completion of the operation it generate DONE1=’1’ indication
the completion of the operation and passes the result as input to the
modulus unit.
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C1,C2
RST
CLK MULTIPLIER
e/d
DONE 1
O/P
4.3.4 MODULUS
The modulus unit performs the modulus operation (i.e. finding the
remainder of the two inputs , the dividend (i.e. O/P) and divisor (i.e. N) and
passes the result to the next unit as per the signal from the control unit.
The inputs to the modulus unit are output of the multiplier unit
(i.e. O/P), RST, control signals (i.e.C1, C2) and CLK.
OPERATION:
• When C1=0 and C2=0 the output of the modulus unit gets initialized to
1.
• When C1=0 and C2=1 the modulus unit perform the operation as shown
in STEP 2, STEP 4 and STEP 6 producing 16 bit result .
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O/P
RST
C1,C2
MODULUS UNIT R
CLK
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DONE 1 DONE 2
RST
RSTIN
C1,C2
CLK
CONTROL UNIT
ENABLE
e/d
OPERATION:
• When RSTIN (system reset) =’1’then the control unit generates the
control signal RST=’1’ which clears and initializes all the modules. All
the modules are initializing as said above.
• When RSTIN =’0’ and ENABLE =’1’ the control unit generates the
control signal RST=’0’ and instructs each module to perform its
operation at their specific timings.
• First clock pulse:
The control unit sets READ to ‘1’.During this time the input
buffer gets enabled and reads the input data.
• Second clock pulse :
C1 and C2 are set to ‘1’.These signals initialize the multiplier
unit where multiplier unit results 0001 to modulator unit.
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Performs the above operation and transfers the results the out put buffer as the
signal of the control unit.
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1. Input Buffer
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity ip is
port(
plain : in STD_LOGIC_VECTOR(15 downto 0);
rst : in STD_LOGIC;
read : in STD_LOGIC;
o : out STD_LOGIC_vector(15 downto 0)
);
end ip ;
architecture ip_arch of ip is
begin
process(rst,read)
variable temp:std_logic_vector(15 downto 0);
begin
if rst='1' then
o<="----------------";
elsif read='1' then
temp:=plain;
o<=temp;
end if;
end process;
end ip_arch;
2. Multiplier
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library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity multi is
port(
rst,c1,c2,e,clk : in STD_LOGIC;
a,b : in STD_LOGIC_VECTOR(15 downto 0);
done : out STD_LOGIC;
o_mul : out STD_LOGIC_VECTOR(31 downto 0)
);
end multi;
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done<='0';
end if;
end if;
end process;
end multi_arch;
3. Modulus
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity mod1 is
port(o_mul: in std_logic_vector(31 downto 0);
rst,c1,c2:in std_logic;
clk:in std_logic;
o_mod:out std_logic_vector(15 downto 0);
done:out std_logic);
end mod1;
architecture mod_arch of mod1 is
begin
process(rst,clk)
variable a,b,c:integer;
constant n:integer:=33;
begin
if rst='1'then
o_mod<="----------------";
done<='0';
elsif clk'event and clk='1'then
if c1='0'and c2='0'then
o_mod<= "0000000000000001";
done<='1';
elsif c1='0'and c2='1'then
a:=conv_integer(o_mul) / n;
b:=a*n;
c:=conv_integer(o_mul)- b;
o_mod<=conv_std_logic_vector(c,16);
done<='1';
else
done<='0';
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end if;
end if;
end process;
end mod_arch;
4.control unit
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.std_logic_unsigned.all;
entity cu is
port(
rstin : in STD_LOGIC;
clk : in STD_LOGIC;
done1 : in STD_LOGIC;
done2 : in STD_LOGIC;
enable : in STD_LOGIC;
c1 : buffer STD_LOGIC;
c2 : buffer STD_LOGIC;
e : out STD_LOGIC;
read,write:out std_logic
);
end cu;
architecture cu_arch of cu is
begin
process(clk)
variable s :integer range 1 to 10;
begin
if rstin='1'then
read<='-';
write<='-';
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c1<='-';
c2<='-';
s:=1;
e<='-';
elsif (clk'event and clk='1') and enable='1' then
case s is
when 1=>
read<='1';
write<='-';
c1<='-';
c2<='-';
when 2=>
read<='0';
write<='-';
c1<='1';
c2<='1'; --initialize m,ultiplier
--e<='0';
when 3=>
read<='0';
write<='-';
c1<='0';
c2<='0'; --initialize modulus
-- e<='0';
when 4=>read<='0';
write<='-';
c1<='1';
c2<='0'; --first multiplication
e<='0';
when 5=>
read<='0';
write<='0';
e<='0';
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end if;
when 6=>
read<='0';
write<='0';
e<='1'; --2nd mul
if(done2='1' or (c1='0' and c2='1'))then
c1<='1';
c2<='0';
end if;
when 7=>
read<='0';
write<='0';
e<='1'; --2nd mod
if(done1='1' or (c1='1' and c2='0'))then
c1<='0';
c2<='1';
end if;
when 8=>
read<='0';
write<='0';
e<='1';
if(done2='1' or (c1='0' and c2='1'))then
c1<='1';
c2<='0';
end if;
when 9=>
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read<='0';
write<='0';
e<='1';
if(done1='1' or (c1='1' and c2='0'))then
c1<='0';
c2<='1';
end if;
when 10=>
write<='1';
read<='0';
c1<='-';
c2<='-';
e<='-';
--when others=>null;
end case ;
if s=10 then
s:=1;
else
s:=s+1;
end if;
end if;
--end if;
end process;
end cu_arch;
5.output buffer
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
entity op is
port(
o_mod : in STD_LOGIC_VECTOR(15 downto 0);
rst : in STD_LOGIC;
write : in STD_LOGIC;
cipher : out STD_LOGIC_VECTOR(15 downto 0)
);
end op ;
architecture op_arch of op is
begin
process(rst,write)
variable temp:std_logic_vector(15 downto 0);
begin
if rst='1' then
cipher<="----------------";
elsif write='1' then
temp:=o_mod;
cipher<=o_mod;
end if;
end process;
end op_arch;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
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entity rsatop is
port(
plain : in STD_LOGIC_vector(15 downto 0);
clk : in STD_LOGIC;
rst,enable : in STD_LOGIC;
cipher : out STD_LOGIC_vector(15 downto 0)
);
end rsatop;
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end component ;
component cu is
port(
rstin : in STD_LOGIC;
clk : in STD_LOGIC;
done1 : in STD_LOGIC;
done2 : in STD_LOGIC;
enable : in STD_LOGIC;
c1 : buffer STD_LOGIC;
c2 : buffer STD_LOGIC;
e : out STD_LOGIC;
read,write:out std_logic
);
end component ;
component op is
port(
o_mod : in STD_LOGIC_VECTOR(15 downto 0);
rst : in STD_LOGIC;
write : in STD_LOGIC;
cipher : out STD_LOGIC_VECTOR(15 downto 0)
);
end component ;
signal read,c1,c2,done1,e,done2,write:std_logic;
signal o,out_mod:std_logic_vector(15 downto 0);
signal out_mul:std_logic_vector(31 downto 0);
begin
u1: ip port map(plain,rst,read,o);
u2:multi port map(rst,c1,c2,e,clk,o,out_mod,done1,out_mul);
u3:mod1 port map(out_mul,rst,c1,c2,clk,out_mod,done2);
u5:op port map(out_mod,rst,write,cipher);
u4:cu port map(rst,clk,done1,done2,enable,c1,c2,e,read,write);
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end rsatop_arch;
1.Input Buffer
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity ip_dec is
port(
cipher : in STD_LOGIC_VECTOR(15 downto 0);
rst : in STD_LOGIC;
read : in STD_LOGIC;
o : out STD_LOGIC_vector(15 downto 0)
);
end ip_dec ;
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end ip_arch;
2.multiplier
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity multi_dec is
port(
rst,c1,c2,d,clk : in STD_LOGIC;
a,b : in STD_LOGIC_VECTOR(15 downto 0);
done : out STD_LOGIC;
o_mul : out STD_LOGIC_VECTOR(31 downto 0)
);
end multi_dec;
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if d='0' then
temp:=1;
else
temp:=conv_integer(a);
end if;
temp1:=conv_integer(b);
if i=1 then
temp1:=temp1;
i:=i+1;
elsif i=2 then
temp1:=temp1*temp1;
i:=i+1;
elsif i=3 then
temp1:=temp1*temp1;
end if;
op1:=temp*temp1;
o_mul<=conv_std_logic_vector(op1,32);
done<='1';
else
done<='0';
end if;
end if;
end process;
end multi;
3.modulus
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity mod_dec is
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begin
process(rst,clk)
variable a,b,c:integer;
constant n:integer:=33;
begin
if rst='1'then
o_mod<="----------------";
done<='0';
elsif clk'event and clk='1'then
if c1='0'and c2='0'then
o_mod<= "0000000000000001";
done<='1';
elsif c1='0'and c2='1'then
a:=conv_integer(o_mul) / n;
b:=a*n;
c:=conv_integer(o_mul)- b;
o_mod<=conv_std_logic_vector(c,16);
done<='1';
else
done<='0';
end if;
end if;
end process;
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end mod1;
4.control unit
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.std_logic_unsigned.all;
entity cu_dec is
port(
rstin : in STD_LOGIC;
clk : in STD_LOGIC;
done1 : in STD_LOGIC;
done2 : in STD_LOGIC;
enable : in STD_LOGIC;
c1 : buffer STD_LOGIC;
c2 : buffer STD_LOGIC;
d : out STD_LOGIC;
read,write:out std_logic
);
end cu_dec;
begin
process(clk)
variable s :integer range 1 to 10;
begin
if rstin='1'then
read<='-';
write<='-';
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c1<='-';
c2<='-';
s:=1;
d<='-';
elsif (clk'event and clk='1') and enable='1' then
case s is
when 1=>
read<='1';
write<='-';
c1<='-';
c2<='-';
when 2=>
read<='0';
write<='-';
c1<='1';
c2<='1'; --initialize m,ultiplier
d<='0';
when 3=>
read<='0';
write<='-';
c1<='0';
c2<='0'; --initialize modulus
d<='0';
when 4=>read<='0';
write<='-';
c1<='1';
c2<='0'; --first multiplication
d<='1';
when 5=>
read<='0';
write<='0';
d<='1';
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end if;
when 6=>
read<='0';
write<='0';
d<='1'; --2nd mul
if(done2='1' or (c1='0' and c2='1'))then
c1<='1';
c2<='0';
end if;
when 7=>
read<='0';
write<='0';
d<='1'; --2nd mod
if(done1='1' or (c1='1' and c2='0'))then
c1<='0';
c2<='1';
end if;
when 8=>
read<='0';
write<='0';
d<='1';
if(done2='1' or (c1='0' and c2='1'))then
c1<='1';
c2<='0';
end if;
when 9=>
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read<='0';
write<='0';
d<='1';
if(done1='1' or (c1='1' and c2='0'))then
c1<='0';
c2<='1';
end if;
when 10=>
write<='1';
read<='0';
c1<='-';
c2<='-';
d<='-';
--when others=>null;
end case ;
if s=10 then
s:=1;
else
s:=s+1;
end if;
end if;
--end if;
end process;
end cu_arch;
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library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity rsa_dec_top is
port(
cipher : in STD_LOGIC_vector(15 downto 0);
clk : in STD_LOGIC;
rst,enable : in STD_LOGIC;
plain : out STD_LOGIC_vector(15 downto 0)
);
end rsa_dec_top;
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component mod_dec
port(o_mul: in std_logic_vector(31 downto 0);
rst,c1,c2:in std_logic;
clk:in std_logic;
o_mod:out std_logic_vector(15 downto 0);
done:out std_logic);
end component ;
component cu_dec is
port(
rstin : in STD_LOGIC;
clk : in STD_LOGIC;
done1 : in STD_LOGIC;
done2 : in STD_LOGIC;
enable : in STD_LOGIC;
c1 : buffer STD_LOGIC;
c2 : buffer STD_LOGIC;
d : out STD_LOGIC;
read,write:out std_logic
);
end component ;
component op_dec is
port(
o_mod : in STD_LOGIC_VECTOR(15 downto 0);
rst : in STD_LOGIC;
write : in STD_LOGIC;
plain : out STD_LOGIC_VECTOR(15 downto 0)
);
end component ;
signal read,c1,c2,done1,d,done2,write:std_logic;
signal o,out_mod:std_logic_vector(15 downto 0);
signal out_mul:std_logic_vector(31 downto 0);
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begin
u1: ip_dec port map(cipher,rst,read,o);
u2:multi_dec port
map(rst,c1,c2,d,clk,o,out_mod,done1,out_mul);
u3:mod_dec port map(out_mul,rst,c1,c2,clk,out_mod,done2);
u5:op_dec port map(out_mod,rst,write,plain);
u4:cu_dec port
map(rst,clk,done1,done2,enable,c1,c2,d,read,write);
end rsadec_arch;
CHAPTER 5
SIMULATION RESULTS
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CHAPTER 6
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========================================================
HDL Synthesis Report
Macro Statistics
# Registers : 10
16-bit register :1
1-bit register :7
32-bit register :2
# Latches :2
16-bit latch :2
# Counters :1
4-bit up counter :1
# Adders/Subtractors :1
16-bit subtractor :1
# Multipliers :3
32x7-bit multiplier :1
16x16-bit multiplier :1
16x18-bit multiplier :1
========================================================
Starting low level synthesis...
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Macro Statistics
# Registers : 56
1-bit register : 55
32-bit register :1
# Counters :1
4-bit up counter :1
# Adders/Subtractors :1
16-bit subtractor :1
# Multipliers :3
32x7-bit multiplier :1
16x16-bit multiplier :1
16x18-bit multiplier :1
Design Statistics
# IOs : 35
Cell Usage :
# BELS : 918
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# GND :1
# LUT1 :4
# LUT2 : 42
# LUT2_D : 14
# LUT2_L : 89
# LUT3 :4
# LUT4 : 52
# LUT4_L : 91
# MULT_AND : 128
# MUXCY : 242
# MUXF5 :3
# VCC :1
# XORCY : 247
# FlipFlops/Latches : 80
# FDC :2
# FDCPE :4
# FDE :5
# FDRE : 34
# FDSE :3
# LD : 32
# Clock Buffers :1
# BUFGP :1
# IO Buffers : 34
# IBUF : 18
# OBUF : 16
========================================================
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS
ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE
TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
x4_wr:Q | NONE | 16 |
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x4_rd:Q | NONE | 16 |
clk | BUFGP | 48 |
-----------------------------------+------------------------+-------+
Timing Summary:
---------------
Speed Grade: -6
Minimum period: 25.627ns (Maximum Frequency: 39.021MHz)
Minimum input arrival time before clock: 3.412ns
Maximum output required time after clock: 6.994ns
Maximum combinational path delay: No path found
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
Offset: 3.412ns (Levels of Logic = 1)
Source: en
Destination: x4_c1
Destination Clock: clk rising
Data Path: en to x4_c1
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 9 0.768 1.908 en_IBUF (en_IBUF)
FDE:CE 0.736 x4_c1
----------------------------------------
Total 3.412ns (1.504ns logic, 1.908ns route)
(44.1% logic, 55.9% route)
-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'x4_wr:Q'
Offset: 6.994ns (Levels of Logic = 1)
Source: x5_dout_0
Destination: ciphertext_0
Source Clock: x4_wr:Q falling
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# Counters :1
4-bit up counter :1
# Adders/Subtractors :1
16-bit subtractor :1
# Multipliers :3
32x7-bit multiplier :1
16x16-bit multiplier :1
16x18-bit multiplier :1
========================================================
Starting low level synthesis...
Optimizing unit <d_controler_dc> ...
Optimizing unit <d_opbuffer> ...
Optimizing unit <d_mod2> ...
Optimizing unit <d_mul2> ...
Optimizing unit <d_ipbuffer> ...
Optimizing unit <dc_top> ...
Building and optimizing final netlist ...
FlipFlop x3_r_0 has been replicated 1 time(s)
FlipFlop x3_r_1 has been replicated 1 time(s)
FlipFlop x3_r_2 has been replicated 1 time(s)
FlipFlop x3_r_3 has been replicated 1 time(s)
FlipFlop x3_r_4 has been replicated 1 time(s)
========================================================
Final Results
Top Level Output File Name : dc_top
Output Format : NGC
Optimization Criterion : Speed
Target Technology : virtex
Keep Hierarchy : No
Macro Generator : macro+
Macro Statistics
# Registers : 56
1-bit register : 55
32-bit register :1
# Counters :1
4-bit up counter :1
# Adders/Subtractors :1
16-bit subtractor :1
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# Multipliers :3
32x7-bit multiplier :1
16x16-bit multiplier :1
16x18-bit multiplier :1
Design Statistics
# IOs : 35
Cell Usage :
# BELS : 917
# GND :1
# LUT1 :4
# LUT2 : 42
# LUT2_D : 14
# LUT2_L : 89
# LUT3 :4
# LUT4 : 51
# LUT4_L : 91
# MULT_AND : 128
# MUXCY : 242
# MUXF5 :3
# VCC :1
# XORCY : 247
# FlipFlops/Latches : 80
# FDC :2
# FDCPE :4
# FDE :5
# FDRE : 34
# FDSE :3
# LD : 32
# Clock Buffers :1
# BUFGP :1
# IO Buffers : 34
# IBUF : 18
# OBUF : 16
========================================================
Clock Information:
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
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x4_wr:Q | NONE | 16 |
x4_rd:Q | NONE | 16 |
clk | BUFGP | 48 |
-----------------------------------+------------------------+-------+
Timing Summary:
---------------
Speed Grade: -6
Minimum period: 25.627ns (Maximum Frequency: 39.021MHz)
Minimum input arrival time before clock: 3.412ns
Maximum output required time after clock: 6.994ns
Maximum combinational path delay: No path found
Timing Detail:
All values displayed in nanoseconds (ns)
-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
Offset: 3.412ns (Levels of Logic = 1)
Source: en
Destination: x4_c1
Destination Clock: clk rising
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The above figure shows the enlarged BEL taken from the
implemented design as shown in above targeting (xcv300-fg456-6) FPGA
Editor tool.
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The above figure shows the enlarged BEL taken from the implemented design
as shown in above targeting (xcv300-fg456-6) FPGA Editor tool.
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The above figure shows the enlarged BEL taken from the
implemented decryption design as shown in above targeting (xcv300-fg456-6
) FPGA Editor tool.
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The above figure shows the chip view implementation of the implemented
decryption design developed on FPGA floor planner.
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CHAPTER 7
CONCLUSION
Over all the complete design is verified for its functionality and found
to be satisfactory.
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