IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 18, NO.

3, MARCH 2010 473

A Low-Cost VLSI Implementation for Efficient

Removal of Impulse Noise
Pei-Yin Chen, Member, IEEE, Chih-Yuan Lien, Student Member, IEEE, and Hsu-Ming Chuang

Abstract—Image and video signals might be corrupted by im- conventional median filter or its modification [2]–[4]. The latter
pulse noise in the process of signal acquisition and transmission. yields visually pleasing images by enlarging local window size
In this paper, an efficient VLSI implementation for removing im- adaptively [15], [16] or doing iterations [14]–[17]. In this paper,
pulse noise is presented. Our extensive experimental results show
that the proposed technique preserves the edge features and ob- we focus only on the lower-complexity denoising techniques
tains excellent performances in terms of quantitative evaluation because of its simplicity and easy implementation with the
and visual quality. The design requires only low computational VLSI circuit.
complexity and two line memory buffers. Its hardware cost is quite In [6], Zhang and Karim proposed a new impulse detector
low. Compared with previous VLSI implementations, our design (NID) for switching median filter. NID used the minimum ab-
achieves better image quality with less hardware cost. Synthesis
results show that the proposed design yields a processing rate of solute value of four convolutions which are obtained by using
about 167 M samples/second by using TSMC 0.18 m technology. 1-D Laplacian operators to detect noisy pixels. A method named
as differential rank impulse detector (DRID) is presented in
Index Terms—Image denoising, impulse noise, pipeline architec-
ture, VLSI. [7]. The impulse detector of DRID is based on a comparison
of signal samples within a narrow rank window by both rank
and absolute value. In [8], Luo proposed a method which can
I. INTRODUCTION efficiently remove the impulse noise (ERIN) based on simple
fuzzy impulse detection technique. An alpha-trimmed mean-
N SUCH applications as printing skills, medical imaging,
I scanning techniques, image segmentation, and face recog-
nition, images are often corrupted by noise in the process
based method (ATMBM) was presented in [9]. It used the alpha-
trimmed mean in impulse detection and replaced the noisy pixel
value by a linear combination of its original value and the me-
of image acquisition and transmission. Hence, an efficient dian of its local window. In [10], a decision-based algorithm
denoising technique is very important for the image processing (DBA) is proposed to remove the corrupted pixel by the me-
applications [1]. Recently, many image denoising methods dian or by its neighboring pixel value according the proposed
have been proposed to carry out the impulse noise suppression decisions.
[2]–[17]. Some of them employ the standard median filter [2] For real-time embedded applications, the VLSI implementa-
or its modifications [3], [4] to implement denoising process. tion of switching median filter for impulse noise removal is nec-
However, these approaches might blur the image since both essary and should be considered. For customers, cost is usually
noisy and noise-free pixels are modified. To avoid the damage the most important issue while choosing consumer electronic
on noise-free pixels, an efficient switching strategy has been products. We hope to focus on low-cost denoising implemen-
proposed in the literature [5]–[17]. tation in this paper. The cost of VLSI implementation depends
In general, the switching median filter [5] consists of two mainly on the required memory and computational complexity.
steps: 1) impulse detection and 2) noise filtering. It locates the Hence, less memory and few operations are necessary for a
noisy pixels with an impulse detector, and then filters them low-cost denoising implementation. Based on these two fac-
rather than the whole pixels of an image to avoid the damage tors, we propose a simple edge-preserved denoising technique
on noise-free pixels. Generally, the denoising methods for (SEPD) and its VLSI implementation for removing fixed-value
impulse noise suppression can be classified into two categories: impulse noise. The storage space needed for SEPD is two line
lower-complexity techniques [6]–[13] and higher-complexity buffers rather than a full frame buffer. Only simple arithmetic
techniques [14]–[17]. The former uses a fixed-size local operations, such as addition and subtraction, are used in SEPD.
window and requires a few line buffers. Furthermore, its We proposed a useful impulse noise detector to detect the noisy
computational complexity is low and can be comparable to pixel and employ an effective design to locate the edge of it. The
experimental results demonstrate that SEPD can obtain better
Manuscript received March 14, 2008; revised September 14, 2008 and De- performances in terms of both quantitative evaluation and visual
cember 02, 2008. First published May 29, 2009; current version published Feb- quality than other state-of-the-art lower-complexity impulse de-
ruary 24, 2010. This work was supported in part by the National Science Council
under Grant 96-2221-E-006-027-MY3 and Grant97-2622-E-006-012-CC3 and
noising methods [6]–[13]. Furthermore, the VLSI implementa-
by the use of Shared Facilities supported by the Program of Top 100 Universi- tion of our method also outperforms previous hardware circuits
ties Advancement, Ministry of Education, Taiwan. [11]–[13], [19], [20] in terms of quantitative evaluation, visual
The authors are with the Department of Computer Science and Information quality, and hardware cost.
Engineering, National Cheng Kung University, Tainan 701, Taiwan (e-mail: py-
chen@csie.ncku.edu.tw; lian@csie.ncku.edu.tw; hsuming@gmail.com). The rest of this paper is organized as follows. In Section II,
Digital Object Identifier 10.1109/TVLSI.2008.2012263 the proposed SEPD is introduced. The VLSI implementation of
1063-8210/$26.00 © 2009 IEEE

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474 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 18, NO. 3, MARCH 2010

Fig. 1. 3 2 3 mask centered on p .

SEPD is described briefly in Section III. In Section IV, the im-

plementation of reduced SEPD is introduced. The implementa-
tion results and comparison are provided in Section V. Conclu-
sions are presented in Section VI.

II. PROPOSED SEPD

Assume that the current pixel to be denoised is located at
coordinate and denoted as , and its luminance values
before and after the denoising process are represented as
and , respectively. If is corrupted by the fixed-value im-
pulse noise, its luminance value will jump to be the minimum
or maximum value in gray scale. Here, we adopt a 3 3 mask
centering on for image denoising. In the current , we
know that the three denoised values at coordinates ,
and are determined at the previous de-
noising process, and the six pixels at coordinates , ,
, , and are not
denoised yet, as shown in Fig. 1. A pipelined hardware archi-
tecture is adopted in the design, so we assume that the denoised
value of is still in the pipeline and not available. Using
the 3 3 values in , SEPD will determine whether is a
noisy pixel or not. If positive, SEPD locates a directional edge
existing in and uses it to determine the reconstructed value
; otherwise, .
SEPD is composed of three components: extreme data
detector, edge-oriented noise filter and impulse arbiter. The
extreme data detector detects the minimum and maximum
luminance values in , and determines whether the lumi- Fig. 2. Pseudo code of our scaling method.
nance values of and its five neighboring pixels are equal
to the extreme data. By observing the spatial correlation, the
edge-oriented noise filter pinpoints a directional edge and uses is equal to or , we set to 1, check
it to generate the estimated value of current pixel. Finally, the whether its five neighboring pixels are equal to the extreme
impulse arbiter brings out the proper result. Fig. 2 shows the data, and store the binary compared results into , as shown in
pseudo code of SEPD. The three components of SEPD are Fig. 2.
described in detail in the following subsections.
B. Edge-Oriented Noise Filter
A. Extreme Data Detector To locate the edge existed in the current , a simple edge-
The extreme data detector detects the minimum and max- catching technique which can be realized easily with VLSI cir-
imum luminance values ( and ) in cuit is adopted. To decide the edge, we consider 12 directional
those processed masks from the first one to the current differences, from to , as shown in Fig. 3. Only those
one in the image. If a pixel is corrupted by the fixed-value composed of noise-free pixels are taken into account to avoid
impulse noise, its luminance value will jump to be the min- possible misdetection. If a bit in is equal to 1, it means that
imum or maximum value in gray scale. If is not equal to the pixel related to the binary flag is suspected to be a noisy
, we conclude that is a noise-free pixel. Directions passing through the suspected pixels are dis-
pixel and the following steps for denoising are skipped. If carded to reduce misdetection. In each condition, at most four

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CHEN et al.: LOW-COST VLSI IMPLEMENTATION FOR EFFICIENT REMOVAL OF IMPULSE NOISE 475

Fig. 3. Twelve directional differences of SEPD.

directions are chosen for low-cost hardware implementation. If

there appear over four directions, only four of them are chose ac- Fig. 4. Thirty-two possible values of B and their corresponding directions in
cording to the variation in angle. Fig. 4 shows the mapping table SEPD.
between and the chosen directions adopted in the design.
If , , , and are all
suspected to be noisy pixels “ ” , no edge overcome this drawback, we add another condition to reduce the
can be processed, so (the estimated value of ) possibility of misdetection. If is a noise-free pixel and the
is equal to the weighted average of luminance values current mask has high spatial correlation, should be close
of three previously denoised pixels and calculated as to and is small. That is to say, might be a
. In other conditions noise-free pixel but the pixel value is or
except when “ ” the edge filter calculates the if is small. We measure and compare it
directional differences of the chosen directions and locates the with a threshold to determine whether is corrupted or not.
smallest one among them, as shown in Fig. 2. The The threshold, denoted as , is a predefined value. Obviously,
smallest directional difference implies that it has the strongest the threshold affects the performance of the proposed method. A
spatial relation with , and probably there exists an edge more appropriate threshold can achieve a better detection result.
in its direction. Hence, the mean of luminance values of the However, it is not easy to derive an optimal threshold through
two pixels which possess the smallest directional difference is analytic formulation. According to our experimental results, we
treated as . set the threshold as 20. If is judged as a corrupted pixel,
For example, if is equal to “10011,” it means that , the reconstructed luminance value is equal to ; other-
and are suspected to be noisy values. Therefore, wise, .
, and are discarded because they contain
those suspected pixels (see Fig. 3). The four chosen directional III. VLSI IMPLEMENTATION OF SEPD
differences are , , and (see Fig. 4). Finally, is SEPD has low computational complexity and requires only
equal to the mean of luminance values of the two pixels which two line buffers, so its cost of VLSI implementation is low. For
possess the smallest directional difference among , , better timing performance, we adopt the pipelined architecture
and . which can produce an output at every clock cycle. In our imple-
mentation, the SRAM used to store the image luminance values
C. Impulse Arbiter is generated with the 0.18 m TSMC/Artisan memory compiler
Since the value of a pixel corrupted by the fixed-value im- [21]. According to the simulation, we found that the access time
pulse noise will jump to be the minimum/maximum value in for SRAM is about 6 ns. Since the operation of SRAM access
gray scale, we can conclude that if is corrupted, is equal belongs to the first pipeline stage of our design, we divide the
to or . However, the converse is not true. remaining denoising steps into 6 pipeline stages evenly to keep
If is equal to or , may be cor- the propagation delay of each pipeline stage around 6 ns.
rupted or just in the region with the highest or lowest luminance. Fig. 5 shows block diagram of the 7-stage pipeline architec-
In other words, a pixel whose value is or ture for SEPD. The architecture consists of five main blocks:
might be identified as a noisy pixel even if it is not corrupted. To line buffer, register bank, extreme data detector, edge-oriented

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476 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 18, NO. 3, MARCH 2010

Fig. 5. Block diagram of VLSI architecture for SEPD.

Fig. 7. Two examples of the interconnections between two line buffers and RB.

Fig. 6. Architecture of register bank in SEPD. When the denoising process shifts from to , only 3
new values are needed to be read
into RB (Reg2, Reg5 and Reg8, respectively) and other 6 pixel
noise filter and impulse arbiter. Each of them is described briefly values are shifted to each one’s proper register. At the same
in the following subsections. time, the previous value in Reg8 (the previous input value from
the input device, ) is written back to the line buffer
A. Line Buffer storing for subsequent denoising process.
SEPD adopts a 3 3 mask, so three scanning lines are The selection signals of the four multiplexers are all set to 1
needed. If are processed, three pixels from , or 0 for denoising the odd or the even rows, respectively. Two
and , are needed to perform the denoising process. With examples are shown in Fig. 7 to illustrate the interconnections
the help of four crossover multiplexers (see Fig. 5), we realize between the two line buffers and RB. Assume that we denoise
three scanning lines with two line buffers. As shown in Fig. 5, , and set all four selection signals to 0, those samples of
Line Buffer-odd and Line Buffer-even are designed to store the and are stored in Line Buffer-odd and Buffer-even,
pixels at odd and even rows, respectively. respectively. The samples of are inputted from the input
To reduce cost and power consumption, the line buffer is im- device, as shown in Fig. 7(a). The previous value in Reg8 and
plemented with a dual-port SRAM (one port for reading out data the denoised results generated by the arbiter are written back to
and the other port for writing back data concurrently) instead of Line Buffer-odd and Line Buffer-even, respectively. After the
a series of shifter registers. If the size of an image is , denoising process of has been completed, Line Buffer-odd
the size required for one line buffer is bytes in which 3 is now full with the whole samples of , while those de-
represents the number of pixels stored in the register bank. noised samples of are all stored in Line Buffer-even. To
denoise , we set all selections signals to 1. Thus the pre-
B. Register Bank vious value in Reg8 and the denoised results generated by the ar-
The register bank (RB), consisting of 9 registers, is used to biter are written back to Line Buffer-even and Line Buffer-odd,
store the 3 3 pixel values of the current mask . Fig. 6 shows respectively, as shown in Fig. 7(b). After the denoising process
its architecture where each 3 registers are connected serially in of has been completed, Line Buffer-even is now full with
a chain to provide three pixel values of a row in , and Reg4 the whole samples of , while those denoised samples of
keeps the luminance value of the current pixel to be de- are stored in Line Buffer-odd.
noised. Obviously, the denoising process for does not start
until enterers from the input device. The nine values C. Extreme Data Detector
stored in RB are then used simultaneously by subsequent ex- Fig. 8 shows the 3-stage pipeline architecture of the extreme
treme data detector and noise filter for denoising. data detector in which P represents the pipeline register and EC
Once the denoising process for is completed, the recon- is the equality comparator that will output logic 1 if both two
structed pixel value generated by the arbiter is outputted input values are identical. The 2-stage min-max tree module is
and written into the line buffer storing to replace . used to find and . Two columns of EC

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CHEN et al.: LOW-COST VLSI IMPLEMENTATION FOR EFFICIENT REMOVAL OF IMPULSE NOISE 477

Fig. 10. Architecture of impulse arbiter.

TABLE I
PART OF THE SCHEDULING OF THE SEPD CHIP

Fig. 8. Architecture of register bank in SEPD.

minimum tree unit. After that, the mean of luminance values of

the two pixels which possess the smallest directional difference
can be obtained. When “ ” the final multi-
plexer will output . When
“ ” the multiplexer will output the mean of the two
pixel values which possess .

E. Impulse Arbiter
Fig. 10 shows the architecture of the impulse arbiter in which
comparator CMP is used to output logic 1 if the upper input
value is greater than the lower one . The final
multiplexer is used to output generated by the noise filter
when is corrupted, or when is noise-free.
Fig. 9. Two-stage pipeline architecture of edge-oriented noise filter. In the design, one clock cycle is needed to fetch a value from
one line buffer and then load it into RB. Three clock cycles are
needed for the extreme data detector. To complete their func-
units are used to determine whether the lower six pixels in tions, the edge-oriented noise filter and impulse arbiter require
are equal to or , respectively. rep- two and one clock cycles, respectively. Totally, seven clock cy-
resents the eight neighboring pixels’ values of in . The cles are needed to perform the denoising processing of a pixel.
six OR gates are employed to generate the binary comparison Table I shows part of the scheduling of these operations. If the
results and . When , it means is a noise-free width of an image is , the output latency is clock cy-
pixel and the following operations can be skipped. In this condi- cles in which 7 means the number of pipeline stage.
tion, we disable those registers storing and to avoid
unnecessary power consumption. IV. IMPLEMENTATION OF REDUCED SEPD
In SEPD, we consider 12 directional differences to decide
D. Edge-Oriented Noise Filter the proper edge. When more edges are considered, more com-
Fig. 9 shows the 2-stage pipeline architecture of the edge-ori- plex computations are required. To further reduce the cost of
ented noise filter in which the unit is used to output the implementation, we modify SEPD and propose another design,
absolute value of difference of two inputs. Using from the de- named as reduced SEPD (RSEPD). Only three directional dif-
tector, the mapping module implements the table shown in Fig. 4 ferences, , and as shown in Fig. 11, are considered in
to locate the four directions which are composed of noise-free RSEPD. As demonstrated in Section V, RSEPD offers slightly
pixels. Four directional differences are calculated with the four poorer image quality but requires much lower cost than SEPD.
units. Then the smallest one is determined by using the Fig. 12 shows the pseudo code of RSEPD.

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478 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 18, NO. 3, MARCH 2010

Fig. 11. Three directional differences in RSEPD.

Fig. 13. Extreme data detector in RSEPD.

Fig. 14. Noise filter in RSEPD.

TABLE II
PART OF THE SCHEDULING OF THE RSEPD CHIP

Fig. 12. Pseudo code of RSEPD method.

The VLSI architecture of RSEPD is also composed of five we can apply three units to calculate three differ-
main blocks. RB, line buffer and impulse arbiter of RSPED ences, and then determine the smallest one with the min-
are identical to those of SEPD; however, there are some differ- imum tree unit.
ence between the extreme detector and noise filter and those of 3) In RSEPD, both the extreme data detector and noise filter
SEPD: need three clock cycles to complete their functions. They
1) In the extreme data detector of RSEPD, only one neigh- work in parallel because there exists no data dependency
boring pixel is considered for edge preservation. As between them. As shown in Fig. 10, the impulse arbiter
shown in Fig. 13, the extreme data detector of RSEPD con- requires one clock cycle to complete its job. Totally,
tains four EC units where two EC units are used to deter- five clock cycles are needed for RSEPD to perform the
mine and another two are used to determine . denoising processing of a pixel. Table II shows part of
2) In the noise filter of RSEPD, three directional differences the scheduling of these operations. The output latency
are considered. The mapping module used in SEPD be- of RSEPD is clock cycles in which 5 means the
comes unnecessary and is removed. As shown in Fig. 14, number of pipeline stage.

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CHEN et al.: LOW-COST VLSI IMPLEMENTATION FOR EFFICIENT REMOVAL OF IMPULSE NOISE 479

Fig. 16. Results of different methods in restoring 60% corrupted image “Lena”.
(a) Noise-free image; (b) noisy image; (c) NID [6]; (d) DRID [7]; (e) ERIN [8];
Fig. 15. Comparisons of PSNR for the reference images. (a) Lena; (b) boat; (c) (f) ATMBM [9]; (g) DBA [10]; (h) RVNP [11]; (i) AMF [12]; (j) NAVF [13];
couple; (d) peppers; (e) airplane; (f) goldhill. (k) MND [15]; (l) BDND [16]; (m) GPF [17]; (n) SEPD; (o) RSEPD.

V. IMPLEMENTATION RESULTS AND COMPARISONS methods (MND [15], BDND [16], GPF [17]), and our methods
To verify the characteristics and performances of various (SEPD, and RSEPD) are compared in terms of objective testing
denoising algorithms, a variety of simulations are carried (quantitative evaluation) and subjective testing (visual quality)
out on the six well-known 512 512 8-bit gray-scale test where the parameters or thresholds of these methods are set as
images: Lena, Boat, Couple, Peppers, Airplane, and Goldhill. suggested.
In the simulations, images are corrupted by impulse noise We employ the peak signal-to-noise ratio (PSNR) to illustrate
(salt-and-pepper noise), where “salt” and “pepper” noise are the quantitative quality of the reconstructed images for various
with equal probability. Furthermore, a wide range of noise ra- methods. As shown in Fig. 15, it can be observed that the per-
tios varied from 10% to 90% with increments of 10% is tested. formances of SEPD are always the best, even the noise ratio is
Totally, eight recent lower-complexity denoising methods (NID as high as 90%. To explore the visual quality, we show the re-
[6], DRID [7], ERIN [8], ATMBM [9], DBA [10], RVNP [11], constructed images of different denoising methods in restoring
AMF [12], NAVF [13]), three higher-complexity denoising 60% corrupted image “Lena” in Fig. 16. Obviously, NID, ERIN,

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480 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 18, NO. 3, MARCH 2010

TABLE III
COMPARISONS OF RESTORATION RESULTS FOR NOISE-FREE “LENA” IMAGE

Hint: mis-detected pixels are those noise-free pixels which are detected as
the noisy pixels by the detection approach.

AMF and GPF produce noticeable black and white dots. DRID,
ATMBM, DBA and NAVF are not good enough with regard to
edge preservation. RVNP brings out blur reconstructed image.
Our SEPD and RSEPD produce visually pleasing images as
the higher-complexity MND and BDND do. Moreover, we also
verify these methods on the noise-free “Lena” image, and the
result is shown in Table III. It can be observed that our SEPD
and RSEPD still perform well.
The proposed VLSI architectures of SEPD and RSEPD were
implemented by using Verilog HDL. We used SYNOPSYS Fig. 17. Results of SEPD with software program and VLSI circuit at different
noise ratio. (a) “Peppers” by software; (b) “peppers” by circuit.
Design Vision to synthesize the designs with TSMC’s 0.18
m cell library. The layouts for the designs were generated TABLE IV
with SYNOPSYS Astro (for auto placement and routing), FEATURES OF FIVE DENOISING IMPLEMENTATIONS
and verified by MENTOR GRAPHIC Calibre (for DRC and
LVS checks), respectively. Nanosim was used for post-layout
transistor-level simulation. Finally, SYNOPSYS PrimePower
was employed to measure the total power consumption. The
synthesis results show that the SEPD chip contains 6352 gate
counts and the RSEPD chip contains 3719 gate counts. Both
of them work in a clock period of 6 ns and can achieve a pro-
cessing rate of about 167 mega pixels per second. Furthermore,
SEPD and RSEPD are also implemented on the Altera Cyclone
II EP2C8F256C6 FPGA board for verification. The operating
clock frequencies of SPED and RSPED are 112.79 MHz
(with 1249 logic elements) and 105.95 MHz (with 706 logic
elements), respectively. Since our design just requires simple
operations (fixed bit-width adding, subtracting, or comparing), we have implemented our design by using three different
the denoised results of SEPD with software program and with technologies, respectively. Table IV shows the detailed com-
the VLSI circuit are identical, as shown in Fig. 17. parisons for various implementations. As demonstrated, our
To explore the advantage of low cost for our design, we com- RSEPD requires the lowest hardware cost and works faster than
pared our RSEPD with three recent denoising chips [11]–[13]. RVNP [11], AMF [12] and NAVF [13]. Furthermore, RSEPD
They were realized with different VLSI implementations, so it obtains better image quality than those methods [11]–[13] as
is very difficult to compare our chip with them directly. Hence, shown in Figs. 15 and 16. In [11], the author claims that their

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CHEN et al.: LOW-COST VLSI IMPLEMENTATION FOR EFFICIENT REMOVAL OF IMPULSE NOISE 481

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1994.
[6] S. Zhang and M. A. Karim, “A new impulse detector for switching Chih-Yuan Lien received the B.S. and M.S. degrees
median filter,” IEEE Signal Process. Lett., vol. 9, no. 11, pp. 360–363, in computer science and information engineering
Nov. 2002. from National Taiwan University, Taipei, Taiwan,
[7] I. Aizenberg and C. Butakoff, “Effective impulse detector based on in 1996 and 1998, respectively. He is currently
rank-order criteria,” IEEE Signal Process. Lett., vol. 11, no. 3, pp. pursuing the Ph.D. degree in computer science and
363–366, Mar. 2004. information engineering from National Cheng Kung
[8] W. Luo, “Efficient removal of impulse noise from digital images,” University, Tainan, Taiwan.
IEEE Trans. Consum. Electron., vol. 52, no. 2, pp. 523–527, May His research interests include image processing,
2006. VLSI chip design, and video coding system.
[9] W. Luo, “An efficient detail-preserving approach for removing im-
pulse noise in images,” IEEE Signal Process. Lett., vol. 13, no. 7, pp.
413–416, Jul. 2006.
[10] K. S. Srinivasan and D. Ebenezer, “A new fast and efficient decision-
based algorithm for removal of high-density impulse noises,” IEEE
Signal Process. Lett., vol. 14, no. 3, pp. 189–192, Mar. 2007. Hsu-Ming Chuang received the B.S. degree in com-
[11] S.-C. Hsia, “Parallel VLSI design for a real-time video-impulse puter science from National Tsing-Hua University,
noise-reduction processor,” IEEE Trans. Very Large Scale Integr. Hsinchu, Taiwan, in 2005, and the M.S. degree in
(VLSI) Syst., vol. 11, no. 4, pp. 651–658, Aug. 2003. computer science and information engineering from
[12] I. Andreadis and G. Louverdis, “Real-time adaptive image impulse National Cheng Kung University, Tainan, Taiwan, in
noise suppression,” IEEE Trans. Instrum. Meas., vol. 53, no. 3, pp. 2007.
798–806, Jun. 2004. His research interests include VLSI chip design,
[13] V. Fischer, R. Lukac, and K. Martin, “Cost-effective video filtering so- data compression, and image processing.
lution for real-time vision systems,” EURASIP J. Appl. Signal Process.,
vol. 2005, no. 13, pp. 2026–2042, Jan. 2005.

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