The Design of Hand Vein Recognition System Based on DSP and CPLD

Abstract. As a new-style biometrics identification technology, hand vein recognition

is widely used in multi-categories recently for its non-contact, anti-counterfeiting and
interference immunity characteristics. In this paper, hand vein recognition system
based on DSP and CPLD is designed according to the requirements for equipment
volume, discernment, and response speed. Composing with video decoder chip, DSP
and CPLD, this recognition system owns many good characteristics, such as
functional integration, simple structure, convenient application and so on, which make
it suitable for circumstances with high requirements for personal identification. The
overall structure and detailed implementation of system hardware architecture are
discussed. Moreover, the design philosophy and specific realization of system
software as well as core algorithms are explored in this paper.

Keywords: Image processing; Hand vein recognition; Digital signal processing;

CPLD

1 Introduction
Biometric recognition [1] is one of the main techniques for personal identification
and security certification based on individual behavioral pattern (such as gait,
signature, keystroke, voiceprint and so on) or physiological features (such as face,
fingerprint, iris, palmar-print and hand vein). Comparing with traditional
identification technologies, biometric recognition is more convenient and safer.
Accordingly, it is extensively used in various authentication circumstances such as
Access Control System, Security Inspection System, financial system and so forth [1-2].
As a new biometric recognition technique, hand vein recognition has some valuable
characteristics, such as non-contact, anti-counterfeiting and interference immunity,
which attract more and more researchers’ attention in recent years [3-4]. As the hot
topic of biometric recognition research, hand vein recognition has been actualized
recently by researchers in Japan and South Korea and some hand vein recognition
equipments are available in the markets now. However, researchers still face with
several urgent problems, such as how to miniaturize the devices, how to improve the
recognition accuracy and how to increase the response speed. Trying to solve those
problems, a hand vein recognition system based on DSP and CPLD is designed in this
paper. Its hardware system mainly consists of standard PAL/NTSC composite video
signal as input, professional video decoder chip, DSP and CPLD. Among them,
professional video decoder chip is used to digitize analog video signals; DSP is
responsible for implementation of algorithms for image processing and process
management of the whole system; CPLD is in charge of time sequence and logic
control of interface between chips and therefore can simplify peripheral circuit.

2 Brief introduction of the system

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 As a whole, the hand vein recognition system is a hybrid structure mainly
consisting of professional integrated video decoder chip, DSP and CPLD. In this
system, standard NTSC/PAL CCD camera is used for image acquisition; high-speed
DSP is employed to image processing; CPLD is adopted in controlling peripheral
circuit. The illustration of the whole system can be shown briefly in Fig.1:

Image acquisition mo dule

I/O mo dule

Oscillator
Crystal Video Decoder
LED
output
FIFO
CPLD
Input
interface
Oscillator
Crystal

DSP
JTAG circuit
FLASH
Reset circuit
SRAM Power
management
Image pro cessing module circuit

Fig.1. Structure of hand vein recognition system

This system has some beneficial attributes, such as functional integration, simple
structure, flexible programming and so on [5]. Based on the functional requirements of
diverse parts of the system, the type choosing of chips is as follows:
1) TI’s TMS320VC5410 is chosen as the DSP chip, SST’s SST39VF400A is
selected as external FLASH, and Cypress’ Cy7c1041 is adopted as external SRAM
taking charge of digital image processing and storage.
2) As the interface of DSP interacting with peripheral equipments, CPLD, in this
paper, use Altera’s MAXII series-EPM570T144. And Verilog HDL is used to design
and realize the control of picture signal input, image data buffering, operations of
outside storage devices and initialization of video decoder I2C
3) Philips’ SAA7113H is used as video decoder chip to convert analog composite
NTSC/PAL video signals of CCD camera into YUV422 digital image signals, and to
export picture synchronization signals and PCLK (Pixel Clock).
4) In this paper, AVER LOGIC’s AL422B is chosen as data buffering FIFO for
its large storage capacity (384K×8bit) and high storage speed.

3.1.1 Image acquisition and decoding circuit

In the analog signals of CCD camera, there are various signals, such as image
signal, HSYNC, horizontal blanking signal, field synchronizing signal, VITS, leading
Eq pulse and so on. Video decoder chip SAA7113H can convert analog video signals
of CCD camera into YUV422 digital image signals and provide the system with
PCLK (Pixel Clock), HSYNC and field synchronizing signal. Port multiplier is used

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in SAA7113H’s DOUT (data out), so that Y-signal (luminance signal) and U/V color
components signal are both outputted through the same ports DO [7..0]. As the image
signal that the system needs is 8bit gray image signal, only Y-signal should be read in
the signal reading process. For the sake of simplifying system hardware, I2C
initialization of SAA7113H is accomplished by CPLD, and its simulation oscillogram
is shown in Fig.2:

Fig.2. Sub-address 0x01 simulation effect

3.1.2 Image data buffer circuit
In this paper, AVER LOGIC’s AL422B is chosen as FIFO (image data buffer
circuit), which is under the control of CPLD. With dynamic RAM (PCLK Pixel
Clock’s refresh frequency range is 1MHz~50MHz) as its storage structure, AL422B
has large and synchronous storage capacity (384K×8bit) and applies to buffer
gathered image data. Every time, the system acquires a frame of 8bit gray image with
the size of 256×256, which takes up 64K×8bit storage space. Based on that, this FIFO
can temporarily store 6 frames of hand vein image.
3.1.3 Control circuit design using CPLD
In the system, most control task of peripheral circuit is fulfilled by CPLD, and its
logic design includes: a. logic switching module of memorizer chip select signal; b.
initialization control module of video decoder I2C; c. windowing disposal of image
signal; d. decoding module for the operation of I/O space. Fig.3 illustrates functional
modules inside CPLD.
SRAM、
XF Logical FLASH
conversion
P/D space
operation

of CS DSP
signal
12C master
controller
SAA7113H
#INT0
Windowing
and writing
image data
to FIFO FIFO
#INT1
Reading data
DSP
from FIFO
I/O space
operation

I/O space Writing data Output by

operation into LED LED
decoding
Reading start
Input signal
signal

Reading Mode
work mode configuration
CPLD Interior pins

Fig.3. Functional modules inside CPLD

For the image acquisition of one integrated frame, sampling begins when DSP
gives instructions. After that, CPLD launches sampling as soon as the first odd field
synchronizing signal arrives. Firstly, PCLK pixel clock keeps on counting when odd

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field row signal is effective, then sampling for even field is carried out in the same
way. In order to realize image windowing control and then to implement image
sampling according to the needed precision, in this paper, row counter and pixel
counter are used to flexibly control the row number of every field and the pixel
number of every row. And its simulation oscillogram is shown in Fig.4:

Fig.4. The windowing control of image signal

3.1.4 DSP and its control circuit
As the core processor of the whole system, DSP can operate normally only when
there are stable power supply and steady CLK. In the system, TI’s LDO linear power
supply chip TPS73HD325 is used to provide DSP with 2.5V core voltage and 3.3V
I/O voltage. Since there is doubling circuit inside TMS320VC5410, 20MHz clock
signal is adopted as DSP’s input clock in peripheral subsystem to reduce the
electromagnetic interference of circuit board. And the connection between DSP and
peripheral equipments is actualized by the control of program/data space extending
pins and the logical conversion of CPLD.
3.1.5 Control circuit of extended memory
With large storage capacity (256K×16bit), extended memory Cy7c1041 is in
charge of accessing programming code and software variables. It has eight 32Kbyte
storage units mapping with the zeroth to 7th 0x8000~0xFFFF space address of DSP
respectively; extended flash memory SST39VF400A (with 256K×16bit storage
capacity) is mainly responsible for confirmation of programming code and user
registration. Although any storage space with low address 0x8000~0xFFFF can be
used in space mapping, the system initially extracts programming code at data space
address 0x8000 when it automatically loading program in the process of power-up.
Hence solidified codes must be stored in data space with starting address 0x8000.
Based on the amount of acquired image data and the actual demand of programming
code, low 32Kbyte FLASH matches with storage space 0x8000~0xFFFF (this space is
valid for FLASH when the voltage of DSP’s XF pin is in high level; otherwise it is
valid for SRAM), and other units in FLASH are mapped to the storage space that is
nonoverlapping with SRAM. So the 9th to Fth 0x8000~0xFFFF storage space is
applied to store users’ registration information.
3.1.6 I/O modular circuit
As a new type of biometrics identification system, hand vein recognition system
can apply to various circumstances for user authentication. Accordingly, this system
must export signals of recognition result to drive other systems. In this system, LED
displays are used to show recognition result. Besides that, light touch switches are
employed in external input. The I/O control of this system is actualized by CPLD. The
system can flexibly extend and use input/output signal through I/O space decoding of
DSP.

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3.2 Software design of the system
As the main part of system software, DSP software is designed according to time
sequences including DSP initialization, acquisition trigger judging, sending
acquisition commands, data reading, data processing, data storage, output of
recognition result and so on. As the main processor of the system, DS P is responsible
for algorithms processing tasks as well as controlling CPLD to operate on peripheral
equipment. For the purpose of utilizing resources of DSP conveniently, mixed
programming based on C and assembly languages is applied in software design of
DSP.
After the system powers up, program in external FLASH is loaded into internal
program space by way of 16bit parallel bootload mode. Then DSP begins to run
program as is shown in the program flowchart below.

Fig.5. Program flowchart of DSP

First of all, DSP initializes a variety of devices. After that, it will judge input
signal of the system until input signal drives the system to operate. Then work pattern
will be judged by reading input signal of I/O space, which is configured by external
pins. There are two kinds of work patterns for the system: registration mode and
authentication mode. In registration mode, the system firstly sends sampling
instructions to CPLD to startup image sampling thrice, then image features, which are
extracted from the mean value image of the three sampling images, will be stored in
FLASH. In authentication mode, the user’s image is acquired and stored in storage
space and then the features of user image can be obtained through image processing;
afterwards the system will compare those features with the user’s registration
information to procure matching result. Image acquisition consists of two processes.
In the first instance, combined with windowing processing, image data output of
video decoder is written into FIFO; and the system will response to interrupt signal of

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INT0 when the writing process is completed. Following this, the system will transfer
image data from FIFO to SRAM via I/O space operation when DSP sends out reading
instructions; and the system will response to interrupt signal of INT1 when the
reading process is finished.
In order to improve the quality of acquired image, the system will continuously
gather three images to calculate their mean variance (VAR) in registration mode. If
VAR is greater than predefined threshold value (T0), image acquisition will be
considered as an inaccurate one and the system will carry out image acquisition again.
Otherwise, image acquisition is deemed successful and the system will function in
proper sequence of registration mode. Preprocessing is applied in authentication mode
to better extract image feature, which is then compared with image feature library in
FLASH. Considering that brightness is uneven in hand vein image, contrast-limited
adaptive histogram equalization (CLAHE) is used for image enhancement. In this
paper, region of interest (ROI) is defined by the position and size of fingers and palm;
then Niblack technique is employed for image binarization; after that binary image is
refined by Hilditch technique. Finally, the system extracts image features, such as the
type, quantity and distance ratio of characteristic points. The flow chart of those
procedures is illustrated in Fig.6:

Fig.6. Algorithms flowchart of hand vein recognition system

4 Conclusions
In this paper, hand vein recognition system based on DSP is researched
comprehensively and its design scheme is proposed as well. In the aspect of device
selection, standard NTSC/PAL CCD camera is adopted in image acquisition to input
analog composite video signals; DSP serves as main processor; CPLD acts as
principal controller; extended FLASH, SRAM and other necessary peripheral devices
are introduced in the system too. Based on all the aforementioned equipments, a
compact hand vein recognition system is reasonably constructed at last. For the

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purpose of saving the processing time of DSP, image acquisition is independent of
DSP. Moreover, according to the trait of hand vein image, recognition algorithm based
on characteristic points is used to improve precision and real-time property of the
system in identity recognition

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